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TARGET_EFM32GG11_STK3701/TOOLCHAIN_ARM_MICRO/efm32gg11b820f2048gl152.h@171:3a7713b1edbc, 2018-11-08 (annotated)

Committer:
AnnaBridge
Date:
Thu Nov 08 11:45:42 2018 +0000
Revision:
171:3a7713b1edbc
Parent:
TARGET_EFM32GG11_STK3701/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG11/device/efm32gg11b820f2048gl152.h@170:e95d10626187 
mbed library. Release version 164

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 170:e95d10626187 1 /**************************************************************************//**
AnnaBridge 170:e95d10626187 2 * @file efm32gg11b820f2048gl152.h
AnnaBridge 170:e95d10626187 3 * @brief CMSIS Cortex-M Peripheral Access Layer Header File
AnnaBridge 170:e95d10626187 4 * for EFM32GG11B820F2048GL152
AnnaBridge 170:e95d10626187 5 * @version 5.3.2
AnnaBridge 170:e95d10626187 6 ******************************************************************************
AnnaBridge 170:e95d10626187 7 * # License
AnnaBridge 170:e95d10626187 8 * <b>Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com</b>
AnnaBridge 170:e95d10626187 9 ******************************************************************************
AnnaBridge 170:e95d10626187 10 *
AnnaBridge 170:e95d10626187 11 * Permission is granted to anyone to use this software for any purpose,
AnnaBridge 170:e95d10626187 12 * including commercial applications, and to alter it and redistribute it
AnnaBridge 170:e95d10626187 13 * freely, subject to the following restrictions:
AnnaBridge 170:e95d10626187 14 *
AnnaBridge 170:e95d10626187 15 * 1. The origin of this software must not be misrepresented; you must not
AnnaBridge 170:e95d10626187 16 * claim that you wrote the original software.@n
AnnaBridge 170:e95d10626187 17 * 2. Altered source versions must be plainly marked as such, and must not be
AnnaBridge 170:e95d10626187 18 * misrepresented as being the original software.@n
AnnaBridge 170:e95d10626187 19 * 3. This notice may not be removed or altered from any source distribution.
AnnaBridge 170:e95d10626187 20 *
AnnaBridge 170:e95d10626187 21 * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
AnnaBridge 170:e95d10626187 22 * has no obligation to support this Software. Silicon Laboratories, Inc. is
AnnaBridge 170:e95d10626187 23 * providing the Software "AS IS", with no express or implied warranties of any
AnnaBridge 170:e95d10626187 24 * kind, including, but not limited to, any implied warranties of
AnnaBridge 170:e95d10626187 25 * merchantability or fitness for any particular purpose or warranties against
AnnaBridge 170:e95d10626187 26 * infringement of any proprietary rights of a third party.
AnnaBridge 170:e95d10626187 27 *
AnnaBridge 170:e95d10626187 28 * Silicon Laboratories, Inc. will not be liable for any consequential,
AnnaBridge 170:e95d10626187 29 * incidental, or special damages, or any other relief, or for any claim by
AnnaBridge 170:e95d10626187 30 * any third party, arising from your use of this Software.
AnnaBridge 170:e95d10626187 31 *
AnnaBridge 170:e95d10626187 32 *****************************************************************************/
AnnaBridge 170:e95d10626187 33
AnnaBridge 170:e95d10626187 34 #if defined(__ICCARM__)
AnnaBridge 170:e95d10626187 35 #pragma system_include /* Treat file as system include file. */
AnnaBridge 170:e95d10626187 36 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
AnnaBridge 170:e95d10626187 37 #pragma clang system_header /* Treat file as system include file. */
AnnaBridge 170:e95d10626187 38 #endif
AnnaBridge 170:e95d10626187 39
AnnaBridge 170:e95d10626187 40 #ifndef EFM32GG11B820F2048GL152_H
AnnaBridge 170:e95d10626187 41 #define EFM32GG11B820F2048GL152_H
AnnaBridge 170:e95d10626187 42
AnnaBridge 170:e95d10626187 43 #ifdef __cplusplus
AnnaBridge 170:e95d10626187 44 extern "C" {
AnnaBridge 170:e95d10626187 45 #endif
AnnaBridge 170:e95d10626187 46
AnnaBridge 170:e95d10626187 47 /**************************************************************************//**
AnnaBridge 170:e95d10626187 48 * @addtogroup Parts
AnnaBridge 170:e95d10626187 49 * @{
AnnaBridge 170:e95d10626187 50 *****************************************************************************/
AnnaBridge 170:e95d10626187 51
AnnaBridge 170:e95d10626187 52 /**************************************************************************//**
AnnaBridge 170:e95d10626187 53 * @defgroup EFM32GG11B820F2048GL152 EFM32GG11B820F2048GL152
AnnaBridge 170:e95d10626187 54 * @{
AnnaBridge 170:e95d10626187 55 *****************************************************************************/
AnnaBridge 170:e95d10626187 56
AnnaBridge 170:e95d10626187 57 /** Interrupt Number Definition */
AnnaBridge 170:e95d10626187 58 typedef enum IRQn{
AnnaBridge 170:e95d10626187 59 /****** Cortex-M4 Processor Exceptions Numbers *******************************************/
AnnaBridge 170:e95d10626187 60 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
AnnaBridge 170:e95d10626187 61 HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */
AnnaBridge 170:e95d10626187 62 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
AnnaBridge 170:e95d10626187 63 BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
AnnaBridge 170:e95d10626187 64 UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
AnnaBridge 170:e95d10626187 65 SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
AnnaBridge 170:e95d10626187 66 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
AnnaBridge 170:e95d10626187 67 PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
AnnaBridge 170:e95d10626187 68 SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
AnnaBridge 170:e95d10626187 69
AnnaBridge 170:e95d10626187 70 /****** EFM32GG11B Peripheral Interrupt Numbers *********************************************/
AnnaBridge 170:e95d10626187 71
AnnaBridge 170:e95d10626187 72 EMU_IRQn = 0, /*!< 16+0 EFM32 EMU Interrupt */
AnnaBridge 170:e95d10626187 73 WDOG0_IRQn = 1, /*!< 16+1 EFM32 WDOG0 Interrupt */
AnnaBridge 170:e95d10626187 74 LDMA_IRQn = 2, /*!< 16+2 EFM32 LDMA Interrupt */
AnnaBridge 170:e95d10626187 75 GPIO_EVEN_IRQn = 3, /*!< 16+3 EFM32 GPIO_EVEN Interrupt */
AnnaBridge 170:e95d10626187 76 SMU_IRQn = 4, /*!< 16+4 EFM32 SMU Interrupt */
AnnaBridge 170:e95d10626187 77 TIMER0_IRQn = 5, /*!< 16+5 EFM32 TIMER0 Interrupt */
AnnaBridge 170:e95d10626187 78 USART0_RX_IRQn = 6, /*!< 16+6 EFM32 USART0_RX Interrupt */
AnnaBridge 170:e95d10626187 79 USART0_TX_IRQn = 7, /*!< 16+7 EFM32 USART0_TX Interrupt */
AnnaBridge 170:e95d10626187 80 ACMP0_IRQn = 8, /*!< 16+8 EFM32 ACMP0 Interrupt */
AnnaBridge 170:e95d10626187 81 ADC0_IRQn = 9, /*!< 16+9 EFM32 ADC0 Interrupt */
AnnaBridge 170:e95d10626187 82 IDAC0_IRQn = 10, /*!< 16+10 EFM32 IDAC0 Interrupt */
AnnaBridge 170:e95d10626187 83 I2C0_IRQn = 11, /*!< 16+11 EFM32 I2C0 Interrupt */
AnnaBridge 170:e95d10626187 84 I2C1_IRQn = 12, /*!< 16+12 EFM32 I2C1 Interrupt */
AnnaBridge 170:e95d10626187 85 GPIO_ODD_IRQn = 13, /*!< 16+13 EFM32 GPIO_ODD Interrupt */
AnnaBridge 170:e95d10626187 86 TIMER1_IRQn = 14, /*!< 16+14 EFM32 TIMER1 Interrupt */
AnnaBridge 170:e95d10626187 87 TIMER2_IRQn = 15, /*!< 16+15 EFM32 TIMER2 Interrupt */
AnnaBridge 170:e95d10626187 88 TIMER3_IRQn = 16, /*!< 16+16 EFM32 TIMER3 Interrupt */
AnnaBridge 170:e95d10626187 89 USART1_RX_IRQn = 17, /*!< 16+17 EFM32 USART1_RX Interrupt */
AnnaBridge 170:e95d10626187 90 USART1_TX_IRQn = 18, /*!< 16+18 EFM32 USART1_TX Interrupt */
AnnaBridge 170:e95d10626187 91 USART2_RX_IRQn = 19, /*!< 16+19 EFM32 USART2_RX Interrupt */
AnnaBridge 170:e95d10626187 92 USART2_TX_IRQn = 20, /*!< 16+20 EFM32 USART2_TX Interrupt */
AnnaBridge 170:e95d10626187 93 UART0_RX_IRQn = 21, /*!< 16+21 EFM32 UART0_RX Interrupt */
AnnaBridge 170:e95d10626187 94 UART0_TX_IRQn = 22, /*!< 16+22 EFM32 UART0_TX Interrupt */
AnnaBridge 170:e95d10626187 95 UART1_RX_IRQn = 23, /*!< 16+23 EFM32 UART1_RX Interrupt */
AnnaBridge 170:e95d10626187 96 UART1_TX_IRQn = 24, /*!< 16+24 EFM32 UART1_TX Interrupt */
AnnaBridge 170:e95d10626187 97 LEUART0_IRQn = 25, /*!< 16+25 EFM32 LEUART0 Interrupt */
AnnaBridge 170:e95d10626187 98 LEUART1_IRQn = 26, /*!< 16+26 EFM32 LEUART1 Interrupt */
AnnaBridge 170:e95d10626187 99 LETIMER0_IRQn = 27, /*!< 16+27 EFM32 LETIMER0 Interrupt */
AnnaBridge 170:e95d10626187 100 PCNT0_IRQn = 28, /*!< 16+28 EFM32 PCNT0 Interrupt */
AnnaBridge 170:e95d10626187 101 PCNT1_IRQn = 29, /*!< 16+29 EFM32 PCNT1 Interrupt */
AnnaBridge 170:e95d10626187 102 PCNT2_IRQn = 30, /*!< 16+30 EFM32 PCNT2 Interrupt */
AnnaBridge 170:e95d10626187 103 RTCC_IRQn = 31, /*!< 16+31 EFM32 RTCC Interrupt */
AnnaBridge 170:e95d10626187 104 CMU_IRQn = 32, /*!< 16+32 EFM32 CMU Interrupt */
AnnaBridge 170:e95d10626187 105 MSC_IRQn = 33, /*!< 16+33 EFM32 MSC Interrupt */
AnnaBridge 170:e95d10626187 106 CRYPTO0_IRQn = 34, /*!< 16+34 EFM32 CRYPTO0 Interrupt */
AnnaBridge 170:e95d10626187 107 CRYOTIMER_IRQn = 35, /*!< 16+35 EFM32 CRYOTIMER Interrupt */
AnnaBridge 170:e95d10626187 108 FPUEH_IRQn = 36, /*!< 16+36 EFM32 FPUEH Interrupt */
AnnaBridge 170:e95d10626187 109 USART3_RX_IRQn = 37, /*!< 16+37 EFM32 USART3_RX Interrupt */
AnnaBridge 170:e95d10626187 110 USART3_TX_IRQn = 38, /*!< 16+38 EFM32 USART3_TX Interrupt */
AnnaBridge 170:e95d10626187 111 USART4_RX_IRQn = 39, /*!< 16+39 EFM32 USART4_RX Interrupt */
AnnaBridge 170:e95d10626187 112 USART4_TX_IRQn = 40, /*!< 16+40 EFM32 USART4_TX Interrupt */
AnnaBridge 170:e95d10626187 113 WTIMER0_IRQn = 41, /*!< 16+41 EFM32 WTIMER0 Interrupt */
AnnaBridge 170:e95d10626187 114 WTIMER1_IRQn = 42, /*!< 16+42 EFM32 WTIMER1 Interrupt */
AnnaBridge 170:e95d10626187 115 WTIMER2_IRQn = 43, /*!< 16+43 EFM32 WTIMER2 Interrupt */
AnnaBridge 170:e95d10626187 116 WTIMER3_IRQn = 44, /*!< 16+44 EFM32 WTIMER3 Interrupt */
AnnaBridge 170:e95d10626187 117 I2C2_IRQn = 45, /*!< 16+45 EFM32 I2C2 Interrupt */
AnnaBridge 170:e95d10626187 118 VDAC0_IRQn = 46, /*!< 16+46 EFM32 VDAC0 Interrupt */
AnnaBridge 170:e95d10626187 119 TIMER4_IRQn = 47, /*!< 16+47 EFM32 TIMER4 Interrupt */
AnnaBridge 170:e95d10626187 120 TIMER5_IRQn = 48, /*!< 16+48 EFM32 TIMER5 Interrupt */
AnnaBridge 170:e95d10626187 121 TIMER6_IRQn = 49, /*!< 16+49 EFM32 TIMER6 Interrupt */
AnnaBridge 170:e95d10626187 122 USART5_RX_IRQn = 50, /*!< 16+50 EFM32 USART5_RX Interrupt */
AnnaBridge 170:e95d10626187 123 USART5_TX_IRQn = 51, /*!< 16+51 EFM32 USART5_TX Interrupt */
AnnaBridge 170:e95d10626187 124 CSEN_IRQn = 52, /*!< 16+52 EFM32 CSEN Interrupt */
AnnaBridge 170:e95d10626187 125 LESENSE_IRQn = 53, /*!< 16+53 EFM32 LESENSE Interrupt */
AnnaBridge 170:e95d10626187 126 EBI_IRQn = 54, /*!< 16+54 EFM32 EBI Interrupt */
AnnaBridge 170:e95d10626187 127 ACMP2_IRQn = 55, /*!< 16+55 EFM32 ACMP2 Interrupt */
AnnaBridge 170:e95d10626187 128 ADC1_IRQn = 56, /*!< 16+56 EFM32 ADC1 Interrupt */
AnnaBridge 170:e95d10626187 129 LCD_IRQn = 57, /*!< 16+57 EFM32 LCD Interrupt */
AnnaBridge 170:e95d10626187 130 SDIO_IRQn = 58, /*!< 16+58 EFM32 SDIO Interrupt */
AnnaBridge 170:e95d10626187 131 ETH_IRQn = 59, /*!< 16+59 EFM32 ETH Interrupt */
AnnaBridge 170:e95d10626187 132 CAN0_IRQn = 60, /*!< 16+60 EFM32 CAN0 Interrupt */
AnnaBridge 170:e95d10626187 133 CAN1_IRQn = 61, /*!< 16+61 EFM32 CAN1 Interrupt */
AnnaBridge 170:e95d10626187 134 USB_IRQn = 62, /*!< 16+62 EFM32 USB Interrupt */
AnnaBridge 170:e95d10626187 135 RTC_IRQn = 63, /*!< 16+63 EFM32 RTC Interrupt */
AnnaBridge 170:e95d10626187 136 WDOG1_IRQn = 64, /*!< 16+64 EFM32 WDOG1 Interrupt */
AnnaBridge 170:e95d10626187 137 LETIMER1_IRQn = 65, /*!< 16+65 EFM32 LETIMER1 Interrupt */
AnnaBridge 170:e95d10626187 138 TRNG0_IRQn = 66, /*!< 16+66 EFM32 TRNG0 Interrupt */
AnnaBridge 170:e95d10626187 139 QSPI0_IRQn = 67, /*!< 16+67 EFM32 QSPI0 Interrupt */
AnnaBridge 170:e95d10626187 140 } IRQn_Type;
AnnaBridge 170:e95d10626187 141
AnnaBridge 170:e95d10626187 142 /**************************************************************************//**
AnnaBridge 170:e95d10626187 143 * @defgroup EFM32GG11B820F2048GL152_Core Core
AnnaBridge 170:e95d10626187 144 * @{
AnnaBridge 170:e95d10626187 145 * @brief Processor and Core Peripheral Section
AnnaBridge 170:e95d10626187 146 *****************************************************************************/
AnnaBridge 170:e95d10626187 147 #define __MPU_PRESENT 1 /**< Presence of MPU */
AnnaBridge 170:e95d10626187 148 #define __FPU_PRESENT 1 /**< Presence of FPU */
AnnaBridge 170:e95d10626187 149 #define __VTOR_PRESENT 1 /**< Presence of VTOR register in SCB */
AnnaBridge 170:e95d10626187 150 #define __NVIC_PRIO_BITS 3 /**< NVIC interrupt priority bits */
AnnaBridge 170:e95d10626187 151 #define __Vendor_SysTickConfig 0 /**< Is 1 if different SysTick counter is used */
AnnaBridge 170:e95d10626187 152
AnnaBridge 170:e95d10626187 153 /** @} End of group EFM32GG11B820F2048GL152_Core */
AnnaBridge 170:e95d10626187 154
AnnaBridge 170:e95d10626187 155 /**************************************************************************//**
AnnaBridge 170:e95d10626187 156 * @defgroup EFM32GG11B820F2048GL152_Part Part
AnnaBridge 170:e95d10626187 157 * @{
AnnaBridge 170:e95d10626187 158 ******************************************************************************/
AnnaBridge 170:e95d10626187 159
AnnaBridge 170:e95d10626187 160 /** Part family */
AnnaBridge 170:e95d10626187 161
AnnaBridge 170:e95d10626187 162 #define _EFM32_GIANT_FAMILY 1 /**< GIANT Gecko MCU Family */
AnnaBridge 170:e95d10626187 163 #define _EFM_DEVICE /**< Silicon Labs EFM-type MCU */
AnnaBridge 170:e95d10626187 164 #define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */
AnnaBridge 170:e95d10626187 165 #define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */
AnnaBridge 170:e95d10626187 166 #define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */
AnnaBridge 170:e95d10626187 167 #define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */
AnnaBridge 170:e95d10626187 168 #define _SILICON_LABS_GECKO_INTERNAL_SDID 100 /**< Silicon Labs internal use only, may change any time */
AnnaBridge 170:e95d10626187 169 #define _SILICON_LABS_GECKO_INTERNAL_SDID_100 /**< Silicon Labs internal use only, may change any time */
AnnaBridge 170:e95d10626187 170 #define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */
AnnaBridge 170:e95d10626187 171 #define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */
AnnaBridge 170:e95d10626187 172 #define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< @deprecated Platform 2, generation 1 */
AnnaBridge 170:e95d10626187 173 #define _SILICON_LABS_32B_PLATFORM_2_GEN 1 /**< @deprecated Platform 2, generation 1 */
AnnaBridge 170:e95d10626187 174
AnnaBridge 170:e95d10626187 175 /* If part number is not defined as compiler option, define it */
AnnaBridge 170:e95d10626187 176 #if !defined(EFM32GG11B820F2048GL152)
AnnaBridge 170:e95d10626187 177 #define EFM32GG11B820F2048GL152 1 /**< GIANT Gecko Part */
AnnaBridge 170:e95d10626187 178 #endif
AnnaBridge 170:e95d10626187 179
AnnaBridge 170:e95d10626187 180 /** Configure part number */
AnnaBridge 170:e95d10626187 181 #define PART_NUMBER "EFM32GG11B820F2048GL152" /**< Part Number */
AnnaBridge 170:e95d10626187 182
AnnaBridge 170:e95d10626187 183 /** Memory Base addresses and limits */
AnnaBridge 170:e95d10626187 184 #define RAM0_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM0_CODE base address */
AnnaBridge 170:e95d10626187 185 #define RAM0_CODE_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM0_CODE available address space */
AnnaBridge 170:e95d10626187 186 #define RAM0_CODE_MEM_END ((uint32_t) 0x1001FFFFUL) /**< RAM0_CODE end address */
AnnaBridge 170:e95d10626187 187 #define RAM0_CODE_MEM_BITS ((uint32_t) 0x00000011UL) /**< RAM0_CODE used bits */
AnnaBridge 170:e95d10626187 188 #define RAM2_MEM_BASE ((uint32_t) 0x20040000UL) /**< RAM2 base address */
AnnaBridge 170:e95d10626187 189 #define RAM2_MEM_SIZE ((uint32_t) 0x40000UL) /**< RAM2 available address space */
AnnaBridge 170:e95d10626187 190 #define RAM2_MEM_END ((uint32_t) 0x2007FFFFUL) /**< RAM2 end address */
AnnaBridge 170:e95d10626187 191 #define RAM2_MEM_BITS ((uint32_t) 0x00000012UL) /**< RAM2 used bits */
AnnaBridge 170:e95d10626187 192 #define RAM1_MEM_BASE ((uint32_t) 0x20020000UL) /**< RAM1 base address */
AnnaBridge 170:e95d10626187 193 #define RAM1_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM1 available address space */
AnnaBridge 170:e95d10626187 194 #define RAM1_MEM_END ((uint32_t) 0x2003FFFFUL) /**< RAM1 end address */
AnnaBridge 170:e95d10626187 195 #define RAM1_MEM_BITS ((uint32_t) 0x00000011UL) /**< RAM1 used bits */
AnnaBridge 170:e95d10626187 196 #define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */
AnnaBridge 170:e95d10626187 197 #define PER_MEM_SIZE ((uint32_t) 0x50000UL) /**< PER available address space */
AnnaBridge 170:e95d10626187 198 #define PER_MEM_END ((uint32_t) 0x4004FFFFUL) /**< PER end address */
AnnaBridge 170:e95d10626187 199 #define PER_MEM_BITS ((uint32_t) 0x00000013UL) /**< PER used bits */
AnnaBridge 170:e95d10626187 200 #define SDIO_MEM_BASE ((uint32_t) 0x400F1000UL) /**< SDIO base address */
AnnaBridge 170:e95d10626187 201 #define SDIO_MEM_SIZE ((uint32_t) 0x1000UL) /**< SDIO available address space */
AnnaBridge 170:e95d10626187 202 #define SDIO_MEM_END ((uint32_t) 0x400F1FFFUL) /**< SDIO end address */
AnnaBridge 170:e95d10626187 203 #define SDIO_MEM_BITS ((uint32_t) 0x0000000CUL) /**< SDIO used bits */
AnnaBridge 170:e95d10626187 204 #define RAM1_CODE_MEM_BASE ((uint32_t) 0x10020000UL) /**< RAM1_CODE base address */
AnnaBridge 170:e95d10626187 205 #define RAM1_CODE_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM1_CODE available address space */
AnnaBridge 170:e95d10626187 206 #define RAM1_CODE_MEM_END ((uint32_t) 0x1003FFFFUL) /**< RAM1_CODE end address */
AnnaBridge 170:e95d10626187 207 #define RAM1_CODE_MEM_BITS ((uint32_t) 0x00000011UL) /**< RAM1_CODE used bits */
AnnaBridge 170:e95d10626187 208 #define FLASH_MEM_BASE ((uint32_t) 0x00000000UL) /**< FLASH base address */
AnnaBridge 170:e95d10626187 209 #define FLASH_MEM_SIZE ((uint32_t) 0x4000000UL) /**< FLASH available address space */
AnnaBridge 170:e95d10626187 210 #define FLASH_MEM_END ((uint32_t) 0x03FFFFFFUL) /**< FLASH end address */
AnnaBridge 170:e95d10626187 211 #define FLASH_MEM_BITS ((uint32_t) 0x0000001AUL) /**< FLASH used bits */
AnnaBridge 170:e95d10626187 212 #define CRYPTO0_MEM_BASE ((uint32_t) 0x400F0000UL) /**< CRYPTO0 base address */
AnnaBridge 170:e95d10626187 213 #define CRYPTO0_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO0 available address space */
AnnaBridge 170:e95d10626187 214 #define CRYPTO0_MEM_END ((uint32_t) 0x400F03FFUL) /**< CRYPTO0 end address */
AnnaBridge 170:e95d10626187 215 #define CRYPTO0_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO0 used bits */
AnnaBridge 170:e95d10626187 216 #define QSPI0_MEM_BASE ((uint32_t) 0xC0000000UL) /**< QSPI0 base address */
AnnaBridge 170:e95d10626187 217 #define QSPI0_MEM_SIZE ((uint32_t) 0x10000000UL) /**< QSPI0 available address space */
AnnaBridge 170:e95d10626187 218 #define QSPI0_MEM_END ((uint32_t) 0xCFFFFFFFUL) /**< QSPI0 end address */
AnnaBridge 170:e95d10626187 219 #define QSPI0_MEM_BITS ((uint32_t) 0x0000001CUL) /**< QSPI0 used bits */
AnnaBridge 170:e95d10626187 220 #define PER1_BITCLR_MEM_BASE ((uint32_t) 0x44050000UL) /**< PER1_BITCLR base address */
AnnaBridge 170:e95d10626187 221 #define PER1_BITCLR_MEM_SIZE ((uint32_t) 0xA0000UL) /**< PER1_BITCLR available address space */
AnnaBridge 170:e95d10626187 222 #define PER1_BITCLR_MEM_END ((uint32_t) 0x440EFFFFUL) /**< PER1_BITCLR end address */
AnnaBridge 170:e95d10626187 223 #define PER1_BITCLR_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER1_BITCLR used bits */
AnnaBridge 170:e95d10626187 224 #define PER_BITCLR_MEM_BASE ((uint32_t) 0x44000000UL) /**< PER_BITCLR base address */
AnnaBridge 170:e95d10626187 225 #define PER_BITCLR_MEM_SIZE ((uint32_t) 0x50000UL) /**< PER_BITCLR available address space */
AnnaBridge 170:e95d10626187 226 #define PER_BITCLR_MEM_END ((uint32_t) 0x4404FFFFUL) /**< PER_BITCLR end address */
AnnaBridge 170:e95d10626187 227 #define PER_BITCLR_MEM_BITS ((uint32_t) 0x00000013UL) /**< PER_BITCLR used bits */
AnnaBridge 170:e95d10626187 228 #define PER1_BITSET_MEM_BASE ((uint32_t) 0x46050000UL) /**< PER1_BITSET base address */
AnnaBridge 170:e95d10626187 229 #define PER1_BITSET_MEM_SIZE ((uint32_t) 0xA0000UL) /**< PER1_BITSET available address space */
AnnaBridge 170:e95d10626187 230 #define PER1_BITSET_MEM_END ((uint32_t) 0x460EFFFFUL) /**< PER1_BITSET end address */
AnnaBridge 170:e95d10626187 231 #define PER1_BITSET_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER1_BITSET used bits */
AnnaBridge 170:e95d10626187 232 #define CRYPTO0_BITSET_MEM_BASE ((uint32_t) 0x460F0000UL) /**< CRYPTO0_BITSET base address */
AnnaBridge 170:e95d10626187 233 #define CRYPTO0_BITSET_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO0_BITSET available address space */
AnnaBridge 170:e95d10626187 234 #define CRYPTO0_BITSET_MEM_END ((uint32_t) 0x460F03FFUL) /**< CRYPTO0_BITSET end address */
AnnaBridge 170:e95d10626187 235 #define CRYPTO0_BITSET_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO0_BITSET used bits */
AnnaBridge 170:e95d10626187 236 #define USB_MEM_BASE ((uint32_t) 0x40100000UL) /**< USB base address */
AnnaBridge 170:e95d10626187 237 #define USB_MEM_SIZE ((uint32_t) 0x40000UL) /**< USB available address space */
AnnaBridge 170:e95d10626187 238 #define USB_MEM_END ((uint32_t) 0x4013FFFFUL) /**< USB end address */
AnnaBridge 170:e95d10626187 239 #define USB_MEM_BITS ((uint32_t) 0x00000012UL) /**< USB used bits */
AnnaBridge 170:e95d10626187 240 #define EBI_CODE_MEM_BASE ((uint32_t) 0x12000000UL) /**< EBI_CODE base address */
AnnaBridge 170:e95d10626187 241 #define EBI_CODE_MEM_SIZE ((uint32_t) 0xE000000UL) /**< EBI_CODE available address space */
AnnaBridge 170:e95d10626187 242 #define EBI_CODE_MEM_END ((uint32_t) 0x1FFFFFFFUL) /**< EBI_CODE end address */
AnnaBridge 170:e95d10626187 243 #define EBI_CODE_MEM_BITS ((uint32_t) 0x0000001CUL) /**< EBI_CODE used bits */
AnnaBridge 170:e95d10626187 244 #define CRYPTO0_BITCLR_MEM_BASE ((uint32_t) 0x440F0000UL) /**< CRYPTO0_BITCLR base address */
AnnaBridge 170:e95d10626187 245 #define CRYPTO0_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO0_BITCLR available address space */
AnnaBridge 170:e95d10626187 246 #define CRYPTO0_BITCLR_MEM_END ((uint32_t) 0x440F03FFUL) /**< CRYPTO0_BITCLR end address */
AnnaBridge 170:e95d10626187 247 #define CRYPTO0_BITCLR_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO0_BITCLR used bits */
AnnaBridge 170:e95d10626187 248 #define PER_BITSET_MEM_BASE ((uint32_t) 0x46000000UL) /**< PER_BITSET base address */
AnnaBridge 170:e95d10626187 249 #define PER_BITSET_MEM_SIZE ((uint32_t) 0x50000UL) /**< PER_BITSET available address space */
AnnaBridge 170:e95d10626187 250 #define PER_BITSET_MEM_END ((uint32_t) 0x4604FFFFUL) /**< PER_BITSET end address */
AnnaBridge 170:e95d10626187 251 #define PER_BITSET_MEM_BITS ((uint32_t) 0x00000013UL) /**< PER_BITSET used bits */
AnnaBridge 170:e95d10626187 252 #define PER1_MEM_BASE ((uint32_t) 0x40050000UL) /**< PER1 base address */
AnnaBridge 170:e95d10626187 253 #define PER1_MEM_SIZE ((uint32_t) 0xA0000UL) /**< PER1 available address space */
AnnaBridge 170:e95d10626187 254 #define PER1_MEM_END ((uint32_t) 0x400EFFFFUL) /**< PER1 end address */
AnnaBridge 170:e95d10626187 255 #define PER1_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER1 used bits */
AnnaBridge 170:e95d10626187 256 #define RAM2_CODE_MEM_BASE ((uint32_t) 0x10040000UL) /**< RAM2_CODE base address */
AnnaBridge 170:e95d10626187 257 #define RAM2_CODE_MEM_SIZE ((uint32_t) 0x40000UL) /**< RAM2_CODE available address space */
AnnaBridge 170:e95d10626187 258 #define RAM2_CODE_MEM_END ((uint32_t) 0x1007FFFFUL) /**< RAM2_CODE end address */
AnnaBridge 170:e95d10626187 259 #define RAM2_CODE_MEM_BITS ((uint32_t) 0x00000012UL) /**< RAM2_CODE used bits */
AnnaBridge 170:e95d10626187 260 #define QSPI0_CODE_MEM_BASE ((uint32_t) 0x04000000UL) /**< QSPI0_CODE base address */
AnnaBridge 170:e95d10626187 261 #define QSPI0_CODE_MEM_SIZE ((uint32_t) 0x8000000UL) /**< QSPI0_CODE available address space */
AnnaBridge 170:e95d10626187 262 #define QSPI0_CODE_MEM_END ((uint32_t) 0x0BFFFFFFUL) /**< QSPI0_CODE end address */
AnnaBridge 170:e95d10626187 263 #define QSPI0_CODE_MEM_BITS ((uint32_t) 0x0000001BUL) /**< QSPI0_CODE used bits */
AnnaBridge 170:e95d10626187 264 #define FLASH_INFO_MEM_BASE ((uint32_t) 0x0F000000UL) /**< FLASH_INFO base address */
AnnaBridge 170:e95d10626187 265 #define FLASH_INFO_MEM_SIZE ((uint32_t) 0x1000000UL) /**< FLASH_INFO available address space */
AnnaBridge 170:e95d10626187 266 #define FLASH_INFO_MEM_END ((uint32_t) 0x0FFFFFFFUL) /**< FLASH_INFO end address */
AnnaBridge 170:e95d10626187 267 #define FLASH_INFO_MEM_BITS ((uint32_t) 0x00000018UL) /**< FLASH_INFO used bits */
AnnaBridge 170:e95d10626187 268 #define RAM0_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM0 base address */
AnnaBridge 170:e95d10626187 269 #define RAM0_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM0 available address space */
AnnaBridge 170:e95d10626187 270 #define RAM0_MEM_END ((uint32_t) 0x2001FFFFUL) /**< RAM0 end address */
AnnaBridge 170:e95d10626187 271 #define RAM0_MEM_BITS ((uint32_t) 0x00000011UL) /**< RAM0 used bits */
AnnaBridge 170:e95d10626187 272 #define EBI_MEM_BASE ((uint32_t) 0x80000000UL) /**< EBI base address */
AnnaBridge 170:e95d10626187 273 #define EBI_MEM_SIZE ((uint32_t) 0x40000000UL) /**< EBI available address space */
AnnaBridge 170:e95d10626187 274 #define EBI_MEM_END ((uint32_t) 0xBFFFFFFFUL) /**< EBI end address */
AnnaBridge 170:e95d10626187 275 #define EBI_MEM_BITS ((uint32_t) 0x0000001EUL) /**< EBI used bits */
AnnaBridge 170:e95d10626187 276
AnnaBridge 170:e95d10626187 277 /** Single RAM space macros combining both RAM ports to match legacy, single-RAM-port chips */
AnnaBridge 170:e95d10626187 278 #define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */
AnnaBridge 170:e95d10626187 279 #define RAM_MEM_SIZE ((uint32_t) 0x80000UL) /**< RAM available address space */
AnnaBridge 170:e95d10626187 280 #define RAM_MEM_END ((uint32_t) 0x2007FFFFUL) /**< RAM end address */
AnnaBridge 170:e95d10626187 281 #define RAM_MEM_BITS ((uint32_t) 0x00000013UL) /**< RAM used bits */
AnnaBridge 170:e95d10626187 282
AnnaBridge 170:e95d10626187 283 /** Bit banding area */
AnnaBridge 170:e95d10626187 284 #define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */
AnnaBridge 170:e95d10626187 285 #define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */
AnnaBridge 170:e95d10626187 286
AnnaBridge 170:e95d10626187 287 /** Flash and SRAM limits for EFM32GG11B820F2048GL152 */
AnnaBridge 170:e95d10626187 288 #define FLASH_BASE (0x00000000UL) /**< Flash Base Address */
AnnaBridge 170:e95d10626187 289 #define FLASH_SIZE (0x00200000UL) /**< Available Flash Memory */
AnnaBridge 170:e95d10626187 290 #define FLASH_PAGE_SIZE 4096U /**< Flash Memory page size (interleaving off) */
AnnaBridge 170:e95d10626187 291 #define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */
AnnaBridge 170:e95d10626187 292 #define SRAM_SIZE (0x00080000UL) /**< Available SRAM Memory */
AnnaBridge 170:e95d10626187 293 #define __CM4_REV 0x001 /**< Cortex-M4 Core revision r0p1 */
AnnaBridge 170:e95d10626187 294 #define PRS_CHAN_COUNT 24 /**< Number of PRS channels */
AnnaBridge 170:e95d10626187 295 #define DMA_CHAN_COUNT 24 /**< Number of DMA channels */
AnnaBridge 170:e95d10626187 296 #define EXT_IRQ_COUNT 70 /**< Number of External (NVIC) interrupts */
AnnaBridge 170:e95d10626187 297
AnnaBridge 170:e95d10626187 298 /** AF channels connect the different on-chip peripherals with the af-mux */
AnnaBridge 170:e95d10626187 299 #define AFCHAN_MAX 355
AnnaBridge 170:e95d10626187 300 /** AF channel maximum location number */
AnnaBridge 170:e95d10626187 301 #define AFCHANLOC_MAX 8
AnnaBridge 170:e95d10626187 302 /** Analog AF channels */
AnnaBridge 170:e95d10626187 303 #define AFACHAN_MAX 184
AnnaBridge 170:e95d10626187 304
AnnaBridge 170:e95d10626187 305 /* Part number capabilities */
AnnaBridge 170:e95d10626187 306
AnnaBridge 170:e95d10626187 307 #define CRYPTO_PRESENT /**< CRYPTO is available in this part */
AnnaBridge 170:e95d10626187 308 #define CRYPTO_COUNT 1 /**< 1 CRYPTOs available */
AnnaBridge 170:e95d10626187 309 #define CAN_PRESENT /**< CAN is available in this part */
AnnaBridge 170:e95d10626187 310 #define CAN_COUNT 2 /**< 2 CANs available */
AnnaBridge 170:e95d10626187 311 #define TIMER_PRESENT /**< TIMER is available in this part */
AnnaBridge 170:e95d10626187 312 #define TIMER_COUNT 7 /**< 7 TIMERs available */
AnnaBridge 170:e95d10626187 313 #define WTIMER_PRESENT /**< WTIMER is available in this part */
AnnaBridge 170:e95d10626187 314 #define WTIMER_COUNT 4 /**< 4 WTIMERs available */
AnnaBridge 170:e95d10626187 315 #define USART_PRESENT /**< USART is available in this part */
AnnaBridge 170:e95d10626187 316 #define USART_COUNT 6 /**< 6 USARTs available */
AnnaBridge 170:e95d10626187 317 #define UART_PRESENT /**< UART is available in this part */
AnnaBridge 170:e95d10626187 318 #define UART_COUNT 2 /**< 2 UARTs available */
AnnaBridge 170:e95d10626187 319 #define QSPI_PRESENT /**< QSPI is available in this part */
AnnaBridge 170:e95d10626187 320 #define QSPI_COUNT 1 /**< 1 QSPIs available */
AnnaBridge 170:e95d10626187 321 #define LEUART_PRESENT /**< LEUART is available in this part */
AnnaBridge 170:e95d10626187 322 #define LEUART_COUNT 2 /**< 2 LEUARTs available */
AnnaBridge 170:e95d10626187 323 #define LETIMER_PRESENT /**< LETIMER is available in this part */
AnnaBridge 170:e95d10626187 324 #define LETIMER_COUNT 2 /**< 2 LETIMERs available */
AnnaBridge 170:e95d10626187 325 #define PCNT_PRESENT /**< PCNT is available in this part */
AnnaBridge 170:e95d10626187 326 #define PCNT_COUNT 3 /**< 3 PCNTs available */
AnnaBridge 170:e95d10626187 327 #define I2C_PRESENT /**< I2C is available in this part */
AnnaBridge 170:e95d10626187 328 #define I2C_COUNT 3 /**< 3 I2Cs available */
AnnaBridge 170:e95d10626187 329 #define ADC_PRESENT /**< ADC is available in this part */
AnnaBridge 170:e95d10626187 330 #define ADC_COUNT 2 /**< 2 ADCs available */
AnnaBridge 170:e95d10626187 331 #define ACMP_PRESENT /**< ACMP is available in this part */
AnnaBridge 170:e95d10626187 332 #define ACMP_COUNT 4 /**< 4 ACMPs available */
AnnaBridge 170:e95d10626187 333 #define VDAC_PRESENT /**< VDAC is available in this part */
AnnaBridge 170:e95d10626187 334 #define VDAC_COUNT 1 /**< 1 VDACs available */
AnnaBridge 170:e95d10626187 335 #define IDAC_PRESENT /**< IDAC is available in this part */
AnnaBridge 170:e95d10626187 336 #define IDAC_COUNT 1 /**< 1 IDACs available */
AnnaBridge 170:e95d10626187 337 #define WDOG_PRESENT /**< WDOG is available in this part */
AnnaBridge 170:e95d10626187 338 #define WDOG_COUNT 2 /**< 2 WDOGs available */
AnnaBridge 170:e95d10626187 339 #define TRNG_PRESENT /**< TRNG is available in this part */
AnnaBridge 170:e95d10626187 340 #define TRNG_COUNT 1 /**< 1 TRNGs available */
AnnaBridge 170:e95d10626187 341 #define MSC_PRESENT /**< MSC is available in this part */
AnnaBridge 170:e95d10626187 342 #define MSC_COUNT 1 /**< 1 MSC available */
AnnaBridge 170:e95d10626187 343 #define EMU_PRESENT /**< EMU is available in this part */
AnnaBridge 170:e95d10626187 344 #define EMU_COUNT 1 /**< 1 EMU available */
AnnaBridge 170:e95d10626187 345 #define RMU_PRESENT /**< RMU is available in this part */
AnnaBridge 170:e95d10626187 346 #define RMU_COUNT 1 /**< 1 RMU available */
AnnaBridge 170:e95d10626187 347 #define CMU_PRESENT /**< CMU is available in this part */
AnnaBridge 170:e95d10626187 348 #define CMU_COUNT 1 /**< 1 CMU available */
AnnaBridge 170:e95d10626187 349 #define LESENSE_PRESENT /**< LESENSE is available in this part */
AnnaBridge 170:e95d10626187 350 #define LESENSE_COUNT 1 /**< 1 LESENSE available */
AnnaBridge 170:e95d10626187 351 #define EBI_PRESENT /**< EBI is available in this part */
AnnaBridge 170:e95d10626187 352 #define EBI_COUNT 1 /**< 1 EBI available */
AnnaBridge 170:e95d10626187 353 #define ETH_PRESENT /**< ETH is available in this part */
AnnaBridge 170:e95d10626187 354 #define ETH_COUNT 1 /**< 1 ETH available */
AnnaBridge 170:e95d10626187 355 #define SDIO_PRESENT /**< SDIO is available in this part */
AnnaBridge 170:e95d10626187 356 #define SDIO_COUNT 1 /**< 1 SDIO available */
AnnaBridge 170:e95d10626187 357 #define GPIO_PRESENT /**< GPIO is available in this part */
AnnaBridge 170:e95d10626187 358 #define GPIO_COUNT 1 /**< 1 GPIO available */
AnnaBridge 170:e95d10626187 359 #define PRS_PRESENT /**< PRS is available in this part */
AnnaBridge 170:e95d10626187 360 #define PRS_COUNT 1 /**< 1 PRS available */
AnnaBridge 170:e95d10626187 361 #define LDMA_PRESENT /**< LDMA is available in this part */
AnnaBridge 170:e95d10626187 362 #define LDMA_COUNT 1 /**< 1 LDMA available */
AnnaBridge 170:e95d10626187 363 #define FPUEH_PRESENT /**< FPUEH is available in this part */
AnnaBridge 170:e95d10626187 364 #define FPUEH_COUNT 1 /**< 1 FPUEH available */
AnnaBridge 170:e95d10626187 365 #define GPCRC_PRESENT /**< GPCRC is available in this part */
AnnaBridge 170:e95d10626187 366 #define GPCRC_COUNT 1 /**< 1 GPCRC available */
AnnaBridge 170:e95d10626187 367 #define CRYOTIMER_PRESENT /**< CRYOTIMER is available in this part */
AnnaBridge 170:e95d10626187 368 #define CRYOTIMER_COUNT 1 /**< 1 CRYOTIMER available */
AnnaBridge 170:e95d10626187 369 #define USB_PRESENT /**< USB is available in this part */
AnnaBridge 170:e95d10626187 370 #define USB_COUNT 1 /**< 1 USB available */
AnnaBridge 170:e95d10626187 371 #define CSEN_PRESENT /**< CSEN is available in this part */
AnnaBridge 170:e95d10626187 372 #define CSEN_COUNT 1 /**< 1 CSEN available */
AnnaBridge 170:e95d10626187 373 #define LCD_PRESENT /**< LCD is available in this part */
AnnaBridge 170:e95d10626187 374 #define LCD_COUNT 1 /**< 1 LCD available */
AnnaBridge 170:e95d10626187 375 #define RTC_PRESENT /**< RTC is available in this part */
AnnaBridge 170:e95d10626187 376 #define RTC_COUNT 1 /**< 1 RTC available */
AnnaBridge 170:e95d10626187 377 #define RTCC_PRESENT /**< RTCC is available in this part */
AnnaBridge 170:e95d10626187 378 #define RTCC_COUNT 1 /**< 1 RTCC available */
AnnaBridge 170:e95d10626187 379 #define ETM_PRESENT /**< ETM is available in this part */
AnnaBridge 170:e95d10626187 380 #define ETM_COUNT 1 /**< 1 ETM available */
AnnaBridge 170:e95d10626187 381 #define BOOTLOADER_PRESENT /**< BOOTLOADER is available in this part */
AnnaBridge 170:e95d10626187 382 #define BOOTLOADER_COUNT 1 /**< 1 BOOTLOADER available */
AnnaBridge 170:e95d10626187 383 #define SMU_PRESENT /**< SMU is available in this part */
AnnaBridge 170:e95d10626187 384 #define SMU_COUNT 1 /**< 1 SMU available */
AnnaBridge 170:e95d10626187 385
AnnaBridge 170:e95d10626187 386 #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
AnnaBridge 170:e95d10626187 387 #include "system_efm32gg11b.h" /* System Header File */
AnnaBridge 170:e95d10626187 388
AnnaBridge 170:e95d10626187 389 /** @} End of group EFM32GG11B820F2048GL152_Part */
AnnaBridge 170:e95d10626187 390
AnnaBridge 170:e95d10626187 391 /**************************************************************************//**
AnnaBridge 170:e95d10626187 392 * @defgroup EFM32GG11B820F2048GL152_Peripheral_TypeDefs Peripheral TypeDefs
AnnaBridge 170:e95d10626187 393 * @{
AnnaBridge 170:e95d10626187 394 * @brief Device Specific Peripheral Register Structures
AnnaBridge 170:e95d10626187 395 *****************************************************************************/
AnnaBridge 170:e95d10626187 396
AnnaBridge 170:e95d10626187 397 #include "efm32gg11b_msc.h"
AnnaBridge 170:e95d10626187 398 #include "efm32gg11b_emu.h"
AnnaBridge 170:e95d10626187 399 #include "efm32gg11b_rmu.h"
AnnaBridge 170:e95d10626187 400 #include "efm32gg11b_cmu.h"
AnnaBridge 170:e95d10626187 401 #include "efm32gg11b_crypto.h"
AnnaBridge 170:e95d10626187 402 #include "efm32gg11b_lesense_st.h"
AnnaBridge 170:e95d10626187 403 #include "efm32gg11b_lesense_buf.h"
AnnaBridge 170:e95d10626187 404 #include "efm32gg11b_lesense_ch.h"
AnnaBridge 170:e95d10626187 405 #include "efm32gg11b_lesense.h"
AnnaBridge 170:e95d10626187 406 #include "efm32gg11b_ebi.h"
AnnaBridge 170:e95d10626187 407 #include "efm32gg11b_eth.h"
AnnaBridge 170:e95d10626187 408 #include "efm32gg11b_sdio.h"
AnnaBridge 170:e95d10626187 409 #include "efm32gg11b_gpio_p.h"
AnnaBridge 170:e95d10626187 410 #include "efm32gg11b_gpio.h"
AnnaBridge 170:e95d10626187 411 #include "efm32gg11b_prs_ch.h"
AnnaBridge 170:e95d10626187 412 #include "efm32gg11b_prs.h"
AnnaBridge 170:e95d10626187 413 #include "efm32gg11b_ldma_ch.h"
AnnaBridge 170:e95d10626187 414 #include "efm32gg11b_ldma.h"
AnnaBridge 170:e95d10626187 415 #include "efm32gg11b_fpueh.h"
AnnaBridge 170:e95d10626187 416 #include "efm32gg11b_gpcrc.h"
AnnaBridge 170:e95d10626187 417 #include "efm32gg11b_can_mir.h"
AnnaBridge 170:e95d10626187 418 #include "efm32gg11b_can.h"
AnnaBridge 170:e95d10626187 419 #include "efm32gg11b_timer_cc.h"
AnnaBridge 170:e95d10626187 420 #include "efm32gg11b_timer.h"
AnnaBridge 170:e95d10626187 421 #include "efm32gg11b_usart.h"
AnnaBridge 170:e95d10626187 422 #include "efm32gg11b_qspi.h"
AnnaBridge 170:e95d10626187 423 #include "efm32gg11b_leuart.h"
AnnaBridge 170:e95d10626187 424 #include "efm32gg11b_letimer.h"
AnnaBridge 170:e95d10626187 425 #include "efm32gg11b_cryotimer.h"
AnnaBridge 170:e95d10626187 426 #include "efm32gg11b_pcnt.h"
AnnaBridge 170:e95d10626187 427 #include "efm32gg11b_i2c.h"
AnnaBridge 170:e95d10626187 428 #include "efm32gg11b_adc.h"
AnnaBridge 170:e95d10626187 429 #include "efm32gg11b_acmp.h"
AnnaBridge 170:e95d10626187 430 #include "efm32gg11b_vdac_opa.h"
AnnaBridge 170:e95d10626187 431 #include "efm32gg11b_vdac.h"
AnnaBridge 170:e95d10626187 432 #include "efm32gg11b_usb_hc.h"
AnnaBridge 170:e95d10626187 433 #include "efm32gg11b_usb_diep.h"
AnnaBridge 170:e95d10626187 434 #include "efm32gg11b_usb_doep.h"
AnnaBridge 170:e95d10626187 435 #include "efm32gg11b_usb.h"
AnnaBridge 170:e95d10626187 436 #include "efm32gg11b_idac.h"
AnnaBridge 170:e95d10626187 437 #include "efm32gg11b_csen.h"
AnnaBridge 170:e95d10626187 438 #include "efm32gg11b_lcd.h"
AnnaBridge 170:e95d10626187 439 #include "efm32gg11b_rtc_comp.h"
AnnaBridge 170:e95d10626187 440 #include "efm32gg11b_rtc.h"
AnnaBridge 170:e95d10626187 441 #include "efm32gg11b_rtcc_cc.h"
AnnaBridge 170:e95d10626187 442 #include "efm32gg11b_rtcc_ret.h"
AnnaBridge 170:e95d10626187 443 #include "efm32gg11b_rtcc.h"
AnnaBridge 170:e95d10626187 444 #include "efm32gg11b_wdog_pch.h"
AnnaBridge 170:e95d10626187 445 #include "efm32gg11b_wdog.h"
AnnaBridge 170:e95d10626187 446 #include "efm32gg11b_etm.h"
AnnaBridge 170:e95d10626187 447 #include "efm32gg11b_smu.h"
AnnaBridge 170:e95d10626187 448 #include "efm32gg11b_trng.h"
AnnaBridge 170:e95d10626187 449 #include "efm32gg11b_dma_descriptor.h"
AnnaBridge 170:e95d10626187 450 #include "efm32gg11b_perpriv_register.h"
AnnaBridge 170:e95d10626187 451 #include "efm32gg11b_devinfo.h"
AnnaBridge 170:e95d10626187 452 #include "efm32gg11b_romtable.h"
AnnaBridge 170:e95d10626187 453
AnnaBridge 170:e95d10626187 454 /** @} End of group EFM32GG11B820F2048GL152_Peripheral_TypeDefs */
AnnaBridge 170:e95d10626187 455
AnnaBridge 170:e95d10626187 456 /**************************************************************************//**
AnnaBridge 170:e95d10626187 457 * @defgroup EFM32GG11B820F2048GL152_Peripheral_Base Peripheral Memory Map
AnnaBridge 170:e95d10626187 458 * @{
AnnaBridge 170:e95d10626187 459 *****************************************************************************/
AnnaBridge 170:e95d10626187 460
AnnaBridge 170:e95d10626187 461 #define MSC_BASE (0x40000000UL) /**< MSC base address */
AnnaBridge 170:e95d10626187 462 #define EMU_BASE (0x400E3000UL) /**< EMU base address */
AnnaBridge 170:e95d10626187 463 #define RMU_BASE (0x400E5000UL) /**< RMU base address */
AnnaBridge 170:e95d10626187 464 #define CMU_BASE (0x400E4000UL) /**< CMU base address */
AnnaBridge 170:e95d10626187 465 #define CRYPTO0_BASE (0x400F0000UL) /**< CRYPTO0 base address */
AnnaBridge 170:e95d10626187 466 #define LESENSE_BASE (0x40055000UL) /**< LESENSE base address */
AnnaBridge 170:e95d10626187 467 #define EBI_BASE (0x4000B000UL) /**< EBI base address */
AnnaBridge 170:e95d10626187 468 #define ETH_BASE (0x40024000UL) /**< ETH base address */
AnnaBridge 170:e95d10626187 469 #define SDIO_BASE (0x400F1000UL) /**< SDIO base address */
AnnaBridge 170:e95d10626187 470 #define GPIO_BASE (0x40088000UL) /**< GPIO base address */
AnnaBridge 170:e95d10626187 471 #define PRS_BASE (0x400E6000UL) /**< PRS base address */
AnnaBridge 170:e95d10626187 472 #define LDMA_BASE (0x40002000UL) /**< LDMA base address */
AnnaBridge 170:e95d10626187 473 #define FPUEH_BASE (0x40001000UL) /**< FPUEH base address */
AnnaBridge 170:e95d10626187 474 #define GPCRC_BASE (0x4001C000UL) /**< GPCRC base address */
AnnaBridge 170:e95d10626187 475 #define CAN0_BASE (0x40004000UL) /**< CAN0 base address */
AnnaBridge 170:e95d10626187 476 #define CAN1_BASE (0x40004400UL) /**< CAN1 base address */
AnnaBridge 170:e95d10626187 477 #define TIMER0_BASE (0x40018000UL) /**< TIMER0 base address */
AnnaBridge 170:e95d10626187 478 #define TIMER1_BASE (0x40018400UL) /**< TIMER1 base address */
AnnaBridge 170:e95d10626187 479 #define TIMER2_BASE (0x40018800UL) /**< TIMER2 base address */
AnnaBridge 170:e95d10626187 480 #define TIMER3_BASE (0x40018C00UL) /**< TIMER3 base address */
AnnaBridge 170:e95d10626187 481 #define TIMER4_BASE (0x40019000UL) /**< TIMER4 base address */
AnnaBridge 170:e95d10626187 482 #define TIMER5_BASE (0x40019400UL) /**< TIMER5 base address */
AnnaBridge 170:e95d10626187 483 #define TIMER6_BASE (0x40019800UL) /**< TIMER6 base address */
AnnaBridge 170:e95d10626187 484 #define WTIMER0_BASE (0x4001A000UL) /**< WTIMER0 base address */
AnnaBridge 170:e95d10626187 485 #define WTIMER1_BASE (0x4001A400UL) /**< WTIMER1 base address */
AnnaBridge 170:e95d10626187 486 #define WTIMER2_BASE (0x4001A800UL) /**< WTIMER2 base address */
AnnaBridge 170:e95d10626187 487 #define WTIMER3_BASE (0x4001AC00UL) /**< WTIMER3 base address */
AnnaBridge 170:e95d10626187 488 #define USART0_BASE (0x40010000UL) /**< USART0 base address */
AnnaBridge 170:e95d10626187 489 #define USART1_BASE (0x40010400UL) /**< USART1 base address */
AnnaBridge 170:e95d10626187 490 #define USART2_BASE (0x40010800UL) /**< USART2 base address */
AnnaBridge 170:e95d10626187 491 #define USART3_BASE (0x40010C00UL) /**< USART3 base address */
AnnaBridge 170:e95d10626187 492 #define USART4_BASE (0x40011000UL) /**< USART4 base address */
AnnaBridge 170:e95d10626187 493 #define USART5_BASE (0x40011400UL) /**< USART5 base address */
AnnaBridge 170:e95d10626187 494 #define UART0_BASE (0x40014000UL) /**< UART0 base address */
AnnaBridge 170:e95d10626187 495 #define UART1_BASE (0x40014400UL) /**< UART1 base address */
AnnaBridge 170:e95d10626187 496 #define QSPI0_BASE (0x4001C400UL) /**< QSPI0 base address */
AnnaBridge 170:e95d10626187 497 #define LEUART0_BASE (0x4006A000UL) /**< LEUART0 base address */
AnnaBridge 170:e95d10626187 498 #define LEUART1_BASE (0x4006A400UL) /**< LEUART1 base address */
AnnaBridge 170:e95d10626187 499 #define LETIMER0_BASE (0x40066000UL) /**< LETIMER0 base address */
AnnaBridge 170:e95d10626187 500 #define LETIMER1_BASE (0x40066400UL) /**< LETIMER1 base address */
AnnaBridge 170:e95d10626187 501 #define CRYOTIMER_BASE (0x4008F000UL) /**< CRYOTIMER base address */
AnnaBridge 170:e95d10626187 502 #define PCNT0_BASE (0x4006E000UL) /**< PCNT0 base address */
AnnaBridge 170:e95d10626187 503 #define PCNT1_BASE (0x4006E400UL) /**< PCNT1 base address */
AnnaBridge 170:e95d10626187 504 #define PCNT2_BASE (0x4006E800UL) /**< PCNT2 base address */
AnnaBridge 170:e95d10626187 505 #define I2C0_BASE (0x40089000UL) /**< I2C0 base address */
AnnaBridge 170:e95d10626187 506 #define I2C1_BASE (0x40089400UL) /**< I2C1 base address */
AnnaBridge 170:e95d10626187 507 #define I2C2_BASE (0x40089800UL) /**< I2C2 base address */
AnnaBridge 170:e95d10626187 508 #define ADC0_BASE (0x40082000UL) /**< ADC0 base address */
AnnaBridge 170:e95d10626187 509 #define ADC1_BASE (0x40082400UL) /**< ADC1 base address */
AnnaBridge 170:e95d10626187 510 #define ACMP0_BASE (0x40080000UL) /**< ACMP0 base address */
AnnaBridge 170:e95d10626187 511 #define ACMP1_BASE (0x40080400UL) /**< ACMP1 base address */
AnnaBridge 170:e95d10626187 512 #define ACMP2_BASE (0x40080800UL) /**< ACMP2 base address */
AnnaBridge 170:e95d10626187 513 #define ACMP3_BASE (0x40080C00UL) /**< ACMP3 base address */
AnnaBridge 170:e95d10626187 514 #define VDAC0_BASE (0x40086000UL) /**< VDAC0 base address */
AnnaBridge 170:e95d10626187 515 #define USB_BASE (0x40022000UL) /**< USB base address */
AnnaBridge 170:e95d10626187 516 #define IDAC0_BASE (0x40084000UL) /**< IDAC0 base address */
AnnaBridge 170:e95d10626187 517 #define CSEN_BASE (0x4008E000UL) /**< CSEN base address */
AnnaBridge 170:e95d10626187 518 #define LCD_BASE (0x40054000UL) /**< LCD base address */
AnnaBridge 170:e95d10626187 519 #define RTC_BASE (0x40060000UL) /**< RTC base address */
AnnaBridge 170:e95d10626187 520 #define RTCC_BASE (0x40062000UL) /**< RTCC base address */
AnnaBridge 170:e95d10626187 521 #define WDOG0_BASE (0x40052000UL) /**< WDOG0 base address */
AnnaBridge 170:e95d10626187 522 #define WDOG1_BASE (0x40052400UL) /**< WDOG1 base address */
AnnaBridge 170:e95d10626187 523 #define ETM_BASE (0xE0041000UL) /**< ETM base address */
AnnaBridge 170:e95d10626187 524 #define SMU_BASE (0x40020000UL) /**< SMU base address */
AnnaBridge 170:e95d10626187 525 #define TRNG0_BASE (0x4001D000UL) /**< TRNG0 base address */
AnnaBridge 170:e95d10626187 526 #define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */
AnnaBridge 170:e95d10626187 527 #define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */
AnnaBridge 170:e95d10626187 528 #define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */
AnnaBridge 170:e95d10626187 529 #define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */
AnnaBridge 170:e95d10626187 530
AnnaBridge 170:e95d10626187 531 /** @} End of group EFM32GG11B820F2048GL152_Peripheral_Base */
AnnaBridge 170:e95d10626187 532
AnnaBridge 170:e95d10626187 533 /**************************************************************************//**
AnnaBridge 170:e95d10626187 534 * @defgroup EFM32GG11B820F2048GL152_Peripheral_Declaration Peripheral Declarations
AnnaBridge 170:e95d10626187 535 * @{
AnnaBridge 170:e95d10626187 536 *****************************************************************************/
AnnaBridge 170:e95d10626187 537
AnnaBridge 170:e95d10626187 538 #define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */
AnnaBridge 170:e95d10626187 539 #define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */
AnnaBridge 170:e95d10626187 540 #define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */
AnnaBridge 170:e95d10626187 541 #define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */
AnnaBridge 170:e95d10626187 542 #define CRYPTO0 ((CRYPTO_TypeDef *) CRYPTO0_BASE) /**< CRYPTO0 base pointer */
AnnaBridge 170:e95d10626187 543 #define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE) /**< LESENSE base pointer */
AnnaBridge 170:e95d10626187 544 #define EBI ((EBI_TypeDef *) EBI_BASE) /**< EBI base pointer */
AnnaBridge 170:e95d10626187 545 #define ETH ((ETH_TypeDef *) ETH_BASE) /**< ETH base pointer */
AnnaBridge 170:e95d10626187 546 #define SDIO ((SDIO_TypeDef *) SDIO_BASE) /**< SDIO base pointer */
AnnaBridge 170:e95d10626187 547 #define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */
AnnaBridge 170:e95d10626187 548 #define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */
AnnaBridge 170:e95d10626187 549 #define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */
AnnaBridge 170:e95d10626187 550 #define FPUEH ((FPUEH_TypeDef *) FPUEH_BASE) /**< FPUEH base pointer */
AnnaBridge 170:e95d10626187 551 #define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */
AnnaBridge 170:e95d10626187 552 #define CAN0 ((CAN_TypeDef *) CAN0_BASE) /**< CAN0 base pointer */
AnnaBridge 170:e95d10626187 553 #define CAN1 ((CAN_TypeDef *) CAN1_BASE) /**< CAN1 base pointer */
AnnaBridge 170:e95d10626187 554 #define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */
AnnaBridge 170:e95d10626187 555 #define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */
AnnaBridge 170:e95d10626187 556 #define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */
AnnaBridge 170:e95d10626187 557 #define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */
AnnaBridge 170:e95d10626187 558 #define TIMER4 ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4 base pointer */
AnnaBridge 170:e95d10626187 559 #define TIMER5 ((TIMER_TypeDef *) TIMER5_BASE) /**< TIMER5 base pointer */
AnnaBridge 170:e95d10626187 560 #define TIMER6 ((TIMER_TypeDef *) TIMER6_BASE) /**< TIMER6 base pointer */
AnnaBridge 170:e95d10626187 561 #define WTIMER0 ((TIMER_TypeDef *) WTIMER0_BASE) /**< WTIMER0 base pointer */
AnnaBridge 170:e95d10626187 562 #define WTIMER1 ((TIMER_TypeDef *) WTIMER1_BASE) /**< WTIMER1 base pointer */
AnnaBridge 170:e95d10626187 563 #define WTIMER2 ((TIMER_TypeDef *) WTIMER2_BASE) /**< WTIMER2 base pointer */
AnnaBridge 170:e95d10626187 564 #define WTIMER3 ((TIMER_TypeDef *) WTIMER3_BASE) /**< WTIMER3 base pointer */
AnnaBridge 170:e95d10626187 565 #define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */
AnnaBridge 170:e95d10626187 566 #define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */
AnnaBridge 170:e95d10626187 567 #define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */
AnnaBridge 170:e95d10626187 568 #define USART3 ((USART_TypeDef *) USART3_BASE) /**< USART3 base pointer */
AnnaBridge 170:e95d10626187 569 #define USART4 ((USART_TypeDef *) USART4_BASE) /**< USART4 base pointer */
AnnaBridge 170:e95d10626187 570 #define USART5 ((USART_TypeDef *) USART5_BASE) /**< USART5 base pointer */
AnnaBridge 170:e95d10626187 571 #define UART0 ((USART_TypeDef *) UART0_BASE) /**< UART0 base pointer */
AnnaBridge 170:e95d10626187 572 #define UART1 ((USART_TypeDef *) UART1_BASE) /**< UART1 base pointer */
AnnaBridge 170:e95d10626187 573 #define QSPI0 ((QSPI_TypeDef *) QSPI0_BASE) /**< QSPI0 base pointer */
AnnaBridge 170:e95d10626187 574 #define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */
AnnaBridge 170:e95d10626187 575 #define LEUART1 ((LEUART_TypeDef *) LEUART1_BASE) /**< LEUART1 base pointer */
AnnaBridge 170:e95d10626187 576 #define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */
AnnaBridge 170:e95d10626187 577 #define LETIMER1 ((LETIMER_TypeDef *) LETIMER1_BASE) /**< LETIMER1 base pointer */
AnnaBridge 170:e95d10626187 578 #define CRYOTIMER ((CRYOTIMER_TypeDef *) CRYOTIMER_BASE) /**< CRYOTIMER base pointer */
AnnaBridge 170:e95d10626187 579 #define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */
AnnaBridge 170:e95d10626187 580 #define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */
AnnaBridge 170:e95d10626187 581 #define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */
AnnaBridge 170:e95d10626187 582 #define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */
AnnaBridge 170:e95d10626187 583 #define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */
AnnaBridge 170:e95d10626187 584 #define I2C2 ((I2C_TypeDef *) I2C2_BASE) /**< I2C2 base pointer */
AnnaBridge 170:e95d10626187 585 #define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */
AnnaBridge 170:e95d10626187 586 #define ADC1 ((ADC_TypeDef *) ADC1_BASE) /**< ADC1 base pointer */
AnnaBridge 170:e95d10626187 587 #define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */
AnnaBridge 170:e95d10626187 588 #define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */
AnnaBridge 170:e95d10626187 589 #define ACMP2 ((ACMP_TypeDef *) ACMP2_BASE) /**< ACMP2 base pointer */
AnnaBridge 170:e95d10626187 590 #define ACMP3 ((ACMP_TypeDef *) ACMP3_BASE) /**< ACMP3 base pointer */
AnnaBridge 170:e95d10626187 591 #define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0 base pointer */
AnnaBridge 170:e95d10626187 592 #define USB ((USB_TypeDef *) USB_BASE) /**< USB base pointer */
AnnaBridge 170:e95d10626187 593 #define IDAC0 ((IDAC_TypeDef *) IDAC0_BASE) /**< IDAC0 base pointer */
AnnaBridge 170:e95d10626187 594 #define CSEN ((CSEN_TypeDef *) CSEN_BASE) /**< CSEN base pointer */
AnnaBridge 170:e95d10626187 595 #define LCD ((LCD_TypeDef *) LCD_BASE) /**< LCD base pointer */
AnnaBridge 170:e95d10626187 596 #define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */
AnnaBridge 170:e95d10626187 597 #define RTCC ((RTCC_TypeDef *) RTCC_BASE) /**< RTCC base pointer */
AnnaBridge 170:e95d10626187 598 #define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */
AnnaBridge 170:e95d10626187 599 #define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1 base pointer */
AnnaBridge 170:e95d10626187 600 #define ETM ((ETM_TypeDef *) ETM_BASE) /**< ETM base pointer */
AnnaBridge 170:e95d10626187 601 #define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU base pointer */
AnnaBridge 170:e95d10626187 602 #define TRNG0 ((TRNG_TypeDef *) TRNG0_BASE) /**< TRNG0 base pointer */
AnnaBridge 170:e95d10626187 603 #define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */
AnnaBridge 170:e95d10626187 604 #define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */
AnnaBridge 170:e95d10626187 605
AnnaBridge 170:e95d10626187 606 /** @} End of group EFM32GG11B820F2048GL152_Peripheral_Declaration */
AnnaBridge 170:e95d10626187 607
AnnaBridge 170:e95d10626187 608 /**************************************************************************//**
AnnaBridge 170:e95d10626187 609 * @defgroup EFM32GG11B820F2048GL152_Peripheral_Offsets Peripheral Offsets
AnnaBridge 170:e95d10626187 610 * @{
AnnaBridge 170:e95d10626187 611 *****************************************************************************/
AnnaBridge 170:e95d10626187 612
AnnaBridge 170:e95d10626187 613 #define CRYPTO_OFFSET 0x400 /**< Offset in bytes between CRYPTO instances */
AnnaBridge 170:e95d10626187 614 #define CAN_OFFSET 0x400 /**< Offset in bytes between CAN instances */
AnnaBridge 170:e95d10626187 615 #define TIMER_OFFSET 0x400 /**< Offset in bytes between TIMER instances */
AnnaBridge 170:e95d10626187 616 #define WTIMER_OFFSET 0x400 /**< Offset in bytes between WTIMER instances */
AnnaBridge 170:e95d10626187 617 #define USART_OFFSET 0x400 /**< Offset in bytes between USART instances */
AnnaBridge 170:e95d10626187 618 #define UART_OFFSET 0x400 /**< Offset in bytes between UART instances */
AnnaBridge 170:e95d10626187 619 #define QSPI_OFFSET 0x400 /**< Offset in bytes between QSPI instances */
AnnaBridge 170:e95d10626187 620 #define LEUART_OFFSET 0x400 /**< Offset in bytes between LEUART instances */
AnnaBridge 170:e95d10626187 621 #define LETIMER_OFFSET 0x400 /**< Offset in bytes between LETIMER instances */
AnnaBridge 170:e95d10626187 622 #define PCNT_OFFSET 0x400 /**< Offset in bytes between PCNT instances */
AnnaBridge 170:e95d10626187 623 #define I2C_OFFSET 0x400 /**< Offset in bytes between I2C instances */
AnnaBridge 170:e95d10626187 624 #define ADC_OFFSET 0x400 /**< Offset in bytes between ADC instances */
AnnaBridge 170:e95d10626187 625 #define ACMP_OFFSET 0x400 /**< Offset in bytes between ACMP instances */
AnnaBridge 170:e95d10626187 626 #define VDAC_OFFSET 0x400 /**< Offset in bytes between VDAC instances */
AnnaBridge 170:e95d10626187 627 #define IDAC_OFFSET 0x400 /**< Offset in bytes between IDAC instances */
AnnaBridge 170:e95d10626187 628 #define WDOG_OFFSET 0x400 /**< Offset in bytes between WDOG instances */
AnnaBridge 170:e95d10626187 629 #define TRNG_OFFSET 0x400 /**< Offset in bytes between TRNG instances */
AnnaBridge 170:e95d10626187 630
AnnaBridge 170:e95d10626187 631 /** @} End of group EFM32GG11B820F2048GL152_Peripheral_Offsets */
AnnaBridge 170:e95d10626187 632
AnnaBridge 170:e95d10626187 633 /**************************************************************************//**
AnnaBridge 170:e95d10626187 634 * @defgroup EFM32GG11B820F2048GL152_BitFields Bit Fields
AnnaBridge 170:e95d10626187 635 * @{
AnnaBridge 170:e95d10626187 636 *****************************************************************************/
AnnaBridge 170:e95d10626187 637
AnnaBridge 170:e95d10626187 638 #include "efm32gg11b_prs_signals.h"
AnnaBridge 170:e95d10626187 639 #include "efm32gg11b_dmareq.h"
AnnaBridge 170:e95d10626187 640
AnnaBridge 170:e95d10626187 641 /**************************************************************************//**
AnnaBridge 170:e95d10626187 642 * @addtogroup EFM32GG11B820F2048GL152_WTIMER
AnnaBridge 170:e95d10626187 643 * @{
AnnaBridge 170:e95d10626187 644 * @defgroup EFM32GG11B820F2048GL152_WTIMER_BitFields WTIMER Bit Fields
AnnaBridge 170:e95d10626187 645 * @{
AnnaBridge 170:e95d10626187 646 *****************************************************************************/
AnnaBridge 170:e95d10626187 647
AnnaBridge 170:e95d10626187 648 /* Bit fields for WTIMER CTRL */
AnnaBridge 170:e95d10626187 649 #define _WTIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CTRL */
AnnaBridge 170:e95d10626187 650 #define _WTIMER_CTRL_MASK 0x3F036FFBUL /**< Mask for WTIMER_CTRL */
AnnaBridge 170:e95d10626187 651 #define _WTIMER_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */
AnnaBridge 170:e95d10626187 652 #define _WTIMER_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */
AnnaBridge 170:e95d10626187 653 #define _WTIMER_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */
AnnaBridge 170:e95d10626187 654 #define _WTIMER_CTRL_MODE_UP 0x00000000UL /**< Mode UP for WTIMER_CTRL */
AnnaBridge 170:e95d10626187 655 #define _WTIMER_CTRL_MODE_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_CTRL */
AnnaBridge 170:e95d10626187 656 #define _WTIMER_CTRL_MODE_UPDOWN 0x00000002UL /**< Mode UPDOWN for WTIMER_CTRL */
AnnaBridge 170:e95d10626187 657 #define _WTIMER_CTRL_MODE_QDEC 0x00000003UL /**< Mode QDEC for WTIMER_CTRL */
AnnaBridge 170:e95d10626187 658 #define WTIMER_CTRL_MODE_DEFAULT (_WTIMER_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CTRL */
AnnaBridge 170:e95d10626187 659 #define WTIMER_CTRL_MODE_UP (_WTIMER_CTRL_MODE_UP << 0) /**< Shifted mode UP for WTIMER_CTRL */
AnnaBridge 170:e95d10626187 660 #define WTIMER_CTRL_MODE_DOWN (_WTIMER_CTRL_MODE_DOWN << 0) /**< Shifted mode DOWN for WTIMER_CTRL */
AnnaBridge 170:e95d10626187 661 #define WTIMER_CTRL_MODE_UPDOWN (_WTIMER_CTRL_MODE_UPDOWN << 0) /**< Shifted mode UPDOWN for WTIMER_CTRL */
AnnaBridge 170:e95d10626187 662 #define WTIMER_CTRL_MODE_QDEC (_WTIMER_CTRL_MODE_QDEC << 0) /**< Shifted mode QDEC for WTIMER_CTRL */
AnnaBridge 170:e95d10626187 663 #define WTIMER_CTRL_SYNC (0x1UL << 3) /**< Timer Start/Stop/Reload Synchronization */
AnnaBridge 170:e95d10626187 664 #define _WTIMER_CTRL_SYNC_SHIFT 3 /**< Shift value for TIMER_SYNC */
AnnaBridge 170:e95d10626187 665 #define _WTIMER_CTRL_SYNC_MASK 0x8UL /**< Bit mask for TIMER_SYNC */
AnnaBridge 170:e95d10626187 666 #define _WTIMER_CTRL_SYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */
AnnaBridge 170:e95d10626187 667 #define WTIMER_CTRL_SYNC_DEFAULT (_WTIMER_CTRL_SYNC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_CTRL */
AnnaBridge 170:e95d10626187 668 #define WTIMER_CTRL_OSMEN (0x1UL << 4) /**< One-shot Mode Enable */
AnnaBridge 170:e95d10626187 669 #define _WTIMER_CTRL_OSMEN_SHIFT 4 /**< Shift value for TIMER_OSMEN */
AnnaBridge 170:e95d10626187 670 #define _WTIMER_CTRL_OSMEN_MASK 0x10UL /**< Bit mask for TIMER_OSMEN */
AnnaBridge 170:e95d10626187 671 #define _WTIMER_CTRL_OSMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */
AnnaBridge 170:e95d10626187 672 #define WTIMER_CTRL_OSMEN_DEFAULT (_WTIMER_CTRL_OSMEN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CTRL */
AnnaBridge 170:e95d10626187 673 #define WTIMER_CTRL_QDM (0x1UL << 5) /**< Quadrature Decoder Mode Selection */
AnnaBridge 170:e95d10626187 674 #define _WTIMER_CTRL_QDM_SHIFT 5 /**< Shift value for TIMER_QDM */
AnnaBridge 170:e95d10626187 675 #define _WTIMER_CTRL_QDM_MASK 0x20UL /**< Bit mask for TIMER_QDM */
AnnaBridge 170:e95d10626187 676 #define _WTIMER_CTRL_QDM_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */
AnnaBridge 170:e95d10626187 677 #define _WTIMER_CTRL_QDM_X2 0x00000000UL /**< Mode X2 for WTIMER_CTRL */
AnnaBridge 170:e95d10626187 678 #define _WTIMER_CTRL_QDM_X4 0x00000001UL /**< Mode X4 for WTIMER_CTRL */
AnnaBridge 170:e95d10626187 679 #define WTIMER_CTRL_QDM_DEFAULT (_WTIMER_CTRL_QDM_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_CTRL */
AnnaBridge 170:e95d10626187 680 #define WTIMER_CTRL_QDM_X2 (_WTIMER_CTRL_QDM_X2 << 5) /**< Shifted mode X2 for WTIMER_CTRL */
AnnaBridge 170:e95d10626187 681 #define WTIMER_CTRL_QDM_X4 (_WTIMER_CTRL_QDM_X4 << 5) /**< Shifted mode X4 for WTIMER_CTRL */
AnnaBridge 170:e95d10626187 682 #define WTIMER_CTRL_DEBUGRUN (0x1UL << 6) /**< Debug Mode Run Enable */
AnnaBridge 170:e95d10626187 683 #define _WTIMER_CTRL_DEBUGRUN_SHIFT 6 /**< Shift value for TIMER_DEBUGRUN */
AnnaBridge 170:e95d10626187 684 #define _WTIMER_CTRL_DEBUGRUN_MASK 0x40UL /**< Bit mask for TIMER_DEBUGRUN */
AnnaBridge 170:e95d10626187 685 #define _WTIMER_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */
AnnaBridge 170:e95d10626187 686 #define WTIMER_CTRL_DEBUGRUN_DEFAULT (_WTIMER_CTRL_DEBUGRUN_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_CTRL */
AnnaBridge 170:e95d10626187 687 #define WTIMER_CTRL_DMACLRACT (0x1UL << 7) /**< DMA Request Clear on Active */
AnnaBridge 170:e95d10626187 688 #define _WTIMER_CTRL_DMACLRACT_SHIFT 7 /**< Shift value for TIMER_DMACLRACT */
AnnaBridge 170:e95d10626187 689 #define _WTIMER_CTRL_DMACLRACT_MASK 0x80UL /**< Bit mask for TIMER_DMACLRACT */
AnnaBridge 170:e95d10626187 690 #define _WTIMER_CTRL_DMACLRACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */
AnnaBridge 170:e95d10626187 691 #define WTIMER_CTRL_DMACLRACT_DEFAULT (_WTIMER_CTRL_DMACLRACT_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_CTRL */
AnnaBridge 170:e95d10626187 692 #define _WTIMER_CTRL_RISEA_SHIFT 8 /**< Shift value for TIMER_RISEA */
AnnaBridge 170:e95d10626187 693 #define _WTIMER_CTRL_RISEA_MASK 0x300UL /**< Bit mask for TIMER_RISEA */
AnnaBridge 170:e95d10626187 694 #define _WTIMER_CTRL_RISEA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */
AnnaBridge 170:e95d10626187 695 #define _WTIMER_CTRL_RISEA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */
AnnaBridge 170:e95d10626187 696 #define _WTIMER_CTRL_RISEA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */
AnnaBridge 170:e95d10626187 697 #define _WTIMER_CTRL_RISEA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */
AnnaBridge 170:e95d10626187 698 #define _WTIMER_CTRL_RISEA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */
AnnaBridge 170:e95d10626187 699 #define WTIMER_CTRL_RISEA_DEFAULT (_WTIMER_CTRL_RISEA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CTRL */
AnnaBridge 170:e95d10626187 700 #define WTIMER_CTRL_RISEA_NONE (_WTIMER_CTRL_RISEA_NONE << 8) /**< Shifted mode NONE for WTIMER_CTRL */
AnnaBridge 170:e95d10626187 701 #define WTIMER_CTRL_RISEA_START (_WTIMER_CTRL_RISEA_START << 8) /**< Shifted mode START for WTIMER_CTRL */
AnnaBridge 170:e95d10626187 702 #define WTIMER_CTRL_RISEA_STOP (_WTIMER_CTRL_RISEA_STOP << 8) /**< Shifted mode STOP for WTIMER_CTRL */
AnnaBridge 170:e95d10626187 703 #define WTIMER_CTRL_RISEA_RELOADSTART (_WTIMER_CTRL_RISEA_RELOADSTART << 8) /**< Shifted mode RELOADSTART for WTIMER_CTRL */
AnnaBridge 170:e95d10626187 704 #define _WTIMER_CTRL_FALLA_SHIFT 10 /**< Shift value for TIMER_FALLA */
AnnaBridge 170:e95d10626187 705 #define _WTIMER_CTRL_FALLA_MASK 0xC00UL /**< Bit mask for TIMER_FALLA */
AnnaBridge 170:e95d10626187 706 #define _WTIMER_CTRL_FALLA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */
AnnaBridge 170:e95d10626187 707 #define _WTIMER_CTRL_FALLA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */
AnnaBridge 170:e95d10626187 708 #define _WTIMER_CTRL_FALLA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */
AnnaBridge 170:e95d10626187 709 #define _WTIMER_CTRL_FALLA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */
AnnaBridge 170:e95d10626187 710 #define _WTIMER_CTRL_FALLA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */
AnnaBridge 170:e95d10626187 711 #define WTIMER_CTRL_FALLA_DEFAULT (_WTIMER_CTRL_FALLA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CTRL */
AnnaBridge 170:e95d10626187 712 #define WTIMER_CTRL_FALLA_NONE (_WTIMER_CTRL_FALLA_NONE << 10) /**< Shifted mode NONE for WTIMER_CTRL */
AnnaBridge 170:e95d10626187 713 #define WTIMER_CTRL_FALLA_START (_WTIMER_CTRL_FALLA_START << 10) /**< Shifted mode START for WTIMER_CTRL */
AnnaBridge 170:e95d10626187 714 #define WTIMER_CTRL_FALLA_STOP (_WTIMER_CTRL_FALLA_STOP << 10) /**< Shifted mode STOP for WTIMER_CTRL */
AnnaBridge 170:e95d10626187 715 #define WTIMER_CTRL_FALLA_RELOADSTART (_WTIMER_CTRL_FALLA_RELOADSTART << 10) /**< Shifted mode RELOADSTART for WTIMER_CTRL */
AnnaBridge 170:e95d10626187 716 #define WTIMER_CTRL_X2CNT (0x1UL << 13) /**< 2x Count Mode */
AnnaBridge 170:e95d10626187 717 #define _WTIMER_CTRL_X2CNT_SHIFT 13 /**< Shift value for TIMER_X2CNT */
AnnaBridge 170:e95d10626187 718 #define _WTIMER_CTRL_X2CNT_MASK 0x2000UL /**< Bit mask for TIMER_X2CNT */
AnnaBridge 170:e95d10626187 719 #define _WTIMER_CTRL_X2CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */
AnnaBridge 170:e95d10626187 720 #define WTIMER_CTRL_X2CNT_DEFAULT (_WTIMER_CTRL_X2CNT_DEFAULT << 13) /**< Shifted mode DEFAULT for WTIMER_CTRL */
AnnaBridge 170:e95d10626187 721 #define WTIMER_CTRL_DISSYNCOUT (0x1UL << 14) /**< Disable Timer from Start/Stop/Reload other Synchronized Timers */
AnnaBridge 170:e95d10626187 722 #define _WTIMER_CTRL_DISSYNCOUT_SHIFT 14 /**< Shift value for TIMER_DISSYNCOUT */
AnnaBridge 170:e95d10626187 723 #define _WTIMER_CTRL_DISSYNCOUT_MASK 0x4000UL /**< Bit mask for TIMER_DISSYNCOUT */
AnnaBridge 170:e95d10626187 724 #define _WTIMER_CTRL_DISSYNCOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */
AnnaBridge 170:e95d10626187 725 #define WTIMER_CTRL_DISSYNCOUT_DEFAULT (_WTIMER_CTRL_DISSYNCOUT_DEFAULT << 14) /**< Shifted mode DEFAULT for WTIMER_CTRL */
AnnaBridge 170:e95d10626187 726 #define _WTIMER_CTRL_CLKSEL_SHIFT 16 /**< Shift value for TIMER_CLKSEL */
AnnaBridge 170:e95d10626187 727 #define _WTIMER_CTRL_CLKSEL_MASK 0x30000UL /**< Bit mask for TIMER_CLKSEL */
AnnaBridge 170:e95d10626187 728 #define _WTIMER_CTRL_CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */
AnnaBridge 170:e95d10626187 729 #define _WTIMER_CTRL_CLKSEL_PRESCHFPERCLK 0x00000000UL /**< Mode PRESCHFPERCLK for WTIMER_CTRL */
AnnaBridge 170:e95d10626187 730 #define _WTIMER_CTRL_CLKSEL_CC1 0x00000001UL /**< Mode CC1 for WTIMER_CTRL */
AnnaBridge 170:e95d10626187 731 #define _WTIMER_CTRL_CLKSEL_TIMEROUF 0x00000002UL /**< Mode TIMEROUF for WTIMER_CTRL */
AnnaBridge 170:e95d10626187 732 #define WTIMER_CTRL_CLKSEL_DEFAULT (_WTIMER_CTRL_CLKSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CTRL */
AnnaBridge 170:e95d10626187 733 #define WTIMER_CTRL_CLKSEL_PRESCHFPERCLK (_WTIMER_CTRL_CLKSEL_PRESCHFPERCLK << 16) /**< Shifted mode PRESCHFPERCLK for WTIMER_CTRL */
AnnaBridge 170:e95d10626187 734 #define WTIMER_CTRL_CLKSEL_CC1 (_WTIMER_CTRL_CLKSEL_CC1 << 16) /**< Shifted mode CC1 for WTIMER_CTRL */
AnnaBridge 170:e95d10626187 735 #define WTIMER_CTRL_CLKSEL_TIMEROUF (_WTIMER_CTRL_CLKSEL_TIMEROUF << 16) /**< Shifted mode TIMEROUF for WTIMER_CTRL */
AnnaBridge 170:e95d10626187 736 #define _WTIMER_CTRL_PRESC_SHIFT 24 /**< Shift value for TIMER_PRESC */
AnnaBridge 170:e95d10626187 737 #define _WTIMER_CTRL_PRESC_MASK 0xF000000UL /**< Bit mask for TIMER_PRESC */
AnnaBridge 170:e95d10626187 738 #define _WTIMER_CTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */
AnnaBridge 170:e95d10626187 739 #define _WTIMER_CTRL_PRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_CTRL */
AnnaBridge 170:e95d10626187 740 #define _WTIMER_CTRL_PRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_CTRL */
AnnaBridge 170:e95d10626187 741 #define _WTIMER_CTRL_PRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_CTRL */
AnnaBridge 170:e95d10626187 742 #define _WTIMER_CTRL_PRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_CTRL */
AnnaBridge 170:e95d10626187 743 #define _WTIMER_CTRL_PRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_CTRL */
AnnaBridge 170:e95d10626187 744 #define _WTIMER_CTRL_PRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_CTRL */
AnnaBridge 170:e95d10626187 745 #define _WTIMER_CTRL_PRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_CTRL */
AnnaBridge 170:e95d10626187 746 #define _WTIMER_CTRL_PRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_CTRL */
AnnaBridge 170:e95d10626187 747 #define _WTIMER_CTRL_PRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_CTRL */
AnnaBridge 170:e95d10626187 748 #define _WTIMER_CTRL_PRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_CTRL */
AnnaBridge 170:e95d10626187 749 #define _WTIMER_CTRL_PRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_CTRL */
AnnaBridge 170:e95d10626187 750 #define WTIMER_CTRL_PRESC_DEFAULT (_WTIMER_CTRL_PRESC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CTRL */
AnnaBridge 170:e95d10626187 751 #define WTIMER_CTRL_PRESC_DIV1 (_WTIMER_CTRL_PRESC_DIV1 << 24) /**< Shifted mode DIV1 for WTIMER_CTRL */
AnnaBridge 170:e95d10626187 752 #define WTIMER_CTRL_PRESC_DIV2 (_WTIMER_CTRL_PRESC_DIV2 << 24) /**< Shifted mode DIV2 for WTIMER_CTRL */
AnnaBridge 170:e95d10626187 753 #define WTIMER_CTRL_PRESC_DIV4 (_WTIMER_CTRL_PRESC_DIV4 << 24) /**< Shifted mode DIV4 for WTIMER_CTRL */
AnnaBridge 170:e95d10626187 754 #define WTIMER_CTRL_PRESC_DIV8 (_WTIMER_CTRL_PRESC_DIV8 << 24) /**< Shifted mode DIV8 for WTIMER_CTRL */
AnnaBridge 170:e95d10626187 755 #define WTIMER_CTRL_PRESC_DIV16 (_WTIMER_CTRL_PRESC_DIV16 << 24) /**< Shifted mode DIV16 for WTIMER_CTRL */
AnnaBridge 170:e95d10626187 756 #define WTIMER_CTRL_PRESC_DIV32 (_WTIMER_CTRL_PRESC_DIV32 << 24) /**< Shifted mode DIV32 for WTIMER_CTRL */
AnnaBridge 170:e95d10626187 757 #define WTIMER_CTRL_PRESC_DIV64 (_WTIMER_CTRL_PRESC_DIV64 << 24) /**< Shifted mode DIV64 for WTIMER_CTRL */
AnnaBridge 170:e95d10626187 758 #define WTIMER_CTRL_PRESC_DIV128 (_WTIMER_CTRL_PRESC_DIV128 << 24) /**< Shifted mode DIV128 for WTIMER_CTRL */
AnnaBridge 170:e95d10626187 759 #define WTIMER_CTRL_PRESC_DIV256 (_WTIMER_CTRL_PRESC_DIV256 << 24) /**< Shifted mode DIV256 for WTIMER_CTRL */
AnnaBridge 170:e95d10626187 760 #define WTIMER_CTRL_PRESC_DIV512 (_WTIMER_CTRL_PRESC_DIV512 << 24) /**< Shifted mode DIV512 for WTIMER_CTRL */
AnnaBridge 170:e95d10626187 761 #define WTIMER_CTRL_PRESC_DIV1024 (_WTIMER_CTRL_PRESC_DIV1024 << 24) /**< Shifted mode DIV1024 for WTIMER_CTRL */
AnnaBridge 170:e95d10626187 762 #define WTIMER_CTRL_ATI (0x1UL << 28) /**< Always Track Inputs */
AnnaBridge 170:e95d10626187 763 #define _WTIMER_CTRL_ATI_SHIFT 28 /**< Shift value for TIMER_ATI */
AnnaBridge 170:e95d10626187 764 #define _WTIMER_CTRL_ATI_MASK 0x10000000UL /**< Bit mask for TIMER_ATI */
AnnaBridge 170:e95d10626187 765 #define _WTIMER_CTRL_ATI_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */
AnnaBridge 170:e95d10626187 766 #define WTIMER_CTRL_ATI_DEFAULT (_WTIMER_CTRL_ATI_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CTRL */
AnnaBridge 170:e95d10626187 767 #define WTIMER_CTRL_RSSCOIST (0x1UL << 29) /**< Reload-Start Sets Compare Output initial State */
AnnaBridge 170:e95d10626187 768 #define _WTIMER_CTRL_RSSCOIST_SHIFT 29 /**< Shift value for TIMER_RSSCOIST */
AnnaBridge 170:e95d10626187 769 #define _WTIMER_CTRL_RSSCOIST_MASK 0x20000000UL /**< Bit mask for TIMER_RSSCOIST */
AnnaBridge 170:e95d10626187 770 #define _WTIMER_CTRL_RSSCOIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */
AnnaBridge 170:e95d10626187 771 #define WTIMER_CTRL_RSSCOIST_DEFAULT (_WTIMER_CTRL_RSSCOIST_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CTRL */
AnnaBridge 170:e95d10626187 772
AnnaBridge 170:e95d10626187 773 /* Bit fields for WTIMER CMD */
AnnaBridge 170:e95d10626187 774 #define _WTIMER_CMD_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CMD */
AnnaBridge 170:e95d10626187 775 #define _WTIMER_CMD_MASK 0x00000003UL /**< Mask for WTIMER_CMD */
AnnaBridge 170:e95d10626187 776 #define WTIMER_CMD_START (0x1UL << 0) /**< Start Timer */
AnnaBridge 170:e95d10626187 777 #define _WTIMER_CMD_START_SHIFT 0 /**< Shift value for TIMER_START */
AnnaBridge 170:e95d10626187 778 #define _WTIMER_CMD_START_MASK 0x1UL /**< Bit mask for TIMER_START */
AnnaBridge 170:e95d10626187 779 #define _WTIMER_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */
AnnaBridge 170:e95d10626187 780 #define WTIMER_CMD_START_DEFAULT (_WTIMER_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CMD */
AnnaBridge 170:e95d10626187 781 #define WTIMER_CMD_STOP (0x1UL << 1) /**< Stop Timer */
AnnaBridge 170:e95d10626187 782 #define _WTIMER_CMD_STOP_SHIFT 1 /**< Shift value for TIMER_STOP */
AnnaBridge 170:e95d10626187 783 #define _WTIMER_CMD_STOP_MASK 0x2UL /**< Bit mask for TIMER_STOP */
AnnaBridge 170:e95d10626187 784 #define _WTIMER_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */
AnnaBridge 170:e95d10626187 785 #define WTIMER_CMD_STOP_DEFAULT (_WTIMER_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_CMD */
AnnaBridge 170:e95d10626187 786
AnnaBridge 170:e95d10626187 787 /* Bit fields for WTIMER STATUS */
AnnaBridge 170:e95d10626187 788 #define _WTIMER_STATUS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_STATUS */
AnnaBridge 170:e95d10626187 789 #define _WTIMER_STATUS_MASK 0x0F0F0F07UL /**< Mask for WTIMER_STATUS */
AnnaBridge 170:e95d10626187 790 #define WTIMER_STATUS_RUNNING (0x1UL << 0) /**< Running */
AnnaBridge 170:e95d10626187 791 #define _WTIMER_STATUS_RUNNING_SHIFT 0 /**< Shift value for TIMER_RUNNING */
AnnaBridge 170:e95d10626187 792 #define _WTIMER_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for TIMER_RUNNING */
AnnaBridge 170:e95d10626187 793 #define _WTIMER_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */
AnnaBridge 170:e95d10626187 794 #define WTIMER_STATUS_RUNNING_DEFAULT (_WTIMER_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_STATUS */
AnnaBridge 170:e95d10626187 795 #define WTIMER_STATUS_DIR (0x1UL << 1) /**< Direction */
AnnaBridge 170:e95d10626187 796 #define _WTIMER_STATUS_DIR_SHIFT 1 /**< Shift value for TIMER_DIR */
AnnaBridge 170:e95d10626187 797 #define _WTIMER_STATUS_DIR_MASK 0x2UL /**< Bit mask for TIMER_DIR */
AnnaBridge 170:e95d10626187 798 #define _WTIMER_STATUS_DIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */
AnnaBridge 170:e95d10626187 799 #define _WTIMER_STATUS_DIR_UP 0x00000000UL /**< Mode UP for WTIMER_STATUS */
AnnaBridge 170:e95d10626187 800 #define _WTIMER_STATUS_DIR_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_STATUS */
AnnaBridge 170:e95d10626187 801 #define WTIMER_STATUS_DIR_DEFAULT (_WTIMER_STATUS_DIR_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_STATUS */
AnnaBridge 170:e95d10626187 802 #define WTIMER_STATUS_DIR_UP (_WTIMER_STATUS_DIR_UP << 1) /**< Shifted mode UP for WTIMER_STATUS */
AnnaBridge 170:e95d10626187 803 #define WTIMER_STATUS_DIR_DOWN (_WTIMER_STATUS_DIR_DOWN << 1) /**< Shifted mode DOWN for WTIMER_STATUS */
AnnaBridge 170:e95d10626187 804 #define WTIMER_STATUS_TOPBV (0x1UL << 2) /**< TOPB Valid */
AnnaBridge 170:e95d10626187 805 #define _WTIMER_STATUS_TOPBV_SHIFT 2 /**< Shift value for TIMER_TOPBV */
AnnaBridge 170:e95d10626187 806 #define _WTIMER_STATUS_TOPBV_MASK 0x4UL /**< Bit mask for TIMER_TOPBV */
AnnaBridge 170:e95d10626187 807 #define _WTIMER_STATUS_TOPBV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */
AnnaBridge 170:e95d10626187 808 #define WTIMER_STATUS_TOPBV_DEFAULT (_WTIMER_STATUS_TOPBV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_STATUS */
AnnaBridge 170:e95d10626187 809 #define WTIMER_STATUS_CCVBV0 (0x1UL << 8) /**< CC0 CCVB Valid */
AnnaBridge 170:e95d10626187 810 #define _WTIMER_STATUS_CCVBV0_SHIFT 8 /**< Shift value for TIMER_CCVBV0 */
AnnaBridge 170:e95d10626187 811 #define _WTIMER_STATUS_CCVBV0_MASK 0x100UL /**< Bit mask for TIMER_CCVBV0 */
AnnaBridge 170:e95d10626187 812 #define _WTIMER_STATUS_CCVBV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */
AnnaBridge 170:e95d10626187 813 #define WTIMER_STATUS_CCVBV0_DEFAULT (_WTIMER_STATUS_CCVBV0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_STATUS */
AnnaBridge 170:e95d10626187 814 #define WTIMER_STATUS_CCVBV1 (0x1UL << 9) /**< CC1 CCVB Valid */
AnnaBridge 170:e95d10626187 815 #define _WTIMER_STATUS_CCVBV1_SHIFT 9 /**< Shift value for TIMER_CCVBV1 */
AnnaBridge 170:e95d10626187 816 #define _WTIMER_STATUS_CCVBV1_MASK 0x200UL /**< Bit mask for TIMER_CCVBV1 */
AnnaBridge 170:e95d10626187 817 #define _WTIMER_STATUS_CCVBV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */
AnnaBridge 170:e95d10626187 818 #define WTIMER_STATUS_CCVBV1_DEFAULT (_WTIMER_STATUS_CCVBV1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_STATUS */
AnnaBridge 170:e95d10626187 819 #define WTIMER_STATUS_CCVBV2 (0x1UL << 10) /**< CC2 CCVB Valid */
AnnaBridge 170:e95d10626187 820 #define _WTIMER_STATUS_CCVBV2_SHIFT 10 /**< Shift value for TIMER_CCVBV2 */
AnnaBridge 170:e95d10626187 821 #define _WTIMER_STATUS_CCVBV2_MASK 0x400UL /**< Bit mask for TIMER_CCVBV2 */
AnnaBridge 170:e95d10626187 822 #define _WTIMER_STATUS_CCVBV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */
AnnaBridge 170:e95d10626187 823 #define WTIMER_STATUS_CCVBV2_DEFAULT (_WTIMER_STATUS_CCVBV2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_STATUS */
AnnaBridge 170:e95d10626187 824 #define WTIMER_STATUS_CCVBV3 (0x1UL << 11) /**< CC3 CCVB Valid */
AnnaBridge 170:e95d10626187 825 #define _WTIMER_STATUS_CCVBV3_SHIFT 11 /**< Shift value for TIMER_CCVBV3 */
AnnaBridge 170:e95d10626187 826 #define _WTIMER_STATUS_CCVBV3_MASK 0x800UL /**< Bit mask for TIMER_CCVBV3 */
AnnaBridge 170:e95d10626187 827 #define _WTIMER_STATUS_CCVBV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */
AnnaBridge 170:e95d10626187 828 #define WTIMER_STATUS_CCVBV3_DEFAULT (_WTIMER_STATUS_CCVBV3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_STATUS */
AnnaBridge 170:e95d10626187 829 #define WTIMER_STATUS_ICV0 (0x1UL << 16) /**< CC0 Input Capture Valid */
AnnaBridge 170:e95d10626187 830 #define _WTIMER_STATUS_ICV0_SHIFT 16 /**< Shift value for TIMER_ICV0 */
AnnaBridge 170:e95d10626187 831 #define _WTIMER_STATUS_ICV0_MASK 0x10000UL /**< Bit mask for TIMER_ICV0 */
AnnaBridge 170:e95d10626187 832 #define _WTIMER_STATUS_ICV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */
AnnaBridge 170:e95d10626187 833 #define WTIMER_STATUS_ICV0_DEFAULT (_WTIMER_STATUS_ICV0_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_STATUS */
AnnaBridge 170:e95d10626187 834 #define WTIMER_STATUS_ICV1 (0x1UL << 17) /**< CC1 Input Capture Valid */
AnnaBridge 170:e95d10626187 835 #define _WTIMER_STATUS_ICV1_SHIFT 17 /**< Shift value for TIMER_ICV1 */
AnnaBridge 170:e95d10626187 836 #define _WTIMER_STATUS_ICV1_MASK 0x20000UL /**< Bit mask for TIMER_ICV1 */
AnnaBridge 170:e95d10626187 837 #define _WTIMER_STATUS_ICV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */
AnnaBridge 170:e95d10626187 838 #define WTIMER_STATUS_ICV1_DEFAULT (_WTIMER_STATUS_ICV1_DEFAULT << 17) /**< Shifted mode DEFAULT for WTIMER_STATUS */
AnnaBridge 170:e95d10626187 839 #define WTIMER_STATUS_ICV2 (0x1UL << 18) /**< CC2 Input Capture Valid */
AnnaBridge 170:e95d10626187 840 #define _WTIMER_STATUS_ICV2_SHIFT 18 /**< Shift value for TIMER_ICV2 */
AnnaBridge 170:e95d10626187 841 #define _WTIMER_STATUS_ICV2_MASK 0x40000UL /**< Bit mask for TIMER_ICV2 */
AnnaBridge 170:e95d10626187 842 #define _WTIMER_STATUS_ICV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */
AnnaBridge 170:e95d10626187 843 #define WTIMER_STATUS_ICV2_DEFAULT (_WTIMER_STATUS_ICV2_DEFAULT << 18) /**< Shifted mode DEFAULT for WTIMER_STATUS */
AnnaBridge 170:e95d10626187 844 #define WTIMER_STATUS_ICV3 (0x1UL << 19) /**< CC3 Input Capture Valid */
AnnaBridge 170:e95d10626187 845 #define _WTIMER_STATUS_ICV3_SHIFT 19 /**< Shift value for TIMER_ICV3 */
AnnaBridge 170:e95d10626187 846 #define _WTIMER_STATUS_ICV3_MASK 0x80000UL /**< Bit mask for TIMER_ICV3 */
AnnaBridge 170:e95d10626187 847 #define _WTIMER_STATUS_ICV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */
AnnaBridge 170:e95d10626187 848 #define WTIMER_STATUS_ICV3_DEFAULT (_WTIMER_STATUS_ICV3_DEFAULT << 19) /**< Shifted mode DEFAULT for WTIMER_STATUS */
AnnaBridge 170:e95d10626187 849 #define WTIMER_STATUS_CCPOL0 (0x1UL << 24) /**< CC0 Polarity */
AnnaBridge 170:e95d10626187 850 #define _WTIMER_STATUS_CCPOL0_SHIFT 24 /**< Shift value for TIMER_CCPOL0 */
AnnaBridge 170:e95d10626187 851 #define _WTIMER_STATUS_CCPOL0_MASK 0x1000000UL /**< Bit mask for TIMER_CCPOL0 */
AnnaBridge 170:e95d10626187 852 #define _WTIMER_STATUS_CCPOL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */
AnnaBridge 170:e95d10626187 853 #define _WTIMER_STATUS_CCPOL0_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */
AnnaBridge 170:e95d10626187 854 #define _WTIMER_STATUS_CCPOL0_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */
AnnaBridge 170:e95d10626187 855 #define WTIMER_STATUS_CCPOL0_DEFAULT (_WTIMER_STATUS_CCPOL0_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_STATUS */
AnnaBridge 170:e95d10626187 856 #define WTIMER_STATUS_CCPOL0_LOWRISE (_WTIMER_STATUS_CCPOL0_LOWRISE << 24) /**< Shifted mode LOWRISE for WTIMER_STATUS */
AnnaBridge 170:e95d10626187 857 #define WTIMER_STATUS_CCPOL0_HIGHFALL (_WTIMER_STATUS_CCPOL0_HIGHFALL << 24) /**< Shifted mode HIGHFALL for WTIMER_STATUS */
AnnaBridge 170:e95d10626187 858 #define WTIMER_STATUS_CCPOL1 (0x1UL << 25) /**< CC1 Polarity */
AnnaBridge 170:e95d10626187 859 #define _WTIMER_STATUS_CCPOL1_SHIFT 25 /**< Shift value for TIMER_CCPOL1 */
AnnaBridge 170:e95d10626187 860 #define _WTIMER_STATUS_CCPOL1_MASK 0x2000000UL /**< Bit mask for TIMER_CCPOL1 */
AnnaBridge 170:e95d10626187 861 #define _WTIMER_STATUS_CCPOL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */
AnnaBridge 170:e95d10626187 862 #define _WTIMER_STATUS_CCPOL1_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */
AnnaBridge 170:e95d10626187 863 #define _WTIMER_STATUS_CCPOL1_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */
AnnaBridge 170:e95d10626187 864 #define WTIMER_STATUS_CCPOL1_DEFAULT (_WTIMER_STATUS_CCPOL1_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_STATUS */
AnnaBridge 170:e95d10626187 865 #define WTIMER_STATUS_CCPOL1_LOWRISE (_WTIMER_STATUS_CCPOL1_LOWRISE << 25) /**< Shifted mode LOWRISE for WTIMER_STATUS */
AnnaBridge 170:e95d10626187 866 #define WTIMER_STATUS_CCPOL1_HIGHFALL (_WTIMER_STATUS_CCPOL1_HIGHFALL << 25) /**< Shifted mode HIGHFALL for WTIMER_STATUS */
AnnaBridge 170:e95d10626187 867 #define WTIMER_STATUS_CCPOL2 (0x1UL << 26) /**< CC2 Polarity */
AnnaBridge 170:e95d10626187 868 #define _WTIMER_STATUS_CCPOL2_SHIFT 26 /**< Shift value for TIMER_CCPOL2 */
AnnaBridge 170:e95d10626187 869 #define _WTIMER_STATUS_CCPOL2_MASK 0x4000000UL /**< Bit mask for TIMER_CCPOL2 */
AnnaBridge 170:e95d10626187 870 #define _WTIMER_STATUS_CCPOL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */
AnnaBridge 170:e95d10626187 871 #define _WTIMER_STATUS_CCPOL2_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */
AnnaBridge 170:e95d10626187 872 #define _WTIMER_STATUS_CCPOL2_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */
AnnaBridge 170:e95d10626187 873 #define WTIMER_STATUS_CCPOL2_DEFAULT (_WTIMER_STATUS_CCPOL2_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_STATUS */
AnnaBridge 170:e95d10626187 874 #define WTIMER_STATUS_CCPOL2_LOWRISE (_WTIMER_STATUS_CCPOL2_LOWRISE << 26) /**< Shifted mode LOWRISE for WTIMER_STATUS */
AnnaBridge 170:e95d10626187 875 #define WTIMER_STATUS_CCPOL2_HIGHFALL (_WTIMER_STATUS_CCPOL2_HIGHFALL << 26) /**< Shifted mode HIGHFALL for WTIMER_STATUS */
AnnaBridge 170:e95d10626187 876 #define WTIMER_STATUS_CCPOL3 (0x1UL << 27) /**< CC3 Polarity */
AnnaBridge 170:e95d10626187 877 #define _WTIMER_STATUS_CCPOL3_SHIFT 27 /**< Shift value for TIMER_CCPOL3 */
AnnaBridge 170:e95d10626187 878 #define _WTIMER_STATUS_CCPOL3_MASK 0x8000000UL /**< Bit mask for TIMER_CCPOL3 */
AnnaBridge 170:e95d10626187 879 #define _WTIMER_STATUS_CCPOL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */
AnnaBridge 170:e95d10626187 880 #define _WTIMER_STATUS_CCPOL3_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */
AnnaBridge 170:e95d10626187 881 #define _WTIMER_STATUS_CCPOL3_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */
AnnaBridge 170:e95d10626187 882 #define WTIMER_STATUS_CCPOL3_DEFAULT (_WTIMER_STATUS_CCPOL3_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_STATUS */
AnnaBridge 170:e95d10626187 883 #define WTIMER_STATUS_CCPOL3_LOWRISE (_WTIMER_STATUS_CCPOL3_LOWRISE << 27) /**< Shifted mode LOWRISE for WTIMER_STATUS */
AnnaBridge 170:e95d10626187 884 #define WTIMER_STATUS_CCPOL3_HIGHFALL (_WTIMER_STATUS_CCPOL3_HIGHFALL << 27) /**< Shifted mode HIGHFALL for WTIMER_STATUS */
AnnaBridge 170:e95d10626187 885
AnnaBridge 170:e95d10626187 886 /* Bit fields for WTIMER IF */
AnnaBridge 170:e95d10626187 887 #define _WTIMER_IF_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IF */
AnnaBridge 170:e95d10626187 888 #define _WTIMER_IF_MASK 0x00000FF7UL /**< Mask for WTIMER_IF */
AnnaBridge 170:e95d10626187 889 #define WTIMER_IF_OF (0x1UL << 0) /**< Overflow Interrupt Flag */
AnnaBridge 170:e95d10626187 890 #define _WTIMER_IF_OF_SHIFT 0 /**< Shift value for TIMER_OF */
AnnaBridge 170:e95d10626187 891 #define _WTIMER_IF_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */
AnnaBridge 170:e95d10626187 892 #define _WTIMER_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */
AnnaBridge 170:e95d10626187 893 #define WTIMER_IF_OF_DEFAULT (_WTIMER_IF_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IF */
AnnaBridge 170:e95d10626187 894 #define WTIMER_IF_UF (0x1UL << 1) /**< Underflow Interrupt Flag */
AnnaBridge 170:e95d10626187 895 #define _WTIMER_IF_UF_SHIFT 1 /**< Shift value for TIMER_UF */
AnnaBridge 170:e95d10626187 896 #define _WTIMER_IF_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */
AnnaBridge 170:e95d10626187 897 #define _WTIMER_IF_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */
AnnaBridge 170:e95d10626187 898 #define WTIMER_IF_UF_DEFAULT (_WTIMER_IF_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IF */
AnnaBridge 170:e95d10626187 899 #define WTIMER_IF_DIRCHG (0x1UL << 2) /**< Direction Change Detect Interrupt Flag */
AnnaBridge 170:e95d10626187 900 #define _WTIMER_IF_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */
AnnaBridge 170:e95d10626187 901 #define _WTIMER_IF_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */
AnnaBridge 170:e95d10626187 902 #define _WTIMER_IF_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */
AnnaBridge 170:e95d10626187 903 #define WTIMER_IF_DIRCHG_DEFAULT (_WTIMER_IF_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IF */
AnnaBridge 170:e95d10626187 904 #define WTIMER_IF_CC0 (0x1UL << 4) /**< CC Channel 0 Interrupt Flag */
AnnaBridge 170:e95d10626187 905 #define _WTIMER_IF_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */
AnnaBridge 170:e95d10626187 906 #define _WTIMER_IF_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */
AnnaBridge 170:e95d10626187 907 #define _WTIMER_IF_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */
AnnaBridge 170:e95d10626187 908 #define WTIMER_IF_CC0_DEFAULT (_WTIMER_IF_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IF */
AnnaBridge 170:e95d10626187 909 #define WTIMER_IF_CC1 (0x1UL << 5) /**< CC Channel 1 Interrupt Flag */
AnnaBridge 170:e95d10626187 910 #define _WTIMER_IF_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */
AnnaBridge 170:e95d10626187 911 #define _WTIMER_IF_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */
AnnaBridge 170:e95d10626187 912 #define _WTIMER_IF_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */
AnnaBridge 170:e95d10626187 913 #define WTIMER_IF_CC1_DEFAULT (_WTIMER_IF_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IF */
AnnaBridge 170:e95d10626187 914 #define WTIMER_IF_CC2 (0x1UL << 6) /**< CC Channel 2 Interrupt Flag */
AnnaBridge 170:e95d10626187 915 #define _WTIMER_IF_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */
AnnaBridge 170:e95d10626187 916 #define _WTIMER_IF_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */
AnnaBridge 170:e95d10626187 917 #define _WTIMER_IF_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */
AnnaBridge 170:e95d10626187 918 #define WTIMER_IF_CC2_DEFAULT (_WTIMER_IF_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IF */
AnnaBridge 170:e95d10626187 919 #define WTIMER_IF_CC3 (0x1UL << 7) /**< CC Channel 3 Interrupt Flag */
AnnaBridge 170:e95d10626187 920 #define _WTIMER_IF_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */
AnnaBridge 170:e95d10626187 921 #define _WTIMER_IF_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */
AnnaBridge 170:e95d10626187 922 #define _WTIMER_IF_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */
AnnaBridge 170:e95d10626187 923 #define WTIMER_IF_CC3_DEFAULT (_WTIMER_IF_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IF */
AnnaBridge 170:e95d10626187 924 #define WTIMER_IF_ICBOF0 (0x1UL << 8) /**< CC Channel 0 Input Capture Buffer Overflow Interrupt Flag */
AnnaBridge 170:e95d10626187 925 #define _WTIMER_IF_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */
AnnaBridge 170:e95d10626187 926 #define _WTIMER_IF_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */
AnnaBridge 170:e95d10626187 927 #define _WTIMER_IF_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */
AnnaBridge 170:e95d10626187 928 #define WTIMER_IF_ICBOF0_DEFAULT (_WTIMER_IF_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IF */
AnnaBridge 170:e95d10626187 929 #define WTIMER_IF_ICBOF1 (0x1UL << 9) /**< CC Channel 1 Input Capture Buffer Overflow Interrupt Flag */
AnnaBridge 170:e95d10626187 930 #define _WTIMER_IF_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */
AnnaBridge 170:e95d10626187 931 #define _WTIMER_IF_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */
AnnaBridge 170:e95d10626187 932 #define _WTIMER_IF_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */
AnnaBridge 170:e95d10626187 933 #define WTIMER_IF_ICBOF1_DEFAULT (_WTIMER_IF_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IF */
AnnaBridge 170:e95d10626187 934 #define WTIMER_IF_ICBOF2 (0x1UL << 10) /**< CC Channel 2 Input Capture Buffer Overflow Interrupt Flag */
AnnaBridge 170:e95d10626187 935 #define _WTIMER_IF_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */
AnnaBridge 170:e95d10626187 936 #define _WTIMER_IF_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */
AnnaBridge 170:e95d10626187 937 #define _WTIMER_IF_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */
AnnaBridge 170:e95d10626187 938 #define WTIMER_IF_ICBOF2_DEFAULT (_WTIMER_IF_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IF */
AnnaBridge 170:e95d10626187 939 #define WTIMER_IF_ICBOF3 (0x1UL << 11) /**< CC Channel 3 Input Capture Buffer Overflow Interrupt Flag */
AnnaBridge 170:e95d10626187 940 #define _WTIMER_IF_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */
AnnaBridge 170:e95d10626187 941 #define _WTIMER_IF_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */
AnnaBridge 170:e95d10626187 942 #define _WTIMER_IF_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */
AnnaBridge 170:e95d10626187 943 #define WTIMER_IF_ICBOF3_DEFAULT (_WTIMER_IF_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IF */
AnnaBridge 170:e95d10626187 944
AnnaBridge 170:e95d10626187 945 /* Bit fields for WTIMER IFS */
AnnaBridge 170:e95d10626187 946 #define _WTIMER_IFS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFS */
AnnaBridge 170:e95d10626187 947 #define _WTIMER_IFS_MASK 0x00000FF7UL /**< Mask for WTIMER_IFS */
AnnaBridge 170:e95d10626187 948 #define WTIMER_IFS_OF (0x1UL << 0) /**< Set OF Interrupt Flag */
AnnaBridge 170:e95d10626187 949 #define _WTIMER_IFS_OF_SHIFT 0 /**< Shift value for TIMER_OF */
AnnaBridge 170:e95d10626187 950 #define _WTIMER_IFS_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */
AnnaBridge 170:e95d10626187 951 #define _WTIMER_IFS_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */
AnnaBridge 170:e95d10626187 952 #define WTIMER_IFS_OF_DEFAULT (_WTIMER_IFS_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFS */
AnnaBridge 170:e95d10626187 953 #define WTIMER_IFS_UF (0x1UL << 1) /**< Set UF Interrupt Flag */
AnnaBridge 170:e95d10626187 954 #define _WTIMER_IFS_UF_SHIFT 1 /**< Shift value for TIMER_UF */
AnnaBridge 170:e95d10626187 955 #define _WTIMER_IFS_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */
AnnaBridge 170:e95d10626187 956 #define _WTIMER_IFS_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */
AnnaBridge 170:e95d10626187 957 #define WTIMER_IFS_UF_DEFAULT (_WTIMER_IFS_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFS */
AnnaBridge 170:e95d10626187 958 #define WTIMER_IFS_DIRCHG (0x1UL << 2) /**< Set DIRCHG Interrupt Flag */
AnnaBridge 170:e95d10626187 959 #define _WTIMER_IFS_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */
AnnaBridge 170:e95d10626187 960 #define _WTIMER_IFS_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */
AnnaBridge 170:e95d10626187 961 #define _WTIMER_IFS_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */
AnnaBridge 170:e95d10626187 962 #define WTIMER_IFS_DIRCHG_DEFAULT (_WTIMER_IFS_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFS */
AnnaBridge 170:e95d10626187 963 #define WTIMER_IFS_CC0 (0x1UL << 4) /**< Set CC0 Interrupt Flag */
AnnaBridge 170:e95d10626187 964 #define _WTIMER_IFS_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */
AnnaBridge 170:e95d10626187 965 #define _WTIMER_IFS_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */
AnnaBridge 170:e95d10626187 966 #define _WTIMER_IFS_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */
AnnaBridge 170:e95d10626187 967 #define WTIMER_IFS_CC0_DEFAULT (_WTIMER_IFS_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFS */
AnnaBridge 170:e95d10626187 968 #define WTIMER_IFS_CC1 (0x1UL << 5) /**< Set CC1 Interrupt Flag */
AnnaBridge 170:e95d10626187 969 #define _WTIMER_IFS_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */
AnnaBridge 170:e95d10626187 970 #define _WTIMER_IFS_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */
AnnaBridge 170:e95d10626187 971 #define _WTIMER_IFS_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */
AnnaBridge 170:e95d10626187 972 #define WTIMER_IFS_CC1_DEFAULT (_WTIMER_IFS_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFS */
AnnaBridge 170:e95d10626187 973 #define WTIMER_IFS_CC2 (0x1UL << 6) /**< Set CC2 Interrupt Flag */
AnnaBridge 170:e95d10626187 974 #define _WTIMER_IFS_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */
AnnaBridge 170:e95d10626187 975 #define _WTIMER_IFS_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */
AnnaBridge 170:e95d10626187 976 #define _WTIMER_IFS_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */
AnnaBridge 170:e95d10626187 977 #define WTIMER_IFS_CC2_DEFAULT (_WTIMER_IFS_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFS */
AnnaBridge 170:e95d10626187 978 #define WTIMER_IFS_CC3 (0x1UL << 7) /**< Set CC3 Interrupt Flag */
AnnaBridge 170:e95d10626187 979 #define _WTIMER_IFS_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */
AnnaBridge 170:e95d10626187 980 #define _WTIMER_IFS_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */
AnnaBridge 170:e95d10626187 981 #define _WTIMER_IFS_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */
AnnaBridge 170:e95d10626187 982 #define WTIMER_IFS_CC3_DEFAULT (_WTIMER_IFS_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFS */
AnnaBridge 170:e95d10626187 983 #define WTIMER_IFS_ICBOF0 (0x1UL << 8) /**< Set ICBOF0 Interrupt Flag */
AnnaBridge 170:e95d10626187 984 #define _WTIMER_IFS_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */
AnnaBridge 170:e95d10626187 985 #define _WTIMER_IFS_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */
AnnaBridge 170:e95d10626187 986 #define _WTIMER_IFS_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */
AnnaBridge 170:e95d10626187 987 #define WTIMER_IFS_ICBOF0_DEFAULT (_WTIMER_IFS_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFS */
AnnaBridge 170:e95d10626187 988 #define WTIMER_IFS_ICBOF1 (0x1UL << 9) /**< Set ICBOF1 Interrupt Flag */
AnnaBridge 170:e95d10626187 989 #define _WTIMER_IFS_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */
AnnaBridge 170:e95d10626187 990 #define _WTIMER_IFS_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */
AnnaBridge 170:e95d10626187 991 #define _WTIMER_IFS_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */
AnnaBridge 170:e95d10626187 992 #define WTIMER_IFS_ICBOF1_DEFAULT (_WTIMER_IFS_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFS */
AnnaBridge 170:e95d10626187 993 #define WTIMER_IFS_ICBOF2 (0x1UL << 10) /**< Set ICBOF2 Interrupt Flag */
AnnaBridge 170:e95d10626187 994 #define _WTIMER_IFS_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */
AnnaBridge 170:e95d10626187 995 #define _WTIMER_IFS_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */
AnnaBridge 170:e95d10626187 996 #define _WTIMER_IFS_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */
AnnaBridge 170:e95d10626187 997 #define WTIMER_IFS_ICBOF2_DEFAULT (_WTIMER_IFS_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFS */
AnnaBridge 170:e95d10626187 998 #define WTIMER_IFS_ICBOF3 (0x1UL << 11) /**< Set ICBOF3 Interrupt Flag */
AnnaBridge 170:e95d10626187 999 #define _WTIMER_IFS_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */
AnnaBridge 170:e95d10626187 1000 #define _WTIMER_IFS_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */
AnnaBridge 170:e95d10626187 1001 #define _WTIMER_IFS_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */
AnnaBridge 170:e95d10626187 1002 #define WTIMER_IFS_ICBOF3_DEFAULT (_WTIMER_IFS_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFS */
AnnaBridge 170:e95d10626187 1003
AnnaBridge 170:e95d10626187 1004 /* Bit fields for WTIMER IFC */
AnnaBridge 170:e95d10626187 1005 #define _WTIMER_IFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFC */
AnnaBridge 170:e95d10626187 1006 #define _WTIMER_IFC_MASK 0x00000FF7UL /**< Mask for WTIMER_IFC */
AnnaBridge 170:e95d10626187 1007 #define WTIMER_IFC_OF (0x1UL << 0) /**< Clear OF Interrupt Flag */
AnnaBridge 170:e95d10626187 1008 #define _WTIMER_IFC_OF_SHIFT 0 /**< Shift value for TIMER_OF */
AnnaBridge 170:e95d10626187 1009 #define _WTIMER_IFC_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */
AnnaBridge 170:e95d10626187 1010 #define _WTIMER_IFC_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */
AnnaBridge 170:e95d10626187 1011 #define WTIMER_IFC_OF_DEFAULT (_WTIMER_IFC_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFC */
AnnaBridge 170:e95d10626187 1012 #define WTIMER_IFC_UF (0x1UL << 1) /**< Clear UF Interrupt Flag */
AnnaBridge 170:e95d10626187 1013 #define _WTIMER_IFC_UF_SHIFT 1 /**< Shift value for TIMER_UF */
AnnaBridge 170:e95d10626187 1014 #define _WTIMER_IFC_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */
AnnaBridge 170:e95d10626187 1015 #define _WTIMER_IFC_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */
AnnaBridge 170:e95d10626187 1016 #define WTIMER_IFC_UF_DEFAULT (_WTIMER_IFC_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFC */
AnnaBridge 170:e95d10626187 1017 #define WTIMER_IFC_DIRCHG (0x1UL << 2) /**< Clear DIRCHG Interrupt Flag */
AnnaBridge 170:e95d10626187 1018 #define _WTIMER_IFC_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */
AnnaBridge 170:e95d10626187 1019 #define _WTIMER_IFC_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */
AnnaBridge 170:e95d10626187 1020 #define _WTIMER_IFC_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */
AnnaBridge 170:e95d10626187 1021 #define WTIMER_IFC_DIRCHG_DEFAULT (_WTIMER_IFC_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFC */
AnnaBridge 170:e95d10626187 1022 #define WTIMER_IFC_CC0 (0x1UL << 4) /**< Clear CC0 Interrupt Flag */
AnnaBridge 170:e95d10626187 1023 #define _WTIMER_IFC_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */
AnnaBridge 170:e95d10626187 1024 #define _WTIMER_IFC_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */
AnnaBridge 170:e95d10626187 1025 #define _WTIMER_IFC_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */
AnnaBridge 170:e95d10626187 1026 #define WTIMER_IFC_CC0_DEFAULT (_WTIMER_IFC_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFC */
AnnaBridge 170:e95d10626187 1027 #define WTIMER_IFC_CC1 (0x1UL << 5) /**< Clear CC1 Interrupt Flag */
AnnaBridge 170:e95d10626187 1028 #define _WTIMER_IFC_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */
AnnaBridge 170:e95d10626187 1029 #define _WTIMER_IFC_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */
AnnaBridge 170:e95d10626187 1030 #define _WTIMER_IFC_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */
AnnaBridge 170:e95d10626187 1031 #define WTIMER_IFC_CC1_DEFAULT (_WTIMER_IFC_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFC */
AnnaBridge 170:e95d10626187 1032 #define WTIMER_IFC_CC2 (0x1UL << 6) /**< Clear CC2 Interrupt Flag */
AnnaBridge 170:e95d10626187 1033 #define _WTIMER_IFC_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */
AnnaBridge 170:e95d10626187 1034 #define _WTIMER_IFC_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */
AnnaBridge 170:e95d10626187 1035 #define _WTIMER_IFC_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */
AnnaBridge 170:e95d10626187 1036 #define WTIMER_IFC_CC2_DEFAULT (_WTIMER_IFC_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFC */
AnnaBridge 170:e95d10626187 1037 #define WTIMER_IFC_CC3 (0x1UL << 7) /**< Clear CC3 Interrupt Flag */
AnnaBridge 170:e95d10626187 1038 #define _WTIMER_IFC_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */
AnnaBridge 170:e95d10626187 1039 #define _WTIMER_IFC_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */
AnnaBridge 170:e95d10626187 1040 #define _WTIMER_IFC_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */
AnnaBridge 170:e95d10626187 1041 #define WTIMER_IFC_CC3_DEFAULT (_WTIMER_IFC_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFC */
AnnaBridge 170:e95d10626187 1042 #define WTIMER_IFC_ICBOF0 (0x1UL << 8) /**< Clear ICBOF0 Interrupt Flag */
AnnaBridge 170:e95d10626187 1043 #define _WTIMER_IFC_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */
AnnaBridge 170:e95d10626187 1044 #define _WTIMER_IFC_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */
AnnaBridge 170:e95d10626187 1045 #define _WTIMER_IFC_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */
AnnaBridge 170:e95d10626187 1046 #define WTIMER_IFC_ICBOF0_DEFAULT (_WTIMER_IFC_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFC */
AnnaBridge 170:e95d10626187 1047 #define WTIMER_IFC_ICBOF1 (0x1UL << 9) /**< Clear ICBOF1 Interrupt Flag */
AnnaBridge 170:e95d10626187 1048 #define _WTIMER_IFC_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */
AnnaBridge 170:e95d10626187 1049 #define _WTIMER_IFC_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */
AnnaBridge 170:e95d10626187 1050 #define _WTIMER_IFC_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */
AnnaBridge 170:e95d10626187 1051 #define WTIMER_IFC_ICBOF1_DEFAULT (_WTIMER_IFC_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFC */
AnnaBridge 170:e95d10626187 1052 #define WTIMER_IFC_ICBOF2 (0x1UL << 10) /**< Clear ICBOF2 Interrupt Flag */
AnnaBridge 170:e95d10626187 1053 #define _WTIMER_IFC_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */
AnnaBridge 170:e95d10626187 1054 #define _WTIMER_IFC_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */
AnnaBridge 170:e95d10626187 1055 #define _WTIMER_IFC_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */
AnnaBridge 170:e95d10626187 1056 #define WTIMER_IFC_ICBOF2_DEFAULT (_WTIMER_IFC_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFC */
AnnaBridge 170:e95d10626187 1057 #define WTIMER_IFC_ICBOF3 (0x1UL << 11) /**< Clear ICBOF3 Interrupt Flag */
AnnaBridge 170:e95d10626187 1058 #define _WTIMER_IFC_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */
AnnaBridge 170:e95d10626187 1059 #define _WTIMER_IFC_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */
AnnaBridge 170:e95d10626187 1060 #define _WTIMER_IFC_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */
AnnaBridge 170:e95d10626187 1061 #define WTIMER_IFC_ICBOF3_DEFAULT (_WTIMER_IFC_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFC */
AnnaBridge 170:e95d10626187 1062
AnnaBridge 170:e95d10626187 1063 /* Bit fields for WTIMER IEN */
AnnaBridge 170:e95d10626187 1064 #define _WTIMER_IEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IEN */
AnnaBridge 170:e95d10626187 1065 #define _WTIMER_IEN_MASK 0x00000FF7UL /**< Mask for WTIMER_IEN */
AnnaBridge 170:e95d10626187 1066 #define WTIMER_IEN_OF (0x1UL << 0) /**< OF Interrupt Enable */
AnnaBridge 170:e95d10626187 1067 #define _WTIMER_IEN_OF_SHIFT 0 /**< Shift value for TIMER_OF */
AnnaBridge 170:e95d10626187 1068 #define _WTIMER_IEN_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */
AnnaBridge 170:e95d10626187 1069 #define _WTIMER_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */
AnnaBridge 170:e95d10626187 1070 #define WTIMER_IEN_OF_DEFAULT (_WTIMER_IEN_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IEN */
AnnaBridge 170:e95d10626187 1071 #define WTIMER_IEN_UF (0x1UL << 1) /**< UF Interrupt Enable */
AnnaBridge 170:e95d10626187 1072 #define _WTIMER_IEN_UF_SHIFT 1 /**< Shift value for TIMER_UF */
AnnaBridge 170:e95d10626187 1073 #define _WTIMER_IEN_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */
AnnaBridge 170:e95d10626187 1074 #define _WTIMER_IEN_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */
AnnaBridge 170:e95d10626187 1075 #define WTIMER_IEN_UF_DEFAULT (_WTIMER_IEN_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IEN */
AnnaBridge 170:e95d10626187 1076 #define WTIMER_IEN_DIRCHG (0x1UL << 2) /**< DIRCHG Interrupt Enable */
AnnaBridge 170:e95d10626187 1077 #define _WTIMER_IEN_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */
AnnaBridge 170:e95d10626187 1078 #define _WTIMER_IEN_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */
AnnaBridge 170:e95d10626187 1079 #define _WTIMER_IEN_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */
AnnaBridge 170:e95d10626187 1080 #define WTIMER_IEN_DIRCHG_DEFAULT (_WTIMER_IEN_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IEN */
AnnaBridge 170:e95d10626187 1081 #define WTIMER_IEN_CC0 (0x1UL << 4) /**< CC0 Interrupt Enable */
AnnaBridge 170:e95d10626187 1082 #define _WTIMER_IEN_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */
AnnaBridge 170:e95d10626187 1083 #define _WTIMER_IEN_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */
AnnaBridge 170:e95d10626187 1084 #define _WTIMER_IEN_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */
AnnaBridge 170:e95d10626187 1085 #define WTIMER_IEN_CC0_DEFAULT (_WTIMER_IEN_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IEN */
AnnaBridge 170:e95d10626187 1086 #define WTIMER_IEN_CC1 (0x1UL << 5) /**< CC1 Interrupt Enable */
AnnaBridge 170:e95d10626187 1087 #define _WTIMER_IEN_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */
AnnaBridge 170:e95d10626187 1088 #define _WTIMER_IEN_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */
AnnaBridge 170:e95d10626187 1089 #define _WTIMER_IEN_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */
AnnaBridge 170:e95d10626187 1090 #define WTIMER_IEN_CC1_DEFAULT (_WTIMER_IEN_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IEN */
AnnaBridge 170:e95d10626187 1091 #define WTIMER_IEN_CC2 (0x1UL << 6) /**< CC2 Interrupt Enable */
AnnaBridge 170:e95d10626187 1092 #define _WTIMER_IEN_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */
AnnaBridge 170:e95d10626187 1093 #define _WTIMER_IEN_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */
AnnaBridge 170:e95d10626187 1094 #define _WTIMER_IEN_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */
AnnaBridge 170:e95d10626187 1095 #define WTIMER_IEN_CC2_DEFAULT (_WTIMER_IEN_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IEN */
AnnaBridge 170:e95d10626187 1096 #define WTIMER_IEN_CC3 (0x1UL << 7) /**< CC3 Interrupt Enable */
AnnaBridge 170:e95d10626187 1097 #define _WTIMER_IEN_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */
AnnaBridge 170:e95d10626187 1098 #define _WTIMER_IEN_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */
AnnaBridge 170:e95d10626187 1099 #define _WTIMER_IEN_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */
AnnaBridge 170:e95d10626187 1100 #define WTIMER_IEN_CC3_DEFAULT (_WTIMER_IEN_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IEN */
AnnaBridge 170:e95d10626187 1101 #define WTIMER_IEN_ICBOF0 (0x1UL << 8) /**< ICBOF0 Interrupt Enable */
AnnaBridge 170:e95d10626187 1102 #define _WTIMER_IEN_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */
AnnaBridge 170:e95d10626187 1103 #define _WTIMER_IEN_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */
AnnaBridge 170:e95d10626187 1104 #define _WTIMER_IEN_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */
AnnaBridge 170:e95d10626187 1105 #define WTIMER_IEN_ICBOF0_DEFAULT (_WTIMER_IEN_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IEN */
AnnaBridge 170:e95d10626187 1106 #define WTIMER_IEN_ICBOF1 (0x1UL << 9) /**< ICBOF1 Interrupt Enable */
AnnaBridge 170:e95d10626187 1107 #define _WTIMER_IEN_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */
AnnaBridge 170:e95d10626187 1108 #define _WTIMER_IEN_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */
AnnaBridge 170:e95d10626187 1109 #define _WTIMER_IEN_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */
AnnaBridge 170:e95d10626187 1110 #define WTIMER_IEN_ICBOF1_DEFAULT (_WTIMER_IEN_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IEN */
AnnaBridge 170:e95d10626187 1111 #define WTIMER_IEN_ICBOF2 (0x1UL << 10) /**< ICBOF2 Interrupt Enable */
AnnaBridge 170:e95d10626187 1112 #define _WTIMER_IEN_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */
AnnaBridge 170:e95d10626187 1113 #define _WTIMER_IEN_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */
AnnaBridge 170:e95d10626187 1114 #define _WTIMER_IEN_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */
AnnaBridge 170:e95d10626187 1115 #define WTIMER_IEN_ICBOF2_DEFAULT (_WTIMER_IEN_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IEN */
AnnaBridge 170:e95d10626187 1116 #define WTIMER_IEN_ICBOF3 (0x1UL << 11) /**< ICBOF3 Interrupt Enable */
AnnaBridge 170:e95d10626187 1117 #define _WTIMER_IEN_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */
AnnaBridge 170:e95d10626187 1118 #define _WTIMER_IEN_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */
AnnaBridge 170:e95d10626187 1119 #define _WTIMER_IEN_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */
AnnaBridge 170:e95d10626187 1120 #define WTIMER_IEN_ICBOF3_DEFAULT (_WTIMER_IEN_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IEN */
AnnaBridge 170:e95d10626187 1121
AnnaBridge 170:e95d10626187 1122 /* Bit fields for WTIMER TOP */
AnnaBridge 170:e95d10626187 1123 #define _WTIMER_TOP_RESETVALUE 0x0000FFFFUL /**< Default value for WTIMER_TOP */
AnnaBridge 170:e95d10626187 1124 #define _WTIMER_TOP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOP */
AnnaBridge 170:e95d10626187 1125 #define _WTIMER_TOP_TOP_SHIFT 0 /**< Shift value for TIMER_TOP */
AnnaBridge 170:e95d10626187 1126 #define _WTIMER_TOP_TOP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOP */
AnnaBridge 170:e95d10626187 1127 #define _WTIMER_TOP_TOP_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for WTIMER_TOP */
AnnaBridge 170:e95d10626187 1128 #define WTIMER_TOP_TOP_DEFAULT (_WTIMER_TOP_TOP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOP */
AnnaBridge 170:e95d10626187 1129
AnnaBridge 170:e95d10626187 1130 /* Bit fields for WTIMER TOPB */
AnnaBridge 170:e95d10626187 1131 #define _WTIMER_TOPB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_TOPB */
AnnaBridge 170:e95d10626187 1132 #define _WTIMER_TOPB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOPB */
AnnaBridge 170:e95d10626187 1133 #define _WTIMER_TOPB_TOPB_SHIFT 0 /**< Shift value for TIMER_TOPB */
AnnaBridge 170:e95d10626187 1134 #define _WTIMER_TOPB_TOPB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOPB */
AnnaBridge 170:e95d10626187 1135 #define _WTIMER_TOPB_TOPB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_TOPB */
AnnaBridge 170:e95d10626187 1136 #define WTIMER_TOPB_TOPB_DEFAULT (_WTIMER_TOPB_TOPB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOPB */
AnnaBridge 170:e95d10626187 1137
AnnaBridge 170:e95d10626187 1138 /* Bit fields for WTIMER CNT */
AnnaBridge 170:e95d10626187 1139 #define _WTIMER_CNT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CNT */
AnnaBridge 170:e95d10626187 1140 #define _WTIMER_CNT_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CNT */
AnnaBridge 170:e95d10626187 1141 #define _WTIMER_CNT_CNT_SHIFT 0 /**< Shift value for TIMER_CNT */
AnnaBridge 170:e95d10626187 1142 #define _WTIMER_CNT_CNT_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CNT */
AnnaBridge 170:e95d10626187 1143 #define _WTIMER_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CNT */
AnnaBridge 170:e95d10626187 1144 #define WTIMER_CNT_CNT_DEFAULT (_WTIMER_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CNT */
AnnaBridge 170:e95d10626187 1145
AnnaBridge 170:e95d10626187 1146 /* Bit fields for WTIMER LOCK */
AnnaBridge 170:e95d10626187 1147 #define _WTIMER_LOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_LOCK */
AnnaBridge 170:e95d10626187 1148 #define _WTIMER_LOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_LOCK */
AnnaBridge 170:e95d10626187 1149 #define _WTIMER_LOCK_TIMERLOCKKEY_SHIFT 0 /**< Shift value for TIMER_TIMERLOCKKEY */
AnnaBridge 170:e95d10626187 1150 #define _WTIMER_LOCK_TIMERLOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_TIMERLOCKKEY */
AnnaBridge 170:e95d10626187 1151 #define _WTIMER_LOCK_TIMERLOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_LOCK */
AnnaBridge 170:e95d10626187 1152 #define _WTIMER_LOCK_TIMERLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_LOCK */
AnnaBridge 170:e95d10626187 1153 #define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_LOCK */
AnnaBridge 170:e95d10626187 1154 #define _WTIMER_LOCK_TIMERLOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_LOCK */
AnnaBridge 170:e95d10626187 1155 #define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_LOCK */
AnnaBridge 170:e95d10626187 1156 #define WTIMER_LOCK_TIMERLOCKKEY_DEFAULT (_WTIMER_LOCK_TIMERLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_LOCK */
AnnaBridge 170:e95d10626187 1157 #define WTIMER_LOCK_TIMERLOCKKEY_LOCK (_WTIMER_LOCK_TIMERLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_LOCK */
AnnaBridge 170:e95d10626187 1158 #define WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_LOCK */
AnnaBridge 170:e95d10626187 1159 #define WTIMER_LOCK_TIMERLOCKKEY_LOCKED (_WTIMER_LOCK_TIMERLOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_LOCK */
AnnaBridge 170:e95d10626187 1160 #define WTIMER_LOCK_TIMERLOCKKEY_UNLOCK (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_LOCK */
AnnaBridge 170:e95d10626187 1161
AnnaBridge 170:e95d10626187 1162 /* Bit fields for WTIMER ROUTEPEN */
AnnaBridge 170:e95d10626187 1163 #define _WTIMER_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTEPEN */
AnnaBridge 170:e95d10626187 1164 #define _WTIMER_ROUTEPEN_MASK 0x0000070FUL /**< Mask for WTIMER_ROUTEPEN */
AnnaBridge 170:e95d10626187 1165 #define WTIMER_ROUTEPEN_CC0PEN (0x1UL << 0) /**< CC Channel 0 Pin Enable */
AnnaBridge 170:e95d10626187 1166 #define _WTIMER_ROUTEPEN_CC0PEN_SHIFT 0 /**< Shift value for TIMER_CC0PEN */
AnnaBridge 170:e95d10626187 1167 #define _WTIMER_ROUTEPEN_CC0PEN_MASK 0x1UL /**< Bit mask for TIMER_CC0PEN */
AnnaBridge 170:e95d10626187 1168 #define _WTIMER_ROUTEPEN_CC0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */
AnnaBridge 170:e95d10626187 1169 #define WTIMER_ROUTEPEN_CC0PEN_DEFAULT (_WTIMER_ROUTEPEN_CC0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */
AnnaBridge 170:e95d10626187 1170 #define WTIMER_ROUTEPEN_CC1PEN (0x1UL << 1) /**< CC Channel 1 Pin Enable */
AnnaBridge 170:e95d10626187 1171 #define _WTIMER_ROUTEPEN_CC1PEN_SHIFT 1 /**< Shift value for TIMER_CC1PEN */
AnnaBridge 170:e95d10626187 1172 #define _WTIMER_ROUTEPEN_CC1PEN_MASK 0x2UL /**< Bit mask for TIMER_CC1PEN */
AnnaBridge 170:e95d10626187 1173 #define _WTIMER_ROUTEPEN_CC1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */
AnnaBridge 170:e95d10626187 1174 #define WTIMER_ROUTEPEN_CC1PEN_DEFAULT (_WTIMER_ROUTEPEN_CC1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */
AnnaBridge 170:e95d10626187 1175 #define WTIMER_ROUTEPEN_CC2PEN (0x1UL << 2) /**< CC Channel 2 Pin Enable */
AnnaBridge 170:e95d10626187 1176 #define _WTIMER_ROUTEPEN_CC2PEN_SHIFT 2 /**< Shift value for TIMER_CC2PEN */
AnnaBridge 170:e95d10626187 1177 #define _WTIMER_ROUTEPEN_CC2PEN_MASK 0x4UL /**< Bit mask for TIMER_CC2PEN */
AnnaBridge 170:e95d10626187 1178 #define _WTIMER_ROUTEPEN_CC2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */
AnnaBridge 170:e95d10626187 1179 #define WTIMER_ROUTEPEN_CC2PEN_DEFAULT (_WTIMER_ROUTEPEN_CC2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */
AnnaBridge 170:e95d10626187 1180 #define WTIMER_ROUTEPEN_CC3PEN (0x1UL << 3) /**< CC Channel 3 Pin Enable */
AnnaBridge 170:e95d10626187 1181 #define _WTIMER_ROUTEPEN_CC3PEN_SHIFT 3 /**< Shift value for TIMER_CC3PEN */
AnnaBridge 170:e95d10626187 1182 #define _WTIMER_ROUTEPEN_CC3PEN_MASK 0x8UL /**< Bit mask for TIMER_CC3PEN */
AnnaBridge 170:e95d10626187 1183 #define _WTIMER_ROUTEPEN_CC3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */
AnnaBridge 170:e95d10626187 1184 #define WTIMER_ROUTEPEN_CC3PEN_DEFAULT (_WTIMER_ROUTEPEN_CC3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */
AnnaBridge 170:e95d10626187 1185 #define WTIMER_ROUTEPEN_CDTI0PEN (0x1UL << 8) /**< CC Channel 0 Complementary Dead-Time Insertion Pin Enable */
AnnaBridge 170:e95d10626187 1186 #define _WTIMER_ROUTEPEN_CDTI0PEN_SHIFT 8 /**< Shift value for TIMER_CDTI0PEN */
AnnaBridge 170:e95d10626187 1187 #define _WTIMER_ROUTEPEN_CDTI0PEN_MASK 0x100UL /**< Bit mask for TIMER_CDTI0PEN */
AnnaBridge 170:e95d10626187 1188 #define _WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */
AnnaBridge 170:e95d10626187 1189 #define WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */
AnnaBridge 170:e95d10626187 1190 #define WTIMER_ROUTEPEN_CDTI1PEN (0x1UL << 9) /**< CC Channel 1 Complementary Dead-Time Insertion Pin Enable */
AnnaBridge 170:e95d10626187 1191 #define _WTIMER_ROUTEPEN_CDTI1PEN_SHIFT 9 /**< Shift value for TIMER_CDTI1PEN */
AnnaBridge 170:e95d10626187 1192 #define _WTIMER_ROUTEPEN_CDTI1PEN_MASK 0x200UL /**< Bit mask for TIMER_CDTI1PEN */
AnnaBridge 170:e95d10626187 1193 #define _WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */
AnnaBridge 170:e95d10626187 1194 #define WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */
AnnaBridge 170:e95d10626187 1195 #define WTIMER_ROUTEPEN_CDTI2PEN (0x1UL << 10) /**< CC Channel 2 Complementary Dead-Time Insertion Pin Enable */
AnnaBridge 170:e95d10626187 1196 #define _WTIMER_ROUTEPEN_CDTI2PEN_SHIFT 10 /**< Shift value for TIMER_CDTI2PEN */
AnnaBridge 170:e95d10626187 1197 #define _WTIMER_ROUTEPEN_CDTI2PEN_MASK 0x400UL /**< Bit mask for TIMER_CDTI2PEN */
AnnaBridge 170:e95d10626187 1198 #define _WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */
AnnaBridge 170:e95d10626187 1199 #define WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */
AnnaBridge 170:e95d10626187 1200
AnnaBridge 170:e95d10626187 1201 /* Bit fields for WTIMER ROUTELOC0 */
AnnaBridge 170:e95d10626187 1202 #define _WTIMER_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC0 */
AnnaBridge 170:e95d10626187 1203 #define _WTIMER_ROUTELOC0_MASK 0x07070707UL /**< Mask for WTIMER_ROUTELOC0 */
AnnaBridge 170:e95d10626187 1204 #define _WTIMER_ROUTELOC0_CC0LOC_SHIFT 0 /**< Shift value for TIMER_CC0LOC */
AnnaBridge 170:e95d10626187 1205 #define _WTIMER_ROUTELOC0_CC0LOC_MASK 0x7UL /**< Bit mask for TIMER_CC0LOC */
AnnaBridge 170:e95d10626187 1206 #define _WTIMER_ROUTELOC0_CC0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */
AnnaBridge 170:e95d10626187 1207 #define _WTIMER_ROUTELOC0_CC0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */
AnnaBridge 170:e95d10626187 1208 #define _WTIMER_ROUTELOC0_CC0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */
AnnaBridge 170:e95d10626187 1209 #define _WTIMER_ROUTELOC0_CC0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */
AnnaBridge 170:e95d10626187 1210 #define _WTIMER_ROUTELOC0_CC0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */
AnnaBridge 170:e95d10626187 1211 #define _WTIMER_ROUTELOC0_CC0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */
AnnaBridge 170:e95d10626187 1212 #define _WTIMER_ROUTELOC0_CC0LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */
AnnaBridge 170:e95d10626187 1213 #define _WTIMER_ROUTELOC0_CC0LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */
AnnaBridge 170:e95d10626187 1214 #define _WTIMER_ROUTELOC0_CC0LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */
AnnaBridge 170:e95d10626187 1215 #define WTIMER_ROUTELOC0_CC0LOC_LOC0 (_WTIMER_ROUTELOC0_CC0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */
AnnaBridge 170:e95d10626187 1216 #define WTIMER_ROUTELOC0_CC0LOC_DEFAULT (_WTIMER_ROUTELOC0_CC0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */
AnnaBridge 170:e95d10626187 1217 #define WTIMER_ROUTELOC0_CC0LOC_LOC1 (_WTIMER_ROUTELOC0_CC0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */
AnnaBridge 170:e95d10626187 1218 #define WTIMER_ROUTELOC0_CC0LOC_LOC2 (_WTIMER_ROUTELOC0_CC0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */
AnnaBridge 170:e95d10626187 1219 #define WTIMER_ROUTELOC0_CC0LOC_LOC3 (_WTIMER_ROUTELOC0_CC0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */
AnnaBridge 170:e95d10626187 1220 #define WTIMER_ROUTELOC0_CC0LOC_LOC4 (_WTIMER_ROUTELOC0_CC0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */
AnnaBridge 170:e95d10626187 1221 #define WTIMER_ROUTELOC0_CC0LOC_LOC5 (_WTIMER_ROUTELOC0_CC0LOC_LOC5 << 0) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */
AnnaBridge 170:e95d10626187 1222 #define WTIMER_ROUTELOC0_CC0LOC_LOC6 (_WTIMER_ROUTELOC0_CC0LOC_LOC6 << 0) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */
AnnaBridge 170:e95d10626187 1223 #define WTIMER_ROUTELOC0_CC0LOC_LOC7 (_WTIMER_ROUTELOC0_CC0LOC_LOC7 << 0) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */
AnnaBridge 170:e95d10626187 1224 #define _WTIMER_ROUTELOC0_CC1LOC_SHIFT 8 /**< Shift value for TIMER_CC1LOC */
AnnaBridge 170:e95d10626187 1225 #define _WTIMER_ROUTELOC0_CC1LOC_MASK 0x700UL /**< Bit mask for TIMER_CC1LOC */
AnnaBridge 170:e95d10626187 1226 #define _WTIMER_ROUTELOC0_CC1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */
AnnaBridge 170:e95d10626187 1227 #define _WTIMER_ROUTELOC0_CC1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */
AnnaBridge 170:e95d10626187 1228 #define _WTIMER_ROUTELOC0_CC1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */
AnnaBridge 170:e95d10626187 1229 #define _WTIMER_ROUTELOC0_CC1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */
AnnaBridge 170:e95d10626187 1230 #define _WTIMER_ROUTELOC0_CC1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */
AnnaBridge 170:e95d10626187 1231 #define _WTIMER_ROUTELOC0_CC1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */
AnnaBridge 170:e95d10626187 1232 #define _WTIMER_ROUTELOC0_CC1LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */
AnnaBridge 170:e95d10626187 1233 #define _WTIMER_ROUTELOC0_CC1LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */
AnnaBridge 170:e95d10626187 1234 #define _WTIMER_ROUTELOC0_CC1LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */
AnnaBridge 170:e95d10626187 1235 #define WTIMER_ROUTELOC0_CC1LOC_LOC0 (_WTIMER_ROUTELOC0_CC1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */
AnnaBridge 170:e95d10626187 1236 #define WTIMER_ROUTELOC0_CC1LOC_DEFAULT (_WTIMER_ROUTELOC0_CC1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */
AnnaBridge 170:e95d10626187 1237 #define WTIMER_ROUTELOC0_CC1LOC_LOC1 (_WTIMER_ROUTELOC0_CC1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */
AnnaBridge 170:e95d10626187 1238 #define WTIMER_ROUTELOC0_CC1LOC_LOC2 (_WTIMER_ROUTELOC0_CC1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */
AnnaBridge 170:e95d10626187 1239 #define WTIMER_ROUTELOC0_CC1LOC_LOC3 (_WTIMER_ROUTELOC0_CC1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */
AnnaBridge 170:e95d10626187 1240 #define WTIMER_ROUTELOC0_CC1LOC_LOC4 (_WTIMER_ROUTELOC0_CC1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */
AnnaBridge 170:e95d10626187 1241 #define WTIMER_ROUTELOC0_CC1LOC_LOC5 (_WTIMER_ROUTELOC0_CC1LOC_LOC5 << 8) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */
AnnaBridge 170:e95d10626187 1242 #define WTIMER_ROUTELOC0_CC1LOC_LOC6 (_WTIMER_ROUTELOC0_CC1LOC_LOC6 << 8) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */
AnnaBridge 170:e95d10626187 1243 #define WTIMER_ROUTELOC0_CC1LOC_LOC7 (_WTIMER_ROUTELOC0_CC1LOC_LOC7 << 8) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */
AnnaBridge 170:e95d10626187 1244 #define _WTIMER_ROUTELOC0_CC2LOC_SHIFT 16 /**< Shift value for TIMER_CC2LOC */
AnnaBridge 170:e95d10626187 1245 #define _WTIMER_ROUTELOC0_CC2LOC_MASK 0x70000UL /**< Bit mask for TIMER_CC2LOC */
AnnaBridge 170:e95d10626187 1246 #define _WTIMER_ROUTELOC0_CC2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */
AnnaBridge 170:e95d10626187 1247 #define _WTIMER_ROUTELOC0_CC2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */
AnnaBridge 170:e95d10626187 1248 #define _WTIMER_ROUTELOC0_CC2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */
AnnaBridge 170:e95d10626187 1249 #define _WTIMER_ROUTELOC0_CC2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */
AnnaBridge 170:e95d10626187 1250 #define _WTIMER_ROUTELOC0_CC2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */
AnnaBridge 170:e95d10626187 1251 #define _WTIMER_ROUTELOC0_CC2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */
AnnaBridge 170:e95d10626187 1252 #define _WTIMER_ROUTELOC0_CC2LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */
AnnaBridge 170:e95d10626187 1253 #define _WTIMER_ROUTELOC0_CC2LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */
AnnaBridge 170:e95d10626187 1254 #define _WTIMER_ROUTELOC0_CC2LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */
AnnaBridge 170:e95d10626187 1255 #define WTIMER_ROUTELOC0_CC2LOC_LOC0 (_WTIMER_ROUTELOC0_CC2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */
AnnaBridge 170:e95d10626187 1256 #define WTIMER_ROUTELOC0_CC2LOC_DEFAULT (_WTIMER_ROUTELOC0_CC2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */
AnnaBridge 170:e95d10626187 1257 #define WTIMER_ROUTELOC0_CC2LOC_LOC1 (_WTIMER_ROUTELOC0_CC2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */
AnnaBridge 170:e95d10626187 1258 #define WTIMER_ROUTELOC0_CC2LOC_LOC2 (_WTIMER_ROUTELOC0_CC2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */
AnnaBridge 170:e95d10626187 1259 #define WTIMER_ROUTELOC0_CC2LOC_LOC3 (_WTIMER_ROUTELOC0_CC2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */
AnnaBridge 170:e95d10626187 1260 #define WTIMER_ROUTELOC0_CC2LOC_LOC4 (_WTIMER_ROUTELOC0_CC2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */
AnnaBridge 170:e95d10626187 1261 #define WTIMER_ROUTELOC0_CC2LOC_LOC5 (_WTIMER_ROUTELOC0_CC2LOC_LOC5 << 16) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */
AnnaBridge 170:e95d10626187 1262 #define WTIMER_ROUTELOC0_CC2LOC_LOC6 (_WTIMER_ROUTELOC0_CC2LOC_LOC6 << 16) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */
AnnaBridge 170:e95d10626187 1263 #define WTIMER_ROUTELOC0_CC2LOC_LOC7 (_WTIMER_ROUTELOC0_CC2LOC_LOC7 << 16) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */
AnnaBridge 170:e95d10626187 1264 #define _WTIMER_ROUTELOC0_CC3LOC_SHIFT 24 /**< Shift value for TIMER_CC3LOC */
AnnaBridge 170:e95d10626187 1265 #define _WTIMER_ROUTELOC0_CC3LOC_MASK 0x7000000UL /**< Bit mask for TIMER_CC3LOC */
AnnaBridge 170:e95d10626187 1266 #define _WTIMER_ROUTELOC0_CC3LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */
AnnaBridge 170:e95d10626187 1267 #define _WTIMER_ROUTELOC0_CC3LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */
AnnaBridge 170:e95d10626187 1268 #define _WTIMER_ROUTELOC0_CC3LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */
AnnaBridge 170:e95d10626187 1269 #define _WTIMER_ROUTELOC0_CC3LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */
AnnaBridge 170:e95d10626187 1270 #define _WTIMER_ROUTELOC0_CC3LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */
AnnaBridge 170:e95d10626187 1271 #define _WTIMER_ROUTELOC0_CC3LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */
AnnaBridge 170:e95d10626187 1272 #define _WTIMER_ROUTELOC0_CC3LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */
AnnaBridge 170:e95d10626187 1273 #define _WTIMER_ROUTELOC0_CC3LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */
AnnaBridge 170:e95d10626187 1274 #define _WTIMER_ROUTELOC0_CC3LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */
AnnaBridge 170:e95d10626187 1275 #define WTIMER_ROUTELOC0_CC3LOC_LOC0 (_WTIMER_ROUTELOC0_CC3LOC_LOC0 << 24) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */
AnnaBridge 170:e95d10626187 1276 #define WTIMER_ROUTELOC0_CC3LOC_DEFAULT (_WTIMER_ROUTELOC0_CC3LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */
AnnaBridge 170:e95d10626187 1277 #define WTIMER_ROUTELOC0_CC3LOC_LOC1 (_WTIMER_ROUTELOC0_CC3LOC_LOC1 << 24) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */
AnnaBridge 170:e95d10626187 1278 #define WTIMER_ROUTELOC0_CC3LOC_LOC2 (_WTIMER_ROUTELOC0_CC3LOC_LOC2 << 24) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */
AnnaBridge 170:e95d10626187 1279 #define WTIMER_ROUTELOC0_CC3LOC_LOC3 (_WTIMER_ROUTELOC0_CC3LOC_LOC3 << 24) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */
AnnaBridge 170:e95d10626187 1280 #define WTIMER_ROUTELOC0_CC3LOC_LOC4 (_WTIMER_ROUTELOC0_CC3LOC_LOC4 << 24) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */
AnnaBridge 170:e95d10626187 1281 #define WTIMER_ROUTELOC0_CC3LOC_LOC5 (_WTIMER_ROUTELOC0_CC3LOC_LOC5 << 24) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */
AnnaBridge 170:e95d10626187 1282 #define WTIMER_ROUTELOC0_CC3LOC_LOC6 (_WTIMER_ROUTELOC0_CC3LOC_LOC6 << 24) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */
AnnaBridge 170:e95d10626187 1283 #define WTIMER_ROUTELOC0_CC3LOC_LOC7 (_WTIMER_ROUTELOC0_CC3LOC_LOC7 << 24) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */
AnnaBridge 170:e95d10626187 1284
AnnaBridge 170:e95d10626187 1285 /* Bit fields for WTIMER ROUTELOC2 */
AnnaBridge 170:e95d10626187 1286 #define _WTIMER_ROUTELOC2_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC2 */
AnnaBridge 170:e95d10626187 1287 #define _WTIMER_ROUTELOC2_MASK 0x00070707UL /**< Mask for WTIMER_ROUTELOC2 */
AnnaBridge 170:e95d10626187 1288 #define _WTIMER_ROUTELOC2_CDTI0LOC_SHIFT 0 /**< Shift value for TIMER_CDTI0LOC */
AnnaBridge 170:e95d10626187 1289 #define _WTIMER_ROUTELOC2_CDTI0LOC_MASK 0x7UL /**< Bit mask for TIMER_CDTI0LOC */
AnnaBridge 170:e95d10626187 1290 #define _WTIMER_ROUTELOC2_CDTI0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */
AnnaBridge 170:e95d10626187 1291 #define _WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */
AnnaBridge 170:e95d10626187 1292 #define _WTIMER_ROUTELOC2_CDTI0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */
AnnaBridge 170:e95d10626187 1293 #define _WTIMER_ROUTELOC2_CDTI0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */
AnnaBridge 170:e95d10626187 1294 #define _WTIMER_ROUTELOC2_CDTI0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */
AnnaBridge 170:e95d10626187 1295 #define _WTIMER_ROUTELOC2_CDTI0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */
AnnaBridge 170:e95d10626187 1296 #define WTIMER_ROUTELOC2_CDTI0LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */
AnnaBridge 170:e95d10626187 1297 #define WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */
AnnaBridge 170:e95d10626187 1298 #define WTIMER_ROUTELOC2_CDTI0LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */
AnnaBridge 170:e95d10626187 1299 #define WTIMER_ROUTELOC2_CDTI0LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */
AnnaBridge 170:e95d10626187 1300 #define WTIMER_ROUTELOC2_CDTI0LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */
AnnaBridge 170:e95d10626187 1301 #define WTIMER_ROUTELOC2_CDTI0LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */
AnnaBridge 170:e95d10626187 1302 #define _WTIMER_ROUTELOC2_CDTI1LOC_SHIFT 8 /**< Shift value for TIMER_CDTI1LOC */
AnnaBridge 170:e95d10626187 1303 #define _WTIMER_ROUTELOC2_CDTI1LOC_MASK 0x700UL /**< Bit mask for TIMER_CDTI1LOC */
AnnaBridge 170:e95d10626187 1304 #define _WTIMER_ROUTELOC2_CDTI1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */
AnnaBridge 170:e95d10626187 1305 #define _WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */
AnnaBridge 170:e95d10626187 1306 #define _WTIMER_ROUTELOC2_CDTI1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */
AnnaBridge 170:e95d10626187 1307 #define _WTIMER_ROUTELOC2_CDTI1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */
AnnaBridge 170:e95d10626187 1308 #define _WTIMER_ROUTELOC2_CDTI1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */
AnnaBridge 170:e95d10626187 1309 #define _WTIMER_ROUTELOC2_CDTI1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */
AnnaBridge 170:e95d10626187 1310 #define WTIMER_ROUTELOC2_CDTI1LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */
AnnaBridge 170:e95d10626187 1311 #define WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */
AnnaBridge 170:e95d10626187 1312 #define WTIMER_ROUTELOC2_CDTI1LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */
AnnaBridge 170:e95d10626187 1313 #define WTIMER_ROUTELOC2_CDTI1LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */
AnnaBridge 170:e95d10626187 1314 #define WTIMER_ROUTELOC2_CDTI1LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */
AnnaBridge 170:e95d10626187 1315 #define WTIMER_ROUTELOC2_CDTI1LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */
AnnaBridge 170:e95d10626187 1316 #define _WTIMER_ROUTELOC2_CDTI2LOC_SHIFT 16 /**< Shift value for TIMER_CDTI2LOC */
AnnaBridge 170:e95d10626187 1317 #define _WTIMER_ROUTELOC2_CDTI2LOC_MASK 0x70000UL /**< Bit mask for TIMER_CDTI2LOC */
AnnaBridge 170:e95d10626187 1318 #define _WTIMER_ROUTELOC2_CDTI2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */
AnnaBridge 170:e95d10626187 1319 #define _WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */
AnnaBridge 170:e95d10626187 1320 #define _WTIMER_ROUTELOC2_CDTI2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */
AnnaBridge 170:e95d10626187 1321 #define _WTIMER_ROUTELOC2_CDTI2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */
AnnaBridge 170:e95d10626187 1322 #define _WTIMER_ROUTELOC2_CDTI2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */
AnnaBridge 170:e95d10626187 1323 #define _WTIMER_ROUTELOC2_CDTI2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */
AnnaBridge 170:e95d10626187 1324 #define WTIMER_ROUTELOC2_CDTI2LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */
AnnaBridge 170:e95d10626187 1325 #define WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */
AnnaBridge 170:e95d10626187 1326 #define WTIMER_ROUTELOC2_CDTI2LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */
AnnaBridge 170:e95d10626187 1327 #define WTIMER_ROUTELOC2_CDTI2LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */
AnnaBridge 170:e95d10626187 1328 #define WTIMER_ROUTELOC2_CDTI2LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */
AnnaBridge 170:e95d10626187 1329 #define WTIMER_ROUTELOC2_CDTI2LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */
AnnaBridge 170:e95d10626187 1330
AnnaBridge 170:e95d10626187 1331 /* Bit fields for WTIMER CC_CTRL */
AnnaBridge 170:e95d10626187 1332 #define _WTIMER_CC_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CTRL */
AnnaBridge 170:e95d10626187 1333 #define _WTIMER_CC_CTRL_MASK 0x7F1F3F17UL /**< Mask for WTIMER_CC_CTRL */
AnnaBridge 170:e95d10626187 1334 #define _WTIMER_CC_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */
AnnaBridge 170:e95d10626187 1335 #define _WTIMER_CC_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */
AnnaBridge 170:e95d10626187 1336 #define _WTIMER_CC_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */
AnnaBridge 170:e95d10626187 1337 #define _WTIMER_CC_CTRL_MODE_OFF 0x00000000UL /**< Mode OFF for WTIMER_CC_CTRL */
AnnaBridge 170:e95d10626187 1338 #define _WTIMER_CC_CTRL_MODE_INPUTCAPTURE 0x00000001UL /**< Mode INPUTCAPTURE for WTIMER_CC_CTRL */
AnnaBridge 170:e95d10626187 1339 #define _WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE 0x00000002UL /**< Mode OUTPUTCOMPARE for WTIMER_CC_CTRL */
AnnaBridge 170:e95d10626187 1340 #define _WTIMER_CC_CTRL_MODE_PWM 0x00000003UL /**< Mode PWM for WTIMER_CC_CTRL */
AnnaBridge 170:e95d10626187 1341 #define WTIMER_CC_CTRL_MODE_DEFAULT (_WTIMER_CC_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */
AnnaBridge 170:e95d10626187 1342 #define WTIMER_CC_CTRL_MODE_OFF (_WTIMER_CC_CTRL_MODE_OFF << 0) /**< Shifted mode OFF for WTIMER_CC_CTRL */
AnnaBridge 170:e95d10626187 1343 #define WTIMER_CC_CTRL_MODE_INPUTCAPTURE (_WTIMER_CC_CTRL_MODE_INPUTCAPTURE << 0) /**< Shifted mode INPUTCAPTURE for WTIMER_CC_CTRL */
AnnaBridge 170:e95d10626187 1344 #define WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE (_WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE << 0) /**< Shifted mode OUTPUTCOMPARE for WTIMER_CC_CTRL */
AnnaBridge 170:e95d10626187 1345 #define WTIMER_CC_CTRL_MODE_PWM (_WTIMER_CC_CTRL_MODE_PWM << 0) /**< Shifted mode PWM for WTIMER_CC_CTRL */
AnnaBridge 170:e95d10626187 1346 #define WTIMER_CC_CTRL_OUTINV (0x1UL << 2) /**< Output Invert */
AnnaBridge 170:e95d10626187 1347 #define _WTIMER_CC_CTRL_OUTINV_SHIFT 2 /**< Shift value for TIMER_OUTINV */
AnnaBridge 170:e95d10626187 1348 #define _WTIMER_CC_CTRL_OUTINV_MASK 0x4UL /**< Bit mask for TIMER_OUTINV */
AnnaBridge 170:e95d10626187 1349 #define _WTIMER_CC_CTRL_OUTINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */
AnnaBridge 170:e95d10626187 1350 #define WTIMER_CC_CTRL_OUTINV_DEFAULT (_WTIMER_CC_CTRL_OUTINV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */
AnnaBridge 170:e95d10626187 1351 #define WTIMER_CC_CTRL_COIST (0x1UL << 4) /**< Compare Output Initial State */
AnnaBridge 170:e95d10626187 1352 #define _WTIMER_CC_CTRL_COIST_SHIFT 4 /**< Shift value for TIMER_COIST */
AnnaBridge 170:e95d10626187 1353 #define _WTIMER_CC_CTRL_COIST_MASK 0x10UL /**< Bit mask for TIMER_COIST */
AnnaBridge 170:e95d10626187 1354 #define _WTIMER_CC_CTRL_COIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */
AnnaBridge 170:e95d10626187 1355 #define WTIMER_CC_CTRL_COIST_DEFAULT (_WTIMER_CC_CTRL_COIST_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */
AnnaBridge 170:e95d10626187 1356 #define _WTIMER_CC_CTRL_CMOA_SHIFT 8 /**< Shift value for TIMER_CMOA */
AnnaBridge 170:e95d10626187 1357 #define _WTIMER_CC_CTRL_CMOA_MASK 0x300UL /**< Bit mask for TIMER_CMOA */
AnnaBridge 170:e95d10626187 1358 #define _WTIMER_CC_CTRL_CMOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */
AnnaBridge 170:e95d10626187 1359 #define _WTIMER_CC_CTRL_CMOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */
AnnaBridge 170:e95d10626187 1360 #define _WTIMER_CC_CTRL_CMOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */
AnnaBridge 170:e95d10626187 1361 #define _WTIMER_CC_CTRL_CMOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */
AnnaBridge 170:e95d10626187 1362 #define _WTIMER_CC_CTRL_CMOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */
AnnaBridge 170:e95d10626187 1363 #define WTIMER_CC_CTRL_CMOA_DEFAULT (_WTIMER_CC_CTRL_CMOA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */
AnnaBridge 170:e95d10626187 1364 #define WTIMER_CC_CTRL_CMOA_NONE (_WTIMER_CC_CTRL_CMOA_NONE << 8) /**< Shifted mode NONE for WTIMER_CC_CTRL */
AnnaBridge 170:e95d10626187 1365 #define WTIMER_CC_CTRL_CMOA_TOGGLE (_WTIMER_CC_CTRL_CMOA_TOGGLE << 8) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */
AnnaBridge 170:e95d10626187 1366 #define WTIMER_CC_CTRL_CMOA_CLEAR (_WTIMER_CC_CTRL_CMOA_CLEAR << 8) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */
AnnaBridge 170:e95d10626187 1367 #define WTIMER_CC_CTRL_CMOA_SET (_WTIMER_CC_CTRL_CMOA_SET << 8) /**< Shifted mode SET for WTIMER_CC_CTRL */
AnnaBridge 170:e95d10626187 1368 #define _WTIMER_CC_CTRL_COFOA_SHIFT 10 /**< Shift value for TIMER_COFOA */
AnnaBridge 170:e95d10626187 1369 #define _WTIMER_CC_CTRL_COFOA_MASK 0xC00UL /**< Bit mask for TIMER_COFOA */
AnnaBridge 170:e95d10626187 1370 #define _WTIMER_CC_CTRL_COFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */
AnnaBridge 170:e95d10626187 1371 #define _WTIMER_CC_CTRL_COFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */
AnnaBridge 170:e95d10626187 1372 #define _WTIMER_CC_CTRL_COFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */
AnnaBridge 170:e95d10626187 1373 #define _WTIMER_CC_CTRL_COFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */
AnnaBridge 170:e95d10626187 1374 #define _WTIMER_CC_CTRL_COFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */
AnnaBridge 170:e95d10626187 1375 #define WTIMER_CC_CTRL_COFOA_DEFAULT (_WTIMER_CC_CTRL_COFOA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */
AnnaBridge 170:e95d10626187 1376 #define WTIMER_CC_CTRL_COFOA_NONE (_WTIMER_CC_CTRL_COFOA_NONE << 10) /**< Shifted mode NONE for WTIMER_CC_CTRL */
AnnaBridge 170:e95d10626187 1377 #define WTIMER_CC_CTRL_COFOA_TOGGLE (_WTIMER_CC_CTRL_COFOA_TOGGLE << 10) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */
AnnaBridge 170:e95d10626187 1378 #define WTIMER_CC_CTRL_COFOA_CLEAR (_WTIMER_CC_CTRL_COFOA_CLEAR << 10) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */
AnnaBridge 170:e95d10626187 1379 #define WTIMER_CC_CTRL_COFOA_SET (_WTIMER_CC_CTRL_COFOA_SET << 10) /**< Shifted mode SET for WTIMER_CC_CTRL */
AnnaBridge 170:e95d10626187 1380 #define _WTIMER_CC_CTRL_CUFOA_SHIFT 12 /**< Shift value for TIMER_CUFOA */
AnnaBridge 170:e95d10626187 1381 #define _WTIMER_CC_CTRL_CUFOA_MASK 0x3000UL /**< Bit mask for TIMER_CUFOA */
AnnaBridge 170:e95d10626187 1382 #define _WTIMER_CC_CTRL_CUFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */
AnnaBridge 170:e95d10626187 1383 #define _WTIMER_CC_CTRL_CUFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */
AnnaBridge 170:e95d10626187 1384 #define _WTIMER_CC_CTRL_CUFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */
AnnaBridge 170:e95d10626187 1385 #define _WTIMER_CC_CTRL_CUFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */
AnnaBridge 170:e95d10626187 1386 #define _WTIMER_CC_CTRL_CUFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */
AnnaBridge 170:e95d10626187 1387 #define WTIMER_CC_CTRL_CUFOA_DEFAULT (_WTIMER_CC_CTRL_CUFOA_DEFAULT << 12) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */
AnnaBridge 170:e95d10626187 1388 #define WTIMER_CC_CTRL_CUFOA_NONE (_WTIMER_CC_CTRL_CUFOA_NONE << 12) /**< Shifted mode NONE for WTIMER_CC_CTRL */
AnnaBridge 170:e95d10626187 1389 #define WTIMER_CC_CTRL_CUFOA_TOGGLE (_WTIMER_CC_CTRL_CUFOA_TOGGLE << 12) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */
AnnaBridge 170:e95d10626187 1390 #define WTIMER_CC_CTRL_CUFOA_CLEAR (_WTIMER_CC_CTRL_CUFOA_CLEAR << 12) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */
AnnaBridge 170:e95d10626187 1391 #define WTIMER_CC_CTRL_CUFOA_SET (_WTIMER_CC_CTRL_CUFOA_SET << 12) /**< Shifted mode SET for WTIMER_CC_CTRL */
AnnaBridge 170:e95d10626187 1392 #define _WTIMER_CC_CTRL_PRSSEL_SHIFT 16 /**< Shift value for TIMER_PRSSEL */
AnnaBridge 170:e95d10626187 1393 #define _WTIMER_CC_CTRL_PRSSEL_MASK 0x1F0000UL /**< Bit mask for TIMER_PRSSEL */
AnnaBridge 170:e95d10626187 1394 #define _WTIMER_CC_CTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */
AnnaBridge 170:e95d10626187 1395 #define _WTIMER_CC_CTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_CC_CTRL */
AnnaBridge 170:e95d10626187 1396 #define _WTIMER_CC_CTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_CC_CTRL */
AnnaBridge 170:e95d10626187 1397 #define _WTIMER_CC_CTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_CC_CTRL */
AnnaBridge 170:e95d10626187 1398 #define _WTIMER_CC_CTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_CC_CTRL */
AnnaBridge 170:e95d10626187 1399 #define _WTIMER_CC_CTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_CC_CTRL */
AnnaBridge 170:e95d10626187 1400 #define _WTIMER_CC_CTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_CC_CTRL */
AnnaBridge 170:e95d10626187 1401 #define _WTIMER_CC_CTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_CC_CTRL */
AnnaBridge 170:e95d10626187 1402 #define _WTIMER_CC_CTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_CC_CTRL */
AnnaBridge 170:e95d10626187 1403 #define _WTIMER_CC_CTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_CC_CTRL */
AnnaBridge 170:e95d10626187 1404 #define _WTIMER_CC_CTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_CC_CTRL */
AnnaBridge 170:e95d10626187 1405 #define _WTIMER_CC_CTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_CC_CTRL */
AnnaBridge 170:e95d10626187 1406 #define _WTIMER_CC_CTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_CC_CTRL */
AnnaBridge 170:e95d10626187 1407 #define _WTIMER_CC_CTRL_PRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_CC_CTRL */
AnnaBridge 170:e95d10626187 1408 #define _WTIMER_CC_CTRL_PRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_CC_CTRL */
AnnaBridge 170:e95d10626187 1409 #define _WTIMER_CC_CTRL_PRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_CC_CTRL */
AnnaBridge 170:e95d10626187 1410 #define _WTIMER_CC_CTRL_PRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_CC_CTRL */
AnnaBridge 170:e95d10626187 1411 #define _WTIMER_CC_CTRL_PRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_CC_CTRL */
AnnaBridge 170:e95d10626187 1412 #define _WTIMER_CC_CTRL_PRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_CC_CTRL */
AnnaBridge 170:e95d10626187 1413 #define _WTIMER_CC_CTRL_PRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_CC_CTRL */
AnnaBridge 170:e95d10626187 1414 #define _WTIMER_CC_CTRL_PRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_CC_CTRL */
AnnaBridge 170:e95d10626187 1415 #define _WTIMER_CC_CTRL_PRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_CC_CTRL */
AnnaBridge 170:e95d10626187 1416 #define _WTIMER_CC_CTRL_PRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_CC_CTRL */
AnnaBridge 170:e95d10626187 1417 #define _WTIMER_CC_CTRL_PRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_CC_CTRL */
AnnaBridge 170:e95d10626187 1418 #define _WTIMER_CC_CTRL_PRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_CC_CTRL */
AnnaBridge 170:e95d10626187 1419 #define WTIMER_CC_CTRL_PRSSEL_DEFAULT (_WTIMER_CC_CTRL_PRSSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */
AnnaBridge 170:e95d10626187 1420 #define WTIMER_CC_CTRL_PRSSEL_PRSCH0 (_WTIMER_CC_CTRL_PRSSEL_PRSCH0 << 16) /**< Shifted mode PRSCH0 for WTIMER_CC_CTRL */
AnnaBridge 170:e95d10626187 1421 #define WTIMER_CC_CTRL_PRSSEL_PRSCH1 (_WTIMER_CC_CTRL_PRSSEL_PRSCH1 << 16) /**< Shifted mode PRSCH1 for WTIMER_CC_CTRL */
AnnaBridge 170:e95d10626187 1422 #define WTIMER_CC_CTRL_PRSSEL_PRSCH2 (_WTIMER_CC_CTRL_PRSSEL_PRSCH2 << 16) /**< Shifted mode PRSCH2 for WTIMER_CC_CTRL */
AnnaBridge 170:e95d10626187 1423 #define WTIMER_CC_CTRL_PRSSEL_PRSCH3 (_WTIMER_CC_CTRL_PRSSEL_PRSCH3 << 16) /**< Shifted mode PRSCH3 for WTIMER_CC_CTRL */
AnnaBridge 170:e95d10626187 1424 #define WTIMER_CC_CTRL_PRSSEL_PRSCH4 (_WTIMER_CC_CTRL_PRSSEL_PRSCH4 << 16) /**< Shifted mode PRSCH4 for WTIMER_CC_CTRL */
AnnaBridge 170:e95d10626187 1425 #define WTIMER_CC_CTRL_PRSSEL_PRSCH5 (_WTIMER_CC_CTRL_PRSSEL_PRSCH5 << 16) /**< Shifted mode PRSCH5 for WTIMER_CC_CTRL */
AnnaBridge 170:e95d10626187 1426 #define WTIMER_CC_CTRL_PRSSEL_PRSCH6 (_WTIMER_CC_CTRL_PRSSEL_PRSCH6 << 16) /**< Shifted mode PRSCH6 for WTIMER_CC_CTRL */
AnnaBridge 170:e95d10626187 1427 #define WTIMER_CC_CTRL_PRSSEL_PRSCH7 (_WTIMER_CC_CTRL_PRSSEL_PRSCH7 << 16) /**< Shifted mode PRSCH7 for WTIMER_CC_CTRL */
AnnaBridge 170:e95d10626187 1428 #define WTIMER_CC_CTRL_PRSSEL_PRSCH8 (_WTIMER_CC_CTRL_PRSSEL_PRSCH8 << 16) /**< Shifted mode PRSCH8 for WTIMER_CC_CTRL */
AnnaBridge 170:e95d10626187 1429 #define WTIMER_CC_CTRL_PRSSEL_PRSCH9 (_WTIMER_CC_CTRL_PRSSEL_PRSCH9 << 16) /**< Shifted mode PRSCH9 for WTIMER_CC_CTRL */
AnnaBridge 170:e95d10626187 1430 #define WTIMER_CC_CTRL_PRSSEL_PRSCH10 (_WTIMER_CC_CTRL_PRSSEL_PRSCH10 << 16) /**< Shifted mode PRSCH10 for WTIMER_CC_CTRL */
AnnaBridge 170:e95d10626187 1431 #define WTIMER_CC_CTRL_PRSSEL_PRSCH11 (_WTIMER_CC_CTRL_PRSSEL_PRSCH11 << 16) /**< Shifted mode PRSCH11 for WTIMER_CC_CTRL */
AnnaBridge 170:e95d10626187 1432 #define WTIMER_CC_CTRL_PRSSEL_PRSCH12 (_WTIMER_CC_CTRL_PRSSEL_PRSCH12 << 16) /**< Shifted mode PRSCH12 for WTIMER_CC_CTRL */
AnnaBridge 170:e95d10626187 1433 #define WTIMER_CC_CTRL_PRSSEL_PRSCH13 (_WTIMER_CC_CTRL_PRSSEL_PRSCH13 << 16) /**< Shifted mode PRSCH13 for WTIMER_CC_CTRL */
AnnaBridge 170:e95d10626187 1434 #define WTIMER_CC_CTRL_PRSSEL_PRSCH14 (_WTIMER_CC_CTRL_PRSSEL_PRSCH14 << 16) /**< Shifted mode PRSCH14 for WTIMER_CC_CTRL */
AnnaBridge 170:e95d10626187 1435 #define WTIMER_CC_CTRL_PRSSEL_PRSCH15 (_WTIMER_CC_CTRL_PRSSEL_PRSCH15 << 16) /**< Shifted mode PRSCH15 for WTIMER_CC_CTRL */
AnnaBridge 170:e95d10626187 1436 #define WTIMER_CC_CTRL_PRSSEL_PRSCH16 (_WTIMER_CC_CTRL_PRSSEL_PRSCH16 << 16) /**< Shifted mode PRSCH16 for WTIMER_CC_CTRL */
AnnaBridge 170:e95d10626187 1437 #define WTIMER_CC_CTRL_PRSSEL_PRSCH17 (_WTIMER_CC_CTRL_PRSSEL_PRSCH17 << 16) /**< Shifted mode PRSCH17 for WTIMER_CC_CTRL */
AnnaBridge 170:e95d10626187 1438 #define WTIMER_CC_CTRL_PRSSEL_PRSCH18 (_WTIMER_CC_CTRL_PRSSEL_PRSCH18 << 16) /**< Shifted mode PRSCH18 for WTIMER_CC_CTRL */
AnnaBridge 170:e95d10626187 1439 #define WTIMER_CC_CTRL_PRSSEL_PRSCH19 (_WTIMER_CC_CTRL_PRSSEL_PRSCH19 << 16) /**< Shifted mode PRSCH19 for WTIMER_CC_CTRL */
AnnaBridge 170:e95d10626187 1440 #define WTIMER_CC_CTRL_PRSSEL_PRSCH20 (_WTIMER_CC_CTRL_PRSSEL_PRSCH20 << 16) /**< Shifted mode PRSCH20 for WTIMER_CC_CTRL */
AnnaBridge 170:e95d10626187 1441 #define WTIMER_CC_CTRL_PRSSEL_PRSCH21 (_WTIMER_CC_CTRL_PRSSEL_PRSCH21 << 16) /**< Shifted mode PRSCH21 for WTIMER_CC_CTRL */
AnnaBridge 170:e95d10626187 1442 #define WTIMER_CC_CTRL_PRSSEL_PRSCH22 (_WTIMER_CC_CTRL_PRSSEL_PRSCH22 << 16) /**< Shifted mode PRSCH22 for WTIMER_CC_CTRL */
AnnaBridge 170:e95d10626187 1443 #define WTIMER_CC_CTRL_PRSSEL_PRSCH23 (_WTIMER_CC_CTRL_PRSSEL_PRSCH23 << 16) /**< Shifted mode PRSCH23 for WTIMER_CC_CTRL */
AnnaBridge 170:e95d10626187 1444 #define _WTIMER_CC_CTRL_ICEDGE_SHIFT 24 /**< Shift value for TIMER_ICEDGE */
AnnaBridge 170:e95d10626187 1445 #define _WTIMER_CC_CTRL_ICEDGE_MASK 0x3000000UL /**< Bit mask for TIMER_ICEDGE */
AnnaBridge 170:e95d10626187 1446 #define _WTIMER_CC_CTRL_ICEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */
AnnaBridge 170:e95d10626187 1447 #define _WTIMER_CC_CTRL_ICEDGE_RISING 0x00000000UL /**< Mode RISING for WTIMER_CC_CTRL */
AnnaBridge 170:e95d10626187 1448 #define _WTIMER_CC_CTRL_ICEDGE_FALLING 0x00000001UL /**< Mode FALLING for WTIMER_CC_CTRL */
AnnaBridge 170:e95d10626187 1449 #define _WTIMER_CC_CTRL_ICEDGE_BOTH 0x00000002UL /**< Mode BOTH for WTIMER_CC_CTRL */
AnnaBridge 170:e95d10626187 1450 #define _WTIMER_CC_CTRL_ICEDGE_NONE 0x00000003UL /**< Mode NONE for WTIMER_CC_CTRL */
AnnaBridge 170:e95d10626187 1451 #define WTIMER_CC_CTRL_ICEDGE_DEFAULT (_WTIMER_CC_CTRL_ICEDGE_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */
AnnaBridge 170:e95d10626187 1452 #define WTIMER_CC_CTRL_ICEDGE_RISING (_WTIMER_CC_CTRL_ICEDGE_RISING << 24) /**< Shifted mode RISING for WTIMER_CC_CTRL */
AnnaBridge 170:e95d10626187 1453 #define WTIMER_CC_CTRL_ICEDGE_FALLING (_WTIMER_CC_CTRL_ICEDGE_FALLING << 24) /**< Shifted mode FALLING for WTIMER_CC_CTRL */
AnnaBridge 170:e95d10626187 1454 #define WTIMER_CC_CTRL_ICEDGE_BOTH (_WTIMER_CC_CTRL_ICEDGE_BOTH << 24) /**< Shifted mode BOTH for WTIMER_CC_CTRL */
AnnaBridge 170:e95d10626187 1455 #define WTIMER_CC_CTRL_ICEDGE_NONE (_WTIMER_CC_CTRL_ICEDGE_NONE << 24) /**< Shifted mode NONE for WTIMER_CC_CTRL */
AnnaBridge 170:e95d10626187 1456 #define _WTIMER_CC_CTRL_ICEVCTRL_SHIFT 26 /**< Shift value for TIMER_ICEVCTRL */
AnnaBridge 170:e95d10626187 1457 #define _WTIMER_CC_CTRL_ICEVCTRL_MASK 0xC000000UL /**< Bit mask for TIMER_ICEVCTRL */
AnnaBridge 170:e95d10626187 1458 #define _WTIMER_CC_CTRL_ICEVCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */
AnnaBridge 170:e95d10626187 1459 #define _WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE 0x00000000UL /**< Mode EVERYEDGE for WTIMER_CC_CTRL */
AnnaBridge 170:e95d10626187 1460 #define _WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE 0x00000001UL /**< Mode EVERYSECONDEDGE for WTIMER_CC_CTRL */
AnnaBridge 170:e95d10626187 1461 #define _WTIMER_CC_CTRL_ICEVCTRL_RISING 0x00000002UL /**< Mode RISING for WTIMER_CC_CTRL */
AnnaBridge 170:e95d10626187 1462 #define _WTIMER_CC_CTRL_ICEVCTRL_FALLING 0x00000003UL /**< Mode FALLING for WTIMER_CC_CTRL */
AnnaBridge 170:e95d10626187 1463 #define WTIMER_CC_CTRL_ICEVCTRL_DEFAULT (_WTIMER_CC_CTRL_ICEVCTRL_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */
AnnaBridge 170:e95d10626187 1464 #define WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE << 26) /**< Shifted mode EVERYEDGE for WTIMER_CC_CTRL */
AnnaBridge 170:e95d10626187 1465 #define WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE << 26) /**< Shifted mode EVERYSECONDEDGE for WTIMER_CC_CTRL */
AnnaBridge 170:e95d10626187 1466 #define WTIMER_CC_CTRL_ICEVCTRL_RISING (_WTIMER_CC_CTRL_ICEVCTRL_RISING << 26) /**< Shifted mode RISING for WTIMER_CC_CTRL */
AnnaBridge 170:e95d10626187 1467 #define WTIMER_CC_CTRL_ICEVCTRL_FALLING (_WTIMER_CC_CTRL_ICEVCTRL_FALLING << 26) /**< Shifted mode FALLING for WTIMER_CC_CTRL */
AnnaBridge 170:e95d10626187 1468 #define WTIMER_CC_CTRL_PRSCONF (0x1UL << 28) /**< PRS Configuration */
AnnaBridge 170:e95d10626187 1469 #define _WTIMER_CC_CTRL_PRSCONF_SHIFT 28 /**< Shift value for TIMER_PRSCONF */
AnnaBridge 170:e95d10626187 1470 #define _WTIMER_CC_CTRL_PRSCONF_MASK 0x10000000UL /**< Bit mask for TIMER_PRSCONF */
AnnaBridge 170:e95d10626187 1471 #define _WTIMER_CC_CTRL_PRSCONF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */
AnnaBridge 170:e95d10626187 1472 #define _WTIMER_CC_CTRL_PRSCONF_PULSE 0x00000000UL /**< Mode PULSE for WTIMER_CC_CTRL */
AnnaBridge 170:e95d10626187 1473 #define _WTIMER_CC_CTRL_PRSCONF_LEVEL 0x00000001UL /**< Mode LEVEL for WTIMER_CC_CTRL */
AnnaBridge 170:e95d10626187 1474 #define WTIMER_CC_CTRL_PRSCONF_DEFAULT (_WTIMER_CC_CTRL_PRSCONF_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */
AnnaBridge 170:e95d10626187 1475 #define WTIMER_CC_CTRL_PRSCONF_PULSE (_WTIMER_CC_CTRL_PRSCONF_PULSE << 28) /**< Shifted mode PULSE for WTIMER_CC_CTRL */
AnnaBridge 170:e95d10626187 1476 #define WTIMER_CC_CTRL_PRSCONF_LEVEL (_WTIMER_CC_CTRL_PRSCONF_LEVEL << 28) /**< Shifted mode LEVEL for WTIMER_CC_CTRL */
AnnaBridge 170:e95d10626187 1477 #define WTIMER_CC_CTRL_INSEL (0x1UL << 29) /**< Input Selection */
AnnaBridge 170:e95d10626187 1478 #define _WTIMER_CC_CTRL_INSEL_SHIFT 29 /**< Shift value for TIMER_INSEL */
AnnaBridge 170:e95d10626187 1479 #define _WTIMER_CC_CTRL_INSEL_MASK 0x20000000UL /**< Bit mask for TIMER_INSEL */
AnnaBridge 170:e95d10626187 1480 #define _WTIMER_CC_CTRL_INSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */
AnnaBridge 170:e95d10626187 1481 #define _WTIMER_CC_CTRL_INSEL_PIN 0x00000000UL /**< Mode PIN for WTIMER_CC_CTRL */
AnnaBridge 170:e95d10626187 1482 #define _WTIMER_CC_CTRL_INSEL_PRS 0x00000001UL /**< Mode PRS for WTIMER_CC_CTRL */
AnnaBridge 170:e95d10626187 1483 #define WTIMER_CC_CTRL_INSEL_DEFAULT (_WTIMER_CC_CTRL_INSEL_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */
AnnaBridge 170:e95d10626187 1484 #define WTIMER_CC_CTRL_INSEL_PIN (_WTIMER_CC_CTRL_INSEL_PIN << 29) /**< Shifted mode PIN for WTIMER_CC_CTRL */
AnnaBridge 170:e95d10626187 1485 #define WTIMER_CC_CTRL_INSEL_PRS (_WTIMER_CC_CTRL_INSEL_PRS << 29) /**< Shifted mode PRS for WTIMER_CC_CTRL */
AnnaBridge 170:e95d10626187 1486 #define WTIMER_CC_CTRL_FILT (0x1UL << 30) /**< Digital Filter */
AnnaBridge 170:e95d10626187 1487 #define _WTIMER_CC_CTRL_FILT_SHIFT 30 /**< Shift value for TIMER_FILT */
AnnaBridge 170:e95d10626187 1488 #define _WTIMER_CC_CTRL_FILT_MASK 0x40000000UL /**< Bit mask for TIMER_FILT */
AnnaBridge 170:e95d10626187 1489 #define _WTIMER_CC_CTRL_FILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */
AnnaBridge 170:e95d10626187 1490 #define _WTIMER_CC_CTRL_FILT_DISABLE 0x00000000UL /**< Mode DISABLE for WTIMER_CC_CTRL */
AnnaBridge 170:e95d10626187 1491 #define _WTIMER_CC_CTRL_FILT_ENABLE 0x00000001UL /**< Mode ENABLE for WTIMER_CC_CTRL */
AnnaBridge 170:e95d10626187 1492 #define WTIMER_CC_CTRL_FILT_DEFAULT (_WTIMER_CC_CTRL_FILT_DEFAULT << 30) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */
AnnaBridge 170:e95d10626187 1493 #define WTIMER_CC_CTRL_FILT_DISABLE (_WTIMER_CC_CTRL_FILT_DISABLE << 30) /**< Shifted mode DISABLE for WTIMER_CC_CTRL */
AnnaBridge 170:e95d10626187 1494 #define WTIMER_CC_CTRL_FILT_ENABLE (_WTIMER_CC_CTRL_FILT_ENABLE << 30) /**< Shifted mode ENABLE for WTIMER_CC_CTRL */
AnnaBridge 170:e95d10626187 1495
AnnaBridge 170:e95d10626187 1496 /* Bit fields for WTIMER CC_CCV */
AnnaBridge 170:e95d10626187 1497 #define _WTIMER_CC_CCV_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCV */
AnnaBridge 170:e95d10626187 1498 #define _WTIMER_CC_CCV_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCV */
AnnaBridge 170:e95d10626187 1499 #define _WTIMER_CC_CCV_CCV_SHIFT 0 /**< Shift value for TIMER_CCV */
AnnaBridge 170:e95d10626187 1500 #define _WTIMER_CC_CCV_CCV_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCV */
AnnaBridge 170:e95d10626187 1501 #define _WTIMER_CC_CCV_CCV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCV */
AnnaBridge 170:e95d10626187 1502 #define WTIMER_CC_CCV_CCV_DEFAULT (_WTIMER_CC_CCV_CCV_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCV */
AnnaBridge 170:e95d10626187 1503
AnnaBridge 170:e95d10626187 1504 /* Bit fields for WTIMER CC_CCVP */
AnnaBridge 170:e95d10626187 1505 #define _WTIMER_CC_CCVP_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVP */
AnnaBridge 170:e95d10626187 1506 #define _WTIMER_CC_CCVP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVP */
AnnaBridge 170:e95d10626187 1507 #define _WTIMER_CC_CCVP_CCVP_SHIFT 0 /**< Shift value for TIMER_CCVP */
AnnaBridge 170:e95d10626187 1508 #define _WTIMER_CC_CCVP_CCVP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVP */
AnnaBridge 170:e95d10626187 1509 #define _WTIMER_CC_CCVP_CCVP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVP */
AnnaBridge 170:e95d10626187 1510 #define WTIMER_CC_CCVP_CCVP_DEFAULT (_WTIMER_CC_CCVP_CCVP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVP */
AnnaBridge 170:e95d10626187 1511
AnnaBridge 170:e95d10626187 1512 /* Bit fields for WTIMER CC_CCVB */
AnnaBridge 170:e95d10626187 1513 #define _WTIMER_CC_CCVB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVB */
AnnaBridge 170:e95d10626187 1514 #define _WTIMER_CC_CCVB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVB */
AnnaBridge 170:e95d10626187 1515 #define _WTIMER_CC_CCVB_CCVB_SHIFT 0 /**< Shift value for TIMER_CCVB */
AnnaBridge 170:e95d10626187 1516 #define _WTIMER_CC_CCVB_CCVB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVB */
AnnaBridge 170:e95d10626187 1517 #define _WTIMER_CC_CCVB_CCVB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVB */
AnnaBridge 170:e95d10626187 1518 #define WTIMER_CC_CCVB_CCVB_DEFAULT (_WTIMER_CC_CCVB_CCVB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVB */
AnnaBridge 170:e95d10626187 1519
AnnaBridge 170:e95d10626187 1520 /* Bit fields for WTIMER DTCTRL */
AnnaBridge 170:e95d10626187 1521 #define _WTIMER_DTCTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTCTRL */
AnnaBridge 170:e95d10626187 1522 #define _WTIMER_DTCTRL_MASK 0x010007FFUL /**< Mask for WTIMER_DTCTRL */
AnnaBridge 170:e95d10626187 1523 #define WTIMER_DTCTRL_DTEN (0x1UL << 0) /**< DTI Enable */
AnnaBridge 170:e95d10626187 1524 #define _WTIMER_DTCTRL_DTEN_SHIFT 0 /**< Shift value for TIMER_DTEN */
AnnaBridge 170:e95d10626187 1525 #define _WTIMER_DTCTRL_DTEN_MASK 0x1UL /**< Bit mask for TIMER_DTEN */
AnnaBridge 170:e95d10626187 1526 #define _WTIMER_DTCTRL_DTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */
AnnaBridge 170:e95d10626187 1527 #define WTIMER_DTCTRL_DTEN_DEFAULT (_WTIMER_DTCTRL_DTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */
AnnaBridge 170:e95d10626187 1528 #define WTIMER_DTCTRL_DTDAS (0x1UL << 1) /**< DTI Automatic Start-up Functionality */
AnnaBridge 170:e95d10626187 1529 #define _WTIMER_DTCTRL_DTDAS_SHIFT 1 /**< Shift value for TIMER_DTDAS */
AnnaBridge 170:e95d10626187 1530 #define _WTIMER_DTCTRL_DTDAS_MASK 0x2UL /**< Bit mask for TIMER_DTDAS */
AnnaBridge 170:e95d10626187 1531 #define _WTIMER_DTCTRL_DTDAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */
AnnaBridge 170:e95d10626187 1532 #define _WTIMER_DTCTRL_DTDAS_NORESTART 0x00000000UL /**< Mode NORESTART for WTIMER_DTCTRL */
AnnaBridge 170:e95d10626187 1533 #define _WTIMER_DTCTRL_DTDAS_RESTART 0x00000001UL /**< Mode RESTART for WTIMER_DTCTRL */
AnnaBridge 170:e95d10626187 1534 #define WTIMER_DTCTRL_DTDAS_DEFAULT (_WTIMER_DTCTRL_DTDAS_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */
AnnaBridge 170:e95d10626187 1535 #define WTIMER_DTCTRL_DTDAS_NORESTART (_WTIMER_DTCTRL_DTDAS_NORESTART << 1) /**< Shifted mode NORESTART for WTIMER_DTCTRL */
AnnaBridge 170:e95d10626187 1536 #define WTIMER_DTCTRL_DTDAS_RESTART (_WTIMER_DTCTRL_DTDAS_RESTART << 1) /**< Shifted mode RESTART for WTIMER_DTCTRL */
AnnaBridge 170:e95d10626187 1537 #define WTIMER_DTCTRL_DTIPOL (0x1UL << 2) /**< DTI Inactive Polarity */
AnnaBridge 170:e95d10626187 1538 #define _WTIMER_DTCTRL_DTIPOL_SHIFT 2 /**< Shift value for TIMER_DTIPOL */
AnnaBridge 170:e95d10626187 1539 #define _WTIMER_DTCTRL_DTIPOL_MASK 0x4UL /**< Bit mask for TIMER_DTIPOL */
AnnaBridge 170:e95d10626187 1540 #define _WTIMER_DTCTRL_DTIPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */
AnnaBridge 170:e95d10626187 1541 #define WTIMER_DTCTRL_DTIPOL_DEFAULT (_WTIMER_DTCTRL_DTIPOL_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */
AnnaBridge 170:e95d10626187 1542 #define WTIMER_DTCTRL_DTCINV (0x1UL << 3) /**< DTI Complementary Output Invert. */
AnnaBridge 170:e95d10626187 1543 #define _WTIMER_DTCTRL_DTCINV_SHIFT 3 /**< Shift value for TIMER_DTCINV */
AnnaBridge 170:e95d10626187 1544 #define _WTIMER_DTCTRL_DTCINV_MASK 0x8UL /**< Bit mask for TIMER_DTCINV */
AnnaBridge 170:e95d10626187 1545 #define _WTIMER_DTCTRL_DTCINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */
AnnaBridge 170:e95d10626187 1546 #define WTIMER_DTCTRL_DTCINV_DEFAULT (_WTIMER_DTCTRL_DTCINV_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */
AnnaBridge 170:e95d10626187 1547 #define _WTIMER_DTCTRL_DTPRSSEL_SHIFT 4 /**< Shift value for TIMER_DTPRSSEL */
AnnaBridge 170:e95d10626187 1548 #define _WTIMER_DTCTRL_DTPRSSEL_MASK 0x1F0UL /**< Bit mask for TIMER_DTPRSSEL */
AnnaBridge 170:e95d10626187 1549 #define _WTIMER_DTCTRL_DTPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */
AnnaBridge 170:e95d10626187 1550 #define _WTIMER_DTCTRL_DTPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTCTRL */
AnnaBridge 170:e95d10626187 1551 #define _WTIMER_DTCTRL_DTPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTCTRL */
AnnaBridge 170:e95d10626187 1552 #define _WTIMER_DTCTRL_DTPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTCTRL */
AnnaBridge 170:e95d10626187 1553 #define _WTIMER_DTCTRL_DTPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTCTRL */
AnnaBridge 170:e95d10626187 1554 #define _WTIMER_DTCTRL_DTPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTCTRL */
AnnaBridge 170:e95d10626187 1555 #define _WTIMER_DTCTRL_DTPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTCTRL */
AnnaBridge 170:e95d10626187 1556 #define _WTIMER_DTCTRL_DTPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTCTRL */
AnnaBridge 170:e95d10626187 1557 #define _WTIMER_DTCTRL_DTPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTCTRL */
AnnaBridge 170:e95d10626187 1558 #define _WTIMER_DTCTRL_DTPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTCTRL */
AnnaBridge 170:e95d10626187 1559 #define _WTIMER_DTCTRL_DTPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTCTRL */
AnnaBridge 170:e95d10626187 1560 #define _WTIMER_DTCTRL_DTPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTCTRL */
AnnaBridge 170:e95d10626187 1561 #define _WTIMER_DTCTRL_DTPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTCTRL */
AnnaBridge 170:e95d10626187 1562 #define _WTIMER_DTCTRL_DTPRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_DTCTRL */
AnnaBridge 170:e95d10626187 1563 #define _WTIMER_DTCTRL_DTPRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_DTCTRL */
AnnaBridge 170:e95d10626187 1564 #define _WTIMER_DTCTRL_DTPRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_DTCTRL */
AnnaBridge 170:e95d10626187 1565 #define _WTIMER_DTCTRL_DTPRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_DTCTRL */
AnnaBridge 170:e95d10626187 1566 #define _WTIMER_DTCTRL_DTPRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_DTCTRL */
AnnaBridge 170:e95d10626187 1567 #define _WTIMER_DTCTRL_DTPRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_DTCTRL */
AnnaBridge 170:e95d10626187 1568 #define _WTIMER_DTCTRL_DTPRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_DTCTRL */
AnnaBridge 170:e95d10626187 1569 #define _WTIMER_DTCTRL_DTPRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_DTCTRL */
AnnaBridge 170:e95d10626187 1570 #define _WTIMER_DTCTRL_DTPRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_DTCTRL */
AnnaBridge 170:e95d10626187 1571 #define _WTIMER_DTCTRL_DTPRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_DTCTRL */
AnnaBridge 170:e95d10626187 1572 #define _WTIMER_DTCTRL_DTPRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_DTCTRL */
AnnaBridge 170:e95d10626187 1573 #define _WTIMER_DTCTRL_DTPRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_DTCTRL */
AnnaBridge 170:e95d10626187 1574 #define WTIMER_DTCTRL_DTPRSSEL_DEFAULT (_WTIMER_DTCTRL_DTPRSSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */
AnnaBridge 170:e95d10626187 1575 #define WTIMER_DTCTRL_DTPRSSEL_PRSCH0 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH0 << 4) /**< Shifted mode PRSCH0 for WTIMER_DTCTRL */
AnnaBridge 170:e95d10626187 1576 #define WTIMER_DTCTRL_DTPRSSEL_PRSCH1 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH1 << 4) /**< Shifted mode PRSCH1 for WTIMER_DTCTRL */
AnnaBridge 170:e95d10626187 1577 #define WTIMER_DTCTRL_DTPRSSEL_PRSCH2 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH2 << 4) /**< Shifted mode PRSCH2 for WTIMER_DTCTRL */
AnnaBridge 170:e95d10626187 1578 #define WTIMER_DTCTRL_DTPRSSEL_PRSCH3 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH3 << 4) /**< Shifted mode PRSCH3 for WTIMER_DTCTRL */
AnnaBridge 170:e95d10626187 1579 #define WTIMER_DTCTRL_DTPRSSEL_PRSCH4 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH4 << 4) /**< Shifted mode PRSCH4 for WTIMER_DTCTRL */
AnnaBridge 170:e95d10626187 1580 #define WTIMER_DTCTRL_DTPRSSEL_PRSCH5 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH5 << 4) /**< Shifted mode PRSCH5 for WTIMER_DTCTRL */
AnnaBridge 170:e95d10626187 1581 #define WTIMER_DTCTRL_DTPRSSEL_PRSCH6 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH6 << 4) /**< Shifted mode PRSCH6 for WTIMER_DTCTRL */
AnnaBridge 170:e95d10626187 1582 #define WTIMER_DTCTRL_DTPRSSEL_PRSCH7 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH7 << 4) /**< Shifted mode PRSCH7 for WTIMER_DTCTRL */
AnnaBridge 170:e95d10626187 1583 #define WTIMER_DTCTRL_DTPRSSEL_PRSCH8 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH8 << 4) /**< Shifted mode PRSCH8 for WTIMER_DTCTRL */
AnnaBridge 170:e95d10626187 1584 #define WTIMER_DTCTRL_DTPRSSEL_PRSCH9 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH9 << 4) /**< Shifted mode PRSCH9 for WTIMER_DTCTRL */
AnnaBridge 170:e95d10626187 1585 #define WTIMER_DTCTRL_DTPRSSEL_PRSCH10 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH10 << 4) /**< Shifted mode PRSCH10 for WTIMER_DTCTRL */
AnnaBridge 170:e95d10626187 1586 #define WTIMER_DTCTRL_DTPRSSEL_PRSCH11 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH11 << 4) /**< Shifted mode PRSCH11 for WTIMER_DTCTRL */
AnnaBridge 170:e95d10626187 1587 #define WTIMER_DTCTRL_DTPRSSEL_PRSCH12 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH12 << 4) /**< Shifted mode PRSCH12 for WTIMER_DTCTRL */
AnnaBridge 170:e95d10626187 1588 #define WTIMER_DTCTRL_DTPRSSEL_PRSCH13 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH13 << 4) /**< Shifted mode PRSCH13 for WTIMER_DTCTRL */
AnnaBridge 170:e95d10626187 1589 #define WTIMER_DTCTRL_DTPRSSEL_PRSCH14 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH14 << 4) /**< Shifted mode PRSCH14 for WTIMER_DTCTRL */
AnnaBridge 170:e95d10626187 1590 #define WTIMER_DTCTRL_DTPRSSEL_PRSCH15 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH15 << 4) /**< Shifted mode PRSCH15 for WTIMER_DTCTRL */
AnnaBridge 170:e95d10626187 1591 #define WTIMER_DTCTRL_DTPRSSEL_PRSCH16 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH16 << 4) /**< Shifted mode PRSCH16 for WTIMER_DTCTRL */
AnnaBridge 170:e95d10626187 1592 #define WTIMER_DTCTRL_DTPRSSEL_PRSCH17 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH17 << 4) /**< Shifted mode PRSCH17 for WTIMER_DTCTRL */
AnnaBridge 170:e95d10626187 1593 #define WTIMER_DTCTRL_DTPRSSEL_PRSCH18 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH18 << 4) /**< Shifted mode PRSCH18 for WTIMER_DTCTRL */
AnnaBridge 170:e95d10626187 1594 #define WTIMER_DTCTRL_DTPRSSEL_PRSCH19 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH19 << 4) /**< Shifted mode PRSCH19 for WTIMER_DTCTRL */
AnnaBridge 170:e95d10626187 1595 #define WTIMER_DTCTRL_DTPRSSEL_PRSCH20 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH20 << 4) /**< Shifted mode PRSCH20 for WTIMER_DTCTRL */
AnnaBridge 170:e95d10626187 1596 #define WTIMER_DTCTRL_DTPRSSEL_PRSCH21 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH21 << 4) /**< Shifted mode PRSCH21 for WTIMER_DTCTRL */
AnnaBridge 170:e95d10626187 1597 #define WTIMER_DTCTRL_DTPRSSEL_PRSCH22 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH22 << 4) /**< Shifted mode PRSCH22 for WTIMER_DTCTRL */
AnnaBridge 170:e95d10626187 1598 #define WTIMER_DTCTRL_DTPRSSEL_PRSCH23 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH23 << 4) /**< Shifted mode PRSCH23 for WTIMER_DTCTRL */
AnnaBridge 170:e95d10626187 1599 #define WTIMER_DTCTRL_DTAR (0x1UL << 9) /**< DTI Always Run */
AnnaBridge 170:e95d10626187 1600 #define _WTIMER_DTCTRL_DTAR_SHIFT 9 /**< Shift value for TIMER_DTAR */
AnnaBridge 170:e95d10626187 1601 #define _WTIMER_DTCTRL_DTAR_MASK 0x200UL /**< Bit mask for TIMER_DTAR */
AnnaBridge 170:e95d10626187 1602 #define _WTIMER_DTCTRL_DTAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */
AnnaBridge 170:e95d10626187 1603 #define WTIMER_DTCTRL_DTAR_DEFAULT (_WTIMER_DTCTRL_DTAR_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */
AnnaBridge 170:e95d10626187 1604 #define WTIMER_DTCTRL_DTFATS (0x1UL << 10) /**< DTI Fault Action on Timer Stop */
AnnaBridge 170:e95d10626187 1605 #define _WTIMER_DTCTRL_DTFATS_SHIFT 10 /**< Shift value for TIMER_DTFATS */
AnnaBridge 170:e95d10626187 1606 #define _WTIMER_DTCTRL_DTFATS_MASK 0x400UL /**< Bit mask for TIMER_DTFATS */
AnnaBridge 170:e95d10626187 1607 #define _WTIMER_DTCTRL_DTFATS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */
AnnaBridge 170:e95d10626187 1608 #define WTIMER_DTCTRL_DTFATS_DEFAULT (_WTIMER_DTCTRL_DTFATS_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */
AnnaBridge 170:e95d10626187 1609 #define WTIMER_DTCTRL_DTPRSEN (0x1UL << 24) /**< DTI PRS Source Enable */
AnnaBridge 170:e95d10626187 1610 #define _WTIMER_DTCTRL_DTPRSEN_SHIFT 24 /**< Shift value for TIMER_DTPRSEN */
AnnaBridge 170:e95d10626187 1611 #define _WTIMER_DTCTRL_DTPRSEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRSEN */
AnnaBridge 170:e95d10626187 1612 #define _WTIMER_DTCTRL_DTPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */
AnnaBridge 170:e95d10626187 1613 #define WTIMER_DTCTRL_DTPRSEN_DEFAULT (_WTIMER_DTCTRL_DTPRSEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */
AnnaBridge 170:e95d10626187 1614
AnnaBridge 170:e95d10626187 1615 /* Bit fields for WTIMER DTTIME */
AnnaBridge 170:e95d10626187 1616 #define _WTIMER_DTTIME_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTTIME */
AnnaBridge 170:e95d10626187 1617 #define _WTIMER_DTTIME_MASK 0x003F3F0FUL /**< Mask for WTIMER_DTTIME */
AnnaBridge 170:e95d10626187 1618 #define _WTIMER_DTTIME_DTPRESC_SHIFT 0 /**< Shift value for TIMER_DTPRESC */
AnnaBridge 170:e95d10626187 1619 #define _WTIMER_DTTIME_DTPRESC_MASK 0xFUL /**< Bit mask for TIMER_DTPRESC */
AnnaBridge 170:e95d10626187 1620 #define _WTIMER_DTTIME_DTPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */
AnnaBridge 170:e95d10626187 1621 #define _WTIMER_DTTIME_DTPRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_DTTIME */
AnnaBridge 170:e95d10626187 1622 #define _WTIMER_DTTIME_DTPRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_DTTIME */
AnnaBridge 170:e95d10626187 1623 #define _WTIMER_DTTIME_DTPRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_DTTIME */
AnnaBridge 170:e95d10626187 1624 #define _WTIMER_DTTIME_DTPRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_DTTIME */
AnnaBridge 170:e95d10626187 1625 #define _WTIMER_DTTIME_DTPRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_DTTIME */
AnnaBridge 170:e95d10626187 1626 #define _WTIMER_DTTIME_DTPRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_DTTIME */
AnnaBridge 170:e95d10626187 1627 #define _WTIMER_DTTIME_DTPRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_DTTIME */
AnnaBridge 170:e95d10626187 1628 #define _WTIMER_DTTIME_DTPRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_DTTIME */
AnnaBridge 170:e95d10626187 1629 #define _WTIMER_DTTIME_DTPRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_DTTIME */
AnnaBridge 170:e95d10626187 1630 #define _WTIMER_DTTIME_DTPRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_DTTIME */
AnnaBridge 170:e95d10626187 1631 #define _WTIMER_DTTIME_DTPRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_DTTIME */
AnnaBridge 170:e95d10626187 1632 #define WTIMER_DTTIME_DTPRESC_DEFAULT (_WTIMER_DTTIME_DTPRESC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTTIME */
AnnaBridge 170:e95d10626187 1633 #define WTIMER_DTTIME_DTPRESC_DIV1 (_WTIMER_DTTIME_DTPRESC_DIV1 << 0) /**< Shifted mode DIV1 for WTIMER_DTTIME */
AnnaBridge 170:e95d10626187 1634 #define WTIMER_DTTIME_DTPRESC_DIV2 (_WTIMER_DTTIME_DTPRESC_DIV2 << 0) /**< Shifted mode DIV2 for WTIMER_DTTIME */
AnnaBridge 170:e95d10626187 1635 #define WTIMER_DTTIME_DTPRESC_DIV4 (_WTIMER_DTTIME_DTPRESC_DIV4 << 0) /**< Shifted mode DIV4 for WTIMER_DTTIME */
AnnaBridge 170:e95d10626187 1636 #define WTIMER_DTTIME_DTPRESC_DIV8 (_WTIMER_DTTIME_DTPRESC_DIV8 << 0) /**< Shifted mode DIV8 for WTIMER_DTTIME */
AnnaBridge 170:e95d10626187 1637 #define WTIMER_DTTIME_DTPRESC_DIV16 (_WTIMER_DTTIME_DTPRESC_DIV16 << 0) /**< Shifted mode DIV16 for WTIMER_DTTIME */
AnnaBridge 170:e95d10626187 1638 #define WTIMER_DTTIME_DTPRESC_DIV32 (_WTIMER_DTTIME_DTPRESC_DIV32 << 0) /**< Shifted mode DIV32 for WTIMER_DTTIME */
AnnaBridge 170:e95d10626187 1639 #define WTIMER_DTTIME_DTPRESC_DIV64 (_WTIMER_DTTIME_DTPRESC_DIV64 << 0) /**< Shifted mode DIV64 for WTIMER_DTTIME */
AnnaBridge 170:e95d10626187 1640 #define WTIMER_DTTIME_DTPRESC_DIV128 (_WTIMER_DTTIME_DTPRESC_DIV128 << 0) /**< Shifted mode DIV128 for WTIMER_DTTIME */
AnnaBridge 170:e95d10626187 1641 #define WTIMER_DTTIME_DTPRESC_DIV256 (_WTIMER_DTTIME_DTPRESC_DIV256 << 0) /**< Shifted mode DIV256 for WTIMER_DTTIME */
AnnaBridge 170:e95d10626187 1642 #define WTIMER_DTTIME_DTPRESC_DIV512 (_WTIMER_DTTIME_DTPRESC_DIV512 << 0) /**< Shifted mode DIV512 for WTIMER_DTTIME */
AnnaBridge 170:e95d10626187 1643 #define WTIMER_DTTIME_DTPRESC_DIV1024 (_WTIMER_DTTIME_DTPRESC_DIV1024 << 0) /**< Shifted mode DIV1024 for WTIMER_DTTIME */
AnnaBridge 170:e95d10626187 1644 #define _WTIMER_DTTIME_DTRISET_SHIFT 8 /**< Shift value for TIMER_DTRISET */
AnnaBridge 170:e95d10626187 1645 #define _WTIMER_DTTIME_DTRISET_MASK 0x3F00UL /**< Bit mask for TIMER_DTRISET */
AnnaBridge 170:e95d10626187 1646 #define _WTIMER_DTTIME_DTRISET_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */
AnnaBridge 170:e95d10626187 1647 #define WTIMER_DTTIME_DTRISET_DEFAULT (_WTIMER_DTTIME_DTRISET_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTTIME */
AnnaBridge 170:e95d10626187 1648 #define _WTIMER_DTTIME_DTFALLT_SHIFT 16 /**< Shift value for TIMER_DTFALLT */
AnnaBridge 170:e95d10626187 1649 #define _WTIMER_DTTIME_DTFALLT_MASK 0x3F0000UL /**< Bit mask for TIMER_DTFALLT */
AnnaBridge 170:e95d10626187 1650 #define _WTIMER_DTTIME_DTFALLT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */
AnnaBridge 170:e95d10626187 1651 #define WTIMER_DTTIME_DTFALLT_DEFAULT (_WTIMER_DTTIME_DTFALLT_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTTIME */
AnnaBridge 170:e95d10626187 1652
AnnaBridge 170:e95d10626187 1653 /* Bit fields for WTIMER DTFC */
AnnaBridge 170:e95d10626187 1654 #define _WTIMER_DTFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFC */
AnnaBridge 170:e95d10626187 1655 #define _WTIMER_DTFC_MASK 0x0F031F1FUL /**< Mask for WTIMER_DTFC */
AnnaBridge 170:e95d10626187 1656 #define _WTIMER_DTFC_DTPRS0FSEL_SHIFT 0 /**< Shift value for TIMER_DTPRS0FSEL */
AnnaBridge 170:e95d10626187 1657 #define _WTIMER_DTFC_DTPRS0FSEL_MASK 0x1FUL /**< Bit mask for TIMER_DTPRS0FSEL */
AnnaBridge 170:e95d10626187 1658 #define _WTIMER_DTFC_DTPRS0FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */
AnnaBridge 170:e95d10626187 1659 #define _WTIMER_DTFC_DTPRS0FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */
AnnaBridge 170:e95d10626187 1660 #define _WTIMER_DTFC_DTPRS0FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */
AnnaBridge 170:e95d10626187 1661 #define _WTIMER_DTFC_DTPRS0FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */
AnnaBridge 170:e95d10626187 1662 #define _WTIMER_DTFC_DTPRS0FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */
AnnaBridge 170:e95d10626187 1663 #define _WTIMER_DTFC_DTPRS0FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */
AnnaBridge 170:e95d10626187 1664 #define _WTIMER_DTFC_DTPRS0FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */
AnnaBridge 170:e95d10626187 1665 #define _WTIMER_DTFC_DTPRS0FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */
AnnaBridge 170:e95d10626187 1666 #define _WTIMER_DTFC_DTPRS0FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */
AnnaBridge 170:e95d10626187 1667 #define _WTIMER_DTFC_DTPRS0FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */
AnnaBridge 170:e95d10626187 1668 #define _WTIMER_DTFC_DTPRS0FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */
AnnaBridge 170:e95d10626187 1669 #define _WTIMER_DTFC_DTPRS0FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */
AnnaBridge 170:e95d10626187 1670 #define _WTIMER_DTFC_DTPRS0FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */
AnnaBridge 170:e95d10626187 1671 #define _WTIMER_DTFC_DTPRS0FSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_DTFC */
AnnaBridge 170:e95d10626187 1672 #define _WTIMER_DTFC_DTPRS0FSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_DTFC */
AnnaBridge 170:e95d10626187 1673 #define _WTIMER_DTFC_DTPRS0FSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_DTFC */
AnnaBridge 170:e95d10626187 1674 #define _WTIMER_DTFC_DTPRS0FSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_DTFC */
AnnaBridge 170:e95d10626187 1675 #define _WTIMER_DTFC_DTPRS0FSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_DTFC */
AnnaBridge 170:e95d10626187 1676 #define _WTIMER_DTFC_DTPRS0FSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_DTFC */
AnnaBridge 170:e95d10626187 1677 #define _WTIMER_DTFC_DTPRS0FSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_DTFC */
AnnaBridge 170:e95d10626187 1678 #define _WTIMER_DTFC_DTPRS0FSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_DTFC */
AnnaBridge 170:e95d10626187 1679 #define _WTIMER_DTFC_DTPRS0FSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_DTFC */
AnnaBridge 170:e95d10626187 1680 #define _WTIMER_DTFC_DTPRS0FSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_DTFC */
AnnaBridge 170:e95d10626187 1681 #define _WTIMER_DTFC_DTPRS0FSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_DTFC */
AnnaBridge 170:e95d10626187 1682 #define _WTIMER_DTFC_DTPRS0FSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_DTFC */
AnnaBridge 170:e95d10626187 1683 #define WTIMER_DTFC_DTPRS0FSEL_DEFAULT (_WTIMER_DTFC_DTPRS0FSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFC */
AnnaBridge 170:e95d10626187 1684 #define WTIMER_DTFC_DTPRS0FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for WTIMER_DTFC */
AnnaBridge 170:e95d10626187 1685 #define WTIMER_DTFC_DTPRS0FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for WTIMER_DTFC */
AnnaBridge 170:e95d10626187 1686 #define WTIMER_DTFC_DTPRS0FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for WTIMER_DTFC */
AnnaBridge 170:e95d10626187 1687 #define WTIMER_DTFC_DTPRS0FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for WTIMER_DTFC */
AnnaBridge 170:e95d10626187 1688 #define WTIMER_DTFC_DTPRS0FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for WTIMER_DTFC */
AnnaBridge 170:e95d10626187 1689 #define WTIMER_DTFC_DTPRS0FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for WTIMER_DTFC */
AnnaBridge 170:e95d10626187 1690 #define WTIMER_DTFC_DTPRS0FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for WTIMER_DTFC */
AnnaBridge 170:e95d10626187 1691 #define WTIMER_DTFC_DTPRS0FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for WTIMER_DTFC */
AnnaBridge 170:e95d10626187 1692 #define WTIMER_DTFC_DTPRS0FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for WTIMER_DTFC */
AnnaBridge 170:e95d10626187 1693 #define WTIMER_DTFC_DTPRS0FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for WTIMER_DTFC */
AnnaBridge 170:e95d10626187 1694 #define WTIMER_DTFC_DTPRS0FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for WTIMER_DTFC */
AnnaBridge 170:e95d10626187 1695 #define WTIMER_DTFC_DTPRS0FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for WTIMER_DTFC */
AnnaBridge 170:e95d10626187 1696 #define WTIMER_DTFC_DTPRS0FSEL_PRSCH12 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH12 << 0) /**< Shifted mode PRSCH12 for WTIMER_DTFC */
AnnaBridge 170:e95d10626187 1697 #define WTIMER_DTFC_DTPRS0FSEL_PRSCH13 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH13 << 0) /**< Shifted mode PRSCH13 for WTIMER_DTFC */
AnnaBridge 170:e95d10626187 1698 #define WTIMER_DTFC_DTPRS0FSEL_PRSCH14 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH14 << 0) /**< Shifted mode PRSCH14 for WTIMER_DTFC */
AnnaBridge 170:e95d10626187 1699 #define WTIMER_DTFC_DTPRS0FSEL_PRSCH15 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH15 << 0) /**< Shifted mode PRSCH15 for WTIMER_DTFC */
AnnaBridge 170:e95d10626187 1700 #define WTIMER_DTFC_DTPRS0FSEL_PRSCH16 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH16 << 0) /**< Shifted mode PRSCH16 for WTIMER_DTFC */
AnnaBridge 170:e95d10626187 1701 #define WTIMER_DTFC_DTPRS0FSEL_PRSCH17 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH17 << 0) /**< Shifted mode PRSCH17 for WTIMER_DTFC */
AnnaBridge 170:e95d10626187 1702 #define WTIMER_DTFC_DTPRS0FSEL_PRSCH18 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH18 << 0) /**< Shifted mode PRSCH18 for WTIMER_DTFC */
AnnaBridge 170:e95d10626187 1703 #define WTIMER_DTFC_DTPRS0FSEL_PRSCH19 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH19 << 0) /**< Shifted mode PRSCH19 for WTIMER_DTFC */
AnnaBridge 170:e95d10626187 1704 #define WTIMER_DTFC_DTPRS0FSEL_PRSCH20 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH20 << 0) /**< Shifted mode PRSCH20 for WTIMER_DTFC */
AnnaBridge 170:e95d10626187 1705 #define WTIMER_DTFC_DTPRS0FSEL_PRSCH21 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH21 << 0) /**< Shifted mode PRSCH21 for WTIMER_DTFC */
AnnaBridge 170:e95d10626187 1706 #define WTIMER_DTFC_DTPRS0FSEL_PRSCH22 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH22 << 0) /**< Shifted mode PRSCH22 for WTIMER_DTFC */
AnnaBridge 170:e95d10626187 1707 #define WTIMER_DTFC_DTPRS0FSEL_PRSCH23 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH23 << 0) /**< Shifted mode PRSCH23 for WTIMER_DTFC */
AnnaBridge 170:e95d10626187 1708 #define _WTIMER_DTFC_DTPRS1FSEL_SHIFT 8 /**< Shift value for TIMER_DTPRS1FSEL */
AnnaBridge 170:e95d10626187 1709 #define _WTIMER_DTFC_DTPRS1FSEL_MASK 0x1F00UL /**< Bit mask for TIMER_DTPRS1FSEL */
AnnaBridge 170:e95d10626187 1710 #define _WTIMER_DTFC_DTPRS1FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */
AnnaBridge 170:e95d10626187 1711 #define _WTIMER_DTFC_DTPRS1FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */
AnnaBridge 170:e95d10626187 1712 #define _WTIMER_DTFC_DTPRS1FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */
AnnaBridge 170:e95d10626187 1713 #define _WTIMER_DTFC_DTPRS1FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */
AnnaBridge 170:e95d10626187 1714 #define _WTIMER_DTFC_DTPRS1FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */
AnnaBridge 170:e95d10626187 1715 #define _WTIMER_DTFC_DTPRS1FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */
AnnaBridge 170:e95d10626187 1716 #define _WTIMER_DTFC_DTPRS1FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */
AnnaBridge 170:e95d10626187 1717 #define _WTIMER_DTFC_DTPRS1FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */
AnnaBridge 170:e95d10626187 1718 #define _WTIMER_DTFC_DTPRS1FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */
AnnaBridge 170:e95d10626187 1719 #define _WTIMER_DTFC_DTPRS1FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */
AnnaBridge 170:e95d10626187 1720 #define _WTIMER_DTFC_DTPRS1FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */
AnnaBridge 170:e95d10626187 1721 #define _WTIMER_DTFC_DTPRS1FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */
AnnaBridge 170:e95d10626187 1722 #define _WTIMER_DTFC_DTPRS1FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */
AnnaBridge 170:e95d10626187 1723 #define _WTIMER_DTFC_DTPRS1FSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_DTFC */
AnnaBridge 170:e95d10626187 1724 #define _WTIMER_DTFC_DTPRS1FSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_DTFC */
AnnaBridge 170:e95d10626187 1725 #define _WTIMER_DTFC_DTPRS1FSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_DTFC */
AnnaBridge 170:e95d10626187 1726 #define _WTIMER_DTFC_DTPRS1FSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_DTFC */
AnnaBridge 170:e95d10626187 1727 #define _WTIMER_DTFC_DTPRS1FSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_DTFC */
AnnaBridge 170:e95d10626187 1728 #define _WTIMER_DTFC_DTPRS1FSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_DTFC */
AnnaBridge 170:e95d10626187 1729 #define _WTIMER_DTFC_DTPRS1FSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_DTFC */
AnnaBridge 170:e95d10626187 1730 #define _WTIMER_DTFC_DTPRS1FSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_DTFC */
AnnaBridge 170:e95d10626187 1731 #define _WTIMER_DTFC_DTPRS1FSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_DTFC */
AnnaBridge 170:e95d10626187 1732 #define _WTIMER_DTFC_DTPRS1FSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_DTFC */
AnnaBridge 170:e95d10626187 1733 #define _WTIMER_DTFC_DTPRS1FSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_DTFC */
AnnaBridge 170:e95d10626187 1734 #define _WTIMER_DTFC_DTPRS1FSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_DTFC */
AnnaBridge 170:e95d10626187 1735 #define WTIMER_DTFC_DTPRS1FSEL_DEFAULT (_WTIMER_DTFC_DTPRS1FSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTFC */
AnnaBridge 170:e95d10626187 1736 #define WTIMER_DTFC_DTPRS1FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH0 << 8) /**< Shifted mode PRSCH0 for WTIMER_DTFC */
AnnaBridge 170:e95d10626187 1737 #define WTIMER_DTFC_DTPRS1FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH1 << 8) /**< Shifted mode PRSCH1 for WTIMER_DTFC */
AnnaBridge 170:e95d10626187 1738 #define WTIMER_DTFC_DTPRS1FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH2 << 8) /**< Shifted mode PRSCH2 for WTIMER_DTFC */
AnnaBridge 170:e95d10626187 1739 #define WTIMER_DTFC_DTPRS1FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH3 << 8) /**< Shifted mode PRSCH3 for WTIMER_DTFC */
AnnaBridge 170:e95d10626187 1740 #define WTIMER_DTFC_DTPRS1FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH4 << 8) /**< Shifted mode PRSCH4 for WTIMER_DTFC */
AnnaBridge 170:e95d10626187 1741 #define WTIMER_DTFC_DTPRS1FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH5 << 8) /**< Shifted mode PRSCH5 for WTIMER_DTFC */
AnnaBridge 170:e95d10626187 1742 #define WTIMER_DTFC_DTPRS1FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH6 << 8) /**< Shifted mode PRSCH6 for WTIMER_DTFC */
AnnaBridge 170:e95d10626187 1743 #define WTIMER_DTFC_DTPRS1FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH7 << 8) /**< Shifted mode PRSCH7 for WTIMER_DTFC */
AnnaBridge 170:e95d10626187 1744 #define WTIMER_DTFC_DTPRS1FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH8 << 8) /**< Shifted mode PRSCH8 for WTIMER_DTFC */
AnnaBridge 170:e95d10626187 1745 #define WTIMER_DTFC_DTPRS1FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH9 << 8) /**< Shifted mode PRSCH9 for WTIMER_DTFC */
AnnaBridge 170:e95d10626187 1746 #define WTIMER_DTFC_DTPRS1FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH10 << 8) /**< Shifted mode PRSCH10 for WTIMER_DTFC */
AnnaBridge 170:e95d10626187 1747 #define WTIMER_DTFC_DTPRS1FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH11 << 8) /**< Shifted mode PRSCH11 for WTIMER_DTFC */
AnnaBridge 170:e95d10626187 1748 #define WTIMER_DTFC_DTPRS1FSEL_PRSCH12 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH12 << 8) /**< Shifted mode PRSCH12 for WTIMER_DTFC */
AnnaBridge 170:e95d10626187 1749 #define WTIMER_DTFC_DTPRS1FSEL_PRSCH13 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH13 << 8) /**< Shifted mode PRSCH13 for WTIMER_DTFC */
AnnaBridge 170:e95d10626187 1750 #define WTIMER_DTFC_DTPRS1FSEL_PRSCH14 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH14 << 8) /**< Shifted mode PRSCH14 for WTIMER_DTFC */
AnnaBridge 170:e95d10626187 1751 #define WTIMER_DTFC_DTPRS1FSEL_PRSCH15 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH15 << 8) /**< Shifted mode PRSCH15 for WTIMER_DTFC */
AnnaBridge 170:e95d10626187 1752 #define WTIMER_DTFC_DTPRS1FSEL_PRSCH16 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH16 << 8) /**< Shifted mode PRSCH16 for WTIMER_DTFC */
AnnaBridge 170:e95d10626187 1753 #define WTIMER_DTFC_DTPRS1FSEL_PRSCH17 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH17 << 8) /**< Shifted mode PRSCH17 for WTIMER_DTFC */
AnnaBridge 170:e95d10626187 1754 #define WTIMER_DTFC_DTPRS1FSEL_PRSCH18 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH18 << 8) /**< Shifted mode PRSCH18 for WTIMER_DTFC */
AnnaBridge 170:e95d10626187 1755 #define WTIMER_DTFC_DTPRS1FSEL_PRSCH19 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH19 << 8) /**< Shifted mode PRSCH19 for WTIMER_DTFC */
AnnaBridge 170:e95d10626187 1756 #define WTIMER_DTFC_DTPRS1FSEL_PRSCH20 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH20 << 8) /**< Shifted mode PRSCH20 for WTIMER_DTFC */
AnnaBridge 170:e95d10626187 1757 #define WTIMER_DTFC_DTPRS1FSEL_PRSCH21 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH21 << 8) /**< Shifted mode PRSCH21 for WTIMER_DTFC */
AnnaBridge 170:e95d10626187 1758 #define WTIMER_DTFC_DTPRS1FSEL_PRSCH22 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH22 << 8) /**< Shifted mode PRSCH22 for WTIMER_DTFC */
AnnaBridge 170:e95d10626187 1759 #define WTIMER_DTFC_DTPRS1FSEL_PRSCH23 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH23 << 8) /**< Shifted mode PRSCH23 for WTIMER_DTFC */
AnnaBridge 170:e95d10626187 1760 #define _WTIMER_DTFC_DTFA_SHIFT 16 /**< Shift value for TIMER_DTFA */
AnnaBridge 170:e95d10626187 1761 #define _WTIMER_DTFC_DTFA_MASK 0x30000UL /**< Bit mask for TIMER_DTFA */
AnnaBridge 170:e95d10626187 1762 #define _WTIMER_DTFC_DTFA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */
AnnaBridge 170:e95d10626187 1763 #define _WTIMER_DTFC_DTFA_NONE 0x00000000UL /**< Mode NONE for WTIMER_DTFC */
AnnaBridge 170:e95d10626187 1764 #define _WTIMER_DTFC_DTFA_INACTIVE 0x00000001UL /**< Mode INACTIVE for WTIMER_DTFC */
AnnaBridge 170:e95d10626187 1765 #define _WTIMER_DTFC_DTFA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_DTFC */
AnnaBridge 170:e95d10626187 1766 #define _WTIMER_DTFC_DTFA_TRISTATE 0x00000003UL /**< Mode TRISTATE for WTIMER_DTFC */
AnnaBridge 170:e95d10626187 1767 #define WTIMER_DTFC_DTFA_DEFAULT (_WTIMER_DTFC_DTFA_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTFC */
AnnaBridge 170:e95d10626187 1768 #define WTIMER_DTFC_DTFA_NONE (_WTIMER_DTFC_DTFA_NONE << 16) /**< Shifted mode NONE for WTIMER_DTFC */
AnnaBridge 170:e95d10626187 1769 #define WTIMER_DTFC_DTFA_INACTIVE (_WTIMER_DTFC_DTFA_INACTIVE << 16) /**< Shifted mode INACTIVE for WTIMER_DTFC */
AnnaBridge 170:e95d10626187 1770 #define WTIMER_DTFC_DTFA_CLEAR (_WTIMER_DTFC_DTFA_CLEAR << 16) /**< Shifted mode CLEAR for WTIMER_DTFC */
AnnaBridge 170:e95d10626187 1771 #define WTIMER_DTFC_DTFA_TRISTATE (_WTIMER_DTFC_DTFA_TRISTATE << 16) /**< Shifted mode TRISTATE for WTIMER_DTFC */
AnnaBridge 170:e95d10626187 1772 #define WTIMER_DTFC_DTPRS0FEN (0x1UL << 24) /**< DTI PRS 0 Fault Enable */
AnnaBridge 170:e95d10626187 1773 #define _WTIMER_DTFC_DTPRS0FEN_SHIFT 24 /**< Shift value for TIMER_DTPRS0FEN */
AnnaBridge 170:e95d10626187 1774 #define _WTIMER_DTFC_DTPRS0FEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRS0FEN */
AnnaBridge 170:e95d10626187 1775 #define _WTIMER_DTFC_DTPRS0FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */
AnnaBridge 170:e95d10626187 1776 #define WTIMER_DTFC_DTPRS0FEN_DEFAULT (_WTIMER_DTFC_DTPRS0FEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTFC */
AnnaBridge 170:e95d10626187 1777 #define WTIMER_DTFC_DTPRS1FEN (0x1UL << 25) /**< DTI PRS 1 Fault Enable */
AnnaBridge 170:e95d10626187 1778 #define _WTIMER_DTFC_DTPRS1FEN_SHIFT 25 /**< Shift value for TIMER_DTPRS1FEN */
AnnaBridge 170:e95d10626187 1779 #define _WTIMER_DTFC_DTPRS1FEN_MASK 0x2000000UL /**< Bit mask for TIMER_DTPRS1FEN */
AnnaBridge 170:e95d10626187 1780 #define _WTIMER_DTFC_DTPRS1FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */
AnnaBridge 170:e95d10626187 1781 #define WTIMER_DTFC_DTPRS1FEN_DEFAULT (_WTIMER_DTFC_DTPRS1FEN_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_DTFC */
AnnaBridge 170:e95d10626187 1782 #define WTIMER_DTFC_DTDBGFEN (0x1UL << 26) /**< DTI Debugger Fault Enable */
AnnaBridge 170:e95d10626187 1783 #define _WTIMER_DTFC_DTDBGFEN_SHIFT 26 /**< Shift value for TIMER_DTDBGFEN */
AnnaBridge 170:e95d10626187 1784 #define _WTIMER_DTFC_DTDBGFEN_MASK 0x4000000UL /**< Bit mask for TIMER_DTDBGFEN */
AnnaBridge 170:e95d10626187 1785 #define _WTIMER_DTFC_DTDBGFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */
AnnaBridge 170:e95d10626187 1786 #define WTIMER_DTFC_DTDBGFEN_DEFAULT (_WTIMER_DTFC_DTDBGFEN_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_DTFC */
AnnaBridge 170:e95d10626187 1787 #define WTIMER_DTFC_DTLOCKUPFEN (0x1UL << 27) /**< DTI Lockup Fault Enable */
AnnaBridge 170:e95d10626187 1788 #define _WTIMER_DTFC_DTLOCKUPFEN_SHIFT 27 /**< Shift value for TIMER_DTLOCKUPFEN */
AnnaBridge 170:e95d10626187 1789 #define _WTIMER_DTFC_DTLOCKUPFEN_MASK 0x8000000UL /**< Bit mask for TIMER_DTLOCKUPFEN */
AnnaBridge 170:e95d10626187 1790 #define _WTIMER_DTFC_DTLOCKUPFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */
AnnaBridge 170:e95d10626187 1791 #define WTIMER_DTFC_DTLOCKUPFEN_DEFAULT (_WTIMER_DTFC_DTLOCKUPFEN_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_DTFC */
AnnaBridge 170:e95d10626187 1792
AnnaBridge 170:e95d10626187 1793 /* Bit fields for WTIMER DTOGEN */
AnnaBridge 170:e95d10626187 1794 #define _WTIMER_DTOGEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTOGEN */
AnnaBridge 170:e95d10626187 1795 #define _WTIMER_DTOGEN_MASK 0x0000003FUL /**< Mask for WTIMER_DTOGEN */
AnnaBridge 170:e95d10626187 1796 #define WTIMER_DTOGEN_DTOGCC0EN (0x1UL << 0) /**< DTI CC0 Output Generation Enable */
AnnaBridge 170:e95d10626187 1797 #define _WTIMER_DTOGEN_DTOGCC0EN_SHIFT 0 /**< Shift value for TIMER_DTOGCC0EN */
AnnaBridge 170:e95d10626187 1798 #define _WTIMER_DTOGEN_DTOGCC0EN_MASK 0x1UL /**< Bit mask for TIMER_DTOGCC0EN */
AnnaBridge 170:e95d10626187 1799 #define _WTIMER_DTOGEN_DTOGCC0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */
AnnaBridge 170:e95d10626187 1800 #define WTIMER_DTOGEN_DTOGCC0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC0EN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */
AnnaBridge 170:e95d10626187 1801 #define WTIMER_DTOGEN_DTOGCC1EN (0x1UL << 1) /**< DTI CC1 Output Generation Enable */
AnnaBridge 170:e95d10626187 1802 #define _WTIMER_DTOGEN_DTOGCC1EN_SHIFT 1 /**< Shift value for TIMER_DTOGCC1EN */
AnnaBridge 170:e95d10626187 1803 #define _WTIMER_DTOGEN_DTOGCC1EN_MASK 0x2UL /**< Bit mask for TIMER_DTOGCC1EN */
AnnaBridge 170:e95d10626187 1804 #define _WTIMER_DTOGEN_DTOGCC1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */
AnnaBridge 170:e95d10626187 1805 #define WTIMER_DTOGEN_DTOGCC1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC1EN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */
AnnaBridge 170:e95d10626187 1806 #define WTIMER_DTOGEN_DTOGCC2EN (0x1UL << 2) /**< DTI CC2 Output Generation Enable */
AnnaBridge 170:e95d10626187 1807 #define _WTIMER_DTOGEN_DTOGCC2EN_SHIFT 2 /**< Shift value for TIMER_DTOGCC2EN */
AnnaBridge 170:e95d10626187 1808 #define _WTIMER_DTOGEN_DTOGCC2EN_MASK 0x4UL /**< Bit mask for TIMER_DTOGCC2EN */
AnnaBridge 170:e95d10626187 1809 #define _WTIMER_DTOGEN_DTOGCC2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */
AnnaBridge 170:e95d10626187 1810 #define WTIMER_DTOGEN_DTOGCC2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC2EN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */
AnnaBridge 170:e95d10626187 1811 #define WTIMER_DTOGEN_DTOGCDTI0EN (0x1UL << 3) /**< DTI CDTI0 Output Generation Enable */
AnnaBridge 170:e95d10626187 1812 #define _WTIMER_DTOGEN_DTOGCDTI0EN_SHIFT 3 /**< Shift value for TIMER_DTOGCDTI0EN */
AnnaBridge 170:e95d10626187 1813 #define _WTIMER_DTOGEN_DTOGCDTI0EN_MASK 0x8UL /**< Bit mask for TIMER_DTOGCDTI0EN */
AnnaBridge 170:e95d10626187 1814 #define _WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */
AnnaBridge 170:e95d10626187 1815 #define WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */
AnnaBridge 170:e95d10626187 1816 #define WTIMER_DTOGEN_DTOGCDTI1EN (0x1UL << 4) /**< DTI CDTI1 Output Generation Enable */
AnnaBridge 170:e95d10626187 1817 #define _WTIMER_DTOGEN_DTOGCDTI1EN_SHIFT 4 /**< Shift value for TIMER_DTOGCDTI1EN */
AnnaBridge 170:e95d10626187 1818 #define _WTIMER_DTOGEN_DTOGCDTI1EN_MASK 0x10UL /**< Bit mask for TIMER_DTOGCDTI1EN */
AnnaBridge 170:e95d10626187 1819 #define _WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */
AnnaBridge 170:e95d10626187 1820 #define WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */
AnnaBridge 170:e95d10626187 1821 #define WTIMER_DTOGEN_DTOGCDTI2EN (0x1UL << 5) /**< DTI CDTI2 Output Generation Enable */
AnnaBridge 170:e95d10626187 1822 #define _WTIMER_DTOGEN_DTOGCDTI2EN_SHIFT 5 /**< Shift value for TIMER_DTOGCDTI2EN */
AnnaBridge 170:e95d10626187 1823 #define _WTIMER_DTOGEN_DTOGCDTI2EN_MASK 0x20UL /**< Bit mask for TIMER_DTOGCDTI2EN */
AnnaBridge 170:e95d10626187 1824 #define _WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */
AnnaBridge 170:e95d10626187 1825 #define WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */
AnnaBridge 170:e95d10626187 1826
AnnaBridge 170:e95d10626187 1827 /* Bit fields for WTIMER DTFAULT */
AnnaBridge 170:e95d10626187 1828 #define _WTIMER_DTFAULT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULT */
AnnaBridge 170:e95d10626187 1829 #define _WTIMER_DTFAULT_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULT */
AnnaBridge 170:e95d10626187 1830 #define WTIMER_DTFAULT_DTPRS0F (0x1UL << 0) /**< DTI PRS 0 Fault */
AnnaBridge 170:e95d10626187 1831 #define _WTIMER_DTFAULT_DTPRS0F_SHIFT 0 /**< Shift value for TIMER_DTPRS0F */
AnnaBridge 170:e95d10626187 1832 #define _WTIMER_DTFAULT_DTPRS0F_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0F */
AnnaBridge 170:e95d10626187 1833 #define _WTIMER_DTFAULT_DTPRS0F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */
AnnaBridge 170:e95d10626187 1834 #define WTIMER_DTFAULT_DTPRS0F_DEFAULT (_WTIMER_DTFAULT_DTPRS0F_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */
AnnaBridge 170:e95d10626187 1835 #define WTIMER_DTFAULT_DTPRS1F (0x1UL << 1) /**< DTI PRS 1 Fault */
AnnaBridge 170:e95d10626187 1836 #define _WTIMER_DTFAULT_DTPRS1F_SHIFT 1 /**< Shift value for TIMER_DTPRS1F */
AnnaBridge 170:e95d10626187 1837 #define _WTIMER_DTFAULT_DTPRS1F_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1F */
AnnaBridge 170:e95d10626187 1838 #define _WTIMER_DTFAULT_DTPRS1F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */
AnnaBridge 170:e95d10626187 1839 #define WTIMER_DTFAULT_DTPRS1F_DEFAULT (_WTIMER_DTFAULT_DTPRS1F_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */
AnnaBridge 170:e95d10626187 1840 #define WTIMER_DTFAULT_DTDBGF (0x1UL << 2) /**< DTI Debugger Fault */
AnnaBridge 170:e95d10626187 1841 #define _WTIMER_DTFAULT_DTDBGF_SHIFT 2 /**< Shift value for TIMER_DTDBGF */
AnnaBridge 170:e95d10626187 1842 #define _WTIMER_DTFAULT_DTDBGF_MASK 0x4UL /**< Bit mask for TIMER_DTDBGF */
AnnaBridge 170:e95d10626187 1843 #define _WTIMER_DTFAULT_DTDBGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */
AnnaBridge 170:e95d10626187 1844 #define WTIMER_DTFAULT_DTDBGF_DEFAULT (_WTIMER_DTFAULT_DTDBGF_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */
AnnaBridge 170:e95d10626187 1845 #define WTIMER_DTFAULT_DTLOCKUPF (0x1UL << 3) /**< DTI Lockup Fault */
AnnaBridge 170:e95d10626187 1846 #define _WTIMER_DTFAULT_DTLOCKUPF_SHIFT 3 /**< Shift value for TIMER_DTLOCKUPF */
AnnaBridge 170:e95d10626187 1847 #define _WTIMER_DTFAULT_DTLOCKUPF_MASK 0x8UL /**< Bit mask for TIMER_DTLOCKUPF */
AnnaBridge 170:e95d10626187 1848 #define _WTIMER_DTFAULT_DTLOCKUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */
AnnaBridge 170:e95d10626187 1849 #define WTIMER_DTFAULT_DTLOCKUPF_DEFAULT (_WTIMER_DTFAULT_DTLOCKUPF_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */
AnnaBridge 170:e95d10626187 1850
AnnaBridge 170:e95d10626187 1851 /* Bit fields for WTIMER DTFAULTC */
AnnaBridge 170:e95d10626187 1852 #define _WTIMER_DTFAULTC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULTC */
AnnaBridge 170:e95d10626187 1853 #define _WTIMER_DTFAULTC_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULTC */
AnnaBridge 170:e95d10626187 1854 #define WTIMER_DTFAULTC_DTPRS0FC (0x1UL << 0) /**< DTI PRS0 Fault Clear */
AnnaBridge 170:e95d10626187 1855 #define _WTIMER_DTFAULTC_DTPRS0FC_SHIFT 0 /**< Shift value for TIMER_DTPRS0FC */
AnnaBridge 170:e95d10626187 1856 #define _WTIMER_DTFAULTC_DTPRS0FC_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0FC */
AnnaBridge 170:e95d10626187 1857 #define _WTIMER_DTFAULTC_DTPRS0FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */
AnnaBridge 170:e95d10626187 1858 #define WTIMER_DTFAULTC_DTPRS0FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS0FC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */
AnnaBridge 170:e95d10626187 1859 #define WTIMER_DTFAULTC_DTPRS1FC (0x1UL << 1) /**< DTI PRS1 Fault Clear */
AnnaBridge 170:e95d10626187 1860 #define _WTIMER_DTFAULTC_DTPRS1FC_SHIFT 1 /**< Shift value for TIMER_DTPRS1FC */
AnnaBridge 170:e95d10626187 1861 #define _WTIMER_DTFAULTC_DTPRS1FC_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1FC */
AnnaBridge 170:e95d10626187 1862 #define _WTIMER_DTFAULTC_DTPRS1FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */
AnnaBridge 170:e95d10626187 1863 #define WTIMER_DTFAULTC_DTPRS1FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS1FC_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */
AnnaBridge 170:e95d10626187 1864 #define WTIMER_DTFAULTC_DTDBGFC (0x1UL << 2) /**< DTI Debugger Fault Clear */
AnnaBridge 170:e95d10626187 1865 #define _WTIMER_DTFAULTC_DTDBGFC_SHIFT 2 /**< Shift value for TIMER_DTDBGFC */
AnnaBridge 170:e95d10626187 1866 #define _WTIMER_DTFAULTC_DTDBGFC_MASK 0x4UL /**< Bit mask for TIMER_DTDBGFC */
AnnaBridge 170:e95d10626187 1867 #define _WTIMER_DTFAULTC_DTDBGFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */
AnnaBridge 170:e95d10626187 1868 #define WTIMER_DTFAULTC_DTDBGFC_DEFAULT (_WTIMER_DTFAULTC_DTDBGFC_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */
AnnaBridge 170:e95d10626187 1869 #define WTIMER_DTFAULTC_TLOCKUPFC (0x1UL << 3) /**< DTI Lockup Fault Clear */
AnnaBridge 170:e95d10626187 1870 #define _WTIMER_DTFAULTC_TLOCKUPFC_SHIFT 3 /**< Shift value for TIMER_TLOCKUPFC */
AnnaBridge 170:e95d10626187 1871 #define _WTIMER_DTFAULTC_TLOCKUPFC_MASK 0x8UL /**< Bit mask for TIMER_TLOCKUPFC */
AnnaBridge 170:e95d10626187 1872 #define _WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */
AnnaBridge 170:e95d10626187 1873 #define WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT (_WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */
AnnaBridge 170:e95d10626187 1874
AnnaBridge 170:e95d10626187 1875 /* Bit fields for WTIMER DTLOCK */
AnnaBridge 170:e95d10626187 1876 #define _WTIMER_DTLOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTLOCK */
AnnaBridge 170:e95d10626187 1877 #define _WTIMER_DTLOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_DTLOCK */
AnnaBridge 170:e95d10626187 1878 #define _WTIMER_DTLOCK_LOCKKEY_SHIFT 0 /**< Shift value for TIMER_LOCKKEY */
AnnaBridge 170:e95d10626187 1879 #define _WTIMER_DTLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_LOCKKEY */
AnnaBridge 170:e95d10626187 1880 #define _WTIMER_DTLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTLOCK */
AnnaBridge 170:e95d10626187 1881 #define _WTIMER_DTLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_DTLOCK */
AnnaBridge 170:e95d10626187 1882 #define _WTIMER_DTLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_DTLOCK */
AnnaBridge 170:e95d10626187 1883 #define _WTIMER_DTLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_DTLOCK */
AnnaBridge 170:e95d10626187 1884 #define _WTIMER_DTLOCK_LOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_DTLOCK */
AnnaBridge 170:e95d10626187 1885 #define WTIMER_DTLOCK_LOCKKEY_DEFAULT (_WTIMER_DTLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTLOCK */
AnnaBridge 170:e95d10626187 1886 #define WTIMER_DTLOCK_LOCKKEY_LOCK (_WTIMER_DTLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_DTLOCK */
AnnaBridge 170:e95d10626187 1887 #define WTIMER_DTLOCK_LOCKKEY_UNLOCKED (_WTIMER_DTLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_DTLOCK */
AnnaBridge 170:e95d10626187 1888 #define WTIMER_DTLOCK_LOCKKEY_LOCKED (_WTIMER_DTLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_DTLOCK */
AnnaBridge 170:e95d10626187 1889 #define WTIMER_DTLOCK_LOCKKEY_UNLOCK (_WTIMER_DTLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_DTLOCK */
AnnaBridge 170:e95d10626187 1890
AnnaBridge 170:e95d10626187 1891 /** @} */
AnnaBridge 170:e95d10626187 1892 /** @} End of group EFM32GG11B820F2048GL152_WTIMER */
AnnaBridge 170:e95d10626187 1893
AnnaBridge 170:e95d10626187 1894 #include "efm32gg11b_uart.h"
AnnaBridge 170:e95d10626187 1895
AnnaBridge 170:e95d10626187 1896 /**************************************************************************//**
AnnaBridge 170:e95d10626187 1897 * @defgroup EFM32GG11B820F2048GL152_UNLOCK Unlock Codes
AnnaBridge 170:e95d10626187 1898 * @{
AnnaBridge 170:e95d10626187 1899 *****************************************************************************/
AnnaBridge 170:e95d10626187 1900 #define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */
AnnaBridge 170:e95d10626187 1901 #define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */
AnnaBridge 170:e95d10626187 1902 #define RMU_UNLOCK_CODE 0xE084 /**< RMU unlock code */
AnnaBridge 170:e95d10626187 1903 #define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */
AnnaBridge 170:e95d10626187 1904 #define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */
AnnaBridge 170:e95d10626187 1905 #define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */
AnnaBridge 170:e95d10626187 1906 #define RTCC_UNLOCK_CODE 0xAEE8 /**< RTCC unlock code */
AnnaBridge 170:e95d10626187 1907
AnnaBridge 170:e95d10626187 1908 /** @} End of group EFM32GG11B820F2048GL152_UNLOCK */
AnnaBridge 170:e95d10626187 1909
AnnaBridge 170:e95d10626187 1910 /** @} End of group EFM32GG11B820F2048GL152_BitFields */
AnnaBridge 170:e95d10626187 1911
AnnaBridge 170:e95d10626187 1912 #include "efm32gg11b_af_ports.h"
AnnaBridge 170:e95d10626187 1913 #include "efm32gg11b_af_pins.h"
AnnaBridge 170:e95d10626187 1914
AnnaBridge 170:e95d10626187 1915 /** @} End of group EFM32GG11B820F2048GL152 */
AnnaBridge 170:e95d10626187 1916
AnnaBridge 170:e95d10626187 1917 /** @} End of group Parts */
AnnaBridge 170:e95d10626187 1918
AnnaBridge 170:e95d10626187 1919 #ifdef __cplusplus
AnnaBridge 170:e95d10626187 1920 }
AnnaBridge 170:e95d10626187 1921 #endif
AnnaBridge 170:e95d10626187 1922 #endif /* EFM32GG11B820F2048GL152_H */