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TARGET_ARM_MPS2_M3/TOOLCHAIN_ARM_STD/SMM_MPS2.h@171:3a7713b1edbc, 2018-11-08 (annotated)
- Committer:
- AnnaBridge
- Date:
- Thu Nov 08 11:45:42 2018 +0000
- Revision:
- 171:3a7713b1edbc
mbed library. Release version 164
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| AnnaBridge | 171:3a7713b1edbc | 1 | /* MPS2 CMSIS Library |
| AnnaBridge | 171:3a7713b1edbc | 2 | * |
| AnnaBridge | 171:3a7713b1edbc | 3 | * Copyright (c) 2006-2016 ARM Limited |
| AnnaBridge | 171:3a7713b1edbc | 4 | * All rights reserved. |
| AnnaBridge | 171:3a7713b1edbc | 5 | * |
| AnnaBridge | 171:3a7713b1edbc | 6 | * Redistribution and use in source and binary forms, with or without |
| AnnaBridge | 171:3a7713b1edbc | 7 | * modification, are permitted provided that the following conditions are met: |
| AnnaBridge | 171:3a7713b1edbc | 8 | * |
| AnnaBridge | 171:3a7713b1edbc | 9 | * 1. Redistributions of source code must retain the above copyright notice, |
| AnnaBridge | 171:3a7713b1edbc | 10 | * this list of conditions and the following disclaimer. |
| AnnaBridge | 171:3a7713b1edbc | 11 | * |
| AnnaBridge | 171:3a7713b1edbc | 12 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| AnnaBridge | 171:3a7713b1edbc | 13 | * this list of conditions and the following disclaimer in the documentation |
| AnnaBridge | 171:3a7713b1edbc | 14 | * and/or other materials provided with the distribution. |
| AnnaBridge | 171:3a7713b1edbc | 15 | * |
| AnnaBridge | 171:3a7713b1edbc | 16 | * 3. Neither the name of the copyright holder nor the names of its contributors |
| AnnaBridge | 171:3a7713b1edbc | 17 | * may be used to endorse or promote products derived from this software without |
| AnnaBridge | 171:3a7713b1edbc | 18 | * specific prior written permission. |
| AnnaBridge | 171:3a7713b1edbc | 19 | * |
| AnnaBridge | 171:3a7713b1edbc | 20 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| AnnaBridge | 171:3a7713b1edbc | 21 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| AnnaBridge | 171:3a7713b1edbc | 22 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| AnnaBridge | 171:3a7713b1edbc | 23 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE |
| AnnaBridge | 171:3a7713b1edbc | 24 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| AnnaBridge | 171:3a7713b1edbc | 25 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| AnnaBridge | 171:3a7713b1edbc | 26 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| AnnaBridge | 171:3a7713b1edbc | 27 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| AnnaBridge | 171:3a7713b1edbc | 28 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| AnnaBridge | 171:3a7713b1edbc | 29 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| AnnaBridge | 171:3a7713b1edbc | 30 | * POSSIBILITY OF SUCH DAMAGE. |
| AnnaBridge | 171:3a7713b1edbc | 31 | ******************************************************************************* |
| AnnaBridge | 171:3a7713b1edbc | 32 | * File: smm_mps2.h |
| AnnaBridge | 171:3a7713b1edbc | 33 | * Release: Version 1.1 |
| AnnaBridge | 171:3a7713b1edbc | 34 | *******************************************************************************/ |
| AnnaBridge | 171:3a7713b1edbc | 35 | |
| AnnaBridge | 171:3a7713b1edbc | 36 | #ifndef __SMM_MPS2_H |
| AnnaBridge | 171:3a7713b1edbc | 37 | #define __SMM_MPS2_H |
| AnnaBridge | 171:3a7713b1edbc | 38 | |
| AnnaBridge | 171:3a7713b1edbc | 39 | #include "peripherallink.h" /* device specific header file */ |
| AnnaBridge | 171:3a7713b1edbc | 40 | |
| AnnaBridge | 171:3a7713b1edbc | 41 | #if defined ( __CC_ARM ) |
| AnnaBridge | 171:3a7713b1edbc | 42 | #pragma anon_unions |
| AnnaBridge | 171:3a7713b1edbc | 43 | #endif |
| AnnaBridge | 171:3a7713b1edbc | 44 | |
| AnnaBridge | 171:3a7713b1edbc | 45 | /******************************************************************************/ |
| AnnaBridge | 171:3a7713b1edbc | 46 | /* FPGA System Register declaration */ |
| AnnaBridge | 171:3a7713b1edbc | 47 | /******************************************************************************/ |
| AnnaBridge | 171:3a7713b1edbc | 48 | |
| AnnaBridge | 171:3a7713b1edbc | 49 | typedef struct |
| AnnaBridge | 171:3a7713b1edbc | 50 | { |
| AnnaBridge | 171:3a7713b1edbc | 51 | __IO uint32_t LED; // Offset: 0x000 (R/W) LED connections |
| AnnaBridge | 171:3a7713b1edbc | 52 | // [31:2] : Reserved |
| AnnaBridge | 171:3a7713b1edbc | 53 | // [1:0] : LEDs |
| AnnaBridge | 171:3a7713b1edbc | 54 | uint32_t RESERVED1[1]; |
| AnnaBridge | 171:3a7713b1edbc | 55 | __IO uint32_t BUTTON; // Offset: 0x008 (R/W) Buttons |
| AnnaBridge | 171:3a7713b1edbc | 56 | // [31:2] : Reserved |
| AnnaBridge | 171:3a7713b1edbc | 57 | // [1:0] : Buttons |
| AnnaBridge | 171:3a7713b1edbc | 58 | uint32_t RESERVED2[1]; |
| AnnaBridge | 171:3a7713b1edbc | 59 | __IO uint32_t CLK1HZ; // Offset: 0x010 (R/W) 1Hz up counter |
| AnnaBridge | 171:3a7713b1edbc | 60 | __IO uint32_t CLK100HZ; // Offset: 0x014 (R/W) 100Hz up counter |
| AnnaBridge | 171:3a7713b1edbc | 61 | __IO uint32_t COUNTER; // Offset: 0x018 (R/W) Cycle Up Counter |
| AnnaBridge | 171:3a7713b1edbc | 62 | // Increments when 32-bit prescale counter reach zero |
| AnnaBridge | 171:3a7713b1edbc | 63 | uint32_t RESERVED3[1]; |
| AnnaBridge | 171:3a7713b1edbc | 64 | __IO uint32_t PRESCALE; // Offset: 0x020 (R/W) Prescaler |
| AnnaBridge | 171:3a7713b1edbc | 65 | // Bit[31:0] : reload value for prescale counter |
| AnnaBridge | 171:3a7713b1edbc | 66 | __IO uint32_t PSCNTR; // Offset: 0x024 (R/W) 32-bit Prescale counter |
| AnnaBridge | 171:3a7713b1edbc | 67 | // current value of the pre-scaler counter |
| AnnaBridge | 171:3a7713b1edbc | 68 | // The Cycle Up Counter increment when the prescale down counter reach 0 |
| AnnaBridge | 171:3a7713b1edbc | 69 | // The pre-scaler counter is reloaded with PRESCALE after reaching 0. |
| AnnaBridge | 171:3a7713b1edbc | 70 | uint32_t RESERVED4[9]; |
| AnnaBridge | 171:3a7713b1edbc | 71 | __IO uint32_t MISC; // Offset: 0x04C (R/W) Misc control */ |
| AnnaBridge | 171:3a7713b1edbc | 72 | // [31:10] : Reserved |
| AnnaBridge | 171:3a7713b1edbc | 73 | // [9] : SHIELD_1_SPI_nCS |
| AnnaBridge | 171:3a7713b1edbc | 74 | // [8] : SHIELD_0_SPI_nCS |
| AnnaBridge | 171:3a7713b1edbc | 75 | // [7] : ADC_SPI_nCS |
| AnnaBridge | 171:3a7713b1edbc | 76 | // [6] : CLCD_BL_CTRL |
| AnnaBridge | 171:3a7713b1edbc | 77 | // [5] : CLCD_RD |
| AnnaBridge | 171:3a7713b1edbc | 78 | // [4] : CLCD_RS |
| AnnaBridge | 171:3a7713b1edbc | 79 | // [3] : CLCD_RESET |
| AnnaBridge | 171:3a7713b1edbc | 80 | // [2] : RESERVED |
| AnnaBridge | 171:3a7713b1edbc | 81 | // [1] : SPI_nSS |
| AnnaBridge | 171:3a7713b1edbc | 82 | // [0] : CLCD_CS |
| AnnaBridge | 171:3a7713b1edbc | 83 | } MPS2_FPGAIO_TypeDef; |
| AnnaBridge | 171:3a7713b1edbc | 84 | |
| AnnaBridge | 171:3a7713b1edbc | 85 | // MISC register bit definitions |
| AnnaBridge | 171:3a7713b1edbc | 86 | |
| AnnaBridge | 171:3a7713b1edbc | 87 | #define CLCD_CS_Pos 0 |
| AnnaBridge | 171:3a7713b1edbc | 88 | #define CLCD_CS_Msk (1UL<<CLCD_CS_Pos) |
| AnnaBridge | 171:3a7713b1edbc | 89 | #define SPI_nSS_Pos 1 |
| AnnaBridge | 171:3a7713b1edbc | 90 | #define SPI_nSS_Msk (1UL<<SPI_nSS_Pos) |
| AnnaBridge | 171:3a7713b1edbc | 91 | #define CLCD_RESET_Pos 3 |
| AnnaBridge | 171:3a7713b1edbc | 92 | #define CLCD_RESET_Msk (1UL<<CLCD_RESET_Pos) |
| AnnaBridge | 171:3a7713b1edbc | 93 | #define CLCD_RS_Pos 4 |
| AnnaBridge | 171:3a7713b1edbc | 94 | #define CLCD_RS_Msk (1UL<<CLCD_RS_Pos) |
| AnnaBridge | 171:3a7713b1edbc | 95 | #define CLCD_RD_Pos 5 |
| AnnaBridge | 171:3a7713b1edbc | 96 | #define CLCD_RD_Msk (1UL<<CLCD_RD_Pos) |
| AnnaBridge | 171:3a7713b1edbc | 97 | #define CLCD_BL_Pos 6 |
| AnnaBridge | 171:3a7713b1edbc | 98 | #define CLCD_BL_Msk (1UL<<CLCD_BL_Pos) |
| AnnaBridge | 171:3a7713b1edbc | 99 | #define ADC_nCS_Pos 7 |
| AnnaBridge | 171:3a7713b1edbc | 100 | #define ADC_nCS_Msk (1UL<<ADC_nCS_Pos) |
| AnnaBridge | 171:3a7713b1edbc | 101 | #define SHIELD_0_nCS_Pos 8 |
| AnnaBridge | 171:3a7713b1edbc | 102 | #define SHIELD_0_nCS_Msk (1UL<<SHIELD_0_nCS_Pos) |
| AnnaBridge | 171:3a7713b1edbc | 103 | #define SHIELD_1_nCS_Pos 9 |
| AnnaBridge | 171:3a7713b1edbc | 104 | #define SHIELD_1_nCS_Msk (1UL<<SHIELD_1_nCS_Pos) |
| AnnaBridge | 171:3a7713b1edbc | 105 | |
| AnnaBridge | 171:3a7713b1edbc | 106 | /******************************************************************************/ |
| AnnaBridge | 171:3a7713b1edbc | 107 | /* SCC Register declaration */ |
| AnnaBridge | 171:3a7713b1edbc | 108 | /******************************************************************************/ |
| AnnaBridge | 171:3a7713b1edbc | 109 | |
| AnnaBridge | 171:3a7713b1edbc | 110 | typedef struct // |
| AnnaBridge | 171:3a7713b1edbc | 111 | { |
| AnnaBridge | 171:3a7713b1edbc | 112 | __IO uint32_t CFG_REG0; // Offset: 0x000 (R/W) Remaps block RAM to ZBT |
| AnnaBridge | 171:3a7713b1edbc | 113 | // [31:1] : Reserved |
| AnnaBridge | 171:3a7713b1edbc | 114 | // [0] 1 : REMAP BlockRam to ZBT |
| AnnaBridge | 171:3a7713b1edbc | 115 | __IO uint32_t LEDS; // Offset: 0x004 (R/W) Controls the MCC user LEDs |
| AnnaBridge | 171:3a7713b1edbc | 116 | // [31:8] : Reserved |
| AnnaBridge | 171:3a7713b1edbc | 117 | // [7:0] : MCC LEDs |
| AnnaBridge | 171:3a7713b1edbc | 118 | uint32_t RESERVED0[1]; |
| AnnaBridge | 171:3a7713b1edbc | 119 | __I uint32_t SWITCHES; // Offset: 0x00C (R/ ) Denotes the state of the MCC user switches |
| AnnaBridge | 171:3a7713b1edbc | 120 | // [31:8] : Reserved |
| AnnaBridge | 171:3a7713b1edbc | 121 | // [7:0] : These bits indicate state of the MCC switches |
| AnnaBridge | 171:3a7713b1edbc | 122 | __I uint32_t CFG_REG4; // Offset: 0x010 (R/ ) Denotes the board revision |
| AnnaBridge | 171:3a7713b1edbc | 123 | // [31:4] : Reserved |
| AnnaBridge | 171:3a7713b1edbc | 124 | // [3:0] : Used by the MCC to pass PCB revision. 0 = A 1 = B |
| AnnaBridge | 171:3a7713b1edbc | 125 | uint32_t RESERVED1[35]; |
| AnnaBridge | 171:3a7713b1edbc | 126 | __IO uint32_t SYS_CFGDATA_RTN; // Offset: 0x0A0 (R/W) User data register |
| AnnaBridge | 171:3a7713b1edbc | 127 | // [31:0] : Data |
| AnnaBridge | 171:3a7713b1edbc | 128 | __IO uint32_t SYS_CFGDATA_OUT; // Offset: 0x0A4 (R/W) User data register |
| AnnaBridge | 171:3a7713b1edbc | 129 | // [31:0] : Data |
| AnnaBridge | 171:3a7713b1edbc | 130 | __IO uint32_t SYS_CFGCTRL; // Offset: 0x0A8 (R/W) Control register |
| AnnaBridge | 171:3a7713b1edbc | 131 | // [31] : Start (generates interrupt on write to this bit) |
| AnnaBridge | 171:3a7713b1edbc | 132 | // [30] : R/W access |
| AnnaBridge | 171:3a7713b1edbc | 133 | // [29:26] : Reserved |
| AnnaBridge | 171:3a7713b1edbc | 134 | // [25:20] : Function value |
| AnnaBridge | 171:3a7713b1edbc | 135 | // [19:12] : Reserved |
| AnnaBridge | 171:3a7713b1edbc | 136 | // [11:0] : Device (value of 0/1/2 for supported clocks) |
| AnnaBridge | 171:3a7713b1edbc | 137 | __IO uint32_t SYS_CFGSTAT; // Offset: 0x0AC (R/W) Contains status information |
| AnnaBridge | 171:3a7713b1edbc | 138 | // [31:2] : Reserved |
| AnnaBridge | 171:3a7713b1edbc | 139 | // [1] : Error |
| AnnaBridge | 171:3a7713b1edbc | 140 | // [0] : Complete |
| AnnaBridge | 171:3a7713b1edbc | 141 | __IO uint32_t RESERVED2[20]; |
| AnnaBridge | 171:3a7713b1edbc | 142 | __IO uint32_t SCC_DLL; // Offset: 0x100 (R/W) DLL Lock Register |
| AnnaBridge | 171:3a7713b1edbc | 143 | // [31:24] : DLL LOCK MASK[7:0] - Indicate if the DLL locked is masked |
| AnnaBridge | 171:3a7713b1edbc | 144 | // [23:16] : DLL LOCK MASK[7:0] - Indicate if the DLLs are locked or unlocked |
| AnnaBridge | 171:3a7713b1edbc | 145 | // [15:1] : Reserved |
| AnnaBridge | 171:3a7713b1edbc | 146 | // [0] : This bit indicates if all enabled DLLs are locked |
| AnnaBridge | 171:3a7713b1edbc | 147 | uint32_t RESERVED3[957]; |
| AnnaBridge | 171:3a7713b1edbc | 148 | __I uint32_t SCC_AID; // Offset: 0xFF8 (R/ ) SCC AID Register |
| AnnaBridge | 171:3a7713b1edbc | 149 | // [31:24] : FPGA build number |
| AnnaBridge | 171:3a7713b1edbc | 150 | // [23:20] : V2M-MPS2 target board revision (A = 0, B = 1) |
| AnnaBridge | 171:3a7713b1edbc | 151 | // [19:11] : Reserved |
| AnnaBridge | 171:3a7713b1edbc | 152 | // [10] : if “1” SCC_SW register has been implemented |
| AnnaBridge | 171:3a7713b1edbc | 153 | // [9] : if “1” SCC_LED register has been implemented |
| AnnaBridge | 171:3a7713b1edbc | 154 | // [8] : if “1” DLL lock register has been implemented |
| AnnaBridge | 171:3a7713b1edbc | 155 | // [7:0] : number of SCC configuration register |
| AnnaBridge | 171:3a7713b1edbc | 156 | __I uint32_t SCC_ID; // Offset: 0xFFC (R/ ) Contains information about the FPGA image |
| AnnaBridge | 171:3a7713b1edbc | 157 | // [31:24] : Implementer ID: 0x41 = ARM |
| AnnaBridge | 171:3a7713b1edbc | 158 | // [23:20] : Application note IP variant number |
| AnnaBridge | 171:3a7713b1edbc | 159 | // [19:16] : IP Architecture: 0x4 =AHB |
| AnnaBridge | 171:3a7713b1edbc | 160 | // [15:4] : Primary part number: 386 = AN386 |
| AnnaBridge | 171:3a7713b1edbc | 161 | // [3:0] : Application note IP revision number |
| AnnaBridge | 171:3a7713b1edbc | 162 | } MPS2_SCC_TypeDef; |
| AnnaBridge | 171:3a7713b1edbc | 163 | |
| AnnaBridge | 171:3a7713b1edbc | 164 | |
| AnnaBridge | 171:3a7713b1edbc | 165 | /******************************************************************************/ |
| AnnaBridge | 171:3a7713b1edbc | 166 | /* SSP Peripheral declaration */ |
| AnnaBridge | 171:3a7713b1edbc | 167 | /******************************************************************************/ |
| AnnaBridge | 171:3a7713b1edbc | 168 | |
| AnnaBridge | 171:3a7713b1edbc | 169 | typedef struct // Document DDI0194G_ssp_pl022_r1p3_trm.pdf |
| AnnaBridge | 171:3a7713b1edbc | 170 | { |
| AnnaBridge | 171:3a7713b1edbc | 171 | __IO uint32_t CR0; // Offset: 0x000 (R/W) Control register 0 |
| AnnaBridge | 171:3a7713b1edbc | 172 | // [31:16] : Reserved |
| AnnaBridge | 171:3a7713b1edbc | 173 | // [15:8] : Serial clock rate |
| AnnaBridge | 171:3a7713b1edbc | 174 | // [7] : SSPCLKOUT phase, applicable to Motorola SPI frame format only |
| AnnaBridge | 171:3a7713b1edbc | 175 | // [6] : SSPCLKOUT polarity, applicable to Motorola SPI frame format only |
| AnnaBridge | 171:3a7713b1edbc | 176 | // [5:4] : Frame format |
| AnnaBridge | 171:3a7713b1edbc | 177 | // [3:0] : Data Size Select |
| AnnaBridge | 171:3a7713b1edbc | 178 | __IO uint32_t CR1; // Offset: 0x004 (R/W) Control register 1 |
| AnnaBridge | 171:3a7713b1edbc | 179 | // [31:4] : Reserved |
| AnnaBridge | 171:3a7713b1edbc | 180 | // [3] : Slave-mode output disable |
| AnnaBridge | 171:3a7713b1edbc | 181 | // [2] : Master or slave mode select |
| AnnaBridge | 171:3a7713b1edbc | 182 | // [1] : Synchronous serial port enable |
| AnnaBridge | 171:3a7713b1edbc | 183 | // [0] : Loop back mode |
| AnnaBridge | 171:3a7713b1edbc | 184 | __IO uint32_t DR; // Offset: 0x008 (R/W) Data register |
| AnnaBridge | 171:3a7713b1edbc | 185 | // [31:16] : Reserved |
| AnnaBridge | 171:3a7713b1edbc | 186 | // [15:0] : Transmit/Receive FIFO |
| AnnaBridge | 171:3a7713b1edbc | 187 | __I uint32_t SR; // Offset: 0x00C (R/ ) Status register |
| AnnaBridge | 171:3a7713b1edbc | 188 | // [31:5] : Reserved |
| AnnaBridge | 171:3a7713b1edbc | 189 | // [4] : PrimeCell SSP busy flag |
| AnnaBridge | 171:3a7713b1edbc | 190 | // [3] : Receive FIFO full |
| AnnaBridge | 171:3a7713b1edbc | 191 | // [2] : Receive FIFO not empty |
| AnnaBridge | 171:3a7713b1edbc | 192 | // [1] : Transmit FIFO not full |
| AnnaBridge | 171:3a7713b1edbc | 193 | // [0] : Transmit FIFO empty |
| AnnaBridge | 171:3a7713b1edbc | 194 | __IO uint32_t CPSR; // Offset: 0x010 (R/W) Clock prescale register |
| AnnaBridge | 171:3a7713b1edbc | 195 | // [31:8] : Reserved |
| AnnaBridge | 171:3a7713b1edbc | 196 | // [8:0] : Clock prescale divisor |
| AnnaBridge | 171:3a7713b1edbc | 197 | __IO uint32_t IMSC; // Offset: 0x014 (R/W) Interrupt mask set or clear register |
| AnnaBridge | 171:3a7713b1edbc | 198 | // [31:4] : Reserved |
| AnnaBridge | 171:3a7713b1edbc | 199 | // [3] : Transmit FIFO interrupt mask |
| AnnaBridge | 171:3a7713b1edbc | 200 | // [2] : Receive FIFO interrupt mask |
| AnnaBridge | 171:3a7713b1edbc | 201 | // [1] : Receive timeout interrupt mask |
| AnnaBridge | 171:3a7713b1edbc | 202 | // [0] : Receive overrun interrupt mask |
| AnnaBridge | 171:3a7713b1edbc | 203 | __I uint32_t RIS; // Offset: 0x018 (R/ ) Raw interrupt status register |
| AnnaBridge | 171:3a7713b1edbc | 204 | // [31:4] : Reserved |
| AnnaBridge | 171:3a7713b1edbc | 205 | // [3] : raw interrupt state, prior to masking, of the SSPTXINTR interrupt |
| AnnaBridge | 171:3a7713b1edbc | 206 | // [2] : raw interrupt state, prior to masking, of the SSPRXINTR interrupt |
| AnnaBridge | 171:3a7713b1edbc | 207 | // [1] : raw interrupt state, prior to masking, of the SSPRTINTR interrupt |
| AnnaBridge | 171:3a7713b1edbc | 208 | // [0] : raw interrupt state, prior to masking, of the SSPRORINTR interrupt |
| AnnaBridge | 171:3a7713b1edbc | 209 | __I uint32_t MIS; // Offset: 0x01C (R/ ) Masked interrupt status register |
| AnnaBridge | 171:3a7713b1edbc | 210 | // [31:4] : Reserved |
| AnnaBridge | 171:3a7713b1edbc | 211 | // [3] : transmit FIFO masked interrupt state, after masking, of the SSPTXINTR interrupt |
| AnnaBridge | 171:3a7713b1edbc | 212 | // [2] : receive FIFO masked interrupt state, after masking, of the SSPRXINTR interrupt |
| AnnaBridge | 171:3a7713b1edbc | 213 | // [1] : receive timeout masked interrupt state, after masking, of the SSPRTINTR interrupt |
| AnnaBridge | 171:3a7713b1edbc | 214 | // [0] : receive over run masked interrupt status, after masking, of the SSPRORINTR interrupt |
| AnnaBridge | 171:3a7713b1edbc | 215 | __O uint32_t ICR; // Offset: 0x020 ( /W) Interrupt clear register |
| AnnaBridge | 171:3a7713b1edbc | 216 | // [31:2] : Reserved |
| AnnaBridge | 171:3a7713b1edbc | 217 | // [1] : Clears the SSPRTINTR interrupt |
| AnnaBridge | 171:3a7713b1edbc | 218 | // [0] : Clears the SSPRORINTR interrupt |
| AnnaBridge | 171:3a7713b1edbc | 219 | __IO uint32_t DMACR; // Offset: 0x024 (R/W) DMA control register |
| AnnaBridge | 171:3a7713b1edbc | 220 | // [31:2] : Reserved |
| AnnaBridge | 171:3a7713b1edbc | 221 | // [1] : Transmit DMA Enable |
| AnnaBridge | 171:3a7713b1edbc | 222 | // [0] : Receive DMA Enable |
| AnnaBridge | 171:3a7713b1edbc | 223 | } MPS2_SSP_TypeDef; |
| AnnaBridge | 171:3a7713b1edbc | 224 | |
| AnnaBridge | 171:3a7713b1edbc | 225 | |
| AnnaBridge | 171:3a7713b1edbc | 226 | // SSP_CR0 Control register 0 |
| AnnaBridge | 171:3a7713b1edbc | 227 | #define SSP_CR0_DSS_Pos 0 // Data Size Select |
| AnnaBridge | 171:3a7713b1edbc | 228 | #define SSP_CR0_DSS_Msk (0xF<<SSP_CR0_DSS_Pos) |
| AnnaBridge | 171:3a7713b1edbc | 229 | #define SSP_CR0_FRF_Pos 4 // Frame Format Select |
| AnnaBridge | 171:3a7713b1edbc | 230 | #define SSP_CR0_FRF_Msk (3UL<<SSP_CR0_FRM_Pos) |
| AnnaBridge | 171:3a7713b1edbc | 231 | #define SSP_CR0_SPO_Pos 6 // SSPCLKOUT polarity |
| AnnaBridge | 171:3a7713b1edbc | 232 | #define SSP_CR0_SPO_Msk (1UL<<SSP_CR0_SPO_Pos) |
| AnnaBridge | 171:3a7713b1edbc | 233 | #define SSP_CR0_SPH_Pos 7 // SSPCLKOUT phase |
| AnnaBridge | 171:3a7713b1edbc | 234 | #define SSP_CR0_SPH_Msk (1UL<<SSP_CR0_SPH_Pos) |
| AnnaBridge | 171:3a7713b1edbc | 235 | #define SSP_CR0_SCR_Pos 8 // Serial Clock Rate (divide) |
| AnnaBridge | 171:3a7713b1edbc | 236 | #define SSP_CR0_SCR_Msk (0xFF<<SSP_CR0_SCR_Pos) |
| AnnaBridge | 171:3a7713b1edbc | 237 | |
| AnnaBridge | 171:3a7713b1edbc | 238 | #define SSP_CR0_SCR_DFLT 0x0300 // Serial Clock Rate (divide), default set at 3 |
| AnnaBridge | 171:3a7713b1edbc | 239 | #define SSP_CR0_FRF_MOT 0x0000 // Frame format, Motorola |
| AnnaBridge | 171:3a7713b1edbc | 240 | #define SSP_CR0_DSS_8 0x0007 // Data packet size, 8bits |
| AnnaBridge | 171:3a7713b1edbc | 241 | #define SSP_CR0_DSS_16 0x000F // Data packet size, 16bits |
| AnnaBridge | 171:3a7713b1edbc | 242 | |
| AnnaBridge | 171:3a7713b1edbc | 243 | // SSP_CR1 Control register 1 |
| AnnaBridge | 171:3a7713b1edbc | 244 | #define SSP_CR1_LBM_Pos 0 // Loop Back Mode |
| AnnaBridge | 171:3a7713b1edbc | 245 | #define SSP_CR1_LBM_Msk (1UL<<SSP_CR1_LBM_Pos) |
| AnnaBridge | 171:3a7713b1edbc | 246 | #define SSP_CR1_SSE_Pos 1 // Serial port enable |
| AnnaBridge | 171:3a7713b1edbc | 247 | #define SSP_CR1_SSE_Msk (1UL<<SSP_CR1_SSE_Pos) |
| AnnaBridge | 171:3a7713b1edbc | 248 | #define SSP_CR1_MS_Pos 2 // Master or Slave mode |
| AnnaBridge | 171:3a7713b1edbc | 249 | #define SSP_CR1_MS_Msk (1UL<<SSP_CR1_MS_Pos) |
| AnnaBridge | 171:3a7713b1edbc | 250 | #define SSP_CR1_SOD_Pos 3 // Slave Output mode Disable |
| AnnaBridge | 171:3a7713b1edbc | 251 | #define SSP_CR1_SOD_Msk (1UL<<SSP_CR1_SOD_Pos) |
| AnnaBridge | 171:3a7713b1edbc | 252 | |
| AnnaBridge | 171:3a7713b1edbc | 253 | // SSP_SR Status register |
| AnnaBridge | 171:3a7713b1edbc | 254 | #define SSP_SR_TFE_Pos 0 // Transmit FIFO empty |
| AnnaBridge | 171:3a7713b1edbc | 255 | #define SSP_SR_TFE_Msk (1UL<<SSP_SR_TFE_Pos) |
| AnnaBridge | 171:3a7713b1edbc | 256 | #define SSP_SR_TNF_Pos 1 // Transmit FIFO not full |
| AnnaBridge | 171:3a7713b1edbc | 257 | #define SSP_SR_TNF_Msk (1UL<<SSP_SR_TNF_Pos) |
| AnnaBridge | 171:3a7713b1edbc | 258 | #define SSP_SR_RNE_Pos 2 // Receive FIFO not empty |
| AnnaBridge | 171:3a7713b1edbc | 259 | #define SSP_SR_RNE_Msk (1UL<<SSP_SR_RNE_Pos) |
| AnnaBridge | 171:3a7713b1edbc | 260 | #define SSP_SR_RFF_Pos 3 // Receive FIFO full |
| AnnaBridge | 171:3a7713b1edbc | 261 | #define SSP_SR_RFF_Msk (1UL<<SSP_SR_RFF_Pos) |
| AnnaBridge | 171:3a7713b1edbc | 262 | #define SSP_SR_BSY_Pos 4 // Busy |
| AnnaBridge | 171:3a7713b1edbc | 263 | #define SSP_SR_BSY_Msk (1UL<<SSP_SR_BSY_Pos) |
| AnnaBridge | 171:3a7713b1edbc | 264 | |
| AnnaBridge | 171:3a7713b1edbc | 265 | // SSP_CPSR Clock prescale register |
| AnnaBridge | 171:3a7713b1edbc | 266 | #define SSP_CPSR_CPD_Pos 0 // Clock prescale divisor |
| AnnaBridge | 171:3a7713b1edbc | 267 | #define SSP_CPSR_CPD_Msk (0xFF<<SSP_CPSR_CDP_Pos) |
| AnnaBridge | 171:3a7713b1edbc | 268 | |
| AnnaBridge | 171:3a7713b1edbc | 269 | #define SSP_CPSR_DFLT 0x0008 // Clock prescale (use with SCR), default set at 8 |
| AnnaBridge | 171:3a7713b1edbc | 270 | |
| AnnaBridge | 171:3a7713b1edbc | 271 | // SSPIMSC Interrupt mask set and clear register |
| AnnaBridge | 171:3a7713b1edbc | 272 | #define SSP_IMSC_RORIM_Pos 0 // Receive overrun not Masked |
| AnnaBridge | 171:3a7713b1edbc | 273 | #define SSP_IMSC_RORIM_Msk (1UL<<SSP_IMSC_RORIM_Pos) |
| AnnaBridge | 171:3a7713b1edbc | 274 | #define SSP_IMSC_RTIM_Pos 1 // Receive timeout not Masked |
| AnnaBridge | 171:3a7713b1edbc | 275 | #define SSP_IMSC_RTIM_Msk (1UL<<SSP_IMSC_RTIM_Pos) |
| AnnaBridge | 171:3a7713b1edbc | 276 | #define SSP_IMSC_RXIM_Pos 2 // Receive FIFO not Masked |
| AnnaBridge | 171:3a7713b1edbc | 277 | #define SSP_IMSC_RXIM_Msk (1UL<<SSP_IMSC_RXIM_Pos) |
| AnnaBridge | 171:3a7713b1edbc | 278 | #define SSP_IMSC_TXIM_Pos 3 // Transmit FIFO not Masked |
| AnnaBridge | 171:3a7713b1edbc | 279 | #define SSP_IMSC_TXIM_Msk (1UL<<SSP_IMSC_TXIM_Pos) |
| AnnaBridge | 171:3a7713b1edbc | 280 | |
| AnnaBridge | 171:3a7713b1edbc | 281 | // SSPRIS Raw interrupt status register |
| AnnaBridge | 171:3a7713b1edbc | 282 | #define SSP_RIS_RORRIS_Pos 0 // Raw Overrun interrupt flag |
| AnnaBridge | 171:3a7713b1edbc | 283 | #define SSP_RIS_RORRIS_Msk (1UL<<SSP_RIS_RORRIS_Pos) |
| AnnaBridge | 171:3a7713b1edbc | 284 | #define SSP_RIS_RTRIS_Pos 1 // Raw Timemout interrupt flag |
| AnnaBridge | 171:3a7713b1edbc | 285 | #define SSP_RIS_RTRIS_Msk (1UL<<SSP_RIS_RTRIS_Pos) |
| AnnaBridge | 171:3a7713b1edbc | 286 | #define SSP_RIS_RXRIS_Pos 2 // Raw Receive interrupt flag |
| AnnaBridge | 171:3a7713b1edbc | 287 | #define SSP_RIS_RXRIS_Msk (1UL<<SSP_RIS_RXRIS_Pos) |
| AnnaBridge | 171:3a7713b1edbc | 288 | #define SSP_RIS_TXRIS_Pos 3 // Raw Transmit interrupt flag |
| AnnaBridge | 171:3a7713b1edbc | 289 | #define SSP_RIS_TXRIS_Msk (1UL<<SSP_RIS_TXRIS_Pos) |
| AnnaBridge | 171:3a7713b1edbc | 290 | |
| AnnaBridge | 171:3a7713b1edbc | 291 | // SSPMIS Masked interrupt status register |
| AnnaBridge | 171:3a7713b1edbc | 292 | #define SSP_MIS_RORMIS_Pos 0 // Masked Overrun interrupt flag |
| AnnaBridge | 171:3a7713b1edbc | 293 | #define SSP_MIS_RORMIS_Msk (1UL<<SSP_MIS_RORMIS_Pos) |
| AnnaBridge | 171:3a7713b1edbc | 294 | #define SSP_MIS_RTMIS_Pos 1 // Masked Timemout interrupt flag |
| AnnaBridge | 171:3a7713b1edbc | 295 | #define SSP_MIS_RTMIS_Msk (1UL<<SSP_MIS_RTMIS_Pos) |
| AnnaBridge | 171:3a7713b1edbc | 296 | #define SSP_MIS_RXMIS_Pos 2 // Masked Receive interrupt flag |
| AnnaBridge | 171:3a7713b1edbc | 297 | #define SSP_MIS_RXMIS_Msk (1UL<<SSP_MIS_RXMIS_Pos) |
| AnnaBridge | 171:3a7713b1edbc | 298 | #define SSP_MIS_TXMIS_Pos 3 // Masked Transmit interrupt flag |
| AnnaBridge | 171:3a7713b1edbc | 299 | #define SSP_MIS_TXMIS_Msk (1UL<<SSP_MIS_TXMIS_Pos) |
| AnnaBridge | 171:3a7713b1edbc | 300 | |
| AnnaBridge | 171:3a7713b1edbc | 301 | // SSPICR Interrupt clear register |
| AnnaBridge | 171:3a7713b1edbc | 302 | #define SSP_ICR_RORIC_Pos 0 // Clears Overrun interrupt flag |
| AnnaBridge | 171:3a7713b1edbc | 303 | #define SSP_ICR_RORIC_Msk (1UL<<SSP_ICR_RORIC_Pos) |
| AnnaBridge | 171:3a7713b1edbc | 304 | #define SSP_ICR_RTIC_Pos 1 // Clears Timemout interrupt flag |
| AnnaBridge | 171:3a7713b1edbc | 305 | #define SSP_ICR_RTIC_Msk (1UL<<SSP_ICR_RTIC_Pos) |
| AnnaBridge | 171:3a7713b1edbc | 306 | |
| AnnaBridge | 171:3a7713b1edbc | 307 | // SSPDMACR DMA control register |
| AnnaBridge | 171:3a7713b1edbc | 308 | #define SSP_DMACR_RXDMAE_Pos 0 // Enable Receive FIFO DMA |
| AnnaBridge | 171:3a7713b1edbc | 309 | #define SSP_DMACR_RXDMAE_Msk (1UL<<SSP_DMACR_RXDMAE_Pos) |
| AnnaBridge | 171:3a7713b1edbc | 310 | #define SSP_DMACR_TXDMAE_Pos 1 // Enable Transmit FIFO DMA |
| AnnaBridge | 171:3a7713b1edbc | 311 | #define SSP_DMACR_TXDMAE_Msk (1UL<<SSP_DMACR_TXDMAE_Pos) |
| AnnaBridge | 171:3a7713b1edbc | 312 | |
| AnnaBridge | 171:3a7713b1edbc | 313 | /******************************************************************************/ |
| AnnaBridge | 171:3a7713b1edbc | 314 | /* Audio and Touch Screen (I2C) Peripheral declaration */ |
| AnnaBridge | 171:3a7713b1edbc | 315 | /******************************************************************************/ |
| AnnaBridge | 171:3a7713b1edbc | 316 | |
| AnnaBridge | 171:3a7713b1edbc | 317 | typedef struct |
| AnnaBridge | 171:3a7713b1edbc | 318 | { |
| AnnaBridge | 171:3a7713b1edbc | 319 | union { |
| AnnaBridge | 171:3a7713b1edbc | 320 | __O uint32_t CONTROLS; // Offset: 0x000 CONTROL Set Register ( /W) |
| AnnaBridge | 171:3a7713b1edbc | 321 | __I uint32_t CONTROL; // Offset: 0x000 CONTROL Status Register (R/ ) |
| AnnaBridge | 171:3a7713b1edbc | 322 | }; |
| AnnaBridge | 171:3a7713b1edbc | 323 | __O uint32_t CONTROLC; // Offset: 0x004 CONTROL Clear Register ( /W) |
| AnnaBridge | 171:3a7713b1edbc | 324 | } MPS2_I2C_TypeDef; |
| AnnaBridge | 171:3a7713b1edbc | 325 | |
| AnnaBridge | 171:3a7713b1edbc | 326 | #define SDA 1 << 1 |
| AnnaBridge | 171:3a7713b1edbc | 327 | #define SCL 1 << 0 |
| AnnaBridge | 171:3a7713b1edbc | 328 | |
| AnnaBridge | 171:3a7713b1edbc | 329 | |
| AnnaBridge | 171:3a7713b1edbc | 330 | /******************************************************************************/ |
| AnnaBridge | 171:3a7713b1edbc | 331 | /* Audio I2S Peripheral declaration */ |
| AnnaBridge | 171:3a7713b1edbc | 332 | /******************************************************************************/ |
| AnnaBridge | 171:3a7713b1edbc | 333 | |
| AnnaBridge | 171:3a7713b1edbc | 334 | typedef struct |
| AnnaBridge | 171:3a7713b1edbc | 335 | { |
| AnnaBridge | 171:3a7713b1edbc | 336 | /*!< Offset: 0x000 CONTROL Register (R/W) */ |
| AnnaBridge | 171:3a7713b1edbc | 337 | __IO uint32_t CONTROL; // <h> CONTROL </h> |
| AnnaBridge | 171:3a7713b1edbc | 338 | // <o.0> TX Enable |
| AnnaBridge | 171:3a7713b1edbc | 339 | // <0=> TX disabled |
| AnnaBridge | 171:3a7713b1edbc | 340 | // <1=> TX enabled |
| AnnaBridge | 171:3a7713b1edbc | 341 | // <o.1> TX IRQ Enable |
| AnnaBridge | 171:3a7713b1edbc | 342 | // <0=> TX IRQ disabled |
| AnnaBridge | 171:3a7713b1edbc | 343 | // <1=> TX IRQ enabled |
| AnnaBridge | 171:3a7713b1edbc | 344 | // <o.2> RX Enable |
| AnnaBridge | 171:3a7713b1edbc | 345 | // <0=> RX disabled |
| AnnaBridge | 171:3a7713b1edbc | 346 | // <1=> RX enabled |
| AnnaBridge | 171:3a7713b1edbc | 347 | // <o.3> RX IRQ Enable |
| AnnaBridge | 171:3a7713b1edbc | 348 | // <0=> RX IRQ disabled |
| AnnaBridge | 171:3a7713b1edbc | 349 | // <1=> RX IRQ enabled |
| AnnaBridge | 171:3a7713b1edbc | 350 | // <o.10..8> TX Buffer Water Level |
| AnnaBridge | 171:3a7713b1edbc | 351 | // <0=> / IRQ triggers when any space available |
| AnnaBridge | 171:3a7713b1edbc | 352 | // <1=> / IRQ triggers when more than 1 space available |
| AnnaBridge | 171:3a7713b1edbc | 353 | // <2=> / IRQ triggers when more than 2 space available |
| AnnaBridge | 171:3a7713b1edbc | 354 | // <3=> / IRQ triggers when more than 3 space available |
| AnnaBridge | 171:3a7713b1edbc | 355 | // <4=> Undefined! |
| AnnaBridge | 171:3a7713b1edbc | 356 | // <5=> Undefined! |
| AnnaBridge | 171:3a7713b1edbc | 357 | // <6=> Undefined! |
| AnnaBridge | 171:3a7713b1edbc | 358 | // <7=> Undefined! |
| AnnaBridge | 171:3a7713b1edbc | 359 | // <o.14..12> RX Buffer Water Level |
| AnnaBridge | 171:3a7713b1edbc | 360 | // <0=> Undefined! |
| AnnaBridge | 171:3a7713b1edbc | 361 | // <1=> / IRQ triggers when less than 1 space available |
| AnnaBridge | 171:3a7713b1edbc | 362 | // <2=> / IRQ triggers when less than 2 space available |
| AnnaBridge | 171:3a7713b1edbc | 363 | // <3=> / IRQ triggers when less than 3 space available |
| AnnaBridge | 171:3a7713b1edbc | 364 | // <4=> / IRQ triggers when less than 4 space available |
| AnnaBridge | 171:3a7713b1edbc | 365 | // <5=> Undefined! |
| AnnaBridge | 171:3a7713b1edbc | 366 | // <6=> Undefined! |
| AnnaBridge | 171:3a7713b1edbc | 367 | // <7=> Undefined! |
| AnnaBridge | 171:3a7713b1edbc | 368 | // <o.16> FIFO reset |
| AnnaBridge | 171:3a7713b1edbc | 369 | // <0=> Normal operation |
| AnnaBridge | 171:3a7713b1edbc | 370 | // <1=> FIFO reset |
| AnnaBridge | 171:3a7713b1edbc | 371 | // <o.17> Audio Codec reset |
| AnnaBridge | 171:3a7713b1edbc | 372 | // <0=> Normal operation |
| AnnaBridge | 171:3a7713b1edbc | 373 | // <1=> Assert audio Codec reset |
| AnnaBridge | 171:3a7713b1edbc | 374 | /*!< Offset: 0x004 STATUS Register (R/ ) */ |
| AnnaBridge | 171:3a7713b1edbc | 375 | __I uint32_t STATUS; // <h> STATUS </h> |
| AnnaBridge | 171:3a7713b1edbc | 376 | // <o.0> TX Buffer alert |
| AnnaBridge | 171:3a7713b1edbc | 377 | // <0=> TX buffer don't need service yet |
| AnnaBridge | 171:3a7713b1edbc | 378 | // <1=> TX buffer need service |
| AnnaBridge | 171:3a7713b1edbc | 379 | // <o.1> RX Buffer alert |
| AnnaBridge | 171:3a7713b1edbc | 380 | // <0=> RX buffer don't need service yet |
| AnnaBridge | 171:3a7713b1edbc | 381 | // <1=> RX buffer need service |
| AnnaBridge | 171:3a7713b1edbc | 382 | // <o.2> TX Buffer Empty |
| AnnaBridge | 171:3a7713b1edbc | 383 | // <0=> TX buffer have data |
| AnnaBridge | 171:3a7713b1edbc | 384 | // <1=> TX buffer empty |
| AnnaBridge | 171:3a7713b1edbc | 385 | // <o.3> TX Buffer Full |
| AnnaBridge | 171:3a7713b1edbc | 386 | // <0=> TX buffer not full |
| AnnaBridge | 171:3a7713b1edbc | 387 | // <1=> TX buffer full |
| AnnaBridge | 171:3a7713b1edbc | 388 | // <o.4> RX Buffer Empty |
| AnnaBridge | 171:3a7713b1edbc | 389 | // <0=> RX buffer have data |
| AnnaBridge | 171:3a7713b1edbc | 390 | // <1=> RX buffer empty |
| AnnaBridge | 171:3a7713b1edbc | 391 | // <o.5> RX Buffer Full |
| AnnaBridge | 171:3a7713b1edbc | 392 | // <0=> RX buffer not full |
| AnnaBridge | 171:3a7713b1edbc | 393 | // <1=> RX buffer full |
| AnnaBridge | 171:3a7713b1edbc | 394 | union { |
| AnnaBridge | 171:3a7713b1edbc | 395 | /*!< Offset: 0x008 Error Status Register (R/ ) */ |
| AnnaBridge | 171:3a7713b1edbc | 396 | __I uint32_t ERROR; // <h> ERROR </h> |
| AnnaBridge | 171:3a7713b1edbc | 397 | // <o.0> TX error |
| AnnaBridge | 171:3a7713b1edbc | 398 | // <0=> Okay |
| AnnaBridge | 171:3a7713b1edbc | 399 | // <1=> TX overrun/underrun |
| AnnaBridge | 171:3a7713b1edbc | 400 | // <o.1> RX error |
| AnnaBridge | 171:3a7713b1edbc | 401 | // <0=> Okay |
| AnnaBridge | 171:3a7713b1edbc | 402 | // <1=> RX overrun/underrun |
| AnnaBridge | 171:3a7713b1edbc | 403 | /*!< Offset: 0x008 Error Clear Register ( /W) */ |
| AnnaBridge | 171:3a7713b1edbc | 404 | __O uint32_t ERRORCLR; // <h> ERRORCLR </h> |
| AnnaBridge | 171:3a7713b1edbc | 405 | // <o.0> TX error |
| AnnaBridge | 171:3a7713b1edbc | 406 | // <0=> Okay |
| AnnaBridge | 171:3a7713b1edbc | 407 | // <1=> Clear TX error |
| AnnaBridge | 171:3a7713b1edbc | 408 | // <o.1> RX error |
| AnnaBridge | 171:3a7713b1edbc | 409 | // <0=> Okay |
| AnnaBridge | 171:3a7713b1edbc | 410 | // <1=> Clear RX error |
| AnnaBridge | 171:3a7713b1edbc | 411 | }; |
| AnnaBridge | 171:3a7713b1edbc | 412 | /*!< Offset: 0x00C Divide ratio Register (R/W) */ |
| AnnaBridge | 171:3a7713b1edbc | 413 | __IO uint32_t DIVIDE; // <h> Divide ratio for Left/Right clock </h> |
| AnnaBridge | 171:3a7713b1edbc | 414 | // <o.9..0> TX error (default 0x80) |
| AnnaBridge | 171:3a7713b1edbc | 415 | /*!< Offset: 0x010 Transmit Buffer ( /W) */ |
| AnnaBridge | 171:3a7713b1edbc | 416 | __O uint32_t TXBUF; // <h> Transmit buffer </h> |
| AnnaBridge | 171:3a7713b1edbc | 417 | // <o.15..0> Right channel |
| AnnaBridge | 171:3a7713b1edbc | 418 | // <o.31..16> Left channel |
| AnnaBridge | 171:3a7713b1edbc | 419 | /*!< Offset: 0x014 Receive Buffer (R/ ) */ |
| AnnaBridge | 171:3a7713b1edbc | 420 | __I uint32_t RXBUF; // <h> Receive buffer </h> |
| AnnaBridge | 171:3a7713b1edbc | 421 | // <o.15..0> Right channel |
| AnnaBridge | 171:3a7713b1edbc | 422 | // <o.31..16> Left channel |
| AnnaBridge | 171:3a7713b1edbc | 423 | uint32_t RESERVED1[186]; |
| AnnaBridge | 171:3a7713b1edbc | 424 | __IO uint32_t ITCR; // <h> Integration Test Control Register </h> |
| AnnaBridge | 171:3a7713b1edbc | 425 | // <o.0> ITEN |
| AnnaBridge | 171:3a7713b1edbc | 426 | // <0=> Normal operation |
| AnnaBridge | 171:3a7713b1edbc | 427 | // <1=> Integration Test mode enable |
| AnnaBridge | 171:3a7713b1edbc | 428 | __O uint32_t ITIP1; // <h> Integration Test Input Register 1</h> |
| AnnaBridge | 171:3a7713b1edbc | 429 | // <o.0> SDIN |
| AnnaBridge | 171:3a7713b1edbc | 430 | __O uint32_t ITOP1; // <h> Integration Test Output Register 1</h> |
| AnnaBridge | 171:3a7713b1edbc | 431 | // <o.0> SDOUT |
| AnnaBridge | 171:3a7713b1edbc | 432 | // <o.1> SCLK |
| AnnaBridge | 171:3a7713b1edbc | 433 | // <o.2> LRCK |
| AnnaBridge | 171:3a7713b1edbc | 434 | // <o.3> IRQOUT |
| AnnaBridge | 171:3a7713b1edbc | 435 | } MPS2_I2S_TypeDef; |
| AnnaBridge | 171:3a7713b1edbc | 436 | |
| AnnaBridge | 171:3a7713b1edbc | 437 | #define I2S_CONTROL_TXEN_Pos 0 |
| AnnaBridge | 171:3a7713b1edbc | 438 | #define I2S_CONTROL_TXEN_Msk (1UL<<I2S_CONTROL_TXEN_Pos) |
| AnnaBridge | 171:3a7713b1edbc | 439 | |
| AnnaBridge | 171:3a7713b1edbc | 440 | #define I2S_CONTROL_TXIRQEN_Pos 1 |
| AnnaBridge | 171:3a7713b1edbc | 441 | #define I2S_CONTROL_TXIRQEN_Msk (1UL<<I2S_CONTROL_TXIRQEN_Pos) |
| AnnaBridge | 171:3a7713b1edbc | 442 | |
| AnnaBridge | 171:3a7713b1edbc | 443 | #define I2S_CONTROL_RXEN_Pos 2 |
| AnnaBridge | 171:3a7713b1edbc | 444 | #define I2S_CONTROL_RXEN_Msk (1UL<<I2S_CONTROL_RXEN_Pos) |
| AnnaBridge | 171:3a7713b1edbc | 445 | |
| AnnaBridge | 171:3a7713b1edbc | 446 | #define I2S_CONTROL_RXIRQEN_Pos 3 |
| AnnaBridge | 171:3a7713b1edbc | 447 | #define I2S_CONTROL_RXIRQEN_Msk (1UL<<I2S_CONTROL_RXIRQEN_Pos) |
| AnnaBridge | 171:3a7713b1edbc | 448 | |
| AnnaBridge | 171:3a7713b1edbc | 449 | #define I2S_CONTROL_TXWLVL_Pos 8 |
| AnnaBridge | 171:3a7713b1edbc | 450 | #define I2S_CONTROL_TXWLVL_Msk (7UL<<I2S_CONTROL_TXWLVL_Pos) |
| AnnaBridge | 171:3a7713b1edbc | 451 | |
| AnnaBridge | 171:3a7713b1edbc | 452 | #define I2S_CONTROL_RXWLVL_Pos 12 |
| AnnaBridge | 171:3a7713b1edbc | 453 | #define I2S_CONTROL_RXWLVL_Msk (7UL<<I2S_CONTROL_RXWLVL_Pos) |
| AnnaBridge | 171:3a7713b1edbc | 454 | /* FIFO reset*/ |
| AnnaBridge | 171:3a7713b1edbc | 455 | #define I2S_CONTROL_FIFORST_Pos 16 |
| AnnaBridge | 171:3a7713b1edbc | 456 | #define I2S_CONTROL_FIFORST_Msk (1UL<<I2S_CONTROL_FIFORST_Pos) |
| AnnaBridge | 171:3a7713b1edbc | 457 | /* Codec reset*/ |
| AnnaBridge | 171:3a7713b1edbc | 458 | #define I2S_CONTROL_CODECRST_Pos 17 |
| AnnaBridge | 171:3a7713b1edbc | 459 | #define I2S_CONTROL_CODECRST_Msk (1UL<<I2S_CONTROL_CODECRST_Pos) |
| AnnaBridge | 171:3a7713b1edbc | 460 | |
| AnnaBridge | 171:3a7713b1edbc | 461 | #define I2S_STATUS_TXIRQ_Pos 0 |
| AnnaBridge | 171:3a7713b1edbc | 462 | #define I2S_STATUS_TXIRQ_Msk (1UL<<I2S_STATUS_TXIRQ_Pos) |
| AnnaBridge | 171:3a7713b1edbc | 463 | |
| AnnaBridge | 171:3a7713b1edbc | 464 | #define I2S_STATUS_RXIRQ_Pos 1 |
| AnnaBridge | 171:3a7713b1edbc | 465 | #define I2S_STATUS_RXIRQ_Msk (1UL<<I2S_STATUS_RXIRQ_Pos) |
| AnnaBridge | 171:3a7713b1edbc | 466 | |
| AnnaBridge | 171:3a7713b1edbc | 467 | #define I2S_STATUS_TXEmpty_Pos 2 |
| AnnaBridge | 171:3a7713b1edbc | 468 | #define I2S_STATUS_TXEmpty_Msk (1UL<<I2S_STATUS_TXEmpty_Pos) |
| AnnaBridge | 171:3a7713b1edbc | 469 | |
| AnnaBridge | 171:3a7713b1edbc | 470 | #define I2S_STATUS_TXFull_Pos 3 |
| AnnaBridge | 171:3a7713b1edbc | 471 | #define I2S_STATUS_TXFull_Msk (1UL<<I2S_STATUS_TXFull_Pos) |
| AnnaBridge | 171:3a7713b1edbc | 472 | |
| AnnaBridge | 171:3a7713b1edbc | 473 | #define I2S_STATUS_RXEmpty_Pos 4 |
| AnnaBridge | 171:3a7713b1edbc | 474 | #define I2S_STATUS_RXEmpty_Msk (1UL<<I2S_STATUS_RXEmpty_Pos) |
| AnnaBridge | 171:3a7713b1edbc | 475 | |
| AnnaBridge | 171:3a7713b1edbc | 476 | #define I2S_STATUS_RXFull_Pos 5 |
| AnnaBridge | 171:3a7713b1edbc | 477 | #define I2S_STATUS_RXFull_Msk (1UL<<I2S_STATUS_RXFull_Pos) |
| AnnaBridge | 171:3a7713b1edbc | 478 | |
| AnnaBridge | 171:3a7713b1edbc | 479 | #define I2S_ERROR_TXERR_Pos 0 |
| AnnaBridge | 171:3a7713b1edbc | 480 | #define I2S_ERROR_TXERR_Msk (1UL<<I2S_ERROR_TXERR_Pos) |
| AnnaBridge | 171:3a7713b1edbc | 481 | |
| AnnaBridge | 171:3a7713b1edbc | 482 | #define I2S_ERROR_RXERR_Pos 1 |
| AnnaBridge | 171:3a7713b1edbc | 483 | #define I2S_ERROR_RXERR_Msk (1UL<<I2S_ERROR_RXERR_Pos) |
| AnnaBridge | 171:3a7713b1edbc | 484 | |
| AnnaBridge | 171:3a7713b1edbc | 485 | /******************************************************************************/ |
| AnnaBridge | 171:3a7713b1edbc | 486 | /* SMSC9220 Register Definitions */ |
| AnnaBridge | 171:3a7713b1edbc | 487 | /******************************************************************************/ |
| AnnaBridge | 171:3a7713b1edbc | 488 | |
| AnnaBridge | 171:3a7713b1edbc | 489 | typedef struct // SMSC LAN9220 |
| AnnaBridge | 171:3a7713b1edbc | 490 | { |
| AnnaBridge | 171:3a7713b1edbc | 491 | __I uint32_t RX_DATA_PORT; // Receive FIFO Ports (offset 0x0) |
| AnnaBridge | 171:3a7713b1edbc | 492 | uint32_t RESERVED1[0x7]; |
| AnnaBridge | 171:3a7713b1edbc | 493 | __O uint32_t TX_DATA_PORT; // Transmit FIFO Ports (offset 0x20) |
| AnnaBridge | 171:3a7713b1edbc | 494 | uint32_t RESERVED2[0x7]; |
| AnnaBridge | 171:3a7713b1edbc | 495 | |
| AnnaBridge | 171:3a7713b1edbc | 496 | __I uint32_t RX_STAT_PORT; // Receive FIFO status port (offset 0x40) |
| AnnaBridge | 171:3a7713b1edbc | 497 | __I uint32_t RX_STAT_PEEK; // Receive FIFO status peek (offset 0x44) |
| AnnaBridge | 171:3a7713b1edbc | 498 | __I uint32_t TX_STAT_PORT; // Transmit FIFO status port (offset 0x48) |
| AnnaBridge | 171:3a7713b1edbc | 499 | __I uint32_t TX_STAT_PEEK; // Transmit FIFO status peek (offset 0x4C) |
| AnnaBridge | 171:3a7713b1edbc | 500 | |
| AnnaBridge | 171:3a7713b1edbc | 501 | __I uint32_t ID_REV; // Chip ID and Revision (offset 0x50) |
| AnnaBridge | 171:3a7713b1edbc | 502 | __IO uint32_t IRQ_CFG; // Main Interrupt Configuration (offset 0x54) |
| AnnaBridge | 171:3a7713b1edbc | 503 | __IO uint32_t INT_STS; // Interrupt Status (offset 0x58) |
| AnnaBridge | 171:3a7713b1edbc | 504 | __IO uint32_t INT_EN; // Interrupt Enable Register (offset 0x5C) |
| AnnaBridge | 171:3a7713b1edbc | 505 | uint32_t RESERVED3; // Reserved for future use (offset 0x60) |
| AnnaBridge | 171:3a7713b1edbc | 506 | __I uint32_t BYTE_TEST; // Read-only byte order testing register 87654321h (offset 0x64) |
| AnnaBridge | 171:3a7713b1edbc | 507 | __IO uint32_t FIFO_INT; // FIFO Level Interrupts (offset 0x68) |
| AnnaBridge | 171:3a7713b1edbc | 508 | __IO uint32_t RX_CFG; // Receive Configuration (offset 0x6C) |
| AnnaBridge | 171:3a7713b1edbc | 509 | __IO uint32_t TX_CFG; // Transmit Configuration (offset 0x70) |
| AnnaBridge | 171:3a7713b1edbc | 510 | __IO uint32_t HW_CFG; // Hardware Configuration (offset 0x74) |
| AnnaBridge | 171:3a7713b1edbc | 511 | __IO uint32_t RX_DP_CTL; // RX Datapath Control (offset 0x78) |
| AnnaBridge | 171:3a7713b1edbc | 512 | __I uint32_t RX_FIFO_INF; // Receive FIFO Information (offset 0x7C) |
| AnnaBridge | 171:3a7713b1edbc | 513 | __I uint32_t TX_FIFO_INF; // Transmit FIFO Information (offset 0x80) |
| AnnaBridge | 171:3a7713b1edbc | 514 | __IO uint32_t PMT_CTRL; // Power Management Control (offset 0x84) |
| AnnaBridge | 171:3a7713b1edbc | 515 | __IO uint32_t GPIO_CFG; // General Purpose IO Configuration (offset 0x88) |
| AnnaBridge | 171:3a7713b1edbc | 516 | __IO uint32_t GPT_CFG; // General Purpose Timer Configuration (offset 0x8C) |
| AnnaBridge | 171:3a7713b1edbc | 517 | __I uint32_t GPT_CNT; // General Purpose Timer Count (offset 0x90) |
| AnnaBridge | 171:3a7713b1edbc | 518 | uint32_t RESERVED4; // Reserved for future use (offset 0x94) |
| AnnaBridge | 171:3a7713b1edbc | 519 | __IO uint32_t ENDIAN; // WORD SWAP Register (offset 0x98) |
| AnnaBridge | 171:3a7713b1edbc | 520 | __I uint32_t FREE_RUN; // Free Run Counter (offset 0x9C) |
| AnnaBridge | 171:3a7713b1edbc | 521 | __I uint32_t RX_DROP; // RX Dropped Frames Counter (offset 0xA0) |
| AnnaBridge | 171:3a7713b1edbc | 522 | __IO uint32_t MAC_CSR_CMD; // MAC CSR Synchronizer Command (offset 0xA4) |
| AnnaBridge | 171:3a7713b1edbc | 523 | __IO uint32_t MAC_CSR_DATA; // MAC CSR Synchronizer Data (offset 0xA8) |
| AnnaBridge | 171:3a7713b1edbc | 524 | __IO uint32_t AFC_CFG; // Automatic Flow Control Configuration (offset 0xAC) |
| AnnaBridge | 171:3a7713b1edbc | 525 | __IO uint32_t E2P_CMD; // EEPROM Command (offset 0xB0) |
| AnnaBridge | 171:3a7713b1edbc | 526 | __IO uint32_t E2P_DATA; // EEPROM Data (offset 0xB4) |
| AnnaBridge | 171:3a7713b1edbc | 527 | |
| AnnaBridge | 171:3a7713b1edbc | 528 | } SMSC9220_TypeDef; |
| AnnaBridge | 171:3a7713b1edbc | 529 | |
| AnnaBridge | 171:3a7713b1edbc | 530 | // SMSC9220 MAC Registers Indices |
| AnnaBridge | 171:3a7713b1edbc | 531 | #define SMSC9220_MAC_CR 0x1 |
| AnnaBridge | 171:3a7713b1edbc | 532 | #define SMSC9220_MAC_ADDRH 0x2 |
| AnnaBridge | 171:3a7713b1edbc | 533 | #define SMSC9220_MAC_ADDRL 0x3 |
| AnnaBridge | 171:3a7713b1edbc | 534 | #define SMSC9220_MAC_HASHH 0x4 |
| AnnaBridge | 171:3a7713b1edbc | 535 | #define SMSC9220_MAC_HASHL 0x5 |
| AnnaBridge | 171:3a7713b1edbc | 536 | #define SMSC9220_MAC_MII_ACC 0x6 |
| AnnaBridge | 171:3a7713b1edbc | 537 | #define SMSC9220_MAC_MII_DATA 0x7 |
| AnnaBridge | 171:3a7713b1edbc | 538 | #define SMSC9220_MAC_FLOW 0x8 |
| AnnaBridge | 171:3a7713b1edbc | 539 | #define SMSC9220_MAC_VLAN1 0x9 |
| AnnaBridge | 171:3a7713b1edbc | 540 | #define SMSC9220_MAC_VLAN2 0xA |
| AnnaBridge | 171:3a7713b1edbc | 541 | #define SMSC9220_MAC_WUFF 0xB |
| AnnaBridge | 171:3a7713b1edbc | 542 | #define SMSC9220_MAC_WUCSR 0xC |
| AnnaBridge | 171:3a7713b1edbc | 543 | |
| AnnaBridge | 171:3a7713b1edbc | 544 | // SMSC9220 PHY Registers Indices |
| AnnaBridge | 171:3a7713b1edbc | 545 | #define SMSC9220_PHY_BCONTROL 0x0 |
| AnnaBridge | 171:3a7713b1edbc | 546 | #define SMSC9220_PHY_BSTATUS 0x1 |
| AnnaBridge | 171:3a7713b1edbc | 547 | #define SMSC9220_PHY_ID1 0x2 |
| AnnaBridge | 171:3a7713b1edbc | 548 | #define SMSC9220_PHY_ID2 0x3 |
| AnnaBridge | 171:3a7713b1edbc | 549 | #define SMSC9220_PHY_ANEG_ADV 0x4 |
| AnnaBridge | 171:3a7713b1edbc | 550 | #define SMSC9220_PHY_ANEG_LPA 0x5 |
| AnnaBridge | 171:3a7713b1edbc | 551 | #define SMSC9220_PHY_ANEG_EXP 0x6 |
| AnnaBridge | 171:3a7713b1edbc | 552 | #define SMSC9220_PHY_MCONTROL 0x17 |
| AnnaBridge | 171:3a7713b1edbc | 553 | #define SMSC9220_PHY_MSTATUS 0x18 |
| AnnaBridge | 171:3a7713b1edbc | 554 | #define SMSC9220_PHY_CSINDICATE 0x27 |
| AnnaBridge | 171:3a7713b1edbc | 555 | #define SMSC9220_PHY_INTSRC 0x29 |
| AnnaBridge | 171:3a7713b1edbc | 556 | #define SMSC9220_PHY_INTMASK 0x30 |
| AnnaBridge | 171:3a7713b1edbc | 557 | #define SMSC9220_PHY_CS 0x31 |
| AnnaBridge | 171:3a7713b1edbc | 558 | |
| AnnaBridge | 171:3a7713b1edbc | 559 | /******************************************************************************/ |
| AnnaBridge | 171:3a7713b1edbc | 560 | /* Peripheral memory map */ |
| AnnaBridge | 171:3a7713b1edbc | 561 | /******************************************************************************/ |
| AnnaBridge | 171:3a7713b1edbc | 562 | |
| AnnaBridge | 171:3a7713b1edbc | 563 | #define MPS2_SSP1_BASE (0x40020000ul) /* User SSP Base Address */ |
| AnnaBridge | 171:3a7713b1edbc | 564 | #define MPS2_SSP0_BASE (0x40021000ul) /* CLCD SSP Base Address */ |
| AnnaBridge | 171:3a7713b1edbc | 565 | #define MPS2_TSC_I2C_BASE (0x40022000ul) /* Touch Screen I2C Base Address */ |
| AnnaBridge | 171:3a7713b1edbc | 566 | #define MPS2_AAIC_I2C_BASE (0x40023000ul) /* Audio Interface I2C Base Address */ |
| AnnaBridge | 171:3a7713b1edbc | 567 | #define MPS2_AAIC_I2S_BASE (0x40024000ul) /* Audio Interface I2S Base Address */ |
| AnnaBridge | 171:3a7713b1edbc | 568 | #define MPS2_SSP2_BASE (0x40025000ul) /* adc SSP Base Address */ |
| AnnaBridge | 171:3a7713b1edbc | 569 | #define MPS2_SSP3_BASE (0x40026000ul) /* Shield 0 SSP Base Address */ |
| AnnaBridge | 171:3a7713b1edbc | 570 | #define MPS2_SSP4_BASE (0x40027000ul) /* Shield 1 SSP Base Address */ |
| AnnaBridge | 171:3a7713b1edbc | 571 | #define MPS2_FPGAIO_BASE (0x40028000ul) /* FPGAIO Base Address */ |
| AnnaBridge | 171:3a7713b1edbc | 572 | #define MPS2_SHIELD0_I2C_BASE (0x40029000ul) /* Shield 0 I2C Base Address */ |
| AnnaBridge | 171:3a7713b1edbc | 573 | #define MPS2_SHIELD1_I2C_BASE (0x4002A000ul) /* Shield 1 I2C Base Address */ |
| AnnaBridge | 171:3a7713b1edbc | 574 | #define MPS2_SCC_BASE (0x4002F000ul) /* SCC Base Address */ |
| AnnaBridge | 171:3a7713b1edbc | 575 | |
| AnnaBridge | 171:3a7713b1edbc | 576 | #ifdef CORTEX_M7 |
| AnnaBridge | 171:3a7713b1edbc | 577 | #define SMSC9220_BASE (0xA0000000ul) /* Ethernet SMSC9220 Base Address */ |
| AnnaBridge | 171:3a7713b1edbc | 578 | #else |
| AnnaBridge | 171:3a7713b1edbc | 579 | #define SMSC9220_BASE (0x40200000ul) /* Ethernet SMSC9220 Base Address */ |
| AnnaBridge | 171:3a7713b1edbc | 580 | #endif |
| AnnaBridge | 171:3a7713b1edbc | 581 | |
| AnnaBridge | 171:3a7713b1edbc | 582 | #define MPS2_VGA_TEXT_BUFFER (0x41000000ul) /* VGA Text Buffer Address */ |
| AnnaBridge | 171:3a7713b1edbc | 583 | #define MPS2_VGA_BUFFER (0x41100000ul) /* VGA Buffer Base Address */ |
| AnnaBridge | 171:3a7713b1edbc | 584 | |
| AnnaBridge | 171:3a7713b1edbc | 585 | /******************************************************************************/ |
| AnnaBridge | 171:3a7713b1edbc | 586 | /* Peripheral declaration */ |
| AnnaBridge | 171:3a7713b1edbc | 587 | /******************************************************************************/ |
| AnnaBridge | 171:3a7713b1edbc | 588 | |
| AnnaBridge | 171:3a7713b1edbc | 589 | #define SMSC9220 ((SMSC9220_TypeDef *) SMSC9220_BASE ) |
| AnnaBridge | 171:3a7713b1edbc | 590 | #define MPS2_TS_I2C ((MPS2_I2C_TypeDef *) MPS2_TSC_I2C_BASE ) |
| AnnaBridge | 171:3a7713b1edbc | 591 | #define MPS2_AAIC_I2C ((MPS2_I2C_TypeDef *) MPS2_AAIC_I2C_BASE ) |
| AnnaBridge | 171:3a7713b1edbc | 592 | #define MPS2_SHIELD0_I2C ((MPS2_I2C_TypeDef *) MPS2_SHIELD0_I2C_BASE ) |
| AnnaBridge | 171:3a7713b1edbc | 593 | #define MPS2_SHIELD1_I2C ((MPS2_I2C_TypeDef *) MPS2_SHIELD1_I2C_BASE ) |
| AnnaBridge | 171:3a7713b1edbc | 594 | #define MPS2_AAIC_I2S ((MPS2_I2S_TypeDef *) MPS2_AAIC_I2S_BASE ) |
| AnnaBridge | 171:3a7713b1edbc | 595 | #define MPS2_FPGAIO ((MPS2_FPGAIO_TypeDef *) MPS2_FPGAIO_BASE ) |
| AnnaBridge | 171:3a7713b1edbc | 596 | #define MPS2_SCC ((MPS2_SCC_TypeDef *) MPS2_SCC_BASE ) |
| AnnaBridge | 171:3a7713b1edbc | 597 | #define MPS2_SSP0 ((MPS2_SSP_TypeDef *) MPS2_SSP0_BASE ) |
| AnnaBridge | 171:3a7713b1edbc | 598 | #define MPS2_SSP1 ((MPS2_SSP_TypeDef *) MPS2_SSP1_BASE ) |
| AnnaBridge | 171:3a7713b1edbc | 599 | #define MPS2_SSP2 ((MPS2_SSP_TypeDef *) MPS2_SSP2_BASE ) |
| AnnaBridge | 171:3a7713b1edbc | 600 | #define MPS2_SSP3 ((MPS2_SSP_TypeDef *) MPS2_SSP3_BASE ) |
| AnnaBridge | 171:3a7713b1edbc | 601 | #define MPS2_SSP4 ((MPS2_SSP_TypeDef *) MPS2_SSP4_BASE ) |
| AnnaBridge | 171:3a7713b1edbc | 602 | |
| AnnaBridge | 171:3a7713b1edbc | 603 | /******************************************************************************/ |
| AnnaBridge | 171:3a7713b1edbc | 604 | /* General Function Definitions */ |
| AnnaBridge | 171:3a7713b1edbc | 605 | /******************************************************************************/ |
| AnnaBridge | 171:3a7713b1edbc | 606 | |
| AnnaBridge | 171:3a7713b1edbc | 607 | |
| AnnaBridge | 171:3a7713b1edbc | 608 | /******************************************************************************/ |
| AnnaBridge | 171:3a7713b1edbc | 609 | /* General MACRO Definitions */ |
| AnnaBridge | 171:3a7713b1edbc | 610 | /******************************************************************************/ |
| AnnaBridge | 171:3a7713b1edbc | 611 | |
| AnnaBridge | 171:3a7713b1edbc | 612 | |
| AnnaBridge | 171:3a7713b1edbc | 613 | |
| AnnaBridge | 171:3a7713b1edbc | 614 | #endif /* __SMM_MPS2_H */ |
