mbed official / mbed

The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

Dependents:   hello SerialTestv11 SerialTestv12 Sierpinski ... more

mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_ARM_BEETLE_SOC/TOOLCHAIN_IAR/spi_def.h@171:3a7713b1edbc, 2018-11-08 (annotated)

Committer:
AnnaBridge
Date:
Thu Nov 08 11:45:42 2018 +0000
Revision:
171:3a7713b1edbc
mbed library. Release version 164

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 171:3a7713b1edbc 1 /* mbed Microcontroller Library
AnnaBridge 171:3a7713b1edbc 2 * Copyright (c) 2015 ARM Limited
AnnaBridge 171:3a7713b1edbc 3 *
AnnaBridge 171:3a7713b1edbc 4 * Licensed under the Apache License, Version 2.0 (the "License");
AnnaBridge 171:3a7713b1edbc 5 * you may not use this file except in compliance with the License.
AnnaBridge 171:3a7713b1edbc 6 * You may obtain a copy of the License at
AnnaBridge 171:3a7713b1edbc 7 *
AnnaBridge 171:3a7713b1edbc 8 * http://www.apache.org/licenses/LICENSE-2.0
AnnaBridge 171:3a7713b1edbc 9 *
AnnaBridge 171:3a7713b1edbc 10 * Unless required by applicable law or agreed to in writing, software
AnnaBridge 171:3a7713b1edbc 11 * distributed under the License is distributed on an "AS IS" BASIS,
AnnaBridge 171:3a7713b1edbc 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
AnnaBridge 171:3a7713b1edbc 13 * See the License for the specific language governing permissions and
AnnaBridge 171:3a7713b1edbc 14 * limitations under the License.
AnnaBridge 171:3a7713b1edbc 15 */
AnnaBridge 171:3a7713b1edbc 16 /*
AnnaBridge 171:3a7713b1edbc 17 * SSP interface Support
AnnaBridge 171:3a7713b1edbc 18 * =====================
AnnaBridge 171:3a7713b1edbc 19 */
AnnaBridge 171:3a7713b1edbc 20
AnnaBridge 171:3a7713b1edbc 21 #ifndef MBED_SPI_DEF_H
AnnaBridge 171:3a7713b1edbc 22 #define MBED_SPI_DEF_H
AnnaBridge 171:3a7713b1edbc 23
AnnaBridge 171:3a7713b1edbc 24 #include <stdint.h> /* standard types definitions */
AnnaBridge 171:3a7713b1edbc 25
AnnaBridge 171:3a7713b1edbc 26 #define Module_ID 0x00090108
AnnaBridge 171:3a7713b1edbc 27
AnnaBridge 171:3a7713b1edbc 28 typedef struct beetle_spi
AnnaBridge 171:3a7713b1edbc 29 {
AnnaBridge 171:3a7713b1edbc 30 __IO uint32_t CONFIG; /* 0x00 RW Configuration Register */
AnnaBridge 171:3a7713b1edbc 31 __I uint32_t IRQ_STATUS; /* 0x04 RO Interrupt Status Register*/
AnnaBridge 171:3a7713b1edbc 32 __O uint32_t IRQ_ENABLE; /* 0x08 WO Interrupt Enable Register*/
AnnaBridge 171:3a7713b1edbc 33 __O uint32_t IRQ_DISABLE; /* 0x0C WO Interrupt Disable Register */
AnnaBridge 171:3a7713b1edbc 34 __I uint32_t IRQ_MASK; /* 0x10 RO Interrupt Mask Register */
AnnaBridge 171:3a7713b1edbc 35 __IO uint32_t SPI_ENABLE; /* 0x14 RW SPI Enable Register */
AnnaBridge 171:3a7713b1edbc 36 __IO uint32_t DELAY; /* 0x18 RW Delay Register */
AnnaBridge 171:3a7713b1edbc 37 __O uint32_t TX_DATA; /* 0x1C WO Transmit Data Register */
AnnaBridge 171:3a7713b1edbc 38 __I uint32_t RX_DATA; /* 0x20 RO Receive Data Register */
AnnaBridge 171:3a7713b1edbc 39 __IO uint32_t SLAVE_IDLE_COUNT; /* 0x24 RW Slave Idle Count Register */
AnnaBridge 171:3a7713b1edbc 40 __IO uint32_t TX_THRESHOLD; /* 0x28 RW TX Threshold Register */
AnnaBridge 171:3a7713b1edbc 41 __IO uint32_t RX_THRESHOLD; /* 0x2C RW RX Threshold Register */
AnnaBridge 171:3a7713b1edbc 42 uint32_t reserved[208];
AnnaBridge 171:3a7713b1edbc 43 __I uint32_t MID; /* 0xFC RO Module ID Register */
AnnaBridge 171:3a7713b1edbc 44 }SPI_TypeDef;
AnnaBridge 171:3a7713b1edbc 45
AnnaBridge 171:3a7713b1edbc 46
AnnaBridge 171:3a7713b1edbc 47 #define SPI0_BASE (0x4000C000ul) /* Shield Header SPI Base Address */
AnnaBridge 171:3a7713b1edbc 48 #define SPI1_BASE (0x4000D000ul) /* ADC SPI Base Address */
AnnaBridge 171:3a7713b1edbc 49
AnnaBridge 171:3a7713b1edbc 50 #define SHIELD_SPI ((SPI_TypeDef *) SPI0_BASE )
AnnaBridge 171:3a7713b1edbc 51 #define ADC_SPI ((SPI_TypeDef *) SPI1_BASE )
AnnaBridge 171:3a7713b1edbc 52
AnnaBridge 171:3a7713b1edbc 53 /* Configuration Register Bit Masks */
AnnaBridge 171:3a7713b1edbc 54 #define CONFIG_MSEL 0x00001 // Bit [00] MSEL Mode Select
AnnaBridge 171:3a7713b1edbc 55 #define CONFIG_CPOL 0x00002 // Bit [01] CPOL External Clock Edge
AnnaBridge 171:3a7713b1edbc 56 #define CONFIG_CPHA 0x00004 // Bit [02] CPHA Clock Phase
AnnaBridge 171:3a7713b1edbc 57 #define CONFIG_MBRD 0x00038 // Bits [05:03] MBRD Master Baud Rate Divisor (2 to 256)
AnnaBridge 171:3a7713b1edbc 58 #define CONFIG_MBRD_0 0x00008
AnnaBridge 171:3a7713b1edbc 59 #define CONFIG_MBRD_1 0x00010
AnnaBridge 171:3a7713b1edbc 60 #define CONFIG_MBRD_2 0x00020
AnnaBridge 171:3a7713b1edbc 61 #define CONFIG_MBRD_SHIFT 3
AnnaBridge 171:3a7713b1edbc 62 #define CONFIG_TWS 0x000C0 // Bits [07:06] TWS Transfer Word Size
AnnaBridge 171:3a7713b1edbc 63 #define CONFIG_TWS_0 0x00000
AnnaBridge 171:3a7713b1edbc 64 #define CONFIG_TWS_1 0x00040
AnnaBridge 171:3a7713b1edbc 65 #define CONFIG_MRCS 0x00100 // Bit [08] MRCS Reference Clock Select
AnnaBridge 171:3a7713b1edbc 66 #define CONFIG_PSD 0x00200 // Bit [09] PSD Peripheral Select Decode
AnnaBridge 171:3a7713b1edbc 67 #define CONFIG_PCSL 0x03C00 // Bits [13:10] PCSL Peripheral Chip Select Lines (master mode only)
AnnaBridge 171:3a7713b1edbc 68 #define CONFIG_MCSE 0x04000 // Bit [14] MCSE Manual Chip Select Enable
AnnaBridge 171:3a7713b1edbc 69 #define CONFIG_MSE 0x08000 // Bit [15] MSE Manual Start Enable
AnnaBridge 171:3a7713b1edbc 70 #define CONFIG_MSC 0x10000 // Bit [16] MSC Manual Start Command
AnnaBridge 171:3a7713b1edbc 71 #define CONFIG_MFGE 0x20000 // Bit [17] MFGE Mode Fail Generation Enable
AnnaBridge 171:3a7713b1edbc 72 #define CONFIG_SPSE 0x40000 // Bit [18] SPSE Sample Point Shift Enable
AnnaBridge 171:3a7713b1edbc 73
AnnaBridge 171:3a7713b1edbc 74 /* Interrupt Status Register Bit Masks */
AnnaBridge 171:3a7713b1edbc 75 #define IRQ_STATUS_ROF 0x01 // Bit [00] ROF RX FIFO Overflow
AnnaBridge 171:3a7713b1edbc 76 #define IRQ_STATUS_MF 0x02 // Bit [01] MF Mode Fail
AnnaBridge 171:3a7713b1edbc 77 #define IRQ_STATUS_TNF 0x04 // Bit [02] TNF TX FIFO Not Full (current FIFO status)
AnnaBridge 171:3a7713b1edbc 78 #define IRQ_STATUS_TF 0x08 // Bit [03] TF TX FIFO Full (current FIFO status)
AnnaBridge 171:3a7713b1edbc 79 #define IRQ_STATUS_RNE 0x10 // Bit [04] RNE RX FIFO Not Empty (current FIFO status)
AnnaBridge 171:3a7713b1edbc 80 #define IRQ_STATUS_RF 0x20 // Bit [05] RF RX FIFO Full (current FIFO status)
AnnaBridge 171:3a7713b1edbc 81 #define IRQ_STATUS_TUF 0x40 // Bit [06] TUF TX FIFO Underflow
AnnaBridge 171:3a7713b1edbc 82
AnnaBridge 171:3a7713b1edbc 83 /* Interrupt Enable Register Bit Masks */
AnnaBridge 171:3a7713b1edbc 84 #define IRQ_ENABLE_ROFE 0x01 // Bit [00] ROFE RX FIFO Overflow Enable
AnnaBridge 171:3a7713b1edbc 85 #define IRQ_ENABLE_MFE 0x02 // Bit [01] MFE Mode Fail Enable
AnnaBridge 171:3a7713b1edbc 86 #define IRQ_ENABLE_TNFE 0x04 // Bit [02] TNFE TX FIFO Not Full Enable
AnnaBridge 171:3a7713b1edbc 87 #define IRQ_ENABLE_TFE 0x08 // Bit [03] TFE TX FIFO Full Enable
AnnaBridge 171:3a7713b1edbc 88 #define IRQ_ENABLE_RNEE 0x10 // Bit [04] RNEE RX FIFO Not Empty Enable
AnnaBridge 171:3a7713b1edbc 89 #define IRQ_ENABLE_RFE 0x20 // Bit [05] RFE RX FIFO Full Enable
AnnaBridge 171:3a7713b1edbc 90 #define IRQ_ENABLE_TUFE 0x40 // Bit [06] TUFE TX FIFO Underflow Enable
AnnaBridge 171:3a7713b1edbc 91
AnnaBridge 171:3a7713b1edbc 92 /* Interrupt Disable Register Bit Masks */
AnnaBridge 171:3a7713b1edbc 93 #define IRQ_DISABLE_ROFD 0x01 // Bit [00] ROFD RX FIFO Overflow Disable
AnnaBridge 171:3a7713b1edbc 94 #define IRQ_DISABLE_MFD 0x02 // Bit [01] MFD Mode Fail Disable
AnnaBridge 171:3a7713b1edbc 95 #define IRQ_DISABLE_TNFD 0x04 // Bit [02] TNFD TX FIFO Not Full Disable
AnnaBridge 171:3a7713b1edbc 96 #define IRQ_DISABLE_TFD 0x08 // Bit [03] TFD TX FIFO Full Disable
AnnaBridge 171:3a7713b1edbc 97 #define IRQ_DISABLE_RNED 0x10 // Bit [04] RNED RX FIFO Not Empty Disable
AnnaBridge 171:3a7713b1edbc 98 #define IRQ_DISABLE_RFD 0x20 // Bit [05] RFD RX FIFO Full Disable
AnnaBridge 171:3a7713b1edbc 99 #define IRQ_DISABLE_TUFD 0x40 // Bit [06] TUFD TX FIFO Underflow Disable
AnnaBridge 171:3a7713b1edbc 100
AnnaBridge 171:3a7713b1edbc 101 /* Interrupt Mask Register Bit Masks */
AnnaBridge 171:3a7713b1edbc 102 #define IRQ_MASK_ROFM 0x01 // Bit [00] ROFM RX FIFO Overflow Mask
AnnaBridge 171:3a7713b1edbc 103 #define IRQ_MASK_MFM 0x02 // Bit [01] MFM Mode Fail Mask
AnnaBridge 171:3a7713b1edbc 104 #define IRQ_MASK_TNFM 0x04 // Bit [02] TNFM TX FIFO Not Full Mask
AnnaBridge 171:3a7713b1edbc 105 #define IRQ_MASK_TFM 0x08 // Bit [03] TFM TX FIFO Full Mask
AnnaBridge 171:3a7713b1edbc 106 #define IRQ_MASK_RNEM 0x10 // Bit [04] RNEM RX FIFO Not Empty Mask
AnnaBridge 171:3a7713b1edbc 107 #define IRQ_MASK_RFM 0x20 // Bit [05] RFM RX FIFO Full Mask
AnnaBridge 171:3a7713b1edbc 108 #define IRQ_MASK_TUFM 0x40 // Bit [06] TUFM TX FIFO Underflow Mask
AnnaBridge 171:3a7713b1edbc 109
AnnaBridge 171:3a7713b1edbc 110 /* SPI Enable Register Bit Masks */
AnnaBridge 171:3a7713b1edbc 111 #define SPI_ENABLE_SPIE 0x01 // Bit [00] SPIE SPI Enable
AnnaBridge 171:3a7713b1edbc 112
AnnaBridge 171:3a7713b1edbc 113 /* Delay Register Bit Masks */
AnnaBridge 171:3a7713b1edbc 114 #define DELAY_D_INIT 0x000000FF // Bits [07:00] D_INIT Delay Init
AnnaBridge 171:3a7713b1edbc 115 #define DELAY_D_AFTER 0x0000FF00 // Bits [15:08] D_AFTER Delay After
AnnaBridge 171:3a7713b1edbc 116 #define DELAY_D_BTWN 0x00FF0000 // Bits [23:16] D_BTWN Delay Between
AnnaBridge 171:3a7713b1edbc 117 #define DELAY_D_NSS 0xFF000000 // Bits [31:24] D_NSS Delay NSS
AnnaBridge 171:3a7713b1edbc 118
AnnaBridge 171:3a7713b1edbc 119 /* Transmit Data Register Bit Masks */
AnnaBridge 171:3a7713b1edbc 120 #define TX_DATA_TDATA 0xFF
AnnaBridge 171:3a7713b1edbc 121
AnnaBridge 171:3a7713b1edbc 122 /* Receive Data Register Bit Masks */
AnnaBridge 171:3a7713b1edbc 123 #define RX_DATA_RDATA 0xFF
AnnaBridge 171:3a7713b1edbc 124
AnnaBridge 171:3a7713b1edbc 125 /* Slave Idle Count Register Bit Masks */
AnnaBridge 171:3a7713b1edbc 126 #define SLAVE_IDLE_COUNT_SICNT 0xFF // Bits [07:00] SICNT Slave Idle Count
AnnaBridge 171:3a7713b1edbc 127
AnnaBridge 171:3a7713b1edbc 128 /* TX Threshold Register Bit Masks */
AnnaBridge 171:3a7713b1edbc 129 #define TX_THRESHOLD_TTRSH 0x07 // Bits [N:00] TTRSH TX Threshold
AnnaBridge 171:3a7713b1edbc 130
AnnaBridge 171:3a7713b1edbc 131 /* RX Threshold Register Bit Masks */
AnnaBridge 171:3a7713b1edbc 132 #define RX_THRESHOLD_RTRSH 0x07 // Bits [N:00] RTRSH RX Threshold
AnnaBridge 171:3a7713b1edbc 133
AnnaBridge 171:3a7713b1edbc 134 #endif