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The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

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mbed 2

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TARGET_ARM_BEETLE_SOC/TOOLCHAIN_IAR/fcache_api.h@171:3a7713b1edbc, 2018-11-08 (annotated)

Committer:
AnnaBridge
Date:
Thu Nov 08 11:45:42 2018 +0000
Revision:
171:3a7713b1edbc
mbed library. Release version 164

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 171:3a7713b1edbc 1 /* mbed Microcontroller Library
AnnaBridge 171:3a7713b1edbc 2 * Copyright (c) 2015 ARM Limited
AnnaBridge 171:3a7713b1edbc 3 *
AnnaBridge 171:3a7713b1edbc 4 * Licensed under the Apache License, Version 2.0 (the "License");
AnnaBridge 171:3a7713b1edbc 5 * you may not use this file except in compliance with the License.
AnnaBridge 171:3a7713b1edbc 6 * You may obtain a copy of the License at
AnnaBridge 171:3a7713b1edbc 7 *
AnnaBridge 171:3a7713b1edbc 8 * http://www.apache.org/licenses/LICENSE-2.0
AnnaBridge 171:3a7713b1edbc 9 *
AnnaBridge 171:3a7713b1edbc 10 * Unless required by applicable law or agreed to in writing, software
AnnaBridge 171:3a7713b1edbc 11 * distributed under the License is distributed on an "AS IS" BASIS,
AnnaBridge 171:3a7713b1edbc 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
AnnaBridge 171:3a7713b1edbc 13 * See the License for the specific language governing permissions and
AnnaBridge 171:3a7713b1edbc 14 * limitations under the License.
AnnaBridge 171:3a7713b1edbc 15 */
AnnaBridge 171:3a7713b1edbc 16
AnnaBridge 171:3a7713b1edbc 17 #ifndef _FCACHE_DRV_H
AnnaBridge 171:3a7713b1edbc 18 #define _FCACHE_DRV_H
AnnaBridge 171:3a7713b1edbc 19
AnnaBridge 171:3a7713b1edbc 20 #ifdef __cplusplus
AnnaBridge 171:3a7713b1edbc 21
AnnaBridge 171:3a7713b1edbc 22 extern "C" {
AnnaBridge 171:3a7713b1edbc 23 #else
AnnaBridge 171:3a7713b1edbc 24 #include <stdio.h>
AnnaBridge 171:3a7713b1edbc 25 #endif
AnnaBridge 171:3a7713b1edbc 26
AnnaBridge 171:3a7713b1edbc 27 /* Flash Cache Address Map */
AnnaBridge 171:3a7713b1edbc 28 #define SYS_FCACHE_BASE 0x40003000
AnnaBridge 171:3a7713b1edbc 29 /* Configuration and Control Register */
AnnaBridge 171:3a7713b1edbc 30 #define SYS_FCACHE_CCR (SYS_FCACHE_BASE)
AnnaBridge 171:3a7713b1edbc 31 /* Status Register */
AnnaBridge 171:3a7713b1edbc 32 #define SYS_FCACHE_SR (SYS_FCACHE_BASE + 0x4)
AnnaBridge 171:3a7713b1edbc 33 /* Interrupt Req Status Register */
AnnaBridge 171:3a7713b1edbc 34 #define SYS_FCACHE_IRQSTAT (SYS_FCACHE_BASE + 0x8)
AnnaBridge 171:3a7713b1edbc 35 /* Cache Statistic Hit Register */
AnnaBridge 171:3a7713b1edbc 36 #define SYS_FCACHE_CSHR (SYS_FCACHE_BASE + 0x14)
AnnaBridge 171:3a7713b1edbc 37 /* Cache Statistic Miss Register */
AnnaBridge 171:3a7713b1edbc 38 #define SYS_FCACHE_CSMR (SYS_FCACHE_BASE + 0x18)
AnnaBridge 171:3a7713b1edbc 39
AnnaBridge 171:3a7713b1edbc 40 /* SYS_FCACHE_CCR (RW): Configuration and Control Register */
AnnaBridge 171:3a7713b1edbc 41 #define FCACHE_EN 1 /* FCache Enable */
AnnaBridge 171:3a7713b1edbc 42 #define FCACHE_INV_REQ (1 << 1) /* Manual Invalidate Request */
AnnaBridge 171:3a7713b1edbc 43 #define FCACHE_POW_REQ (1 << 2) /* Manual SRAM Power Request */
AnnaBridge 171:3a7713b1edbc 44 #define FCACHE_SET_MAN_POW (1 << 3) /* Power Control Setting */
AnnaBridge 171:3a7713b1edbc 45 #define FCACHE_SET_MAN_INV (1 << 4) /* Invalidate Control Setting */
AnnaBridge 171:3a7713b1edbc 46 #define FCACHE_SET_PREFETCH (1 << 5) /* Cache Prefetch Setting */
AnnaBridge 171:3a7713b1edbc 47 #define FCACHE_STATISTIC_EN (1 << 6) /* Enable Statistics Logic */
AnnaBridge 171:3a7713b1edbc 48
AnnaBridge 171:3a7713b1edbc 49 /* SYS_FCACHE_SR (RO): Status Register */
AnnaBridge 171:3a7713b1edbc 50 #define FCACHE_CS 0x3 /* Cache Status Mask */
AnnaBridge 171:3a7713b1edbc 51 #define FCACHE_CS_DISABLED 0x0
AnnaBridge 171:3a7713b1edbc 52 #define FCACHE_CS_ENABLING 0x1
AnnaBridge 171:3a7713b1edbc 53 #define FCACHE_CS_ENABLED 0x2
AnnaBridge 171:3a7713b1edbc 54 #define FCACHE_CS_DISABLING 0x3
AnnaBridge 171:3a7713b1edbc 55 #define FCACHE_INV_STAT 0x4 /* Invalidating Status */
AnnaBridge 171:3a7713b1edbc 56 #define FCACHE_POW_STAT 0x10 /* SRAM Power Ack */
AnnaBridge 171:3a7713b1edbc 57
AnnaBridge 171:3a7713b1edbc 58 /* SYS_FCACHE_IRQSTAT (RW): Interrupt Req Status Register */
AnnaBridge 171:3a7713b1edbc 59 #define FCACHE_POW_ERR 1 /* SRAM Power Error */
AnnaBridge 171:3a7713b1edbc 60 #define FCACHE_MAN_INV_ERR (1 << 1) /* Manual Invalidation error status */
AnnaBridge 171:3a7713b1edbc 61
AnnaBridge 171:3a7713b1edbc 62 /* Macros */
AnnaBridge 171:3a7713b1edbc 63 #define FCache_Readl(reg) *(volatile unsigned int *)reg
AnnaBridge 171:3a7713b1edbc 64 #define FCache_Writel(reg, val) *(volatile unsigned int *)reg = val;
AnnaBridge 171:3a7713b1edbc 65
AnnaBridge 171:3a7713b1edbc 66 /* Functions */
AnnaBridge 171:3a7713b1edbc 67
AnnaBridge 171:3a7713b1edbc 68 /*
AnnaBridge 171:3a7713b1edbc 69 * FCache_DriverInitialize: flash cache driver initialize funtion
AnnaBridge 171:3a7713b1edbc 70 */
AnnaBridge 171:3a7713b1edbc 71 void FCache_DriverInitialize(void);
AnnaBridge 171:3a7713b1edbc 72
AnnaBridge 171:3a7713b1edbc 73 /*
AnnaBridge 171:3a7713b1edbc 74 * FCache_Enable: Enables the flash cache mode
AnnaBridge 171:3a7713b1edbc 75 * mode: supported modes:
AnnaBridge 171:3a7713b1edbc 76 * 0 - auto-power auto-invalidate
AnnaBridge 171:3a7713b1edbc 77 * 1 - manual-power, manual-invalidate
AnnaBridge 171:3a7713b1edbc 78 */
AnnaBridge 171:3a7713b1edbc 79 void FCache_Enable(int mode);
AnnaBridge 171:3a7713b1edbc 80
AnnaBridge 171:3a7713b1edbc 81 /*
AnnaBridge 171:3a7713b1edbc 82 * FCache_Disable: Disables the flash cache mode previously enabled
AnnaBridge 171:3a7713b1edbc 83 */
AnnaBridge 171:3a7713b1edbc 84 void FCache_Disable(void);
AnnaBridge 171:3a7713b1edbc 85
AnnaBridge 171:3a7713b1edbc 86 /*
AnnaBridge 171:3a7713b1edbc 87 * FCache_Invalidate: to be invalidated the cache needs to be disabled.
AnnaBridge 171:3a7713b1edbc 88 * return -1: flash cannot be disabled
AnnaBridge 171:3a7713b1edbc 89 * -2: flash cannot be enabled
AnnaBridge 171:3a7713b1edbc 90 */
AnnaBridge 171:3a7713b1edbc 91 int FCache_Invalidate(void);
AnnaBridge 171:3a7713b1edbc 92
AnnaBridge 171:3a7713b1edbc 93 /*
AnnaBridge 171:3a7713b1edbc 94 * FCache_GetStats: provides cache stats
AnnaBridge 171:3a7713b1edbc 95 */
AnnaBridge 171:3a7713b1edbc 96 unsigned int * FCache_GetStats(void);
AnnaBridge 171:3a7713b1edbc 97
AnnaBridge 171:3a7713b1edbc 98 /*
AnnaBridge 171:3a7713b1edbc 99 * FCache_isEnabled: returns 1 if FCache is enabled
AnnaBridge 171:3a7713b1edbc 100 */
AnnaBridge 171:3a7713b1edbc 101 unsigned int FCache_isEnabled(void);
AnnaBridge 171:3a7713b1edbc 102
AnnaBridge 171:3a7713b1edbc 103 #ifdef __cplusplus
AnnaBridge 171:3a7713b1edbc 104 }
AnnaBridge 171:3a7713b1edbc 105 #endif
AnnaBridge 171:3a7713b1edbc 106 #endif /* _FCACHE_DRV_H */