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TARGET_ARM_BEETLE_SOC/TOOLCHAIN_IAR/CMSDK_BEETLE.h@171:3a7713b1edbc, 2018-11-08 (annotated)

Committer:
AnnaBridge
Date:
Thu Nov 08 11:45:42 2018 +0000
Revision:
171:3a7713b1edbc
mbed library. Release version 164

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 171:3a7713b1edbc 1 /*
AnnaBridge 171:3a7713b1edbc 2 * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
AnnaBridge 171:3a7713b1edbc 3 *
AnnaBridge 171:3a7713b1edbc 4 * SPDX-License-Identifier: Apache-2.0
AnnaBridge 171:3a7713b1edbc 5 *
AnnaBridge 171:3a7713b1edbc 6 * Licensed under the Apache License, Version 2.0 (the License); you may
AnnaBridge 171:3a7713b1edbc 7 * not use this file except in compliance with the License.
AnnaBridge 171:3a7713b1edbc 8 * You may obtain a copy of the License at
AnnaBridge 171:3a7713b1edbc 9 *
AnnaBridge 171:3a7713b1edbc 10 * http://www.apache.org/licenses/LICENSE-2.0
AnnaBridge 171:3a7713b1edbc 11 *
AnnaBridge 171:3a7713b1edbc 12 * Unless required by applicable law or agreed to in writing, software
AnnaBridge 171:3a7713b1edbc 13 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
AnnaBridge 171:3a7713b1edbc 14 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
AnnaBridge 171:3a7713b1edbc 15 * See the License for the specific language governing permissions and
AnnaBridge 171:3a7713b1edbc 16 * limitations under the License.
AnnaBridge 171:3a7713b1edbc 17 */
AnnaBridge 171:3a7713b1edbc 18 /*
AnnaBridge 171:3a7713b1edbc 19 * This file is derivative of CMSIS V5.00 ARMCM3.h
AnnaBridge 171:3a7713b1edbc 20 */
AnnaBridge 171:3a7713b1edbc 21
AnnaBridge 171:3a7713b1edbc 22
AnnaBridge 171:3a7713b1edbc 23 #ifndef CMSDK_BEETLE_H
AnnaBridge 171:3a7713b1edbc 24 #define CMSDK_BEETLE_H
AnnaBridge 171:3a7713b1edbc 25
AnnaBridge 171:3a7713b1edbc 26 #ifdef __cplusplus
AnnaBridge 171:3a7713b1edbc 27 extern "C" {
AnnaBridge 171:3a7713b1edbc 28 #endif
AnnaBridge 171:3a7713b1edbc 29
AnnaBridge 171:3a7713b1edbc 30
AnnaBridge 171:3a7713b1edbc 31 /* ------------------------- Interrupt Number Definition ------------------------ */
AnnaBridge 171:3a7713b1edbc 32
AnnaBridge 171:3a7713b1edbc 33 typedef enum IRQn
AnnaBridge 171:3a7713b1edbc 34 {
AnnaBridge 171:3a7713b1edbc 35 /* ------------------- Cortex-M3 Processor Exceptions Numbers ------------------- */
AnnaBridge 171:3a7713b1edbc 36 NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */
AnnaBridge 171:3a7713b1edbc 37 HardFault_IRQn = -13, /* 3 HardFault Interrupt */
AnnaBridge 171:3a7713b1edbc 38 MemoryManagement_IRQn = -12, /* 4 Memory Management Interrupt */
AnnaBridge 171:3a7713b1edbc 39 BusFault_IRQn = -11, /* 5 Bus Fault Interrupt */
AnnaBridge 171:3a7713b1edbc 40 UsageFault_IRQn = -10, /* 6 Usage Fault Interrupt */
AnnaBridge 171:3a7713b1edbc 41 SVCall_IRQn = -5, /* 11 SV Call Interrupt */
AnnaBridge 171:3a7713b1edbc 42 DebugMonitor_IRQn = -4, /* 12 Debug Monitor Interrupt */
AnnaBridge 171:3a7713b1edbc 43 PendSV_IRQn = -2, /* 14 Pend SV Interrupt */
AnnaBridge 171:3a7713b1edbc 44 SysTick_IRQn = -1, /* 15 System Tick Interrupt */
AnnaBridge 171:3a7713b1edbc 45
AnnaBridge 171:3a7713b1edbc 46 /* --------------------- CMSDK_BEETLE Specific Interrupt Numbers ---------------- */
AnnaBridge 171:3a7713b1edbc 47 UART0_IRQn = 0, /* UART 0 RX and TX Combined Interrupt */
AnnaBridge 171:3a7713b1edbc 48 Spare_IRQn = 1, /* Undefined */
AnnaBridge 171:3a7713b1edbc 49 UART1_IRQn = 2, /* UART 1 RX and TX Combined Interrupt */
AnnaBridge 171:3a7713b1edbc 50 I2C0_IRQn = 3, /* I2C 0 Interrupt */
AnnaBridge 171:3a7713b1edbc 51 I2C1_IRQn = 4, /* I2C 1 Interrupt */
AnnaBridge 171:3a7713b1edbc 52 RTC_IRQn = 5, /* RTC Interrupt */
AnnaBridge 171:3a7713b1edbc 53 PORT0_ALL_IRQn = 6, /* GPIO Port 0 combined Interrupt */
AnnaBridge 171:3a7713b1edbc 54 PORT1_ALL_IRQn = 7, /* GPIO Port 1 combined Interrupt */
AnnaBridge 171:3a7713b1edbc 55 TIMER0_IRQn = 8, /* TIMER 0 Interrupt */
AnnaBridge 171:3a7713b1edbc 56 TIMER1_IRQn = 9, /* TIMER 1 Interrupt */
AnnaBridge 171:3a7713b1edbc 57 DUALTIMER_IRQn = 10, /* Dual Timer Interrupt */
AnnaBridge 171:3a7713b1edbc 58 SPI0_IRQn = 11, /* SPI 0 Interrupt */
AnnaBridge 171:3a7713b1edbc 59 UARTOVF_IRQn = 12, /* UART 0,1,2 Overflow Interrupt */
AnnaBridge 171:3a7713b1edbc 60 SPI1_IRQn = 13, /* SPI 1 Interrupt */
AnnaBridge 171:3a7713b1edbc 61 QSPI_IRQn = 14, /* QUAD SPI Interrupt */
AnnaBridge 171:3a7713b1edbc 62 DMA_IRQn = 15, /* Reserved for DMA Interrup */
AnnaBridge 171:3a7713b1edbc 63 PORT0_0_IRQn = 16, /* All P0 I/O pins used as irq source */
AnnaBridge 171:3a7713b1edbc 64 PORT0_1_IRQn = 17, /* There are 16 pins in total */
AnnaBridge 171:3a7713b1edbc 65 PORT0_2_IRQn = 18,
AnnaBridge 171:3a7713b1edbc 66 PORT0_3_IRQn = 19,
AnnaBridge 171:3a7713b1edbc 67 PORT0_4_IRQn = 20,
AnnaBridge 171:3a7713b1edbc 68 PORT0_5_IRQn = 21,
AnnaBridge 171:3a7713b1edbc 69 PORT0_6_IRQn = 22,
AnnaBridge 171:3a7713b1edbc 70 PORT0_7_IRQn = 23,
AnnaBridge 171:3a7713b1edbc 71 PORT0_8_IRQn = 24,
AnnaBridge 171:3a7713b1edbc 72 PORT0_9_IRQn = 25,
AnnaBridge 171:3a7713b1edbc 73 PORT0_10_IRQn = 26,
AnnaBridge 171:3a7713b1edbc 74 PORT0_11_IRQn = 27,
AnnaBridge 171:3a7713b1edbc 75 PORT0_12_IRQn = 28,
AnnaBridge 171:3a7713b1edbc 76 PORT0_13_IRQn = 29,
AnnaBridge 171:3a7713b1edbc 77 PORT0_14_IRQn = 30,
AnnaBridge 171:3a7713b1edbc 78 PORT0_15_IRQn = 31,
AnnaBridge 171:3a7713b1edbc 79 SYSERROR_IRQn = 32, /* System Error Interrupt */
AnnaBridge 171:3a7713b1edbc 80 EFLASH_IRQn = 33, /* Embedded Flash Interrupt */
AnnaBridge 171:3a7713b1edbc 81 LLCC_TXCMD_EMPTY_IRQn = 34, /* t.b.a */
AnnaBridge 171:3a7713b1edbc 82 LLCC_TXEVT_EMPTY_IRQn = 35, /* t.b.a */
AnnaBridge 171:3a7713b1edbc 83 LLCC_TXDMAH_DONE_IRQn = 36, /* t.b.a */
AnnaBridge 171:3a7713b1edbc 84 LLCC_TXDMAL_DONE_IRQn = 37, /* t.b.a */
AnnaBridge 171:3a7713b1edbc 85 LLCC_RXCMD_VALID_IRQn = 38, /* t.b.a */
AnnaBridge 171:3a7713b1edbc 86 LLCC_RXEVT_VALID_IRQn = 39, /* t.b.a */
AnnaBridge 171:3a7713b1edbc 87 LLCC_RXDMAH_DONE_IRQn = 40, /* t.b.a */
AnnaBridge 171:3a7713b1edbc 88 LLCC_RXDMAL_DONE_IRQn = 41, /* t.b.a */
AnnaBridge 171:3a7713b1edbc 89 PORT2_ALL_IRQn = 42, /* GPIO Port 2 combined Interrupt */
AnnaBridge 171:3a7713b1edbc 90 PORT3_ALL_IRQn = 43, /* GPIO Port 3 combined Interrupt */
AnnaBridge 171:3a7713b1edbc 91 TRNG_IRQn = 44, /* Random number generator Interrupt */
AnnaBridge 171:3a7713b1edbc 92 } IRQn_Type;
AnnaBridge 171:3a7713b1edbc 93
AnnaBridge 171:3a7713b1edbc 94
AnnaBridge 171:3a7713b1edbc 95 /* ================================================================================ */
AnnaBridge 171:3a7713b1edbc 96 /* ================ Processor and Core Peripheral Section ================ */
AnnaBridge 171:3a7713b1edbc 97 /* ================================================================================ */
AnnaBridge 171:3a7713b1edbc 98
AnnaBridge 171:3a7713b1edbc 99 /* -------- Configuration of the Cortex-M3 Processor and Core Peripherals ------- */
AnnaBridge 171:3a7713b1edbc 100 #define __CM3_REV 0x0201U /* Core revision r2p1 */
AnnaBridge 171:3a7713b1edbc 101 #define __MPU_PRESENT 1 /* MPU present */
AnnaBridge 171:3a7713b1edbc 102 #define __VTOR_PRESENT 1 /* VTOR present or not */
AnnaBridge 171:3a7713b1edbc 103 #define __NVIC_PRIO_BITS 3 /* Number of Bits used for Priority Levels */
AnnaBridge 171:3a7713b1edbc 104 #define __Vendor_SysTickConfig 0 /* Set to 1 if different SysTick Config is used */
AnnaBridge 171:3a7713b1edbc 105
AnnaBridge 171:3a7713b1edbc 106 #include <core_cm3.h> /* Processor and core peripherals */
AnnaBridge 171:3a7713b1edbc 107 #include "system_CMSDK_BEETLE.h" /* System Header */
AnnaBridge 171:3a7713b1edbc 108
AnnaBridge 171:3a7713b1edbc 109
AnnaBridge 171:3a7713b1edbc 110 /* ================================================================================ */
AnnaBridge 171:3a7713b1edbc 111 /* ================ Device Specific Peripheral Section ================ */
AnnaBridge 171:3a7713b1edbc 112 /* ================================================================================ */
AnnaBridge 171:3a7713b1edbc 113
AnnaBridge 171:3a7713b1edbc 114 /* ------------------- Start of section using anonymous unions ------------------ */
AnnaBridge 171:3a7713b1edbc 115 #if defined ( __CC_ARM )
AnnaBridge 171:3a7713b1edbc 116 #pragma push
AnnaBridge 171:3a7713b1edbc 117 #pragma anon_unions
AnnaBridge 171:3a7713b1edbc 118 #elif defined(__ICCARM__)
AnnaBridge 171:3a7713b1edbc 119 #pragma language=extended
AnnaBridge 171:3a7713b1edbc 120 #elif defined(__GNUC__)
AnnaBridge 171:3a7713b1edbc 121 /* anonymous unions are enabled by default */
AnnaBridge 171:3a7713b1edbc 122 #elif defined(__TMS470__)
AnnaBridge 171:3a7713b1edbc 123 /* anonymous unions are enabled by default */
AnnaBridge 171:3a7713b1edbc 124 #elif defined(__TASKING__)
AnnaBridge 171:3a7713b1edbc 125 #pragma warning 586
AnnaBridge 171:3a7713b1edbc 126 #else
AnnaBridge 171:3a7713b1edbc 127 #warning Not supported compiler type
AnnaBridge 171:3a7713b1edbc 128 #endif
AnnaBridge 171:3a7713b1edbc 129
AnnaBridge 171:3a7713b1edbc 130 /* ======================================================================== */
AnnaBridge 171:3a7713b1edbc 131 /* ============ LLCC/DMAC v1 ============ */
AnnaBridge 171:3a7713b1edbc 132 /* ======================================================================== */
AnnaBridge 171:3a7713b1edbc 133
AnnaBridge 171:3a7713b1edbc 134 typedef struct
AnnaBridge 171:3a7713b1edbc 135 {
AnnaBridge 171:3a7713b1edbc 136 __IO uint32_t BUF_STATE; // +0x00
AnnaBridge 171:3a7713b1edbc 137 __I uint32_t STATUS; // +0x00
AnnaBridge 171:3a7713b1edbc 138 __IO uint32_t PTR_ADDR; // +0x08
AnnaBridge 171:3a7713b1edbc 139 __IO uint32_t PTR_CTRL; // +0x0c
AnnaBridge 171:3a7713b1edbc 140 __O uint32_t NXT_ADDR; // +0x10
AnnaBridge 171:3a7713b1edbc 141 __O uint32_t NXT_CTRL; // +0x14
AnnaBridge 171:3a7713b1edbc 142 __I uint32_t rsvd_18[2]; // +0x18
AnnaBridge 171:3a7713b1edbc 143 __IO uint32_t BUF0_ADDR; // +0x20
AnnaBridge 171:3a7713b1edbc 144 __IO uint32_t BUF0_CTRL; // +0x24
AnnaBridge 171:3a7713b1edbc 145 __I uint32_t rsvd_28[2]; // +0x28
AnnaBridge 171:3a7713b1edbc 146 __IO uint32_t BUF1_ADDR; // +0x30
AnnaBridge 171:3a7713b1edbc 147 __IO uint32_t BUF1_CTRL; // +0x34
AnnaBridge 171:3a7713b1edbc 148 __IO uint32_t INTEN; // +0x38
AnnaBridge 171:3a7713b1edbc 149 __IO uint32_t IRQSTATUS; // +0x3c
AnnaBridge 171:3a7713b1edbc 150 } DMAC_CHAN_TypeDef;
AnnaBridge 171:3a7713b1edbc 151
AnnaBridge 171:3a7713b1edbc 152 // DMA buffer control state machine
AnnaBridge 171:3a7713b1edbc 153 #define DMAC_BUFSTATE_MT 0
AnnaBridge 171:3a7713b1edbc 154 #define DMAC_BUFSTATE_A 1
AnnaBridge 171:3a7713b1edbc 155 #define DMAC_BUFSTATE_AB 5
AnnaBridge 171:3a7713b1edbc 156 #define DMAC_BUFSTATE_B 2
AnnaBridge 171:3a7713b1edbc 157 #define DMAC_BUFSTATE_BA 6
AnnaBridge 171:3a7713b1edbc 158 #define DMAC_BUFSTATE_FULL_IDX 2
AnnaBridge 171:3a7713b1edbc 159
AnnaBridge 171:3a7713b1edbc 160 // DMA Control structure MASKs
AnnaBridge 171:3a7713b1edbc 161 #define DMAC_CHAN_ADDR_MASK 0xfffffffc
AnnaBridge 171:3a7713b1edbc 162 #define DMAC_CHAN_COUNT_MASK 0x0000ffff
AnnaBridge 171:3a7713b1edbc 163 #define DMAC_CHAN_SIZE_MASK 0x00030000
AnnaBridge 171:3a7713b1edbc 164 #define DMAC_CHAN_AFIX_MASK 0x00040000
AnnaBridge 171:3a7713b1edbc 165 #define DMAC_CHAN_LOOP_MASK 0x00080000
AnnaBridge 171:3a7713b1edbc 166 #define DMAC_CHAN_ATTR_MASK 0xfff00000
AnnaBridge 171:3a7713b1edbc 167 #define DMAC_CHAN_COUNT_IDX_LO 0
AnnaBridge 171:3a7713b1edbc 168 #define DMAC_CHAN_COUNT_IDX_HI 15
AnnaBridge 171:3a7713b1edbc 169 #define DMAC_CHAN_SIZE_IDX_LO 16
AnnaBridge 171:3a7713b1edbc 170 #define DMAC_CHAN_SIZE_IDX_HI 17
AnnaBridge 171:3a7713b1edbc 171 #define DMAC_CHAN_AFIX_IDX 18
AnnaBridge 171:3a7713b1edbc 172 #define DMAC_CHAN_LOOP_IDX 19
AnnaBridge 171:3a7713b1edbc 173 #define DMAC_CHAN_TRIG_IDX_LO 20
AnnaBridge 171:3a7713b1edbc 174 #define DMAC_CHAN_TRIG_IDX_HI 23
AnnaBridge 171:3a7713b1edbc 175 #define DMAC_CHAN_ATTR_IDX_LO 24
AnnaBridge 171:3a7713b1edbc 176 #define DMAC_CHAN_ATTR_IDX_HI 31
AnnaBridge 171:3a7713b1edbc 177 #define DMAC_CHAN_IRQ_IDX 0
AnnaBridge 171:3a7713b1edbc 178 #define DMAC_CHAN_ERR_IDX 1
AnnaBridge 171:3a7713b1edbc 179
AnnaBridge 171:3a7713b1edbc 180 typedef struct
AnnaBridge 171:3a7713b1edbc 181 {
AnnaBridge 171:3a7713b1edbc 182 __I uint32_t ID_MAIN; // +0x0000
AnnaBridge 171:3a7713b1edbc 183 __I uint32_t ID_REV; // +0x0004
AnnaBridge 171:3a7713b1edbc 184 __I uint32_t rsvd_0008[30]; // +0x0008
AnnaBridge 171:3a7713b1edbc 185 __IO uint32_t STANDBY_CTRL; // +0x0080
AnnaBridge 171:3a7713b1edbc 186 } LLCC_CTL_TypeDef;
AnnaBridge 171:3a7713b1edbc 187
AnnaBridge 171:3a7713b1edbc 188 typedef struct
AnnaBridge 171:3a7713b1edbc 189 {
AnnaBridge 171:3a7713b1edbc 190 __I uint32_t CMD_DATA0; // +0x2000
AnnaBridge 171:3a7713b1edbc 191 __I uint32_t CMD_DATA1; // +0x2004
AnnaBridge 171:3a7713b1edbc 192 __I uint32_t rsvd_008[14]; // +0x2008
AnnaBridge 171:3a7713b1edbc 193 __I uint32_t DMAH_DATA0; // +0x2040
AnnaBridge 171:3a7713b1edbc 194 __I uint32_t DMAH_DATA1; // +0x2044
AnnaBridge 171:3a7713b1edbc 195 __I uint32_t rsvd_048[6]; // +0x2048
AnnaBridge 171:3a7713b1edbc 196 __I uint32_t DMAL_DATA0; // +0x2060
AnnaBridge 171:3a7713b1edbc 197 __I uint32_t DMAL_DATA1; // +0x2064
AnnaBridge 171:3a7713b1edbc 198 __I uint32_t rsvd_068[6]; // +0x2068
AnnaBridge 171:3a7713b1edbc 199 __I uint32_t EVT_DATA0; // +0x2080
AnnaBridge 171:3a7713b1edbc 200 __I uint32_t EVT_DATA1; // +0x2084
AnnaBridge 171:3a7713b1edbc 201 __I uint32_t rsvd_088[14]; // +0x2088
AnnaBridge 171:3a7713b1edbc 202 __I uint32_t INTERRUPT; // +0x20c0
AnnaBridge 171:3a7713b1edbc 203 __IO uint32_t INTENMASK; // +0x20c4
AnnaBridge 171:3a7713b1edbc 204 __IO uint32_t INTENMASK_SET; // +0x20c8
AnnaBridge 171:3a7713b1edbc 205 __IO uint32_t INTENMASK_CLR; // +0x20cc
AnnaBridge 171:3a7713b1edbc 206 __I uint32_t REQUEST; // +0x20d0
AnnaBridge 171:3a7713b1edbc 207 __I uint32_t rsvd_0d4[3]; // +0x20d4
AnnaBridge 171:3a7713b1edbc 208 __I uint32_t XFERREQ; // +0x20e0
AnnaBridge 171:3a7713b1edbc 209 __I uint32_t XFERACK; // +0x20e4
AnnaBridge 171:3a7713b1edbc 210 __I uint32_t rsvd_0e8[6]; // +0x20e8
AnnaBridge 171:3a7713b1edbc 211 } LLCC_RXD_TypeDef;
AnnaBridge 171:3a7713b1edbc 212
AnnaBridge 171:3a7713b1edbc 213 typedef struct
AnnaBridge 171:3a7713b1edbc 214 {
AnnaBridge 171:3a7713b1edbc 215 __IO uint32_t CMD_DATA0; // +0x3000
AnnaBridge 171:3a7713b1edbc 216 __IO uint32_t CMD_DATA1; // +0x3004
AnnaBridge 171:3a7713b1edbc 217 __I uint32_t rsvd_008[14]; // +0x3008
AnnaBridge 171:3a7713b1edbc 218 __IO uint32_t DMAH_DATA0; // +0x3040
AnnaBridge 171:3a7713b1edbc 219 __IO uint32_t DMAH_DATA1; // +0x3044
AnnaBridge 171:3a7713b1edbc 220 __I uint32_t rsvd_048[6]; // +0x3048
AnnaBridge 171:3a7713b1edbc 221 __IO uint32_t DMAL_DATA0; // +0x3060
AnnaBridge 171:3a7713b1edbc 222 __IO uint32_t DMAL_DATA1; // +0x3064
AnnaBridge 171:3a7713b1edbc 223 __I uint32_t rsvd_068[6]; // +0x3068
AnnaBridge 171:3a7713b1edbc 224 __IO uint32_t EVT_DATA0; // +0x3080
AnnaBridge 171:3a7713b1edbc 225 __IO uint32_t EVT_DATA1; // +0x3084
AnnaBridge 171:3a7713b1edbc 226 __I uint32_t rsvd_088[14]; // +0x3088
AnnaBridge 171:3a7713b1edbc 227 __I uint32_t INTERRUPT; // +0x30c0
AnnaBridge 171:3a7713b1edbc 228 __IO uint32_t INTENMASK; // +0x30c4
AnnaBridge 171:3a7713b1edbc 229 __IO uint32_t INTENMASK_SET; // +0x30c8
AnnaBridge 171:3a7713b1edbc 230 __IO uint32_t INTENMASK_CLR; // +0x30cc
AnnaBridge 171:3a7713b1edbc 231 __I uint32_t REQUEST; // +0x30d0
AnnaBridge 171:3a7713b1edbc 232 __I uint32_t ACTIVE; // +0x30d4
AnnaBridge 171:3a7713b1edbc 233 __I uint32_t VCREADY; // +0x30d8
AnnaBridge 171:3a7713b1edbc 234 __I uint32_t rsvd_0dc; // +0x30dc
AnnaBridge 171:3a7713b1edbc 235 __IO uint32_t XFERREQ; // +0x30e0
AnnaBridge 171:3a7713b1edbc 236 __I uint32_t XFERACK; // +0x30e4
AnnaBridge 171:3a7713b1edbc 237 __I uint32_t rsvd_0e8[6]; // +0x30e8
AnnaBridge 171:3a7713b1edbc 238 } LLCC_TXD_TypeDef;
AnnaBridge 171:3a7713b1edbc 239
AnnaBridge 171:3a7713b1edbc 240 // TX?RX buffer handshake/interrupt fields
AnnaBridge 171:3a7713b1edbc 241 #define LLCC_CMD0_MASK 0x01
AnnaBridge 171:3a7713b1edbc 242 #define LLCC_CMD1_MASK 0x02
AnnaBridge 171:3a7713b1edbc 243 #define LLCC_CMD_MASK 0x03
AnnaBridge 171:3a7713b1edbc 244 #define LLCC_CMD_IRQ_MASK LLCC_CMD_MASK
AnnaBridge 171:3a7713b1edbc 245 #define LLCC_DMAH1_MASK 0x04
AnnaBridge 171:3a7713b1edbc 246 #define LLCC_DMAH2_MASK 0x08
AnnaBridge 171:3a7713b1edbc 247 #define LLCC_DMAH_MASK 0x0c
AnnaBridge 171:3a7713b1edbc 248 #define LLCC_DMAL1_MASK 0x10
AnnaBridge 171:3a7713b1edbc 249 #define LLCC_DMAL2_MASK 0x20
AnnaBridge 171:3a7713b1edbc 250 #define LLCC_DMAL_MASK 0x30
AnnaBridge 171:3a7713b1edbc 251 #define LLCC_EVT0_MASK 0x40
AnnaBridge 171:3a7713b1edbc 252 #define LLCC_EVT1_MASK 0x80
AnnaBridge 171:3a7713b1edbc 253 #define LLCC_EVT_IRQ_MASK LLCC_EVT1_MASK
AnnaBridge 171:3a7713b1edbc 254 #define LLCC_EVT_MASK 0xc0
AnnaBridge 171:3a7713b1edbc 255 #define LLCC_CMD0_IDX 0
AnnaBridge 171:3a7713b1edbc 256 #define LLCC_CMD1_IDX 1
AnnaBridge 171:3a7713b1edbc 257 #define LLCC_CMD_IDX LLCC_CMD1_IDX
AnnaBridge 171:3a7713b1edbc 258 #define LLCC_CMD_IRQ_IDX 1
AnnaBridge 171:3a7713b1edbc 259 #define LLCC_DMAH1_IDX 2
AnnaBridge 171:3a7713b1edbc 260 #define LLCC_DMAH2_IDX 3
AnnaBridge 171:3a7713b1edbc 261 #define LLCC_DMAL1_IDX 4
AnnaBridge 171:3a7713b1edbc 262 #define LLCC_DMAL2_IDX 5
AnnaBridge 171:3a7713b1edbc 263 #define LLCC_EVT0_IDX 6
AnnaBridge 171:3a7713b1edbc 264 #define LLCC_EVT1_IDX 7
AnnaBridge 171:3a7713b1edbc 265 #define LLCC_EVT_IDX LLCC_EVT1_IDX
AnnaBridge 171:3a7713b1edbc 266
AnnaBridge 171:3a7713b1edbc 267 /*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/
AnnaBridge 171:3a7713b1edbc 268 typedef struct
AnnaBridge 171:3a7713b1edbc 269 {
AnnaBridge 171:3a7713b1edbc 270 __IO uint32_t DATA; /* Offset: 0x000 (R/W) Data Register */
AnnaBridge 171:3a7713b1edbc 271 __IO uint32_t STATE; /* Offset: 0x004 (R/W) Status Register */
AnnaBridge 171:3a7713b1edbc 272 __IO uint32_t CTRL; /* Offset: 0x008 (R/W) Control Register */
AnnaBridge 171:3a7713b1edbc 273 union {
AnnaBridge 171:3a7713b1edbc 274 __I uint32_t INTSTATUS; /* Offset: 0x00C (R/ ) Interrupt Status Register */
AnnaBridge 171:3a7713b1edbc 275 __O uint32_t INTCLEAR; /* Offset: 0x00C ( /W) Interrupt Clear Register */
AnnaBridge 171:3a7713b1edbc 276 };
AnnaBridge 171:3a7713b1edbc 277 __IO uint32_t BAUDDIV; /* Offset: 0x010 (R/W) Baudrate Divider Register */
AnnaBridge 171:3a7713b1edbc 278
AnnaBridge 171:3a7713b1edbc 279 } CMSDK_UART_TypeDef;
AnnaBridge 171:3a7713b1edbc 280
AnnaBridge 171:3a7713b1edbc 281 /* CMSDK_UART DATA Register Definitions */
AnnaBridge 171:3a7713b1edbc 282
AnnaBridge 171:3a7713b1edbc 283 #define CMSDK_UART_DATA_Pos 0 /* CMSDK_UART_DATA_Pos: DATA Position */
AnnaBridge 171:3a7713b1edbc 284 #define CMSDK_UART_DATA_Msk (0xFFul << CMSDK_UART_DATA_Pos) /* CMSDK_UART DATA: DATA Mask */
AnnaBridge 171:3a7713b1edbc 285
AnnaBridge 171:3a7713b1edbc 286 #define CMSDK_UART_STATE_RXOR_Pos 3 /* CMSDK_UART STATE: RXOR Position */
AnnaBridge 171:3a7713b1edbc 287 #define CMSDK_UART_STATE_RXOR_Msk (0x1ul << CMSDK_UART_STATE_RXOR_Pos) /* CMSDK_UART STATE: RXOR Mask */
AnnaBridge 171:3a7713b1edbc 288
AnnaBridge 171:3a7713b1edbc 289 #define CMSDK_UART_STATE_TXOR_Pos 2 /* CMSDK_UART STATE: TXOR Position */
AnnaBridge 171:3a7713b1edbc 290 #define CMSDK_UART_STATE_TXOR_Msk (0x1ul << CMSDK_UART_STATE_TXOR_Pos) /* CMSDK_UART STATE: TXOR Mask */
AnnaBridge 171:3a7713b1edbc 291
AnnaBridge 171:3a7713b1edbc 292 #define CMSDK_UART_STATE_RXBF_Pos 1 /* CMSDK_UART STATE: RXBF Position */
AnnaBridge 171:3a7713b1edbc 293 #define CMSDK_UART_STATE_RXBF_Msk (0x1ul << CMSDK_UART_STATE_RXBF_Pos) /* CMSDK_UART STATE: RXBF Mask */
AnnaBridge 171:3a7713b1edbc 294
AnnaBridge 171:3a7713b1edbc 295 #define CMSDK_UART_STATE_TXBF_Pos 0 /* CMSDK_UART STATE: TXBF Position */
AnnaBridge 171:3a7713b1edbc 296 #define CMSDK_UART_STATE_TXBF_Msk (0x1ul << CMSDK_UART_STATE_TXBF_Pos ) /* CMSDK_UART STATE: TXBF Mask */
AnnaBridge 171:3a7713b1edbc 297
AnnaBridge 171:3a7713b1edbc 298 #define CMSDK_UART_CTRL_HSTM_Pos 6 /* CMSDK_UART CTRL: HSTM Position */
AnnaBridge 171:3a7713b1edbc 299 #define CMSDK_UART_CTRL_HSTM_Msk (0x01ul << CMSDK_UART_CTRL_HSTM_Pos) /* CMSDK_UART CTRL: HSTM Mask */
AnnaBridge 171:3a7713b1edbc 300
AnnaBridge 171:3a7713b1edbc 301 #define CMSDK_UART_CTRL_RXORIRQEN_Pos 5 /* CMSDK_UART CTRL: RXORIRQEN Position */
AnnaBridge 171:3a7713b1edbc 302 #define CMSDK_UART_CTRL_RXORIRQEN_Msk (0x01ul << CMSDK_UART_CTRL_RXORIRQEN_Pos) /* CMSDK_UART CTRL: RXORIRQEN Mask */
AnnaBridge 171:3a7713b1edbc 303
AnnaBridge 171:3a7713b1edbc 304 #define CMSDK_UART_CTRL_TXORIRQEN_Pos 4 /* CMSDK_UART CTRL: TXORIRQEN Position */
AnnaBridge 171:3a7713b1edbc 305 #define CMSDK_UART_CTRL_TXORIRQEN_Msk (0x01ul << CMSDK_UART_CTRL_TXORIRQEN_Pos) /* CMSDK_UART CTRL: TXORIRQEN Mask */
AnnaBridge 171:3a7713b1edbc 306
AnnaBridge 171:3a7713b1edbc 307 #define CMSDK_UART_CTRL_RXIRQEN_Pos 3 /* CMSDK_UART CTRL: RXIRQEN Position */
AnnaBridge 171:3a7713b1edbc 308 #define CMSDK_UART_CTRL_RXIRQEN_Msk (0x01ul << CMSDK_UART_CTRL_RXIRQEN_Pos) /* CMSDK_UART CTRL: RXIRQEN Mask */
AnnaBridge 171:3a7713b1edbc 309
AnnaBridge 171:3a7713b1edbc 310 #define CMSDK_UART_CTRL_TXIRQEN_Pos 2 /* CMSDK_UART CTRL: TXIRQEN Position */
AnnaBridge 171:3a7713b1edbc 311 #define CMSDK_UART_CTRL_TXIRQEN_Msk (0x01ul << CMSDK_UART_CTRL_TXIRQEN_Pos) /* CMSDK_UART CTRL: TXIRQEN Mask */
AnnaBridge 171:3a7713b1edbc 312
AnnaBridge 171:3a7713b1edbc 313 #define CMSDK_UART_CTRL_RXEN_Pos 1 /* CMSDK_UART CTRL: RXEN Position */
AnnaBridge 171:3a7713b1edbc 314 #define CMSDK_UART_CTRL_RXEN_Msk (0x01ul << CMSDK_UART_CTRL_RXEN_Pos) /* CMSDK_UART CTRL: RXEN Mask */
AnnaBridge 171:3a7713b1edbc 315
AnnaBridge 171:3a7713b1edbc 316 #define CMSDK_UART_CTRL_TXEN_Pos 0 /* CMSDK_UART CTRL: TXEN Position */
AnnaBridge 171:3a7713b1edbc 317 #define CMSDK_UART_CTRL_TXEN_Msk (0x01ul << CMSDK_UART_CTRL_TXEN_Pos) /* CMSDK_UART CTRL: TXEN Mask */
AnnaBridge 171:3a7713b1edbc 318
AnnaBridge 171:3a7713b1edbc 319 #define CMSDK_UART_INTSTATUS_RXORIRQ_Pos 3 /* CMSDK_UART CTRL: RXORIRQ Position */
AnnaBridge 171:3a7713b1edbc 320 #define CMSDK_UART_INTSTATUS_RXORIRQ_Msk (0x01ul << CMSDK_UART_INTSTATUS_RXORIRQ_Pos) /* CMSDK_UART CTRL: RXORIRQ Mask */
AnnaBridge 171:3a7713b1edbc 321
AnnaBridge 171:3a7713b1edbc 322 #define CMSDK_UART_INTSTATUS_TXORIRQ_Pos 2 /* CMSDK_UART CTRL: TXORIRQ Position */
AnnaBridge 171:3a7713b1edbc 323 #define CMSDK_UART_INTSTATUS_TXORIRQ_Msk (0x01ul << CMSDK_UART_INTSTATUS_TXORIRQ_Pos) /* CMSDK_UART CTRL: TXORIRQ Mask */
AnnaBridge 171:3a7713b1edbc 324
AnnaBridge 171:3a7713b1edbc 325 #define CMSDK_UART_INTSTATUS_RXIRQ_Pos 1 /* CMSDK_UART CTRL: RXIRQ Position */
AnnaBridge 171:3a7713b1edbc 326 #define CMSDK_UART_INTSTATUS_RXIRQ_Msk (0x01ul << CMSDK_UART_INTSTATUS_RXIRQ_Pos) /* CMSDK_UART CTRL: RXIRQ Mask */
AnnaBridge 171:3a7713b1edbc 327
AnnaBridge 171:3a7713b1edbc 328 #define CMSDK_UART_INTSTATUS_TXIRQ_Pos 0 /* CMSDK_UART CTRL: TXIRQ Position */
AnnaBridge 171:3a7713b1edbc 329 #define CMSDK_UART_INTSTATUS_TXIRQ_Msk (0x01ul << CMSDK_UART_INTSTATUS_TXIRQ_Pos) /* CMSDK_UART CTRL: TXIRQ Mask */
AnnaBridge 171:3a7713b1edbc 330
AnnaBridge 171:3a7713b1edbc 331 #define CMSDK_UART_BAUDDIV_Pos 0 /* CMSDK_UART BAUDDIV: BAUDDIV Position */
AnnaBridge 171:3a7713b1edbc 332 #define CMSDK_UART_BAUDDIV_Msk (0xFFFFFul << CMSDK_UART_BAUDDIV_Pos) /* CMSDK_UART BAUDDIV: BAUDDIV Mask */
AnnaBridge 171:3a7713b1edbc 333
AnnaBridge 171:3a7713b1edbc 334
AnnaBridge 171:3a7713b1edbc 335 /*----------------------------- Timer (TIMER) -------------------------------*/
AnnaBridge 171:3a7713b1edbc 336 typedef struct
AnnaBridge 171:3a7713b1edbc 337 {
AnnaBridge 171:3a7713b1edbc 338 __IO uint32_t CTRL; /* Offset: 0x000 (R/W) Control Register */
AnnaBridge 171:3a7713b1edbc 339 __IO uint32_t VALUE; /* Offset: 0x004 (R/W) Current Value Register */
AnnaBridge 171:3a7713b1edbc 340 __IO uint32_t RELOAD; /* Offset: 0x008 (R/W) Reload Value Register */
AnnaBridge 171:3a7713b1edbc 341 union {
AnnaBridge 171:3a7713b1edbc 342 __I uint32_t INTSTATUS; /* Offset: 0x00C (R/ ) Interrupt Status Register */
AnnaBridge 171:3a7713b1edbc 343 __O uint32_t INTCLEAR; /* Offset: 0x00C ( /W) Interrupt Clear Register */
AnnaBridge 171:3a7713b1edbc 344 };
AnnaBridge 171:3a7713b1edbc 345
AnnaBridge 171:3a7713b1edbc 346 } CMSDK_TIMER_TypeDef;
AnnaBridge 171:3a7713b1edbc 347
AnnaBridge 171:3a7713b1edbc 348 /* CMSDK_TIMER CTRL Register Definitions */
AnnaBridge 171:3a7713b1edbc 349
AnnaBridge 171:3a7713b1edbc 350 #define CMSDK_TIMER_CTRL_IRQEN_Pos 3 /* CMSDK_TIMER CTRL: IRQEN Position */
AnnaBridge 171:3a7713b1edbc 351 #define CMSDK_TIMER_CTRL_IRQEN_Msk (0x01ul << CMSDK_TIMER_CTRL_IRQEN_Pos) /* CMSDK_TIMER CTRL: IRQEN Mask */
AnnaBridge 171:3a7713b1edbc 352
AnnaBridge 171:3a7713b1edbc 353 #define CMSDK_TIMER_CTRL_SELEXTCLK_Pos 2 /* CMSDK_TIMER CTRL: SELEXTCLK Position */
AnnaBridge 171:3a7713b1edbc 354 #define CMSDK_TIMER_CTRL_SELEXTCLK_Msk (0x01ul << CMSDK_TIMER_CTRL_SELEXTCLK_Pos) /* CMSDK_TIMER CTRL: SELEXTCLK Mask */
AnnaBridge 171:3a7713b1edbc 355
AnnaBridge 171:3a7713b1edbc 356 #define CMSDK_TIMER_CTRL_SELEXTEN_Pos 1 /* CMSDK_TIMER CTRL: SELEXTEN Position */
AnnaBridge 171:3a7713b1edbc 357 #define CMSDK_TIMER_CTRL_SELEXTEN_Msk (0x01ul << CMSDK_TIMER_CTRL_SELEXTEN_Pos) /* CMSDK_TIMER CTRL: SELEXTEN Mask */
AnnaBridge 171:3a7713b1edbc 358
AnnaBridge 171:3a7713b1edbc 359 #define CMSDK_TIMER_CTRL_EN_Pos 0 /* CMSDK_TIMER CTRL: EN Position */
AnnaBridge 171:3a7713b1edbc 360 #define CMSDK_TIMER_CTRL_EN_Msk (0x01ul << CMSDK_TIMER_CTRL_EN_Pos) /* CMSDK_TIMER CTRL: EN Mask */
AnnaBridge 171:3a7713b1edbc 361
AnnaBridge 171:3a7713b1edbc 362 #define CMSDK_TIMER_VAL_CURRENT_Pos 0 /* CMSDK_TIMER VALUE: CURRENT Position */
AnnaBridge 171:3a7713b1edbc 363 #define CMSDK_TIMER_VAL_CURRENT_Msk (0xFFFFFFFFul << CMSDK_TIMER_VAL_CURRENT_Pos) /* CMSDK_TIMER VALUE: CURRENT Mask */
AnnaBridge 171:3a7713b1edbc 364
AnnaBridge 171:3a7713b1edbc 365 #define CMSDK_TIMER_RELOAD_VAL_Pos 0 /* CMSDK_TIMER RELOAD: RELOAD Position */
AnnaBridge 171:3a7713b1edbc 366 #define CMSDK_TIMER_RELOAD_VAL_Msk (0xFFFFFFFFul << CMSDK_TIMER_RELOAD_VAL_Pos) /* CMSDK_TIMER RELOAD: RELOAD Mask */
AnnaBridge 171:3a7713b1edbc 367
AnnaBridge 171:3a7713b1edbc 368 #define CMSDK_TIMER_INTSTATUS_Pos 0 /* CMSDK_TIMER INTSTATUS: INTSTATUSPosition */
AnnaBridge 171:3a7713b1edbc 369 #define CMSDK_TIMER_INTSTATUS_Msk (0x01ul << CMSDK_TIMER_INTSTATUS_Pos) /* CMSDK_TIMER INTSTATUS: INTSTATUSMask */
AnnaBridge 171:3a7713b1edbc 370
AnnaBridge 171:3a7713b1edbc 371 #define CMSDK_TIMER_INTCLEAR_Pos 0 /* CMSDK_TIMER INTCLEAR: INTCLEAR Position */
AnnaBridge 171:3a7713b1edbc 372 #define CMSDK_TIMER_INTCLEAR_Msk (0x01ul << CMSDK_TIMER_INTCLEAR_Pos) /* CMSDK_TIMER INTCLEAR: INTCLEAR Mask */
AnnaBridge 171:3a7713b1edbc 373
AnnaBridge 171:3a7713b1edbc 374
AnnaBridge 171:3a7713b1edbc 375 /*------------- Timer (TIM) --------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 376 typedef struct
AnnaBridge 171:3a7713b1edbc 377 {
AnnaBridge 171:3a7713b1edbc 378 __IO uint32_t Timer1Load; /* Offset: 0x000 (R/W) Timer 1 Load */
AnnaBridge 171:3a7713b1edbc 379 __I uint32_t Timer1Value; /* Offset: 0x004 (R/ ) Timer 1 Counter Current Value */
AnnaBridge 171:3a7713b1edbc 380 __IO uint32_t Timer1Control; /* Offset: 0x008 (R/W) Timer 1 Control */
AnnaBridge 171:3a7713b1edbc 381 __O uint32_t Timer1IntClr; /* Offset: 0x00C ( /W) Timer 1 Interrupt Clear */
AnnaBridge 171:3a7713b1edbc 382 __I uint32_t Timer1RIS; /* Offset: 0x010 (R/ ) Timer 1 Raw Interrupt Status */
AnnaBridge 171:3a7713b1edbc 383 __I uint32_t Timer1MIS; /* Offset: 0x014 (R/ ) Timer 1 Masked Interrupt Status */
AnnaBridge 171:3a7713b1edbc 384 __IO uint32_t Timer1BGLoad; /* Offset: 0x018 (R/W) Background Load Register */
AnnaBridge 171:3a7713b1edbc 385 uint32_t RESERVED0;
AnnaBridge 171:3a7713b1edbc 386 __IO uint32_t Timer2Load; /* Offset: 0x020 (R/W) Timer 2 Load */
AnnaBridge 171:3a7713b1edbc 387 __I uint32_t Timer2Value; /* Offset: 0x024 (R/ ) Timer 2 Counter Current Value */
AnnaBridge 171:3a7713b1edbc 388 __IO uint32_t Timer2Control; /* Offset: 0x028 (R/W) Timer 2 Control */
AnnaBridge 171:3a7713b1edbc 389 __O uint32_t Timer2IntClr; /* Offset: 0x02C ( /W) Timer 2 Interrupt Clear */
AnnaBridge 171:3a7713b1edbc 390 __I uint32_t Timer2RIS; /* Offset: 0x030 (R/ ) Timer 2 Raw Interrupt Status */
AnnaBridge 171:3a7713b1edbc 391 __I uint32_t Timer2MIS; /* Offset: 0x034 (R/ ) Timer 2 Masked Interrupt Status */
AnnaBridge 171:3a7713b1edbc 392 __IO uint32_t Timer2BGLoad; /* Offset: 0x038 (R/W) Background Load Register */
AnnaBridge 171:3a7713b1edbc 393 uint32_t RESERVED1[945];
AnnaBridge 171:3a7713b1edbc 394 __IO uint32_t ITCR; /* Offset: 0xF00 (R/W) Integration Test Control Register */
AnnaBridge 171:3a7713b1edbc 395 __O uint32_t ITOP; /* Offset: 0xF04 ( /W) Integration Test Output Set Register */
AnnaBridge 171:3a7713b1edbc 396 } CMSDK_DUALTIMER_BOTH_TypeDef;
AnnaBridge 171:3a7713b1edbc 397
AnnaBridge 171:3a7713b1edbc 398 #define CMSDK_DUALTIMER1_LOAD_Pos 0 /* CMSDK_DUALTIMER1 LOAD: LOAD Position */
AnnaBridge 171:3a7713b1edbc 399 #define CMSDK_DUALTIMER1_LOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER1_LOAD_Pos) /* CMSDK_DUALTIMER1 LOAD: LOAD Mask */
AnnaBridge 171:3a7713b1edbc 400
AnnaBridge 171:3a7713b1edbc 401 #define CMSDK_DUALTIMER1_VALUE_Pos 0 /* CMSDK_DUALTIMER1 VALUE: VALUE Position */
AnnaBridge 171:3a7713b1edbc 402 #define CMSDK_DUALTIMER1_VALUE_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER1_VALUE_Pos) /* CMSDK_DUALTIMER1 VALUE: VALUE Mask */
AnnaBridge 171:3a7713b1edbc 403
AnnaBridge 171:3a7713b1edbc 404 #define CMSDK_DUALTIMER1_CTRL_EN_Pos 7 /* CMSDK_DUALTIMER1 CTRL_EN: CTRL Enable Position */
AnnaBridge 171:3a7713b1edbc 405 #define CMSDK_DUALTIMER1_CTRL_EN_Msk (0x1ul << CMSDK_DUALTIMER1_CTRL_EN_Pos) /* CMSDK_DUALTIMER1 CTRL_EN: CTRL Enable Mask */
AnnaBridge 171:3a7713b1edbc 406
AnnaBridge 171:3a7713b1edbc 407 #define CMSDK_DUALTIMER1_CTRL_MODE_Pos 6 /* CMSDK_DUALTIMER1 CTRL_MODE: CTRL MODE Position */
AnnaBridge 171:3a7713b1edbc 408 #define CMSDK_DUALTIMER1_CTRL_MODE_Msk (0x1ul << CMSDK_DUALTIMER1_CTRL_MODE_Pos) /* CMSDK_DUALTIMER1 CTRL_MODE: CTRL MODE Mask */
AnnaBridge 171:3a7713b1edbc 409
AnnaBridge 171:3a7713b1edbc 410 #define CMSDK_DUALTIMER1_CTRL_INTEN_Pos 5 /* CMSDK_DUALTIMER1 CTRL_INTEN: CTRL Int Enable Position */
AnnaBridge 171:3a7713b1edbc 411 #define CMSDK_DUALTIMER1_CTRL_INTEN_Msk (0x1ul << CMSDK_DUALTIMER1_CTRL_INTEN_Pos) /* CMSDK_DUALTIMER1 CTRL_INTEN: CTRL Int Enable Mask */
AnnaBridge 171:3a7713b1edbc 412
AnnaBridge 171:3a7713b1edbc 413 #define CMSDK_DUALTIMER1_CTRL_PRESCALE_Pos 2 /* CMSDK_DUALTIMER1 CTRL_PRESCALE: CTRL PRESCALE Position */
AnnaBridge 171:3a7713b1edbc 414 #define CMSDK_DUALTIMER1_CTRL_PRESCALE_Msk (0x3ul << CMSDK_DUALTIMER1_CTRL_PRESCALE_Pos) /* CMSDK_DUALTIMER1 CTRL_PRESCALE: CTRL PRESCALE Mask */
AnnaBridge 171:3a7713b1edbc 415
AnnaBridge 171:3a7713b1edbc 416 #define CMSDK_DUALTIMER1_CTRL_SIZE_Pos 1 /* CMSDK_DUALTIMER1 CTRL_SIZE: CTRL SIZE Position */
AnnaBridge 171:3a7713b1edbc 417 #define CMSDK_DUALTIMER1_CTRL_SIZE_Msk (0x1ul << CMSDK_DUALTIMER1_CTRL_SIZE_Pos) /* CMSDK_DUALTIMER1 CTRL_SIZE: CTRL SIZE Mask */
AnnaBridge 171:3a7713b1edbc 418
AnnaBridge 171:3a7713b1edbc 419 #define CMSDK_DUALTIMER1_CTRL_ONESHOOT_Pos 0 /* CMSDK_DUALTIMER1 CTRL_ONESHOOT: CTRL ONESHOOT Position */
AnnaBridge 171:3a7713b1edbc 420 #define CMSDK_DUALTIMER1_CTRL_ONESHOOT_Msk (0x1ul << CMSDK_DUALTIMER1_CTRL_ONESHOOT_Pos) /* CMSDK_DUALTIMER1 CTRL_ONESHOOT: CTRL ONESHOOT Mask */
AnnaBridge 171:3a7713b1edbc 421
AnnaBridge 171:3a7713b1edbc 422 #define CMSDK_DUALTIMER1_INTCLR_Pos 0 /* CMSDK_DUALTIMER1 INTCLR: INT Clear Position */
AnnaBridge 171:3a7713b1edbc 423 #define CMSDK_DUALTIMER1_INTCLR_Msk (0x1ul << CMSDK_DUALTIMER1_INTCLR_Pos) /* CMSDK_DUALTIMER1 INTCLR: INT Clear Mask */
AnnaBridge 171:3a7713b1edbc 424
AnnaBridge 171:3a7713b1edbc 425 #define CMSDK_DUALTIMER1_RAWINTSTAT_Pos 0 /* CMSDK_DUALTIMER1 RAWINTSTAT: Raw Int Status Position */
AnnaBridge 171:3a7713b1edbc 426 #define CMSDK_DUALTIMER1_RAWINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER1_RAWINTSTAT_Pos) /* CMSDK_DUALTIMER1 RAWINTSTAT: Raw Int Status Mask */
AnnaBridge 171:3a7713b1edbc 427
AnnaBridge 171:3a7713b1edbc 428 #define CMSDK_DUALTIMER1_MASKINTSTAT_Pos 0 /* CMSDK_DUALTIMER1 MASKINTSTAT: Mask Int Status Position */
AnnaBridge 171:3a7713b1edbc 429 #define CMSDK_DUALTIMER1_MASKINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER1_MASKINTSTAT_Pos) /* CMSDK_DUALTIMER1 MASKINTSTAT: Mask Int Status Mask */
AnnaBridge 171:3a7713b1edbc 430
AnnaBridge 171:3a7713b1edbc 431 #define CMSDK_DUALTIMER1_BGLOAD_Pos 0 /* CMSDK_DUALTIMER1 BGLOAD: Background Load Position */
AnnaBridge 171:3a7713b1edbc 432 #define CMSDK_DUALTIMER1_BGLOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER1_BGLOAD_Pos) /* CMSDK_DUALTIMER1 BGLOAD: Background Load Mask */
AnnaBridge 171:3a7713b1edbc 433
AnnaBridge 171:3a7713b1edbc 434 #define CMSDK_DUALTIMER2_LOAD_Pos 0 /* CMSDK_DUALTIMER2 LOAD: LOAD Position */
AnnaBridge 171:3a7713b1edbc 435 #define CMSDK_DUALTIMER2_LOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER2_LOAD_Pos) /* CMSDK_DUALTIMER2 LOAD: LOAD Mask */
AnnaBridge 171:3a7713b1edbc 436
AnnaBridge 171:3a7713b1edbc 437 #define CMSDK_DUALTIMER2_VALUE_Pos 0 /* CMSDK_DUALTIMER2 VALUE: VALUE Position */
AnnaBridge 171:3a7713b1edbc 438 #define CMSDK_DUALTIMER2_VALUE_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER2_VALUE_Pos) /* CMSDK_DUALTIMER2 VALUE: VALUE Mask */
AnnaBridge 171:3a7713b1edbc 439
AnnaBridge 171:3a7713b1edbc 440 #define CMSDK_DUALTIMER2_CTRL_EN_Pos 7 /* CMSDK_DUALTIMER2 CTRL_EN: CTRL Enable Position */
AnnaBridge 171:3a7713b1edbc 441 #define CMSDK_DUALTIMER2_CTRL_EN_Msk (0x1ul << CMSDK_DUALTIMER2_CTRL_EN_Pos) /* CMSDK_DUALTIMER2 CTRL_EN: CTRL Enable Mask */
AnnaBridge 171:3a7713b1edbc 442
AnnaBridge 171:3a7713b1edbc 443 #define CMSDK_DUALTIMER2_CTRL_MODE_Pos 6 /* CMSDK_DUALTIMER2 CTRL_MODE: CTRL MODE Position */
AnnaBridge 171:3a7713b1edbc 444 #define CMSDK_DUALTIMER2_CTRL_MODE_Msk (0x1ul << CMSDK_DUALTIMER2_CTRL_MODE_Pos) /* CMSDK_DUALTIMER2 CTRL_MODE: CTRL MODE Mask */
AnnaBridge 171:3a7713b1edbc 445
AnnaBridge 171:3a7713b1edbc 446 #define CMSDK_DUALTIMER2_CTRL_INTEN_Pos 5 /* CMSDK_DUALTIMER2 CTRL_INTEN: CTRL Int Enable Position */
AnnaBridge 171:3a7713b1edbc 447 #define CMSDK_DUALTIMER2_CTRL_INTEN_Msk (0x1ul << CMSDK_DUALTIMER2_CTRL_INTEN_Pos) /* CMSDK_DUALTIMER2 CTRL_INTEN: CTRL Int Enable Mask */
AnnaBridge 171:3a7713b1edbc 448
AnnaBridge 171:3a7713b1edbc 449 #define CMSDK_DUALTIMER2_CTRL_PRESCALE_Pos 2 /* CMSDK_DUALTIMER2 CTRL_PRESCALE: CTRL PRESCALE Position */
AnnaBridge 171:3a7713b1edbc 450 #define CMSDK_DUALTIMER2_CTRL_PRESCALE_Msk (0x3ul << CMSDK_DUALTIMER2_CTRL_PRESCALE_Pos) /* CMSDK_DUALTIMER2 CTRL_PRESCALE: CTRL PRESCALE Mask */
AnnaBridge 171:3a7713b1edbc 451
AnnaBridge 171:3a7713b1edbc 452 #define CMSDK_DUALTIMER2_CTRL_SIZE_Pos 1 /* CMSDK_DUALTIMER2 CTRL_SIZE: CTRL SIZE Position */
AnnaBridge 171:3a7713b1edbc 453 #define CMSDK_DUALTIMER2_CTRL_SIZE_Msk (0x1ul << CMSDK_DUALTIMER2_CTRL_SIZE_Pos) /* CMSDK_DUALTIMER2 CTRL_SIZE: CTRL SIZE Mask */
AnnaBridge 171:3a7713b1edbc 454
AnnaBridge 171:3a7713b1edbc 455 #define CMSDK_DUALTIMER2_CTRL_ONESHOOT_Pos 0 /* CMSDK_DUALTIMER2 CTRL_ONESHOOT: CTRL ONESHOOT Position */
AnnaBridge 171:3a7713b1edbc 456 #define CMSDK_DUALTIMER2_CTRL_ONESHOOT_Msk (0x1ul << CMSDK_DUALTIMER2_CTRL_ONESHOOT_Pos) /* CMSDK_DUALTIMER2 CTRL_ONESHOOT: CTRL ONESHOOT Mask */
AnnaBridge 171:3a7713b1edbc 457
AnnaBridge 171:3a7713b1edbc 458 #define CMSDK_DUALTIMER2_INTCLR_Pos 0 /* CMSDK_DUALTIMER2 INTCLR: INT Clear Position */
AnnaBridge 171:3a7713b1edbc 459 #define CMSDK_DUALTIMER2_INTCLR_Msk (0x1ul << CMSDK_DUALTIMER2_INTCLR_Pos) /* CMSDK_DUALTIMER2 INTCLR: INT Clear Mask */
AnnaBridge 171:3a7713b1edbc 460
AnnaBridge 171:3a7713b1edbc 461 #define CMSDK_DUALTIMER2_RAWINTSTAT_Pos 0 /* CMSDK_DUALTIMER2 RAWINTSTAT: Raw Int Status Position */
AnnaBridge 171:3a7713b1edbc 462 #define CMSDK_DUALTIMER2_RAWINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER2_RAWINTSTAT_Pos) /* CMSDK_DUALTIMER2 RAWINTSTAT: Raw Int Status Mask */
AnnaBridge 171:3a7713b1edbc 463
AnnaBridge 171:3a7713b1edbc 464 #define CMSDK_DUALTIMER2_MASKINTSTAT_Pos 0 /* CMSDK_DUALTIMER2 MASKINTSTAT: Mask Int Status Position */
AnnaBridge 171:3a7713b1edbc 465 #define CMSDK_DUALTIMER2_MASKINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER2_MASKINTSTAT_Pos) /* CMSDK_DUALTIMER2 MASKINTSTAT: Mask Int Status Mask */
AnnaBridge 171:3a7713b1edbc 466
AnnaBridge 171:3a7713b1edbc 467 #define CMSDK_DUALTIMER2_BGLOAD_Pos 0 /* CMSDK_DUALTIMER2 BGLOAD: Background Load Position */
AnnaBridge 171:3a7713b1edbc 468 #define CMSDK_DUALTIMER2_BGLOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER2_BGLOAD_Pos) /* CMSDK_DUALTIMER2 BGLOAD: Background Load Mask */
AnnaBridge 171:3a7713b1edbc 469
AnnaBridge 171:3a7713b1edbc 470
AnnaBridge 171:3a7713b1edbc 471 typedef struct
AnnaBridge 171:3a7713b1edbc 472 {
AnnaBridge 171:3a7713b1edbc 473 __IO uint32_t TimerLoad; /* Offset: 0x000 (R/W) Timer Load */
AnnaBridge 171:3a7713b1edbc 474 __I uint32_t TimerValue; /* Offset: 0x000 (R/W) Timer Counter Current Value */
AnnaBridge 171:3a7713b1edbc 475 __IO uint32_t TimerControl; /* Offset: 0x000 (R/W) Timer Control */
AnnaBridge 171:3a7713b1edbc 476 __O uint32_t TimerIntClr; /* Offset: 0x000 (R/W) Timer Interrupt Clear */
AnnaBridge 171:3a7713b1edbc 477 __I uint32_t TimerRIS; /* Offset: 0x000 (R/W) Timer Raw Interrupt Status */
AnnaBridge 171:3a7713b1edbc 478 __I uint32_t TimerMIS; /* Offset: 0x000 (R/W) Timer Masked Interrupt Status */
AnnaBridge 171:3a7713b1edbc 479 __IO uint32_t TimerBGLoad; /* Offset: 0x000 (R/W) Background Load Register */
AnnaBridge 171:3a7713b1edbc 480 } CMSDK_DUALTIMER_SINGLE_TypeDef;
AnnaBridge 171:3a7713b1edbc 481
AnnaBridge 171:3a7713b1edbc 482 #define CMSDK_DUALTIMER_LOAD_Pos 0 /* CMSDK_DUALTIMER LOAD: LOAD Position */
AnnaBridge 171:3a7713b1edbc 483 #define CMSDK_DUALTIMER_LOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER_LOAD_Pos) /* CMSDK_DUALTIMER LOAD: LOAD Mask */
AnnaBridge 171:3a7713b1edbc 484
AnnaBridge 171:3a7713b1edbc 485 #define CMSDK_DUALTIMER_VALUE_Pos 0 /* CMSDK_DUALTIMER VALUE: VALUE Position */
AnnaBridge 171:3a7713b1edbc 486 #define CMSDK_DUALTIMER_VALUE_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER_VALUE_Pos) /* CMSDK_DUALTIMER VALUE: VALUE Mask */
AnnaBridge 171:3a7713b1edbc 487
AnnaBridge 171:3a7713b1edbc 488 #define CMSDK_DUALTIMER_CTRL_EN_Pos 7 /* CMSDK_DUALTIMER CTRL_EN: CTRL Enable Position */
AnnaBridge 171:3a7713b1edbc 489 #define CMSDK_DUALTIMER_CTRL_EN_Msk (0x1ul << CMSDK_DUALTIMER_CTRL_EN_Pos) /* CMSDK_DUALTIMER CTRL_EN: CTRL Enable Mask */
AnnaBridge 171:3a7713b1edbc 490
AnnaBridge 171:3a7713b1edbc 491 #define CMSDK_DUALTIMER_CTRL_MODE_Pos 6 /* CMSDK_DUALTIMER CTRL_MODE: CTRL MODE Position */
AnnaBridge 171:3a7713b1edbc 492 #define CMSDK_DUALTIMER_CTRL_MODE_Msk (0x1ul << CMSDK_DUALTIMER_CTRL_MODE_Pos) /* CMSDK_DUALTIMER CTRL_MODE: CTRL MODE Mask */
AnnaBridge 171:3a7713b1edbc 493
AnnaBridge 171:3a7713b1edbc 494 #define CMSDK_DUALTIMER_CTRL_INTEN_Pos 5 /* CMSDK_DUALTIMER CTRL_INTEN: CTRL Int Enable Position */
AnnaBridge 171:3a7713b1edbc 495 #define CMSDK_DUALTIMER_CTRL_INTEN_Msk (0x1ul << CMSDK_DUALTIMER_CTRL_INTEN_Pos) /* CMSDK_DUALTIMER CTRL_INTEN: CTRL Int Enable Mask */
AnnaBridge 171:3a7713b1edbc 496
AnnaBridge 171:3a7713b1edbc 497 #define CMSDK_DUALTIMER_CTRL_PRESCALE_Pos 2 /* CMSDK_DUALTIMER CTRL_PRESCALE: CTRL PRESCALE Position */
AnnaBridge 171:3a7713b1edbc 498 #define CMSDK_DUALTIMER_CTRL_PRESCALE_Msk (0x3ul << CMSDK_DUALTIMER_CTRL_PRESCALE_Pos) /* CMSDK_DUALTIMER CTRL_PRESCALE: CTRL PRESCALE Mask */
AnnaBridge 171:3a7713b1edbc 499
AnnaBridge 171:3a7713b1edbc 500 #define CMSDK_DUALTIMER_CTRL_SIZE_Pos 1 /* CMSDK_DUALTIMER CTRL_SIZE: CTRL SIZE Position */
AnnaBridge 171:3a7713b1edbc 501 #define CMSDK_DUALTIMER_CTRL_SIZE_Msk (0x1ul << CMSDK_DUALTIMER_CTRL_SIZE_Pos) /* CMSDK_DUALTIMER CTRL_SIZE: CTRL SIZE Mask */
AnnaBridge 171:3a7713b1edbc 502
AnnaBridge 171:3a7713b1edbc 503 #define CMSDK_DUALTIMER_CTRL_ONESHOOT_Pos 0 /* CMSDK_DUALTIMER CTRL_ONESHOOT: CTRL ONESHOOT Position */
AnnaBridge 171:3a7713b1edbc 504 #define CMSDK_DUALTIMER_CTRL_ONESHOOT_Msk (0x1ul << CMSDK_DUALTIMER_CTRL_ONESHOOT_Pos) /* CMSDK_DUALTIMER CTRL_ONESHOOT: CTRL ONESHOOT Mask */
AnnaBridge 171:3a7713b1edbc 505
AnnaBridge 171:3a7713b1edbc 506 #define CMSDK_DUALTIMER_INTCLR_Pos 0 /* CMSDK_DUALTIMER INTCLR: INT Clear Position */
AnnaBridge 171:3a7713b1edbc 507 #define CMSDK_DUALTIMER_INTCLR_Msk (0x1ul << CMSDK_DUALTIMER_INTCLR_Pos) /* CMSDK_DUALTIMER INTCLR: INT Clear Mask */
AnnaBridge 171:3a7713b1edbc 508
AnnaBridge 171:3a7713b1edbc 509 #define CMSDK_DUALTIMER_RAWINTSTAT_Pos 0 /* CMSDK_DUALTIMER RAWINTSTAT: Raw Int Status Position */
AnnaBridge 171:3a7713b1edbc 510 #define CMSDK_DUALTIMER_RAWINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER_RAWINTSTAT_Pos) /* CMSDK_DUALTIMER RAWINTSTAT: Raw Int Status Mask */
AnnaBridge 171:3a7713b1edbc 511
AnnaBridge 171:3a7713b1edbc 512 #define CMSDK_DUALTIMER_MASKINTSTAT_Pos 0 /* CMSDK_DUALTIMER MASKINTSTAT: Mask Int Status Position */
AnnaBridge 171:3a7713b1edbc 513 #define CMSDK_DUALTIMER_MASKINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER_MASKINTSTAT_Pos) /* CMSDK_DUALTIMER MASKINTSTAT: Mask Int Status Mask */
AnnaBridge 171:3a7713b1edbc 514
AnnaBridge 171:3a7713b1edbc 515 #define CMSDK_DUALTIMER_BGLOAD_Pos 0 /* CMSDK_DUALTIMER BGLOAD: Background Load Position */
AnnaBridge 171:3a7713b1edbc 516 #define CMSDK_DUALTIMER_BGLOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER_BGLOAD_Pos) /* CMSDK_DUALTIMER BGLOAD: Background Load Mask */
AnnaBridge 171:3a7713b1edbc 517
AnnaBridge 171:3a7713b1edbc 518
AnnaBridge 171:3a7713b1edbc 519 /*-------------------- General Purpose Input Output (GPIO) -------------------*/
AnnaBridge 171:3a7713b1edbc 520 typedef struct
AnnaBridge 171:3a7713b1edbc 521 {
AnnaBridge 171:3a7713b1edbc 522 __IO uint32_t DATA; /* Offset: 0x000 (R/W) DATA Register */
AnnaBridge 171:3a7713b1edbc 523 __IO uint32_t DATAOUT; /* Offset: 0x004 (R/W) Data Output Latch Register */
AnnaBridge 171:3a7713b1edbc 524 uint32_t RESERVED0[2];
AnnaBridge 171:3a7713b1edbc 525 __IO uint32_t OUTENABLESET; /* Offset: 0x010 (R/W) Output Enable Set Register */
AnnaBridge 171:3a7713b1edbc 526 __IO uint32_t OUTENABLECLR; /* Offset: 0x014 (R/W) Output Enable Clear Register */
AnnaBridge 171:3a7713b1edbc 527 __IO uint32_t ALTFUNCSET; /* Offset: 0x018 (R/W) Alternate Function Set Register */
AnnaBridge 171:3a7713b1edbc 528 __IO uint32_t ALTFUNCCLR; /* Offset: 0x01C (R/W) Alternate Function Clear Register */
AnnaBridge 171:3a7713b1edbc 529 __IO uint32_t INTENSET; /* Offset: 0x020 (R/W) Interrupt Enable Set Register */
AnnaBridge 171:3a7713b1edbc 530 __IO uint32_t INTENCLR; /* Offset: 0x024 (R/W) Interrupt Enable Clear Register */
AnnaBridge 171:3a7713b1edbc 531 __IO uint32_t INTTYPESET; /* Offset: 0x028 (R/W) Interrupt Type Set Register */
AnnaBridge 171:3a7713b1edbc 532 __IO uint32_t INTTYPECLR; /* Offset: 0x02C (R/W) Interrupt Type Clear Register */
AnnaBridge 171:3a7713b1edbc 533 __IO uint32_t INTPOLSET; /* Offset: 0x030 (R/W) Interrupt Polarity Set Register */
AnnaBridge 171:3a7713b1edbc 534 __IO uint32_t INTPOLCLR; /* Offset: 0x034 (R/W) Interrupt Polarity Clear Register */
AnnaBridge 171:3a7713b1edbc 535 union {
AnnaBridge 171:3a7713b1edbc 536 __I uint32_t INTSTATUS; /* Offset: 0x038 (R/ ) Interrupt Status Register */
AnnaBridge 171:3a7713b1edbc 537 __O uint32_t INTCLEAR; /* Offset: 0x038 ( /W) Interrupt Clear Register */
AnnaBridge 171:3a7713b1edbc 538 };
AnnaBridge 171:3a7713b1edbc 539 uint32_t RESERVED1[241];
AnnaBridge 171:3a7713b1edbc 540 __IO uint32_t LB_MASKED[256]; /* Offset: 0x400 - 0x7FC Lower byte Masked Access Register (R/W) */
AnnaBridge 171:3a7713b1edbc 541 __IO uint32_t UB_MASKED[256]; /* Offset: 0x800 - 0xBFC Upper byte Masked Access Register (R/W) */
AnnaBridge 171:3a7713b1edbc 542 } CMSDK_GPIO_TypeDef;
AnnaBridge 171:3a7713b1edbc 543
AnnaBridge 171:3a7713b1edbc 544 #define CMSDK_GPIO_DATA_Pos 0 /* CMSDK_GPIO DATA: DATA Position */
AnnaBridge 171:3a7713b1edbc 545 #define CMSDK_GPIO_DATA_Msk (0xFFFFul << CMSDK_GPIO_DATA_Pos) /* CMSDK_GPIO DATA: DATA Mask */
AnnaBridge 171:3a7713b1edbc 546
AnnaBridge 171:3a7713b1edbc 547 #define CMSDK_GPIO_DATAOUT_Pos 0 /* CMSDK_GPIO DATAOUT: DATAOUT Position */
AnnaBridge 171:3a7713b1edbc 548 #define CMSDK_GPIO_DATAOUT_Msk (0xFFFFul << CMSDK_GPIO_DATAOUT_Pos) /* CMSDK_GPIO DATAOUT: DATAOUT Mask */
AnnaBridge 171:3a7713b1edbc 549
AnnaBridge 171:3a7713b1edbc 550 #define CMSDK_GPIO_OUTENSET_Pos 0 /* CMSDK_GPIO OUTEN: OUTEN Position */
AnnaBridge 171:3a7713b1edbc 551 #define CMSDK_GPIO_OUTENSET_Msk (0xFFFFul << CMSDK_GPIO_OUTEN_Pos) /* CMSDK_GPIO OUTEN: OUTEN Mask */
AnnaBridge 171:3a7713b1edbc 552
AnnaBridge 171:3a7713b1edbc 553 #define CMSDK_GPIO_OUTENCLR_Pos 0 /* CMSDK_GPIO OUTEN: OUTEN Position */
AnnaBridge 171:3a7713b1edbc 554 #define CMSDK_GPIO_OUTENCLR_Msk (0xFFFFul << CMSDK_GPIO_OUTEN_Pos) /* CMSDK_GPIO OUTEN: OUTEN Mask */
AnnaBridge 171:3a7713b1edbc 555
AnnaBridge 171:3a7713b1edbc 556 #define CMSDK_GPIO_ALTFUNCSET_Pos 0 /* CMSDK_GPIO ALTFUNC: ALTFUNC Position */
AnnaBridge 171:3a7713b1edbc 557 #define CMSDK_GPIO_ALTFUNCSET_Msk (0xFFFFul << CMSDK_GPIO_ALTFUNC_Pos) /* CMSDK_GPIO ALTFUNC: ALTFUNC Mask */
AnnaBridge 171:3a7713b1edbc 558
AnnaBridge 171:3a7713b1edbc 559 #define CMSDK_GPIO_ALTFUNCCLR_Pos 0 /* CMSDK_GPIO ALTFUNC: ALTFUNC Position */
AnnaBridge 171:3a7713b1edbc 560 #define CMSDK_GPIO_ALTFUNCCLR_Msk (0xFFFFul << CMSDK_GPIO_ALTFUNC_Pos) /* CMSDK_GPIO ALTFUNC: ALTFUNC Mask */
AnnaBridge 171:3a7713b1edbc 561
AnnaBridge 171:3a7713b1edbc 562 #define CMSDK_GPIO_INTENSET_Pos 0 /* CMSDK_GPIO INTEN: INTEN Position */
AnnaBridge 171:3a7713b1edbc 563 #define CMSDK_GPIO_INTENSET_Msk (0xFFFFul << CMSDK_GPIO_INTEN_Pos) /* CMSDK_GPIO INTEN: INTEN Mask */
AnnaBridge 171:3a7713b1edbc 564
AnnaBridge 171:3a7713b1edbc 565 #define CMSDK_GPIO_INTENCLR_Pos 0 /* CMSDK_GPIO INTEN: INTEN Position */
AnnaBridge 171:3a7713b1edbc 566 #define CMSDK_GPIO_INTENCLR_Msk (0xFFFFul << CMSDK_GPIO_INTEN_Pos) /* CMSDK_GPIO INTEN: INTEN Mask */
AnnaBridge 171:3a7713b1edbc 567
AnnaBridge 171:3a7713b1edbc 568 #define CMSDK_GPIO_INTTYPESET_Pos 0 /* CMSDK_GPIO INTTYPE: INTTYPE Position */
AnnaBridge 171:3a7713b1edbc 569 #define CMSDK_GPIO_INTTYPESET_Msk (0xFFFFul << CMSDK_GPIO_INTTYPE_Pos) /* CMSDK_GPIO INTTYPE: INTTYPE Mask */
AnnaBridge 171:3a7713b1edbc 570
AnnaBridge 171:3a7713b1edbc 571 #define CMSDK_GPIO_INTTYPECLR_Pos 0 /* CMSDK_GPIO INTTYPE: INTTYPE Position */
AnnaBridge 171:3a7713b1edbc 572 #define CMSDK_GPIO_INTTYPECLR_Msk (0xFFFFul << CMSDK_GPIO_INTTYPE_Pos) /* CMSDK_GPIO INTTYPE: INTTYPE Mask */
AnnaBridge 171:3a7713b1edbc 573
AnnaBridge 171:3a7713b1edbc 574 #define CMSDK_GPIO_INTPOLSET_Pos 0 /* CMSDK_GPIO INTPOL: INTPOL Position */
AnnaBridge 171:3a7713b1edbc 575 #define CMSDK_GPIO_INTPOLSET_Msk (0xFFFFul << CMSDK_GPIO_INTPOL_Pos) /* CMSDK_GPIO INTPOL: INTPOL Mask */
AnnaBridge 171:3a7713b1edbc 576
AnnaBridge 171:3a7713b1edbc 577 #define CMSDK_GPIO_INTPOLCLR_Pos 0 /* CMSDK_GPIO INTPOL: INTPOL Position */
AnnaBridge 171:3a7713b1edbc 578 #define CMSDK_GPIO_INTPOLCLR_Msk (0xFFFFul << CMSDK_GPIO_INTPOL_Pos) /* CMSDK_GPIO INTPOL: INTPOL Mask */
AnnaBridge 171:3a7713b1edbc 579
AnnaBridge 171:3a7713b1edbc 580 #define CMSDK_GPIO_INTSTATUS_Pos 0 /* CMSDK_GPIO INTSTATUS: INTSTATUS Position */
AnnaBridge 171:3a7713b1edbc 581 #define CMSDK_GPIO_INTSTATUS_Msk (0xFFul << CMSDK_GPIO_INTSTATUS_Pos) /* CMSDK_GPIO INTSTATUS: INTSTATUS Mask */
AnnaBridge 171:3a7713b1edbc 582
AnnaBridge 171:3a7713b1edbc 583 #define CMSDK_GPIO_INTCLEAR_Pos 0 /* CMSDK_GPIO INTCLEAR: INTCLEAR Position */
AnnaBridge 171:3a7713b1edbc 584 #define CMSDK_GPIO_INTCLEAR_Msk (0xFFul << CMSDK_GPIO_INTCLEAR_Pos) /* CMSDK_GPIO INTCLEAR: INTCLEAR Mask */
AnnaBridge 171:3a7713b1edbc 585
AnnaBridge 171:3a7713b1edbc 586 #define CMSDK_GPIO_MASKLOWBYTE_Pos 0 /* CMSDK_GPIO MASKLOWBYTE: MASKLOWBYTE Position */
AnnaBridge 171:3a7713b1edbc 587 #define CMSDK_GPIO_MASKLOWBYTE_Msk (0x00FFul << CMSDK_GPIO_MASKLOWBYTE_Pos) /* CMSDK_GPIO MASKLOWBYTE: MASKLOWBYTE Mask */
AnnaBridge 171:3a7713b1edbc 588
AnnaBridge 171:3a7713b1edbc 589 #define CMSDK_GPIO_MASKHIGHBYTE_Pos 0 /* CMSDK_GPIO MASKHIGHBYTE: MASKHIGHBYTE Position */
AnnaBridge 171:3a7713b1edbc 590 #define CMSDK_GPIO_MASKHIGHBYTE_Msk (0xFF00ul << CMSDK_GPIO_MASKHIGHBYTE_Pos) /* CMSDK_GPIO MASKHIGHBYTE: MASKHIGHBYTE Mask */
AnnaBridge 171:3a7713b1edbc 591
AnnaBridge 171:3a7713b1edbc 592
AnnaBridge 171:3a7713b1edbc 593 /*------------- System Control (SYSCON) --------------------------------------*/
AnnaBridge 171:3a7713b1edbc 594 typedef struct
AnnaBridge 171:3a7713b1edbc 595 {
AnnaBridge 171:3a7713b1edbc 596 __IO uint32_t REMAP; /* Offset: 0x000 (R/W) Remap Control Register */
AnnaBridge 171:3a7713b1edbc 597 __IO uint32_t PMUCTRL; /* Offset: 0x004 (R/W) PMU Control Register */
AnnaBridge 171:3a7713b1edbc 598 __IO uint32_t RESETOP; /* Offset: 0x008 (R/W) Reset Option Register */
AnnaBridge 171:3a7713b1edbc 599 __IO uint32_t EMICTRL; /* Offset: 0x00C (R/W) EMI Control Register */
AnnaBridge 171:3a7713b1edbc 600 __IO uint32_t RSTINFO; /* Offset: 0x010 (R/W) Reset Information Register */
AnnaBridge 171:3a7713b1edbc 601 uint32_t RESERVED0[3];
AnnaBridge 171:3a7713b1edbc 602 __IO uint32_t AHBPER0SET; /* Offset: 0x020 (R/W)AHB peripheral access control set */
AnnaBridge 171:3a7713b1edbc 603 __IO uint32_t AHBPER0CLR; /* Offset: 0x024 (R/W)AHB peripheral access control clear */
AnnaBridge 171:3a7713b1edbc 604 uint32_t RESERVED1[2];
AnnaBridge 171:3a7713b1edbc 605 __IO uint32_t APBPER0SET; /* Offset: 0x030 (R/W)APB peripheral access control set */
AnnaBridge 171:3a7713b1edbc 606 __IO uint32_t APBPER0CLR; /* Offset: 0x034 (R/W)APB peripheral access control clear */
AnnaBridge 171:3a7713b1edbc 607 uint32_t RESERVED2[2];
AnnaBridge 171:3a7713b1edbc 608 __IO uint32_t MAINCLK; /* Offset: 0x040 (R/W) Main Clock Control Register */
AnnaBridge 171:3a7713b1edbc 609 __IO uint32_t AUXCLK; /* Offset: 0x044 (R/W) Auxiliary / RTC Control Register */
AnnaBridge 171:3a7713b1edbc 610 __IO uint32_t PLLCTRL; /* Offset: 0x048 (R/W) PLL Control Register */
AnnaBridge 171:3a7713b1edbc 611 __IO uint32_t PLLSTATUS; /* Offset: 0x04C (R/W) PLL Status Register */
AnnaBridge 171:3a7713b1edbc 612 __IO uint32_t SLEEPCFG; /* Offset: 0x050 (R/W) Sleep Control Register */
AnnaBridge 171:3a7713b1edbc 613 __IO uint32_t FLASHAUXCFG; /* Offset: 0x054 (R/W) Flash auxiliary settings Control Register */
AnnaBridge 171:3a7713b1edbc 614 uint32_t RESERVED3[10];
AnnaBridge 171:3a7713b1edbc 615 __IO uint32_t AHBCLKCFG0SET; /* Offset: 0x080 (R/W) AHB Peripheral Clock set in Active state */
AnnaBridge 171:3a7713b1edbc 616 __IO uint32_t AHBCLKCFG0CLR; /* Offset: 0x084 (R/W) AHB Peripheral Clock clear in Active state */
AnnaBridge 171:3a7713b1edbc 617 __IO uint32_t AHBCLKCFG1SET; /* Offset: 0x088 (R/W) AHB Peripheral Clock set in Sleep state */
AnnaBridge 171:3a7713b1edbc 618 __IO uint32_t AHBCLKCFG1CLR; /* Offset: 0x08C (R/W) AHB Peripheral Clock clear in Sleep state */
AnnaBridge 171:3a7713b1edbc 619 __IO uint32_t AHBCLKCFG2SET; /* Offset: 0x090 (R/W) AHB Peripheral Clock set in Deep Sleep state */
AnnaBridge 171:3a7713b1edbc 620 __IO uint32_t AHBCLKCFG2CLR; /* Offset: 0x094 (R/W) AHB Peripheral Clock clear in Deep Sleep state */
AnnaBridge 171:3a7713b1edbc 621 uint32_t RESERVED4[2];
AnnaBridge 171:3a7713b1edbc 622 __IO uint32_t APBCLKCFG0SET; /* Offset: 0x0A0 (R/W) APB Peripheral Clock set in Active state */
AnnaBridge 171:3a7713b1edbc 623 __IO uint32_t APBCLKCFG0CLR; /* Offset: 0x0A4 (R/W) APB Peripheral Clock clear in Active state */
AnnaBridge 171:3a7713b1edbc 624 __IO uint32_t APBCLKCFG1SET; /* Offset: 0x0A8 (R/W) APB Peripheral Clock set in Sleep state */
AnnaBridge 171:3a7713b1edbc 625 __IO uint32_t APBCLKCFG1CLR; /* Offset: 0x0AC (R/W) APB Peripheral Clock clear in Sleep state */
AnnaBridge 171:3a7713b1edbc 626 __IO uint32_t APBCLKCFG2SET; /* Offset: 0x0B0 (R/W) APB Peripheral Clock set in Deep Sleep state */
AnnaBridge 171:3a7713b1edbc 627 __IO uint32_t APBCLKCFG2CLR; /* Offset: 0x0B4 (R/W) APB Peripheral Clock clear in Deep Sleep state */
AnnaBridge 171:3a7713b1edbc 628 uint32_t RESERVED5[2];
AnnaBridge 171:3a7713b1edbc 629 __IO uint32_t AHBPRST0SET; /* Offset: 0x0C0 (R/W) AHB Peripheral reset select set */
AnnaBridge 171:3a7713b1edbc 630 __IO uint32_t AHBPRST0CLR; /* Offset: 0x0C4 (R/W) AHB Peripheral reset select clear */
AnnaBridge 171:3a7713b1edbc 631 __IO uint32_t APBPRST0SET; /* Offset: 0x0C8 (R/W) APB Peripheral reset select set */
AnnaBridge 171:3a7713b1edbc 632 __IO uint32_t APBPRST0CLR; /* Offset: 0x0CC (R/W) APB Peripheral reset select clear */
AnnaBridge 171:3a7713b1edbc 633 __IO uint32_t PWRDNCFG0SET; /* Offset: 0x0D0 (R/W) AHB Power down sleep wakeup source set */
AnnaBridge 171:3a7713b1edbc 634 __IO uint32_t PWRDNCFG0CLR; /* Offset: 0x0D4 (R/W) AHB Power down sleep wakeup source clear */
AnnaBridge 171:3a7713b1edbc 635 __IO uint32_t PWRDNCFG1SET; /* Offset: 0x0D8 (R/W) APB Power down sleep wakeup source set */
AnnaBridge 171:3a7713b1edbc 636 __IO uint32_t PWRDNCFG1CLR; /* Offset: 0x0DC (R/W) APB Power down sleep wakeup source clear */
AnnaBridge 171:3a7713b1edbc 637 __O uint32_t RTCRESET; /* Offset: 0x0E0 ( /W) RTC reset */
AnnaBridge 171:3a7713b1edbc 638 __IO uint32_t EVENTCFG; /* Offset: 0x0E4 (R/W) Event interface Control Register */
AnnaBridge 171:3a7713b1edbc 639 uint32_t RESERVED6[2];
AnnaBridge 171:3a7713b1edbc 640 __IO uint32_t PWROVRIDE0; /* Offset: 0x0F0 (R/W) SRAM Power control overide */
AnnaBridge 171:3a7713b1edbc 641 __IO uint32_t PWROVRIDE1; /* Offset: 0x0F4 (R/W) Embedded Flash Power control overide */
AnnaBridge 171:3a7713b1edbc 642 __I uint32_t MEMORYSTATUS; /* Offset: 0x0F8 (R/ ) Memory Status Register */
AnnaBridge 171:3a7713b1edbc 643 uint32_t RESERVED7[1];
AnnaBridge 171:3a7713b1edbc 644 __IO uint32_t GPIOPADCFG0; /* Offset: 0x100 (R/W) IO pad settings */
AnnaBridge 171:3a7713b1edbc 645 __IO uint32_t GPIOPADCFG1; /* Offset: 0x104 (R/W) IO pad settings */
AnnaBridge 171:3a7713b1edbc 646 __IO uint32_t TESTMODECFG; /* Offset: 0x108 (R/W) Testmode boot bypass */
AnnaBridge 171:3a7713b1edbc 647 } CMSDK_SYSCON_TypeDef;
AnnaBridge 171:3a7713b1edbc 648
AnnaBridge 171:3a7713b1edbc 649 #define CMSDK_SYSCON_REMAP_Pos 0
AnnaBridge 171:3a7713b1edbc 650 #define CMSDK_SYSCON_REMAP_Msk (0x01ul << CMSDK_SYSCON_REMAP_Pos) /* CMSDK_SYSCON MEME_CTRL: REMAP Mask */
AnnaBridge 171:3a7713b1edbc 651
AnnaBridge 171:3a7713b1edbc 652 #define CMSDK_SYSCON_PMUCTRL_EN_Pos 0
AnnaBridge 171:3a7713b1edbc 653 #define CMSDK_SYSCON_PMUCTRL_EN_Msk (0x01ul << CMSDK_SYSCON_PMUCTRL_EN_Pos) /* CMSDK_SYSCON PMUCTRL: PMUCTRL ENABLE Mask */
AnnaBridge 171:3a7713b1edbc 654
AnnaBridge 171:3a7713b1edbc 655 #define CMSDK_SYSCON_LOCKUPRST_RESETOP_Pos 0
AnnaBridge 171:3a7713b1edbc 656 #define CMSDK_SYSCON_LOCKUPRST_RESETOP_Msk (0x01ul << CMSDK_SYSCON_LOCKUPRST_RESETOP_Pos) /* CMSDK_SYSCON SYS_CTRL: LOCKUP RESET ENABLE Mask */
AnnaBridge 171:3a7713b1edbc 657
AnnaBridge 171:3a7713b1edbc 658 #define CMSDK_SYSCON_EMICTRL_SIZE_Pos 24
AnnaBridge 171:3a7713b1edbc 659 #define CMSDK_SYSCON_EMICTRL_SIZE_Msk (0x00001ul << CMSDK_SYSCON_EMICTRL_SIZE_Pos) /* CMSDK_SYSCON EMICTRL: SIZE Mask */
AnnaBridge 171:3a7713b1edbc 660
AnnaBridge 171:3a7713b1edbc 661 #define CMSDK_SYSCON_EMICTRL_TACYC_Pos 16
AnnaBridge 171:3a7713b1edbc 662 #define CMSDK_SYSCON_EMICTRL_TACYC_Msk (0x00007ul << CMSDK_SYSCON_EMICTRL_TACYC_Pos) /* CMSDK_SYSCON EMICTRL: TURNAROUNDCYCLE Mask */
AnnaBridge 171:3a7713b1edbc 663
AnnaBridge 171:3a7713b1edbc 664 #define CMSDK_SYSCON_EMICTRL_WCYC_Pos 8
AnnaBridge 171:3a7713b1edbc 665 #define CMSDK_SYSCON_EMICTRL_WCYC_Msk (0x00003ul << CMSDK_SYSCON_EMICTRL_WCYC_Pos) /* CMSDK_SYSCON EMICTRL: WRITECYCLE Mask */
AnnaBridge 171:3a7713b1edbc 666
AnnaBridge 171:3a7713b1edbc 667 #define CMSDK_SYSCON_EMICTRL_RCYC_Pos 0
AnnaBridge 171:3a7713b1edbc 668 #define CMSDK_SYSCON_EMICTRL_RCYC_Msk (0x00007ul << CMSDK_SYSCON_EMICTRL_RCYC_Pos) /* CMSDK_SYSCON EMICTRL: READCYCLE Mask */
AnnaBridge 171:3a7713b1edbc 669
AnnaBridge 171:3a7713b1edbc 670 #define CMSDK_SYSCON_RSTINFO_SYSRESETREQ_Pos 0
AnnaBridge 171:3a7713b1edbc 671 #define CMSDK_SYSCON_RSTINFO_SYSRESETREQ_Msk (0x00001ul << CMSDK_SYSCON_RSTINFO_SYSRESETREQ_Pos) /* CMSDK_SYSCON RSTINFO: SYSRESETREQ Mask */
AnnaBridge 171:3a7713b1edbc 672
AnnaBridge 171:3a7713b1edbc 673 #define CMSDK_SYSCON_RSTINFO_WDOGRESETREQ_Pos 1
AnnaBridge 171:3a7713b1edbc 674 #define CMSDK_SYSCON_RSTINFO_WDOGRESETREQ_Msk (0x00001ul << CMSDK_SYSCON_RSTINFO_WDOGRESETREQ_Pos) /* CMSDK_SYSCON RSTINFO: WDOGRESETREQ Mask */
AnnaBridge 171:3a7713b1edbc 675
AnnaBridge 171:3a7713b1edbc 676 #define CMSDK_SYSCON_RSTINFO_LOCKUPRESET_Pos 2
AnnaBridge 171:3a7713b1edbc 677 #define CMSDK_SYSCON_RSTINFO_LOCKUPRESET_Msk (0x00001ul << CMSDK_SYSCON_RSTINFO_LOCKUPRESET_Pos) /* CMSDK_SYSCON RSTINFO: LOCKUPRESET Mask */
AnnaBridge 171:3a7713b1edbc 678
AnnaBridge 171:3a7713b1edbc 679
AnnaBridge 171:3a7713b1edbc 680 /*------------- PL230 uDMA (PL230) --------------------------------------*/
AnnaBridge 171:3a7713b1edbc 681 typedef struct
AnnaBridge 171:3a7713b1edbc 682 {
AnnaBridge 171:3a7713b1edbc 683 __I uint32_t DMA_STATUS; /* Offset: 0x000 (R/W) DMA status Register */
AnnaBridge 171:3a7713b1edbc 684 __O uint32_t DMA_CFG; /* Offset: 0x004 ( /W) DMA configuration Register */
AnnaBridge 171:3a7713b1edbc 685 __IO uint32_t CTRL_BASE_PTR; /* Offset: 0x008 (R/W) Channel Control Data Base Pointer Register */
AnnaBridge 171:3a7713b1edbc 686 __I uint32_t ALT_CTRL_BASE_PTR; /* Offset: 0x00C (R/ ) Channel Alternate Control Data Base Pointer Register */
AnnaBridge 171:3a7713b1edbc 687 __I uint32_t DMA_WAITONREQ_STATUS; /* Offset: 0x010 (R/ ) Channel Wait On Request Status Register */
AnnaBridge 171:3a7713b1edbc 688 __O uint32_t CHNL_SW_REQUEST; /* Offset: 0x014 ( /W) Channel Software Request Register */
AnnaBridge 171:3a7713b1edbc 689 __IO uint32_t CHNL_USEBURST_SET; /* Offset: 0x018 (R/W) Channel UseBurst Set Register */
AnnaBridge 171:3a7713b1edbc 690 __O uint32_t CHNL_USEBURST_CLR; /* Offset: 0x01C ( /W) Channel UseBurst Clear Register */
AnnaBridge 171:3a7713b1edbc 691 __IO uint32_t CHNL_REQ_MASK_SET; /* Offset: 0x020 (R/W) Channel Request Mask Set Register */
AnnaBridge 171:3a7713b1edbc 692 __O uint32_t CHNL_REQ_MASK_CLR; /* Offset: 0x024 ( /W) Channel Request Mask Clear Register */
AnnaBridge 171:3a7713b1edbc 693 __IO uint32_t CHNL_ENABLE_SET; /* Offset: 0x028 (R/W) Channel Enable Set Register */
AnnaBridge 171:3a7713b1edbc 694 __O uint32_t CHNL_ENABLE_CLR; /* Offset: 0x02C ( /W) Channel Enable Clear Register */
AnnaBridge 171:3a7713b1edbc 695 __IO uint32_t CHNL_PRI_ALT_SET; /* Offset: 0x030 (R/W) Channel Primary-Alterante Set Register */
AnnaBridge 171:3a7713b1edbc 696 __O uint32_t CHNL_PRI_ALT_CLR; /* Offset: 0x034 ( /W) Channel Primary-Alterante Clear Register */
AnnaBridge 171:3a7713b1edbc 697 __IO uint32_t CHNL_PRIORITY_SET; /* Offset: 0x038 (R/W) Channel Priority Set Register */
AnnaBridge 171:3a7713b1edbc 698 __O uint32_t CHNL_PRIORITY_CLR; /* Offset: 0x03C ( /W) Channel Priority Clear Register */
AnnaBridge 171:3a7713b1edbc 699 uint32_t RESERVED0[3];
AnnaBridge 171:3a7713b1edbc 700 __IO uint32_t ERR_CLR; /* Offset: 0x04C Bus Error Clear Register (R/W) */
AnnaBridge 171:3a7713b1edbc 701
AnnaBridge 171:3a7713b1edbc 702 } CMSDK_PL230_TypeDef;
AnnaBridge 171:3a7713b1edbc 703
AnnaBridge 171:3a7713b1edbc 704 #define PL230_DMA_CHNL_BITS 0
AnnaBridge 171:3a7713b1edbc 705
AnnaBridge 171:3a7713b1edbc 706 #define CMSDK_PL230_DMA_STATUS_MSTREN_Pos 0 /* CMSDK_PL230 DMA STATUS: MSTREN Position */
AnnaBridge 171:3a7713b1edbc 707 #define CMSDK_PL230_DMA_STATUS_MSTREN_Msk (0x00000001ul << CMSDK_PL230_DMA_STATUS_MSTREN_Pos) /* CMSDK_PL230 DMA STATUS: MSTREN Mask */
AnnaBridge 171:3a7713b1edbc 708
AnnaBridge 171:3a7713b1edbc 709 #define CMSDK_PL230_DMA_STATUS_STATE_Pos 0 /* CMSDK_PL230 DMA STATUS: STATE Position */
AnnaBridge 171:3a7713b1edbc 710 #define CMSDK_PL230_DMA_STATUS_STATE_Msk (0x0000000Ful << CMSDK_PL230_DMA_STATUS_STATE_Pos) /* CMSDK_PL230 DMA STATUS: STATE Mask */
AnnaBridge 171:3a7713b1edbc 711
AnnaBridge 171:3a7713b1edbc 712 #define CMSDK_PL230_DMA_STATUS_CHNLS_MINUS1_Pos 0 /* CMSDK_PL230 DMA STATUS: CHNLS_MINUS1 Position */
AnnaBridge 171:3a7713b1edbc 713 #define CMSDK_PL230_DMA_STATUS_CHNLS_MINUS1_Msk (0x0000001Ful << CMSDK_PL230_DMA_STATUS_CHNLS_MINUS1_Pos) /* CMSDK_PL230 DMA STATUS: CHNLS_MINUS1 Mask */
AnnaBridge 171:3a7713b1edbc 714
AnnaBridge 171:3a7713b1edbc 715 #define CMSDK_PL230_DMA_STATUS_TEST_STATUS_Pos 0 /* CMSDK_PL230 DMA STATUS: TEST_STATUS Position */
AnnaBridge 171:3a7713b1edbc 716 #define CMSDK_PL230_DMA_STATUS_TEST_STATUS_Msk (0x00000001ul << CMSDK_PL230_DMA_STATUS_TEST_STATUS_Pos) /* CMSDK_PL230 DMA STATUS: TEST_STATUS Mask */
AnnaBridge 171:3a7713b1edbc 717
AnnaBridge 171:3a7713b1edbc 718 #define CMSDK_PL230_DMA_CFG_MSTREN_Pos 0 /* CMSDK_PL230 DMA CFG: MSTREN Position */
AnnaBridge 171:3a7713b1edbc 719 #define CMSDK_PL230_DMA_CFG_MSTREN_Msk (0x00000001ul << CMSDK_PL230_DMA_CFG_MSTREN_Pos) /* CMSDK_PL230 DMA CFG: MSTREN Mask */
AnnaBridge 171:3a7713b1edbc 720
AnnaBridge 171:3a7713b1edbc 721 #define CMSDK_PL230_DMA_CFG_CPCCACHE_Pos 2 /* CMSDK_PL230 DMA CFG: CPCCACHE Position */
AnnaBridge 171:3a7713b1edbc 722 #define CMSDK_PL230_DMA_CFG_CPCCACHE_Msk (0x00000001ul << CMSDK_PL230_DMA_CFG_CPCCACHE_Pos) /* CMSDK_PL230 DMA CFG: CPCCACHE Mask */
AnnaBridge 171:3a7713b1edbc 723
AnnaBridge 171:3a7713b1edbc 724 #define CMSDK_PL230_DMA_CFG_CPCBUF_Pos 1 /* CMSDK_PL230 DMA CFG: CPCBUF Position */
AnnaBridge 171:3a7713b1edbc 725 #define CMSDK_PL230_DMA_CFG_CPCBUF_Msk (0x00000001ul << CMSDK_PL230_DMA_CFG_CPCBUF_Pos) /* CMSDK_PL230 DMA CFG: CPCBUF Mask */
AnnaBridge 171:3a7713b1edbc 726
AnnaBridge 171:3a7713b1edbc 727 #define CMSDK_PL230_DMA_CFG_CPCPRIV_Pos 0 /* CMSDK_PL230 DMA CFG: CPCPRIV Position */
AnnaBridge 171:3a7713b1edbc 728 #define CMSDK_PL230_DMA_CFG_CPCPRIV_Msk (0x00000001ul << CMSDK_PL230_DMA_CFG_CPCPRIV_Pos) /* CMSDK_PL230 DMA CFG: CPCPRIV Mask */
AnnaBridge 171:3a7713b1edbc 729
AnnaBridge 171:3a7713b1edbc 730 #define CMSDK_PL230_CTRL_BASE_PTR_Pos PL230_DMA_CHNL_BITS + 5 /* CMSDK_PL230 STATUS: BASE_PTR Position */
AnnaBridge 171:3a7713b1edbc 731 #define CMSDK_PL230_CTRL_BASE_PTR_Msk (0x0FFFFFFFul << CMSDK_PL230_CTRL_BASE_PTR_Pos) /* CMSDK_PL230 STATUS: BASE_PTR Mask */
AnnaBridge 171:3a7713b1edbc 732
AnnaBridge 171:3a7713b1edbc 733 #define CMSDK_PL230_ALT_CTRL_BASE_PTR_Pos 0 /* CMSDK_PL230 STATUS: MSTREN Position */
AnnaBridge 171:3a7713b1edbc 734 #define CMSDK_PL230_ALT_CTRL_BASE_PTR_Msk (0xFFFFFFFFul << CMSDK_PL230_ALT_CTRL_BASE_PTR_Pos) /* CMSDK_PL230 STATUS: MSTREN Mask */
AnnaBridge 171:3a7713b1edbc 735
AnnaBridge 171:3a7713b1edbc 736 #define CMSDK_PL230_DMA_WAITONREQ_STATUS_Pos 0 /* CMSDK_PL230 DMA_WAITONREQ_STATUS: DMA_WAITONREQ_STATUS Position */
AnnaBridge 171:3a7713b1edbc 737 #define CMSDK_PL230_DMA_WAITONREQ_STATUS_Msk (0xFFFFFFFFul << CMSDK_PL230_DMA_WAITONREQ_STATUS_Pos) /* CMSDK_PL230 DMA_WAITONREQ_STATUS: DMA_WAITONREQ_STATUS Mask */
AnnaBridge 171:3a7713b1edbc 738
AnnaBridge 171:3a7713b1edbc 739 #define CMSDK_PL230_CHNL_SW_REQUEST_Pos 0 /* CMSDK_PL230 CHNL_SW_REQUEST: CHNL_SW_REQUEST Position */
AnnaBridge 171:3a7713b1edbc 740 #define CMSDK_PL230_CHNL_SW_REQUEST_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_SW_REQUEST_Pos) /* CMSDK_PL230 CHNL_SW_REQUEST: CHNL_SW_REQUEST Mask */
AnnaBridge 171:3a7713b1edbc 741
AnnaBridge 171:3a7713b1edbc 742 #define CMSDK_PL230_CHNL_USEBURST_SET_Pos 0 /* CMSDK_PL230 CHNL_USEBURST: SET Position */
AnnaBridge 171:3a7713b1edbc 743 #define CMSDK_PL230_CHNL_USEBURST_SET_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_USEBURST_SET_Pos) /* CMSDK_PL230 CHNL_USEBURST: SET Mask */
AnnaBridge 171:3a7713b1edbc 744
AnnaBridge 171:3a7713b1edbc 745 #define CMSDK_PL230_CHNL_USEBURST_CLR_Pos 0 /* CMSDK_PL230 CHNL_USEBURST: CLR Position */
AnnaBridge 171:3a7713b1edbc 746 #define CMSDK_PL230_CHNL_USEBURST_CLR_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_USEBURST_CLR_Pos) /* CMSDK_PL230 CHNL_USEBURST: CLR Mask */
AnnaBridge 171:3a7713b1edbc 747
AnnaBridge 171:3a7713b1edbc 748 #define CMSDK_PL230_CHNL_REQ_MASK_SET_Pos 0 /* CMSDK_PL230 CHNL_REQ_MASK: SET Position */
AnnaBridge 171:3a7713b1edbc 749 #define CMSDK_PL230_CHNL_REQ_MASK_SET_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_REQ_MASK_SET_Pos) /* CMSDK_PL230 CHNL_REQ_MASK: SET Mask */
AnnaBridge 171:3a7713b1edbc 750
AnnaBridge 171:3a7713b1edbc 751 #define CMSDK_PL230_CHNL_REQ_MASK_CLR_Pos 0 /* CMSDK_PL230 CHNL_REQ_MASK: CLR Position */
AnnaBridge 171:3a7713b1edbc 752 #define CMSDK_PL230_CHNL_REQ_MASK_CLR_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_REQ_MASK_CLR_Pos) /* CMSDK_PL230 CHNL_REQ_MASK: CLR Mask */
AnnaBridge 171:3a7713b1edbc 753
AnnaBridge 171:3a7713b1edbc 754 #define CMSDK_PL230_CHNL_ENABLE_SET_Pos 0 /* CMSDK_PL230 CHNL_ENABLE: SET Position */
AnnaBridge 171:3a7713b1edbc 755 #define CMSDK_PL230_CHNL_ENABLE_SET_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_ENABLE_SET_Pos) /* CMSDK_PL230 CHNL_ENABLE: SET Mask */
AnnaBridge 171:3a7713b1edbc 756
AnnaBridge 171:3a7713b1edbc 757 #define CMSDK_PL230_CHNL_ENABLE_CLR_Pos 0 /* CMSDK_PL230 CHNL_ENABLE: CLR Position */
AnnaBridge 171:3a7713b1edbc 758 #define CMSDK_PL230_CHNL_ENABLE_CLR_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_ENABLE_CLR_Pos) /* CMSDK_PL230 CHNL_ENABLE: CLR Mask */
AnnaBridge 171:3a7713b1edbc 759
AnnaBridge 171:3a7713b1edbc 760 #define CMSDK_PL230_CHNL_PRI_ALT_SET_Pos 0 /* CMSDK_PL230 CHNL_PRI_ALT: SET Position */
AnnaBridge 171:3a7713b1edbc 761 #define CMSDK_PL230_CHNL_PRI_ALT_SET_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_PRI_ALT_SET_Pos) /* CMSDK_PL230 CHNL_PRI_ALT: SET Mask */
AnnaBridge 171:3a7713b1edbc 762
AnnaBridge 171:3a7713b1edbc 763 #define CMSDK_PL230_CHNL_PRI_ALT_CLR_Pos 0 /* CMSDK_PL230 CHNL_PRI_ALT: CLR Position */
AnnaBridge 171:3a7713b1edbc 764 #define CMSDK_PL230_CHNL_PRI_ALT_CLR_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_PRI_ALT_CLR_Pos) /* CMSDK_PL230 CHNL_PRI_ALT: CLR Mask */
AnnaBridge 171:3a7713b1edbc 765
AnnaBridge 171:3a7713b1edbc 766 #define CMSDK_PL230_CHNL_PRIORITY_SET_Pos 0 /* CMSDK_PL230 CHNL_PRIORITY: SET Position */
AnnaBridge 171:3a7713b1edbc 767 #define CMSDK_PL230_CHNL_PRIORITY_SET_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_PRIORITY_SET_Pos) /* CMSDK_PL230 CHNL_PRIORITY: SET Mask */
AnnaBridge 171:3a7713b1edbc 768
AnnaBridge 171:3a7713b1edbc 769 #define CMSDK_PL230_CHNL_PRIORITY_CLR_Pos 0 /* CMSDK_PL230 CHNL_PRIORITY: CLR Position */
AnnaBridge 171:3a7713b1edbc 770 #define CMSDK_PL230_CHNL_PRIORITY_CLR_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_PRIORITY_CLR_Pos) /* CMSDK_PL230 CHNL_PRIORITY: CLR Mask */
AnnaBridge 171:3a7713b1edbc 771
AnnaBridge 171:3a7713b1edbc 772 #define CMSDK_PL230_ERR_CLR_Pos 0 /* CMSDK_PL230 ERR: CLR Position */
AnnaBridge 171:3a7713b1edbc 773 #define CMSDK_PL230_ERR_CLR_Msk (0x00000001ul << CMSDK_PL230_ERR_CLR_Pos) /* CMSDK_PL230 ERR: CLR Mask */
AnnaBridge 171:3a7713b1edbc 774
AnnaBridge 171:3a7713b1edbc 775
AnnaBridge 171:3a7713b1edbc 776 /*------------------- Watchdog ----------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 777 typedef struct
AnnaBridge 171:3a7713b1edbc 778 {
AnnaBridge 171:3a7713b1edbc 779
AnnaBridge 171:3a7713b1edbc 780 __IO uint32_t LOAD; /* Offset: 0x000 (R/W) Watchdog Load Register */
AnnaBridge 171:3a7713b1edbc 781 __I uint32_t VALUE; /* Offset: 0x004 (R/ ) Watchdog Value Register */
AnnaBridge 171:3a7713b1edbc 782 __IO uint32_t CTRL; /* Offset: 0x008 (R/W) Watchdog Control Register */
AnnaBridge 171:3a7713b1edbc 783 __O uint32_t INTCLR; /* Offset: 0x00C ( /W) Watchdog Clear Interrupt Register */
AnnaBridge 171:3a7713b1edbc 784 __I uint32_t RAWINTSTAT; /* Offset: 0x010 (R/ ) Watchdog Raw Interrupt Status Register */
AnnaBridge 171:3a7713b1edbc 785 __I uint32_t MASKINTSTAT; /* Offset: 0x014 (R/ ) Watchdog Interrupt Status Register */
AnnaBridge 171:3a7713b1edbc 786 uint32_t RESERVED0[762];
AnnaBridge 171:3a7713b1edbc 787 __IO uint32_t LOCK; /* Offset: 0xC00 (R/W) Watchdog Lock Register */
AnnaBridge 171:3a7713b1edbc 788 uint32_t RESERVED1[191];
AnnaBridge 171:3a7713b1edbc 789 __IO uint32_t ITCR; /* Offset: 0xF00 (R/W) Watchdog Integration Test Control Register */
AnnaBridge 171:3a7713b1edbc 790 __O uint32_t ITOP; /* Offset: 0xF04 ( /W) Watchdog Integration Test Output Set Register */
AnnaBridge 171:3a7713b1edbc 791 }CMSDK_WATCHDOG_TypeDef;
AnnaBridge 171:3a7713b1edbc 792
AnnaBridge 171:3a7713b1edbc 793 #define CMSDK_Watchdog_LOAD_Pos 0 /* CMSDK_Watchdog LOAD: LOAD Position */
AnnaBridge 171:3a7713b1edbc 794 #define CMSDK_Watchdog_LOAD_Msk (0xFFFFFFFFul << CMSDK_Watchdog_LOAD_Pos) /* CMSDK_Watchdog LOAD: LOAD Mask */
AnnaBridge 171:3a7713b1edbc 795
AnnaBridge 171:3a7713b1edbc 796 #define CMSDK_Watchdog_VALUE_Pos 0 /* CMSDK_Watchdog VALUE: VALUE Position */
AnnaBridge 171:3a7713b1edbc 797 #define CMSDK_Watchdog_VALUE_Msk (0xFFFFFFFFul << CMSDK_Watchdog_VALUE_Pos) /* CMSDK_Watchdog VALUE: VALUE Mask */
AnnaBridge 171:3a7713b1edbc 798
AnnaBridge 171:3a7713b1edbc 799 #define CMSDK_Watchdog_CTRL_RESEN_Pos 1 /* CMSDK_Watchdog CTRL_RESEN: Enable Reset Output Position */
AnnaBridge 171:3a7713b1edbc 800 #define CMSDK_Watchdog_CTRL_RESEN_Msk (0x1ul << CMSDK_Watchdog_CTRL_RESEN_Pos) /* CMSDK_Watchdog CTRL_RESEN: Enable Reset Output Mask */
AnnaBridge 171:3a7713b1edbc 801
AnnaBridge 171:3a7713b1edbc 802 #define CMSDK_Watchdog_CTRL_INTEN_Pos 0 /* CMSDK_Watchdog CTRL_INTEN: Int Enable Position */
AnnaBridge 171:3a7713b1edbc 803 #define CMSDK_Watchdog_CTRL_INTEN_Msk (0x1ul << CMSDK_Watchdog_CTRL_INTEN_Pos) /* CMSDK_Watchdog CTRL_INTEN: Int Enable Mask */
AnnaBridge 171:3a7713b1edbc 804
AnnaBridge 171:3a7713b1edbc 805 #define CMSDK_Watchdog_INTCLR_Pos 0 /* CMSDK_Watchdog INTCLR: Int Clear Position */
AnnaBridge 171:3a7713b1edbc 806 #define CMSDK_Watchdog_INTCLR_Msk (0x1ul << CMSDK_Watchdog_INTCLR_Pos) /* CMSDK_Watchdog INTCLR: Int Clear Mask */
AnnaBridge 171:3a7713b1edbc 807
AnnaBridge 171:3a7713b1edbc 808 #define CMSDK_Watchdog_RAWINTSTAT_Pos 0 /* CMSDK_Watchdog RAWINTSTAT: Raw Int Status Position */
AnnaBridge 171:3a7713b1edbc 809 #define CMSDK_Watchdog_RAWINTSTAT_Msk (0x1ul << CMSDK_Watchdog_RAWINTSTAT_Pos) /* CMSDK_Watchdog RAWINTSTAT: Raw Int Status Mask */
AnnaBridge 171:3a7713b1edbc 810
AnnaBridge 171:3a7713b1edbc 811 #define CMSDK_Watchdog_MASKINTSTAT_Pos 0 /* CMSDK_Watchdog MASKINTSTAT: Mask Int Status Position */
AnnaBridge 171:3a7713b1edbc 812 #define CMSDK_Watchdog_MASKINTSTAT_Msk (0x1ul << CMSDK_Watchdog_MASKINTSTAT_Pos) /* CMSDK_Watchdog MASKINTSTAT: Mask Int Status Mask */
AnnaBridge 171:3a7713b1edbc 813
AnnaBridge 171:3a7713b1edbc 814 #define CMSDK_Watchdog_LOCK_Pos 0 /* CMSDK_Watchdog LOCK: LOCK Position */
AnnaBridge 171:3a7713b1edbc 815 #define CMSDK_Watchdog_LOCK_Msk (0x1ul << CMSDK_Watchdog_LOCK_Pos) /* CMSDK_Watchdog LOCK: LOCK Mask */
AnnaBridge 171:3a7713b1edbc 816
AnnaBridge 171:3a7713b1edbc 817 #define CMSDK_Watchdog_INTEGTESTEN_Pos 0 /* CMSDK_Watchdog INTEGTESTEN: Integration Test Enable Position */
AnnaBridge 171:3a7713b1edbc 818 #define CMSDK_Watchdog_INTEGTESTEN_Msk (0x1ul << CMSDK_Watchdog_INTEGTESTEN_Pos) /* CMSDK_Watchdog INTEGTESTEN: Integration Test Enable Mask */
AnnaBridge 171:3a7713b1edbc 819
AnnaBridge 171:3a7713b1edbc 820 #define CMSDK_Watchdog_INTEGTESTOUTSET_Pos 1 /* CMSDK_Watchdog INTEGTESTOUTSET: Integration Test Output Set Position */
AnnaBridge 171:3a7713b1edbc 821 #define CMSDK_Watchdog_INTEGTESTOUTSET_Msk (0x1ul << CMSDK_Watchdog_INTEGTESTOUTSET_Pos) /* CMSDK_Watchdog INTEGTESTOUTSET: Integration Test Output Set Mask */
AnnaBridge 171:3a7713b1edbc 822
AnnaBridge 171:3a7713b1edbc 823
AnnaBridge 171:3a7713b1edbc 824
AnnaBridge 171:3a7713b1edbc 825 /* -------------------- End of section using anonymous unions ------------------- */
AnnaBridge 171:3a7713b1edbc 826 #if defined ( __CC_ARM )
AnnaBridge 171:3a7713b1edbc 827 #pragma pop
AnnaBridge 171:3a7713b1edbc 828 #elif defined(__ICCARM__)
AnnaBridge 171:3a7713b1edbc 829 /* leave anonymous unions enabled */
AnnaBridge 171:3a7713b1edbc 830 #elif defined(__GNUC__)
AnnaBridge 171:3a7713b1edbc 831 /* anonymous unions are enabled by default */
AnnaBridge 171:3a7713b1edbc 832 #elif defined(__TMS470__)
AnnaBridge 171:3a7713b1edbc 833 /* anonymous unions are enabled by default */
AnnaBridge 171:3a7713b1edbc 834 #elif defined(__TASKING__)
AnnaBridge 171:3a7713b1edbc 835 #pragma warning restore
AnnaBridge 171:3a7713b1edbc 836 #else
AnnaBridge 171:3a7713b1edbc 837 #warning Not supported compiler type
AnnaBridge 171:3a7713b1edbc 838 #endif
AnnaBridge 171:3a7713b1edbc 839
AnnaBridge 171:3a7713b1edbc 840
AnnaBridge 171:3a7713b1edbc 841
AnnaBridge 171:3a7713b1edbc 842
AnnaBridge 171:3a7713b1edbc 843 /* ================================================================================ */
AnnaBridge 171:3a7713b1edbc 844 /* ================ Peripheral memory map ================ */
AnnaBridge 171:3a7713b1edbc 845 /* ================================================================================ */
AnnaBridge 171:3a7713b1edbc 846
AnnaBridge 171:3a7713b1edbc 847 /* Peripheral and SRAM base address */
AnnaBridge 171:3a7713b1edbc 848 #define CMSDK_FLASH_BASE (0x00000000UL)
AnnaBridge 171:3a7713b1edbc 849 #define CMSDK_SRAM_BASE (0x20000000UL)
AnnaBridge 171:3a7713b1edbc 850 #define CMSDK_PERIPH_BASE (0x40000000UL)
AnnaBridge 171:3a7713b1edbc 851
AnnaBridge 171:3a7713b1edbc 852 #define CMSDK_RAM_BASE (0x20000000UL)
AnnaBridge 171:3a7713b1edbc 853 #define CMSDK_APB_BASE (0x40000000UL)
AnnaBridge 171:3a7713b1edbc 854 #define CMSDK_AHB_BASE (0x40010000UL)
AnnaBridge 171:3a7713b1edbc 855
AnnaBridge 171:3a7713b1edbc 856 #define LLCC_CONT_BASE (0xA0000000UL)
AnnaBridge 171:3a7713b1edbc 857 #define LLCC_CTRL_BASE (LLCC_CONT_BASE)
AnnaBridge 171:3a7713b1edbc 858 #define LLCC_RXD_BASE (LLCC_CONT_BASE+0x2000)
AnnaBridge 171:3a7713b1edbc 859 #define LLCC_TXD_BASE (LLCC_CONT_BASE+0x3000)
AnnaBridge 171:3a7713b1edbc 860
AnnaBridge 171:3a7713b1edbc 861 #define DMAC_CONT_BASE (0xA0001000UL)
AnnaBridge 171:3a7713b1edbc 862 #define DMAC_DMARH_BASE (DMAC_CONT_BASE+0x00)
AnnaBridge 171:3a7713b1edbc 863 #define DMAC_DMARL_BASE (DMAC_CONT_BASE+0x40)
AnnaBridge 171:3a7713b1edbc 864 #define DMAC_DMAWH_BASE (DMAC_CONT_BASE+0x80)
AnnaBridge 171:3a7713b1edbc 865 #define DMAC_DMAWL_BASE (DMAC_CONT_BASE+0xC0)
AnnaBridge 171:3a7713b1edbc 866 #define DMAC_HCIR_BASE DMAC_DMARL_BASE
AnnaBridge 171:3a7713b1edbc 867 #define DMAC_HCIW_BASE DMAC_DMAWL_BASE
AnnaBridge 171:3a7713b1edbc 868 #define CMSDK_TIMER0_BASE (CMSDK_APB_BASE + 0x0000UL)
AnnaBridge 171:3a7713b1edbc 869 #define CMSDK_TIMER1_BASE (CMSDK_APB_BASE + 0x1000UL)
AnnaBridge 171:3a7713b1edbc 870 #define CMSDK_DUALTIMER_BASE (CMSDK_APB_BASE + 0x2000UL)
AnnaBridge 171:3a7713b1edbc 871 #define CMSDK_DUALTIMER_1_BASE (CMSDK_DUALTIMER_BASE)
AnnaBridge 171:3a7713b1edbc 872 #define CMSDK_DUALTIMER_2_BASE (CMSDK_DUALTIMER_BASE + 0x20UL)
AnnaBridge 171:3a7713b1edbc 873 #define CMSDK_UART0_BASE (CMSDK_APB_BASE + 0x4000UL)
AnnaBridge 171:3a7713b1edbc 874 #define CMSDK_UART1_BASE (CMSDK_APB_BASE + 0x5000UL)
AnnaBridge 171:3a7713b1edbc 875 #define CMSDK_RTC_BASE (CMSDK_APB_BASE + 0x6000UL)
AnnaBridge 171:3a7713b1edbc 876 #define CMSDK_WATCHDOG_BASE (CMSDK_APB_BASE + 0x8000UL)
AnnaBridge 171:3a7713b1edbc 877
AnnaBridge 171:3a7713b1edbc 878 /* AHB peripherals */
AnnaBridge 171:3a7713b1edbc 879 #define CMSDK_GPIO0_BASE (CMSDK_AHB_BASE + 0x0000UL)
AnnaBridge 171:3a7713b1edbc 880 #define CMSDK_GPIO1_BASE (CMSDK_AHB_BASE + 0x1000UL)
AnnaBridge 171:3a7713b1edbc 881 #define CMSDK_GPIO2_BASE (CMSDK_AHB_BASE + 0x2000UL)
AnnaBridge 171:3a7713b1edbc 882 #define CMSDK_GPIO3_BASE (CMSDK_AHB_BASE + 0x3000UL)
AnnaBridge 171:3a7713b1edbc 883 #define CMSDK_SYSCTRL_BASE (CMSDK_AHB_BASE + 0xF000UL)
AnnaBridge 171:3a7713b1edbc 884
AnnaBridge 171:3a7713b1edbc 885
AnnaBridge 171:3a7713b1edbc 886 /* ================================================================================ */
AnnaBridge 171:3a7713b1edbc 887 /* ================ Peripheral declaration ================ */
AnnaBridge 171:3a7713b1edbc 888 /* ================================================================================ */
AnnaBridge 171:3a7713b1edbc 889
AnnaBridge 171:3a7713b1edbc 890 #define CMSDK_UART0 ((CMSDK_UART_TypeDef *) CMSDK_UART0_BASE )
AnnaBridge 171:3a7713b1edbc 891 #define CMSDK_UART1 ((CMSDK_UART_TypeDef *) CMSDK_UART1_BASE )
AnnaBridge 171:3a7713b1edbc 892 #define CMSDK_TIMER0 ((CMSDK_TIMER_TypeDef *) CMSDK_TIMER0_BASE )
AnnaBridge 171:3a7713b1edbc 893 #define CMSDK_TIMER1 ((CMSDK_TIMER_TypeDef *) CMSDK_TIMER1_BASE )
AnnaBridge 171:3a7713b1edbc 894 #define CMSDK_DUALTIMER ((CMSDK_DUALTIMER_BOTH_TypeDef *) CMSDK_DUALTIMER_BASE )
AnnaBridge 171:3a7713b1edbc 895 #define CMSDK_DUALTIMER1 ((CMSDK_DUALTIMER_SINGLE_TypeDef *) CMSDK_DUALTIMER_1_BASE )
AnnaBridge 171:3a7713b1edbc 896 #define CMSDK_DUALTIMER2 ((CMSDK_DUALTIMER_SINGLE_TypeDef *) CMSDK_DUALTIMER_2_BASE )
AnnaBridge 171:3a7713b1edbc 897 #define CMSDK_WATCHDOG ((CMSDK_WATCHDOG_TypeDef *) CMSDK_WATCHDOG_BASE )
AnnaBridge 171:3a7713b1edbc 898 #define CMSDK_DMA ((CMSDK_PL230_TypeDef *) CMSDK_PL230_BASE )
AnnaBridge 171:3a7713b1edbc 899 #define CMSDK_GPIO0 ((CMSDK_GPIO_TypeDef *) CMSDK_GPIO0_BASE )
AnnaBridge 171:3a7713b1edbc 900 #define CMSDK_GPIO1 ((CMSDK_GPIO_TypeDef *) CMSDK_GPIO1_BASE )
AnnaBridge 171:3a7713b1edbc 901 #define CMSDK_GPIO2 ((CMSDK_GPIO_TypeDef *) CMSDK_GPIO2_BASE )
AnnaBridge 171:3a7713b1edbc 902 #define CMSDK_GPIO3 ((CMSDK_GPIO_TypeDef *) CMSDK_GPIO3_BASE )
AnnaBridge 171:3a7713b1edbc 903 #define CMSDK_SYSCON ((CMSDK_SYSCON_TypeDef *) CMSDK_SYSCTRL_BASE )
AnnaBridge 171:3a7713b1edbc 904
AnnaBridge 171:3a7713b1edbc 905 #define LLCC_CTL ((LLCC_CTL_TypeDef *) LLCC_CTRL_BASE)
AnnaBridge 171:3a7713b1edbc 906 #define LLCC_RXD ((LLCC_RXD_TypeDef *) LLCC_RXD_BASE)
AnnaBridge 171:3a7713b1edbc 907 #define LLCC_TXD ((LLCC_TXD_TypeDef *) LLCC_TXD_BASE)
AnnaBridge 171:3a7713b1edbc 908 #define DMAC_DMARH ((DMAC_CHAN_TypeDef *) DMAC_DMARH_BASE)
AnnaBridge 171:3a7713b1edbc 909 #define DMAC_DMARL ((DMAC_CHAN_TypeDef *) DMAC_DMARL_BASE)
AnnaBridge 171:3a7713b1edbc 910 #define DMAC_DMAWH ((DMAC_CHAN_TypeDef *) DMAC_DMAWH_BASE)
AnnaBridge 171:3a7713b1edbc 911 #define DMAC_DMAWL ((DMAC_CHAN_TypeDef *) DMAC_DMAWL_BASE)
AnnaBridge 171:3a7713b1edbc 912 #define DMAC_HCIR DMAC_DMAWL
AnnaBridge 171:3a7713b1edbc 913 #define DMAC_HCIW DMAC_DMARL
AnnaBridge 171:3a7713b1edbc 914
AnnaBridge 171:3a7713b1edbc 915 /*********************************************************************
AnnaBridge 171:3a7713b1edbc 916 * GPIO 2 / 3 BIT FEILD POS, OUTPUTS
AnnaBridge 171:3a7713b1edbc 917 *************************************************************************/
AnnaBridge 171:3a7713b1edbc 918 /* GPIO 2 */
AnnaBridge 171:3a7713b1edbc 919 #define CORDIO_LLCCTRL_RESETX_BIT (1<<0)
AnnaBridge 171:3a7713b1edbc 920 #define CORDIO_LLCCTRL_SYSTEM_RESET_BIT (1<<1)
AnnaBridge 171:3a7713b1edbc 921 #define CORDIO_LLCCTRL_LLC_RESET_BIT (1<<2)
AnnaBridge 171:3a7713b1edbc 922 #define CORDIO_LLCCTRL_WAKE_REQ_BIT (1<<3)
AnnaBridge 171:3a7713b1edbc 923 #define CORDIO_LLCCTRL_SLEEP_REQ_BIT (1<<4)
AnnaBridge 171:3a7713b1edbc 924 #define CORDIO_LLCCTRL_SWITCHING_REGULATOR_REQUEST_BIT (1<<5)
AnnaBridge 171:3a7713b1edbc 925 #define CORDIO_LLCCTRL_BATTERY_STATUS_REQUEST_BIT (1<<6)
AnnaBridge 171:3a7713b1edbc 926 #define CORDIO_LLCCTRL_32M_XTAL_REQUEST_BIT (1<<7)
AnnaBridge 171:3a7713b1edbc 927
AnnaBridge 171:3a7713b1edbc 928 /* GPIO 3 */
AnnaBridge 171:3a7713b1edbc 929 #define CORDIO_LLCCTRL_VMEM_ON_BIT ((1<<10) | (1 << 11))
AnnaBridge 171:3a7713b1edbc 930
AnnaBridge 171:3a7713b1edbc 931 /*********************************************************************
AnnaBridge 171:3a7713b1edbc 932 * GPIO 2 / 3 BIT FEILD POS, INPUTS
AnnaBridge 171:3a7713b1edbc 933 *************************************************************************/
AnnaBridge 171:3a7713b1edbc 934
AnnaBridge 171:3a7713b1edbc 935 #define CORDIO_LLCCTRL_RESET_SYNDROME_MSK (3<<0)
AnnaBridge 171:3a7713b1edbc 936
AnnaBridge 171:3a7713b1edbc 937 #define CORDIO_LLCCTRL_STATUS_ACTIVE_32KXTAL_BIT (1<<2)
AnnaBridge 171:3a7713b1edbc 938 #define CORDIO_LLCCTRL_STATUS_ACTIVE_32MXTAL_BIT (1<<3)
AnnaBridge 171:3a7713b1edbc 939
AnnaBridge 171:3a7713b1edbc 940 #define CORDIO_LLCCTRL_STATUS_BATTERY_DET3V_BIT (1<<4)
AnnaBridge 171:3a7713b1edbc 941 #define CORDIO_LLCCTRL_STATUS_BATTERY_STATUS_BIT (1<<5)
AnnaBridge 171:3a7713b1edbc 942 #define CORDIO_LLCCTRL_STATUS_V1V_ON_STATUS_BIT (1<<6)
AnnaBridge 171:3a7713b1edbc 943 #define CORDIO_LLCCTRL_STATUS_AWAKE_BIT (1<<7)
AnnaBridge 171:3a7713b1edbc 944
AnnaBridge 171:3a7713b1edbc 945 /**************************************************************/
AnnaBridge 171:3a7713b1edbc 946 // RESET LOW
AnnaBridge 171:3a7713b1edbc 947 #define CORDIO_LLCCTRL_RESETX_ASSERT() (CMSDK_GPIO2->DATAOUT &=~CORDIO_LLCCTRL_RESETX_BIT)
AnnaBridge 171:3a7713b1edbc 948 #define CORDIO_LLCCTRL_RESETX_NEGATE() (CMSDK_GPIO2->DATAOUT |= CORDIO_LLCCTRL_RESETX_BIT)
AnnaBridge 171:3a7713b1edbc 949 // RESET HIGH
AnnaBridge 171:3a7713b1edbc 950 #define CORDIO_LLCCTRL_SYSTEM_RESET_ASSERT() (CMSDK_GPIO2->DATAOUT |=CORDIO_LLCCTRL_SYSTEM_RESET_BIT)
AnnaBridge 171:3a7713b1edbc 951 #define CORDIO_LLCCTRL_SYSTEM_RESET_NEGATE() (CMSDK_GPIO2->DATAOUT &=~CORDIO_LLCCTRL_SYSTEM_RESET_BIT)
AnnaBridge 171:3a7713b1edbc 952
AnnaBridge 171:3a7713b1edbc 953 // RESET HIGH
AnnaBridge 171:3a7713b1edbc 954 #define CORDIO_LLCCTRL_LLC_RESET_ASSERT() (CMSDK_GPIO2->DATAOUT |=CORDIO_LLCCTRL_LLC_RESET_BIT)
AnnaBridge 171:3a7713b1edbc 955 #define CORDIO_LLCCTRL_LLC_RESET_NEGATE() (CMSDK_GPIO2->DATAOUT &=~CORDIO_LLCCTRL_LLC_RESET_BIT)
AnnaBridge 171:3a7713b1edbc 956
AnnaBridge 171:3a7713b1edbc 957 // ACTIVE HIGH
AnnaBridge 171:3a7713b1edbc 958 #define CORDIO_LLCCTRL_WAKE_REQ_ASSERT() (CMSDK_GPIO2->DATAOUT |=CORDIO_LLCCTRL_WAKE_REQ_BIT)
AnnaBridge 171:3a7713b1edbc 959 #define CORDIO_LLCCTRL_WAKE_REQ_NEGATE() (CMSDK_GPIO2->DATAOUT &=~CORDIO_LLCCTRL_WAKE_REQ_BIT)
AnnaBridge 171:3a7713b1edbc 960
AnnaBridge 171:3a7713b1edbc 961 // ACTIVE HIGH
AnnaBridge 171:3a7713b1edbc 962 #define CORDIO_LLCCTRL_SLEEP_REQ_ASSERT() (CMSDK_GPIO2->DATAOUT |=CORDIO_LLCCTRL_SLEEP_REQ_BIT)
AnnaBridge 171:3a7713b1edbc 963 #define CORDIO_LLCCTRL_SLEEP_REQ_NEGATE() (CMSDK_GPIO2->DATAOUT &=~CORDIO_LLCCTRL_SLEEP_REQ_BIT)
AnnaBridge 171:3a7713b1edbc 964
AnnaBridge 171:3a7713b1edbc 965 // ACTIVE HIGH
AnnaBridge 171:3a7713b1edbc 966 #define CORDIO_LLCCTRL_SWITCHING_REGULATOR_REQUEST_ASSERT() (CMSDK_GPIO2->DATAOUT |=CORDIO_LLCCTRL_SWITCHING_REGULATOR_REQUEST_BIT)
AnnaBridge 171:3a7713b1edbc 967 #define CORDIO_LLCCTRL_SWITCHING_REGULATOR_REQUEST_NEGATE() (CMSDK_GPIO2->DATAOUT &=~CORDIO_LLCCTRL_SWITCHING_REGULATOR_REQUEST_BIT)
AnnaBridge 171:3a7713b1edbc 968 // ACTIVE HIGH
AnnaBridge 171:3a7713b1edbc 969 #define CORDIO_LLCCTRL_BATTERY_STATUS_REQUEST_ASSERT() (CMSDK_GPIO2->DATAOUT |=CORDIO_LLCCTRL_BATTERY_STATUS_REQUEST_BIT)
AnnaBridge 171:3a7713b1edbc 970 #define CORDIO_LLCCTRL_BATTERY_STATUS_REQUEST_NEGATE() (CMSDK_GPIO2->DATAOUT &=~CORDIO_LLCCTRL_BATTERY_STATUS_REQUEST_BIT)
AnnaBridge 171:3a7713b1edbc 971
AnnaBridge 171:3a7713b1edbc 972 // ACTIVE HIGH
AnnaBridge 171:3a7713b1edbc 973 #define CORDIO_LLCCTRL_32M_XTAL_REQUEST_ASSERT() (CMSDK_GPIO2->DATAOUT |=CORDIO_LLCCTRL_32M_XTAL_REQUEST_BIT)
AnnaBridge 171:3a7713b1edbc 974 #define CORDIO_LLCCTRL_32M_XTAL_REQUEST_NEGATE() (CMSDK_GPIO2->DATAOUT &=~CORDIO_LLCCTRL_32M_XTAL_REQUEST_BIT)
AnnaBridge 171:3a7713b1edbc 975 // ASSERTS HIGH
AnnaBridge 171:3a7713b1edbc 976 #define CORDIO_LLCCTRL_VMEM_ON_ASSERT() (CMSDK_GPIO3->DATAOUT |=CORDIO_LLCCTRL_VMEM_ON_BIT)
AnnaBridge 171:3a7713b1edbc 977 #define CORDIO_LLCCTRL_VMEM_ON_NEGATE() (CMSDK_GPIO3->DATAOUT &=~CORDIO_LLCCTRL_VMEM_ON_BIT)
AnnaBridge 171:3a7713b1edbc 978
AnnaBridge 171:3a7713b1edbc 979
AnnaBridge 171:3a7713b1edbc 980 /************ READ STATUS ********************/
AnnaBridge 171:3a7713b1edbc 981
AnnaBridge 171:3a7713b1edbc 982 // ACTIVE HIGH, BIT INDEPANDENT
AnnaBridge 171:3a7713b1edbc 983 #define CORDIO_LLCCTRL_RESET_SYNDROME_GET() (CMSDK_GPIO2->DATA & CORDIO_LLCCTRL_RESET_SYNDROME_MSK)
AnnaBridge 171:3a7713b1edbc 984 // ACTIVE HIGH
AnnaBridge 171:3a7713b1edbc 985 #define CORDIO_LLCCTRL_STATUS_ACTIVE_32KXTAL_GET() (CMSDK_GPIO2->DATA & CORDIO_LLCCTRL_STATUS_ACTIVE_32KXTAL_BIT)
AnnaBridge 171:3a7713b1edbc 986 // ACTIVE HIGH
AnnaBridge 171:3a7713b1edbc 987 #define CORDIO_LLCCTRL_STATUS_ACTIVE_32MXTAL_GET() (CMSDK_GPIO2->DATA & CORDIO_LLCCTRL_STATUS_ACTIVE_32MXTAL_BIT)
AnnaBridge 171:3a7713b1edbc 988 // ACTIVE HIGH
AnnaBridge 171:3a7713b1edbc 989 #define CORDIO_LLCCTRL_STATUS_BATTERY_DET3V_GET() (CMSDK_GPIO2->DATA & CORDIO_LLCCTRL_STATUS_BATTERY_DET3V_BIT)
AnnaBridge 171:3a7713b1edbc 990 // ACTIVE HIGH
AnnaBridge 171:3a7713b1edbc 991 #define CORDIO_LLCCTRL_STATUS_BATTERY_STATUS_GET() (CMSDK_GPIO2->DATA & CORDIO_LLCCTRL_STATUS_BATTERY_STATUS_BIT)
AnnaBridge 171:3a7713b1edbc 992 // ACTIVE HIGH
AnnaBridge 171:3a7713b1edbc 993 #define CORDIO_LLCCTRL_STATUS_V1V_ON_STATUS_GET() (CMSDK_GPIO2->DATA & CORDIO_LLCCTRL_STATUS_V1V_ON_STATUS_BIT)
AnnaBridge 171:3a7713b1edbc 994 // ACTIVE HIGH
AnnaBridge 171:3a7713b1edbc 995 #define CORDIO_LLCCTRL_STATUS_AWAKE_GET() (CMSDK_GPIO2->DATA & CORDIO_LLCCTRL_STATUS_AWAKE_BIT)
AnnaBridge 171:3a7713b1edbc 996
AnnaBridge 171:3a7713b1edbc 997
AnnaBridge 171:3a7713b1edbc 998 /* ---- DEBUG MASK & VALUE BITs used for diagnosis ---- */
AnnaBridge 171:3a7713b1edbc 999 #define INSTALL_DEBUG__GPIO_TOGGLES
AnnaBridge 171:3a7713b1edbc 1000
AnnaBridge 171:3a7713b1edbc 1001 #ifdef INSTALL_DEBUG__GPIO_TOGGLES
AnnaBridge 171:3a7713b1edbc 1002
AnnaBridge 171:3a7713b1edbc 1003 #define GPIO_TOGGLES_MSK (0xFC)
AnnaBridge 171:3a7713b1edbc 1004
AnnaBridge 171:3a7713b1edbc 1005 #define BIT_0 (1<<0)
AnnaBridge 171:3a7713b1edbc 1006 #define BIT_1 (1<<1)
AnnaBridge 171:3a7713b1edbc 1007 #define BIT_2 (1<<2)
AnnaBridge 171:3a7713b1edbc 1008 #define BIT_3 (1<<3)
AnnaBridge 171:3a7713b1edbc 1009 #define BIT_4 (1<<4)
AnnaBridge 171:3a7713b1edbc 1010 #define BIT_5 (1<<5)
AnnaBridge 171:3a7713b1edbc 1011 #define BIT_6 (1<<6)
AnnaBridge 171:3a7713b1edbc 1012 #define BIT_7 (1<<7)
AnnaBridge 171:3a7713b1edbc 1013
AnnaBridge 171:3a7713b1edbc 1014 #define BIT_SET(B) (CMSDK_GPIO0->DATAOUT |= ((B) & (GPIO_TOGGLES_MSK)))
AnnaBridge 171:3a7713b1edbc 1015
AnnaBridge 171:3a7713b1edbc 1016 #define BIT_CLR(B) (CMSDK_GPIO0->DATAOUT &= ~((B) & (GPIO_TOGGLES_MSK)))
AnnaBridge 171:3a7713b1edbc 1017
AnnaBridge 171:3a7713b1edbc 1018 /* BIT TOGGLE, XOR */
AnnaBridge 171:3a7713b1edbc 1019 #define BIT_TGL(B) (CMSDK_GPIO0->DATAOUT ^= ((B) & (GPIO_TOGGLES_MSK)))
AnnaBridge 171:3a7713b1edbc 1020
AnnaBridge 171:3a7713b1edbc 1021 #endif
AnnaBridge 171:3a7713b1edbc 1022
AnnaBridge 171:3a7713b1edbc 1023 #ifdef __cplusplus
AnnaBridge 171:3a7713b1edbc 1024 }
AnnaBridge 171:3a7713b1edbc 1025 #endif
AnnaBridge 171:3a7713b1edbc 1026
AnnaBridge 171:3a7713b1edbc 1027 #endif /* CMSDK_BEETLE_H */