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TARGET_DISCO_F334C8/core_caFunc.h@108:34e6b704fe68, 2015-10-02 (annotated)

Committer:
Kojto
Date:
Fri Oct 02 07:35:07 2015 +0200
Revision:
108:34e6b704fe68
Parent:
100:cbbeb26dbd92
Child:
115:87f2f5183dfb
Release 108  of the mbed library



Changes:

- new platforms - ELMO_F411RE, WIZNET_7500P, ARM_MPS2_BEID

- EFM32 - bugfixes in rtc, serial

- Cortex A cmsis - update files

- STML4 - RAM fixes

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Kojto 100:cbbeb26dbd92 1 /**************************************************************************//**
Kojto 100:cbbeb26dbd92 2 * @file core_caFunc.h
Kojto 100:cbbeb26dbd92 3 * @brief CMSIS Cortex-A Core Function Access Header File
Kojto 100:cbbeb26dbd92 4 * @version V3.10
Kojto 108:34e6b704fe68 5 * @date 30 Oct 2013
Kojto 100:cbbeb26dbd92 6 *
Kojto 100:cbbeb26dbd92 7 * @note
Kojto 100:cbbeb26dbd92 8 *
Kojto 100:cbbeb26dbd92 9 ******************************************************************************/
Kojto 108:34e6b704fe68 10 /* Copyright (c) 2009 - 2013 ARM LIMITED
Kojto 100:cbbeb26dbd92 11
Kojto 100:cbbeb26dbd92 12 All rights reserved.
Kojto 100:cbbeb26dbd92 13 Redistribution and use in source and binary forms, with or without
Kojto 100:cbbeb26dbd92 14 modification, are permitted provided that the following conditions are met:
Kojto 100:cbbeb26dbd92 15 - Redistributions of source code must retain the above copyright
Kojto 100:cbbeb26dbd92 16 notice, this list of conditions and the following disclaimer.
Kojto 100:cbbeb26dbd92 17 - Redistributions in binary form must reproduce the above copyright
Kojto 100:cbbeb26dbd92 18 notice, this list of conditions and the following disclaimer in the
Kojto 100:cbbeb26dbd92 19 documentation and/or other materials provided with the distribution.
Kojto 100:cbbeb26dbd92 20 - Neither the name of ARM nor the names of its contributors may be used
Kojto 100:cbbeb26dbd92 21 to endorse or promote products derived from this software without
Kojto 100:cbbeb26dbd92 22 specific prior written permission.
Kojto 100:cbbeb26dbd92 23 *
Kojto 100:cbbeb26dbd92 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Kojto 100:cbbeb26dbd92 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Kojto 100:cbbeb26dbd92 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
Kojto 100:cbbeb26dbd92 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
Kojto 100:cbbeb26dbd92 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
Kojto 100:cbbeb26dbd92 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
Kojto 100:cbbeb26dbd92 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
Kojto 100:cbbeb26dbd92 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
Kojto 100:cbbeb26dbd92 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
Kojto 100:cbbeb26dbd92 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
Kojto 100:cbbeb26dbd92 34 POSSIBILITY OF SUCH DAMAGE.
Kojto 100:cbbeb26dbd92 35 ---------------------------------------------------------------------------*/
Kojto 100:cbbeb26dbd92 36
Kojto 100:cbbeb26dbd92 37
Kojto 100:cbbeb26dbd92 38 #ifndef __CORE_CAFUNC_H__
Kojto 100:cbbeb26dbd92 39 #define __CORE_CAFUNC_H__
Kojto 100:cbbeb26dbd92 40
Kojto 100:cbbeb26dbd92 41
Kojto 100:cbbeb26dbd92 42 /* ########################### Core Function Access ########################### */
Kojto 100:cbbeb26dbd92 43 /** \ingroup CMSIS_Core_FunctionInterface
Kojto 100:cbbeb26dbd92 44 \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
Kojto 100:cbbeb26dbd92 45 @{
Kojto 100:cbbeb26dbd92 46 */
Kojto 100:cbbeb26dbd92 47
Kojto 100:cbbeb26dbd92 48 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
Kojto 100:cbbeb26dbd92 49 /* ARM armcc specific functions */
Kojto 100:cbbeb26dbd92 50
Kojto 100:cbbeb26dbd92 51 #if (__ARMCC_VERSION < 400677)
Kojto 100:cbbeb26dbd92 52 #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
Kojto 100:cbbeb26dbd92 53 #endif
Kojto 100:cbbeb26dbd92 54
Kojto 100:cbbeb26dbd92 55 #define MODE_USR 0x10
Kojto 100:cbbeb26dbd92 56 #define MODE_FIQ 0x11
Kojto 100:cbbeb26dbd92 57 #define MODE_IRQ 0x12
Kojto 100:cbbeb26dbd92 58 #define MODE_SVC 0x13
Kojto 100:cbbeb26dbd92 59 #define MODE_MON 0x16
Kojto 100:cbbeb26dbd92 60 #define MODE_ABT 0x17
Kojto 100:cbbeb26dbd92 61 #define MODE_HYP 0x1A
Kojto 100:cbbeb26dbd92 62 #define MODE_UND 0x1B
Kojto 100:cbbeb26dbd92 63 #define MODE_SYS 0x1F
Kojto 100:cbbeb26dbd92 64
Kojto 100:cbbeb26dbd92 65 /** \brief Get APSR Register
Kojto 100:cbbeb26dbd92 66
Kojto 100:cbbeb26dbd92 67 This function returns the content of the APSR Register.
Kojto 100:cbbeb26dbd92 68
Kojto 100:cbbeb26dbd92 69 \return APSR Register value
Kojto 100:cbbeb26dbd92 70 */
Kojto 100:cbbeb26dbd92 71 __STATIC_INLINE uint32_t __get_APSR(void)
Kojto 100:cbbeb26dbd92 72 {
Kojto 100:cbbeb26dbd92 73 register uint32_t __regAPSR __ASM("apsr");
Kojto 100:cbbeb26dbd92 74 return(__regAPSR);
Kojto 100:cbbeb26dbd92 75 }
Kojto 100:cbbeb26dbd92 76
Kojto 100:cbbeb26dbd92 77
Kojto 100:cbbeb26dbd92 78 /** \brief Get CPSR Register
Kojto 100:cbbeb26dbd92 79
Kojto 100:cbbeb26dbd92 80 This function returns the content of the CPSR Register.
Kojto 100:cbbeb26dbd92 81
Kojto 100:cbbeb26dbd92 82 \return CPSR Register value
Kojto 100:cbbeb26dbd92 83 */
Kojto 100:cbbeb26dbd92 84 __STATIC_INLINE uint32_t __get_CPSR(void)
Kojto 100:cbbeb26dbd92 85 {
Kojto 100:cbbeb26dbd92 86 register uint32_t __regCPSR __ASM("cpsr");
Kojto 100:cbbeb26dbd92 87 return(__regCPSR);
Kojto 100:cbbeb26dbd92 88 }
Kojto 100:cbbeb26dbd92 89
Kojto 100:cbbeb26dbd92 90 /** \brief Set Stack Pointer
Kojto 100:cbbeb26dbd92 91
Kojto 100:cbbeb26dbd92 92 This function assigns the given value to the current stack pointer.
Kojto 100:cbbeb26dbd92 93
Kojto 100:cbbeb26dbd92 94 \param [in] topOfStack Stack Pointer value to set
Kojto 100:cbbeb26dbd92 95 */
Kojto 100:cbbeb26dbd92 96 register uint32_t __regSP __ASM("sp");
Kojto 100:cbbeb26dbd92 97 __STATIC_INLINE void __set_SP(uint32_t topOfStack)
Kojto 100:cbbeb26dbd92 98 {
Kojto 100:cbbeb26dbd92 99 __regSP = topOfStack;
Kojto 100:cbbeb26dbd92 100 }
Kojto 100:cbbeb26dbd92 101
Kojto 100:cbbeb26dbd92 102
Kojto 100:cbbeb26dbd92 103 /** \brief Get link register
Kojto 100:cbbeb26dbd92 104
Kojto 100:cbbeb26dbd92 105 This function returns the value of the link register
Kojto 100:cbbeb26dbd92 106
Kojto 100:cbbeb26dbd92 107 \return Value of link register
Kojto 100:cbbeb26dbd92 108 */
Kojto 100:cbbeb26dbd92 109 register uint32_t __reglr __ASM("lr");
Kojto 100:cbbeb26dbd92 110 __STATIC_INLINE uint32_t __get_LR(void)
Kojto 100:cbbeb26dbd92 111 {
Kojto 100:cbbeb26dbd92 112 return(__reglr);
Kojto 100:cbbeb26dbd92 113 }
Kojto 100:cbbeb26dbd92 114
Kojto 100:cbbeb26dbd92 115 /** \brief Set link register
Kojto 100:cbbeb26dbd92 116
Kojto 100:cbbeb26dbd92 117 This function sets the value of the link register
Kojto 100:cbbeb26dbd92 118
Kojto 100:cbbeb26dbd92 119 \param [in] lr LR value to set
Kojto 100:cbbeb26dbd92 120 */
Kojto 100:cbbeb26dbd92 121 __STATIC_INLINE void __set_LR(uint32_t lr)
Kojto 100:cbbeb26dbd92 122 {
Kojto 100:cbbeb26dbd92 123 __reglr = lr;
Kojto 100:cbbeb26dbd92 124 }
Kojto 100:cbbeb26dbd92 125
Kojto 100:cbbeb26dbd92 126 /** \brief Set Process Stack Pointer
Kojto 100:cbbeb26dbd92 127
Kojto 100:cbbeb26dbd92 128 This function assigns the given value to the USR/SYS Stack Pointer (PSP).
Kojto 100:cbbeb26dbd92 129
Kojto 100:cbbeb26dbd92 130 \param [in] topOfProcStack USR/SYS Stack Pointer value to set
Kojto 100:cbbeb26dbd92 131 */
Kojto 100:cbbeb26dbd92 132 __STATIC_ASM void __set_PSP(uint32_t topOfProcStack)
Kojto 100:cbbeb26dbd92 133 {
Kojto 100:cbbeb26dbd92 134 ARM
Kojto 100:cbbeb26dbd92 135 PRESERVE8
Kojto 100:cbbeb26dbd92 136
Kojto 100:cbbeb26dbd92 137 BIC R0, R0, #7 ;ensure stack is 8-byte aligned
Kojto 100:cbbeb26dbd92 138 MRS R1, CPSR
Kojto 100:cbbeb26dbd92 139 CPS #MODE_SYS ;no effect in USR mode
Kojto 100:cbbeb26dbd92 140 MOV SP, R0
Kojto 100:cbbeb26dbd92 141 MSR CPSR_c, R1 ;no effect in USR mode
Kojto 100:cbbeb26dbd92 142 ISB
Kojto 100:cbbeb26dbd92 143 BX LR
Kojto 100:cbbeb26dbd92 144
Kojto 100:cbbeb26dbd92 145 }
Kojto 100:cbbeb26dbd92 146
Kojto 100:cbbeb26dbd92 147 /** \brief Set User Mode
Kojto 100:cbbeb26dbd92 148
Kojto 100:cbbeb26dbd92 149 This function changes the processor state to User Mode
Kojto 100:cbbeb26dbd92 150 */
Kojto 100:cbbeb26dbd92 151 __STATIC_ASM void __set_CPS_USR(void)
Kojto 100:cbbeb26dbd92 152 {
Kojto 100:cbbeb26dbd92 153 ARM
Kojto 100:cbbeb26dbd92 154
Kojto 100:cbbeb26dbd92 155 CPS #MODE_USR
Kojto 100:cbbeb26dbd92 156 BX LR
Kojto 100:cbbeb26dbd92 157 }
Kojto 100:cbbeb26dbd92 158
Kojto 100:cbbeb26dbd92 159
Kojto 100:cbbeb26dbd92 160 /** \brief Enable FIQ
Kojto 100:cbbeb26dbd92 161
Kojto 100:cbbeb26dbd92 162 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
Kojto 100:cbbeb26dbd92 163 Can only be executed in Privileged modes.
Kojto 100:cbbeb26dbd92 164 */
Kojto 100:cbbeb26dbd92 165 #define __enable_fault_irq __enable_fiq
Kojto 100:cbbeb26dbd92 166
Kojto 100:cbbeb26dbd92 167
Kojto 100:cbbeb26dbd92 168 /** \brief Disable FIQ
Kojto 100:cbbeb26dbd92 169
Kojto 100:cbbeb26dbd92 170 This function disables FIQ interrupts by setting the F-bit in the CPSR.
Kojto 100:cbbeb26dbd92 171 Can only be executed in Privileged modes.
Kojto 100:cbbeb26dbd92 172 */
Kojto 100:cbbeb26dbd92 173 #define __disable_fault_irq __disable_fiq
Kojto 100:cbbeb26dbd92 174
Kojto 100:cbbeb26dbd92 175
Kojto 100:cbbeb26dbd92 176 /** \brief Get FPSCR
Kojto 100:cbbeb26dbd92 177
Kojto 100:cbbeb26dbd92 178 This function returns the current value of the Floating Point Status/Control register.
Kojto 100:cbbeb26dbd92 179
Kojto 100:cbbeb26dbd92 180 \return Floating Point Status/Control register value
Kojto 100:cbbeb26dbd92 181 */
Kojto 100:cbbeb26dbd92 182 __STATIC_INLINE uint32_t __get_FPSCR(void)
Kojto 100:cbbeb26dbd92 183 {
Kojto 100:cbbeb26dbd92 184 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
Kojto 100:cbbeb26dbd92 185 register uint32_t __regfpscr __ASM("fpscr");
Kojto 100:cbbeb26dbd92 186 return(__regfpscr);
Kojto 100:cbbeb26dbd92 187 #else
Kojto 100:cbbeb26dbd92 188 return(0);
Kojto 100:cbbeb26dbd92 189 #endif
Kojto 100:cbbeb26dbd92 190 }
Kojto 100:cbbeb26dbd92 191
Kojto 100:cbbeb26dbd92 192
Kojto 100:cbbeb26dbd92 193 /** \brief Set FPSCR
Kojto 100:cbbeb26dbd92 194
Kojto 100:cbbeb26dbd92 195 This function assigns the given value to the Floating Point Status/Control register.
Kojto 100:cbbeb26dbd92 196
Kojto 100:cbbeb26dbd92 197 \param [in] fpscr Floating Point Status/Control value to set
Kojto 100:cbbeb26dbd92 198 */
Kojto 100:cbbeb26dbd92 199 __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
Kojto 100:cbbeb26dbd92 200 {
Kojto 100:cbbeb26dbd92 201 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
Kojto 100:cbbeb26dbd92 202 register uint32_t __regfpscr __ASM("fpscr");
Kojto 100:cbbeb26dbd92 203 __regfpscr = (fpscr);
Kojto 100:cbbeb26dbd92 204 #endif
Kojto 100:cbbeb26dbd92 205 }
Kojto 100:cbbeb26dbd92 206
Kojto 100:cbbeb26dbd92 207 /** \brief Get FPEXC
Kojto 100:cbbeb26dbd92 208
Kojto 100:cbbeb26dbd92 209 This function returns the current value of the Floating Point Exception Control register.
Kojto 100:cbbeb26dbd92 210
Kojto 100:cbbeb26dbd92 211 \return Floating Point Exception Control register value
Kojto 100:cbbeb26dbd92 212 */
Kojto 100:cbbeb26dbd92 213 __STATIC_INLINE uint32_t __get_FPEXC(void)
Kojto 100:cbbeb26dbd92 214 {
Kojto 100:cbbeb26dbd92 215 #if (__FPU_PRESENT == 1)
Kojto 100:cbbeb26dbd92 216 register uint32_t __regfpexc __ASM("fpexc");
Kojto 100:cbbeb26dbd92 217 return(__regfpexc);
Kojto 100:cbbeb26dbd92 218 #else
Kojto 100:cbbeb26dbd92 219 return(0);
Kojto 100:cbbeb26dbd92 220 #endif
Kojto 100:cbbeb26dbd92 221 }
Kojto 100:cbbeb26dbd92 222
Kojto 100:cbbeb26dbd92 223
Kojto 100:cbbeb26dbd92 224 /** \brief Set FPEXC
Kojto 100:cbbeb26dbd92 225
Kojto 100:cbbeb26dbd92 226 This function assigns the given value to the Floating Point Exception Control register.
Kojto 100:cbbeb26dbd92 227
Kojto 100:cbbeb26dbd92 228 \param [in] fpscr Floating Point Exception Control value to set
Kojto 100:cbbeb26dbd92 229 */
Kojto 100:cbbeb26dbd92 230 __STATIC_INLINE void __set_FPEXC(uint32_t fpexc)
Kojto 100:cbbeb26dbd92 231 {
Kojto 100:cbbeb26dbd92 232 #if (__FPU_PRESENT == 1)
Kojto 100:cbbeb26dbd92 233 register uint32_t __regfpexc __ASM("fpexc");
Kojto 100:cbbeb26dbd92 234 __regfpexc = (fpexc);
Kojto 100:cbbeb26dbd92 235 #endif
Kojto 100:cbbeb26dbd92 236 }
Kojto 100:cbbeb26dbd92 237
Kojto 100:cbbeb26dbd92 238 /** \brief Get CPACR
Kojto 100:cbbeb26dbd92 239
Kojto 100:cbbeb26dbd92 240 This function returns the current value of the Coprocessor Access Control register.
Kojto 100:cbbeb26dbd92 241
Kojto 100:cbbeb26dbd92 242 \return Coprocessor Access Control register value
Kojto 100:cbbeb26dbd92 243 */
Kojto 100:cbbeb26dbd92 244 __STATIC_INLINE uint32_t __get_CPACR(void)
Kojto 100:cbbeb26dbd92 245 {
Kojto 100:cbbeb26dbd92 246 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
Kojto 100:cbbeb26dbd92 247 return __regCPACR;
Kojto 100:cbbeb26dbd92 248 }
Kojto 100:cbbeb26dbd92 249
Kojto 100:cbbeb26dbd92 250 /** \brief Set CPACR
Kojto 100:cbbeb26dbd92 251
Kojto 100:cbbeb26dbd92 252 This function assigns the given value to the Coprocessor Access Control register.
Kojto 100:cbbeb26dbd92 253
Kojto 108:34e6b704fe68 254 \param [in] cpacr Coprocessor Acccess Control value to set
Kojto 100:cbbeb26dbd92 255 */
Kojto 100:cbbeb26dbd92 256 __STATIC_INLINE void __set_CPACR(uint32_t cpacr)
Kojto 100:cbbeb26dbd92 257 {
Kojto 100:cbbeb26dbd92 258 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
Kojto 100:cbbeb26dbd92 259 __regCPACR = cpacr;
Kojto 100:cbbeb26dbd92 260 __ISB();
Kojto 100:cbbeb26dbd92 261 }
Kojto 100:cbbeb26dbd92 262
Kojto 100:cbbeb26dbd92 263 /** \brief Get CBAR
Kojto 100:cbbeb26dbd92 264
Kojto 100:cbbeb26dbd92 265 This function returns the value of the Configuration Base Address register.
Kojto 100:cbbeb26dbd92 266
Kojto 100:cbbeb26dbd92 267 \return Configuration Base Address register value
Kojto 100:cbbeb26dbd92 268 */
Kojto 100:cbbeb26dbd92 269 __STATIC_INLINE uint32_t __get_CBAR() {
Kojto 100:cbbeb26dbd92 270 register uint32_t __regCBAR __ASM("cp15:4:c15:c0:0");
Kojto 100:cbbeb26dbd92 271 return(__regCBAR);
Kojto 100:cbbeb26dbd92 272 }
Kojto 100:cbbeb26dbd92 273
Kojto 100:cbbeb26dbd92 274 /** \brief Get TTBR0
Kojto 100:cbbeb26dbd92 275
Kojto 108:34e6b704fe68 276 This function returns the value of the Translation Table Base Register 0.
Kojto 100:cbbeb26dbd92 277
Kojto 100:cbbeb26dbd92 278 \return Translation Table Base Register 0 value
Kojto 100:cbbeb26dbd92 279 */
Kojto 100:cbbeb26dbd92 280 __STATIC_INLINE uint32_t __get_TTBR0() {
Kojto 100:cbbeb26dbd92 281 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
Kojto 100:cbbeb26dbd92 282 return(__regTTBR0);
Kojto 100:cbbeb26dbd92 283 }
Kojto 100:cbbeb26dbd92 284
Kojto 100:cbbeb26dbd92 285 /** \brief Set TTBR0
Kojto 100:cbbeb26dbd92 286
Kojto 108:34e6b704fe68 287 This function assigns the given value to the Translation Table Base Register 0.
Kojto 100:cbbeb26dbd92 288
Kojto 100:cbbeb26dbd92 289 \param [in] ttbr0 Translation Table Base Register 0 value to set
Kojto 100:cbbeb26dbd92 290 */
Kojto 100:cbbeb26dbd92 291 __STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) {
Kojto 100:cbbeb26dbd92 292 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
Kojto 100:cbbeb26dbd92 293 __regTTBR0 = ttbr0;
Kojto 100:cbbeb26dbd92 294 __ISB();
Kojto 100:cbbeb26dbd92 295 }
Kojto 100:cbbeb26dbd92 296
Kojto 100:cbbeb26dbd92 297 /** \brief Get DACR
Kojto 100:cbbeb26dbd92 298
Kojto 100:cbbeb26dbd92 299 This function returns the value of the Domain Access Control Register.
Kojto 100:cbbeb26dbd92 300
Kojto 100:cbbeb26dbd92 301 \return Domain Access Control Register value
Kojto 100:cbbeb26dbd92 302 */
Kojto 100:cbbeb26dbd92 303 __STATIC_INLINE uint32_t __get_DACR() {
Kojto 100:cbbeb26dbd92 304 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
Kojto 100:cbbeb26dbd92 305 return(__regDACR);
Kojto 100:cbbeb26dbd92 306 }
Kojto 100:cbbeb26dbd92 307
Kojto 100:cbbeb26dbd92 308 /** \brief Set DACR
Kojto 100:cbbeb26dbd92 309
Kojto 108:34e6b704fe68 310 This function assigns the given value to the Domain Access Control Register.
Kojto 100:cbbeb26dbd92 311
Kojto 100:cbbeb26dbd92 312 \param [in] dacr Domain Access Control Register value to set
Kojto 100:cbbeb26dbd92 313 */
Kojto 100:cbbeb26dbd92 314 __STATIC_INLINE void __set_DACR(uint32_t dacr) {
Kojto 100:cbbeb26dbd92 315 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
Kojto 100:cbbeb26dbd92 316 __regDACR = dacr;
Kojto 100:cbbeb26dbd92 317 __ISB();
Kojto 100:cbbeb26dbd92 318 }
Kojto 100:cbbeb26dbd92 319
Kojto 100:cbbeb26dbd92 320 /******************************** Cache and BTAC enable ****************************************************/
Kojto 100:cbbeb26dbd92 321
Kojto 100:cbbeb26dbd92 322 /** \brief Set SCTLR
Kojto 100:cbbeb26dbd92 323
Kojto 100:cbbeb26dbd92 324 This function assigns the given value to the System Control Register.
Kojto 100:cbbeb26dbd92 325
Kojto 108:34e6b704fe68 326 \param [in] sctlr System Control Register value to set
Kojto 100:cbbeb26dbd92 327 */
Kojto 100:cbbeb26dbd92 328 __STATIC_INLINE void __set_SCTLR(uint32_t sctlr)
Kojto 100:cbbeb26dbd92 329 {
Kojto 100:cbbeb26dbd92 330 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
Kojto 100:cbbeb26dbd92 331 __regSCTLR = sctlr;
Kojto 100:cbbeb26dbd92 332 }
Kojto 100:cbbeb26dbd92 333
Kojto 100:cbbeb26dbd92 334 /** \brief Get SCTLR
Kojto 100:cbbeb26dbd92 335
Kojto 100:cbbeb26dbd92 336 This function returns the value of the System Control Register.
Kojto 100:cbbeb26dbd92 337
Kojto 100:cbbeb26dbd92 338 \return System Control Register value
Kojto 100:cbbeb26dbd92 339 */
Kojto 100:cbbeb26dbd92 340 __STATIC_INLINE uint32_t __get_SCTLR() {
Kojto 100:cbbeb26dbd92 341 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
Kojto 100:cbbeb26dbd92 342 return(__regSCTLR);
Kojto 100:cbbeb26dbd92 343 }
Kojto 100:cbbeb26dbd92 344
Kojto 100:cbbeb26dbd92 345 /** \brief Enable Caches
Kojto 100:cbbeb26dbd92 346
Kojto 100:cbbeb26dbd92 347 Enable Caches
Kojto 100:cbbeb26dbd92 348 */
Kojto 100:cbbeb26dbd92 349 __STATIC_INLINE void __enable_caches(void) {
Kojto 100:cbbeb26dbd92 350 // Set I bit 12 to enable I Cache
Kojto 100:cbbeb26dbd92 351 // Set C bit 2 to enable D Cache
Kojto 100:cbbeb26dbd92 352 __set_SCTLR( __get_SCTLR() | (1 << 12) | (1 << 2));
Kojto 100:cbbeb26dbd92 353 }
Kojto 100:cbbeb26dbd92 354
Kojto 100:cbbeb26dbd92 355 /** \brief Disable Caches
Kojto 100:cbbeb26dbd92 356
Kojto 100:cbbeb26dbd92 357 Disable Caches
Kojto 100:cbbeb26dbd92 358 */
Kojto 100:cbbeb26dbd92 359 __STATIC_INLINE void __disable_caches(void) {
Kojto 100:cbbeb26dbd92 360 // Clear I bit 12 to disable I Cache
Kojto 100:cbbeb26dbd92 361 // Clear C bit 2 to disable D Cache
Kojto 100:cbbeb26dbd92 362 __set_SCTLR( __get_SCTLR() & ~(1 << 12) & ~(1 << 2));
Kojto 100:cbbeb26dbd92 363 __ISB();
Kojto 100:cbbeb26dbd92 364 }
Kojto 100:cbbeb26dbd92 365
Kojto 100:cbbeb26dbd92 366 /** \brief Enable BTAC
Kojto 100:cbbeb26dbd92 367
Kojto 100:cbbeb26dbd92 368 Enable BTAC
Kojto 100:cbbeb26dbd92 369 */
Kojto 100:cbbeb26dbd92 370 __STATIC_INLINE void __enable_btac(void) {
Kojto 100:cbbeb26dbd92 371 // Set Z bit 11 to enable branch prediction
Kojto 100:cbbeb26dbd92 372 __set_SCTLR( __get_SCTLR() | (1 << 11));
Kojto 100:cbbeb26dbd92 373 __ISB();
Kojto 100:cbbeb26dbd92 374 }
Kojto 100:cbbeb26dbd92 375
Kojto 100:cbbeb26dbd92 376 /** \brief Disable BTAC
Kojto 100:cbbeb26dbd92 377
Kojto 100:cbbeb26dbd92 378 Disable BTAC
Kojto 100:cbbeb26dbd92 379 */
Kojto 100:cbbeb26dbd92 380 __STATIC_INLINE void __disable_btac(void) {
Kojto 100:cbbeb26dbd92 381 // Clear Z bit 11 to disable branch prediction
Kojto 100:cbbeb26dbd92 382 __set_SCTLR( __get_SCTLR() & ~(1 << 11));
Kojto 100:cbbeb26dbd92 383 }
Kojto 100:cbbeb26dbd92 384
Kojto 100:cbbeb26dbd92 385
Kojto 100:cbbeb26dbd92 386 /** \brief Enable MMU
Kojto 100:cbbeb26dbd92 387
Kojto 100:cbbeb26dbd92 388 Enable MMU
Kojto 100:cbbeb26dbd92 389 */
Kojto 100:cbbeb26dbd92 390 __STATIC_INLINE void __enable_mmu(void) {
Kojto 100:cbbeb26dbd92 391 // Set M bit 0 to enable the MMU
Kojto 100:cbbeb26dbd92 392 // Set AFE bit to enable simplified access permissions model
Kojto 100:cbbeb26dbd92 393 // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking
Kojto 100:cbbeb26dbd92 394 __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29));
Kojto 100:cbbeb26dbd92 395 __ISB();
Kojto 100:cbbeb26dbd92 396 }
Kojto 100:cbbeb26dbd92 397
Kojto 108:34e6b704fe68 398 /** \brief Disable MMU
Kojto 100:cbbeb26dbd92 399
Kojto 108:34e6b704fe68 400 Disable MMU
Kojto 100:cbbeb26dbd92 401 */
Kojto 100:cbbeb26dbd92 402 __STATIC_INLINE void __disable_mmu(void) {
Kojto 100:cbbeb26dbd92 403 // Clear M bit 0 to disable the MMU
Kojto 100:cbbeb26dbd92 404 __set_SCTLR( __get_SCTLR() & ~1);
Kojto 100:cbbeb26dbd92 405 __ISB();
Kojto 100:cbbeb26dbd92 406 }
Kojto 100:cbbeb26dbd92 407
Kojto 100:cbbeb26dbd92 408 /******************************** TLB maintenance operations ************************************************/
Kojto 100:cbbeb26dbd92 409 /** \brief Invalidate the whole tlb
Kojto 100:cbbeb26dbd92 410
Kojto 100:cbbeb26dbd92 411 TLBIALL. Invalidate the whole tlb
Kojto 100:cbbeb26dbd92 412 */
Kojto 100:cbbeb26dbd92 413
Kojto 100:cbbeb26dbd92 414 __STATIC_INLINE void __ca9u_inv_tlb_all(void) {
Kojto 100:cbbeb26dbd92 415 register uint32_t __TLBIALL __ASM("cp15:0:c8:c7:0");
Kojto 100:cbbeb26dbd92 416 __TLBIALL = 0;
Kojto 100:cbbeb26dbd92 417 __DSB();
Kojto 100:cbbeb26dbd92 418 __ISB();
Kojto 100:cbbeb26dbd92 419 }
Kojto 100:cbbeb26dbd92 420
Kojto 100:cbbeb26dbd92 421 /******************************** BTB maintenance operations ************************************************/
Kojto 100:cbbeb26dbd92 422 /** \brief Invalidate entire branch predictor array
Kojto 100:cbbeb26dbd92 423
Kojto 100:cbbeb26dbd92 424 BPIALL. Branch Predictor Invalidate All.
Kojto 100:cbbeb26dbd92 425 */
Kojto 100:cbbeb26dbd92 426
Kojto 100:cbbeb26dbd92 427 __STATIC_INLINE void __v7_inv_btac(void) {
Kojto 100:cbbeb26dbd92 428 register uint32_t __BPIALL __ASM("cp15:0:c7:c5:6");
Kojto 100:cbbeb26dbd92 429 __BPIALL = 0;
Kojto 100:cbbeb26dbd92 430 __DSB(); //ensure completion of the invalidation
Kojto 100:cbbeb26dbd92 431 __ISB(); //ensure instruction fetch path sees new state
Kojto 100:cbbeb26dbd92 432 }
Kojto 100:cbbeb26dbd92 433
Kojto 100:cbbeb26dbd92 434
Kojto 100:cbbeb26dbd92 435 /******************************** L1 cache operations ******************************************************/
Kojto 100:cbbeb26dbd92 436
Kojto 100:cbbeb26dbd92 437 /** \brief Invalidate the whole I$
Kojto 100:cbbeb26dbd92 438
Kojto 100:cbbeb26dbd92 439 ICIALLU. Instruction Cache Invalidate All to PoU
Kojto 100:cbbeb26dbd92 440 */
Kojto 100:cbbeb26dbd92 441 __STATIC_INLINE void __v7_inv_icache_all(void) {
Kojto 100:cbbeb26dbd92 442 register uint32_t __ICIALLU __ASM("cp15:0:c7:c5:0");
Kojto 100:cbbeb26dbd92 443 __ICIALLU = 0;
Kojto 100:cbbeb26dbd92 444 __DSB(); //ensure completion of the invalidation
Kojto 100:cbbeb26dbd92 445 __ISB(); //ensure instruction fetch path sees new I cache state
Kojto 100:cbbeb26dbd92 446 }
Kojto 100:cbbeb26dbd92 447
Kojto 100:cbbeb26dbd92 448 /** \brief Clean D$ by MVA
Kojto 100:cbbeb26dbd92 449
Kojto 100:cbbeb26dbd92 450 DCCMVAC. Data cache clean by MVA to PoC
Kojto 100:cbbeb26dbd92 451 */
Kojto 100:cbbeb26dbd92 452 __STATIC_INLINE void __v7_clean_dcache_mva(void *va) {
Kojto 100:cbbeb26dbd92 453 register uint32_t __DCCMVAC __ASM("cp15:0:c7:c10:1");
Kojto 100:cbbeb26dbd92 454 __DCCMVAC = (uint32_t)va;
Kojto 100:cbbeb26dbd92 455 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
Kojto 100:cbbeb26dbd92 456 }
Kojto 100:cbbeb26dbd92 457
Kojto 100:cbbeb26dbd92 458 /** \brief Invalidate D$ by MVA
Kojto 100:cbbeb26dbd92 459
Kojto 100:cbbeb26dbd92 460 DCIMVAC. Data cache invalidate by MVA to PoC
Kojto 100:cbbeb26dbd92 461 */
Kojto 100:cbbeb26dbd92 462 __STATIC_INLINE void __v7_inv_dcache_mva(void *va) {
Kojto 100:cbbeb26dbd92 463 register uint32_t __DCIMVAC __ASM("cp15:0:c7:c6:1");
Kojto 100:cbbeb26dbd92 464 __DCIMVAC = (uint32_t)va;
Kojto 100:cbbeb26dbd92 465 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
Kojto 100:cbbeb26dbd92 466 }
Kojto 100:cbbeb26dbd92 467
Kojto 100:cbbeb26dbd92 468 /** \brief Clean and Invalidate D$ by MVA
Kojto 100:cbbeb26dbd92 469
Kojto 100:cbbeb26dbd92 470 DCCIMVAC. Data cache clean and invalidate by MVA to PoC
Kojto 100:cbbeb26dbd92 471 */
Kojto 100:cbbeb26dbd92 472 __STATIC_INLINE void __v7_clean_inv_dcache_mva(void *va) {
Kojto 100:cbbeb26dbd92 473 register uint32_t __DCCIMVAC __ASM("cp15:0:c7:c14:1");
Kojto 100:cbbeb26dbd92 474 __DCCIMVAC = (uint32_t)va;
Kojto 100:cbbeb26dbd92 475 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
Kojto 100:cbbeb26dbd92 476 }
Kojto 100:cbbeb26dbd92 477
Kojto 108:34e6b704fe68 478 /** \brief Clean and Invalidate the entire data or unified cache
Kojto 108:34e6b704fe68 479
Kojto 108:34e6b704fe68 480 Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency.
Kojto 100:cbbeb26dbd92 481 */
Kojto 100:cbbeb26dbd92 482 #pragma push
Kojto 100:cbbeb26dbd92 483 #pragma arm
Kojto 100:cbbeb26dbd92 484 __STATIC_ASM void __v7_all_cache(uint32_t op) {
Kojto 100:cbbeb26dbd92 485 ARM
Kojto 100:cbbeb26dbd92 486
Kojto 100:cbbeb26dbd92 487 PUSH {R4-R11}
Kojto 100:cbbeb26dbd92 488
Kojto 100:cbbeb26dbd92 489 MRC p15, 1, R6, c0, c0, 1 // Read CLIDR
Kojto 100:cbbeb26dbd92 490 ANDS R3, R6, #0x07000000 // Extract coherency level
Kojto 100:cbbeb26dbd92 491 MOV R3, R3, LSR #23 // Total cache levels << 1
Kojto 100:cbbeb26dbd92 492 BEQ Finished // If 0, no need to clean
Kojto 100:cbbeb26dbd92 493
Kojto 100:cbbeb26dbd92 494 MOV R10, #0 // R10 holds current cache level << 1
Kojto 100:cbbeb26dbd92 495 Loop1 ADD R2, R10, R10, LSR #1 // R2 holds cache "Set" position
Kojto 100:cbbeb26dbd92 496 MOV R1, R6, LSR R2 // Bottom 3 bits are the Cache-type for this level
Kojto 100:cbbeb26dbd92 497 AND R1, R1, #7 // Isolate those lower 3 bits
Kojto 100:cbbeb26dbd92 498 CMP R1, #2
Kojto 100:cbbeb26dbd92 499 BLT Skip // No cache or only instruction cache at this level
Kojto 100:cbbeb26dbd92 500
Kojto 100:cbbeb26dbd92 501 MCR p15, 2, R10, c0, c0, 0 // Write the Cache Size selection register
Kojto 100:cbbeb26dbd92 502 ISB // ISB to sync the change to the CacheSizeID reg
Kojto 100:cbbeb26dbd92 503 MRC p15, 1, R1, c0, c0, 0 // Reads current Cache Size ID register
Kojto 100:cbbeb26dbd92 504 AND R2, R1, #7 // Extract the line length field
Kojto 100:cbbeb26dbd92 505 ADD R2, R2, #4 // Add 4 for the line length offset (log2 16 bytes)
Kojto 100:cbbeb26dbd92 506 LDR R4, =0x3FF
Kojto 100:cbbeb26dbd92 507 ANDS R4, R4, R1, LSR #3 // R4 is the max number on the way size (right aligned)
Kojto 100:cbbeb26dbd92 508 CLZ R5, R4 // R5 is the bit position of the way size increment
Kojto 100:cbbeb26dbd92 509 LDR R7, =0x7FFF
Kojto 100:cbbeb26dbd92 510 ANDS R7, R7, R1, LSR #13 // R7 is the max number of the index size (right aligned)
Kojto 100:cbbeb26dbd92 511
Kojto 100:cbbeb26dbd92 512 Loop2 MOV R9, R4 // R9 working copy of the max way size (right aligned)
Kojto 100:cbbeb26dbd92 513
Kojto 100:cbbeb26dbd92 514 Loop3 ORR R11, R10, R9, LSL R5 // Factor in the Way number and cache number into R11
Kojto 100:cbbeb26dbd92 515 ORR R11, R11, R7, LSL R2 // Factor in the Set number
Kojto 100:cbbeb26dbd92 516 CMP R0, #0
Kojto 100:cbbeb26dbd92 517 BNE Dccsw
Kojto 100:cbbeb26dbd92 518 MCR p15, 0, R11, c7, c6, 2 // DCISW. Invalidate by Set/Way
Kojto 100:cbbeb26dbd92 519 B cont
Kojto 100:cbbeb26dbd92 520 Dccsw CMP R0, #1
Kojto 100:cbbeb26dbd92 521 BNE Dccisw
Kojto 100:cbbeb26dbd92 522 MCR p15, 0, R11, c7, c10, 2 // DCCSW. Clean by Set/Way
Kojto 100:cbbeb26dbd92 523 B cont
Kojto 108:34e6b704fe68 524 Dccisw MCR p15, 0, R11, c7, c14, 2 // DCCISW. Clean and Invalidate by Set/Way
Kojto 100:cbbeb26dbd92 525 cont SUBS R9, R9, #1 // Decrement the Way number
Kojto 100:cbbeb26dbd92 526 BGE Loop3
Kojto 100:cbbeb26dbd92 527 SUBS R7, R7, #1 // Decrement the Set number
Kojto 100:cbbeb26dbd92 528 BGE Loop2
Kojto 108:34e6b704fe68 529 Skip ADD R10, R10, #2 // Increment the cache number
Kojto 100:cbbeb26dbd92 530 CMP R3, R10
Kojto 100:cbbeb26dbd92 531 BGT Loop1
Kojto 100:cbbeb26dbd92 532
Kojto 100:cbbeb26dbd92 533 Finished
Kojto 100:cbbeb26dbd92 534 DSB
Kojto 100:cbbeb26dbd92 535 POP {R4-R11}
Kojto 100:cbbeb26dbd92 536 BX lr
Kojto 100:cbbeb26dbd92 537
Kojto 100:cbbeb26dbd92 538 }
Kojto 100:cbbeb26dbd92 539 #pragma pop
Kojto 100:cbbeb26dbd92 540
Kojto 100:cbbeb26dbd92 541
Kojto 100:cbbeb26dbd92 542 /** \brief Invalidate the whole D$
Kojto 100:cbbeb26dbd92 543
Kojto 100:cbbeb26dbd92 544 DCISW. Invalidate by Set/Way
Kojto 100:cbbeb26dbd92 545 */
Kojto 100:cbbeb26dbd92 546
Kojto 100:cbbeb26dbd92 547 __STATIC_INLINE void __v7_inv_dcache_all(void) {
Kojto 100:cbbeb26dbd92 548 __v7_all_cache(0);
Kojto 100:cbbeb26dbd92 549 }
Kojto 100:cbbeb26dbd92 550
Kojto 100:cbbeb26dbd92 551 /** \brief Clean the whole D$
Kojto 100:cbbeb26dbd92 552
Kojto 100:cbbeb26dbd92 553 DCCSW. Clean by Set/Way
Kojto 100:cbbeb26dbd92 554 */
Kojto 100:cbbeb26dbd92 555
Kojto 100:cbbeb26dbd92 556 __STATIC_INLINE void __v7_clean_dcache_all(void) {
Kojto 100:cbbeb26dbd92 557 __v7_all_cache(1);
Kojto 100:cbbeb26dbd92 558 }
Kojto 100:cbbeb26dbd92 559
Kojto 100:cbbeb26dbd92 560 /** \brief Clean and invalidate the whole D$
Kojto 100:cbbeb26dbd92 561
Kojto 100:cbbeb26dbd92 562 DCCISW. Clean and Invalidate by Set/Way
Kojto 100:cbbeb26dbd92 563 */
Kojto 100:cbbeb26dbd92 564
Kojto 100:cbbeb26dbd92 565 __STATIC_INLINE void __v7_clean_inv_dcache_all(void) {
Kojto 100:cbbeb26dbd92 566 __v7_all_cache(2);
Kojto 100:cbbeb26dbd92 567 }
Kojto 100:cbbeb26dbd92 568
Kojto 100:cbbeb26dbd92 569 #include "core_ca_mmu.h"
Kojto 100:cbbeb26dbd92 570
Kojto 100:cbbeb26dbd92 571 #elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/
Kojto 100:cbbeb26dbd92 572
Kojto 100:cbbeb26dbd92 573 #error IAR Compiler support not implemented for Cortex-A
Kojto 100:cbbeb26dbd92 574
Kojto 100:cbbeb26dbd92 575 #elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
Kojto 100:cbbeb26dbd92 576 /* GNU gcc specific functions */
Kojto 100:cbbeb26dbd92 577
Kojto 100:cbbeb26dbd92 578 #define MODE_USR 0x10
Kojto 100:cbbeb26dbd92 579 #define MODE_FIQ 0x11
Kojto 100:cbbeb26dbd92 580 #define MODE_IRQ 0x12
Kojto 100:cbbeb26dbd92 581 #define MODE_SVC 0x13
Kojto 100:cbbeb26dbd92 582 #define MODE_MON 0x16
Kojto 100:cbbeb26dbd92 583 #define MODE_ABT 0x17
Kojto 100:cbbeb26dbd92 584 #define MODE_HYP 0x1A
Kojto 100:cbbeb26dbd92 585 #define MODE_UND 0x1B
Kojto 100:cbbeb26dbd92 586 #define MODE_SYS 0x1F
Kojto 100:cbbeb26dbd92 587
Kojto 100:cbbeb26dbd92 588
Kojto 100:cbbeb26dbd92 589 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
Kojto 100:cbbeb26dbd92 590 {
Kojto 100:cbbeb26dbd92 591 __ASM volatile ("cpsie i");
Kojto 100:cbbeb26dbd92 592 }
Kojto 100:cbbeb26dbd92 593
Kojto 100:cbbeb26dbd92 594 /** \brief Disable IRQ Interrupts
Kojto 100:cbbeb26dbd92 595
Kojto 100:cbbeb26dbd92 596 This function disables IRQ interrupts by setting the I-bit in the CPSR.
Kojto 100:cbbeb26dbd92 597 Can only be executed in Privileged modes.
Kojto 100:cbbeb26dbd92 598 */
Kojto 100:cbbeb26dbd92 599 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __disable_irq(void)
Kojto 100:cbbeb26dbd92 600 {
Kojto 100:cbbeb26dbd92 601 uint32_t result;
Kojto 100:cbbeb26dbd92 602
Kojto 100:cbbeb26dbd92 603 __ASM volatile ("mrs %0, cpsr" : "=r" (result));
Kojto 100:cbbeb26dbd92 604 __ASM volatile ("cpsid i");
Kojto 100:cbbeb26dbd92 605 return(result & 0x80);
Kojto 100:cbbeb26dbd92 606 }
Kojto 100:cbbeb26dbd92 607
Kojto 100:cbbeb26dbd92 608
Kojto 100:cbbeb26dbd92 609 /** \brief Get APSR Register
Kojto 100:cbbeb26dbd92 610
Kojto 100:cbbeb26dbd92 611 This function returns the content of the APSR Register.
Kojto 100:cbbeb26dbd92 612
Kojto 100:cbbeb26dbd92 613 \return APSR Register value
Kojto 100:cbbeb26dbd92 614 */
Kojto 100:cbbeb26dbd92 615 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
Kojto 100:cbbeb26dbd92 616 {
Kojto 100:cbbeb26dbd92 617 #if 1
Kojto 108:34e6b704fe68 618 register uint32_t __regAPSR;
Kojto 108:34e6b704fe68 619 __ASM volatile ("mrs %0, apsr" : "=r" (__regAPSR) );
Kojto 100:cbbeb26dbd92 620 #else
Kojto 100:cbbeb26dbd92 621 register uint32_t __regAPSR __ASM("apsr");
Kojto 108:34e6b704fe68 622 #endif
Kojto 100:cbbeb26dbd92 623 return(__regAPSR);
Kojto 100:cbbeb26dbd92 624 }
Kojto 100:cbbeb26dbd92 625
Kojto 100:cbbeb26dbd92 626
Kojto 100:cbbeb26dbd92 627 /** \brief Get CPSR Register
Kojto 100:cbbeb26dbd92 628
Kojto 100:cbbeb26dbd92 629 This function returns the content of the CPSR Register.
Kojto 100:cbbeb26dbd92 630
Kojto 100:cbbeb26dbd92 631 \return CPSR Register value
Kojto 100:cbbeb26dbd92 632 */
Kojto 100:cbbeb26dbd92 633 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CPSR(void)
Kojto 100:cbbeb26dbd92 634 {
Kojto 100:cbbeb26dbd92 635 #if 1
Kojto 100:cbbeb26dbd92 636 register uint32_t __regCPSR;
Kojto 100:cbbeb26dbd92 637 __ASM volatile ("mrs %0, cpsr" : "=r" (__regCPSR));
Kojto 100:cbbeb26dbd92 638 #else
Kojto 100:cbbeb26dbd92 639 register uint32_t __regCPSR __ASM("cpsr");
Kojto 100:cbbeb26dbd92 640 #endif
Kojto 100:cbbeb26dbd92 641 return(__regCPSR);
Kojto 100:cbbeb26dbd92 642 }
Kojto 100:cbbeb26dbd92 643
Kojto 100:cbbeb26dbd92 644 #if 0
Kojto 100:cbbeb26dbd92 645 /** \brief Set Stack Pointer
Kojto 100:cbbeb26dbd92 646
Kojto 100:cbbeb26dbd92 647 This function assigns the given value to the current stack pointer.
Kojto 100:cbbeb26dbd92 648
Kojto 100:cbbeb26dbd92 649 \param [in] topOfStack Stack Pointer value to set
Kojto 100:cbbeb26dbd92 650 */
Kojto 100:cbbeb26dbd92 651 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_SP(uint32_t topOfStack)
Kojto 100:cbbeb26dbd92 652 {
Kojto 100:cbbeb26dbd92 653 register uint32_t __regSP __ASM("sp");
Kojto 100:cbbeb26dbd92 654 __regSP = topOfStack;
Kojto 100:cbbeb26dbd92 655 }
Kojto 100:cbbeb26dbd92 656 #endif
Kojto 100:cbbeb26dbd92 657
Kojto 100:cbbeb26dbd92 658 /** \brief Get link register
Kojto 100:cbbeb26dbd92 659
Kojto 100:cbbeb26dbd92 660 This function returns the value of the link register
Kojto 100:cbbeb26dbd92 661
Kojto 100:cbbeb26dbd92 662 \return Value of link register
Kojto 100:cbbeb26dbd92 663 */
Kojto 100:cbbeb26dbd92 664 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_LR(void)
Kojto 100:cbbeb26dbd92 665 {
Kojto 100:cbbeb26dbd92 666 register uint32_t __reglr __ASM("lr");
Kojto 100:cbbeb26dbd92 667 return(__reglr);
Kojto 100:cbbeb26dbd92 668 }
Kojto 100:cbbeb26dbd92 669
Kojto 100:cbbeb26dbd92 670 #if 0
Kojto 100:cbbeb26dbd92 671 /** \brief Set link register
Kojto 100:cbbeb26dbd92 672
Kojto 100:cbbeb26dbd92 673 This function sets the value of the link register
Kojto 100:cbbeb26dbd92 674
Kojto 100:cbbeb26dbd92 675 \param [in] lr LR value to set
Kojto 100:cbbeb26dbd92 676 */
Kojto 100:cbbeb26dbd92 677 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_LR(uint32_t lr)
Kojto 100:cbbeb26dbd92 678 {
Kojto 100:cbbeb26dbd92 679 register uint32_t __reglr __ASM("lr");
Kojto 100:cbbeb26dbd92 680 __reglr = lr;
Kojto 100:cbbeb26dbd92 681 }
Kojto 100:cbbeb26dbd92 682 #endif
Kojto 100:cbbeb26dbd92 683
Kojto 100:cbbeb26dbd92 684 /** \brief Set Process Stack Pointer
Kojto 100:cbbeb26dbd92 685
Kojto 100:cbbeb26dbd92 686 This function assigns the given value to the USR/SYS Stack Pointer (PSP).
Kojto 100:cbbeb26dbd92 687
Kojto 100:cbbeb26dbd92 688 \param [in] topOfProcStack USR/SYS Stack Pointer value to set
Kojto 100:cbbeb26dbd92 689 */
Kojto 108:34e6b704fe68 690 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
Kojto 108:34e6b704fe68 691 {
Kojto 108:34e6b704fe68 692 __asm__ volatile (
Kojto 108:34e6b704fe68 693 ".ARM;"
Kojto 108:34e6b704fe68 694 ".eabi_attribute Tag_ABI_align8_preserved,1;"
Kojto 108:34e6b704fe68 695
Kojto 108:34e6b704fe68 696 "BIC R0, R0, #7;" /* ;ensure stack is 8-byte aligned */
Kojto 108:34e6b704fe68 697 "MRS R1, CPSR;"
Kojto 108:34e6b704fe68 698 "CPS %0;" /* ;no effect in USR mode */
Kojto 108:34e6b704fe68 699 "MOV SP, R0;"
Kojto 108:34e6b704fe68 700 "MSR CPSR_c, R1;" /* ;no effect in USR mode */
Kojto 108:34e6b704fe68 701 "ISB;"
Kojto 108:34e6b704fe68 702 //"BX LR;"
Kojto 108:34e6b704fe68 703 :
Kojto 108:34e6b704fe68 704 : "i"(MODE_SYS)
Kojto 108:34e6b704fe68 705 : "r0", "r1");
Kojto 108:34e6b704fe68 706 return;
Kojto 108:34e6b704fe68 707 }
Kojto 100:cbbeb26dbd92 708
Kojto 100:cbbeb26dbd92 709 /** \brief Set User Mode
Kojto 100:cbbeb26dbd92 710
Kojto 100:cbbeb26dbd92 711 This function changes the processor state to User Mode
Kojto 108:34e6b704fe68 712 */
Kojto 108:34e6b704fe68 713 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CPS_USR(void)
Kojto 108:34e6b704fe68 714 {
Kojto 108:34e6b704fe68 715 __asm__ volatile (
Kojto 108:34e6b704fe68 716 ".ARM;"
Kojto 100:cbbeb26dbd92 717
Kojto 108:34e6b704fe68 718 "CPS %0;"
Kojto 108:34e6b704fe68 719 //"BX LR;"
Kojto 108:34e6b704fe68 720 :
Kojto 108:34e6b704fe68 721 : "i"(MODE_USR)
Kojto 108:34e6b704fe68 722 : );
Kojto 108:34e6b704fe68 723 return;
Kojto 108:34e6b704fe68 724 }
Kojto 108:34e6b704fe68 725
Kojto 100:cbbeb26dbd92 726
Kojto 100:cbbeb26dbd92 727 /** \brief Enable FIQ
Kojto 100:cbbeb26dbd92 728
Kojto 100:cbbeb26dbd92 729 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
Kojto 100:cbbeb26dbd92 730 Can only be executed in Privileged modes.
Kojto 100:cbbeb26dbd92 731 */
Kojto 108:34e6b704fe68 732 #define __enable_fault_irq() __asm__ volatile ("cpsie f")
Kojto 100:cbbeb26dbd92 733
Kojto 100:cbbeb26dbd92 734
Kojto 100:cbbeb26dbd92 735 /** \brief Disable FIQ
Kojto 100:cbbeb26dbd92 736
Kojto 100:cbbeb26dbd92 737 This function disables FIQ interrupts by setting the F-bit in the CPSR.
Kojto 100:cbbeb26dbd92 738 Can only be executed in Privileged modes.
Kojto 100:cbbeb26dbd92 739 */
Kojto 108:34e6b704fe68 740 #define __disable_fault_irq() __asm__ volatile ("cpsid f")
Kojto 100:cbbeb26dbd92 741
Kojto 100:cbbeb26dbd92 742
Kojto 100:cbbeb26dbd92 743 /** \brief Get FPSCR
Kojto 100:cbbeb26dbd92 744
Kojto 100:cbbeb26dbd92 745 This function returns the current value of the Floating Point Status/Control register.
Kojto 100:cbbeb26dbd92 746
Kojto 100:cbbeb26dbd92 747 \return Floating Point Status/Control register value
Kojto 100:cbbeb26dbd92 748 */
Kojto 100:cbbeb26dbd92 749 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
Kojto 100:cbbeb26dbd92 750 {
Kojto 100:cbbeb26dbd92 751 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
Kojto 100:cbbeb26dbd92 752 #if 1
Kojto 100:cbbeb26dbd92 753 uint32_t result;
Kojto 100:cbbeb26dbd92 754
Kojto 100:cbbeb26dbd92 755 __ASM volatile ("vmrs %0, fpscr" : "=r" (result) );
Kojto 100:cbbeb26dbd92 756 return (result);
Kojto 100:cbbeb26dbd92 757 #else
Kojto 100:cbbeb26dbd92 758 register uint32_t __regfpscr __ASM("fpscr");
Kojto 100:cbbeb26dbd92 759 return(__regfpscr);
Kojto 100:cbbeb26dbd92 760 #endif
Kojto 100:cbbeb26dbd92 761 #else
Kojto 100:cbbeb26dbd92 762 return(0);
Kojto 100:cbbeb26dbd92 763 #endif
Kojto 100:cbbeb26dbd92 764 }
Kojto 100:cbbeb26dbd92 765
Kojto 100:cbbeb26dbd92 766
Kojto 100:cbbeb26dbd92 767 /** \brief Set FPSCR
Kojto 100:cbbeb26dbd92 768
Kojto 100:cbbeb26dbd92 769 This function assigns the given value to the Floating Point Status/Control register.
Kojto 100:cbbeb26dbd92 770
Kojto 100:cbbeb26dbd92 771 \param [in] fpscr Floating Point Status/Control value to set
Kojto 100:cbbeb26dbd92 772 */
Kojto 100:cbbeb26dbd92 773 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
Kojto 100:cbbeb26dbd92 774 {
Kojto 100:cbbeb26dbd92 775 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
Kojto 100:cbbeb26dbd92 776 #if 1
Kojto 100:cbbeb26dbd92 777 __ASM volatile ("vmsr fpscr, %0" : : "r" (fpscr) );
Kojto 100:cbbeb26dbd92 778 #else
Kojto 100:cbbeb26dbd92 779 register uint32_t __regfpscr __ASM("fpscr");
Kojto 100:cbbeb26dbd92 780 __regfpscr = (fpscr);
Kojto 100:cbbeb26dbd92 781 #endif
Kojto 100:cbbeb26dbd92 782 #endif
Kojto 100:cbbeb26dbd92 783 }
Kojto 100:cbbeb26dbd92 784
Kojto 100:cbbeb26dbd92 785 /** \brief Get FPEXC
Kojto 100:cbbeb26dbd92 786
Kojto 100:cbbeb26dbd92 787 This function returns the current value of the Floating Point Exception Control register.
Kojto 100:cbbeb26dbd92 788
Kojto 100:cbbeb26dbd92 789 \return Floating Point Exception Control register value
Kojto 100:cbbeb26dbd92 790 */
Kojto 100:cbbeb26dbd92 791 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPEXC(void)
Kojto 100:cbbeb26dbd92 792 {
Kojto 100:cbbeb26dbd92 793 #if (__FPU_PRESENT == 1)
Kojto 100:cbbeb26dbd92 794 #if 1
Kojto 100:cbbeb26dbd92 795 uint32_t result;
Kojto 100:cbbeb26dbd92 796
Kojto 100:cbbeb26dbd92 797 __ASM volatile ("vmrs %0, fpexc" : "=r" (result));
Kojto 100:cbbeb26dbd92 798 return (result);
Kojto 100:cbbeb26dbd92 799 #else
Kojto 100:cbbeb26dbd92 800 register uint32_t __regfpexc __ASM("fpexc");
Kojto 100:cbbeb26dbd92 801 return(__regfpexc);
Kojto 100:cbbeb26dbd92 802 #endif
Kojto 100:cbbeb26dbd92 803 #else
Kojto 100:cbbeb26dbd92 804 return(0);
Kojto 100:cbbeb26dbd92 805 #endif
Kojto 100:cbbeb26dbd92 806 }
Kojto 100:cbbeb26dbd92 807
Kojto 100:cbbeb26dbd92 808
Kojto 100:cbbeb26dbd92 809 /** \brief Set FPEXC
Kojto 100:cbbeb26dbd92 810
Kojto 100:cbbeb26dbd92 811 This function assigns the given value to the Floating Point Exception Control register.
Kojto 100:cbbeb26dbd92 812
Kojto 100:cbbeb26dbd92 813 \param [in] fpscr Floating Point Exception Control value to set
Kojto 100:cbbeb26dbd92 814 */
Kojto 100:cbbeb26dbd92 815 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPEXC(uint32_t fpexc)
Kojto 100:cbbeb26dbd92 816 {
Kojto 100:cbbeb26dbd92 817 #if (__FPU_PRESENT == 1)
Kojto 100:cbbeb26dbd92 818 #if 1
Kojto 100:cbbeb26dbd92 819 __ASM volatile ("vmsr fpexc, %0" : : "r" (fpexc));
Kojto 100:cbbeb26dbd92 820 #else
Kojto 100:cbbeb26dbd92 821 register uint32_t __regfpexc __ASM("fpexc");
Kojto 100:cbbeb26dbd92 822 __regfpexc = (fpexc);
Kojto 100:cbbeb26dbd92 823 #endif
Kojto 100:cbbeb26dbd92 824 #endif
Kojto 100:cbbeb26dbd92 825 }
Kojto 100:cbbeb26dbd92 826
Kojto 100:cbbeb26dbd92 827 /** \brief Get CPACR
Kojto 100:cbbeb26dbd92 828
Kojto 100:cbbeb26dbd92 829 This function returns the current value of the Coprocessor Access Control register.
Kojto 100:cbbeb26dbd92 830
Kojto 100:cbbeb26dbd92 831 \return Coprocessor Access Control register value
Kojto 100:cbbeb26dbd92 832 */
Kojto 100:cbbeb26dbd92 833 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CPACR(void)
Kojto 100:cbbeb26dbd92 834 {
Kojto 100:cbbeb26dbd92 835 #if 1
Kojto 100:cbbeb26dbd92 836 register uint32_t __regCPACR;
Kojto 100:cbbeb26dbd92 837 __ASM volatile ("mrc p15, 0, %0, c1, c0, 2" : "=r" (__regCPACR));
Kojto 100:cbbeb26dbd92 838 #else
Kojto 100:cbbeb26dbd92 839 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
Kojto 100:cbbeb26dbd92 840 #endif
Kojto 100:cbbeb26dbd92 841 return __regCPACR;
Kojto 100:cbbeb26dbd92 842 }
Kojto 100:cbbeb26dbd92 843
Kojto 100:cbbeb26dbd92 844 /** \brief Set CPACR
Kojto 100:cbbeb26dbd92 845
Kojto 100:cbbeb26dbd92 846 This function assigns the given value to the Coprocessor Access Control register.
Kojto 100:cbbeb26dbd92 847
Kojto 108:34e6b704fe68 848 \param [in] cpacr Coprocessor Acccess Control value to set
Kojto 100:cbbeb26dbd92 849 */
Kojto 100:cbbeb26dbd92 850 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CPACR(uint32_t cpacr)
Kojto 100:cbbeb26dbd92 851 {
Kojto 100:cbbeb26dbd92 852 #if 1
Kojto 100:cbbeb26dbd92 853 __ASM volatile ("mcr p15, 0, %0, c1, c0, 2" : : "r" (cpacr));
Kojto 100:cbbeb26dbd92 854 #else
Kojto 100:cbbeb26dbd92 855 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
Kojto 100:cbbeb26dbd92 856 __regCPACR = cpacr;
Kojto 100:cbbeb26dbd92 857 #endif
Kojto 100:cbbeb26dbd92 858 __ISB();
Kojto 100:cbbeb26dbd92 859 }
Kojto 100:cbbeb26dbd92 860
Kojto 100:cbbeb26dbd92 861 /** \brief Get CBAR
Kojto 100:cbbeb26dbd92 862
Kojto 100:cbbeb26dbd92 863 This function returns the value of the Configuration Base Address register.
Kojto 100:cbbeb26dbd92 864
Kojto 100:cbbeb26dbd92 865 \return Configuration Base Address register value
Kojto 100:cbbeb26dbd92 866 */
Kojto 100:cbbeb26dbd92 867 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CBAR() {
Kojto 100:cbbeb26dbd92 868 #if 1
Kojto 100:cbbeb26dbd92 869 register uint32_t __regCBAR;
Kojto 100:cbbeb26dbd92 870 __ASM volatile ("mrc p15, 4, %0, c15, c0, 0" : "=r" (__regCBAR));
Kojto 100:cbbeb26dbd92 871 #else
Kojto 100:cbbeb26dbd92 872 register uint32_t __regCBAR __ASM("cp15:4:c15:c0:0");
Kojto 100:cbbeb26dbd92 873 #endif
Kojto 100:cbbeb26dbd92 874 return(__regCBAR);
Kojto 100:cbbeb26dbd92 875 }
Kojto 100:cbbeb26dbd92 876
Kojto 100:cbbeb26dbd92 877 /** \brief Get TTBR0
Kojto 100:cbbeb26dbd92 878
Kojto 108:34e6b704fe68 879 This function returns the value of the Translation Table Base Register 0.
Kojto 100:cbbeb26dbd92 880
Kojto 100:cbbeb26dbd92 881 \return Translation Table Base Register 0 value
Kojto 100:cbbeb26dbd92 882 */
Kojto 100:cbbeb26dbd92 883 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_TTBR0() {
Kojto 100:cbbeb26dbd92 884 #if 1
Kojto 100:cbbeb26dbd92 885 register uint32_t __regTTBR0;
Kojto 100:cbbeb26dbd92 886 __ASM volatile ("mrc p15, 0, %0, c2, c0, 0" : "=r" (__regTTBR0));
Kojto 100:cbbeb26dbd92 887 #else
Kojto 100:cbbeb26dbd92 888 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
Kojto 100:cbbeb26dbd92 889 #endif
Kojto 100:cbbeb26dbd92 890 return(__regTTBR0);
Kojto 100:cbbeb26dbd92 891 }
Kojto 100:cbbeb26dbd92 892
Kojto 100:cbbeb26dbd92 893 /** \brief Set TTBR0
Kojto 100:cbbeb26dbd92 894
Kojto 108:34e6b704fe68 895 This function assigns the given value to the Translation Table Base Register 0.
Kojto 100:cbbeb26dbd92 896
Kojto 100:cbbeb26dbd92 897 \param [in] ttbr0 Translation Table Base Register 0 value to set
Kojto 100:cbbeb26dbd92 898 */
Kojto 100:cbbeb26dbd92 899 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) {
Kojto 100:cbbeb26dbd92 900 #if 1
Kojto 100:cbbeb26dbd92 901 __ASM volatile ("mcr p15, 0, %0, c2, c0, 0" : : "r" (ttbr0));
Kojto 100:cbbeb26dbd92 902 #else
Kojto 100:cbbeb26dbd92 903 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
Kojto 100:cbbeb26dbd92 904 __regTTBR0 = ttbr0;
Kojto 100:cbbeb26dbd92 905 #endif
Kojto 100:cbbeb26dbd92 906 __ISB();
Kojto 100:cbbeb26dbd92 907 }
Kojto 100:cbbeb26dbd92 908
Kojto 100:cbbeb26dbd92 909 /** \brief Get DACR
Kojto 100:cbbeb26dbd92 910
Kojto 100:cbbeb26dbd92 911 This function returns the value of the Domain Access Control Register.
Kojto 100:cbbeb26dbd92 912
Kojto 100:cbbeb26dbd92 913 \return Domain Access Control Register value
Kojto 100:cbbeb26dbd92 914 */
Kojto 100:cbbeb26dbd92 915 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_DACR() {
Kojto 100:cbbeb26dbd92 916 #if 1
Kojto 100:cbbeb26dbd92 917 register uint32_t __regDACR;
Kojto 100:cbbeb26dbd92 918 __ASM volatile ("mrc p15, 0, %0, c3, c0, 0" : "=r" (__regDACR));
Kojto 100:cbbeb26dbd92 919 #else
Kojto 100:cbbeb26dbd92 920 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
Kojto 100:cbbeb26dbd92 921 #endif
Kojto 100:cbbeb26dbd92 922 return(__regDACR);
Kojto 100:cbbeb26dbd92 923 }
Kojto 100:cbbeb26dbd92 924
Kojto 100:cbbeb26dbd92 925 /** \brief Set DACR
Kojto 100:cbbeb26dbd92 926
Kojto 108:34e6b704fe68 927 This function assigns the given value to the Domain Access Control Register.
Kojto 100:cbbeb26dbd92 928
Kojto 100:cbbeb26dbd92 929 \param [in] dacr Domain Access Control Register value to set
Kojto 100:cbbeb26dbd92 930 */
Kojto 100:cbbeb26dbd92 931 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_DACR(uint32_t dacr) {
Kojto 100:cbbeb26dbd92 932 #if 1
Kojto 100:cbbeb26dbd92 933 __ASM volatile ("mcr p15, 0, %0, c3, c0, 0" : : "r" (dacr));
Kojto 100:cbbeb26dbd92 934 #else
Kojto 100:cbbeb26dbd92 935 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
Kojto 100:cbbeb26dbd92 936 __regDACR = dacr;
Kojto 100:cbbeb26dbd92 937 #endif
Kojto 100:cbbeb26dbd92 938 __ISB();
Kojto 100:cbbeb26dbd92 939 }
Kojto 100:cbbeb26dbd92 940
Kojto 100:cbbeb26dbd92 941 /******************************** Cache and BTAC enable ****************************************************/
Kojto 100:cbbeb26dbd92 942
Kojto 100:cbbeb26dbd92 943 /** \brief Set SCTLR
Kojto 100:cbbeb26dbd92 944
Kojto 100:cbbeb26dbd92 945 This function assigns the given value to the System Control Register.
Kojto 100:cbbeb26dbd92 946
Kojto 108:34e6b704fe68 947 \param [in] sctlr System Control Register value to set
Kojto 100:cbbeb26dbd92 948 */
Kojto 100:cbbeb26dbd92 949 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_SCTLR(uint32_t sctlr)
Kojto 100:cbbeb26dbd92 950 {
Kojto 100:cbbeb26dbd92 951 #if 1
Kojto 100:cbbeb26dbd92 952 __ASM volatile ("mcr p15, 0, %0, c1, c0, 0" : : "r" (sctlr));
Kojto 100:cbbeb26dbd92 953 #else
Kojto 100:cbbeb26dbd92 954 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
Kojto 100:cbbeb26dbd92 955 __regSCTLR = sctlr;
Kojto 100:cbbeb26dbd92 956 #endif
Kojto 100:cbbeb26dbd92 957 }
Kojto 100:cbbeb26dbd92 958
Kojto 100:cbbeb26dbd92 959 /** \brief Get SCTLR
Kojto 100:cbbeb26dbd92 960
Kojto 100:cbbeb26dbd92 961 This function returns the value of the System Control Register.
Kojto 100:cbbeb26dbd92 962
Kojto 100:cbbeb26dbd92 963 \return System Control Register value
Kojto 100:cbbeb26dbd92 964 */
Kojto 100:cbbeb26dbd92 965 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_SCTLR() {
Kojto 100:cbbeb26dbd92 966 #if 1
Kojto 100:cbbeb26dbd92 967 register uint32_t __regSCTLR;
Kojto 100:cbbeb26dbd92 968 __ASM volatile ("mrc p15, 0, %0, c1, c0, 0" : "=r" (__regSCTLR));
Kojto 100:cbbeb26dbd92 969 #else
Kojto 100:cbbeb26dbd92 970 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
Kojto 100:cbbeb26dbd92 971 #endif
Kojto 100:cbbeb26dbd92 972 return(__regSCTLR);
Kojto 100:cbbeb26dbd92 973 }
Kojto 100:cbbeb26dbd92 974
Kojto 100:cbbeb26dbd92 975 /** \brief Enable Caches
Kojto 100:cbbeb26dbd92 976
Kojto 100:cbbeb26dbd92 977 Enable Caches
Kojto 100:cbbeb26dbd92 978 */
Kojto 100:cbbeb26dbd92 979 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_caches(void) {
Kojto 100:cbbeb26dbd92 980 // Set I bit 12 to enable I Cache
Kojto 100:cbbeb26dbd92 981 // Set C bit 2 to enable D Cache
Kojto 100:cbbeb26dbd92 982 __set_SCTLR( __get_SCTLR() | (1 << 12) | (1 << 2));
Kojto 100:cbbeb26dbd92 983 }
Kojto 100:cbbeb26dbd92 984
Kojto 100:cbbeb26dbd92 985 /** \brief Disable Caches
Kojto 100:cbbeb26dbd92 986
Kojto 100:cbbeb26dbd92 987 Disable Caches
Kojto 100:cbbeb26dbd92 988 */
Kojto 100:cbbeb26dbd92 989 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_caches(void) {
Kojto 100:cbbeb26dbd92 990 // Clear I bit 12 to disable I Cache
Kojto 100:cbbeb26dbd92 991 // Clear C bit 2 to disable D Cache
Kojto 100:cbbeb26dbd92 992 __set_SCTLR( __get_SCTLR() & ~(1 << 12) & ~(1 << 2));
Kojto 100:cbbeb26dbd92 993 __ISB();
Kojto 100:cbbeb26dbd92 994 }
Kojto 100:cbbeb26dbd92 995
Kojto 100:cbbeb26dbd92 996 /** \brief Enable BTAC
Kojto 100:cbbeb26dbd92 997
Kojto 100:cbbeb26dbd92 998 Enable BTAC
Kojto 100:cbbeb26dbd92 999 */
Kojto 100:cbbeb26dbd92 1000 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_btac(void) {
Kojto 100:cbbeb26dbd92 1001 // Set Z bit 11 to enable branch prediction
Kojto 100:cbbeb26dbd92 1002 __set_SCTLR( __get_SCTLR() | (1 << 11));
Kojto 100:cbbeb26dbd92 1003 __ISB();
Kojto 100:cbbeb26dbd92 1004 }
Kojto 100:cbbeb26dbd92 1005
Kojto 100:cbbeb26dbd92 1006 /** \brief Disable BTAC
Kojto 100:cbbeb26dbd92 1007
Kojto 100:cbbeb26dbd92 1008 Disable BTAC
Kojto 100:cbbeb26dbd92 1009 */
Kojto 100:cbbeb26dbd92 1010 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_btac(void) {
Kojto 100:cbbeb26dbd92 1011 // Clear Z bit 11 to disable branch prediction
Kojto 100:cbbeb26dbd92 1012 __set_SCTLR( __get_SCTLR() & ~(1 << 11));
Kojto 100:cbbeb26dbd92 1013 }
Kojto 100:cbbeb26dbd92 1014
Kojto 100:cbbeb26dbd92 1015
Kojto 100:cbbeb26dbd92 1016 /** \brief Enable MMU
Kojto 100:cbbeb26dbd92 1017
Kojto 100:cbbeb26dbd92 1018 Enable MMU
Kojto 100:cbbeb26dbd92 1019 */
Kojto 100:cbbeb26dbd92 1020 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_mmu(void) {
Kojto 100:cbbeb26dbd92 1021 // Set M bit 0 to enable the MMU
Kojto 100:cbbeb26dbd92 1022 // Set AFE bit to enable simplified access permissions model
Kojto 100:cbbeb26dbd92 1023 // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking
Kojto 100:cbbeb26dbd92 1024 __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29));
Kojto 100:cbbeb26dbd92 1025 __ISB();
Kojto 100:cbbeb26dbd92 1026 }
Kojto 100:cbbeb26dbd92 1027
Kojto 108:34e6b704fe68 1028 /** \brief Disable MMU
Kojto 100:cbbeb26dbd92 1029
Kojto 108:34e6b704fe68 1030 Disable MMU
Kojto 100:cbbeb26dbd92 1031 */
Kojto 100:cbbeb26dbd92 1032 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_mmu(void) {
Kojto 100:cbbeb26dbd92 1033 // Clear M bit 0 to disable the MMU
Kojto 100:cbbeb26dbd92 1034 __set_SCTLR( __get_SCTLR() & ~1);
Kojto 100:cbbeb26dbd92 1035 __ISB();
Kojto 100:cbbeb26dbd92 1036 }
Kojto 100:cbbeb26dbd92 1037
Kojto 100:cbbeb26dbd92 1038 /******************************** TLB maintenance operations ************************************************/
Kojto 100:cbbeb26dbd92 1039 /** \brief Invalidate the whole tlb
Kojto 100:cbbeb26dbd92 1040
Kojto 100:cbbeb26dbd92 1041 TLBIALL. Invalidate the whole tlb
Kojto 100:cbbeb26dbd92 1042 */
Kojto 100:cbbeb26dbd92 1043
Kojto 100:cbbeb26dbd92 1044 __attribute__( ( always_inline ) ) __STATIC_INLINE void __ca9u_inv_tlb_all(void) {
Kojto 100:cbbeb26dbd92 1045 #if 1
Kojto 100:cbbeb26dbd92 1046 __ASM volatile ("mcr p15, 0, %0, c8, c7, 0" : : "r" (0));
Kojto 100:cbbeb26dbd92 1047 #else
Kojto 100:cbbeb26dbd92 1048 register uint32_t __TLBIALL __ASM("cp15:0:c8:c7:0");
Kojto 100:cbbeb26dbd92 1049 __TLBIALL = 0;
Kojto 100:cbbeb26dbd92 1050 #endif
Kojto 100:cbbeb26dbd92 1051 __DSB();
Kojto 100:cbbeb26dbd92 1052 __ISB();
Kojto 100:cbbeb26dbd92 1053 }
Kojto 100:cbbeb26dbd92 1054
Kojto 100:cbbeb26dbd92 1055 /******************************** BTB maintenance operations ************************************************/
Kojto 100:cbbeb26dbd92 1056 /** \brief Invalidate entire branch predictor array
Kojto 100:cbbeb26dbd92 1057
Kojto 100:cbbeb26dbd92 1058 BPIALL. Branch Predictor Invalidate All.
Kojto 100:cbbeb26dbd92 1059 */
Kojto 100:cbbeb26dbd92 1060
Kojto 100:cbbeb26dbd92 1061 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_btac(void) {
Kojto 100:cbbeb26dbd92 1062 #if 1
Kojto 100:cbbeb26dbd92 1063 __ASM volatile ("mcr p15, 0, %0, c7, c5, 6" : : "r" (0));
Kojto 100:cbbeb26dbd92 1064 #else
Kojto 100:cbbeb26dbd92 1065 register uint32_t __BPIALL __ASM("cp15:0:c7:c5:6");
Kojto 100:cbbeb26dbd92 1066 __BPIALL = 0;
Kojto 100:cbbeb26dbd92 1067 #endif
Kojto 100:cbbeb26dbd92 1068 __DSB(); //ensure completion of the invalidation
Kojto 100:cbbeb26dbd92 1069 __ISB(); //ensure instruction fetch path sees new state
Kojto 100:cbbeb26dbd92 1070 }
Kojto 100:cbbeb26dbd92 1071
Kojto 100:cbbeb26dbd92 1072
Kojto 100:cbbeb26dbd92 1073 /******************************** L1 cache operations ******************************************************/
Kojto 100:cbbeb26dbd92 1074
Kojto 100:cbbeb26dbd92 1075 /** \brief Invalidate the whole I$
Kojto 100:cbbeb26dbd92 1076
Kojto 100:cbbeb26dbd92 1077 ICIALLU. Instruction Cache Invalidate All to PoU
Kojto 100:cbbeb26dbd92 1078 */
Kojto 100:cbbeb26dbd92 1079 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_icache_all(void) {
Kojto 100:cbbeb26dbd92 1080 #if 1
Kojto 100:cbbeb26dbd92 1081 __ASM volatile ("mcr p15, 0, %0, c7, c5, 0" : : "r" (0));
Kojto 100:cbbeb26dbd92 1082 #else
Kojto 100:cbbeb26dbd92 1083 register uint32_t __ICIALLU __ASM("cp15:0:c7:c5:0");
Kojto 100:cbbeb26dbd92 1084 __ICIALLU = 0;
Kojto 100:cbbeb26dbd92 1085 #endif
Kojto 100:cbbeb26dbd92 1086 __DSB(); //ensure completion of the invalidation
Kojto 100:cbbeb26dbd92 1087 __ISB(); //ensure instruction fetch path sees new I cache state
Kojto 100:cbbeb26dbd92 1088 }
Kojto 100:cbbeb26dbd92 1089
Kojto 100:cbbeb26dbd92 1090 /** \brief Clean D$ by MVA
Kojto 100:cbbeb26dbd92 1091
Kojto 100:cbbeb26dbd92 1092 DCCMVAC. Data cache clean by MVA to PoC
Kojto 100:cbbeb26dbd92 1093 */
Kojto 100:cbbeb26dbd92 1094 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_dcache_mva(void *va) {
Kojto 100:cbbeb26dbd92 1095 #if 1
Kojto 100:cbbeb26dbd92 1096 __ASM volatile ("mcr p15, 0, %0, c7, c10, 1" : : "r" ((uint32_t)va));
Kojto 100:cbbeb26dbd92 1097 #else
Kojto 100:cbbeb26dbd92 1098 register uint32_t __DCCMVAC __ASM("cp15:0:c7:c10:1");
Kojto 100:cbbeb26dbd92 1099 __DCCMVAC = (uint32_t)va;
Kojto 100:cbbeb26dbd92 1100 #endif
Kojto 100:cbbeb26dbd92 1101 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
Kojto 100:cbbeb26dbd92 1102 }
Kojto 100:cbbeb26dbd92 1103
Kojto 100:cbbeb26dbd92 1104 /** \brief Invalidate D$ by MVA
Kojto 100:cbbeb26dbd92 1105
Kojto 100:cbbeb26dbd92 1106 DCIMVAC. Data cache invalidate by MVA to PoC
Kojto 100:cbbeb26dbd92 1107 */
Kojto 100:cbbeb26dbd92 1108 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_dcache_mva(void *va) {
Kojto 100:cbbeb26dbd92 1109 #if 1
Kojto 100:cbbeb26dbd92 1110 __ASM volatile ("mcr p15, 0, %0, c7, c6, 1" : : "r" ((uint32_t)va));
Kojto 100:cbbeb26dbd92 1111 #else
Kojto 100:cbbeb26dbd92 1112 register uint32_t __DCIMVAC __ASM("cp15:0:c7:c6:1");
Kojto 100:cbbeb26dbd92 1113 __DCIMVAC = (uint32_t)va;
Kojto 100:cbbeb26dbd92 1114 #endif
Kojto 100:cbbeb26dbd92 1115 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
Kojto 100:cbbeb26dbd92 1116 }
Kojto 100:cbbeb26dbd92 1117
Kojto 100:cbbeb26dbd92 1118 /** \brief Clean and Invalidate D$ by MVA
Kojto 100:cbbeb26dbd92 1119
Kojto 100:cbbeb26dbd92 1120 DCCIMVAC. Data cache clean and invalidate by MVA to PoC
Kojto 100:cbbeb26dbd92 1121 */
Kojto 100:cbbeb26dbd92 1122 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_inv_dcache_mva(void *va) {
Kojto 100:cbbeb26dbd92 1123 #if 1
Kojto 100:cbbeb26dbd92 1124 __ASM volatile ("mcr p15, 0, %0, c7, c14, 1" : : "r" ((uint32_t)va));
Kojto 100:cbbeb26dbd92 1125 #else
Kojto 100:cbbeb26dbd92 1126 register uint32_t __DCCIMVAC __ASM("cp15:0:c7:c14:1");
Kojto 100:cbbeb26dbd92 1127 __DCCIMVAC = (uint32_t)va;
Kojto 100:cbbeb26dbd92 1128 #endif
Kojto 100:cbbeb26dbd92 1129 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
Kojto 100:cbbeb26dbd92 1130 }
Kojto 100:cbbeb26dbd92 1131
Kojto 108:34e6b704fe68 1132 /** \brief Clean and Invalidate the entire data or unified cache
Kojto 100:cbbeb26dbd92 1133
Kojto 108:34e6b704fe68 1134 Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency.
Kojto 100:cbbeb26dbd92 1135 */
Kojto 100:cbbeb26dbd92 1136 extern void __v7_all_cache(uint32_t op);
Kojto 100:cbbeb26dbd92 1137
Kojto 100:cbbeb26dbd92 1138
Kojto 100:cbbeb26dbd92 1139 /** \brief Invalidate the whole D$
Kojto 100:cbbeb26dbd92 1140
Kojto 100:cbbeb26dbd92 1141 DCISW. Invalidate by Set/Way
Kojto 100:cbbeb26dbd92 1142 */
Kojto 100:cbbeb26dbd92 1143
Kojto 100:cbbeb26dbd92 1144 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_dcache_all(void) {
Kojto 100:cbbeb26dbd92 1145 __v7_all_cache(0);
Kojto 100:cbbeb26dbd92 1146 }
Kojto 100:cbbeb26dbd92 1147
Kojto 100:cbbeb26dbd92 1148 /** \brief Clean the whole D$
Kojto 100:cbbeb26dbd92 1149
Kojto 100:cbbeb26dbd92 1150 DCCSW. Clean by Set/Way
Kojto 100:cbbeb26dbd92 1151 */
Kojto 100:cbbeb26dbd92 1152
Kojto 100:cbbeb26dbd92 1153 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_dcache_all(void) {
Kojto 100:cbbeb26dbd92 1154 __v7_all_cache(1);
Kojto 100:cbbeb26dbd92 1155 }
Kojto 100:cbbeb26dbd92 1156
Kojto 100:cbbeb26dbd92 1157 /** \brief Clean and invalidate the whole D$
Kojto 100:cbbeb26dbd92 1158
Kojto 100:cbbeb26dbd92 1159 DCCISW. Clean and Invalidate by Set/Way
Kojto 100:cbbeb26dbd92 1160 */
Kojto 100:cbbeb26dbd92 1161
Kojto 100:cbbeb26dbd92 1162 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_inv_dcache_all(void) {
Kojto 100:cbbeb26dbd92 1163 __v7_all_cache(2);
Kojto 100:cbbeb26dbd92 1164 }
Kojto 100:cbbeb26dbd92 1165
Kojto 100:cbbeb26dbd92 1166 #include "core_ca_mmu.h"
Kojto 100:cbbeb26dbd92 1167
Kojto 100:cbbeb26dbd92 1168 #elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/
Kojto 100:cbbeb26dbd92 1169
Kojto 100:cbbeb26dbd92 1170 #error TASKING Compiler support not implemented for Cortex-A
Kojto 100:cbbeb26dbd92 1171
Kojto 100:cbbeb26dbd92 1172 #endif
Kojto 100:cbbeb26dbd92 1173
Kojto 100:cbbeb26dbd92 1174 /*@} end of CMSIS_Core_RegAccFunctions */
Kojto 100:cbbeb26dbd92 1175
Kojto 100:cbbeb26dbd92 1176
Kojto 100:cbbeb26dbd92 1177 #endif /* __CORE_CAFUNC_H__ */