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TARGET_NUCLEO_F756ZG/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_rcc_ex.h@146:22da6e220af6, 2017-07-06 (annotated)

Committer:
AnnaBridge
Date:
Thu Jul 06 15:30:22 2017 +0100
Revision:
146:22da6e220af6
Parent:
139:856d2700e60b 
Release 146 of the mbed library.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 126:abea610beb85 1 /**
AnnaBridge 126:abea610beb85 2 ******************************************************************************
AnnaBridge 126:abea610beb85 3 * @file stm32f7xx_hal_rcc_ex.h
AnnaBridge 126:abea610beb85 4 * @author MCD Application Team
AnnaBridge 146:22da6e220af6 5 * @version V1.2.2
AnnaBridge 146:22da6e220af6 6 * @date 14-April-2017
AnnaBridge 126:abea610beb85 7 * @brief Header file of RCC HAL Extension module.
AnnaBridge 126:abea610beb85 8 ******************************************************************************
AnnaBridge 126:abea610beb85 9 * @attention
AnnaBridge 126:abea610beb85 10 *
AnnaBridge 146:22da6e220af6 11 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
AnnaBridge 126:abea610beb85 12 *
AnnaBridge 126:abea610beb85 13 * Redistribution and use in source and binary forms, with or without modification,
AnnaBridge 126:abea610beb85 14 * are permitted provided that the following conditions are met:
AnnaBridge 126:abea610beb85 15 * 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge 126:abea610beb85 16 * this list of conditions and the following disclaimer.
AnnaBridge 126:abea610beb85 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge 126:abea610beb85 18 * this list of conditions and the following disclaimer in the documentation
AnnaBridge 126:abea610beb85 19 * and/or other materials provided with the distribution.
AnnaBridge 126:abea610beb85 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
AnnaBridge 126:abea610beb85 21 * may be used to endorse or promote products derived from this software
AnnaBridge 126:abea610beb85 22 * without specific prior written permission.
AnnaBridge 126:abea610beb85 23 *
AnnaBridge 126:abea610beb85 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge 126:abea610beb85 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge 126:abea610beb85 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge 126:abea610beb85 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge 126:abea610beb85 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge 126:abea610beb85 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge 126:abea610beb85 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge 126:abea610beb85 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge 126:abea610beb85 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge 126:abea610beb85 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge 126:abea610beb85 34 *
AnnaBridge 126:abea610beb85 35 ******************************************************************************
AnnaBridge 126:abea610beb85 36 */
AnnaBridge 126:abea610beb85 37
AnnaBridge 126:abea610beb85 38 /* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge 126:abea610beb85 39 #ifndef __STM32F7xx_HAL_RCC_EX_H
AnnaBridge 126:abea610beb85 40 #define __STM32F7xx_HAL_RCC_EX_H
AnnaBridge 126:abea610beb85 41
AnnaBridge 126:abea610beb85 42 #ifdef __cplusplus
AnnaBridge 126:abea610beb85 43 extern "C" {
AnnaBridge 126:abea610beb85 44 #endif
AnnaBridge 126:abea610beb85 45
AnnaBridge 126:abea610beb85 46 /* Includes ------------------------------------------------------------------*/
AnnaBridge 126:abea610beb85 47 #include "stm32f7xx_hal_def.h"
AnnaBridge 126:abea610beb85 48
AnnaBridge 126:abea610beb85 49 /** @addtogroup STM32F7xx_HAL_Driver
AnnaBridge 126:abea610beb85 50 * @{
AnnaBridge 126:abea610beb85 51 */
AnnaBridge 126:abea610beb85 52
AnnaBridge 126:abea610beb85 53 /** @addtogroup RCCEx
AnnaBridge 126:abea610beb85 54 * @{
AnnaBridge 126:abea610beb85 55 */
AnnaBridge 126:abea610beb85 56
AnnaBridge 126:abea610beb85 57 /* Exported types ------------------------------------------------------------*/
AnnaBridge 126:abea610beb85 58 /** @defgroup RCCEx_Exported_Types RCCEx Exported Types
AnnaBridge 126:abea610beb85 59 * @{
AnnaBridge 126:abea610beb85 60 */
AnnaBridge 126:abea610beb85 61
AnnaBridge 126:abea610beb85 62 /**
AnnaBridge 126:abea610beb85 63 * @brief RCC PLL configuration structure definition
AnnaBridge 126:abea610beb85 64 */
AnnaBridge 126:abea610beb85 65 typedef struct
AnnaBridge 126:abea610beb85 66 {
AnnaBridge 126:abea610beb85 67 uint32_t PLLState; /*!< The new state of the PLL.
AnnaBridge 126:abea610beb85 68 This parameter can be a value of @ref RCC_PLL_Config */
AnnaBridge 126:abea610beb85 69
AnnaBridge 126:abea610beb85 70 uint32_t PLLSource; /*!< RCC_PLLSource: PLL entry clock source.
AnnaBridge 126:abea610beb85 71 This parameter must be a value of @ref RCC_PLL_Clock_Source */
AnnaBridge 126:abea610beb85 72
AnnaBridge 126:abea610beb85 73 uint32_t PLLM; /*!< PLLM: Division factor for PLL VCO input clock.
AnnaBridge 126:abea610beb85 74 This parameter must be a number between Min_Data = 2 and Max_Data = 63 */
AnnaBridge 126:abea610beb85 75
AnnaBridge 126:abea610beb85 76 uint32_t PLLN; /*!< PLLN: Multiplication factor for PLL VCO output clock.
AnnaBridge 126:abea610beb85 77 This parameter must be a number between Min_Data = 50 and Max_Data = 432 */
AnnaBridge 126:abea610beb85 78
AnnaBridge 126:abea610beb85 79 uint32_t PLLP; /*!< PLLP: Division factor for main system clock (SYSCLK).
AnnaBridge 126:abea610beb85 80 This parameter must be a value of @ref RCC_PLLP_Clock_Divider */
AnnaBridge 126:abea610beb85 81
AnnaBridge 126:abea610beb85 82 uint32_t PLLQ; /*!< PLLQ: Division factor for OTG FS, SDMMC and RNG clocks.
AnnaBridge 126:abea610beb85 83 This parameter must be a number between Min_Data = 2 and Max_Data = 15 */
AnnaBridge 126:abea610beb85 84 #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
AnnaBridge 126:abea610beb85 85 uint32_t PLLR; /*!< PLLR: Division factor for DSI clock.
AnnaBridge 126:abea610beb85 86 This parameter must be a number between Min_Data = 2 and Max_Data = 7 */
AnnaBridge 126:abea610beb85 87 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
AnnaBridge 126:abea610beb85 88
AnnaBridge 126:abea610beb85 89 }RCC_PLLInitTypeDef;
AnnaBridge 126:abea610beb85 90
AnnaBridge 126:abea610beb85 91 /**
AnnaBridge 126:abea610beb85 92 * @brief PLLI2S Clock structure definition
AnnaBridge 126:abea610beb85 93 */
AnnaBridge 126:abea610beb85 94 typedef struct
AnnaBridge 126:abea610beb85 95 {
AnnaBridge 126:abea610beb85 96 uint32_t PLLI2SN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
AnnaBridge 126:abea610beb85 97 This parameter must be a number between Min_Data = 50 and Max_Data = 432.
AnnaBridge 126:abea610beb85 98 This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
AnnaBridge 126:abea610beb85 99
AnnaBridge 126:abea610beb85 100 uint32_t PLLI2SR; /*!< Specifies the division factor for I2S clock.
AnnaBridge 126:abea610beb85 101 This parameter must be a number between Min_Data = 2 and Max_Data = 7.
AnnaBridge 126:abea610beb85 102 This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
AnnaBridge 126:abea610beb85 103
AnnaBridge 126:abea610beb85 104 uint32_t PLLI2SQ; /*!< Specifies the division factor for SAI1 clock.
AnnaBridge 126:abea610beb85 105 This parameter must be a number between Min_Data = 2 and Max_Data = 15.
AnnaBridge 126:abea610beb85 106 This parameter will be used only when PLLI2S is selected as Clock Source SAI */
AnnaBridge 126:abea610beb85 107
<> 135:176b8275d35d 108 #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) || defined (STM32F767xx) || \
<> 135:176b8275d35d 109 defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
AnnaBridge 126:abea610beb85 110 uint32_t PLLI2SP; /*!< Specifies the division factor for SPDIF-RX clock.
AnnaBridge 126:abea610beb85 111 This parameter must be a value of @ref RCCEx_PLLI2SP_Clock_Divider.
AnnaBridge 126:abea610beb85 112 This parameter will be used only when PLLI2S is selected as Clock Source SPDIF-RX */
<> 135:176b8275d35d 113 #endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
AnnaBridge 126:abea610beb85 114 }RCC_PLLI2SInitTypeDef;
AnnaBridge 126:abea610beb85 115
AnnaBridge 126:abea610beb85 116 /**
AnnaBridge 126:abea610beb85 117 * @brief PLLSAI Clock structure definition
AnnaBridge 126:abea610beb85 118 */
AnnaBridge 126:abea610beb85 119 typedef struct
AnnaBridge 126:abea610beb85 120 {
AnnaBridge 126:abea610beb85 121 uint32_t PLLSAIN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
AnnaBridge 126:abea610beb85 122 This parameter must be a number between Min_Data = 50 and Max_Data = 432.
AnnaBridge 126:abea610beb85 123 This parameter will be used only when PLLSAI is selected as Clock Source SAI or LTDC */
AnnaBridge 126:abea610beb85 124
AnnaBridge 126:abea610beb85 125 uint32_t PLLSAIQ; /*!< Specifies the division factor for SAI1 clock.
AnnaBridge 126:abea610beb85 126 This parameter must be a number between Min_Data = 2 and Max_Data = 15.
AnnaBridge 126:abea610beb85 127 This parameter will be used only when PLLSAI is selected as Clock Source SAI or LTDC */
<> 135:176b8275d35d 128
<> 135:176b8275d35d 129 #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) || defined (STM32F767xx) || \
<> 135:176b8275d35d 130 defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
AnnaBridge 126:abea610beb85 131 uint32_t PLLSAIR; /*!< specifies the division factor for LTDC clock
AnnaBridge 126:abea610beb85 132 This parameter must be a number between Min_Data = 2 and Max_Data = 7.
AnnaBridge 126:abea610beb85 133 This parameter will be used only when PLLSAI is selected as Clock Source LTDC */
<> 135:176b8275d35d 134 #endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
<> 135:176b8275d35d 135
AnnaBridge 126:abea610beb85 136 uint32_t PLLSAIP; /*!< Specifies the division factor for 48MHz clock.
AnnaBridge 126:abea610beb85 137 This parameter must be a value of @ref RCCEx_PLLSAIP_Clock_Divider
AnnaBridge 126:abea610beb85 138 This parameter will be used only when PLLSAI is disabled */
AnnaBridge 126:abea610beb85 139 }RCC_PLLSAIInitTypeDef;
AnnaBridge 126:abea610beb85 140
AnnaBridge 126:abea610beb85 141 /**
AnnaBridge 126:abea610beb85 142 * @brief RCC extended clocks structure definition
AnnaBridge 126:abea610beb85 143 */
AnnaBridge 126:abea610beb85 144 typedef struct
AnnaBridge 126:abea610beb85 145 {
AnnaBridge 126:abea610beb85 146 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
AnnaBridge 126:abea610beb85 147 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
AnnaBridge 126:abea610beb85 148
AnnaBridge 126:abea610beb85 149 RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters.
AnnaBridge 126:abea610beb85 150 This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
AnnaBridge 126:abea610beb85 151
AnnaBridge 126:abea610beb85 152 RCC_PLLSAIInitTypeDef PLLSAI; /*!< PLL SAI structure parameters.
AnnaBridge 126:abea610beb85 153 This parameter will be used only when PLLI2S is selected as Clock Source SAI or LTDC */
AnnaBridge 126:abea610beb85 154
AnnaBridge 126:abea610beb85 155 uint32_t PLLI2SDivQ; /*!< Specifies the PLLI2S division factor for SAI1 clock.
AnnaBridge 126:abea610beb85 156 This parameter must be a number between Min_Data = 1 and Max_Data = 32
AnnaBridge 126:abea610beb85 157 This parameter will be used only when PLLI2S is selected as Clock Source SAI */
AnnaBridge 126:abea610beb85 158
AnnaBridge 126:abea610beb85 159 uint32_t PLLSAIDivQ; /*!< Specifies the PLLI2S division factor for SAI1 clock.
AnnaBridge 126:abea610beb85 160 This parameter must be a number between Min_Data = 1 and Max_Data = 32
AnnaBridge 126:abea610beb85 161 This parameter will be used only when PLLSAI is selected as Clock Source SAI */
AnnaBridge 126:abea610beb85 162
AnnaBridge 126:abea610beb85 163 uint32_t PLLSAIDivR; /*!< Specifies the PLLSAI division factor for LTDC clock.
AnnaBridge 126:abea610beb85 164 This parameter must be one value of @ref RCCEx_PLLSAI_DIVR */
AnnaBridge 126:abea610beb85 165
AnnaBridge 126:abea610beb85 166 uint32_t RTCClockSelection; /*!< Specifies RTC Clock source Selection.
AnnaBridge 126:abea610beb85 167 This parameter can be a value of @ref RCC_RTC_Clock_Source */
AnnaBridge 126:abea610beb85 168
AnnaBridge 126:abea610beb85 169 uint32_t I2sClockSelection; /*!< Specifies I2S Clock source Selection.
AnnaBridge 126:abea610beb85 170 This parameter can be a value of @ref RCCEx_I2S_Clock_Source */
AnnaBridge 126:abea610beb85 171
AnnaBridge 126:abea610beb85 172 uint32_t TIMPresSelection; /*!< Specifies TIM Clock Prescalers Selection.
AnnaBridge 126:abea610beb85 173 This parameter can be a value of @ref RCCEx_TIM_Prescaler_Selection */
AnnaBridge 126:abea610beb85 174
AnnaBridge 126:abea610beb85 175 uint32_t Sai1ClockSelection; /*!< Specifies SAI1 Clock Prescalers Selection
AnnaBridge 126:abea610beb85 176 This parameter can be a value of @ref RCCEx_SAI1_Clock_Source */
AnnaBridge 126:abea610beb85 177
AnnaBridge 126:abea610beb85 178 uint32_t Sai2ClockSelection; /*!< Specifies SAI2 Clock Prescalers Selection
AnnaBridge 126:abea610beb85 179 This parameter can be a value of @ref RCCEx_SAI2_Clock_Source */
AnnaBridge 126:abea610beb85 180
AnnaBridge 126:abea610beb85 181 uint32_t Usart1ClockSelection; /*!< USART1 clock source
AnnaBridge 126:abea610beb85 182 This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
AnnaBridge 126:abea610beb85 183
AnnaBridge 126:abea610beb85 184 uint32_t Usart2ClockSelection; /*!< USART2 clock source
AnnaBridge 126:abea610beb85 185 This parameter can be a value of @ref RCCEx_USART2_Clock_Source */
AnnaBridge 126:abea610beb85 186
AnnaBridge 126:abea610beb85 187 uint32_t Usart3ClockSelection; /*!< USART3 clock source
AnnaBridge 126:abea610beb85 188 This parameter can be a value of @ref RCCEx_USART3_Clock_Source */
AnnaBridge 126:abea610beb85 189
AnnaBridge 126:abea610beb85 190 uint32_t Uart4ClockSelection; /*!< UART4 clock source
AnnaBridge 126:abea610beb85 191 This parameter can be a value of @ref RCCEx_UART4_Clock_Source */
AnnaBridge 126:abea610beb85 192
AnnaBridge 126:abea610beb85 193 uint32_t Uart5ClockSelection; /*!< UART5 clock source
AnnaBridge 126:abea610beb85 194 This parameter can be a value of @ref RCCEx_UART5_Clock_Source */
AnnaBridge 126:abea610beb85 195
AnnaBridge 126:abea610beb85 196 uint32_t Usart6ClockSelection; /*!< USART6 clock source
AnnaBridge 126:abea610beb85 197 This parameter can be a value of @ref RCCEx_USART6_Clock_Source */
AnnaBridge 126:abea610beb85 198
AnnaBridge 126:abea610beb85 199 uint32_t Uart7ClockSelection; /*!< UART7 clock source
AnnaBridge 126:abea610beb85 200 This parameter can be a value of @ref RCCEx_UART7_Clock_Source */
AnnaBridge 126:abea610beb85 201
AnnaBridge 126:abea610beb85 202 uint32_t Uart8ClockSelection; /*!< UART8 clock source
AnnaBridge 126:abea610beb85 203 This parameter can be a value of @ref RCCEx_UART8_Clock_Source */
AnnaBridge 126:abea610beb85 204
AnnaBridge 126:abea610beb85 205 uint32_t I2c1ClockSelection; /*!< I2C1 clock source
AnnaBridge 126:abea610beb85 206 This parameter can be a value of @ref RCCEx_I2C1_Clock_Source */
AnnaBridge 126:abea610beb85 207
AnnaBridge 126:abea610beb85 208 uint32_t I2c2ClockSelection; /*!< I2C2 clock source
AnnaBridge 126:abea610beb85 209 This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */
AnnaBridge 126:abea610beb85 210
AnnaBridge 126:abea610beb85 211 uint32_t I2c3ClockSelection; /*!< I2C3 clock source
AnnaBridge 126:abea610beb85 212 This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */
AnnaBridge 126:abea610beb85 213
AnnaBridge 126:abea610beb85 214 uint32_t I2c4ClockSelection; /*!< I2C4 clock source
AnnaBridge 126:abea610beb85 215 This parameter can be a value of @ref RCCEx_I2C4_Clock_Source */
AnnaBridge 126:abea610beb85 216
AnnaBridge 126:abea610beb85 217 uint32_t Lptim1ClockSelection; /*!< Specifies LPTIM1 clock source
AnnaBridge 126:abea610beb85 218 This parameter can be a value of @ref RCCEx_LPTIM1_Clock_Source */
AnnaBridge 126:abea610beb85 219
AnnaBridge 126:abea610beb85 220 uint32_t CecClockSelection; /*!< CEC clock source
AnnaBridge 126:abea610beb85 221 This parameter can be a value of @ref RCCEx_CEC_Clock_Source */
AnnaBridge 126:abea610beb85 222
AnnaBridge 126:abea610beb85 223 uint32_t Clk48ClockSelection; /*!< Specifies 48Mhz clock source used by USB OTG FS, RNG and SDMMC
AnnaBridge 126:abea610beb85 224 This parameter can be a value of @ref RCCEx_CLK48_Clock_Source */
AnnaBridge 126:abea610beb85 225
AnnaBridge 126:abea610beb85 226 uint32_t Sdmmc1ClockSelection; /*!< SDMMC1 clock source
AnnaBridge 126:abea610beb85 227 This parameter can be a value of @ref RCCEx_SDMMC1_Clock_Source */
AnnaBridge 126:abea610beb85 228
<> 139:856d2700e60b 229 #if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\
<> 139:856d2700e60b 230 defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
AnnaBridge 126:abea610beb85 231 uint32_t Sdmmc2ClockSelection; /*!< SDMMC2 clock source
AnnaBridge 126:abea610beb85 232 This parameter can be a value of @ref RCCEx_SDMMC2_Clock_Source */
<> 139:856d2700e60b 233 #endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
AnnaBridge 126:abea610beb85 234
<> 139:856d2700e60b 235 #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
AnnaBridge 126:abea610beb85 236 uint32_t Dfsdm1ClockSelection; /*!< DFSDM1 clock source
AnnaBridge 126:abea610beb85 237 This parameter can be a value of @ref RCCEx_DFSDM1_Kernel_Clock_Source */
AnnaBridge 126:abea610beb85 238
AnnaBridge 126:abea610beb85 239 uint32_t Dfsdm1AudioClockSelection; /*!< DFSDM1 clock source
AnnaBridge 126:abea610beb85 240 This parameter can be a value of @ref RCCEx_DFSDM1_AUDIO_Clock_Source */
AnnaBridge 126:abea610beb85 241 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
AnnaBridge 126:abea610beb85 242 }RCC_PeriphCLKInitTypeDef;
AnnaBridge 126:abea610beb85 243 /**
AnnaBridge 126:abea610beb85 244 * @}
AnnaBridge 126:abea610beb85 245 */
AnnaBridge 126:abea610beb85 246
AnnaBridge 126:abea610beb85 247 /* Exported constants --------------------------------------------------------*/
AnnaBridge 126:abea610beb85 248 /** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants
AnnaBridge 126:abea610beb85 249 * @{
AnnaBridge 126:abea610beb85 250 */
AnnaBridge 126:abea610beb85 251
AnnaBridge 126:abea610beb85 252 /** @defgroup RCCEx_Periph_Clock_Selection RCC Periph Clock Selection
AnnaBridge 126:abea610beb85 253 * @{
AnnaBridge 126:abea610beb85 254 */
AnnaBridge 126:abea610beb85 255 #define RCC_PERIPHCLK_I2S ((uint32_t)0x00000001U)
AnnaBridge 126:abea610beb85 256 #if defined(STM32F746xx) || defined(STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
AnnaBridge 126:abea610beb85 257 #define RCC_PERIPHCLK_LTDC ((uint32_t)0x00000008U)
AnnaBridge 126:abea610beb85 258 #endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
AnnaBridge 126:abea610beb85 259 #define RCC_PERIPHCLK_TIM ((uint32_t)0x00000010U)
AnnaBridge 126:abea610beb85 260 #define RCC_PERIPHCLK_RTC ((uint32_t)0x00000020U)
AnnaBridge 126:abea610beb85 261 #define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000040U)
AnnaBridge 126:abea610beb85 262 #define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000080U)
AnnaBridge 126:abea610beb85 263 #define RCC_PERIPHCLK_USART3 ((uint32_t)0x00000100U)
AnnaBridge 126:abea610beb85 264 #define RCC_PERIPHCLK_UART4 ((uint32_t)0x00000200U)
AnnaBridge 126:abea610beb85 265 #define RCC_PERIPHCLK_UART5 ((uint32_t)0x00000400U)
AnnaBridge 126:abea610beb85 266 #define RCC_PERIPHCLK_USART6 ((uint32_t)0x00000800U)
AnnaBridge 126:abea610beb85 267 #define RCC_PERIPHCLK_UART7 ((uint32_t)0x00001000U)
AnnaBridge 126:abea610beb85 268 #define RCC_PERIPHCLK_UART8 ((uint32_t)0x00002000U)
AnnaBridge 126:abea610beb85 269 #define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00004000U)
AnnaBridge 126:abea610beb85 270 #define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00008000U)
AnnaBridge 126:abea610beb85 271 #define RCC_PERIPHCLK_I2C3 ((uint32_t)0x00010000U)
AnnaBridge 126:abea610beb85 272 #define RCC_PERIPHCLK_I2C4 ((uint32_t)0x00020000U)
AnnaBridge 126:abea610beb85 273 #define RCC_PERIPHCLK_LPTIM1 ((uint32_t)0x00040000U)
AnnaBridge 126:abea610beb85 274 #define RCC_PERIPHCLK_SAI1 ((uint32_t)0x00080000U)
AnnaBridge 126:abea610beb85 275 #define RCC_PERIPHCLK_SAI2 ((uint32_t)0x00100000U)
AnnaBridge 126:abea610beb85 276 #define RCC_PERIPHCLK_CLK48 ((uint32_t)0x00200000U)
AnnaBridge 126:abea610beb85 277 #define RCC_PERIPHCLK_CEC ((uint32_t)0x00400000U)
AnnaBridge 126:abea610beb85 278 #define RCC_PERIPHCLK_SDMMC1 ((uint32_t)0x00800000U)
AnnaBridge 126:abea610beb85 279 #define RCC_PERIPHCLK_SPDIFRX ((uint32_t)0x01000000U)
AnnaBridge 126:abea610beb85 280 #define RCC_PERIPHCLK_PLLI2S ((uint32_t)0x02000000U)
<> 139:856d2700e60b 281 #if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\
<> 139:856d2700e60b 282 defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
AnnaBridge 126:abea610beb85 283 #define RCC_PERIPHCLK_SDMMC2 ((uint32_t)0x04000000U)
<> 139:856d2700e60b 284 #endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
<> 139:856d2700e60b 285 #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
AnnaBridge 126:abea610beb85 286 #define RCC_PERIPHCLK_DFSDM1 ((uint32_t)0x08000000U)
AnnaBridge 126:abea610beb85 287 #define RCC_PERIPHCLK_DFSDM1_AUDIO ((uint32_t)0x10000000U)
<> 135:176b8275d35d 288 #endif /* STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
AnnaBridge 126:abea610beb85 289
AnnaBridge 126:abea610beb85 290 /**
AnnaBridge 126:abea610beb85 291 * @}
AnnaBridge 126:abea610beb85 292 */
AnnaBridge 126:abea610beb85 293
<> 135:176b8275d35d 294 #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) || defined (STM32F767xx) || \
<> 135:176b8275d35d 295 defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
AnnaBridge 126:abea610beb85 296 /** @defgroup RCCEx_PLLI2SP_Clock_Divider RCCEx PLLI2SP Clock Divider
AnnaBridge 126:abea610beb85 297 * @{
AnnaBridge 126:abea610beb85 298 */
AnnaBridge 126:abea610beb85 299 #define RCC_PLLI2SP_DIV2 ((uint32_t)0x00000000U)
AnnaBridge 126:abea610beb85 300 #define RCC_PLLI2SP_DIV4 ((uint32_t)0x00000001U)
AnnaBridge 126:abea610beb85 301 #define RCC_PLLI2SP_DIV6 ((uint32_t)0x00000002U)
AnnaBridge 126:abea610beb85 302 #define RCC_PLLI2SP_DIV8 ((uint32_t)0x00000003U)
AnnaBridge 126:abea610beb85 303 /**
AnnaBridge 126:abea610beb85 304 * @}
AnnaBridge 126:abea610beb85 305 */
<> 135:176b8275d35d 306 #endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
AnnaBridge 126:abea610beb85 307
AnnaBridge 126:abea610beb85 308 /** @defgroup RCCEx_PLLSAIP_Clock_Divider RCCEx PLLSAIP Clock Divider
AnnaBridge 126:abea610beb85 309 * @{
AnnaBridge 126:abea610beb85 310 */
AnnaBridge 126:abea610beb85 311 #define RCC_PLLSAIP_DIV2 ((uint32_t)0x00000000U)
AnnaBridge 126:abea610beb85 312 #define RCC_PLLSAIP_DIV4 ((uint32_t)0x00000001U)
AnnaBridge 126:abea610beb85 313 #define RCC_PLLSAIP_DIV6 ((uint32_t)0x00000002U)
AnnaBridge 126:abea610beb85 314 #define RCC_PLLSAIP_DIV8 ((uint32_t)0x00000003U)
AnnaBridge 126:abea610beb85 315 /**
AnnaBridge 126:abea610beb85 316 * @}
AnnaBridge 126:abea610beb85 317 */
AnnaBridge 126:abea610beb85 318
AnnaBridge 126:abea610beb85 319 /** @defgroup RCCEx_PLLSAI_DIVR RCCEx PLLSAI DIVR
AnnaBridge 126:abea610beb85 320 * @{
AnnaBridge 126:abea610beb85 321 */
AnnaBridge 126:abea610beb85 322 #define RCC_PLLSAIDIVR_2 ((uint32_t)0x00000000U)
AnnaBridge 126:abea610beb85 323 #define RCC_PLLSAIDIVR_4 RCC_DCKCFGR1_PLLSAIDIVR_0
AnnaBridge 126:abea610beb85 324 #define RCC_PLLSAIDIVR_8 RCC_DCKCFGR1_PLLSAIDIVR_1
AnnaBridge 126:abea610beb85 325 #define RCC_PLLSAIDIVR_16 RCC_DCKCFGR1_PLLSAIDIVR
AnnaBridge 126:abea610beb85 326 /**
AnnaBridge 126:abea610beb85 327 * @}
AnnaBridge 126:abea610beb85 328 */
AnnaBridge 126:abea610beb85 329
AnnaBridge 126:abea610beb85 330 /** @defgroup RCCEx_I2S_Clock_Source RCCEx I2S Clock Source
AnnaBridge 126:abea610beb85 331 * @{
AnnaBridge 126:abea610beb85 332 */
AnnaBridge 126:abea610beb85 333 #define RCC_I2SCLKSOURCE_PLLI2S ((uint32_t)0x00000000U)
AnnaBridge 126:abea610beb85 334 #define RCC_I2SCLKSOURCE_EXT RCC_CFGR_I2SSRC
AnnaBridge 126:abea610beb85 335
AnnaBridge 126:abea610beb85 336 /**
AnnaBridge 126:abea610beb85 337 * @}
AnnaBridge 126:abea610beb85 338 */
AnnaBridge 126:abea610beb85 339
AnnaBridge 126:abea610beb85 340
AnnaBridge 126:abea610beb85 341 /** @defgroup RCCEx_SAI1_Clock_Source RCCEx SAI1 Clock Source
AnnaBridge 126:abea610beb85 342 * @{
AnnaBridge 126:abea610beb85 343 */
AnnaBridge 126:abea610beb85 344 #define RCC_SAI1CLKSOURCE_PLLSAI ((uint32_t)0x00000000U)
AnnaBridge 126:abea610beb85 345 #define RCC_SAI1CLKSOURCE_PLLI2S RCC_DCKCFGR1_SAI1SEL_0
AnnaBridge 126:abea610beb85 346 #define RCC_SAI1CLKSOURCE_PIN RCC_DCKCFGR1_SAI1SEL_1
AnnaBridge 126:abea610beb85 347 #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
AnnaBridge 126:abea610beb85 348 #define RCC_SAI1CLKSOURCE_PLLSRC RCC_DCKCFGR1_SAI1SEL
AnnaBridge 126:abea610beb85 349 #endif /* STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
AnnaBridge 126:abea610beb85 350 /**
AnnaBridge 126:abea610beb85 351 * @}
AnnaBridge 126:abea610beb85 352 */
AnnaBridge 126:abea610beb85 353
AnnaBridge 126:abea610beb85 354 /** @defgroup RCCEx_SAI2_Clock_Source RCCEx SAI2 Clock Source
AnnaBridge 126:abea610beb85 355 * @{
AnnaBridge 126:abea610beb85 356 */
AnnaBridge 126:abea610beb85 357 #define RCC_SAI2CLKSOURCE_PLLSAI ((uint32_t)0x00000000U)
AnnaBridge 126:abea610beb85 358 #define RCC_SAI2CLKSOURCE_PLLI2S RCC_DCKCFGR1_SAI2SEL_0
AnnaBridge 126:abea610beb85 359 #define RCC_SAI2CLKSOURCE_PIN RCC_DCKCFGR1_SAI2SEL_1
AnnaBridge 126:abea610beb85 360 #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
AnnaBridge 126:abea610beb85 361 #define RCC_SAI2CLKSOURCE_PLLSRC RCC_DCKCFGR1_SAI2SEL
AnnaBridge 126:abea610beb85 362 #endif /* STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
AnnaBridge 126:abea610beb85 363 /**
AnnaBridge 126:abea610beb85 364 * @}
AnnaBridge 126:abea610beb85 365 */
AnnaBridge 126:abea610beb85 366
AnnaBridge 126:abea610beb85 367 /** @defgroup RCCEx_CEC_Clock_Source RCCEx CEC Clock Source
AnnaBridge 126:abea610beb85 368 * @{
AnnaBridge 126:abea610beb85 369 */
AnnaBridge 126:abea610beb85 370 #define RCC_CECCLKSOURCE_LSE ((uint32_t)0x00000000U)
AnnaBridge 126:abea610beb85 371 #define RCC_CECCLKSOURCE_HSI RCC_DCKCFGR2_CECSEL /* CEC clock is HSI/488*/
AnnaBridge 126:abea610beb85 372 /**
AnnaBridge 126:abea610beb85 373 * @}
AnnaBridge 126:abea610beb85 374 */
AnnaBridge 126:abea610beb85 375
AnnaBridge 126:abea610beb85 376 /** @defgroup RCCEx_USART1_Clock_Source RCCEx USART1 Clock Source
AnnaBridge 126:abea610beb85 377 * @{
AnnaBridge 126:abea610beb85 378 */
AnnaBridge 126:abea610beb85 379 #define RCC_USART1CLKSOURCE_PCLK2 ((uint32_t)0x00000000U)
AnnaBridge 126:abea610beb85 380 #define RCC_USART1CLKSOURCE_SYSCLK RCC_DCKCFGR2_USART1SEL_0
AnnaBridge 126:abea610beb85 381 #define RCC_USART1CLKSOURCE_HSI RCC_DCKCFGR2_USART1SEL_1
AnnaBridge 126:abea610beb85 382 #define RCC_USART1CLKSOURCE_LSE RCC_DCKCFGR2_USART1SEL
AnnaBridge 126:abea610beb85 383 /**
AnnaBridge 126:abea610beb85 384 * @}
AnnaBridge 126:abea610beb85 385 */
AnnaBridge 126:abea610beb85 386
AnnaBridge 126:abea610beb85 387 /** @defgroup RCCEx_USART2_Clock_Source RCCEx USART2 Clock Source
AnnaBridge 126:abea610beb85 388 * @{
AnnaBridge 126:abea610beb85 389 */
AnnaBridge 126:abea610beb85 390 #define RCC_USART2CLKSOURCE_PCLK1 ((uint32_t)0x00000000U)
AnnaBridge 126:abea610beb85 391 #define RCC_USART2CLKSOURCE_SYSCLK RCC_DCKCFGR2_USART2SEL_0
AnnaBridge 126:abea610beb85 392 #define RCC_USART2CLKSOURCE_HSI RCC_DCKCFGR2_USART2SEL_1
AnnaBridge 126:abea610beb85 393 #define RCC_USART2CLKSOURCE_LSE RCC_DCKCFGR2_USART2SEL
AnnaBridge 126:abea610beb85 394 /**
AnnaBridge 126:abea610beb85 395 * @}
AnnaBridge 126:abea610beb85 396 */
AnnaBridge 126:abea610beb85 397
AnnaBridge 126:abea610beb85 398 /** @defgroup RCCEx_USART3_Clock_Source RCCEx USART3 Clock Source
AnnaBridge 126:abea610beb85 399 * @{
AnnaBridge 126:abea610beb85 400 */
AnnaBridge 126:abea610beb85 401 #define RCC_USART3CLKSOURCE_PCLK1 ((uint32_t)0x00000000U)
AnnaBridge 126:abea610beb85 402 #define RCC_USART3CLKSOURCE_SYSCLK RCC_DCKCFGR2_USART3SEL_0
AnnaBridge 126:abea610beb85 403 #define RCC_USART3CLKSOURCE_HSI RCC_DCKCFGR2_USART3SEL_1
AnnaBridge 126:abea610beb85 404 #define RCC_USART3CLKSOURCE_LSE RCC_DCKCFGR2_USART3SEL
AnnaBridge 126:abea610beb85 405 /**
AnnaBridge 126:abea610beb85 406 * @}
AnnaBridge 126:abea610beb85 407 */
AnnaBridge 126:abea610beb85 408
AnnaBridge 126:abea610beb85 409 /** @defgroup RCCEx_UART4_Clock_Source RCCEx UART4 Clock Source
AnnaBridge 126:abea610beb85 410 * @{
AnnaBridge 126:abea610beb85 411 */
AnnaBridge 126:abea610beb85 412 #define RCC_UART4CLKSOURCE_PCLK1 ((uint32_t)0x00000000U)
AnnaBridge 126:abea610beb85 413 #define RCC_UART4CLKSOURCE_SYSCLK RCC_DCKCFGR2_UART4SEL_0
AnnaBridge 126:abea610beb85 414 #define RCC_UART4CLKSOURCE_HSI RCC_DCKCFGR2_UART4SEL_1
AnnaBridge 126:abea610beb85 415 #define RCC_UART4CLKSOURCE_LSE RCC_DCKCFGR2_UART4SEL
AnnaBridge 126:abea610beb85 416 /**
AnnaBridge 126:abea610beb85 417 * @}
AnnaBridge 126:abea610beb85 418 */
AnnaBridge 126:abea610beb85 419
AnnaBridge 126:abea610beb85 420 /** @defgroup RCCEx_UART5_Clock_Source RCCEx UART5 Clock Source
AnnaBridge 126:abea610beb85 421 * @{
AnnaBridge 126:abea610beb85 422 */
AnnaBridge 126:abea610beb85 423 #define RCC_UART5CLKSOURCE_PCLK1 ((uint32_t)0x00000000U)
AnnaBridge 126:abea610beb85 424 #define RCC_UART5CLKSOURCE_SYSCLK RCC_DCKCFGR2_UART5SEL_0
AnnaBridge 126:abea610beb85 425 #define RCC_UART5CLKSOURCE_HSI RCC_DCKCFGR2_UART5SEL_1
AnnaBridge 126:abea610beb85 426 #define RCC_UART5CLKSOURCE_LSE RCC_DCKCFGR2_UART5SEL
AnnaBridge 126:abea610beb85 427 /**
AnnaBridge 126:abea610beb85 428 * @}
AnnaBridge 126:abea610beb85 429 */
AnnaBridge 126:abea610beb85 430
AnnaBridge 126:abea610beb85 431 /** @defgroup RCCEx_USART6_Clock_Source RCCEx USART6 Clock Source
AnnaBridge 126:abea610beb85 432 * @{
AnnaBridge 126:abea610beb85 433 */
AnnaBridge 126:abea610beb85 434 #define RCC_USART6CLKSOURCE_PCLK2 ((uint32_t)0x00000000U)
AnnaBridge 126:abea610beb85 435 #define RCC_USART6CLKSOURCE_SYSCLK RCC_DCKCFGR2_USART6SEL_0
AnnaBridge 126:abea610beb85 436 #define RCC_USART6CLKSOURCE_HSI RCC_DCKCFGR2_USART6SEL_1
AnnaBridge 126:abea610beb85 437 #define RCC_USART6CLKSOURCE_LSE RCC_DCKCFGR2_USART6SEL
AnnaBridge 126:abea610beb85 438 /**
AnnaBridge 126:abea610beb85 439 * @}
AnnaBridge 126:abea610beb85 440 */
AnnaBridge 126:abea610beb85 441
AnnaBridge 126:abea610beb85 442 /** @defgroup RCCEx_UART7_Clock_Source RCCEx UART7 Clock Source
AnnaBridge 126:abea610beb85 443 * @{
AnnaBridge 126:abea610beb85 444 */
AnnaBridge 126:abea610beb85 445 #define RCC_UART7CLKSOURCE_PCLK1 ((uint32_t)0x00000000U)
AnnaBridge 126:abea610beb85 446 #define RCC_UART7CLKSOURCE_SYSCLK RCC_DCKCFGR2_UART7SEL_0
AnnaBridge 126:abea610beb85 447 #define RCC_UART7CLKSOURCE_HSI RCC_DCKCFGR2_UART7SEL_1
AnnaBridge 126:abea610beb85 448 #define RCC_UART7CLKSOURCE_LSE RCC_DCKCFGR2_UART7SEL
AnnaBridge 126:abea610beb85 449 /**
AnnaBridge 126:abea610beb85 450 * @}
AnnaBridge 126:abea610beb85 451 */
AnnaBridge 126:abea610beb85 452
AnnaBridge 126:abea610beb85 453 /** @defgroup RCCEx_UART8_Clock_Source RCCEx UART8 Clock Source
AnnaBridge 126:abea610beb85 454 * @{
AnnaBridge 126:abea610beb85 455 */
AnnaBridge 126:abea610beb85 456 #define RCC_UART8CLKSOURCE_PCLK1 ((uint32_t)0x00000000U)
AnnaBridge 126:abea610beb85 457 #define RCC_UART8CLKSOURCE_SYSCLK RCC_DCKCFGR2_UART8SEL_0
AnnaBridge 126:abea610beb85 458 #define RCC_UART8CLKSOURCE_HSI RCC_DCKCFGR2_UART8SEL_1
AnnaBridge 126:abea610beb85 459 #define RCC_UART8CLKSOURCE_LSE RCC_DCKCFGR2_UART8SEL
AnnaBridge 126:abea610beb85 460 /**
AnnaBridge 126:abea610beb85 461 * @}
AnnaBridge 126:abea610beb85 462 */
AnnaBridge 126:abea610beb85 463
AnnaBridge 126:abea610beb85 464 /** @defgroup RCCEx_I2C1_Clock_Source RCCEx I2C1 Clock Source
AnnaBridge 126:abea610beb85 465 * @{
AnnaBridge 126:abea610beb85 466 */
AnnaBridge 126:abea610beb85 467 #define RCC_I2C1CLKSOURCE_PCLK1 ((uint32_t)0x00000000U)
AnnaBridge 126:abea610beb85 468 #define RCC_I2C1CLKSOURCE_SYSCLK RCC_DCKCFGR2_I2C1SEL_0
AnnaBridge 126:abea610beb85 469 #define RCC_I2C1CLKSOURCE_HSI RCC_DCKCFGR2_I2C1SEL_1
AnnaBridge 126:abea610beb85 470 /**
AnnaBridge 126:abea610beb85 471 * @}
AnnaBridge 126:abea610beb85 472 */
AnnaBridge 126:abea610beb85 473
AnnaBridge 126:abea610beb85 474 /** @defgroup RCCEx_I2C2_Clock_Source RCCEx I2C2 Clock Source
AnnaBridge 126:abea610beb85 475 * @{
AnnaBridge 126:abea610beb85 476 */
AnnaBridge 126:abea610beb85 477 #define RCC_I2C2CLKSOURCE_PCLK1 ((uint32_t)0x00000000U)
AnnaBridge 126:abea610beb85 478 #define RCC_I2C2CLKSOURCE_SYSCLK RCC_DCKCFGR2_I2C2SEL_0
AnnaBridge 126:abea610beb85 479 #define RCC_I2C2CLKSOURCE_HSI RCC_DCKCFGR2_I2C2SEL_1
AnnaBridge 126:abea610beb85 480
AnnaBridge 126:abea610beb85 481 /**
AnnaBridge 126:abea610beb85 482 * @}
AnnaBridge 126:abea610beb85 483 */
AnnaBridge 126:abea610beb85 484
AnnaBridge 126:abea610beb85 485 /** @defgroup RCCEx_I2C3_Clock_Source RCCEx I2C3 Clock Source
AnnaBridge 126:abea610beb85 486 * @{
AnnaBridge 126:abea610beb85 487 */
AnnaBridge 126:abea610beb85 488 #define RCC_I2C3CLKSOURCE_PCLK1 ((uint32_t)0x00000000U)
AnnaBridge 126:abea610beb85 489 #define RCC_I2C3CLKSOURCE_SYSCLK RCC_DCKCFGR2_I2C3SEL_0
AnnaBridge 126:abea610beb85 490 #define RCC_I2C3CLKSOURCE_HSI RCC_DCKCFGR2_I2C3SEL_1
AnnaBridge 126:abea610beb85 491 /**
AnnaBridge 126:abea610beb85 492 * @}
AnnaBridge 126:abea610beb85 493 */
AnnaBridge 126:abea610beb85 494
AnnaBridge 126:abea610beb85 495 /** @defgroup RCCEx_I2C4_Clock_Source RCCEx I2C4 Clock Source
AnnaBridge 126:abea610beb85 496 * @{
AnnaBridge 126:abea610beb85 497 */
AnnaBridge 126:abea610beb85 498 #define RCC_I2C4CLKSOURCE_PCLK1 ((uint32_t)0x00000000U)
AnnaBridge 126:abea610beb85 499 #define RCC_I2C4CLKSOURCE_SYSCLK RCC_DCKCFGR2_I2C4SEL_0
AnnaBridge 126:abea610beb85 500 #define RCC_I2C4CLKSOURCE_HSI RCC_DCKCFGR2_I2C4SEL_1
AnnaBridge 126:abea610beb85 501 /**
AnnaBridge 126:abea610beb85 502 * @}
AnnaBridge 126:abea610beb85 503 */
AnnaBridge 126:abea610beb85 504
AnnaBridge 126:abea610beb85 505 /** @defgroup RCCEx_LPTIM1_Clock_Source RCCEx LPTIM1 Clock Source
AnnaBridge 126:abea610beb85 506 * @{
AnnaBridge 126:abea610beb85 507 */
<> 139:856d2700e60b 508 #define RCC_LPTIM1CLKSOURCE_PCLK1 ((uint32_t)0x00000000U)
AnnaBridge 126:abea610beb85 509 #define RCC_LPTIM1CLKSOURCE_LSI RCC_DCKCFGR2_LPTIM1SEL_0
AnnaBridge 126:abea610beb85 510 #define RCC_LPTIM1CLKSOURCE_HSI RCC_DCKCFGR2_LPTIM1SEL_1
AnnaBridge 126:abea610beb85 511 #define RCC_LPTIM1CLKSOURCE_LSE RCC_DCKCFGR2_LPTIM1SEL
AnnaBridge 126:abea610beb85 512
AnnaBridge 126:abea610beb85 513 /**
AnnaBridge 126:abea610beb85 514 * @}
AnnaBridge 126:abea610beb85 515 */
AnnaBridge 126:abea610beb85 516
AnnaBridge 126:abea610beb85 517 /** @defgroup RCCEx_CLK48_Clock_Source RCCEx CLK48 Clock Source
AnnaBridge 126:abea610beb85 518 * @{
AnnaBridge 126:abea610beb85 519 */
AnnaBridge 126:abea610beb85 520 #define RCC_CLK48SOURCE_PLL ((uint32_t)0x00000000U)
AnnaBridge 126:abea610beb85 521 #define RCC_CLK48SOURCE_PLLSAIP RCC_DCKCFGR2_CK48MSEL
AnnaBridge 126:abea610beb85 522 /**
AnnaBridge 126:abea610beb85 523 * @}
AnnaBridge 126:abea610beb85 524 */
AnnaBridge 126:abea610beb85 525
AnnaBridge 126:abea610beb85 526 /** @defgroup RCCEx_TIM_Prescaler_Selection RCCEx TIM Prescaler Selection
AnnaBridge 126:abea610beb85 527 * @{
AnnaBridge 126:abea610beb85 528 */
AnnaBridge 126:abea610beb85 529 #define RCC_TIMPRES_DESACTIVATED ((uint32_t)0x00000000U)
AnnaBridge 126:abea610beb85 530 #define RCC_TIMPRES_ACTIVATED RCC_DCKCFGR1_TIMPRE
AnnaBridge 126:abea610beb85 531 /**
AnnaBridge 126:abea610beb85 532 * @}
AnnaBridge 126:abea610beb85 533 */
AnnaBridge 126:abea610beb85 534
AnnaBridge 126:abea610beb85 535 /** @defgroup RCCEx_SDMMC1_Clock_Source RCCEx SDMMC1 Clock Source
AnnaBridge 126:abea610beb85 536 * @{
AnnaBridge 126:abea610beb85 537 */
AnnaBridge 126:abea610beb85 538 #define RCC_SDMMC1CLKSOURCE_CLK48 ((uint32_t)0x00000000U)
AnnaBridge 126:abea610beb85 539 #define RCC_SDMMC1CLKSOURCE_SYSCLK RCC_DCKCFGR2_SDMMC1SEL
AnnaBridge 126:abea610beb85 540 /**
AnnaBridge 126:abea610beb85 541 * @}
AnnaBridge 126:abea610beb85 542 */
AnnaBridge 126:abea610beb85 543
<> 139:856d2700e60b 544 #if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\
<> 139:856d2700e60b 545 defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
AnnaBridge 126:abea610beb85 546 /** @defgroup RCCEx_SDMMC2_Clock_Source RCCEx SDMMC2 Clock Source
AnnaBridge 126:abea610beb85 547 * @{
AnnaBridge 126:abea610beb85 548 */
AnnaBridge 126:abea610beb85 549 #define RCC_SDMMC2CLKSOURCE_CLK48 ((uint32_t)0x00000000U)
AnnaBridge 126:abea610beb85 550 #define RCC_SDMMC2CLKSOURCE_SYSCLK RCC_DCKCFGR2_SDMMC2SEL
AnnaBridge 126:abea610beb85 551 /**
AnnaBridge 126:abea610beb85 552 * @}
<> 139:856d2700e60b 553 */
<> 139:856d2700e60b 554 #endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
<> 139:856d2700e60b 555
<> 139:856d2700e60b 556 #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
AnnaBridge 126:abea610beb85 557 /** @defgroup RCCEx_DFSDM1_Kernel_Clock_Source RCCEx DFSDM1 Kernel Clock Source
AnnaBridge 126:abea610beb85 558 * @{
AnnaBridge 126:abea610beb85 559 */
<> 139:856d2700e60b 560 #define RCC_DFSDM1CLKSOURCE_PCLK2 ((uint32_t)0x00000000U)
AnnaBridge 126:abea610beb85 561 #define RCC_DFSDM1CLKSOURCE_SYSCLK RCC_DCKCFGR1_DFSDM1SEL
AnnaBridge 126:abea610beb85 562 /**
AnnaBridge 126:abea610beb85 563 * @}
AnnaBridge 126:abea610beb85 564 */
AnnaBridge 126:abea610beb85 565
AnnaBridge 126:abea610beb85 566 /** @defgroup RCCEx_DFSDM1_AUDIO_Clock_Source RCCEx DFSDM1 AUDIO Clock Source
AnnaBridge 126:abea610beb85 567 * @{
AnnaBridge 126:abea610beb85 568 */
AnnaBridge 126:abea610beb85 569 #define RCC_DFSDM1AUDIOCLKSOURCE_SAI1 ((uint32_t)0x00000000U)
AnnaBridge 126:abea610beb85 570 #define RCC_DFSDM1AUDIOCLKSOURCE_SAI2 RCC_DCKCFGR1_ADFSDM1SEL
AnnaBridge 126:abea610beb85 571 /**
AnnaBridge 126:abea610beb85 572 * @}
AnnaBridge 126:abea610beb85 573 */
AnnaBridge 126:abea610beb85 574 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
AnnaBridge 126:abea610beb85 575
AnnaBridge 126:abea610beb85 576 #if defined (STM32F769xx) || defined (STM32F779xx)
AnnaBridge 126:abea610beb85 577 /** @defgroup RCCEx_DSI_Clock_Source RCC DSI Clock Source
AnnaBridge 126:abea610beb85 578 * @{
AnnaBridge 126:abea610beb85 579 */
AnnaBridge 126:abea610beb85 580 #define RCC_DSICLKSOURCE_DSIPHY ((uint32_t)0x00000000U)
AnnaBridge 126:abea610beb85 581 #define RCC_DSICLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR2_DSISEL)
AnnaBridge 126:abea610beb85 582 /**
AnnaBridge 126:abea610beb85 583 * @}
AnnaBridge 126:abea610beb85 584 */
AnnaBridge 126:abea610beb85 585 #endif /* STM32F769xx || STM32F779xx */
AnnaBridge 126:abea610beb85 586
AnnaBridge 126:abea610beb85 587 /**
AnnaBridge 126:abea610beb85 588 * @}
AnnaBridge 126:abea610beb85 589 */
AnnaBridge 126:abea610beb85 590
AnnaBridge 126:abea610beb85 591 /* Exported macro ------------------------------------------------------------*/
AnnaBridge 126:abea610beb85 592 /** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros
AnnaBridge 126:abea610beb85 593 * @{
AnnaBridge 126:abea610beb85 594 */
AnnaBridge 126:abea610beb85 595 /** @defgroup RCCEx_Peripheral_Clock_Enable_Disable RCCEx_Peripheral_Clock_Enable_Disable
AnnaBridge 126:abea610beb85 596 * @brief Enables or disables the AHB/APB peripheral clock.
AnnaBridge 126:abea610beb85 597 * @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge 126:abea610beb85 598 * is disabled and the application software has to enable this clock before
AnnaBridge 126:abea610beb85 599 * using it.
AnnaBridge 126:abea610beb85 600 * @{
AnnaBridge 126:abea610beb85 601 */
AnnaBridge 126:abea610beb85 602
AnnaBridge 126:abea610beb85 603 /** @brief Enables or disables the AHB1 peripheral clock.
AnnaBridge 126:abea610beb85 604 * @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge 126:abea610beb85 605 * is disabled and the application software has to enable this clock before
AnnaBridge 126:abea610beb85 606 * using it.
AnnaBridge 126:abea610beb85 607 */
AnnaBridge 126:abea610beb85 608 #define __HAL_RCC_BKPSRAM_CLK_ENABLE() do { \
AnnaBridge 126:abea610beb85 609 __IO uint32_t tmpreg; \
AnnaBridge 126:abea610beb85 610 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
AnnaBridge 126:abea610beb85 611 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 126:abea610beb85 612 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
AnnaBridge 126:abea610beb85 613 UNUSED(tmpreg); \
AnnaBridge 126:abea610beb85 614 } while(0)
AnnaBridge 126:abea610beb85 615
AnnaBridge 126:abea610beb85 616 #define __HAL_RCC_DTCMRAMEN_CLK_ENABLE() do { \
AnnaBridge 126:abea610beb85 617 __IO uint32_t tmpreg; \
AnnaBridge 126:abea610beb85 618 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DTCMRAMEN);\
AnnaBridge 126:abea610beb85 619 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 126:abea610beb85 620 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DTCMRAMEN);\
AnnaBridge 126:abea610beb85 621 UNUSED(tmpreg); \
AnnaBridge 126:abea610beb85 622 } while(0)
AnnaBridge 126:abea610beb85 623
AnnaBridge 126:abea610beb85 624 #define __HAL_RCC_DMA2_CLK_ENABLE() do { \
AnnaBridge 126:abea610beb85 625 __IO uint32_t tmpreg; \
AnnaBridge 126:abea610beb85 626 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
AnnaBridge 126:abea610beb85 627 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 126:abea610beb85 628 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
AnnaBridge 126:abea610beb85 629 UNUSED(tmpreg); \
<> 139:856d2700e60b 630 } while(0)
AnnaBridge 126:abea610beb85 631
AnnaBridge 126:abea610beb85 632 #define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() do { \
AnnaBridge 126:abea610beb85 633 __IO uint32_t tmpreg; \
AnnaBridge 126:abea610beb85 634 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
AnnaBridge 126:abea610beb85 635 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 126:abea610beb85 636 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
AnnaBridge 126:abea610beb85 637 UNUSED(tmpreg); \
AnnaBridge 126:abea610beb85 638 } while(0)
AnnaBridge 126:abea610beb85 639
AnnaBridge 126:abea610beb85 640 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() do { \
AnnaBridge 126:abea610beb85 641 __IO uint32_t tmpreg; \
AnnaBridge 126:abea610beb85 642 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
AnnaBridge 126:abea610beb85 643 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 126:abea610beb85 644 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
AnnaBridge 126:abea610beb85 645 UNUSED(tmpreg); \
AnnaBridge 126:abea610beb85 646 } while(0)
AnnaBridge 126:abea610beb85 647
AnnaBridge 126:abea610beb85 648 #define __HAL_RCC_GPIOA_CLK_ENABLE() do { \
AnnaBridge 126:abea610beb85 649 __IO uint32_t tmpreg; \
AnnaBridge 126:abea610beb85 650 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\
AnnaBridge 126:abea610beb85 651 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 126:abea610beb85 652 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\
AnnaBridge 126:abea610beb85 653 UNUSED(tmpreg); \
AnnaBridge 126:abea610beb85 654 } while(0)
AnnaBridge 126:abea610beb85 655
AnnaBridge 126:abea610beb85 656 #define __HAL_RCC_GPIOB_CLK_ENABLE() do { \
AnnaBridge 126:abea610beb85 657 __IO uint32_t tmpreg; \
AnnaBridge 126:abea610beb85 658 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\
AnnaBridge 126:abea610beb85 659 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 126:abea610beb85 660 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\
AnnaBridge 126:abea610beb85 661 UNUSED(tmpreg); \
AnnaBridge 126:abea610beb85 662 } while(0)
AnnaBridge 126:abea610beb85 663
AnnaBridge 126:abea610beb85 664 #define __HAL_RCC_GPIOC_CLK_ENABLE() do { \
AnnaBridge 126:abea610beb85 665 __IO uint32_t tmpreg; \
AnnaBridge 126:abea610beb85 666 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\
AnnaBridge 126:abea610beb85 667 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 126:abea610beb85 668 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\
AnnaBridge 126:abea610beb85 669 UNUSED(tmpreg); \
AnnaBridge 126:abea610beb85 670 } while(0)
AnnaBridge 126:abea610beb85 671
AnnaBridge 126:abea610beb85 672 #define __HAL_RCC_GPIOD_CLK_ENABLE() do { \
AnnaBridge 126:abea610beb85 673 __IO uint32_t tmpreg; \
AnnaBridge 126:abea610beb85 674 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
AnnaBridge 126:abea610beb85 675 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 126:abea610beb85 676 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
AnnaBridge 126:abea610beb85 677 UNUSED(tmpreg); \
AnnaBridge 126:abea610beb85 678 } while(0)
AnnaBridge 126:abea610beb85 679
AnnaBridge 126:abea610beb85 680 #define __HAL_RCC_GPIOE_CLK_ENABLE() do { \
AnnaBridge 126:abea610beb85 681 __IO uint32_t tmpreg; \
AnnaBridge 126:abea610beb85 682 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
AnnaBridge 126:abea610beb85 683 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 126:abea610beb85 684 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
AnnaBridge 126:abea610beb85 685 UNUSED(tmpreg); \
AnnaBridge 126:abea610beb85 686 } while(0)
AnnaBridge 126:abea610beb85 687
AnnaBridge 126:abea610beb85 688 #define __HAL_RCC_GPIOF_CLK_ENABLE() do { \
AnnaBridge 126:abea610beb85 689 __IO uint32_t tmpreg; \
AnnaBridge 126:abea610beb85 690 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
AnnaBridge 126:abea610beb85 691 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 126:abea610beb85 692 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
AnnaBridge 126:abea610beb85 693 UNUSED(tmpreg); \
AnnaBridge 126:abea610beb85 694 } while(0)
AnnaBridge 126:abea610beb85 695
AnnaBridge 126:abea610beb85 696 #define __HAL_RCC_GPIOG_CLK_ENABLE() do { \
AnnaBridge 126:abea610beb85 697 __IO uint32_t tmpreg; \
AnnaBridge 126:abea610beb85 698 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
AnnaBridge 126:abea610beb85 699 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 126:abea610beb85 700 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
AnnaBridge 126:abea610beb85 701 UNUSED(tmpreg); \
AnnaBridge 126:abea610beb85 702 } while(0)
AnnaBridge 126:abea610beb85 703
AnnaBridge 126:abea610beb85 704 #define __HAL_RCC_GPIOH_CLK_ENABLE() do { \
AnnaBridge 126:abea610beb85 705 __IO uint32_t tmpreg; \
AnnaBridge 126:abea610beb85 706 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN);\
AnnaBridge 126:abea610beb85 707 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 126:abea610beb85 708 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN);\
AnnaBridge 126:abea610beb85 709 UNUSED(tmpreg); \
AnnaBridge 126:abea610beb85 710 } while(0)
AnnaBridge 126:abea610beb85 711
AnnaBridge 126:abea610beb85 712 #define __HAL_RCC_GPIOI_CLK_ENABLE() do { \
AnnaBridge 126:abea610beb85 713 __IO uint32_t tmpreg; \
AnnaBridge 126:abea610beb85 714 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\
AnnaBridge 126:abea610beb85 715 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 126:abea610beb85 716 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\
AnnaBridge 126:abea610beb85 717 UNUSED(tmpreg); \
AnnaBridge 126:abea610beb85 718 } while(0)
AnnaBridge 126:abea610beb85 719
<> 139:856d2700e60b 720 #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\
<> 139:856d2700e60b 721 defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
AnnaBridge 126:abea610beb85 722 #define __HAL_RCC_GPIOJ_CLK_ENABLE() do { \
AnnaBridge 126:abea610beb85 723 __IO uint32_t tmpreg; \
AnnaBridge 126:abea610beb85 724 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOJEN);\
AnnaBridge 126:abea610beb85 725 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 126:abea610beb85 726 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOJEN);\
AnnaBridge 126:abea610beb85 727 UNUSED(tmpreg); \
AnnaBridge 126:abea610beb85 728 } while(0)
AnnaBridge 126:abea610beb85 729
AnnaBridge 126:abea610beb85 730 #define __HAL_RCC_GPIOK_CLK_ENABLE() do { \
AnnaBridge 126:abea610beb85 731 __IO uint32_t tmpreg; \
AnnaBridge 126:abea610beb85 732 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOKEN);\
AnnaBridge 126:abea610beb85 733 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 126:abea610beb85 734 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOKEN);\
AnnaBridge 126:abea610beb85 735 UNUSED(tmpreg); \
AnnaBridge 126:abea610beb85 736 } while(0)
<> 139:856d2700e60b 737
<> 139:856d2700e60b 738 #define __HAL_RCC_DMA2D_CLK_ENABLE() do { \
<> 139:856d2700e60b 739 __IO uint32_t tmpreg; \
<> 139:856d2700e60b 740 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN);\
<> 139:856d2700e60b 741 /* Delay after an RCC peripheral clock enabling */ \
<> 139:856d2700e60b 742 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN);\
<> 139:856d2700e60b 743 UNUSED(tmpreg); \
<> 139:856d2700e60b 744 } while(0)
<> 139:856d2700e60b 745 #endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
AnnaBridge 126:abea610beb85 746
AnnaBridge 126:abea610beb85 747 #define __HAL_RCC_BKPSRAM_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_BKPSRAMEN))
AnnaBridge 126:abea610beb85 748 #define __HAL_RCC_DTCMRAMEN_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DTCMRAMEN))
AnnaBridge 126:abea610beb85 749 #define __HAL_RCC_DMA2_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2EN))
AnnaBridge 126:abea610beb85 750 #define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSEN))
AnnaBridge 126:abea610beb85 751 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSULPIEN))
AnnaBridge 126:abea610beb85 752 #define __HAL_RCC_GPIOA_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOAEN))
AnnaBridge 126:abea610beb85 753 #define __HAL_RCC_GPIOB_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOBEN))
AnnaBridge 126:abea610beb85 754 #define __HAL_RCC_GPIOC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOCEN))
AnnaBridge 126:abea610beb85 755 #define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN))
AnnaBridge 126:abea610beb85 756 #define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN))
AnnaBridge 126:abea610beb85 757 #define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN))
AnnaBridge 126:abea610beb85 758 #define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN))
AnnaBridge 126:abea610beb85 759 #define __HAL_RCC_GPIOH_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOHEN))
AnnaBridge 126:abea610beb85 760 #define __HAL_RCC_GPIOI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOIEN))
<> 139:856d2700e60b 761 #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\
<> 139:856d2700e60b 762 defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
AnnaBridge 126:abea610beb85 763 #define __HAL_RCC_GPIOJ_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOJEN))
AnnaBridge 126:abea610beb85 764 #define __HAL_RCC_GPIOK_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOKEN))
<> 139:856d2700e60b 765 #define __HAL_RCC_DMA2D_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2DEN))
<> 139:856d2700e60b 766 #endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
<> 139:856d2700e60b 767
<> 139:856d2700e60b 768 #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\
<> 139:856d2700e60b 769 defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
AnnaBridge 126:abea610beb85 770 /**
AnnaBridge 126:abea610beb85 771 * @brief Enable ETHERNET clock.
AnnaBridge 126:abea610beb85 772 */
AnnaBridge 126:abea610beb85 773 #define __HAL_RCC_ETHMAC_CLK_ENABLE() do { \
AnnaBridge 126:abea610beb85 774 __IO uint32_t tmpreg; \
AnnaBridge 126:abea610beb85 775 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\
AnnaBridge 126:abea610beb85 776 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 126:abea610beb85 777 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\
AnnaBridge 126:abea610beb85 778 UNUSED(tmpreg); \
AnnaBridge 126:abea610beb85 779 } while(0)
AnnaBridge 126:abea610beb85 780
AnnaBridge 126:abea610beb85 781 #define __HAL_RCC_ETHMACTX_CLK_ENABLE() do { \
AnnaBridge 126:abea610beb85 782 __IO uint32_t tmpreg; \
AnnaBridge 126:abea610beb85 783 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\
AnnaBridge 126:abea610beb85 784 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 126:abea610beb85 785 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\
AnnaBridge 126:abea610beb85 786 UNUSED(tmpreg); \
AnnaBridge 126:abea610beb85 787 } while(0)
AnnaBridge 126:abea610beb85 788
AnnaBridge 126:abea610beb85 789 #define __HAL_RCC_ETHMACRX_CLK_ENABLE() do { \
AnnaBridge 126:abea610beb85 790 __IO uint32_t tmpreg; \
AnnaBridge 126:abea610beb85 791 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\
AnnaBridge 126:abea610beb85 792 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 126:abea610beb85 793 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\
AnnaBridge 126:abea610beb85 794 UNUSED(tmpreg); \
AnnaBridge 126:abea610beb85 795 } while(0)
AnnaBridge 126:abea610beb85 796
AnnaBridge 126:abea610beb85 797 #define __HAL_RCC_ETHMACPTP_CLK_ENABLE() do { \
AnnaBridge 126:abea610beb85 798 __IO uint32_t tmpreg; \
AnnaBridge 126:abea610beb85 799 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\
AnnaBridge 126:abea610beb85 800 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 126:abea610beb85 801 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\
AnnaBridge 126:abea610beb85 802 UNUSED(tmpreg); \
AnnaBridge 126:abea610beb85 803 } while(0)
AnnaBridge 126:abea610beb85 804
AnnaBridge 126:abea610beb85 805 #define __HAL_RCC_ETH_CLK_ENABLE() do { \
AnnaBridge 126:abea610beb85 806 __HAL_RCC_ETHMAC_CLK_ENABLE(); \
AnnaBridge 126:abea610beb85 807 __HAL_RCC_ETHMACTX_CLK_ENABLE(); \
AnnaBridge 126:abea610beb85 808 __HAL_RCC_ETHMACRX_CLK_ENABLE(); \
AnnaBridge 126:abea610beb85 809 } while(0)
AnnaBridge 126:abea610beb85 810 /**
AnnaBridge 126:abea610beb85 811 * @brief Disable ETHERNET clock.
AnnaBridge 126:abea610beb85 812 */
AnnaBridge 126:abea610beb85 813 #define __HAL_RCC_ETHMAC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACEN))
AnnaBridge 126:abea610beb85 814 #define __HAL_RCC_ETHMACTX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACTXEN))
AnnaBridge 126:abea610beb85 815 #define __HAL_RCC_ETHMACRX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACRXEN))
AnnaBridge 126:abea610beb85 816 #define __HAL_RCC_ETHMACPTP_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACPTPEN))
AnnaBridge 126:abea610beb85 817 #define __HAL_RCC_ETH_CLK_DISABLE() do { \
AnnaBridge 126:abea610beb85 818 __HAL_RCC_ETHMACTX_CLK_DISABLE(); \
AnnaBridge 126:abea610beb85 819 __HAL_RCC_ETHMACRX_CLK_DISABLE(); \
AnnaBridge 126:abea610beb85 820 __HAL_RCC_ETHMAC_CLK_DISABLE(); \
AnnaBridge 126:abea610beb85 821 } while(0)
<> 139:856d2700e60b 822 #endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
AnnaBridge 126:abea610beb85 823
AnnaBridge 126:abea610beb85 824 /** @brief Enable or disable the AHB2 peripheral clock.
AnnaBridge 126:abea610beb85 825 * @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge 126:abea610beb85 826 * is disabled and the application software has to enable this clock before
AnnaBridge 126:abea610beb85 827 * using it.
AnnaBridge 126:abea610beb85 828 */
<> 139:856d2700e60b 829 #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\
<> 139:856d2700e60b 830 defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
AnnaBridge 126:abea610beb85 831 #define __HAL_RCC_DCMI_CLK_ENABLE() do { \
AnnaBridge 126:abea610beb85 832 __IO uint32_t tmpreg; \
AnnaBridge 126:abea610beb85 833 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
AnnaBridge 126:abea610beb85 834 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 126:abea610beb85 835 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
AnnaBridge 126:abea610beb85 836 UNUSED(tmpreg); \
AnnaBridge 126:abea610beb85 837 } while(0)
<> 139:856d2700e60b 838 #define __HAL_RCC_DCMI_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN))
<> 139:856d2700e60b 839 #endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
AnnaBridge 126:abea610beb85 840
AnnaBridge 126:abea610beb85 841 #if defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
AnnaBridge 126:abea610beb85 842 #define __HAL_RCC_JPEG_CLK_ENABLE() do { \
AnnaBridge 126:abea610beb85 843 __IO uint32_t tmpreg; \
AnnaBridge 126:abea610beb85 844 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_JPEGEN);\
AnnaBridge 126:abea610beb85 845 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 126:abea610beb85 846 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_JPEGEN);\
AnnaBridge 126:abea610beb85 847 UNUSED(tmpreg); \
AnnaBridge 126:abea610beb85 848 } while(0)
AnnaBridge 126:abea610beb85 849 #define __HAL_RCC_JPEG_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_JPEGEN))
AnnaBridge 126:abea610beb85 850 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
AnnaBridge 126:abea610beb85 851
AnnaBridge 126:abea610beb85 852 #define __HAL_RCC_RNG_CLK_ENABLE() do { \
AnnaBridge 126:abea610beb85 853 __IO uint32_t tmpreg; \
AnnaBridge 126:abea610beb85 854 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
AnnaBridge 126:abea610beb85 855 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 126:abea610beb85 856 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
AnnaBridge 126:abea610beb85 857 UNUSED(tmpreg); \
AnnaBridge 126:abea610beb85 858 } while(0)
AnnaBridge 126:abea610beb85 859
AnnaBridge 126:abea610beb85 860 #define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do { \
AnnaBridge 126:abea610beb85 861 __IO uint32_t tmpreg; \
AnnaBridge 126:abea610beb85 862 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN);\
AnnaBridge 126:abea610beb85 863 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 126:abea610beb85 864 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN);\
AnnaBridge 126:abea610beb85 865 UNUSED(tmpreg); \
AnnaBridge 126:abea610beb85 866 __HAL_RCC_SYSCFG_CLK_ENABLE();\
AnnaBridge 126:abea610beb85 867 } while(0)
<> 139:856d2700e60b 868
AnnaBridge 126:abea610beb85 869 #define __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN))
AnnaBridge 126:abea610beb85 870
AnnaBridge 126:abea610beb85 871 #define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN))
AnnaBridge 126:abea610beb85 872 #if defined(STM32F756xx) || defined (STM32F777xx) || defined (STM32F779xx)
AnnaBridge 126:abea610beb85 873 #define __HAL_RCC_CRYP_CLK_ENABLE() do { \
AnnaBridge 126:abea610beb85 874 __IO uint32_t tmpreg; \
AnnaBridge 126:abea610beb85 875 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
AnnaBridge 126:abea610beb85 876 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 126:abea610beb85 877 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
AnnaBridge 126:abea610beb85 878 UNUSED(tmpreg); \
AnnaBridge 126:abea610beb85 879 } while(0)
AnnaBridge 126:abea610beb85 880
AnnaBridge 126:abea610beb85 881 #define __HAL_RCC_HASH_CLK_ENABLE() do { \
AnnaBridge 126:abea610beb85 882 __IO uint32_t tmpreg; \
AnnaBridge 126:abea610beb85 883 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\
AnnaBridge 126:abea610beb85 884 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 126:abea610beb85 885 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\
AnnaBridge 126:abea610beb85 886 UNUSED(tmpreg); \
AnnaBridge 126:abea610beb85 887 } while(0)
AnnaBridge 126:abea610beb85 888
AnnaBridge 126:abea610beb85 889 #define __HAL_RCC_CRYP_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_CRYPEN))
AnnaBridge 126:abea610beb85 890 #define __HAL_RCC_HASH_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_HASHEN))
AnnaBridge 126:abea610beb85 891 #endif /* STM32F756x || STM32F777xx || STM32F779xx */
AnnaBridge 126:abea610beb85 892
<> 139:856d2700e60b 893 #if defined(STM32F732xx) || defined (STM32F733xx)
<> 139:856d2700e60b 894 #define __HAL_RCC_AES_CLK_ENABLE() do { \
<> 139:856d2700e60b 895 __IO uint32_t tmpreg; \
<> 139:856d2700e60b 896 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN);\
<> 139:856d2700e60b 897 /* Delay after an RCC peripheral clock enabling */ \
<> 139:856d2700e60b 898 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN);\
<> 139:856d2700e60b 899 UNUSED(tmpreg); \
<> 139:856d2700e60b 900 } while(0)
<> 139:856d2700e60b 901
<> 139:856d2700e60b 902 #define __HAL_RCC_AES_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_AESEN))
<> 139:856d2700e60b 903 #endif /* STM32F732xx || STM32F733xx */
<> 139:856d2700e60b 904
AnnaBridge 126:abea610beb85 905 /** @brief Enables or disables the AHB3 peripheral clock.
AnnaBridge 126:abea610beb85 906 * @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge 126:abea610beb85 907 * is disabled and the application software has to enable this clock before
AnnaBridge 126:abea610beb85 908 * using it.
AnnaBridge 126:abea610beb85 909 */
AnnaBridge 126:abea610beb85 910 #define __HAL_RCC_FMC_CLK_ENABLE() do { \
AnnaBridge 126:abea610beb85 911 __IO uint32_t tmpreg; \
AnnaBridge 126:abea610beb85 912 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\
AnnaBridge 126:abea610beb85 913 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 126:abea610beb85 914 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\
AnnaBridge 126:abea610beb85 915 UNUSED(tmpreg); \
AnnaBridge 126:abea610beb85 916 } while(0)
AnnaBridge 126:abea610beb85 917
AnnaBridge 126:abea610beb85 918 #define __HAL_RCC_QSPI_CLK_ENABLE() do { \
AnnaBridge 126:abea610beb85 919 __IO uint32_t tmpreg; \
AnnaBridge 126:abea610beb85 920 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
AnnaBridge 126:abea610beb85 921 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 126:abea610beb85 922 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
AnnaBridge 126:abea610beb85 923 UNUSED(tmpreg); \
AnnaBridge 126:abea610beb85 924 } while(0)
AnnaBridge 126:abea610beb85 925
AnnaBridge 126:abea610beb85 926 #define __HAL_RCC_FMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FMCEN))
AnnaBridge 126:abea610beb85 927 #define __HAL_RCC_QSPI_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_QSPIEN))
AnnaBridge 126:abea610beb85 928
AnnaBridge 126:abea610beb85 929 /** @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
AnnaBridge 126:abea610beb85 930 * @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge 126:abea610beb85 931 * is disabled and the application software has to enable this clock before
AnnaBridge 126:abea610beb85 932 * using it.
AnnaBridge 126:abea610beb85 933 */
AnnaBridge 126:abea610beb85 934 #define __HAL_RCC_TIM2_CLK_ENABLE() do { \
AnnaBridge 126:abea610beb85 935 __IO uint32_t tmpreg; \
AnnaBridge 126:abea610beb85 936 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
AnnaBridge 126:abea610beb85 937 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 126:abea610beb85 938 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
AnnaBridge 126:abea610beb85 939 UNUSED(tmpreg); \
AnnaBridge 126:abea610beb85 940 } while(0)
AnnaBridge 126:abea610beb85 941
AnnaBridge 126:abea610beb85 942 #define __HAL_RCC_TIM3_CLK_ENABLE() do { \
AnnaBridge 126:abea610beb85 943 __IO uint32_t tmpreg; \
AnnaBridge 126:abea610beb85 944 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
AnnaBridge 126:abea610beb85 945 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 126:abea610beb85 946 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
AnnaBridge 126:abea610beb85 947 UNUSED(tmpreg); \
AnnaBridge 126:abea610beb85 948 } while(0)
AnnaBridge 126:abea610beb85 949
AnnaBridge 126:abea610beb85 950 #define __HAL_RCC_TIM4_CLK_ENABLE() do { \
AnnaBridge 126:abea610beb85 951 __IO uint32_t tmpreg; \
AnnaBridge 126:abea610beb85 952 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
AnnaBridge 126:abea610beb85 953 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 126:abea610beb85 954 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
AnnaBridge 126:abea610beb85 955 UNUSED(tmpreg); \
AnnaBridge 126:abea610beb85 956 } while(0)
AnnaBridge 126:abea610beb85 957
AnnaBridge 126:abea610beb85 958 #define __HAL_RCC_TIM5_CLK_ENABLE() do { \
AnnaBridge 126:abea610beb85 959 __IO uint32_t tmpreg; \
AnnaBridge 126:abea610beb85 960 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
AnnaBridge 126:abea610beb85 961 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 126:abea610beb85 962 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
AnnaBridge 126:abea610beb85 963 UNUSED(tmpreg); \
AnnaBridge 126:abea610beb85 964 } while(0)
AnnaBridge 126:abea610beb85 965
AnnaBridge 126:abea610beb85 966 #define __HAL_RCC_TIM6_CLK_ENABLE() do { \
AnnaBridge 126:abea610beb85 967 __IO uint32_t tmpreg; \
AnnaBridge 126:abea610beb85 968 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
AnnaBridge 126:abea610beb85 969 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 126:abea610beb85 970 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
AnnaBridge 126:abea610beb85 971 UNUSED(tmpreg); \
AnnaBridge 126:abea610beb85 972 } while(0)
AnnaBridge 126:abea610beb85 973
AnnaBridge 126:abea610beb85 974 #define __HAL_RCC_TIM7_CLK_ENABLE() do { \
AnnaBridge 126:abea610beb85 975 __IO uint32_t tmpreg; \
AnnaBridge 126:abea610beb85 976 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
AnnaBridge 126:abea610beb85 977 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 126:abea610beb85 978 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
AnnaBridge 126:abea610beb85 979 UNUSED(tmpreg); \
AnnaBridge 126:abea610beb85 980 } while(0)
AnnaBridge 126:abea610beb85 981
AnnaBridge 126:abea610beb85 982 #define __HAL_RCC_TIM12_CLK_ENABLE() do { \
AnnaBridge 126:abea610beb85 983 __IO uint32_t tmpreg; \
AnnaBridge 126:abea610beb85 984 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
AnnaBridge 126:abea610beb85 985 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 126:abea610beb85 986 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
AnnaBridge 126:abea610beb85 987 UNUSED(tmpreg); \
AnnaBridge 126:abea610beb85 988 } while(0)
AnnaBridge 126:abea610beb85 989
AnnaBridge 126:abea610beb85 990 #define __HAL_RCC_TIM13_CLK_ENABLE() do { \
AnnaBridge 126:abea610beb85 991 __IO uint32_t tmpreg; \
AnnaBridge 126:abea610beb85 992 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
AnnaBridge 126:abea610beb85 993 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 126:abea610beb85 994 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
AnnaBridge 126:abea610beb85 995 UNUSED(tmpreg); \
AnnaBridge 126:abea610beb85 996 } while(0)
AnnaBridge 126:abea610beb85 997
AnnaBridge 126:abea610beb85 998 #define __HAL_RCC_TIM14_CLK_ENABLE() do { \
AnnaBridge 126:abea610beb85 999 __IO uint32_t tmpreg; \
AnnaBridge 126:abea610beb85 1000 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
AnnaBridge 126:abea610beb85 1001 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 126:abea610beb85 1002 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
AnnaBridge 126:abea610beb85 1003 UNUSED(tmpreg); \
AnnaBridge 126:abea610beb85 1004 } while(0)
AnnaBridge 126:abea610beb85 1005
AnnaBridge 126:abea610beb85 1006 #define __HAL_RCC_LPTIM1_CLK_ENABLE() do { \
AnnaBridge 126:abea610beb85 1007 __IO uint32_t tmpreg; \
AnnaBridge 126:abea610beb85 1008 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN);\
AnnaBridge 126:abea610beb85 1009 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 126:abea610beb85 1010 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN);\
AnnaBridge 126:abea610beb85 1011 UNUSED(tmpreg); \
AnnaBridge 126:abea610beb85 1012 } while(0)
AnnaBridge 126:abea610beb85 1013
<> 139:856d2700e60b 1014 #if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) ||\
<> 139:856d2700e60b 1015 defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) ||\
<> 139:856d2700e60b 1016 defined (STM32F779xx)
AnnaBridge 126:abea610beb85 1017 #define __HAL_RCC_RTC_CLK_ENABLE() do { \
AnnaBridge 126:abea610beb85 1018 __IO uint32_t tmpreg; \
AnnaBridge 126:abea610beb85 1019 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_RTCEN);\
AnnaBridge 126:abea610beb85 1020 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 126:abea610beb85 1021 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_RTCEN);\
AnnaBridge 126:abea610beb85 1022 UNUSED(tmpreg); \
AnnaBridge 126:abea610beb85 1023 } while(0)
<> 139:856d2700e60b 1024 #endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx ||
<> 139:856d2700e60b 1025 STM32F769xx || STM32F777xx || STM32F779xx */
<> 139:856d2700e60b 1026
<> 139:856d2700e60b 1027 #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
AnnaBridge 126:abea610beb85 1028 #define __HAL_RCC_CAN3_CLK_ENABLE() do { \
AnnaBridge 126:abea610beb85 1029 __IO uint32_t tmpreg; \
AnnaBridge 126:abea610beb85 1030 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN3EN);\
AnnaBridge 126:abea610beb85 1031 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 126:abea610beb85 1032 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN3EN);\
AnnaBridge 126:abea610beb85 1033 UNUSED(tmpreg); \
AnnaBridge 126:abea610beb85 1034 } while(0)
AnnaBridge 126:abea610beb85 1035 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
AnnaBridge 126:abea610beb85 1036
AnnaBridge 126:abea610beb85 1037 #define __HAL_RCC_SPI2_CLK_ENABLE() do { \
AnnaBridge 126:abea610beb85 1038 __IO uint32_t tmpreg; \
AnnaBridge 126:abea610beb85 1039 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
AnnaBridge 126:abea610beb85 1040 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 126:abea610beb85 1041 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
AnnaBridge 126:abea610beb85 1042 UNUSED(tmpreg); \
AnnaBridge 126:abea610beb85 1043 } while(0)
AnnaBridge 126:abea610beb85 1044
AnnaBridge 126:abea610beb85 1045 #define __HAL_RCC_SPI3_CLK_ENABLE() do { \
AnnaBridge 126:abea610beb85 1046 __IO uint32_t tmpreg; \
AnnaBridge 126:abea610beb85 1047 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
AnnaBridge 126:abea610beb85 1048 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 126:abea610beb85 1049 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
AnnaBridge 126:abea610beb85 1050 UNUSED(tmpreg); \
AnnaBridge 126:abea610beb85 1051 } while(0)
AnnaBridge 126:abea610beb85 1052
AnnaBridge 126:abea610beb85 1053 #define __HAL_RCC_USART2_CLK_ENABLE() do { \
AnnaBridge 126:abea610beb85 1054 __IO uint32_t tmpreg; \
AnnaBridge 126:abea610beb85 1055 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
AnnaBridge 126:abea610beb85 1056 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 126:abea610beb85 1057 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
AnnaBridge 126:abea610beb85 1058 UNUSED(tmpreg); \
AnnaBridge 126:abea610beb85 1059 } while(0)
AnnaBridge 126:abea610beb85 1060
AnnaBridge 126:abea610beb85 1061 #define __HAL_RCC_USART3_CLK_ENABLE() do { \
AnnaBridge 126:abea610beb85 1062 __IO uint32_t tmpreg; \
AnnaBridge 126:abea610beb85 1063 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
AnnaBridge 126:abea610beb85 1064 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 126:abea610beb85 1065 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
AnnaBridge 126:abea610beb85 1066 UNUSED(tmpreg); \
AnnaBridge 126:abea610beb85 1067 } while(0)
AnnaBridge 126:abea610beb85 1068
AnnaBridge 126:abea610beb85 1069 #define __HAL_RCC_UART4_CLK_ENABLE() do { \
AnnaBridge 126:abea610beb85 1070 __IO uint32_t tmpreg; \
AnnaBridge 126:abea610beb85 1071 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
AnnaBridge 126:abea610beb85 1072 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 126:abea610beb85 1073 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
AnnaBridge 126:abea610beb85 1074 UNUSED(tmpreg); \
AnnaBridge 126:abea610beb85 1075 } while(0)
AnnaBridge 126:abea610beb85 1076
AnnaBridge 126:abea610beb85 1077 #define __HAL_RCC_UART5_CLK_ENABLE() do { \
AnnaBridge 126:abea610beb85 1078 __IO uint32_t tmpreg; \
AnnaBridge 126:abea610beb85 1079 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
AnnaBridge 126:abea610beb85 1080 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 126:abea610beb85 1081 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
AnnaBridge 126:abea610beb85 1082 UNUSED(tmpreg); \
AnnaBridge 126:abea610beb85 1083 } while(0)
AnnaBridge 126:abea610beb85 1084
AnnaBridge 126:abea610beb85 1085 #define __HAL_RCC_I2C1_CLK_ENABLE() do { \
AnnaBridge 126:abea610beb85 1086 __IO uint32_t tmpreg; \
AnnaBridge 126:abea610beb85 1087 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
AnnaBridge 126:abea610beb85 1088 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 126:abea610beb85 1089 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
AnnaBridge 126:abea610beb85 1090 UNUSED(tmpreg); \
AnnaBridge 126:abea610beb85 1091 } while(0)
AnnaBridge 126:abea610beb85 1092
AnnaBridge 126:abea610beb85 1093 #define __HAL_RCC_I2C2_CLK_ENABLE() do { \
AnnaBridge 126:abea610beb85 1094 __IO uint32_t tmpreg; \
AnnaBridge 126:abea610beb85 1095 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
AnnaBridge 126:abea610beb85 1096 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 126:abea610beb85 1097 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
AnnaBridge 126:abea610beb85 1098 UNUSED(tmpreg); \
AnnaBridge 126:abea610beb85 1099 } while(0)
AnnaBridge 126:abea610beb85 1100
AnnaBridge 126:abea610beb85 1101 #define __HAL_RCC_I2C3_CLK_ENABLE() do { \
AnnaBridge 126:abea610beb85 1102 __IO uint32_t tmpreg; \
AnnaBridge 126:abea610beb85 1103 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
AnnaBridge 126:abea610beb85 1104 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 126:abea610beb85 1105 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
AnnaBridge 126:abea610beb85 1106 UNUSED(tmpreg); \
AnnaBridge 126:abea610beb85 1107 } while(0)
<> 139:856d2700e60b 1108
AnnaBridge 126:abea610beb85 1109 #define __HAL_RCC_CAN1_CLK_ENABLE() do { \
AnnaBridge 126:abea610beb85 1110 __IO uint32_t tmpreg; \
AnnaBridge 126:abea610beb85 1111 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
AnnaBridge 126:abea610beb85 1112 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 126:abea610beb85 1113 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
AnnaBridge 126:abea610beb85 1114 UNUSED(tmpreg); \
AnnaBridge 126:abea610beb85 1115 } while(0)
AnnaBridge 126:abea610beb85 1116
AnnaBridge 126:abea610beb85 1117 #define __HAL_RCC_DAC_CLK_ENABLE() do { \
AnnaBridge 126:abea610beb85 1118 __IO uint32_t tmpreg; \
AnnaBridge 126:abea610beb85 1119 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
AnnaBridge 126:abea610beb85 1120 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 126:abea610beb85 1121 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
AnnaBridge 126:abea610beb85 1122 UNUSED(tmpreg); \
AnnaBridge 126:abea610beb85 1123 } while(0)
AnnaBridge 126:abea610beb85 1124
AnnaBridge 126:abea610beb85 1125 #define __HAL_RCC_UART7_CLK_ENABLE() do { \
AnnaBridge 126:abea610beb85 1126 __IO uint32_t tmpreg; \
AnnaBridge 126:abea610beb85 1127 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN);\
AnnaBridge 126:abea610beb85 1128 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 126:abea610beb85 1129 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN);\
AnnaBridge 126:abea610beb85 1130 UNUSED(tmpreg); \
AnnaBridge 126:abea610beb85 1131 } while(0)
AnnaBridge 126:abea610beb85 1132
AnnaBridge 126:abea610beb85 1133 #define __HAL_RCC_UART8_CLK_ENABLE() do { \
AnnaBridge 126:abea610beb85 1134 __IO uint32_t tmpreg; \
AnnaBridge 126:abea610beb85 1135 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN);\
AnnaBridge 126:abea610beb85 1136 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 126:abea610beb85 1137 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN);\
AnnaBridge 126:abea610beb85 1138 UNUSED(tmpreg); \
AnnaBridge 126:abea610beb85 1139 } while(0)
<> 139:856d2700e60b 1140
<> 139:856d2700e60b 1141 #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\
<> 139:856d2700e60b 1142 defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
<> 139:856d2700e60b 1143 #define __HAL_RCC_SPDIFRX_CLK_ENABLE() do { \
<> 139:856d2700e60b 1144 __IO uint32_t tmpreg; \
<> 139:856d2700e60b 1145 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPDIFRXEN);\
<> 139:856d2700e60b 1146 /* Delay after an RCC peripheral clock enabling */ \
<> 139:856d2700e60b 1147 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPDIFRXEN);\
<> 139:856d2700e60b 1148 UNUSED(tmpreg); \
<> 139:856d2700e60b 1149 } while(0)
<> 139:856d2700e60b 1150
<> 139:856d2700e60b 1151 #define __HAL_RCC_I2C4_CLK_ENABLE() do { \
<> 139:856d2700e60b 1152 __IO uint32_t tmpreg; \
<> 139:856d2700e60b 1153 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C4EN);\
<> 139:856d2700e60b 1154 /* Delay after an RCC peripheral clock enabling */ \
<> 139:856d2700e60b 1155 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C4EN);\
<> 139:856d2700e60b 1156 UNUSED(tmpreg); \
<> 139:856d2700e60b 1157 } while(0)
<> 139:856d2700e60b 1158
<> 139:856d2700e60b 1159 #define __HAL_RCC_CAN2_CLK_ENABLE() do { \
<> 139:856d2700e60b 1160 __IO uint32_t tmpreg; \
<> 139:856d2700e60b 1161 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
<> 139:856d2700e60b 1162 /* Delay after an RCC peripheral clock enabling */ \
<> 139:856d2700e60b 1163 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
<> 139:856d2700e60b 1164 UNUSED(tmpreg); \
<> 139:856d2700e60b 1165 } while(0)
<> 139:856d2700e60b 1166
<> 139:856d2700e60b 1167 #define __HAL_RCC_CEC_CLK_ENABLE() do { \
<> 139:856d2700e60b 1168 __IO uint32_t tmpreg; \
<> 139:856d2700e60b 1169 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\
<> 139:856d2700e60b 1170 /* Delay after an RCC peripheral clock enabling */ \
<> 139:856d2700e60b 1171 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\
<> 139:856d2700e60b 1172 UNUSED(tmpreg); \
<> 139:856d2700e60b 1173 } while(0)
<> 139:856d2700e60b 1174 #endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
AnnaBridge 126:abea610beb85 1175
AnnaBridge 126:abea610beb85 1176 #define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
AnnaBridge 126:abea610beb85 1177 #define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
AnnaBridge 126:abea610beb85 1178 #define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
AnnaBridge 126:abea610beb85 1179 #define __HAL_RCC_TIM5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN))
AnnaBridge 126:abea610beb85 1180 #define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
AnnaBridge 126:abea610beb85 1181 #define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
AnnaBridge 126:abea610beb85 1182 #define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
AnnaBridge 126:abea610beb85 1183 #define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
AnnaBridge 126:abea610beb85 1184 #define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
AnnaBridge 126:abea610beb85 1185 #define __HAL_RCC_LPTIM1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_LPTIM1EN))
<> 139:856d2700e60b 1186 #if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) ||\
<> 139:856d2700e60b 1187 defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) ||\
<> 139:856d2700e60b 1188 defined (STM32F779xx)
<> 139:856d2700e60b 1189 #define __HAL_RCC_RTC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_RTCEN))
<> 139:856d2700e60b 1190 #endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx ||
<> 139:856d2700e60b 1191 STM32F769xx || STM32F777xx || STM32F779xx */
AnnaBridge 126:abea610beb85 1192 #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
AnnaBridge 126:abea610beb85 1193 #define __HAL_RCC_CAN3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN3EN))
AnnaBridge 126:abea610beb85 1194 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
AnnaBridge 126:abea610beb85 1195 #define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))
AnnaBridge 126:abea610beb85 1196 #define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
AnnaBridge 126:abea610beb85 1197 #define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))
AnnaBridge 126:abea610beb85 1198 #define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
AnnaBridge 126:abea610beb85 1199 #define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
AnnaBridge 126:abea610beb85 1200 #define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
AnnaBridge 126:abea610beb85 1201 #define __HAL_RCC_I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))
AnnaBridge 126:abea610beb85 1202 #define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
AnnaBridge 126:abea610beb85 1203 #define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
AnnaBridge 126:abea610beb85 1204 #define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN))
AnnaBridge 126:abea610beb85 1205 #define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
AnnaBridge 126:abea610beb85 1206 #define __HAL_RCC_UART7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART7EN))
AnnaBridge 126:abea610beb85 1207 #define __HAL_RCC_UART8_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART8EN))
<> 139:856d2700e60b 1208 #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\
<> 139:856d2700e60b 1209 defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
<> 139:856d2700e60b 1210 #define __HAL_RCC_SPDIFRX_CLK_DISABLE()(RCC->APB1ENR &= ~(RCC_APB1ENR_SPDIFRXEN))
<> 139:856d2700e60b 1211 #define __HAL_RCC_I2C4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C4EN))
<> 139:856d2700e60b 1212 #define __HAL_RCC_CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN))
<> 139:856d2700e60b 1213 #define __HAL_RCC_CEC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CECEN))
<> 139:856d2700e60b 1214 #endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
AnnaBridge 126:abea610beb85 1215
AnnaBridge 126:abea610beb85 1216 /** @brief Enable or disable the High Speed APB (APB2) peripheral clock.
AnnaBridge 126:abea610beb85 1217 * @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge 126:abea610beb85 1218 * is disabled and the application software has to enable this clock before
AnnaBridge 126:abea610beb85 1219 * using it.
AnnaBridge 126:abea610beb85 1220 */
AnnaBridge 126:abea610beb85 1221 #define __HAL_RCC_TIM1_CLK_ENABLE() do { \
AnnaBridge 126:abea610beb85 1222 __IO uint32_t tmpreg; \
AnnaBridge 126:abea610beb85 1223 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
AnnaBridge 126:abea610beb85 1224 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 126:abea610beb85 1225 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
AnnaBridge 126:abea610beb85 1226 UNUSED(tmpreg); \
AnnaBridge 126:abea610beb85 1227 } while(0)
AnnaBridge 126:abea610beb85 1228
AnnaBridge 126:abea610beb85 1229 #define __HAL_RCC_TIM8_CLK_ENABLE() do { \
AnnaBridge 126:abea610beb85 1230 __IO uint32_t tmpreg; \
AnnaBridge 126:abea610beb85 1231 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
AnnaBridge 126:abea610beb85 1232 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 126:abea610beb85 1233 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
AnnaBridge 126:abea610beb85 1234 UNUSED(tmpreg); \
AnnaBridge 126:abea610beb85 1235 } while(0)
AnnaBridge 126:abea610beb85 1236
AnnaBridge 126:abea610beb85 1237 #define __HAL_RCC_USART1_CLK_ENABLE() do { \
AnnaBridge 126:abea610beb85 1238 __IO uint32_t tmpreg; \
AnnaBridge 126:abea610beb85 1239 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
AnnaBridge 126:abea610beb85 1240 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 126:abea610beb85 1241 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
AnnaBridge 126:abea610beb85 1242 UNUSED(tmpreg); \
AnnaBridge 126:abea610beb85 1243 } while(0)
AnnaBridge 126:abea610beb85 1244
AnnaBridge 126:abea610beb85 1245 #define __HAL_RCC_USART6_CLK_ENABLE() do { \
AnnaBridge 126:abea610beb85 1246 __IO uint32_t tmpreg; \
AnnaBridge 126:abea610beb85 1247 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\
AnnaBridge 126:abea610beb85 1248 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 126:abea610beb85 1249 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\
AnnaBridge 126:abea610beb85 1250 UNUSED(tmpreg); \
AnnaBridge 126:abea610beb85 1251 } while(0)
AnnaBridge 126:abea610beb85 1252
<> 139:856d2700e60b 1253 #if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\
<> 139:856d2700e60b 1254 defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
AnnaBridge 126:abea610beb85 1255 #define __HAL_RCC_SDMMC2_CLK_ENABLE() do { \
AnnaBridge 126:abea610beb85 1256 __IO uint32_t tmpreg; \
AnnaBridge 126:abea610beb85 1257 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC2EN);\
AnnaBridge 126:abea610beb85 1258 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 126:abea610beb85 1259 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC2EN);\
AnnaBridge 126:abea610beb85 1260 UNUSED(tmpreg); \
AnnaBridge 126:abea610beb85 1261 } while(0)
<> 139:856d2700e60b 1262 #endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
AnnaBridge 126:abea610beb85 1263
AnnaBridge 126:abea610beb85 1264 #define __HAL_RCC_ADC1_CLK_ENABLE() do { \
AnnaBridge 126:abea610beb85 1265 __IO uint32_t tmpreg; \
AnnaBridge 126:abea610beb85 1266 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
AnnaBridge 126:abea610beb85 1267 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 126:abea610beb85 1268 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
AnnaBridge 126:abea610beb85 1269 UNUSED(tmpreg); \
AnnaBridge 126:abea610beb85 1270 } while(0)
AnnaBridge 126:abea610beb85 1271
AnnaBridge 126:abea610beb85 1272 #define __HAL_RCC_ADC2_CLK_ENABLE() do { \
AnnaBridge 126:abea610beb85 1273 __IO uint32_t tmpreg; \
AnnaBridge 126:abea610beb85 1274 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
AnnaBridge 126:abea610beb85 1275 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 126:abea610beb85 1276 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
AnnaBridge 126:abea610beb85 1277 UNUSED(tmpreg); \
AnnaBridge 126:abea610beb85 1278 } while(0)
AnnaBridge 126:abea610beb85 1279
AnnaBridge 126:abea610beb85 1280 #define __HAL_RCC_ADC3_CLK_ENABLE() do { \
AnnaBridge 126:abea610beb85 1281 __IO uint32_t tmpreg; \
AnnaBridge 126:abea610beb85 1282 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
AnnaBridge 126:abea610beb85 1283 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 126:abea610beb85 1284 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
AnnaBridge 126:abea610beb85 1285 UNUSED(tmpreg); \
AnnaBridge 126:abea610beb85 1286 } while(0)
AnnaBridge 126:abea610beb85 1287
AnnaBridge 126:abea610beb85 1288 #define __HAL_RCC_SDMMC1_CLK_ENABLE() do { \
AnnaBridge 126:abea610beb85 1289 __IO uint32_t tmpreg; \
AnnaBridge 126:abea610beb85 1290 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN);\
AnnaBridge 126:abea610beb85 1291 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 126:abea610beb85 1292 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN);\
AnnaBridge 126:abea610beb85 1293 UNUSED(tmpreg); \
AnnaBridge 126:abea610beb85 1294 } while(0)
AnnaBridge 126:abea610beb85 1295
AnnaBridge 126:abea610beb85 1296 #define __HAL_RCC_SPI1_CLK_ENABLE() do { \
AnnaBridge 126:abea610beb85 1297 __IO uint32_t tmpreg; \
AnnaBridge 126:abea610beb85 1298 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
AnnaBridge 126:abea610beb85 1299 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 126:abea610beb85 1300 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
AnnaBridge 126:abea610beb85 1301 UNUSED(tmpreg); \
AnnaBridge 126:abea610beb85 1302 } while(0)
AnnaBridge 126:abea610beb85 1303
AnnaBridge 126:abea610beb85 1304 #define __HAL_RCC_SPI4_CLK_ENABLE() do { \
AnnaBridge 126:abea610beb85 1305 __IO uint32_t tmpreg; \
AnnaBridge 126:abea610beb85 1306 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
AnnaBridge 126:abea610beb85 1307 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 126:abea610beb85 1308 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
AnnaBridge 126:abea610beb85 1309 UNUSED(tmpreg); \
AnnaBridge 126:abea610beb85 1310 } while(0)
AnnaBridge 126:abea610beb85 1311
AnnaBridge 126:abea610beb85 1312 #define __HAL_RCC_TIM9_CLK_ENABLE() do { \
AnnaBridge 126:abea610beb85 1313 __IO uint32_t tmpreg; \
AnnaBridge 126:abea610beb85 1314 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\
AnnaBridge 126:abea610beb85 1315 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 126:abea610beb85 1316 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\
AnnaBridge 126:abea610beb85 1317 UNUSED(tmpreg); \
AnnaBridge 126:abea610beb85 1318 } while(0)
AnnaBridge 126:abea610beb85 1319
AnnaBridge 126:abea610beb85 1320 #define __HAL_RCC_TIM10_CLK_ENABLE() do { \
AnnaBridge 126:abea610beb85 1321 __IO uint32_t tmpreg; \
AnnaBridge 126:abea610beb85 1322 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
AnnaBridge 126:abea610beb85 1323 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 126:abea610beb85 1324 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
AnnaBridge 126:abea610beb85 1325 UNUSED(tmpreg); \
AnnaBridge 126:abea610beb85 1326 } while(0)
AnnaBridge 126:abea610beb85 1327
AnnaBridge 126:abea610beb85 1328 #define __HAL_RCC_TIM11_CLK_ENABLE() do { \
AnnaBridge 126:abea610beb85 1329 __IO uint32_t tmpreg; \
AnnaBridge 126:abea610beb85 1330 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\
AnnaBridge 126:abea610beb85 1331 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 126:abea610beb85 1332 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\
AnnaBridge 126:abea610beb85 1333 UNUSED(tmpreg); \
AnnaBridge 126:abea610beb85 1334 } while(0)
AnnaBridge 126:abea610beb85 1335
AnnaBridge 126:abea610beb85 1336 #define __HAL_RCC_SPI5_CLK_ENABLE() do { \
AnnaBridge 126:abea610beb85 1337 __IO uint32_t tmpreg; \
AnnaBridge 126:abea610beb85 1338 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
AnnaBridge 126:abea610beb85 1339 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 126:abea610beb85 1340 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
AnnaBridge 126:abea610beb85 1341 UNUSED(tmpreg); \
AnnaBridge 126:abea610beb85 1342 } while(0)
AnnaBridge 126:abea610beb85 1343
AnnaBridge 126:abea610beb85 1344 #define __HAL_RCC_SPI6_CLK_ENABLE() do { \
AnnaBridge 126:abea610beb85 1345 __IO uint32_t tmpreg; \
AnnaBridge 126:abea610beb85 1346 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI6EN);\
AnnaBridge 126:abea610beb85 1347 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 126:abea610beb85 1348 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI6EN);\
AnnaBridge 126:abea610beb85 1349 UNUSED(tmpreg); \
AnnaBridge 126:abea610beb85 1350 } while(0)
AnnaBridge 126:abea610beb85 1351
AnnaBridge 126:abea610beb85 1352 #define __HAL_RCC_SAI1_CLK_ENABLE() do { \
AnnaBridge 126:abea610beb85 1353 __IO uint32_t tmpreg; \
AnnaBridge 126:abea610beb85 1354 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
AnnaBridge 126:abea610beb85 1355 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 126:abea610beb85 1356 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
AnnaBridge 126:abea610beb85 1357 UNUSED(tmpreg); \
AnnaBridge 126:abea610beb85 1358 } while(0)
AnnaBridge 126:abea610beb85 1359
AnnaBridge 126:abea610beb85 1360 #define __HAL_RCC_SAI2_CLK_ENABLE() do { \
AnnaBridge 126:abea610beb85 1361 __IO uint32_t tmpreg; \
AnnaBridge 126:abea610beb85 1362 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN);\
AnnaBridge 126:abea610beb85 1363 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 126:abea610beb85 1364 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN);\
AnnaBridge 126:abea610beb85 1365 UNUSED(tmpreg); \
AnnaBridge 126:abea610beb85 1366 } while(0)
AnnaBridge 126:abea610beb85 1367
AnnaBridge 126:abea610beb85 1368 #if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
AnnaBridge 126:abea610beb85 1369 #define __HAL_RCC_LTDC_CLK_ENABLE() do { \
AnnaBridge 126:abea610beb85 1370 __IO uint32_t tmpreg; \
AnnaBridge 126:abea610beb85 1371 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN);\
AnnaBridge 126:abea610beb85 1372 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 126:abea610beb85 1373 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN);\
AnnaBridge 126:abea610beb85 1374 UNUSED(tmpreg); \
AnnaBridge 126:abea610beb85 1375 } while(0)
AnnaBridge 126:abea610beb85 1376 #endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
AnnaBridge 126:abea610beb85 1377
AnnaBridge 126:abea610beb85 1378 #if defined (STM32F769xx) || defined (STM32F779xx)
AnnaBridge 126:abea610beb85 1379 #define __HAL_RCC_DSI_CLK_ENABLE() do { \
AnnaBridge 126:abea610beb85 1380 __IO uint32_t tmpreg; \
AnnaBridge 126:abea610beb85 1381 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN);\
AnnaBridge 126:abea610beb85 1382 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 126:abea610beb85 1383 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN);\
AnnaBridge 126:abea610beb85 1384 UNUSED(tmpreg); \
AnnaBridge 126:abea610beb85 1385 } while(0)
AnnaBridge 126:abea610beb85 1386 #endif /* STM32F769xx || STM32F779xx */
AnnaBridge 126:abea610beb85 1387
AnnaBridge 126:abea610beb85 1388 #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
AnnaBridge 126:abea610beb85 1389 #define __HAL_RCC_DFSDM1_CLK_ENABLE() do { \
AnnaBridge 126:abea610beb85 1390 __IO uint32_t tmpreg; \
AnnaBridge 126:abea610beb85 1391 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN);\
AnnaBridge 126:abea610beb85 1392 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 126:abea610beb85 1393 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN);\
AnnaBridge 126:abea610beb85 1394 UNUSED(tmpreg); \
AnnaBridge 126:abea610beb85 1395 } while(0)
AnnaBridge 126:abea610beb85 1396
AnnaBridge 126:abea610beb85 1397 #define __HAL_RCC_MDIO_CLK_ENABLE() do { \
AnnaBridge 126:abea610beb85 1398 __IO uint32_t tmpreg; \
AnnaBridge 126:abea610beb85 1399 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_MDIOEN);\
AnnaBridge 126:abea610beb85 1400 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 126:abea610beb85 1401 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_MDIOEN);\
AnnaBridge 126:abea610beb85 1402 UNUSED(tmpreg); \
AnnaBridge 126:abea610beb85 1403 } while(0)
AnnaBridge 126:abea610beb85 1404 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
<> 139:856d2700e60b 1405 #if defined (STM32F723xx) || defined (STM32F733xx)
<> 139:856d2700e60b 1406 #define __HAL_RCC_OTGPHYC_CLK_ENABLE() do { \
<> 139:856d2700e60b 1407 __IO uint32_t tmpreg; \
<> 139:856d2700e60b 1408 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_OTGPHYCEN);\
<> 139:856d2700e60b 1409 /* Delay after an RCC peripheral clock enabling */ \
<> 139:856d2700e60b 1410 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_OTGPHYCEN);\
<> 139:856d2700e60b 1411 UNUSED(tmpreg); \
<> 139:856d2700e60b 1412 } while(0)
<> 139:856d2700e60b 1413 #endif /* STM32F723xx || STM32F733xx */
AnnaBridge 126:abea610beb85 1414
AnnaBridge 126:abea610beb85 1415 #define __HAL_RCC_TIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN))
AnnaBridge 126:abea610beb85 1416 #define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))
AnnaBridge 126:abea610beb85 1417 #define __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN))
AnnaBridge 126:abea610beb85 1418 #define __HAL_RCC_USART6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART6EN))
<> 139:856d2700e60b 1419 #if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\
<> 139:856d2700e60b 1420 defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
AnnaBridge 126:abea610beb85 1421 #define __HAL_RCC_SDMMC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDMMC2EN))
<> 139:856d2700e60b 1422 #endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
AnnaBridge 126:abea610beb85 1423 #define __HAL_RCC_ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN))
AnnaBridge 126:abea610beb85 1424 #define __HAL_RCC_ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN))
AnnaBridge 126:abea610beb85 1425 #define __HAL_RCC_ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN))
AnnaBridge 126:abea610beb85 1426 #define __HAL_RCC_SDMMC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDMMC1EN))
AnnaBridge 126:abea610beb85 1427 #define __HAL_RCC_SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
AnnaBridge 126:abea610beb85 1428 #define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN))
AnnaBridge 126:abea610beb85 1429 #define __HAL_RCC_TIM9_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM9EN))
AnnaBridge 126:abea610beb85 1430 #define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
AnnaBridge 126:abea610beb85 1431 #define __HAL_RCC_TIM11_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM11EN))
AnnaBridge 126:abea610beb85 1432 #define __HAL_RCC_SPI5_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN))
AnnaBridge 126:abea610beb85 1433 #define __HAL_RCC_SPI6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI6EN))
AnnaBridge 126:abea610beb85 1434 #define __HAL_RCC_SAI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI1EN))
AnnaBridge 126:abea610beb85 1435 #define __HAL_RCC_SAI2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI2EN))
AnnaBridge 126:abea610beb85 1436 #if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
AnnaBridge 126:abea610beb85 1437 #define __HAL_RCC_LTDC_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_LTDCEN))
AnnaBridge 126:abea610beb85 1438 #endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
AnnaBridge 126:abea610beb85 1439 #if defined (STM32F769xx) || defined (STM32F779xx)
AnnaBridge 126:abea610beb85 1440 #define __HAL_RCC_DSI_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_DSIEN))
AnnaBridge 126:abea610beb85 1441 #endif /* STM32F769xx || STM32F779xx */
AnnaBridge 126:abea610beb85 1442 #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
<> 139:856d2700e60b 1443 #define __HAL_RCC_DFSDM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_DFSDM1EN))
<> 139:856d2700e60b 1444 #define __HAL_RCC_MDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_MDIOEN))
AnnaBridge 126:abea610beb85 1445 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
<> 139:856d2700e60b 1446 #if defined (STM32F723xx) || defined (STM32F733xx)
<> 139:856d2700e60b 1447 #define __HAL_RCC_OTGPHYC_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_OTGPHYCEN))
<> 139:856d2700e60b 1448 #endif /* STM32F723xx || STM32F733xx */
AnnaBridge 126:abea610beb85 1449
AnnaBridge 126:abea610beb85 1450 /**
AnnaBridge 126:abea610beb85 1451 * @}
AnnaBridge 126:abea610beb85 1452 */
AnnaBridge 126:abea610beb85 1453
AnnaBridge 126:abea610beb85 1454
AnnaBridge 126:abea610beb85 1455 /** @defgroup RCCEx_Peripheral_Clock_Enable_Disable_Status Peripheral Clock Enable Disable Status
AnnaBridge 126:abea610beb85 1456 * @brief Get the enable or disable status of the AHB/APB peripheral clock.
AnnaBridge 126:abea610beb85 1457 * @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge 126:abea610beb85 1458 * is disabled and the application software has to enable this clock before
AnnaBridge 126:abea610beb85 1459 * using it.
AnnaBridge 126:abea610beb85 1460 * @{
AnnaBridge 126:abea610beb85 1461 */
AnnaBridge 126:abea610beb85 1462
AnnaBridge 126:abea610beb85 1463 /** @brief Get the enable or disable status of the AHB1 peripheral clock.
AnnaBridge 126:abea610beb85 1464 * @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge 126:abea610beb85 1465 * is disabled and the application software has to enable this clock before
AnnaBridge 126:abea610beb85 1466 * using it.
AnnaBridge 126:abea610beb85 1467 */
AnnaBridge 126:abea610beb85 1468 #define __HAL_RCC_BKPSRAM_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) != RESET)
AnnaBridge 126:abea610beb85 1469 #define __HAL_RCC_DTCMRAMEN_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DTCMRAMEN)) != RESET)
AnnaBridge 126:abea610beb85 1470 #define __HAL_RCC_DMA2_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2EN)) != RESET)
AnnaBridge 126:abea610beb85 1471 #define __HAL_RCC_USB_OTG_HS_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) != RESET)
AnnaBridge 126:abea610beb85 1472 #define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) != RESET)
AnnaBridge 126:abea610beb85 1473 #define __HAL_RCC_GPIOA_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOAEN)) != RESET)
AnnaBridge 126:abea610beb85 1474 #define __HAL_RCC_GPIOB_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOBEN)) != RESET)
AnnaBridge 126:abea610beb85 1475 #define __HAL_RCC_GPIOC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOCEN)) != RESET)
AnnaBridge 126:abea610beb85 1476 #define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET)
AnnaBridge 126:abea610beb85 1477 #define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET)
AnnaBridge 126:abea610beb85 1478 #define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) != RESET)
AnnaBridge 126:abea610beb85 1479 #define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) != RESET)
AnnaBridge 126:abea610beb85 1480 #define __HAL_RCC_GPIOH_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOHEN)) != RESET)
AnnaBridge 126:abea610beb85 1481 #define __HAL_RCC_GPIOI_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOIEN)) != RESET)
<> 139:856d2700e60b 1482 #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\
<> 139:856d2700e60b 1483 defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
AnnaBridge 126:abea610beb85 1484 #define __HAL_RCC_GPIOJ_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOJEN)) != RESET)
AnnaBridge 126:abea610beb85 1485 #define __HAL_RCC_GPIOK_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOKEN)) != RESET)
<> 139:856d2700e60b 1486 #define __HAL_RCC_DMA2D_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2DEN)) != RESET)
<> 139:856d2700e60b 1487 #endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
AnnaBridge 126:abea610beb85 1488
AnnaBridge 126:abea610beb85 1489 #define __HAL_RCC_BKPSRAM_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) == RESET)
AnnaBridge 126:abea610beb85 1490 #define __HAL_RCC_DTCMRAMEN_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DTCMRAMEN)) == RESET)
AnnaBridge 126:abea610beb85 1491 #define __HAL_RCC_DMA2_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2EN)) == RESET)
AnnaBridge 126:abea610beb85 1492 #define __HAL_RCC_USB_OTG_HS_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) == RESET)
AnnaBridge 126:abea610beb85 1493 #define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) == RESET)
AnnaBridge 126:abea610beb85 1494 #define __HAL_RCC_GPIOA_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOAEN)) == RESET)
AnnaBridge 126:abea610beb85 1495 #define __HAL_RCC_GPIOB_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOBEN)) == RESET)
AnnaBridge 126:abea610beb85 1496 #define __HAL_RCC_GPIOC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOCEN)) == RESET)
AnnaBridge 126:abea610beb85 1497 #define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET)
AnnaBridge 126:abea610beb85 1498 #define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET)
AnnaBridge 126:abea610beb85 1499 #define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) == RESET)
AnnaBridge 126:abea610beb85 1500 #define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) == RESET)
AnnaBridge 126:abea610beb85 1501 #define __HAL_RCC_GPIOH_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOHEN)) == RESET)
AnnaBridge 126:abea610beb85 1502 #define __HAL_RCC_GPIOI_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOIEN)) == RESET)
<> 139:856d2700e60b 1503 #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\
<> 139:856d2700e60b 1504 defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
AnnaBridge 126:abea610beb85 1505 #define __HAL_RCC_GPIOJ_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOJEN)) == RESET)
AnnaBridge 126:abea610beb85 1506 #define __HAL_RCC_GPIOK_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOKEN)) == RESET)
<> 139:856d2700e60b 1507 #define __HAL_RCC_DMA2D_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2DEN)) == RESET)
<> 139:856d2700e60b 1508 #endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
<> 139:856d2700e60b 1509
<> 139:856d2700e60b 1510 #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\
<> 139:856d2700e60b 1511 defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
AnnaBridge 126:abea610beb85 1512 /**
AnnaBridge 126:abea610beb85 1513 * @brief Enable ETHERNET clock.
AnnaBridge 126:abea610beb85 1514 */
AnnaBridge 126:abea610beb85 1515 #define __HAL_RCC_ETHMAC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACEN)) != RESET)
AnnaBridge 126:abea610beb85 1516 #define __HAL_RCC_ETHMACTX_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACTXEN)) != RESET)
AnnaBridge 126:abea610beb85 1517 #define __HAL_RCC_ETHMACRX_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACRXEN)) != RESET)
AnnaBridge 126:abea610beb85 1518 #define __HAL_RCC_ETHMACPTP_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACPTPEN)) != RESET)
AnnaBridge 126:abea610beb85 1519 #define __HAL_RCC_ETH_IS_CLK_ENABLED() (__HAL_RCC_ETHMAC_IS_CLK_ENABLED() && \
AnnaBridge 126:abea610beb85 1520 __HAL_RCC_ETHMACTX_IS_CLK_ENABLED() && \
AnnaBridge 126:abea610beb85 1521 __HAL_RCC_ETHMACRX_IS_CLK_ENABLED())
AnnaBridge 126:abea610beb85 1522
AnnaBridge 126:abea610beb85 1523 /**
AnnaBridge 126:abea610beb85 1524 * @brief Disable ETHERNET clock.
AnnaBridge 126:abea610beb85 1525 */
AnnaBridge 126:abea610beb85 1526 #define __HAL_RCC_ETHMAC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACEN)) == RESET)
AnnaBridge 126:abea610beb85 1527 #define __HAL_RCC_ETHMACTX_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACTXEN)) == RESET)
AnnaBridge 126:abea610beb85 1528 #define __HAL_RCC_ETHMACRX_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACRXEN)) == RESET)
AnnaBridge 126:abea610beb85 1529 #define __HAL_RCC_ETHMACPTP_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACPTPEN)) == RESET)
AnnaBridge 126:abea610beb85 1530 #define __HAL_RCC_ETH_IS_CLK_DISABLED() (__HAL_RCC_ETHMAC_IS_CLK_DISABLED() && \
AnnaBridge 126:abea610beb85 1531 __HAL_RCC_ETHMACTX_IS_CLK_DISABLED() && \
AnnaBridge 126:abea610beb85 1532 __HAL_RCC_ETHMACRX_IS_CLK_DISABLED())
<> 139:856d2700e60b 1533 #endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
AnnaBridge 126:abea610beb85 1534
AnnaBridge 126:abea610beb85 1535 /** @brief Get the enable or disable status of the AHB2 peripheral clock.
AnnaBridge 126:abea610beb85 1536 * @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge 126:abea610beb85 1537 * is disabled and the application software has to enable this clock before
AnnaBridge 126:abea610beb85 1538 * using it.
AnnaBridge 126:abea610beb85 1539 */
AnnaBridge 126:abea610beb85 1540 #define __HAL_RCC_RNG_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) != RESET)
AnnaBridge 126:abea610beb85 1541 #define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET)
AnnaBridge 126:abea610beb85 1542
AnnaBridge 126:abea610beb85 1543 #define __HAL_RCC_RNG_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) == RESET)
AnnaBridge 126:abea610beb85 1544 #define __HAL_RCC_USB_IS_OTG_FS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET)
AnnaBridge 126:abea610beb85 1545
AnnaBridge 126:abea610beb85 1546 #if defined(STM32F756xx) || defined (STM32F777xx) || defined (STM32F779xx)
AnnaBridge 126:abea610beb85 1547 #define __HAL_RCC_CRYP_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_CRYPEN)) != RESET)
AnnaBridge 126:abea610beb85 1548 #define __HAL_RCC_HASH_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_HASHEN)) != RESET)
AnnaBridge 126:abea610beb85 1549 #define __HAL_RCC_CRYP_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_CRYPEN)) == RESET)
AnnaBridge 126:abea610beb85 1550 #define __HAL_RCC_HASH_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_HASHEN)) == RESET)
AnnaBridge 126:abea610beb85 1551 #endif /* STM32F756xx || STM32F777xx || STM32F779xx */
AnnaBridge 126:abea610beb85 1552
<> 139:856d2700e60b 1553 #if defined(STM32F732xx) || defined (STM32F733xx)
<> 139:856d2700e60b 1554 #define __HAL_RCC_AES_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_AESEN)) != RESET)
<> 139:856d2700e60b 1555 #define __HAL_RCC_AES_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_AESEN)) == RESET)
<> 139:856d2700e60b 1556 #endif /* STM32F732xx || STM32F733xx */
<> 139:856d2700e60b 1557
<> 139:856d2700e60b 1558 #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\
<> 139:856d2700e60b 1559 defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
<> 139:856d2700e60b 1560 #define __HAL_RCC_DCMI_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) != RESET)
<> 139:856d2700e60b 1561 #define __HAL_RCC_DCMI_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) == RESET)
<> 139:856d2700e60b 1562 #endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
<> 139:856d2700e60b 1563
AnnaBridge 126:abea610beb85 1564 #if defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
AnnaBridge 126:abea610beb85 1565 #define __HAL_RCC_JPEG_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_JPEGEN)) != RESET)
AnnaBridge 126:abea610beb85 1566 #define __HAL_RCC_JPEG_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_JPEGEN)) == RESET)
AnnaBridge 126:abea610beb85 1567 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
AnnaBridge 126:abea610beb85 1568
AnnaBridge 126:abea610beb85 1569 /** @brief Get the enable or disable status of the AHB3 peripheral clock.
AnnaBridge 126:abea610beb85 1570 * @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge 126:abea610beb85 1571 * is disabled and the application software has to enable this clock before
AnnaBridge 126:abea610beb85 1572 * using it.
AnnaBridge 126:abea610beb85 1573 */
AnnaBridge 126:abea610beb85 1574 #define __HAL_RCC_FMC_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) != RESET)
AnnaBridge 126:abea610beb85 1575 #define __HAL_RCC_QSPI_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) != RESET)
AnnaBridge 126:abea610beb85 1576
AnnaBridge 126:abea610beb85 1577 #define __HAL_RCC_FMC_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) == RESET)
AnnaBridge 126:abea610beb85 1578 #define __HAL_RCC_QSPI_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) == RESET)
AnnaBridge 126:abea610beb85 1579
AnnaBridge 126:abea610beb85 1580 /** @brief Get the enable or disable status of the APB1 peripheral clock.
AnnaBridge 126:abea610beb85 1581 * @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge 126:abea610beb85 1582 * is disabled and the application software has to enable this clock before
AnnaBridge 126:abea610beb85 1583 * using it.
AnnaBridge 126:abea610beb85 1584 */
AnnaBridge 126:abea610beb85 1585 #define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET)
AnnaBridge 126:abea610beb85 1586 #define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET)
AnnaBridge 126:abea610beb85 1587 #define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET)
AnnaBridge 126:abea610beb85 1588 #define __HAL_RCC_TIM5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) != RESET)
AnnaBridge 126:abea610beb85 1589 #define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET)
AnnaBridge 126:abea610beb85 1590 #define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET)
AnnaBridge 126:abea610beb85 1591 #define __HAL_RCC_TIM12_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET)
AnnaBridge 126:abea610beb85 1592 #define __HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET)
AnnaBridge 126:abea610beb85 1593 #define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET)
AnnaBridge 126:abea610beb85 1594 #define __HAL_RCC_LPTIM1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_LPTIM1EN)) != RESET)
AnnaBridge 126:abea610beb85 1595 #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
AnnaBridge 126:abea610beb85 1596 #define __HAL_RCC_CAN3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN3EN)) != RESET)
AnnaBridge 126:abea610beb85 1597 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
AnnaBridge 126:abea610beb85 1598 #define __HAL_RCC_SPI2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) != RESET)
AnnaBridge 126:abea610beb85 1599 #define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET)
AnnaBridge 126:abea610beb85 1600 #define __HAL_RCC_USART2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) != RESET)
AnnaBridge 126:abea610beb85 1601 #define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET)
AnnaBridge 126:abea610beb85 1602 #define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET)
AnnaBridge 126:abea610beb85 1603 #define __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET)
AnnaBridge 126:abea610beb85 1604 #define __HAL_RCC_I2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) != RESET)
AnnaBridge 126:abea610beb85 1605 #define __HAL_RCC_I2C2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) != RESET)
AnnaBridge 126:abea610beb85 1606 #define __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET)
AnnaBridge 126:abea610beb85 1607 #define __HAL_RCC_CAN1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) != RESET)
AnnaBridge 126:abea610beb85 1608 #define __HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET)
AnnaBridge 126:abea610beb85 1609 #define __HAL_RCC_UART7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART7EN)) != RESET)
AnnaBridge 126:abea610beb85 1610 #define __HAL_RCC_UART8_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART8EN)) != RESET)
AnnaBridge 126:abea610beb85 1611
AnnaBridge 126:abea610beb85 1612 #define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET)
AnnaBridge 126:abea610beb85 1613 #define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET)
AnnaBridge 126:abea610beb85 1614 #define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET)
AnnaBridge 126:abea610beb85 1615 #define __HAL_RCC_TIM5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) == RESET)
AnnaBridge 126:abea610beb85 1616 #define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET)
AnnaBridge 126:abea610beb85 1617 #define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET)
AnnaBridge 126:abea610beb85 1618 #define __HAL_RCC_TIM12_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET)
AnnaBridge 126:abea610beb85 1619 #define __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET)
AnnaBridge 126:abea610beb85 1620 #define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET)
AnnaBridge 126:abea610beb85 1621 #define __HAL_RCC_LPTIM1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_LPTIM1EN)) == RESET)
AnnaBridge 126:abea610beb85 1622 #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
AnnaBridge 126:abea610beb85 1623 #define __HAL_RCC_CAN3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN3EN)) == RESET)
AnnaBridge 126:abea610beb85 1624 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
AnnaBridge 126:abea610beb85 1625 #define __HAL_RCC_SPI2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) == RESET)
AnnaBridge 126:abea610beb85 1626 #define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET)
AnnaBridge 126:abea610beb85 1627 #define __HAL_RCC_USART2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) == RESET)
AnnaBridge 126:abea610beb85 1628 #define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET)
AnnaBridge 126:abea610beb85 1629 #define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET)
AnnaBridge 126:abea610beb85 1630 #define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET)
AnnaBridge 126:abea610beb85 1631 #define __HAL_RCC_I2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) == RESET)
AnnaBridge 126:abea610beb85 1632 #define __HAL_RCC_I2C2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) == RESET)
AnnaBridge 126:abea610beb85 1633 #define __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET)
AnnaBridge 126:abea610beb85 1634 #define __HAL_RCC_CAN1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) == RESET)
AnnaBridge 126:abea610beb85 1635 #define __HAL_RCC_DAC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET)
AnnaBridge 126:abea610beb85 1636 #define __HAL_RCC_UART7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART7EN)) == RESET)
AnnaBridge 126:abea610beb85 1637 #define __HAL_RCC_UART8_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART8EN)) == RESET)
<> 139:856d2700e60b 1638 #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\
<> 139:856d2700e60b 1639 defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
<> 139:856d2700e60b 1640 #define __HAL_RCC_SPDIFRX_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPDIFRXEN)) != RESET)
<> 139:856d2700e60b 1641 #define __HAL_RCC_CAN2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) != RESET)
<> 139:856d2700e60b 1642 #define __HAL_RCC_CEC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) != RESET)
<> 139:856d2700e60b 1643 #define __HAL_RCC_I2C4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C4EN)) != RESET)
<> 139:856d2700e60b 1644
<> 139:856d2700e60b 1645 #define __HAL_RCC_SPDIFRX_IS_CLK_DISABLED()((RCC->APB1ENR & (RCC_APB1ENR_SPDIFRXEN)) == RESET)
<> 139:856d2700e60b 1646 #define __HAL_RCC_CAN2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) == RESET)
<> 139:856d2700e60b 1647 #define __HAL_RCC_CEC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) == RESET)
<> 139:856d2700e60b 1648 #define __HAL_RCC_I2C4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C4EN)) == RESET)
<> 139:856d2700e60b 1649 #endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
<> 139:856d2700e60b 1650
<> 139:856d2700e60b 1651 #if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) ||\
<> 139:856d2700e60b 1652 defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) ||\
<> 139:856d2700e60b 1653 defined (STM32F779xx)
<> 139:856d2700e60b 1654 #define __HAL_RCC_RTC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_RTCEN)) != RESET)
<> 139:856d2700e60b 1655 #define __HAL_RCC_RTC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_RTCEN)) == RESET)
<> 139:856d2700e60b 1656 #endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx ||
<> 139:856d2700e60b 1657 STM32F769xx || STM32F777xx || STM32F779xx */
AnnaBridge 126:abea610beb85 1658
AnnaBridge 126:abea610beb85 1659 /** @brief Get the enable or disable status of the APB2 peripheral clock.
AnnaBridge 126:abea610beb85 1660 * @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge 126:abea610beb85 1661 * is disabled and the application software has to enable this clock before
AnnaBridge 126:abea610beb85 1662 * using it.
AnnaBridge 126:abea610beb85 1663 */
AnnaBridge 126:abea610beb85 1664 #define __HAL_RCC_TIM1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) != RESET)
AnnaBridge 126:abea610beb85 1665 #define __HAL_RCC_TIM8_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) != RESET)
AnnaBridge 126:abea610beb85 1666 #define __HAL_RCC_USART1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) != RESET)
AnnaBridge 126:abea610beb85 1667 #define __HAL_RCC_USART6_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART6EN)) != RESET)
AnnaBridge 126:abea610beb85 1668 #define __HAL_RCC_ADC1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) != RESET)
AnnaBridge 126:abea610beb85 1669 #define __HAL_RCC_ADC2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) != RESET)
AnnaBridge 126:abea610beb85 1670 #define __HAL_RCC_ADC3_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) != RESET)
AnnaBridge 126:abea610beb85 1671 #define __HAL_RCC_SDMMC1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDMMC1EN)) != RESET)
AnnaBridge 126:abea610beb85 1672 #define __HAL_RCC_SPI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) != RESET)
AnnaBridge 126:abea610beb85 1673 #define __HAL_RCC_SPI4_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET)
AnnaBridge 126:abea610beb85 1674 #define __HAL_RCC_TIM9_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) != RESET)
AnnaBridge 126:abea610beb85 1675 #define __HAL_RCC_TIM10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET)
AnnaBridge 126:abea610beb85 1676 #define __HAL_RCC_TIM11_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) != RESET)
AnnaBridge 126:abea610beb85 1677 #define __HAL_RCC_SPI5_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) != RESET)
AnnaBridge 126:abea610beb85 1678 #define __HAL_RCC_SPI6_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI6EN)) != RESET)
AnnaBridge 126:abea610beb85 1679 #define __HAL_RCC_SAI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) != RESET)
AnnaBridge 126:abea610beb85 1680 #define __HAL_RCC_SAI2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI2EN)) != RESET)
AnnaBridge 126:abea610beb85 1681 #if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
AnnaBridge 126:abea610beb85 1682 #define __HAL_RCC_LTDC_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_LTDCEN)) != RESET)
AnnaBridge 126:abea610beb85 1683 #endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
AnnaBridge 126:abea610beb85 1684 #if defined (STM32F769xx) || defined (STM32F779xx)
AnnaBridge 126:abea610beb85 1685 #define __HAL_RCC_DSI_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DSIEN)) != RESET)
AnnaBridge 126:abea610beb85 1686 #endif /* STM32F769xx || STM32F779xx */
<> 139:856d2700e60b 1687 #if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\
<> 139:856d2700e60b 1688 defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
AnnaBridge 126:abea610beb85 1689 #define __HAL_RCC_SDMMC2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDMMC2EN)) != RESET)
<> 139:856d2700e60b 1690 #endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
<> 139:856d2700e60b 1691 #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
<> 139:856d2700e60b 1692 #define __HAL_RCC_DFSDM1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DFSDM1EN)) != RESET)
AnnaBridge 126:abea610beb85 1693 #define __HAL_RCC_MDIO_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_MDIOEN)) != RESET)
AnnaBridge 126:abea610beb85 1694 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
<> 139:856d2700e60b 1695 #if defined (STM32F723xx) || defined (STM32F733xx)
<> 139:856d2700e60b 1696 #define __HAL_RCC_OTGPHYC_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_OTGPHYCEN)) != RESET)
<> 139:856d2700e60b 1697 #endif /* STM32F723xx || STM32F733xx */
<> 139:856d2700e60b 1698
AnnaBridge 126:abea610beb85 1699 #define __HAL_RCC_TIM1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) == RESET)
AnnaBridge 126:abea610beb85 1700 #define __HAL_RCC_TIM8_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) == RESET)
AnnaBridge 126:abea610beb85 1701 #define __HAL_RCC_USART1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) == RESET)
AnnaBridge 126:abea610beb85 1702 #define __HAL_RCC_USART6_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART6EN)) == RESET)
AnnaBridge 126:abea610beb85 1703 #define __HAL_RCC_ADC1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) == RESET)
AnnaBridge 126:abea610beb85 1704 #define __HAL_RCC_ADC2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) == RESET)
AnnaBridge 126:abea610beb85 1705 #define __HAL_RCC_ADC3_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) == RESET)
AnnaBridge 126:abea610beb85 1706 #define __HAL_RCC_SDMMC1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDMMC1EN)) == RESET)
AnnaBridge 126:abea610beb85 1707 #define __HAL_RCC_SPI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) == RESET)
AnnaBridge 126:abea610beb85 1708 #define __HAL_RCC_SPI4_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET)
AnnaBridge 126:abea610beb85 1709 #define __HAL_RCC_TIM9_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) == RESET)
AnnaBridge 126:abea610beb85 1710 #define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET)
AnnaBridge 126:abea610beb85 1711 #define __HAL_RCC_TIM11_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) == RESET)
AnnaBridge 126:abea610beb85 1712 #define __HAL_RCC_SPI5_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) == RESET)
AnnaBridge 126:abea610beb85 1713 #define __HAL_RCC_SPI6_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI6EN)) == RESET)
AnnaBridge 126:abea610beb85 1714 #define __HAL_RCC_SAI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) == RESET)
AnnaBridge 126:abea610beb85 1715 #define __HAL_RCC_SAI2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI2EN)) == RESET)
AnnaBridge 126:abea610beb85 1716 #if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
AnnaBridge 126:abea610beb85 1717 #define __HAL_RCC_LTDC_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_LTDCEN)) == RESET)
AnnaBridge 126:abea610beb85 1718 #endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
AnnaBridge 126:abea610beb85 1719 #if defined (STM32F769xx) || defined (STM32F779xx)
AnnaBridge 126:abea610beb85 1720 #define __HAL_RCC_DSI_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DSIEN)) == RESET)
AnnaBridge 126:abea610beb85 1721 #endif /* STM32F769xx || STM32F779xx */
<> 139:856d2700e60b 1722 #if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\
<> 139:856d2700e60b 1723 defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
AnnaBridge 126:abea610beb85 1724 #define __HAL_RCC_SDMMC2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDMMC2EN)) == RESET)
<> 139:856d2700e60b 1725 #endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
<> 139:856d2700e60b 1726 #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
<> 139:856d2700e60b 1727 #define __HAL_RCC_DFSDM1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DFSDM1EN)) == RESET)
AnnaBridge 126:abea610beb85 1728 #define __HAL_RCC_MDIO_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_MDIOEN)) == RESET)
AnnaBridge 126:abea610beb85 1729 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
<> 139:856d2700e60b 1730 #if defined (STM32F723xx) || defined (STM32F733xx)
<> 139:856d2700e60b 1731 #define __HAL_RCC_OTGPHYC_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_OTGPHYCEN)) == RESET)
<> 139:856d2700e60b 1732 #endif /* STM32F723xx || STM32F733xx */
<> 139:856d2700e60b 1733
AnnaBridge 126:abea610beb85 1734 /**
AnnaBridge 126:abea610beb85 1735 * @}
AnnaBridge 126:abea610beb85 1736 */
AnnaBridge 126:abea610beb85 1737
AnnaBridge 126:abea610beb85 1738 /** @defgroup RCCEx_Force_Release_Peripheral_Reset RCCEx Force Release Peripheral Reset
AnnaBridge 126:abea610beb85 1739 * @brief Forces or releases AHB/APB peripheral reset.
AnnaBridge 126:abea610beb85 1740 * @{
AnnaBridge 126:abea610beb85 1741 */
AnnaBridge 126:abea610beb85 1742
AnnaBridge 126:abea610beb85 1743 /** @brief Force or release AHB1 peripheral reset.
AnnaBridge 126:abea610beb85 1744 */
AnnaBridge 126:abea610beb85 1745 #define __HAL_RCC_DMA2_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA2RST))
AnnaBridge 126:abea610beb85 1746 #define __HAL_RCC_USB_OTG_HS_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_OTGHRST))
AnnaBridge 126:abea610beb85 1747 #define __HAL_RCC_GPIOA_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOARST))
AnnaBridge 126:abea610beb85 1748 #define __HAL_RCC_GPIOB_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOBRST))
AnnaBridge 126:abea610beb85 1749 #define __HAL_RCC_GPIOC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOCRST))
AnnaBridge 126:abea610beb85 1750 #define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIODRST))
AnnaBridge 126:abea610beb85 1751 #define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOERST))
AnnaBridge 126:abea610beb85 1752 #define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOFRST))
AnnaBridge 126:abea610beb85 1753 #define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOGRST))
AnnaBridge 126:abea610beb85 1754 #define __HAL_RCC_GPIOH_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOHRST))
AnnaBridge 126:abea610beb85 1755 #define __HAL_RCC_GPIOI_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOIRST))
AnnaBridge 126:abea610beb85 1756
AnnaBridge 126:abea610beb85 1757 #define __HAL_RCC_DMA2_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA2RST))
AnnaBridge 126:abea610beb85 1758 #define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_OTGHRST))
AnnaBridge 126:abea610beb85 1759 #define __HAL_RCC_GPIOA_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOARST))
AnnaBridge 126:abea610beb85 1760 #define __HAL_RCC_GPIOB_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOBRST))
AnnaBridge 126:abea610beb85 1761 #define __HAL_RCC_GPIOC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOCRST))
AnnaBridge 126:abea610beb85 1762 #define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST))
AnnaBridge 126:abea610beb85 1763 #define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST))
AnnaBridge 126:abea610beb85 1764 #define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST))
AnnaBridge 126:abea610beb85 1765 #define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST))
AnnaBridge 126:abea610beb85 1766 #define __HAL_RCC_GPIOH_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOHRST))
AnnaBridge 126:abea610beb85 1767 #define __HAL_RCC_GPIOI_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOIRST))
<> 139:856d2700e60b 1768
<> 139:856d2700e60b 1769 #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\
<> 139:856d2700e60b 1770 defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
<> 139:856d2700e60b 1771 #define __HAL_RCC_DMA2D_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA2DRST))
<> 139:856d2700e60b 1772 #define __HAL_RCC_ETHMAC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_ETHMACRST))
<> 139:856d2700e60b 1773 #define __HAL_RCC_GPIOJ_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOJRST))
<> 139:856d2700e60b 1774 #define __HAL_RCC_GPIOK_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOKRST))
<> 139:856d2700e60b 1775
<> 139:856d2700e60b 1776 #define __HAL_RCC_DMA2D_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA2DRST))
<> 139:856d2700e60b 1777 #define __HAL_RCC_ETHMAC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_ETHMACRST))
AnnaBridge 126:abea610beb85 1778 #define __HAL_RCC_GPIOJ_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOJRST))
AnnaBridge 126:abea610beb85 1779 #define __HAL_RCC_GPIOK_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOKRST))
<> 139:856d2700e60b 1780 #endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
<> 139:856d2700e60b 1781
AnnaBridge 126:abea610beb85 1782 /** @brief Force or release AHB2 peripheral reset.
AnnaBridge 126:abea610beb85 1783 */
AnnaBridge 126:abea610beb85 1784 #define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFFU)
AnnaBridge 126:abea610beb85 1785 #define __HAL_RCC_RNG_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_RNGRST))
AnnaBridge 126:abea610beb85 1786 #define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_OTGFSRST))
AnnaBridge 126:abea610beb85 1787
AnnaBridge 126:abea610beb85 1788 #define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00U)
AnnaBridge 126:abea610beb85 1789 #define __HAL_RCC_RNG_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_RNGRST))
AnnaBridge 126:abea610beb85 1790 #define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST))
AnnaBridge 126:abea610beb85 1791
AnnaBridge 126:abea610beb85 1792 #if defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
AnnaBridge 126:abea610beb85 1793 #define __HAL_RCC_JPEG_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_JPEGRST))
AnnaBridge 126:abea610beb85 1794 #define __HAL_RCC_JPEG_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_JPEGRST))
AnnaBridge 126:abea610beb85 1795 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
AnnaBridge 126:abea610beb85 1796
AnnaBridge 126:abea610beb85 1797 #if defined(STM32F756xx) || defined (STM32F777xx) || defined (STM32F779xx)
AnnaBridge 126:abea610beb85 1798 #define __HAL_RCC_CRYP_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_CRYPRST))
AnnaBridge 126:abea610beb85 1799 #define __HAL_RCC_HASH_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_HASHRST))
AnnaBridge 126:abea610beb85 1800 #define __HAL_RCC_CRYP_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_CRYPRST))
AnnaBridge 126:abea610beb85 1801 #define __HAL_RCC_HASH_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_HASHRST))
AnnaBridge 126:abea610beb85 1802 #endif /* STM32F756xx || STM32F777xx || STM32F779xx */
<> 139:856d2700e60b 1803
<> 139:856d2700e60b 1804 #if defined(STM32F732xx) || defined (STM32F733xx)
<> 139:856d2700e60b 1805 #define __HAL_RCC_AES_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_AESRST))
<> 139:856d2700e60b 1806 #define __HAL_RCC_AES_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_AESRST))
<> 139:856d2700e60b 1807 #endif /* STM32F732xx || STM32F733xx */
<> 139:856d2700e60b 1808
<> 139:856d2700e60b 1809 #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\
<> 139:856d2700e60b 1810 defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
<> 139:856d2700e60b 1811 #define __HAL_RCC_DCMI_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_DCMIRST))
<> 139:856d2700e60b 1812 #define __HAL_RCC_DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_DCMIRST))
<> 139:856d2700e60b 1813 #endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
AnnaBridge 126:abea610beb85 1814
AnnaBridge 126:abea610beb85 1815 /** @brief Force or release AHB3 peripheral reset
AnnaBridge 126:abea610beb85 1816 */
AnnaBridge 126:abea610beb85 1817 #define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU)
AnnaBridge 126:abea610beb85 1818 #define __HAL_RCC_FMC_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FMCRST))
AnnaBridge 126:abea610beb85 1819 #define __HAL_RCC_QSPI_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_QSPIRST))
AnnaBridge 126:abea610beb85 1820
AnnaBridge 126:abea610beb85 1821 #define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U)
AnnaBridge 126:abea610beb85 1822 #define __HAL_RCC_FMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FMCRST))
AnnaBridge 126:abea610beb85 1823 #define __HAL_RCC_QSPI_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_QSPIRST))
AnnaBridge 126:abea610beb85 1824
AnnaBridge 126:abea610beb85 1825 /** @brief Force or release APB1 peripheral reset.
AnnaBridge 126:abea610beb85 1826 */
AnnaBridge 126:abea610beb85 1827 #define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST))
AnnaBridge 126:abea610beb85 1828 #define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST))
AnnaBridge 126:abea610beb85 1829 #define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST))
AnnaBridge 126:abea610beb85 1830 #define __HAL_RCC_TIM5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM5RST))
AnnaBridge 126:abea610beb85 1831 #define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST))
AnnaBridge 126:abea610beb85 1832 #define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST))
AnnaBridge 126:abea610beb85 1833 #define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST))
AnnaBridge 126:abea610beb85 1834 #define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST))
AnnaBridge 126:abea610beb85 1835 #define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST))
AnnaBridge 126:abea610beb85 1836 #define __HAL_RCC_LPTIM1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_LPTIM1RST))
AnnaBridge 126:abea610beb85 1837 #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
AnnaBridge 126:abea610beb85 1838 #define __HAL_RCC_CAN3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN3RST))
AnnaBridge 126:abea610beb85 1839 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
AnnaBridge 126:abea610beb85 1840 #define __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST))
AnnaBridge 126:abea610beb85 1841 #define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST))
AnnaBridge 126:abea610beb85 1842 #define __HAL_RCC_USART2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART2RST))
AnnaBridge 126:abea610beb85 1843 #define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST))
AnnaBridge 126:abea610beb85 1844 #define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST))
AnnaBridge 126:abea610beb85 1845 #define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST))
AnnaBridge 126:abea610beb85 1846 #define __HAL_RCC_I2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C1RST))
AnnaBridge 126:abea610beb85 1847 #define __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST))
AnnaBridge 126:abea610beb85 1848 #define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST))
AnnaBridge 126:abea610beb85 1849 #define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN1RST))
AnnaBridge 126:abea610beb85 1850 #define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST))
AnnaBridge 126:abea610beb85 1851 #define __HAL_RCC_UART7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART7RST))
AnnaBridge 126:abea610beb85 1852 #define __HAL_RCC_UART8_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART8RST))
AnnaBridge 126:abea610beb85 1853
AnnaBridge 126:abea610beb85 1854 #define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
AnnaBridge 126:abea610beb85 1855 #define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
AnnaBridge 126:abea610beb85 1856 #define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
AnnaBridge 126:abea610beb85 1857 #define __HAL_RCC_TIM5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST))
AnnaBridge 126:abea610beb85 1858 #define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
AnnaBridge 126:abea610beb85 1859 #define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
AnnaBridge 126:abea610beb85 1860 #define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))
AnnaBridge 126:abea610beb85 1861 #define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))
AnnaBridge 126:abea610beb85 1862 #define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
AnnaBridge 126:abea610beb85 1863 #define __HAL_RCC_LPTIM1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_LPTIM1RST))
AnnaBridge 126:abea610beb85 1864 #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
AnnaBridge 126:abea610beb85 1865 #define __HAL_RCC_CAN3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN3RST))
AnnaBridge 126:abea610beb85 1866 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
AnnaBridge 126:abea610beb85 1867 #define __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST))
AnnaBridge 126:abea610beb85 1868 #define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
AnnaBridge 126:abea610beb85 1869 #define __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST))
AnnaBridge 126:abea610beb85 1870 #define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
AnnaBridge 126:abea610beb85 1871 #define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
AnnaBridge 126:abea610beb85 1872 #define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
AnnaBridge 126:abea610beb85 1873 #define __HAL_RCC_I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST))
AnnaBridge 126:abea610beb85 1874 #define __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST))
AnnaBridge 126:abea610beb85 1875 #define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))
AnnaBridge 126:abea610beb85 1876 #define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST))
AnnaBridge 126:abea610beb85 1877 #define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
AnnaBridge 126:abea610beb85 1878 #define __HAL_RCC_UART7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART7RST))
AnnaBridge 126:abea610beb85 1879 #define __HAL_RCC_UART8_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART8RST))
AnnaBridge 126:abea610beb85 1880
<> 139:856d2700e60b 1881 #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\
<> 139:856d2700e60b 1882 defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
<> 139:856d2700e60b 1883 #define __HAL_RCC_SPDIFRX_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPDIFRXRST))
<> 139:856d2700e60b 1884 #define __HAL_RCC_I2C4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C4RST))
<> 139:856d2700e60b 1885 #define __HAL_RCC_CAN2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN2RST))
<> 139:856d2700e60b 1886 #define __HAL_RCC_CEC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CECRST))
<> 139:856d2700e60b 1887
<> 139:856d2700e60b 1888 #define __HAL_RCC_SPDIFRX_RELEASE_RESET()(RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPDIFRXRST))
<> 139:856d2700e60b 1889 #define __HAL_RCC_I2C4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C4RST))
<> 139:856d2700e60b 1890 #define __HAL_RCC_CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST))
<> 139:856d2700e60b 1891 #define __HAL_RCC_CEC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CECRST))
<> 139:856d2700e60b 1892 #endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
<> 139:856d2700e60b 1893
AnnaBridge 126:abea610beb85 1894 /** @brief Force or release APB2 peripheral reset.
AnnaBridge 126:abea610beb85 1895 */
AnnaBridge 126:abea610beb85 1896 #define __HAL_RCC_TIM1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM1RST))
AnnaBridge 126:abea610beb85 1897 #define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST))
AnnaBridge 126:abea610beb85 1898 #define __HAL_RCC_USART1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART1RST))
AnnaBridge 126:abea610beb85 1899 #define __HAL_RCC_USART6_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART6RST))
AnnaBridge 126:abea610beb85 1900 #define __HAL_RCC_ADC_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADCRST))
AnnaBridge 126:abea610beb85 1901 #define __HAL_RCC_SDMMC1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDMMC1RST))
AnnaBridge 126:abea610beb85 1902 #define __HAL_RCC_SPI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST))
AnnaBridge 126:abea610beb85 1903 #define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI4RST))
AnnaBridge 126:abea610beb85 1904 #define __HAL_RCC_TIM9_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM9RST))
AnnaBridge 126:abea610beb85 1905 #define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST))
AnnaBridge 126:abea610beb85 1906 #define __HAL_RCC_TIM11_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM11RST))
AnnaBridge 126:abea610beb85 1907 #define __HAL_RCC_SPI5_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI5RST))
AnnaBridge 126:abea610beb85 1908 #define __HAL_RCC_SPI6_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI6RST))
AnnaBridge 126:abea610beb85 1909 #define __HAL_RCC_SAI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SAI1RST))
AnnaBridge 126:abea610beb85 1910 #define __HAL_RCC_SAI2_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SAI2RST))
AnnaBridge 126:abea610beb85 1911 #if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
AnnaBridge 126:abea610beb85 1912 #define __HAL_RCC_LTDC_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_LTDCRST))
AnnaBridge 126:abea610beb85 1913 #endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
<> 139:856d2700e60b 1914 #if defined (STM32F723xx) || defined (STM32F733xx)
<> 139:856d2700e60b 1915 #define __HAL_RCC_OTGPHYC_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_OTGPHYCRST))
<> 139:856d2700e60b 1916 #endif /* STM32F723xx || STM32F733xx */
AnnaBridge 126:abea610beb85 1917
AnnaBridge 126:abea610beb85 1918 #define __HAL_RCC_TIM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST))
AnnaBridge 126:abea610beb85 1919 #define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST))
AnnaBridge 126:abea610beb85 1920 #define __HAL_RCC_USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST))
AnnaBridge 126:abea610beb85 1921 #define __HAL_RCC_USART6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART6RST))
AnnaBridge 126:abea610beb85 1922 #define __HAL_RCC_ADC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADCRST))
AnnaBridge 126:abea610beb85 1923 #define __HAL_RCC_SDMMC1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDMMC1RST))
AnnaBridge 126:abea610beb85 1924 #define __HAL_RCC_SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST))
AnnaBridge 126:abea610beb85 1925 #define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST))
AnnaBridge 126:abea610beb85 1926 #define __HAL_RCC_TIM9_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM9RST))
AnnaBridge 126:abea610beb85 1927 #define __HAL_RCC_TIM10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))
AnnaBridge 126:abea610beb85 1928 #define __HAL_RCC_TIM11_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM11RST))
AnnaBridge 126:abea610beb85 1929 #define __HAL_RCC_SPI5_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST))
AnnaBridge 126:abea610beb85 1930 #define __HAL_RCC_SPI6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI6RST))
AnnaBridge 126:abea610beb85 1931 #define __HAL_RCC_SAI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI1RST))
AnnaBridge 126:abea610beb85 1932 #define __HAL_RCC_SAI2_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI2RST))
AnnaBridge 126:abea610beb85 1933 #if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
AnnaBridge 126:abea610beb85 1934 #define __HAL_RCC_LTDC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_LTDCRST))
AnnaBridge 126:abea610beb85 1935 #endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
<> 139:856d2700e60b 1936 #if defined (STM32F723xx) || defined (STM32F733xx)
<> 139:856d2700e60b 1937 #define __HAL_RCC_OTGPHYC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_OTGPHYCRST))
<> 139:856d2700e60b 1938 #endif /* STM32F723xx || STM32F733xx */
AnnaBridge 126:abea610beb85 1939
AnnaBridge 126:abea610beb85 1940 #if defined (STM32F769xx) || defined (STM32F779xx)
AnnaBridge 126:abea610beb85 1941 #define __HAL_RCC_DSI_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_DSIRST))
AnnaBridge 126:abea610beb85 1942 #define __HAL_RCC_DSI_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_DSIRST))
AnnaBridge 126:abea610beb85 1943 #endif /* STM32F769xx || STM32F779xx */
AnnaBridge 126:abea610beb85 1944
<> 139:856d2700e60b 1945 #if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\
<> 139:856d2700e60b 1946 defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
<> 139:856d2700e60b 1947 #define __HAL_RCC_SDMMC2_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDMMC2RST))
<> 139:856d2700e60b 1948 #define __HAL_RCC_SDMMC2_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDMMC2RST))
<> 139:856d2700e60b 1949 #endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
<> 139:856d2700e60b 1950
AnnaBridge 126:abea610beb85 1951 #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
AnnaBridge 126:abea610beb85 1952 #define __HAL_RCC_DFSDM1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_DFSDM1RST))
AnnaBridge 126:abea610beb85 1953 #define __HAL_RCC_MDIO_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_MDIORST))
AnnaBridge 126:abea610beb85 1954 #define __HAL_RCC_DFSDM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_DFSDM1RST))
AnnaBridge 126:abea610beb85 1955 #define __HAL_RCC_MDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_MDIORST))
AnnaBridge 126:abea610beb85 1956 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
AnnaBridge 126:abea610beb85 1957 /**
AnnaBridge 126:abea610beb85 1958 * @}
AnnaBridge 126:abea610beb85 1959 */
AnnaBridge 126:abea610beb85 1960
AnnaBridge 126:abea610beb85 1961 /** @defgroup RCCEx_Peripheral_Clock_Sleep_Enable_Disable RCCEx Peripheral Clock Sleep Enable Disable
AnnaBridge 126:abea610beb85 1962 * @brief Enables or disables the AHB/APB peripheral clock during Low Power (Sleep) mode.
AnnaBridge 126:abea610beb85 1963 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
AnnaBridge 126:abea610beb85 1964 * power consumption.
AnnaBridge 126:abea610beb85 1965 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
AnnaBridge 126:abea610beb85 1966 * @note By default, all peripheral clocks are enabled during SLEEP mode.
AnnaBridge 126:abea610beb85 1967 * @{
AnnaBridge 126:abea610beb85 1968 */
AnnaBridge 126:abea610beb85 1969
AnnaBridge 126:abea610beb85 1970 /** @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
AnnaBridge 126:abea610beb85 1971 */
AnnaBridge 126:abea610beb85 1972 #define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN))
AnnaBridge 126:abea610beb85 1973 #define __HAL_RCC_AXI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_AXILPEN))
AnnaBridge 126:abea610beb85 1974 #define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN))
AnnaBridge 126:abea610beb85 1975 #define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM2LPEN))
AnnaBridge 126:abea610beb85 1976 #define __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_BKPSRAMLPEN))
AnnaBridge 126:abea610beb85 1977 #define __HAL_RCC_DTCM_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DTCMLPEN))
AnnaBridge 126:abea610beb85 1978 #define __HAL_RCC_DMA2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA2LPEN))
AnnaBridge 126:abea610beb85 1979 #define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSLPEN))
AnnaBridge 126:abea610beb85 1980 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSULPILPEN))
AnnaBridge 126:abea610beb85 1981 #define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOALPEN))
AnnaBridge 126:abea610beb85 1982 #define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOBLPEN))
AnnaBridge 126:abea610beb85 1983 #define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOCLPEN))
AnnaBridge 126:abea610beb85 1984 #define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIODLPEN))
AnnaBridge 126:abea610beb85 1985 #define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOELPEN))
AnnaBridge 126:abea610beb85 1986 #define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOFLPEN))
AnnaBridge 126:abea610beb85 1987 #define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOGLPEN))
AnnaBridge 126:abea610beb85 1988 #define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOHLPEN))
AnnaBridge 126:abea610beb85 1989 #define __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOILPEN))
AnnaBridge 126:abea610beb85 1990
AnnaBridge 126:abea610beb85 1991 #define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN))
AnnaBridge 126:abea610beb85 1992 #define __HAL_RCC_AXI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_AXILPEN))
AnnaBridge 126:abea610beb85 1993 #define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN))
AnnaBridge 126:abea610beb85 1994 #define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN))
AnnaBridge 126:abea610beb85 1995 #define __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_BKPSRAMLPEN))
AnnaBridge 126:abea610beb85 1996 #define __HAL_RCC_DTCM_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DTCMLPEN))
AnnaBridge 126:abea610beb85 1997 #define __HAL_RCC_DMA2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA2LPEN))
AnnaBridge 126:abea610beb85 1998 #define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSLPEN))
AnnaBridge 126:abea610beb85 1999 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSULPILPEN))
AnnaBridge 126:abea610beb85 2000 #define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOALPEN))
AnnaBridge 126:abea610beb85 2001 #define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOBLPEN))
AnnaBridge 126:abea610beb85 2002 #define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOCLPEN))
AnnaBridge 126:abea610beb85 2003 #define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN))
AnnaBridge 126:abea610beb85 2004 #define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN))
AnnaBridge 126:abea610beb85 2005 #define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN))
AnnaBridge 126:abea610beb85 2006 #define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN))
AnnaBridge 126:abea610beb85 2007 #define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOHLPEN))
AnnaBridge 126:abea610beb85 2008 #define __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOILPEN))
<> 139:856d2700e60b 2009
<> 139:856d2700e60b 2010 #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\
<> 139:856d2700e60b 2011 defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
<> 139:856d2700e60b 2012 #define __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA2DLPEN))
<> 139:856d2700e60b 2013 #define __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACLPEN))
<> 139:856d2700e60b 2014 #define __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACTXLPEN))
<> 139:856d2700e60b 2015 #define __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACRXLPEN))
<> 139:856d2700e60b 2016 #define __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACPTPLPEN))
<> 139:856d2700e60b 2017 #define __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOJLPEN))
<> 139:856d2700e60b 2018 #define __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOKLPEN))
<> 139:856d2700e60b 2019
<> 139:856d2700e60b 2020 #define __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA2DLPEN))
<> 139:856d2700e60b 2021 #define __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACLPEN))
<> 139:856d2700e60b 2022 #define __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACTXLPEN))
<> 139:856d2700e60b 2023 #define __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACRXLPEN))
<> 139:856d2700e60b 2024 #define __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACPTPLPEN))
AnnaBridge 126:abea610beb85 2025 #define __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOJLPEN))
AnnaBridge 126:abea610beb85 2026 #define __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOKLPEN))
<> 139:856d2700e60b 2027 #endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
AnnaBridge 126:abea610beb85 2028
AnnaBridge 126:abea610beb85 2029 /** @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
AnnaBridge 126:abea610beb85 2030 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
AnnaBridge 126:abea610beb85 2031 * power consumption.
AnnaBridge 126:abea610beb85 2032 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
AnnaBridge 126:abea610beb85 2033 * @note By default, all peripheral clocks are enabled during SLEEP mode.
AnnaBridge 126:abea610beb85 2034 */
<> 139:856d2700e60b 2035 #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\
<> 139:856d2700e60b 2036 defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
AnnaBridge 126:abea610beb85 2037 #define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN))
AnnaBridge 126:abea610beb85 2038 #define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_DCMILPEN))
<> 139:856d2700e60b 2039 #endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
AnnaBridge 126:abea610beb85 2040
AnnaBridge 126:abea610beb85 2041 #if defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
AnnaBridge 126:abea610beb85 2042 #define __HAL_RCC_JPEG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_JPEGLPEN))
AnnaBridge 126:abea610beb85 2043 #define __HAL_RCC_JPEG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_JPEGLPEN))
AnnaBridge 126:abea610beb85 2044 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
AnnaBridge 126:abea610beb85 2045
AnnaBridge 126:abea610beb85 2046 #define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN))
AnnaBridge 126:abea610beb85 2047 #define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_RNGLPEN))
AnnaBridge 126:abea610beb85 2048
AnnaBridge 126:abea610beb85 2049 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_OTGFSLPEN))
AnnaBridge 126:abea610beb85 2050 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN))
AnnaBridge 126:abea610beb85 2051
AnnaBridge 126:abea610beb85 2052 #if defined(STM32F756xx) || defined (STM32F777xx) || defined (STM32F779xx)
AnnaBridge 126:abea610beb85 2053 #define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_CRYPLPEN))
AnnaBridge 126:abea610beb85 2054 #define __HAL_RCC_HASH_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_HASHLPEN))
AnnaBridge 126:abea610beb85 2055
AnnaBridge 126:abea610beb85 2056 #define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_CRYPLPEN))
AnnaBridge 126:abea610beb85 2057 #define __HAL_RCC_HASH_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_HASHLPEN))
AnnaBridge 126:abea610beb85 2058 #endif /* STM32F756xx || STM32F777xx || STM32F779xx */
<> 139:856d2700e60b 2059
<> 139:856d2700e60b 2060 #if defined(STM32F732xx) || defined (STM32F733xx)
<> 139:856d2700e60b 2061 #define __HAL_RCC_AES_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_AESLPEN))
<> 139:856d2700e60b 2062 #define __HAL_RCC_AES_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_AESLPEN))
<> 139:856d2700e60b 2063 #endif /* STM32F732xx || STM32F733xx */
AnnaBridge 126:abea610beb85 2064
AnnaBridge 126:abea610beb85 2065 /** @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode.
AnnaBridge 126:abea610beb85 2066 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
AnnaBridge 126:abea610beb85 2067 * power consumption.
AnnaBridge 126:abea610beb85 2068 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
AnnaBridge 126:abea610beb85 2069 * @note By default, all peripheral clocks are enabled during SLEEP mode.
AnnaBridge 126:abea610beb85 2070 */
AnnaBridge 126:abea610beb85 2071 #define __HAL_RCC_FMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FMCLPEN))
AnnaBridge 126:abea610beb85 2072 #define __HAL_RCC_FMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FMCLPEN))
AnnaBridge 126:abea610beb85 2073
AnnaBridge 126:abea610beb85 2074 #define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_QSPILPEN))
AnnaBridge 126:abea610beb85 2075 #define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_QSPILPEN))
AnnaBridge 126:abea610beb85 2076
AnnaBridge 126:abea610beb85 2077 /** @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
AnnaBridge 126:abea610beb85 2078 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
AnnaBridge 126:abea610beb85 2079 * power consumption.
AnnaBridge 126:abea610beb85 2080 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
AnnaBridge 126:abea610beb85 2081 * @note By default, all peripheral clocks are enabled during SLEEP mode.
AnnaBridge 126:abea610beb85 2082 */
AnnaBridge 126:abea610beb85 2083 #define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM2LPEN))
AnnaBridge 126:abea610beb85 2084 #define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM3LPEN))
AnnaBridge 126:abea610beb85 2085 #define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM4LPEN))
AnnaBridge 126:abea610beb85 2086 #define __HAL_RCC_TIM5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM5LPEN))
AnnaBridge 126:abea610beb85 2087 #define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM6LPEN))
AnnaBridge 126:abea610beb85 2088 #define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM7LPEN))
AnnaBridge 126:abea610beb85 2089 #define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM12LPEN))
AnnaBridge 126:abea610beb85 2090 #define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM13LPEN))
AnnaBridge 126:abea610beb85 2091 #define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM14LPEN))
AnnaBridge 126:abea610beb85 2092 #define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_LPTIM1LPEN))
AnnaBridge 126:abea610beb85 2093 #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
AnnaBridge 126:abea610beb85 2094 #define __HAL_RCC_CAN3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN3LPEN))
AnnaBridge 126:abea610beb85 2095 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
AnnaBridge 126:abea610beb85 2096 #define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI2LPEN))
AnnaBridge 126:abea610beb85 2097 #define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN))
AnnaBridge 126:abea610beb85 2098 #define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART2LPEN))
AnnaBridge 126:abea610beb85 2099 #define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART3LPEN))
AnnaBridge 126:abea610beb85 2100 #define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART4LPEN))
AnnaBridge 126:abea610beb85 2101 #define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART5LPEN))
AnnaBridge 126:abea610beb85 2102 #define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C1LPEN))
AnnaBridge 126:abea610beb85 2103 #define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C2LPEN))
AnnaBridge 126:abea610beb85 2104 #define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C3LPEN))
AnnaBridge 126:abea610beb85 2105 #define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN1LPEN))
AnnaBridge 126:abea610beb85 2106 #define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_DACLPEN))
AnnaBridge 126:abea610beb85 2107 #define __HAL_RCC_UART7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART7LPEN))
AnnaBridge 126:abea610beb85 2108 #define __HAL_RCC_UART8_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART8LPEN))
AnnaBridge 126:abea610beb85 2109
AnnaBridge 126:abea610beb85 2110 #define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN))
AnnaBridge 126:abea610beb85 2111 #define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN))
AnnaBridge 126:abea610beb85 2112 #define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN))
AnnaBridge 126:abea610beb85 2113 #define __HAL_RCC_TIM5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM5LPEN))
AnnaBridge 126:abea610beb85 2114 #define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN))
AnnaBridge 126:abea610beb85 2115 #define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN))
AnnaBridge 126:abea610beb85 2116 #define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN))
AnnaBridge 126:abea610beb85 2117 #define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN))
AnnaBridge 126:abea610beb85 2118 #define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN))
AnnaBridge 126:abea610beb85 2119 #define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_LPTIM1LPEN))
AnnaBridge 126:abea610beb85 2120 #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
AnnaBridge 126:abea610beb85 2121 #define __HAL_RCC_CAN3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN3LPEN))
AnnaBridge 126:abea610beb85 2122 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
AnnaBridge 126:abea610beb85 2123 #define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI2LPEN))
AnnaBridge 126:abea610beb85 2124 #define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN))
AnnaBridge 126:abea610beb85 2125 #define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART2LPEN))
AnnaBridge 126:abea610beb85 2126 #define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN))
AnnaBridge 126:abea610beb85 2127 #define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN))
AnnaBridge 126:abea610beb85 2128 #define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN))
AnnaBridge 126:abea610beb85 2129 #define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C1LPEN))
AnnaBridge 126:abea610beb85 2130 #define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C2LPEN))
AnnaBridge 126:abea610beb85 2131 #define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN))
AnnaBridge 126:abea610beb85 2132 #define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN))
AnnaBridge 126:abea610beb85 2133 #define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN))
AnnaBridge 126:abea610beb85 2134 #define __HAL_RCC_UART7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART7LPEN))
AnnaBridge 126:abea610beb85 2135 #define __HAL_RCC_UART8_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART8LPEN))
AnnaBridge 126:abea610beb85 2136
<> 139:856d2700e60b 2137 #if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) ||\
<> 139:856d2700e60b 2138 defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) ||\
<> 139:856d2700e60b 2139 defined (STM32F779xx)
<> 139:856d2700e60b 2140 #define __HAL_RCC_RTC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_RTCLPEN))
<> 139:856d2700e60b 2141 #define __HAL_RCC_RTC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_RTCLPEN))
<> 139:856d2700e60b 2142 #endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx ||
<> 139:856d2700e60b 2143 STM32F769xx || STM32F777xx || STM32F779xx */
<> 139:856d2700e60b 2144
<> 139:856d2700e60b 2145 #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\
<> 139:856d2700e60b 2146 defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
<> 139:856d2700e60b 2147 #define __HAL_RCC_SPDIFRX_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPDIFRXLPEN))
<> 139:856d2700e60b 2148 #define __HAL_RCC_I2C4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C4LPEN))
<> 139:856d2700e60b 2149 #define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN2LPEN))
<> 139:856d2700e60b 2150 #define __HAL_RCC_CEC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CECLPEN))
<> 139:856d2700e60b 2151
<> 139:856d2700e60b 2152 #define __HAL_RCC_SPDIFRX_CLK_SLEEP_DISABLE()(RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPDIFRXLPEN))
<> 139:856d2700e60b 2153 #define __HAL_RCC_I2C4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C4LPEN))
<> 139:856d2700e60b 2154 #define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN))
<> 139:856d2700e60b 2155 #define __HAL_RCC_CEC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CECLPEN))
<> 139:856d2700e60b 2156 #endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
<> 139:856d2700e60b 2157
AnnaBridge 126:abea610beb85 2158 /** @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
AnnaBridge 126:abea610beb85 2159 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
AnnaBridge 126:abea610beb85 2160 * power consumption.
AnnaBridge 126:abea610beb85 2161 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
AnnaBridge 126:abea610beb85 2162 * @note By default, all peripheral clocks are enabled during SLEEP mode.
AnnaBridge 126:abea610beb85 2163 */
AnnaBridge 126:abea610beb85 2164 #define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM1LPEN))
AnnaBridge 126:abea610beb85 2165 #define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM8LPEN))
AnnaBridge 126:abea610beb85 2166 #define __HAL_RCC_USART1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_USART1LPEN))
AnnaBridge 126:abea610beb85 2167 #define __HAL_RCC_USART6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_USART6LPEN))
AnnaBridge 126:abea610beb85 2168 #define __HAL_RCC_ADC1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC1LPEN))
AnnaBridge 126:abea610beb85 2169 #define __HAL_RCC_ADC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC2LPEN))
AnnaBridge 126:abea610beb85 2170 #define __HAL_RCC_ADC3_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC3LPEN))
AnnaBridge 126:abea610beb85 2171 #define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SDMMC1LPEN))
AnnaBridge 126:abea610beb85 2172 #define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI1LPEN))
AnnaBridge 126:abea610beb85 2173 #define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI4LPEN))
AnnaBridge 126:abea610beb85 2174 #define __HAL_RCC_TIM9_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM9LPEN))
AnnaBridge 126:abea610beb85 2175 #define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM10LPEN))
AnnaBridge 126:abea610beb85 2176 #define __HAL_RCC_TIM11_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM11LPEN))
AnnaBridge 126:abea610beb85 2177 #define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI5LPEN))
AnnaBridge 126:abea610beb85 2178 #define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SAI1LPEN))
AnnaBridge 126:abea610beb85 2179 #define __HAL_RCC_SAI2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SAI2LPEN))
AnnaBridge 126:abea610beb85 2180 #if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
AnnaBridge 126:abea610beb85 2181 #define __HAL_RCC_LTDC_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_LTDCLPEN))
AnnaBridge 126:abea610beb85 2182 #endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
AnnaBridge 126:abea610beb85 2183
AnnaBridge 126:abea610beb85 2184 #define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM1LPEN))
AnnaBridge 126:abea610beb85 2185 #define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN))
AnnaBridge 126:abea610beb85 2186 #define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART1LPEN))
AnnaBridge 126:abea610beb85 2187 #define __HAL_RCC_USART6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART6LPEN))
AnnaBridge 126:abea610beb85 2188 #define __HAL_RCC_ADC1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC1LPEN))
AnnaBridge 126:abea610beb85 2189 #define __HAL_RCC_ADC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC2LPEN))
AnnaBridge 126:abea610beb85 2190 #define __HAL_RCC_ADC3_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC3LPEN))
AnnaBridge 126:abea610beb85 2191 #define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDMMC1LPEN))
AnnaBridge 126:abea610beb85 2192 #define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI1LPEN))
AnnaBridge 126:abea610beb85 2193 #define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN))
AnnaBridge 126:abea610beb85 2194 #define __HAL_RCC_TIM9_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM9LPEN))
AnnaBridge 126:abea610beb85 2195 #define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN))
AnnaBridge 126:abea610beb85 2196 #define __HAL_RCC_TIM11_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM11LPEN))
AnnaBridge 126:abea610beb85 2197 #define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN))
AnnaBridge 126:abea610beb85 2198 #define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI1LPEN))
AnnaBridge 126:abea610beb85 2199 #define __HAL_RCC_SAI2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI2LPEN))
AnnaBridge 126:abea610beb85 2200 #if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
AnnaBridge 126:abea610beb85 2201 #define __HAL_RCC_LTDC_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_LTDCLPEN))
AnnaBridge 126:abea610beb85 2202 #endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
AnnaBridge 126:abea610beb85 2203 #if defined (STM32F769xx) || defined (STM32F779xx)
AnnaBridge 126:abea610beb85 2204 #define __HAL_RCC_DSI_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_DSILPEN))
AnnaBridge 126:abea610beb85 2205 #define __HAL_RCC_DSI_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_DSILPEN))
AnnaBridge 126:abea610beb85 2206 #endif /* STM32F769xx || STM32F779xx */
AnnaBridge 126:abea610beb85 2207 #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
AnnaBridge 126:abea610beb85 2208 #define __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_DFSDM1LPEN))
AnnaBridge 126:abea610beb85 2209 #define __HAL_RCC_MDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_MDIOLPEN))
AnnaBridge 126:abea610beb85 2210 #define __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_DFSDM1LPEN))
AnnaBridge 126:abea610beb85 2211 #define __HAL_RCC_MDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_MDIOLPEN))
AnnaBridge 126:abea610beb85 2212 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
<> 139:856d2700e60b 2213 #if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\
<> 139:856d2700e60b 2214 defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
<> 139:856d2700e60b 2215 #define __HAL_RCC_SDMMC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SDMMC2LPEN))
<> 139:856d2700e60b 2216 #define __HAL_RCC_SDMMC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDMMC2LPEN))
<> 139:856d2700e60b 2217 #endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
<> 139:856d2700e60b 2218
<> 139:856d2700e60b 2219 #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\
<> 139:856d2700e60b 2220 defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
<> 139:856d2700e60b 2221 #define __HAL_RCC_SPI6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI6LPEN))
<> 139:856d2700e60b 2222 #define __HAL_RCC_SPI6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI6LPEN))
<> 139:856d2700e60b 2223 #endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
AnnaBridge 126:abea610beb85 2224 /**
AnnaBridge 126:abea610beb85 2225 * @}
AnnaBridge 126:abea610beb85 2226 */
AnnaBridge 126:abea610beb85 2227
AnnaBridge 126:abea610beb85 2228 /** @defgroup RCC_Clock_Sleep_Enable_Disable_Status AHB/APB Peripheral Clock Sleep Enable Disable Status
AnnaBridge 126:abea610beb85 2229 * @brief Get the enable or disable status of the AHB/APB peripheral clock during Low Power (Sleep) mode.
AnnaBridge 126:abea610beb85 2230 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
AnnaBridge 126:abea610beb85 2231 * power consumption.
AnnaBridge 126:abea610beb85 2232 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
AnnaBridge 126:abea610beb85 2233 * @note By default, all peripheral clocks are enabled during SLEEP mode.
AnnaBridge 126:abea610beb85 2234 * @{
AnnaBridge 126:abea610beb85 2235 */
AnnaBridge 126:abea610beb85 2236
AnnaBridge 126:abea610beb85 2237 /** @brief Get the enable or disable status of the AHB1 peripheral clock during Low Power (Sleep) mode.
AnnaBridge 126:abea610beb85 2238 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
AnnaBridge 126:abea610beb85 2239 * power consumption.
AnnaBridge 126:abea610beb85 2240 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
AnnaBridge 126:abea610beb85 2241 * @note By default, all peripheral clocks are enabled during SLEEP mode.
AnnaBridge 126:abea610beb85 2242 */
AnnaBridge 126:abea610beb85 2243 #define __HAL_RCC_FLITF_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_FLITFLPEN)) != RESET)
AnnaBridge 126:abea610beb85 2244 #define __HAL_RCC_AXI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_AXILPEN)) != RESET)
AnnaBridge 126:abea610beb85 2245 #define __HAL_RCC_SRAM1_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_SRAM1LPEN)) != RESET)
AnnaBridge 126:abea610beb85 2246 #define __HAL_RCC_SRAM2_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_SRAM2LPEN)) != RESET)
AnnaBridge 126:abea610beb85 2247 #define __HAL_RCC_BKPSRAM_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_BKPSRAMLPEN)) != RESET)
AnnaBridge 126:abea610beb85 2248 #define __HAL_RCC_DTCM_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DTCMLPEN)) != RESET)
AnnaBridge 126:abea610beb85 2249 #define __HAL_RCC_DMA2_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2LPEN)) != RESET)
AnnaBridge 126:abea610beb85 2250 #define __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_OTGHSLPEN)) != RESET)
AnnaBridge 126:abea610beb85 2251 #define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_OTGHSULPILPEN)) != RESET)
AnnaBridge 126:abea610beb85 2252 #define __HAL_RCC_GPIOA_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOALPEN)) != RESET)
AnnaBridge 126:abea610beb85 2253 #define __HAL_RCC_GPIOB_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOBLPEN)) != RESET)
AnnaBridge 126:abea610beb85 2254 #define __HAL_RCC_GPIOC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOCLPEN)) != RESET)
AnnaBridge 126:abea610beb85 2255 #define __HAL_RCC_GPIOD_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIODLPEN)) != RESET)
AnnaBridge 126:abea610beb85 2256 #define __HAL_RCC_GPIOE_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOELPEN)) != RESET)
AnnaBridge 126:abea610beb85 2257 #define __HAL_RCC_GPIOF_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOFLPEN)) != RESET)
AnnaBridge 126:abea610beb85 2258 #define __HAL_RCC_GPIOG_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOGLPEN)) != RESET)
AnnaBridge 126:abea610beb85 2259 #define __HAL_RCC_GPIOH_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOHLPEN)) != RESET)
AnnaBridge 126:abea610beb85 2260 #define __HAL_RCC_GPIOI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOILPEN)) != RESET)
AnnaBridge 126:abea610beb85 2261
AnnaBridge 126:abea610beb85 2262 #define __HAL_RCC_FLITF_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_FLITFLPEN)) == RESET)
AnnaBridge 126:abea610beb85 2263 #define __HAL_RCC_AXI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_AXILPEN)) == RESET)
AnnaBridge 126:abea610beb85 2264 #define __HAL_RCC_SRAM1_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_SRAM1LPEN)) == RESET)
AnnaBridge 126:abea610beb85 2265 #define __HAL_RCC_SRAM2_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_SRAM2LPEN)) == RESET)
AnnaBridge 126:abea610beb85 2266 #define __HAL_RCC_BKPSRAM_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_BKPSRAMLPEN)) == RESET)
AnnaBridge 126:abea610beb85 2267 #define __HAL_RCC_DTCM_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DTCMLPEN)) == RESET)
AnnaBridge 126:abea610beb85 2268 #define __HAL_RCC_DMA2_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2LPEN)) == RESET)
AnnaBridge 126:abea610beb85 2269 #define __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_OTGHSLPEN)) == RESET)
AnnaBridge 126:abea610beb85 2270 #define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_OTGHSULPILPEN)) == RESET)
AnnaBridge 126:abea610beb85 2271 #define __HAL_RCC_GPIOA_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOALPEN)) == RESET)
AnnaBridge 126:abea610beb85 2272 #define __HAL_RCC_GPIOB_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOBLPEN)) == RESET)
AnnaBridge 126:abea610beb85 2273 #define __HAL_RCC_GPIOC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOCLPEN)) == RESET)
AnnaBridge 126:abea610beb85 2274 #define __HAL_RCC_GPIOD_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIODLPEN)) == RESET)
AnnaBridge 126:abea610beb85 2275 #define __HAL_RCC_GPIOE_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOELPEN)) == RESET)
AnnaBridge 126:abea610beb85 2276 #define __HAL_RCC_GPIOF_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOFLPEN)) == RESET)
AnnaBridge 126:abea610beb85 2277 #define __HAL_RCC_GPIOG_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOGLPEN)) == RESET)
AnnaBridge 126:abea610beb85 2278 #define __HAL_RCC_GPIOH_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOHLPEN)) == RESET)
AnnaBridge 126:abea610beb85 2279 #define __HAL_RCC_GPIOI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOILPEN)) == RESET)
<> 139:856d2700e60b 2280
<> 139:856d2700e60b 2281 #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\
<> 139:856d2700e60b 2282 defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
<> 139:856d2700e60b 2283 #define __HAL_RCC_DMA2D_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2DLPEN)) != RESET)
<> 139:856d2700e60b 2284 #define __HAL_RCC_ETHMAC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACLPEN)) != RESET)
<> 139:856d2700e60b 2285 #define __HAL_RCC_ETHMACTX_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACTXLPEN)) != RESET)
<> 139:856d2700e60b 2286 #define __HAL_RCC_ETHMACRX_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACRXLPEN)) != RESET)
<> 139:856d2700e60b 2287 #define __HAL_RCC_ETHMACPTP_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACPTPLPEN)) != RESET)
<> 139:856d2700e60b 2288 #define __HAL_RCC_GPIOJ_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOJLPEN)) != RESET)
<> 139:856d2700e60b 2289 #define __HAL_RCC_GPIOK_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOKLPEN)) != RESET)
<> 139:856d2700e60b 2290
<> 139:856d2700e60b 2291 #define __HAL_RCC_DMA2D_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2DLPEN)) == RESET)
<> 139:856d2700e60b 2292 #define __HAL_RCC_ETHMAC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACLPEN)) == RESET)
<> 139:856d2700e60b 2293 #define __HAL_RCC_ETHMACTX_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACTXLPEN)) == RESET)
<> 139:856d2700e60b 2294 #define __HAL_RCC_ETHMACRX_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACRXLPEN)) == RESET)
<> 139:856d2700e60b 2295 #define __HAL_RCC_ETHMACPTP_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACPTPLPEN)) == RESET)
AnnaBridge 126:abea610beb85 2296 #define __HAL_RCC_GPIOJ_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOJLPEN)) == RESET)
AnnaBridge 126:abea610beb85 2297 #define __HAL_RCC_GPIOK_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOKLPEN)) == RESET)
<> 139:856d2700e60b 2298 #endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
AnnaBridge 126:abea610beb85 2299
AnnaBridge 126:abea610beb85 2300 /** @brief Get the enable or disable status of the AHB2 peripheral clock during Low Power (Sleep) mode.
AnnaBridge 126:abea610beb85 2301 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
AnnaBridge 126:abea610beb85 2302 * power consumption.
AnnaBridge 126:abea610beb85 2303 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
AnnaBridge 126:abea610beb85 2304 * @note By default, all peripheral clocks are enabled during SLEEP mode.
AnnaBridge 126:abea610beb85 2305 */
<> 139:856d2700e60b 2306 #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\
<> 139:856d2700e60b 2307 defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
AnnaBridge 126:abea610beb85 2308 #define __HAL_RCC_DCMI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DCMILPEN)) != RESET)
AnnaBridge 126:abea610beb85 2309 #define __HAL_RCC_DCMI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DCMILPEN)) == RESET)
<> 139:856d2700e60b 2310 #endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
AnnaBridge 126:abea610beb85 2311
AnnaBridge 126:abea610beb85 2312 #if defined(STM32F767xx) || defined(STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
AnnaBridge 126:abea610beb85 2313 #define __HAL_RCC_JPEG_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_JPEGLPEN)) != RESET)
AnnaBridge 126:abea610beb85 2314 #define __HAL_RCC_JPEG_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_JPEGLPEN)) == RESET)
AnnaBridge 126:abea610beb85 2315 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
AnnaBridge 126:abea610beb85 2316
AnnaBridge 126:abea610beb85 2317 #define __HAL_RCC_RNG_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_RNGLPEN)) != RESET)
AnnaBridge 126:abea610beb85 2318 #define __HAL_RCC_RNG_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_RNGLPEN)) == RESET)
AnnaBridge 126:abea610beb85 2319
AnnaBridge 126:abea610beb85 2320 #define __HAL_RCC_USB_OTG_FS_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_OTGFSLPEN)) != RESET)
AnnaBridge 126:abea610beb85 2321 #define __HAL_RCC_USB_OTG_FS_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_OTGFSLPEN)) == RESET)
AnnaBridge 126:abea610beb85 2322
AnnaBridge 126:abea610beb85 2323 #if defined(STM32F756xx) || defined (STM32F777xx) || defined (STM32F779xx)
AnnaBridge 126:abea610beb85 2324 #define __HAL_RCC_CRYP_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_CRYPLPEN)) != RESET)
AnnaBridge 126:abea610beb85 2325 #define __HAL_RCC_HASH_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_HASHLPEN)) != RESET)
AnnaBridge 126:abea610beb85 2326
AnnaBridge 126:abea610beb85 2327 #define __HAL_RCC_CRYP_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_CRYPLPEN)) == RESET)
AnnaBridge 126:abea610beb85 2328 #define __HAL_RCC_HASH_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_HASHLPEN)) == RESET)
AnnaBridge 126:abea610beb85 2329 #endif /* STM32F756xx || STM32F777xx || STM32F779xx */
<> 139:856d2700e60b 2330
<> 139:856d2700e60b 2331 #if defined(STM32F732xx) || defined (STM32F733xx)
<> 139:856d2700e60b 2332 #define __HAL_RCC_AES_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_AESLPEN)) != RESET)
<> 139:856d2700e60b 2333 #define __HAL_RCC_AES_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_AESLPEN)) == RESET)
<> 139:856d2700e60b 2334 #endif /* STM32F732xx || STM32F733xx */
AnnaBridge 126:abea610beb85 2335
AnnaBridge 126:abea610beb85 2336 /** @brief Get the enable or disable status of the AHB3 peripheral clock during Low Power (Sleep) mode.
AnnaBridge 126:abea610beb85 2337 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
AnnaBridge 126:abea610beb85 2338 * power consumption.
AnnaBridge 126:abea610beb85 2339 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
AnnaBridge 126:abea610beb85 2340 * @note By default, all peripheral clocks are enabled during SLEEP mode.
AnnaBridge 126:abea610beb85 2341 */
AnnaBridge 126:abea610beb85 2342 #define __HAL_RCC_FMC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & (RCC_AHB3LPENR_FMCLPEN)) != RESET)
AnnaBridge 126:abea610beb85 2343 #define __HAL_RCC_FMC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & (RCC_AHB3LPENR_FMCLPEN)) == RESET)
AnnaBridge 126:abea610beb85 2344
AnnaBridge 126:abea610beb85 2345 #define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & (RCC_AHB3LPENR_QSPILPEN)) != RESET)
AnnaBridge 126:abea610beb85 2346 #define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & (RCC_AHB3LPENR_QSPILPEN)) == RESET)
AnnaBridge 126:abea610beb85 2347
AnnaBridge 126:abea610beb85 2348 /** @brief Get the enable or disable status of the APB1 peripheral clock during Low Power (Sleep) mode.
AnnaBridge 126:abea610beb85 2349 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
AnnaBridge 126:abea610beb85 2350 * power consumption.
AnnaBridge 126:abea610beb85 2351 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
AnnaBridge 126:abea610beb85 2352 * @note By default, all peripheral clocks are enabled during SLEEP mode.
AnnaBridge 126:abea610beb85 2353 */
AnnaBridge 126:abea610beb85 2354 #define __HAL_RCC_TIM2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM2LPEN)) != RESET)
AnnaBridge 126:abea610beb85 2355 #define __HAL_RCC_TIM3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM3LPEN)) != RESET)
AnnaBridge 126:abea610beb85 2356 #define __HAL_RCC_TIM4_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM4LPEN)) != RESET)
AnnaBridge 126:abea610beb85 2357 #define __HAL_RCC_TIM5_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM5LPEN)) != RESET)
AnnaBridge 126:abea610beb85 2358 #define __HAL_RCC_TIM6_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM6LPEN)) != RESET)
AnnaBridge 126:abea610beb85 2359 #define __HAL_RCC_TIM7_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM7LPEN)) != RESET)
AnnaBridge 126:abea610beb85 2360 #define __HAL_RCC_TIM12_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM12LPEN)) != RESET)
AnnaBridge 126:abea610beb85 2361 #define __HAL_RCC_TIM13_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM13LPEN)) != RESET)
AnnaBridge 126:abea610beb85 2362 #define __HAL_RCC_TIM14_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM14LPEN)) != RESET)
AnnaBridge 126:abea610beb85 2363 #define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_LPTIM1LPEN)) != RESET)
<> 139:856d2700e60b 2364 #if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) ||\
<> 139:856d2700e60b 2365 defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) ||\
<> 139:856d2700e60b 2366 defined (STM32F779xx)
<> 139:856d2700e60b 2367 #define __HAL_RCC_RTC_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_RTCLPEN)) != RESET)
<> 139:856d2700e60b 2368 #endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx ||
<> 139:856d2700e60b 2369 STM32F769xx || STM32F777xx || STM32F779xx */
AnnaBridge 126:abea610beb85 2370 #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
AnnaBridge 126:abea610beb85 2371 #define __HAL_RCC_CAN3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN3LPEN)) != RESET)
AnnaBridge 126:abea610beb85 2372 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
AnnaBridge 126:abea610beb85 2373 #define __HAL_RCC_SPI2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI2LPEN)) != RESET)
AnnaBridge 126:abea610beb85 2374 #define __HAL_RCC_SPI3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI3LPEN)) != RESET)
AnnaBridge 126:abea610beb85 2375 #define __HAL_RCC_USART2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_USART2LPEN)) != RESET)
AnnaBridge 126:abea610beb85 2376 #define __HAL_RCC_USART3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_USART3LPEN)) != RESET)
AnnaBridge 126:abea610beb85 2377 #define __HAL_RCC_UART4_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART4LPEN)) != RESET)
AnnaBridge 126:abea610beb85 2378 #define __HAL_RCC_UART5_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART5LPEN)) != RESET)
AnnaBridge 126:abea610beb85 2379 #define __HAL_RCC_I2C1_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C1LPEN)) != RESET)
AnnaBridge 126:abea610beb85 2380 #define __HAL_RCC_I2C2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C2LPEN)) != RESET)
AnnaBridge 126:abea610beb85 2381 #define __HAL_RCC_I2C3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C3LPEN)) != RESET)
AnnaBridge 126:abea610beb85 2382 #define __HAL_RCC_CAN1_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN1LPEN)) != RESET)
AnnaBridge 126:abea610beb85 2383 #define __HAL_RCC_DAC_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_DACLPEN)) != RESET)
AnnaBridge 126:abea610beb85 2384 #define __HAL_RCC_UART7_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART7LPEN)) != RESET)
AnnaBridge 126:abea610beb85 2385 #define __HAL_RCC_UART8_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART8LPEN)) != RESET)
AnnaBridge 126:abea610beb85 2386
AnnaBridge 126:abea610beb85 2387 #define __HAL_RCC_TIM2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM2LPEN)) == RESET)
AnnaBridge 126:abea610beb85 2388 #define __HAL_RCC_TIM3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM3LPEN)) == RESET)
AnnaBridge 126:abea610beb85 2389 #define __HAL_RCC_TIM4_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM4LPEN)) == RESET)
AnnaBridge 126:abea610beb85 2390 #define __HAL_RCC_TIM5_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM5LPEN)) == RESET)
AnnaBridge 126:abea610beb85 2391 #define __HAL_RCC_TIM6_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM6LPEN)) == RESET)
AnnaBridge 126:abea610beb85 2392 #define __HAL_RCC_TIM7_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM7LPEN)) == RESET)
AnnaBridge 126:abea610beb85 2393 #define __HAL_RCC_TIM12_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM12LPEN)) == RESET)
AnnaBridge 126:abea610beb85 2394 #define __HAL_RCC_TIM13_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM13LPEN)) == RESET)
AnnaBridge 126:abea610beb85 2395 #define __HAL_RCC_TIM14_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM14LPEN)) == RESET)
AnnaBridge 126:abea610beb85 2396 #define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_LPTIM1LPEN)) == RESET)
<> 139:856d2700e60b 2397 #if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) ||\
<> 139:856d2700e60b 2398 defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) ||\
<> 139:856d2700e60b 2399 defined (STM32F779xx)
<> 139:856d2700e60b 2400 #define __HAL_RCC_RTC_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_RTCLPEN)) == RESET)
<> 139:856d2700e60b 2401 #endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx ||
<> 139:856d2700e60b 2402 STM32F769xx || STM32F777xx || STM32F779xx */
AnnaBridge 126:abea610beb85 2403 #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
AnnaBridge 126:abea610beb85 2404 #define __HAL_RCC_CAN3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN3LPEN)) == RESET)
AnnaBridge 126:abea610beb85 2405 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
AnnaBridge 126:abea610beb85 2406 #define __HAL_RCC_SPI2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI2LPEN)) == RESET)
AnnaBridge 126:abea610beb85 2407 #define __HAL_RCC_SPI3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI3LPEN)) == RESET)
AnnaBridge 126:abea610beb85 2408 #define __HAL_RCC_USART2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_USART2LPEN)) == RESET)
AnnaBridge 126:abea610beb85 2409 #define __HAL_RCC_USART3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_USART3LPEN)) == RESET)
AnnaBridge 126:abea610beb85 2410 #define __HAL_RCC_UART4_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART4LPEN)) == RESET)
AnnaBridge 126:abea610beb85 2411 #define __HAL_RCC_UART5_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART5LPEN)) == RESET)
AnnaBridge 126:abea610beb85 2412 #define __HAL_RCC_I2C1_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C1LPEN)) == RESET)
AnnaBridge 126:abea610beb85 2413 #define __HAL_RCC_I2C2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C2LPEN)) == RESET)
AnnaBridge 126:abea610beb85 2414 #define __HAL_RCC_I2C3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C3LPEN)) == RESET)
AnnaBridge 126:abea610beb85 2415 #define __HAL_RCC_CAN1_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN1LPEN)) == RESET)
AnnaBridge 126:abea610beb85 2416 #define __HAL_RCC_DAC_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_DACLPEN)) == RESET)
AnnaBridge 126:abea610beb85 2417 #define __HAL_RCC_UART7_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART7LPEN)) == RESET)
AnnaBridge 126:abea610beb85 2418 #define __HAL_RCC_UART8_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART8LPEN)) == RESET)
AnnaBridge 126:abea610beb85 2419
<> 139:856d2700e60b 2420 #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\
<> 139:856d2700e60b 2421 defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
<> 139:856d2700e60b 2422 #define __HAL_RCC_SPDIFRX_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPDIFRXLPEN)) != RESET)
<> 139:856d2700e60b 2423 #define __HAL_RCC_I2C4_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C4LPEN)) != RESET)
<> 139:856d2700e60b 2424 #define __HAL_RCC_CAN2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN2LPEN)) != RESET)
<> 139:856d2700e60b 2425 #define __HAL_RCC_CEC_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CECLPEN)) != RESET)
<> 139:856d2700e60b 2426
<> 139:856d2700e60b 2427 #define __HAL_RCC_SPDIFRX_IS_CLK_SLEEP_DISABLED()((RCC->APB1LPENR & (RCC_APB1LPENR_SPDIFRXLPEN)) == RESET)
<> 139:856d2700e60b 2428 #define __HAL_RCC_I2C4_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C4LPEN)) == RESET)
<> 139:856d2700e60b 2429 #define __HAL_RCC_CAN2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN2LPEN)) == RESET)
<> 139:856d2700e60b 2430 #define __HAL_RCC_CEC_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CECLPEN)) == RESET)
<> 139:856d2700e60b 2431 #endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
<> 139:856d2700e60b 2432
AnnaBridge 126:abea610beb85 2433 /** @brief Get the enable or disable status of the APB2 peripheral clock during Low Power (Sleep) mode.
AnnaBridge 126:abea610beb85 2434 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
AnnaBridge 126:abea610beb85 2435 * power consumption.
AnnaBridge 126:abea610beb85 2436 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
AnnaBridge 126:abea610beb85 2437 * @note By default, all peripheral clocks are enabled during SLEEP mode.
AnnaBridge 126:abea610beb85 2438 */
AnnaBridge 126:abea610beb85 2439 #define __HAL_RCC_TIM1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM1LPEN)) != RESET)
AnnaBridge 126:abea610beb85 2440 #define __HAL_RCC_TIM8_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM8LPEN)) != RESET)
AnnaBridge 126:abea610beb85 2441 #define __HAL_RCC_USART1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART1LPEN)) != RESET)
AnnaBridge 126:abea610beb85 2442 #define __HAL_RCC_USART6_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART6LPEN)) != RESET)
AnnaBridge 126:abea610beb85 2443 #define __HAL_RCC_ADC1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC1LPEN)) != RESET)
AnnaBridge 126:abea610beb85 2444 #define __HAL_RCC_ADC2_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC2LPEN)) != RESET)
AnnaBridge 126:abea610beb85 2445 #define __HAL_RCC_ADC3_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC3LPEN)) != RESET)
AnnaBridge 126:abea610beb85 2446 #define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SDMMC1LPEN)) != RESET)
AnnaBridge 126:abea610beb85 2447 #define __HAL_RCC_SPI1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI1LPEN)) != RESET)
AnnaBridge 126:abea610beb85 2448 #define __HAL_RCC_SPI4_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI4LPEN)) != RESET)
AnnaBridge 126:abea610beb85 2449 #define __HAL_RCC_TIM9_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM9LPEN)) != RESET)
AnnaBridge 126:abea610beb85 2450 #define __HAL_RCC_TIM10_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM10LPEN)) != RESET)
AnnaBridge 126:abea610beb85 2451 #define __HAL_RCC_TIM11_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM11LPEN)) != RESET)
AnnaBridge 126:abea610beb85 2452 #define __HAL_RCC_SPI5_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI5LPEN)) != RESET)
AnnaBridge 126:abea610beb85 2453 #define __HAL_RCC_SAI1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI1LPEN)) != RESET)
AnnaBridge 126:abea610beb85 2454 #define __HAL_RCC_SAI2_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI2LPEN)) != RESET)
AnnaBridge 126:abea610beb85 2455 #if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
AnnaBridge 126:abea610beb85 2456 #define __HAL_RCC_LTDC_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_LTDCLPEN)) != RESET)
AnnaBridge 126:abea610beb85 2457 #endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
AnnaBridge 126:abea610beb85 2458 #if defined (STM32F769xx) || defined (STM32F779xx)
AnnaBridge 126:abea610beb85 2459 #define __HAL_RCC_DSI_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_DSILPEN)) != RESET)
AnnaBridge 126:abea610beb85 2460 #endif /* STM32F769xx || STM32F779xx */
<> 139:856d2700e60b 2461 #if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\
<> 139:856d2700e60b 2462 defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
<> 139:856d2700e60b 2463 #define __HAL_RCC_SDMMC2_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SDMMC2LPEN)) != RESET)
<> 139:856d2700e60b 2464 #endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
AnnaBridge 126:abea610beb85 2465 #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
AnnaBridge 126:abea610beb85 2466 #define __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_DFSDM1LPEN)) != RESET)
AnnaBridge 126:abea610beb85 2467 #define __HAL_RCC_MDIO_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_MDIOLPEN)) != RESET)
AnnaBridge 126:abea610beb85 2468 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
AnnaBridge 126:abea610beb85 2469
AnnaBridge 126:abea610beb85 2470 #define __HAL_RCC_TIM1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM1LPEN)) == RESET)
AnnaBridge 126:abea610beb85 2471 #define __HAL_RCC_TIM8_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM8LPEN)) == RESET)
AnnaBridge 126:abea610beb85 2472 #define __HAL_RCC_USART1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART1LPEN)) == RESET)
AnnaBridge 126:abea610beb85 2473 #define __HAL_RCC_USART6_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART6LPEN)) == RESET)
AnnaBridge 126:abea610beb85 2474 #define __HAL_RCC_ADC1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC1LPEN)) == RESET)
AnnaBridge 126:abea610beb85 2475 #define __HAL_RCC_ADC2_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC2LPEN)) == RESET)
AnnaBridge 126:abea610beb85 2476 #define __HAL_RCC_ADC3_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC3LPEN)) == RESET)
AnnaBridge 126:abea610beb85 2477 #define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SDMMC1LPEN)) == RESET)
AnnaBridge 126:abea610beb85 2478 #define __HAL_RCC_SPI1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI1LPEN)) == RESET)
AnnaBridge 126:abea610beb85 2479 #define __HAL_RCC_SPI4_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI4LPEN)) == RESET)
AnnaBridge 126:abea610beb85 2480 #define __HAL_RCC_TIM9_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM9LPEN)) == RESET)
AnnaBridge 126:abea610beb85 2481 #define __HAL_RCC_TIM10_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM10LPEN)) == RESET)
AnnaBridge 126:abea610beb85 2482 #define __HAL_RCC_TIM11_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM11LPEN)) == RESET)
AnnaBridge 126:abea610beb85 2483 #define __HAL_RCC_SPI5_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI5LPEN)) == RESET)
AnnaBridge 126:abea610beb85 2484 #define __HAL_RCC_SAI1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI1LPEN)) == RESET)
AnnaBridge 126:abea610beb85 2485 #define __HAL_RCC_SAI2_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI2LPEN)) == RESET)
AnnaBridge 126:abea610beb85 2486 #if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
AnnaBridge 126:abea610beb85 2487 #define __HAL_RCC_LTDC_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_LTDCLPEN)) == RESET)
AnnaBridge 126:abea610beb85 2488 #endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
AnnaBridge 126:abea610beb85 2489 #if defined (STM32F769xx) || defined (STM32F779xx)
AnnaBridge 126:abea610beb85 2490 #define __HAL_RCC_DSI_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_DSILPEN)) == RESET)
AnnaBridge 126:abea610beb85 2491 #endif /* STM32F769xx || STM32F779xx */
<> 139:856d2700e60b 2492 #if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\
<> 139:856d2700e60b 2493 defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
<> 139:856d2700e60b 2494 #define __HAL_RCC_SDMMC2_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SDMMC2LPEN)) == RESET)
<> 139:856d2700e60b 2495 #endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
AnnaBridge 126:abea610beb85 2496 #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
AnnaBridge 126:abea610beb85 2497 #define __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_DFSDM1LPEN)) == RESET)
AnnaBridge 126:abea610beb85 2498 #define __HAL_RCC_MDIO_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_MDIOLPEN)) == RESET)
AnnaBridge 126:abea610beb85 2499 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
<> 139:856d2700e60b 2500
<> 139:856d2700e60b 2501 #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\
<> 139:856d2700e60b 2502 defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
<> 139:856d2700e60b 2503 #define __HAL_RCC_SPI6_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI6LPEN)) != RESET)
<> 139:856d2700e60b 2504 #define __HAL_RCC_SPI6_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI6LPEN)) == RESET)
<> 139:856d2700e60b 2505 #endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
AnnaBridge 126:abea610beb85 2506 /**
AnnaBridge 126:abea610beb85 2507 * @}
AnnaBridge 126:abea610beb85 2508 */
AnnaBridge 126:abea610beb85 2509
AnnaBridge 126:abea610beb85 2510 /*------------------------------- PLL Configuration --------------------------*/
AnnaBridge 126:abea610beb85 2511 #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
AnnaBridge 126:abea610beb85 2512 /** @brief Macro to configure the main PLL clock source, multiplication and division factors.
AnnaBridge 126:abea610beb85 2513 * @note This function must be used only when the main PLL is disabled.
AnnaBridge 126:abea610beb85 2514 * @param __RCC_PLLSource__: specifies the PLL entry clock source.
AnnaBridge 126:abea610beb85 2515 * This parameter can be one of the following values:
AnnaBridge 126:abea610beb85 2516 * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
AnnaBridge 126:abea610beb85 2517 * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
AnnaBridge 126:abea610beb85 2518 * @note This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S.
AnnaBridge 126:abea610beb85 2519 * @param __PLLM__: specifies the division factor for PLL VCO input clock
AnnaBridge 126:abea610beb85 2520 * This parameter must be a number between Min_Data = 2 and Max_Data = 63.
AnnaBridge 126:abea610beb85 2521 * @note You have to set the PLLM parameter correctly to ensure that the VCO input
AnnaBridge 126:abea610beb85 2522 * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
AnnaBridge 126:abea610beb85 2523 * of 2 MHz to limit PLL jitter.
AnnaBridge 126:abea610beb85 2524 * @param __PLLN__: specifies the multiplication factor for PLL VCO output clock
AnnaBridge 126:abea610beb85 2525 * This parameter must be a number between Min_Data = 50 and Max_Data = 432.
AnnaBridge 126:abea610beb85 2526 * @note You have to set the PLLN parameter correctly to ensure that the VCO
AnnaBridge 126:abea610beb85 2527 * output frequency is between 100 and 432 MHz.
AnnaBridge 126:abea610beb85 2528 * @param __PLLP__: specifies the division factor for main system clock (SYSCLK)
AnnaBridge 126:abea610beb85 2529 * This parameter must be a number in the range {2, 4, 6, or 8}.
AnnaBridge 126:abea610beb85 2530 * @note You have to set the PLLP parameter correctly to not exceed 216 MHz on
AnnaBridge 126:abea610beb85 2531 * the System clock frequency.
AnnaBridge 126:abea610beb85 2532 * @param __PLLQ__: specifies the division factor for OTG FS, SDMMC and RNG clocks
AnnaBridge 126:abea610beb85 2533 * This parameter must be a number between Min_Data = 2 and Max_Data = 15.
AnnaBridge 126:abea610beb85 2534 * @note If the USB OTG FS is used in your application, you have to set the
AnnaBridge 126:abea610beb85 2535 * PLLQ parameter correctly to have 48 MHz clock for the USB. However,
AnnaBridge 126:abea610beb85 2536 * the SDMMC and RNG need a frequency lower than or equal to 48 MHz to work
AnnaBridge 126:abea610beb85 2537 * correctly.
AnnaBridge 126:abea610beb85 2538 * @param __PLLR__: specifies the division factor for DSI clock
AnnaBridge 126:abea610beb85 2539 * This parameter must be a number between Min_Data = 2 and Max_Data = 7.
AnnaBridge 126:abea610beb85 2540 */
AnnaBridge 126:abea610beb85 2541 #define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__,__PLLR__) \
AnnaBridge 126:abea610beb85 2542 (RCC->PLLCFGR = ((__RCC_PLLSource__) | (__PLLM__) | \
AnnaBridge 126:abea610beb85 2543 ((__PLLN__) << POSITION_VAL(RCC_PLLCFGR_PLLN)) | \
AnnaBridge 126:abea610beb85 2544 ((((__PLLP__) >> 1) -1) << POSITION_VAL(RCC_PLLCFGR_PLLP)) | \
AnnaBridge 126:abea610beb85 2545 ((__PLLQ__) << POSITION_VAL(RCC_PLLCFGR_PLLQ)) | \
AnnaBridge 126:abea610beb85 2546 ((__PLLR__) << POSITION_VAL(RCC_PLLCFGR_PLLR))))
AnnaBridge 126:abea610beb85 2547 #else
AnnaBridge 126:abea610beb85 2548 /** @brief Macro to configure the main PLL clock source, multiplication and division factors.
AnnaBridge 126:abea610beb85 2549 * @note This function must be used only when the main PLL is disabled.
AnnaBridge 126:abea610beb85 2550 * @param __RCC_PLLSource__: specifies the PLL entry clock source.
AnnaBridge 126:abea610beb85 2551 * This parameter can be one of the following values:
AnnaBridge 126:abea610beb85 2552 * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
AnnaBridge 126:abea610beb85 2553 * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
AnnaBridge 126:abea610beb85 2554 * @note This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S.
AnnaBridge 126:abea610beb85 2555 * @param __PLLM__: specifies the division factor for PLL VCO input clock
AnnaBridge 126:abea610beb85 2556 * This parameter must be a number between Min_Data = 2 and Max_Data = 63.
AnnaBridge 126:abea610beb85 2557 * @note You have to set the PLLM parameter correctly to ensure that the VCO input
AnnaBridge 126:abea610beb85 2558 * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
AnnaBridge 126:abea610beb85 2559 * of 2 MHz to limit PLL jitter.
AnnaBridge 126:abea610beb85 2560 * @param __PLLN__: specifies the multiplication factor for PLL VCO output clock
AnnaBridge 126:abea610beb85 2561 * This parameter must be a number between Min_Data = 50 and Max_Data = 432.
AnnaBridge 126:abea610beb85 2562 * @note You have to set the PLLN parameter correctly to ensure that the VCO
AnnaBridge 126:abea610beb85 2563 * output frequency is between 100 and 432 MHz.
AnnaBridge 126:abea610beb85 2564 * @param __PLLP__: specifies the division factor for main system clock (SYSCLK)
AnnaBridge 126:abea610beb85 2565 * This parameter must be a number in the range {2, 4, 6, or 8}.
AnnaBridge 126:abea610beb85 2566 * @note You have to set the PLLP parameter correctly to not exceed 216 MHz on
AnnaBridge 126:abea610beb85 2567 * the System clock frequency.
AnnaBridge 126:abea610beb85 2568 * @param __PLLQ__: specifies the division factor for OTG FS, SDMMC and RNG clocks
AnnaBridge 126:abea610beb85 2569 * This parameter must be a number between Min_Data = 2 and Max_Data = 15.
AnnaBridge 126:abea610beb85 2570 * @note If the USB OTG FS is used in your application, you have to set the
AnnaBridge 126:abea610beb85 2571 * PLLQ parameter correctly to have 48 MHz clock for the USB. However,
AnnaBridge 126:abea610beb85 2572 * the SDMMC and RNG need a frequency lower than or equal to 48 MHz to work
AnnaBridge 126:abea610beb85 2573 * correctly.
AnnaBridge 126:abea610beb85 2574 */
AnnaBridge 126:abea610beb85 2575 #define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__) \
AnnaBridge 126:abea610beb85 2576 (RCC->PLLCFGR = (0x20000000 | (__RCC_PLLSource__) | (__PLLM__)| \
AnnaBridge 126:abea610beb85 2577 ((__PLLN__) << POSITION_VAL(RCC_PLLCFGR_PLLN)) | \
AnnaBridge 126:abea610beb85 2578 ((((__PLLP__) >> 1) -1) << POSITION_VAL(RCC_PLLCFGR_PLLP)) | \
AnnaBridge 126:abea610beb85 2579 ((__PLLQ__) << POSITION_VAL(RCC_PLLCFGR_PLLQ))))
AnnaBridge 126:abea610beb85 2580 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
AnnaBridge 126:abea610beb85 2581 /*---------------------------------------------------------------------------------------------*/
AnnaBridge 126:abea610beb85 2582
AnnaBridge 126:abea610beb85 2583 /** @brief Macro to configure the Timers clocks prescalers
AnnaBridge 126:abea610beb85 2584 * @param __PRESC__ : specifies the Timers clocks prescalers selection
AnnaBridge 126:abea610beb85 2585 * This parameter can be one of the following values:
AnnaBridge 126:abea610beb85 2586 * @arg RCC_TIMPRES_DESACTIVATED: The Timers kernels clocks prescaler is
AnnaBridge 126:abea610beb85 2587 * equal to HPRE if PPREx is corresponding to division by 1 or 2,
AnnaBridge 126:abea610beb85 2588 * else it is equal to [(HPRE * PPREx) / 2] if PPREx is corresponding to
AnnaBridge 126:abea610beb85 2589 * division by 4 or more.
AnnaBridge 126:abea610beb85 2590 * @arg RCC_TIMPRES_ACTIVATED: The Timers kernels clocks prescaler is
AnnaBridge 126:abea610beb85 2591 * equal to HPRE if PPREx is corresponding to division by 1, 2 or 4,
AnnaBridge 126:abea610beb85 2592 * else it is equal to [(HPRE * PPREx) / 4] if PPREx is corresponding
AnnaBridge 126:abea610beb85 2593 * to division by 8 or more.
AnnaBridge 126:abea610beb85 2594 */
AnnaBridge 126:abea610beb85 2595 #define __HAL_RCC_TIMCLKPRESCALER(__PRESC__) do {RCC->DCKCFGR1 &= ~(RCC_DCKCFGR1_TIMPRE);\
AnnaBridge 126:abea610beb85 2596 RCC->DCKCFGR1 |= (__PRESC__); \
AnnaBridge 126:abea610beb85 2597 }while(0)
AnnaBridge 126:abea610beb85 2598
AnnaBridge 126:abea610beb85 2599 /** @brief Macros to Enable or Disable the PLLISAI.
AnnaBridge 126:abea610beb85 2600 * @note The PLLSAI is disabled by hardware when entering STOP and STANDBY modes.
AnnaBridge 126:abea610beb85 2601 */
AnnaBridge 126:abea610beb85 2602 #define __HAL_RCC_PLLSAI_ENABLE() (RCC->CR |= (RCC_CR_PLLSAION))
AnnaBridge 126:abea610beb85 2603 #define __HAL_RCC_PLLSAI_DISABLE() (RCC->CR &= ~(RCC_CR_PLLSAION))
AnnaBridge 126:abea610beb85 2604
<> 139:856d2700e60b 2605 #if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx)
<> 139:856d2700e60b 2606 /** @brief Macro to configure the PLLSAI clock multiplication and division factors.
<> 139:856d2700e60b 2607 * @note This function must be used only when the PLLSAI is disabled.
<> 139:856d2700e60b 2608 * @note PLLSAI clock source is common with the main PLL (configured in
<> 139:856d2700e60b 2609 * RCC_PLLConfig function )
<> 139:856d2700e60b 2610 * @param __PLLSAIN__: specifies the multiplication factor for PLLSAI VCO output clock.
<> 139:856d2700e60b 2611 * This parameter must be a number between Min_Data = 50 and Max_Data = 432.
<> 139:856d2700e60b 2612 * @note You have to set the PLLSAIN parameter correctly to ensure that the VCO
<> 139:856d2700e60b 2613 * output frequency is between Min_Data = 100 and Max_Data = 432 MHz.
<> 139:856d2700e60b 2614 * @param __PLLSAIP__: specifies the division factor for USB, RNG, SDMMC clocks
<> 139:856d2700e60b 2615 * This parameter can be a value of @ref RCCEx_PLLSAIP_Clock_Divider.
<> 139:856d2700e60b 2616 * @param __PLLSAIQ__: specifies the division factor for SAI clock
<> 139:856d2700e60b 2617 * This parameter must be a number between Min_Data = 2 and Max_Data = 15.
<> 139:856d2700e60b 2618 */
<> 139:856d2700e60b 2619 #define __HAL_RCC_PLLSAI_CONFIG(__PLLSAIN__, __PLLSAIP__, __PLLSAIQ__) \
<> 139:856d2700e60b 2620 (RCC->PLLSAICFGR = ((__PLLSAIN__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIN)) |\
<> 139:856d2700e60b 2621 ((__PLLSAIP__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIP)) |\
<> 139:856d2700e60b 2622 ((__PLLSAIQ__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ)))
<> 139:856d2700e60b 2623
<> 139:856d2700e60b 2624 /** @brief Macro to configure the PLLI2S clock multiplication and division factors.
<> 139:856d2700e60b 2625 * @note This macro must be used only when the PLLI2S is disabled.
<> 139:856d2700e60b 2626 * @note PLLI2S clock source is common with the main PLL (configured in
<> 139:856d2700e60b 2627 * HAL_RCC_ClockConfig() API)
<> 139:856d2700e60b 2628 * @param __PLLI2SN__: specifies the multiplication factor for PLLI2S VCO output clock.
<> 139:856d2700e60b 2629 * This parameter must be a number between Min_Data = 50 and Max_Data = 432.
<> 139:856d2700e60b 2630 * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO
<> 139:856d2700e60b 2631 * output frequency is between Min_Data = 100 and Max_Data = 432 MHz.
<> 139:856d2700e60b 2632 * @param __PLLI2SQ__: specifies the division factor for SAI clock.
<> 139:856d2700e60b 2633 * This parameter must be a number between Min_Data = 2 and Max_Data = 15.
<> 139:856d2700e60b 2634 * @param __PLLI2SR__: specifies the division factor for I2S clock
<> 139:856d2700e60b 2635 * This parameter must be a number between Min_Data = 2 and Max_Data = 7.
<> 139:856d2700e60b 2636 * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
<> 139:856d2700e60b 2637 * on the I2S clock frequency.
<> 139:856d2700e60b 2638 */
<> 139:856d2700e60b 2639 #define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SN__, __PLLI2SQ__, __PLLI2SR__) \
<> 139:856d2700e60b 2640 (RCC->PLLI2SCFGR = ((__PLLI2SN__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN)) |\
<> 139:856d2700e60b 2641 ((__PLLI2SQ__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SQ)) |\
<> 139:856d2700e60b 2642 ((__PLLI2SR__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR)))
<> 139:856d2700e60b 2643 #else
AnnaBridge 126:abea610beb85 2644 /** @brief Macro to configure the PLLSAI clock multiplication and division factors.
AnnaBridge 126:abea610beb85 2645 * @note This function must be used only when the PLLSAI is disabled.
AnnaBridge 126:abea610beb85 2646 * @note PLLSAI clock source is common with the main PLL (configured in
AnnaBridge 126:abea610beb85 2647 * RCC_PLLConfig function )
AnnaBridge 126:abea610beb85 2648 * @param __PLLSAIN__: specifies the multiplication factor for PLLSAI VCO output clock.
AnnaBridge 126:abea610beb85 2649 * This parameter must be a number between Min_Data = 50 and Max_Data = 432.
AnnaBridge 126:abea610beb85 2650 * @note You have to set the PLLSAIN parameter correctly to ensure that the VCO
AnnaBridge 126:abea610beb85 2651 * output frequency is between Min_Data = 100 and Max_Data = 432 MHz.
AnnaBridge 126:abea610beb85 2652 * @param __PLLSAIP__: specifies the division factor for USB, RNG, SDMMC clocks
AnnaBridge 126:abea610beb85 2653 * This parameter can be a value of @ref RCCEx_PLLSAIP_Clock_Divider.
AnnaBridge 126:abea610beb85 2654 * @param __PLLSAIQ__: specifies the division factor for SAI clock
AnnaBridge 126:abea610beb85 2655 * This parameter must be a number between Min_Data = 2 and Max_Data = 15.
AnnaBridge 126:abea610beb85 2656 * @param __PLLSAIR__: specifies the division factor for LTDC clock
AnnaBridge 126:abea610beb85 2657 * This parameter must be a number between Min_Data = 2 and Max_Data = 7.
AnnaBridge 126:abea610beb85 2658 */
AnnaBridge 126:abea610beb85 2659 #define __HAL_RCC_PLLSAI_CONFIG(__PLLSAIN__, __PLLSAIP__, __PLLSAIQ__, __PLLSAIR__) \
AnnaBridge 126:abea610beb85 2660 (RCC->PLLSAICFGR = ((__PLLSAIN__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIN)) |\
AnnaBridge 126:abea610beb85 2661 ((__PLLSAIP__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIP)) |\
AnnaBridge 126:abea610beb85 2662 ((__PLLSAIQ__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ)) |\
AnnaBridge 126:abea610beb85 2663 ((__PLLSAIR__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIR)))
AnnaBridge 126:abea610beb85 2664
AnnaBridge 126:abea610beb85 2665 /** @brief Macro to configure the PLLI2S clock multiplication and division factors.
AnnaBridge 126:abea610beb85 2666 * @note This macro must be used only when the PLLI2S is disabled.
AnnaBridge 126:abea610beb85 2667 * @note PLLI2S clock source is common with the main PLL (configured in
AnnaBridge 126:abea610beb85 2668 * HAL_RCC_ClockConfig() API)
AnnaBridge 126:abea610beb85 2669 * @param __PLLI2SN__: specifies the multiplication factor for PLLI2S VCO output clock.
AnnaBridge 126:abea610beb85 2670 * This parameter must be a number between Min_Data = 50 and Max_Data = 432.
AnnaBridge 126:abea610beb85 2671 * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO
AnnaBridge 126:abea610beb85 2672 * output frequency is between Min_Data = 100 and Max_Data = 432 MHz.
AnnaBridge 126:abea610beb85 2673 * @param __PLLI2SP__: specifies the division factor for SPDDIF-RX clock.
AnnaBridge 126:abea610beb85 2674 * This parameter can be a value of @ref RCCEx_PLLI2SP_Clock_Divider.
AnnaBridge 126:abea610beb85 2675 * @param __PLLI2SQ__: specifies the division factor for SAI clock.
AnnaBridge 126:abea610beb85 2676 * This parameter must be a number between Min_Data = 2 and Max_Data = 15.
AnnaBridge 126:abea610beb85 2677 * @param __PLLI2SR__: specifies the division factor for I2S clock
AnnaBridge 126:abea610beb85 2678 * This parameter must be a number between Min_Data = 2 and Max_Data = 7.
AnnaBridge 126:abea610beb85 2679 * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
AnnaBridge 126:abea610beb85 2680 * on the I2S clock frequency.
AnnaBridge 126:abea610beb85 2681 */
AnnaBridge 126:abea610beb85 2682 #define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SN__, __PLLI2SP__, __PLLI2SQ__, __PLLI2SR__) \
AnnaBridge 126:abea610beb85 2683 (RCC->PLLI2SCFGR = ((__PLLI2SN__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN)) |\
AnnaBridge 126:abea610beb85 2684 ((__PLLI2SP__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SP)) |\
AnnaBridge 126:abea610beb85 2685 ((__PLLI2SQ__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SQ)) |\
AnnaBridge 126:abea610beb85 2686 ((__PLLI2SR__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR)))
<> 139:856d2700e60b 2687 #endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx */
AnnaBridge 126:abea610beb85 2688
AnnaBridge 126:abea610beb85 2689 /** @brief Macro to configure the SAI clock Divider coming from PLLI2S.
AnnaBridge 126:abea610beb85 2690 * @note This function must be called before enabling the PLLI2S.
AnnaBridge 126:abea610beb85 2691 * @param __PLLI2SDivQ__: specifies the PLLI2S division factor for SAI1 clock .
AnnaBridge 126:abea610beb85 2692 * This parameter must be a number between 1 and 32.
AnnaBridge 126:abea610beb85 2693 * SAI1 clock frequency = f(PLLI2SQ) / __PLLI2SDivQ__
AnnaBridge 126:abea610beb85 2694 */
AnnaBridge 126:abea610beb85 2695 #define __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(__PLLI2SDivQ__) (MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_PLLI2SDIVQ, (__PLLI2SDivQ__)-1))
AnnaBridge 126:abea610beb85 2696
AnnaBridge 126:abea610beb85 2697 /** @brief Macro to configure the SAI clock Divider coming from PLLSAI.
AnnaBridge 126:abea610beb85 2698 * @note This function must be called before enabling the PLLSAI.
AnnaBridge 126:abea610beb85 2699 * @param __PLLSAIDivQ__: specifies the PLLSAI division factor for SAI1 clock .
AnnaBridge 126:abea610beb85 2700 * This parameter must be a number between Min_Data = 1 and Max_Data = 32.
AnnaBridge 126:abea610beb85 2701 * SAI1 clock frequency = f(PLLSAIQ) / __PLLSAIDivQ__
AnnaBridge 126:abea610beb85 2702 */
AnnaBridge 126:abea610beb85 2703 #define __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(__PLLSAIDivQ__) (MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_PLLSAIDIVQ, ((__PLLSAIDivQ__)-1)<<8))
AnnaBridge 126:abea610beb85 2704
<> 139:856d2700e60b 2705 #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\
<> 139:856d2700e60b 2706 defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
AnnaBridge 126:abea610beb85 2707 /** @brief Macro to configure the LTDC clock Divider coming from PLLSAI.
AnnaBridge 126:abea610beb85 2708 * @note This function must be called before enabling the PLLSAI.
AnnaBridge 126:abea610beb85 2709 * @param __PLLSAIDivR__: specifies the PLLSAI division factor for LTDC clock .
AnnaBridge 126:abea610beb85 2710 * This parameter can be a value of @ref RCCEx_PLLSAI_DIVR.
AnnaBridge 126:abea610beb85 2711 * LTDC clock frequency = f(PLLSAIR) / __PLLSAIDivR__
AnnaBridge 126:abea610beb85 2712 */
AnnaBridge 126:abea610beb85 2713 #define __HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(__PLLSAIDivR__)\
AnnaBridge 126:abea610beb85 2714 MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_PLLSAIDIVR, (uint32_t)(__PLLSAIDivR__))
<> 139:856d2700e60b 2715 #endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
AnnaBridge 126:abea610beb85 2716
AnnaBridge 126:abea610beb85 2717 /** @brief Macro to configure SAI1 clock source selection.
AnnaBridge 126:abea610beb85 2718 * @note This function must be called before enabling PLLSAI, PLLI2S and
AnnaBridge 126:abea610beb85 2719 * the SAI clock.
AnnaBridge 126:abea610beb85 2720 * @param __SOURCE__: specifies the SAI1 clock source.
AnnaBridge 126:abea610beb85 2721 * This parameter can be one of the following values:
AnnaBridge 126:abea610beb85 2722 * @arg RCC_SAI1CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used
AnnaBridge 126:abea610beb85 2723 * as SAI1 clock.
AnnaBridge 126:abea610beb85 2724 * @arg RCC_SAI1CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used
AnnaBridge 126:abea610beb85 2725 * as SAI1 clock.
AnnaBridge 126:abea610beb85 2726 * @arg RCC_SAI1CLKSOURCE_PIN: External clock mapped on the I2S_CKIN pin
AnnaBridge 126:abea610beb85 2727 * used as SAI1 clock.
AnnaBridge 126:abea610beb85 2728 * @arg RCC_SAI1CLKSOURCE_PLLSRC: HSI or HSE depending from PLL Source clock
AnnaBridge 126:abea610beb85 2729 * used as SAI1 clock.
AnnaBridge 126:abea610beb85 2730 * @note The RCC_SAI1CLKSOURCE_PLLSRC value is only available with STM32F767/769/777/779xx Devices
AnnaBridge 126:abea610beb85 2731 */
AnnaBridge 126:abea610beb85 2732 #define __HAL_RCC_SAI1_CONFIG(__SOURCE__)\
AnnaBridge 126:abea610beb85 2733 MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_SAI1SEL, (uint32_t)(__SOURCE__))
AnnaBridge 126:abea610beb85 2734
AnnaBridge 126:abea610beb85 2735 /** @brief Macro to get the SAI1 clock source.
AnnaBridge 126:abea610beb85 2736 * @retval The clock source can be one of the following values:
AnnaBridge 126:abea610beb85 2737 * @arg RCC_SAI1CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used
AnnaBridge 126:abea610beb85 2738 * as SAI1 clock.
AnnaBridge 126:abea610beb85 2739 * @arg RCC_SAI1CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used
AnnaBridge 126:abea610beb85 2740 * as SAI1 clock.
AnnaBridge 126:abea610beb85 2741 * @arg RCC_SAI1CLKSOURCE_PIN: External clock mapped on the I2S_CKIN pin
AnnaBridge 126:abea610beb85 2742 * used as SAI1 clock.
AnnaBridge 126:abea610beb85 2743 * @arg RCC_SAI1CLKSOURCE_PLLSRC: HSI or HSE depending from PLL Source clock
AnnaBridge 126:abea610beb85 2744 * used as SAI1 clock.
AnnaBridge 126:abea610beb85 2745 * @note The RCC_SAI1CLKSOURCE_PLLSRC value is only available with STM32F767/769/777/779xx Devices
AnnaBridge 126:abea610beb85 2746 */
AnnaBridge 126:abea610beb85 2747 #define __HAL_RCC_GET_SAI1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR1, RCC_DCKCFGR1_SAI1SEL)))
AnnaBridge 126:abea610beb85 2748
AnnaBridge 126:abea610beb85 2749
AnnaBridge 126:abea610beb85 2750 /** @brief Macro to configure SAI2 clock source selection.
AnnaBridge 126:abea610beb85 2751 * @note This function must be called before enabling PLLSAI, PLLI2S and
AnnaBridge 126:abea610beb85 2752 * the SAI clock.
AnnaBridge 126:abea610beb85 2753 * @param __SOURCE__: specifies the SAI2 clock source.
AnnaBridge 126:abea610beb85 2754 * This parameter can be one of the following values:
AnnaBridge 126:abea610beb85 2755 * @arg RCC_SAI2CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used
AnnaBridge 126:abea610beb85 2756 * as SAI2 clock.
AnnaBridge 126:abea610beb85 2757 * @arg RCC_SAI2CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used
AnnaBridge 126:abea610beb85 2758 * as SAI2 clock.
AnnaBridge 126:abea610beb85 2759 * @arg RCC_SAI2CLKSOURCE_PIN: External clock mapped on the I2S_CKIN pin
AnnaBridge 126:abea610beb85 2760 * used as SAI2 clock.
AnnaBridge 126:abea610beb85 2761 * @arg RCC_SAI2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL Source clock
AnnaBridge 126:abea610beb85 2762 * used as SAI2 clock.
AnnaBridge 126:abea610beb85 2763 * @note The RCC_SAI2CLKSOURCE_PLLSRC value is only available with STM32F767/769/777/779xx Devices
AnnaBridge 126:abea610beb85 2764 */
AnnaBridge 126:abea610beb85 2765 #define __HAL_RCC_SAI2_CONFIG(__SOURCE__)\
AnnaBridge 126:abea610beb85 2766 MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_SAI2SEL, (uint32_t)(__SOURCE__))
AnnaBridge 126:abea610beb85 2767
AnnaBridge 126:abea610beb85 2768
AnnaBridge 126:abea610beb85 2769 /** @brief Macro to get the SAI2 clock source.
AnnaBridge 126:abea610beb85 2770 * @retval The clock source can be one of the following values:
AnnaBridge 126:abea610beb85 2771 * @arg RCC_SAI2CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used
AnnaBridge 126:abea610beb85 2772 * as SAI2 clock.
AnnaBridge 126:abea610beb85 2773 * @arg RCC_SAI2CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used
AnnaBridge 126:abea610beb85 2774 * as SAI2 clock.
AnnaBridge 126:abea610beb85 2775 * @arg RCC_SAI2CLKSOURCE_PIN: External clock mapped on the I2S_CKIN pin
AnnaBridge 126:abea610beb85 2776 * used as SAI2 clock.
AnnaBridge 126:abea610beb85 2777 * @arg RCC_SAI2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL Source clock
AnnaBridge 126:abea610beb85 2778 * used as SAI2 clock.
AnnaBridge 126:abea610beb85 2779 * @note The RCC_SAI2CLKSOURCE_PLLSRC value is only available with STM32F767/769/777/779xx Devices
AnnaBridge 126:abea610beb85 2780 */
AnnaBridge 126:abea610beb85 2781 #define __HAL_RCC_GET_SAI2_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR1, RCC_DCKCFGR1_SAI2SEL)))
AnnaBridge 126:abea610beb85 2782
AnnaBridge 126:abea610beb85 2783
AnnaBridge 126:abea610beb85 2784 /** @brief Enable PLLSAI_RDY interrupt.
AnnaBridge 126:abea610beb85 2785 */
AnnaBridge 126:abea610beb85 2786 #define __HAL_RCC_PLLSAI_ENABLE_IT() (RCC->CIR |= (RCC_CIR_PLLSAIRDYIE))
AnnaBridge 126:abea610beb85 2787
AnnaBridge 126:abea610beb85 2788 /** @brief Disable PLLSAI_RDY interrupt.
AnnaBridge 126:abea610beb85 2789 */
AnnaBridge 126:abea610beb85 2790 #define __HAL_RCC_PLLSAI_DISABLE_IT() (RCC->CIR &= ~(RCC_CIR_PLLSAIRDYIE))
AnnaBridge 126:abea610beb85 2791
AnnaBridge 126:abea610beb85 2792 /** @brief Clear the PLLSAI RDY interrupt pending bits.
AnnaBridge 126:abea610beb85 2793 */
AnnaBridge 126:abea610beb85 2794 #define __HAL_RCC_PLLSAI_CLEAR_IT() (RCC->CIR |= (RCC_CIR_PLLSAIRDYF))
AnnaBridge 126:abea610beb85 2795
AnnaBridge 126:abea610beb85 2796 /** @brief Check the PLLSAI RDY interrupt has occurred or not.
AnnaBridge 126:abea610beb85 2797 * @retval The new state (TRUE or FALSE).
AnnaBridge 126:abea610beb85 2798 */
AnnaBridge 126:abea610beb85 2799 #define __HAL_RCC_PLLSAI_GET_IT() ((RCC->CIR & (RCC_CIR_PLLSAIRDYIE)) == (RCC_CIR_PLLSAIRDYIE))
AnnaBridge 126:abea610beb85 2800
AnnaBridge 126:abea610beb85 2801 /** @brief Check PLLSAI RDY flag is set or not.
AnnaBridge 126:abea610beb85 2802 * @retval The new state (TRUE or FALSE).
AnnaBridge 126:abea610beb85 2803 */
AnnaBridge 126:abea610beb85 2804 #define __HAL_RCC_PLLSAI_GET_FLAG() ((RCC->CR & (RCC_CR_PLLSAIRDY)) == (RCC_CR_PLLSAIRDY))
AnnaBridge 126:abea610beb85 2805
AnnaBridge 126:abea610beb85 2806 /** @brief Macro to Get I2S clock source selection.
AnnaBridge 126:abea610beb85 2807 * @retval The clock source can be one of the following values:
AnnaBridge 126:abea610beb85 2808 * @arg RCC_I2SCLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR used as I2S clock.
AnnaBridge 126:abea610beb85 2809 * @arg RCC_I2SCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as I2S clock source
AnnaBridge 126:abea610beb85 2810 */
AnnaBridge 126:abea610beb85 2811 #define __HAL_RCC_GET_I2SCLKSOURCE() (READ_BIT(RCC->CFGR, RCC_CFGR_I2SSRC))
AnnaBridge 126:abea610beb85 2812
AnnaBridge 126:abea610beb85 2813 /** @brief Macro to configure the I2C1 clock (I2C1CLK).
AnnaBridge 126:abea610beb85 2814 *
AnnaBridge 126:abea610beb85 2815 * @param __I2C1_CLKSOURCE__: specifies the I2C1 clock source.
AnnaBridge 126:abea610beb85 2816 * This parameter can be one of the following values:
AnnaBridge 126:abea610beb85 2817 * @arg RCC_I2C1CLKSOURCE_PCLK1: PCLK1 selected as I2C1 clock
AnnaBridge 126:abea610beb85 2818 * @arg RCC_I2C1CLKSOURCE_HSI: HSI selected as I2C1 clock
AnnaBridge 126:abea610beb85 2819 * @arg RCC_I2C1CLKSOURCE_SYSCLK: System Clock selected as I2C1 clock
AnnaBridge 126:abea610beb85 2820 */
AnnaBridge 126:abea610beb85 2821 #define __HAL_RCC_I2C1_CONFIG(__I2C1_CLKSOURCE__) \
AnnaBridge 126:abea610beb85 2822 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C1SEL, (uint32_t)(__I2C1_CLKSOURCE__))
AnnaBridge 126:abea610beb85 2823
AnnaBridge 126:abea610beb85 2824 /** @brief Macro to get the I2C1 clock source.
AnnaBridge 126:abea610beb85 2825 * @retval The clock source can be one of the following values:
AnnaBridge 126:abea610beb85 2826 * @arg RCC_I2C1CLKSOURCE_PCLK1: PCLK1 selected as I2C1 clock
AnnaBridge 126:abea610beb85 2827 * @arg RCC_I2C1CLKSOURCE_HSI: HSI selected as I2C1 clock
AnnaBridge 126:abea610beb85 2828 * @arg RCC_I2C1CLKSOURCE_SYSCLK: System Clock selected as I2C1 clock
AnnaBridge 126:abea610beb85 2829 */
AnnaBridge 126:abea610beb85 2830 #define __HAL_RCC_GET_I2C1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C1SEL)))
AnnaBridge 126:abea610beb85 2831
AnnaBridge 126:abea610beb85 2832 /** @brief Macro to configure the I2C2 clock (I2C2CLK).
AnnaBridge 126:abea610beb85 2833 *
AnnaBridge 126:abea610beb85 2834 * @param __I2C2_CLKSOURCE__: specifies the I2C2 clock source.
AnnaBridge 126:abea610beb85 2835 * This parameter can be one of the following values:
AnnaBridge 126:abea610beb85 2836 * @arg RCC_I2C2CLKSOURCE_PCLK1: PCLK1 selected as I2C2 clock
AnnaBridge 126:abea610beb85 2837 * @arg RCC_I2C2CLKSOURCE_HSI: HSI selected as I2C2 clock
AnnaBridge 126:abea610beb85 2838 * @arg RCC_I2C2CLKSOURCE_SYSCLK: System Clock selected as I2C2 clock
AnnaBridge 126:abea610beb85 2839 */
AnnaBridge 126:abea610beb85 2840 #define __HAL_RCC_I2C2_CONFIG(__I2C2_CLKSOURCE__) \
AnnaBridge 126:abea610beb85 2841 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C2SEL, (uint32_t)(__I2C2_CLKSOURCE__))
AnnaBridge 126:abea610beb85 2842
AnnaBridge 126:abea610beb85 2843 /** @brief Macro to get the I2C2 clock source.
AnnaBridge 126:abea610beb85 2844 * @retval The clock source can be one of the following values:
AnnaBridge 126:abea610beb85 2845 * @arg RCC_I2C2CLKSOURCE_PCLK1: PCLK1 selected as I2C2 clock
AnnaBridge 126:abea610beb85 2846 * @arg RCC_I2C2CLKSOURCE_HSI: HSI selected as I2C2 clock
AnnaBridge 126:abea610beb85 2847 * @arg RCC_I2C2CLKSOURCE_SYSCLK: System Clock selected as I2C2 clock
AnnaBridge 126:abea610beb85 2848 */
AnnaBridge 126:abea610beb85 2849 #define __HAL_RCC_GET_I2C2_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C2SEL)))
AnnaBridge 126:abea610beb85 2850
AnnaBridge 126:abea610beb85 2851 /** @brief Macro to configure the I2C3 clock (I2C3CLK).
AnnaBridge 126:abea610beb85 2852 *
AnnaBridge 126:abea610beb85 2853 * @param __I2C3_CLKSOURCE__: specifies the I2C3 clock source.
AnnaBridge 126:abea610beb85 2854 * This parameter can be one of the following values:
AnnaBridge 126:abea610beb85 2855 * @arg RCC_I2C3CLKSOURCE_PCLK1: PCLK1 selected as I2C3 clock
AnnaBridge 126:abea610beb85 2856 * @arg RCC_I2C3CLKSOURCE_HSI: HSI selected as I2C3 clock
AnnaBridge 126:abea610beb85 2857 * @arg RCC_I2C3CLKSOURCE_SYSCLK: System Clock selected as I2C3 clock
AnnaBridge 126:abea610beb85 2858 */
AnnaBridge 126:abea610beb85 2859 #define __HAL_RCC_I2C3_CONFIG(__I2C3_CLKSOURCE__) \
AnnaBridge 126:abea610beb85 2860 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C3SEL, (uint32_t)(__I2C3_CLKSOURCE__))
AnnaBridge 126:abea610beb85 2861
AnnaBridge 126:abea610beb85 2862 /** @brief macro to get the I2C3 clock source.
AnnaBridge 126:abea610beb85 2863 * @retval The clock source can be one of the following values:
AnnaBridge 126:abea610beb85 2864 * @arg RCC_I2C3CLKSOURCE_PCLK1: PCLK1 selected as I2C3 clock
AnnaBridge 126:abea610beb85 2865 * @arg RCC_I2C3CLKSOURCE_HSI: HSI selected as I2C3 clock
AnnaBridge 126:abea610beb85 2866 * @arg RCC_I2C3CLKSOURCE_SYSCLK: System Clock selected as I2C3 clock
AnnaBridge 126:abea610beb85 2867 */
AnnaBridge 126:abea610beb85 2868 #define __HAL_RCC_GET_I2C3_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C3SEL)))
AnnaBridge 126:abea610beb85 2869
AnnaBridge 126:abea610beb85 2870 /** @brief Macro to configure the I2C4 clock (I2C4CLK).
AnnaBridge 126:abea610beb85 2871 *
AnnaBridge 126:abea610beb85 2872 * @param __I2C4_CLKSOURCE__: specifies the I2C4 clock source.
AnnaBridge 126:abea610beb85 2873 * This parameter can be one of the following values:
AnnaBridge 126:abea610beb85 2874 * @arg RCC_I2C4CLKSOURCE_PCLK1: PCLK1 selected as I2C4 clock
AnnaBridge 126:abea610beb85 2875 * @arg RCC_I2C4CLKSOURCE_HSI: HSI selected as I2C4 clock
AnnaBridge 126:abea610beb85 2876 * @arg RCC_I2C4CLKSOURCE_SYSCLK: System Clock selected as I2C4 clock
AnnaBridge 126:abea610beb85 2877 */
AnnaBridge 126:abea610beb85 2878 #define __HAL_RCC_I2C4_CONFIG(__I2C4_CLKSOURCE__) \
AnnaBridge 126:abea610beb85 2879 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C4SEL, (uint32_t)(__I2C4_CLKSOURCE__))
AnnaBridge 126:abea610beb85 2880
AnnaBridge 126:abea610beb85 2881 /** @brief macro to get the I2C4 clock source.
AnnaBridge 126:abea610beb85 2882 * @retval The clock source can be one of the following values:
AnnaBridge 126:abea610beb85 2883 * @arg RCC_I2C4CLKSOURCE_PCLK1: PCLK1 selected as I2C4 clock
AnnaBridge 126:abea610beb85 2884 * @arg RCC_I2C4CLKSOURCE_HSI: HSI selected as I2C4 clock
AnnaBridge 126:abea610beb85 2885 * @arg RCC_I2C4CLKSOURCE_SYSCLK: System Clock selected as I2C4 clock
AnnaBridge 126:abea610beb85 2886 */
AnnaBridge 126:abea610beb85 2887 #define __HAL_RCC_GET_I2C4_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C4SEL)))
AnnaBridge 126:abea610beb85 2888
AnnaBridge 126:abea610beb85 2889 /** @brief Macro to configure the USART1 clock (USART1CLK).
AnnaBridge 126:abea610beb85 2890 *
AnnaBridge 126:abea610beb85 2891 * @param __USART1_CLKSOURCE__: specifies the USART1 clock source.
AnnaBridge 126:abea610beb85 2892 * This parameter can be one of the following values:
AnnaBridge 126:abea610beb85 2893 * @arg RCC_USART1CLKSOURCE_PCLK2: PCLK2 selected as USART1 clock
AnnaBridge 126:abea610beb85 2894 * @arg RCC_USART1CLKSOURCE_HSI: HSI selected as USART1 clock
AnnaBridge 126:abea610beb85 2895 * @arg RCC_USART1CLKSOURCE_SYSCLK: System Clock selected as USART1 clock
AnnaBridge 126:abea610beb85 2896 * @arg RCC_USART1CLKSOURCE_LSE: LSE selected as USART1 clock
AnnaBridge 126:abea610beb85 2897 */
AnnaBridge 126:abea610beb85 2898 #define __HAL_RCC_USART1_CONFIG(__USART1_CLKSOURCE__) \
AnnaBridge 126:abea610beb85 2899 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_USART1SEL, (uint32_t)(__USART1_CLKSOURCE__))
AnnaBridge 126:abea610beb85 2900
AnnaBridge 126:abea610beb85 2901 /** @brief macro to get the USART1 clock source.
AnnaBridge 126:abea610beb85 2902 * @retval The clock source can be one of the following values:
AnnaBridge 126:abea610beb85 2903 * @arg RCC_USART1CLKSOURCE_PCLK2: PCLK2 selected as USART1 clock
AnnaBridge 126:abea610beb85 2904 * @arg RCC_USART1CLKSOURCE_HSI: HSI selected as USART1 clock
AnnaBridge 126:abea610beb85 2905 * @arg RCC_USART1CLKSOURCE_SYSCLK: System Clock selected as USART1 clock
AnnaBridge 126:abea610beb85 2906 * @arg RCC_USART1CLKSOURCE_LSE: LSE selected as USART1 clock
AnnaBridge 126:abea610beb85 2907 */
AnnaBridge 126:abea610beb85 2908 #define __HAL_RCC_GET_USART1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_USART1SEL)))
AnnaBridge 126:abea610beb85 2909
AnnaBridge 126:abea610beb85 2910 /** @brief Macro to configure the USART2 clock (USART2CLK).
AnnaBridge 126:abea610beb85 2911 *
AnnaBridge 126:abea610beb85 2912 * @param __USART2_CLKSOURCE__: specifies the USART2 clock source.
AnnaBridge 126:abea610beb85 2913 * This parameter can be one of the following values:
AnnaBridge 126:abea610beb85 2914 * @arg RCC_USART2CLKSOURCE_PCLK1: PCLK1 selected as USART2 clock
AnnaBridge 126:abea610beb85 2915 * @arg RCC_USART2CLKSOURCE_HSI: HSI selected as USART2 clock
AnnaBridge 126:abea610beb85 2916 * @arg RCC_USART2CLKSOURCE_SYSCLK: System Clock selected as USART2 clock
AnnaBridge 126:abea610beb85 2917 * @arg RCC_USART2CLKSOURCE_LSE: LSE selected as USART2 clock
AnnaBridge 126:abea610beb85 2918 */
AnnaBridge 126:abea610beb85 2919 #define __HAL_RCC_USART2_CONFIG(__USART2_CLKSOURCE__) \
AnnaBridge 126:abea610beb85 2920 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_USART2SEL, (uint32_t)(__USART2_CLKSOURCE__))
AnnaBridge 126:abea610beb85 2921
AnnaBridge 126:abea610beb85 2922 /** @brief macro to get the USART2 clock source.
AnnaBridge 126:abea610beb85 2923 * @retval The clock source can be one of the following values:
AnnaBridge 126:abea610beb85 2924 * @arg RCC_USART2CLKSOURCE_PCLK1: PCLK1 selected as USART2 clock
AnnaBridge 126:abea610beb85 2925 * @arg RCC_USART2CLKSOURCE_HSI: HSI selected as USART2 clock
AnnaBridge 126:abea610beb85 2926 * @arg RCC_USART2CLKSOURCE_SYSCLK: System Clock selected as USART2 clock
AnnaBridge 126:abea610beb85 2927 * @arg RCC_USART2CLKSOURCE_LSE: LSE selected as USART2 clock
AnnaBridge 126:abea610beb85 2928 */
AnnaBridge 126:abea610beb85 2929 #define __HAL_RCC_GET_USART2_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_USART2SEL)))
AnnaBridge 126:abea610beb85 2930
AnnaBridge 126:abea610beb85 2931 /** @brief Macro to configure the USART3 clock (USART3CLK).
AnnaBridge 126:abea610beb85 2932 *
AnnaBridge 126:abea610beb85 2933 * @param __USART3_CLKSOURCE__: specifies the USART3 clock source.
AnnaBridge 126:abea610beb85 2934 * This parameter can be one of the following values:
AnnaBridge 126:abea610beb85 2935 * @arg RCC_USART3CLKSOURCE_PCLK1: PCLK1 selected as USART3 clock
AnnaBridge 126:abea610beb85 2936 * @arg RCC_USART3CLKSOURCE_HSI: HSI selected as USART3 clock
AnnaBridge 126:abea610beb85 2937 * @arg RCC_USART3CLKSOURCE_SYSCLK: System Clock selected as USART3 clock
AnnaBridge 126:abea610beb85 2938 * @arg RCC_USART3CLKSOURCE_LSE: LSE selected as USART3 clock
AnnaBridge 126:abea610beb85 2939 */
AnnaBridge 126:abea610beb85 2940 #define __HAL_RCC_USART3_CONFIG(__USART3_CLKSOURCE__) \
AnnaBridge 126:abea610beb85 2941 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_USART3SEL, (uint32_t)(__USART3_CLKSOURCE__))
AnnaBridge 126:abea610beb85 2942
AnnaBridge 126:abea610beb85 2943 /** @brief macro to get the USART3 clock source.
AnnaBridge 126:abea610beb85 2944 * @retval The clock source can be one of the following values:
AnnaBridge 126:abea610beb85 2945 * @arg RCC_USART3CLKSOURCE_PCLK1: PCLK1 selected as USART3 clock
AnnaBridge 126:abea610beb85 2946 * @arg RCC_USART3CLKSOURCE_HSI: HSI selected as USART3 clock
AnnaBridge 126:abea610beb85 2947 * @arg RCC_USART3CLKSOURCE_SYSCLK: System Clock selected as USART3 clock
AnnaBridge 126:abea610beb85 2948 * @arg RCC_USART3CLKSOURCE_LSE: LSE selected as USART3 clock
AnnaBridge 126:abea610beb85 2949 */
AnnaBridge 126:abea610beb85 2950 #define __HAL_RCC_GET_USART3_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_USART3SEL)))
AnnaBridge 126:abea610beb85 2951
AnnaBridge 126:abea610beb85 2952 /** @brief Macro to configure the UART4 clock (UART4CLK).
AnnaBridge 126:abea610beb85 2953 *
AnnaBridge 126:abea610beb85 2954 * @param __UART4_CLKSOURCE__: specifies the UART4 clock source.
AnnaBridge 126:abea610beb85 2955 * This parameter can be one of the following values:
AnnaBridge 126:abea610beb85 2956 * @arg RCC_UART4CLKSOURCE_PCLK1: PCLK1 selected as UART4 clock
AnnaBridge 126:abea610beb85 2957 * @arg RCC_UART4CLKSOURCE_HSI: HSI selected as UART4 clock
AnnaBridge 126:abea610beb85 2958 * @arg RCC_UART4CLKSOURCE_SYSCLK: System Clock selected as UART4 clock
AnnaBridge 126:abea610beb85 2959 * @arg RCC_UART4CLKSOURCE_LSE: LSE selected as UART4 clock
AnnaBridge 126:abea610beb85 2960 */
AnnaBridge 126:abea610beb85 2961 #define __HAL_RCC_UART4_CONFIG(__UART4_CLKSOURCE__) \
AnnaBridge 126:abea610beb85 2962 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_UART4SEL, (uint32_t)(__UART4_CLKSOURCE__))
AnnaBridge 126:abea610beb85 2963
AnnaBridge 126:abea610beb85 2964 /** @brief macro to get the UART4 clock source.
AnnaBridge 126:abea610beb85 2965 * @retval The clock source can be one of the following values:
AnnaBridge 126:abea610beb85 2966 * @arg RCC_UART4CLKSOURCE_PCLK1: PCLK1 selected as UART4 clock
AnnaBridge 126:abea610beb85 2967 * @arg RCC_UART4CLKSOURCE_HSI: HSI selected as UART4 clock
AnnaBridge 126:abea610beb85 2968 * @arg RCC_UART4CLKSOURCE_SYSCLK: System Clock selected as UART4 clock
AnnaBridge 126:abea610beb85 2969 * @arg RCC_UART4CLKSOURCE_LSE: LSE selected as UART4 clock
AnnaBridge 126:abea610beb85 2970 */
AnnaBridge 126:abea610beb85 2971 #define __HAL_RCC_GET_UART4_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_UART4SEL)))
AnnaBridge 126:abea610beb85 2972
AnnaBridge 126:abea610beb85 2973 /** @brief Macro to configure the UART5 clock (UART5CLK).
AnnaBridge 126:abea610beb85 2974 *
AnnaBridge 126:abea610beb85 2975 * @param __UART5_CLKSOURCE__: specifies the UART5 clock source.
AnnaBridge 126:abea610beb85 2976 * This parameter can be one of the following values:
AnnaBridge 126:abea610beb85 2977 * @arg RCC_UART5CLKSOURCE_PCLK1: PCLK1 selected as UART5 clock
AnnaBridge 126:abea610beb85 2978 * @arg RCC_UART5CLKSOURCE_HSI: HSI selected as UART5 clock
AnnaBridge 126:abea610beb85 2979 * @arg RCC_UART5CLKSOURCE_SYSCLK: System Clock selected as UART5 clock
AnnaBridge 126:abea610beb85 2980 * @arg RCC_UART5CLKSOURCE_LSE: LSE selected as UART5 clock
AnnaBridge 126:abea610beb85 2981 */
AnnaBridge 126:abea610beb85 2982 #define __HAL_RCC_UART5_CONFIG(__UART5_CLKSOURCE__) \
AnnaBridge 126:abea610beb85 2983 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_UART5SEL, (uint32_t)(__UART5_CLKSOURCE__))
AnnaBridge 126:abea610beb85 2984
AnnaBridge 126:abea610beb85 2985 /** @brief macro to get the UART5 clock source.
AnnaBridge 126:abea610beb85 2986 * @retval The clock source can be one of the following values:
AnnaBridge 126:abea610beb85 2987 * @arg RCC_UART5CLKSOURCE_PCLK1: PCLK1 selected as UART5 clock
AnnaBridge 126:abea610beb85 2988 * @arg RCC_UART5CLKSOURCE_HSI: HSI selected as UART5 clock
AnnaBridge 126:abea610beb85 2989 * @arg RCC_UART5CLKSOURCE_SYSCLK: System Clock selected as UART5 clock
AnnaBridge 126:abea610beb85 2990 * @arg RCC_UART5CLKSOURCE_LSE: LSE selected as UART5 clock
AnnaBridge 126:abea610beb85 2991 */
AnnaBridge 126:abea610beb85 2992 #define __HAL_RCC_GET_UART5_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_UART5SEL)))
AnnaBridge 126:abea610beb85 2993
AnnaBridge 126:abea610beb85 2994 /** @brief Macro to configure the USART6 clock (USART6CLK).
AnnaBridge 126:abea610beb85 2995 *
AnnaBridge 126:abea610beb85 2996 * @param __USART6_CLKSOURCE__: specifies the USART6 clock source.
AnnaBridge 126:abea610beb85 2997 * This parameter can be one of the following values:
AnnaBridge 126:abea610beb85 2998 * @arg RCC_USART6CLKSOURCE_PCLK1: PCLK1 selected as USART6 clock
AnnaBridge 126:abea610beb85 2999 * @arg RCC_USART6CLKSOURCE_HSI: HSI selected as USART6 clock
AnnaBridge 126:abea610beb85 3000 * @arg RCC_USART6CLKSOURCE_SYSCLK: System Clock selected as USART6 clock
AnnaBridge 126:abea610beb85 3001 * @arg RCC_USART6CLKSOURCE_LSE: LSE selected as USART6 clock
AnnaBridge 126:abea610beb85 3002 */
AnnaBridge 126:abea610beb85 3003 #define __HAL_RCC_USART6_CONFIG(__USART6_CLKSOURCE__) \
AnnaBridge 126:abea610beb85 3004 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_USART6SEL, (uint32_t)(__USART6_CLKSOURCE__))
AnnaBridge 126:abea610beb85 3005
AnnaBridge 126:abea610beb85 3006 /** @brief macro to get the USART6 clock source.
AnnaBridge 126:abea610beb85 3007 * @retval The clock source can be one of the following values:
AnnaBridge 126:abea610beb85 3008 * @arg RCC_USART6CLKSOURCE_PCLK1: PCLK1 selected as USART6 clock
AnnaBridge 126:abea610beb85 3009 * @arg RCC_USART6CLKSOURCE_HSI: HSI selected as USART6 clock
AnnaBridge 126:abea610beb85 3010 * @arg RCC_USART6CLKSOURCE_SYSCLK: System Clock selected as USART6 clock
AnnaBridge 126:abea610beb85 3011 * @arg RCC_USART6CLKSOURCE_LSE: LSE selected as USART6 clock
AnnaBridge 126:abea610beb85 3012 */
AnnaBridge 126:abea610beb85 3013 #define __HAL_RCC_GET_USART6_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_USART6SEL)))
AnnaBridge 126:abea610beb85 3014
AnnaBridge 126:abea610beb85 3015 /** @brief Macro to configure the UART7 clock (UART7CLK).
AnnaBridge 126:abea610beb85 3016 *
AnnaBridge 126:abea610beb85 3017 * @param __UART7_CLKSOURCE__: specifies the UART7 clock source.
AnnaBridge 126:abea610beb85 3018 * This parameter can be one of the following values:
AnnaBridge 126:abea610beb85 3019 * @arg RCC_UART7CLKSOURCE_PCLK1: PCLK1 selected as UART7 clock
AnnaBridge 126:abea610beb85 3020 * @arg RCC_UART7CLKSOURCE_HSI: HSI selected as UART7 clock
AnnaBridge 126:abea610beb85 3021 * @arg RCC_UART7CLKSOURCE_SYSCLK: System Clock selected as UART7 clock
AnnaBridge 126:abea610beb85 3022 * @arg RCC_UART7CLKSOURCE_LSE: LSE selected as UART7 clock
AnnaBridge 126:abea610beb85 3023 */
AnnaBridge 126:abea610beb85 3024 #define __HAL_RCC_UART7_CONFIG(__UART7_CLKSOURCE__) \
AnnaBridge 126:abea610beb85 3025 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_UART7SEL, (uint32_t)(__UART7_CLKSOURCE__))
AnnaBridge 126:abea610beb85 3026
AnnaBridge 126:abea610beb85 3027 /** @brief macro to get the UART7 clock source.
AnnaBridge 126:abea610beb85 3028 * @retval The clock source can be one of the following values:
AnnaBridge 126:abea610beb85 3029 * @arg RCC_UART7CLKSOURCE_PCLK1: PCLK1 selected as UART7 clock
AnnaBridge 126:abea610beb85 3030 * @arg RCC_UART7CLKSOURCE_HSI: HSI selected as UART7 clock
AnnaBridge 126:abea610beb85 3031 * @arg RCC_UART7CLKSOURCE_SYSCLK: System Clock selected as UART7 clock
AnnaBridge 126:abea610beb85 3032 * @arg RCC_UART7CLKSOURCE_LSE: LSE selected as UART7 clock
AnnaBridge 126:abea610beb85 3033 */
AnnaBridge 126:abea610beb85 3034 #define __HAL_RCC_GET_UART7_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_UART7SEL)))
AnnaBridge 126:abea610beb85 3035
AnnaBridge 126:abea610beb85 3036 /** @brief Macro to configure the UART8 clock (UART8CLK).
AnnaBridge 126:abea610beb85 3037 *
AnnaBridge 126:abea610beb85 3038 * @param __UART8_CLKSOURCE__: specifies the UART8 clock source.
AnnaBridge 126:abea610beb85 3039 * This parameter can be one of the following values:
AnnaBridge 126:abea610beb85 3040 * @arg RCC_UART8CLKSOURCE_PCLK1: PCLK1 selected as UART8 clock
AnnaBridge 126:abea610beb85 3041 * @arg RCC_UART8CLKSOURCE_HSI: HSI selected as UART8 clock
AnnaBridge 126:abea610beb85 3042 * @arg RCC_UART8CLKSOURCE_SYSCLK: System Clock selected as UART8 clock
AnnaBridge 126:abea610beb85 3043 * @arg RCC_UART8CLKSOURCE_LSE: LSE selected as UART8 clock
AnnaBridge 126:abea610beb85 3044 */
AnnaBridge 126:abea610beb85 3045 #define __HAL_RCC_UART8_CONFIG(__UART8_CLKSOURCE__) \
AnnaBridge 126:abea610beb85 3046 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_UART8SEL, (uint32_t)(__UART8_CLKSOURCE__))
AnnaBridge 126:abea610beb85 3047
AnnaBridge 126:abea610beb85 3048 /** @brief macro to get the UART8 clock source.
AnnaBridge 126:abea610beb85 3049 * @retval The clock source can be one of the following values:
AnnaBridge 126:abea610beb85 3050 * @arg RCC_UART8CLKSOURCE_PCLK1: PCLK1 selected as UART8 clock
AnnaBridge 126:abea610beb85 3051 * @arg RCC_UART8CLKSOURCE_HSI: HSI selected as UART8 clock
AnnaBridge 126:abea610beb85 3052 * @arg RCC_UART8CLKSOURCE_SYSCLK: System Clock selected as UART8 clock
AnnaBridge 126:abea610beb85 3053 * @arg RCC_UART8CLKSOURCE_LSE: LSE selected as UART8 clock
AnnaBridge 126:abea610beb85 3054 */
AnnaBridge 126:abea610beb85 3055 #define __HAL_RCC_GET_UART8_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_UART8SEL)))
AnnaBridge 126:abea610beb85 3056
AnnaBridge 126:abea610beb85 3057 /** @brief Macro to configure the LPTIM1 clock (LPTIM1CLK).
AnnaBridge 126:abea610beb85 3058 *
AnnaBridge 126:abea610beb85 3059 * @param __LPTIM1_CLKSOURCE__: specifies the LPTIM1 clock source.
AnnaBridge 126:abea610beb85 3060 * This parameter can be one of the following values:
<> 139:856d2700e60b 3061 * @arg RCC_LPTIM1CLKSOURCE_PCLK1: PCLK selected as LPTIM1 clock
AnnaBridge 126:abea610beb85 3062 * @arg RCC_LPTIM1CLKSOURCE_HSI: HSI selected as LPTIM1 clock
AnnaBridge 126:abea610beb85 3063 * @arg RCC_LPTIM1CLKSOURCE_LSI: LSI selected as LPTIM1 clock
AnnaBridge 126:abea610beb85 3064 * @arg RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock
AnnaBridge 126:abea610beb85 3065 */
AnnaBridge 126:abea610beb85 3066 #define __HAL_RCC_LPTIM1_CONFIG(__LPTIM1_CLKSOURCE__) \
AnnaBridge 126:abea610beb85 3067 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL, (uint32_t)(__LPTIM1_CLKSOURCE__))
AnnaBridge 126:abea610beb85 3068
AnnaBridge 126:abea610beb85 3069 /** @brief macro to get the LPTIM1 clock source.
AnnaBridge 126:abea610beb85 3070 * @retval The clock source can be one of the following values:
<> 139:856d2700e60b 3071 * @arg RCC_LPTIM1CLKSOURCE_PCLK1: PCLK selected as LPTIM1 clock
AnnaBridge 126:abea610beb85 3072 * @arg RCC_LPTIM1CLKSOURCE_HSI: HSI selected as LPTIM1 clock
AnnaBridge 126:abea610beb85 3073 * @arg RCC_LPTIM1CLKSOURCE_LSI: LSI selected as LPTIM1 clock
AnnaBridge 126:abea610beb85 3074 * @arg RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock
AnnaBridge 126:abea610beb85 3075 */
AnnaBridge 126:abea610beb85 3076 #define __HAL_RCC_GET_LPTIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL)))
AnnaBridge 126:abea610beb85 3077
AnnaBridge 126:abea610beb85 3078 /** @brief Macro to configure the CEC clock (CECCLK).
AnnaBridge 126:abea610beb85 3079 *
AnnaBridge 126:abea610beb85 3080 * @param __CEC_CLKSOURCE__: specifies the CEC clock source.
AnnaBridge 126:abea610beb85 3081 * This parameter can be one of the following values:
AnnaBridge 126:abea610beb85 3082 * @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock
AnnaBridge 126:abea610beb85 3083 * @arg RCC_CECCLKSOURCE_HSI: HSI divided by 488 selected as CEC clock
AnnaBridge 126:abea610beb85 3084 */
AnnaBridge 126:abea610beb85 3085 #define __HAL_RCC_CEC_CONFIG(__CEC_CLKSOURCE__) \
AnnaBridge 126:abea610beb85 3086 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL, (uint32_t)(__CEC_CLKSOURCE__))
AnnaBridge 126:abea610beb85 3087
AnnaBridge 126:abea610beb85 3088 /** @brief macro to get the CEC clock source.
AnnaBridge 126:abea610beb85 3089 * @retval The clock source can be one of the following values:
AnnaBridge 126:abea610beb85 3090 * @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock
AnnaBridge 126:abea610beb85 3091 * @arg RCC_CECCLKSOURCE_HSI: HSI selected as CEC clock
AnnaBridge 126:abea610beb85 3092 */
AnnaBridge 126:abea610beb85 3093 #define __HAL_RCC_GET_CEC_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL)))
AnnaBridge 126:abea610beb85 3094
AnnaBridge 126:abea610beb85 3095 /** @brief Macro to configure the CLK48 source (CLK48CLK).
AnnaBridge 126:abea610beb85 3096 *
AnnaBridge 126:abea610beb85 3097 * @param __CLK48_SOURCE__: specifies the CLK48 clock source.
AnnaBridge 126:abea610beb85 3098 * This parameter can be one of the following values:
AnnaBridge 126:abea610beb85 3099 * @arg RCC_CLK48SOURCE_PLL: PLL selected as CLK48 source
AnnaBridge 126:abea610beb85 3100 * @arg RCC_CLK48SOURCE_PLLSAIP: PLLSAIP selected as CLK48 source
AnnaBridge 126:abea610beb85 3101 */
AnnaBridge 126:abea610beb85 3102 #define __HAL_RCC_CLK48_CONFIG(__CLK48_SOURCE__) \
AnnaBridge 126:abea610beb85 3103 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, (uint32_t)(__CLK48_SOURCE__))
AnnaBridge 126:abea610beb85 3104
AnnaBridge 126:abea610beb85 3105 /** @brief macro to get the CLK48 source.
AnnaBridge 126:abea610beb85 3106 * @retval The clock source can be one of the following values:
AnnaBridge 126:abea610beb85 3107 * @arg RCC_CLK48SOURCE_PLL: PLL used as CLK48 source
AnnaBridge 126:abea610beb85 3108 * @arg RCC_CLK48SOURCE_PLLSAIP: PLLSAIP used as CLK48 source
AnnaBridge 126:abea610beb85 3109 */
AnnaBridge 126:abea610beb85 3110 #define __HAL_RCC_GET_CLK48_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL)))
AnnaBridge 126:abea610beb85 3111
AnnaBridge 126:abea610beb85 3112 /** @brief Macro to configure the SDMMC1 clock (SDMMC1CLK).
AnnaBridge 126:abea610beb85 3113 *
AnnaBridge 126:abea610beb85 3114 * @param __SDMMC1_CLKSOURCE__: specifies the SDMMC1 clock source.
AnnaBridge 126:abea610beb85 3115 * This parameter can be one of the following values:
AnnaBridge 126:abea610beb85 3116 * @arg RCC_SDMMC1CLKSOURCE_CLK48: CLK48 selected as SDMMC clock
AnnaBridge 126:abea610beb85 3117 * @arg RCC_SDMMC1CLKSOURCE_SYSCLK: SYSCLK selected as SDMMC clock
AnnaBridge 126:abea610beb85 3118 */
AnnaBridge 126:abea610beb85 3119 #define __HAL_RCC_SDMMC1_CONFIG(__SDMMC1_CLKSOURCE__) \
AnnaBridge 126:abea610beb85 3120 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SDMMC1SEL, (uint32_t)(__SDMMC1_CLKSOURCE__))
AnnaBridge 126:abea610beb85 3121
AnnaBridge 126:abea610beb85 3122 /** @brief macro to get the SDMMC1 clock source.
AnnaBridge 126:abea610beb85 3123 * @retval The clock source can be one of the following values:
AnnaBridge 126:abea610beb85 3124 * @arg RCC_SDMMC1CLKSOURCE_CLK48: CLK48 selected as SDMMC1 clock
AnnaBridge 126:abea610beb85 3125 * @arg RCC_SDMMC1CLKSOURCE_SYSCLK: SYSCLK selected as SDMMC1 clock
AnnaBridge 126:abea610beb85 3126 */
AnnaBridge 126:abea610beb85 3127 #define __HAL_RCC_GET_SDMMC1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SDMMC1SEL)))
AnnaBridge 126:abea610beb85 3128
<> 139:856d2700e60b 3129 #if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\
<> 139:856d2700e60b 3130 defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
AnnaBridge 126:abea610beb85 3131 /** @brief Macro to configure the SDMMC2 clock (SDMMC2CLK).
AnnaBridge 126:abea610beb85 3132 * @param __SDMMC2_CLKSOURCE__: specifies the SDMMC2 clock source.
AnnaBridge 126:abea610beb85 3133 * This parameter can be one of the following values:
AnnaBridge 126:abea610beb85 3134 * @arg RCC_SDMMC2CLKSOURCE_CLK48: CLK48 selected as SDMMC2 clock
AnnaBridge 126:abea610beb85 3135 * @arg RCC_SDMMC2CLKSOURCE_SYSCLK: SYSCLK selected as SDMMC2 clock
AnnaBridge 126:abea610beb85 3136 */
AnnaBridge 126:abea610beb85 3137 #define __HAL_RCC_SDMMC2_CONFIG(__SDMMC2_CLKSOURCE__) \
AnnaBridge 126:abea610beb85 3138 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SDMMC2SEL, (uint32_t)(__SDMMC2_CLKSOURCE__))
AnnaBridge 126:abea610beb85 3139
AnnaBridge 126:abea610beb85 3140 /** @brief macro to get the SDMMC2 clock source.
AnnaBridge 126:abea610beb85 3141 * @retval The clock source can be one of the following values:
AnnaBridge 126:abea610beb85 3142 * @arg RCC_SDMMC2CLKSOURCE_CLK48: CLK48 selected as SDMMC2 clock
AnnaBridge 126:abea610beb85 3143 * @arg RCC_SDMMC2CLKSOURCE_SYSCLK: SYSCLK selected as SDMMC2 clock
AnnaBridge 126:abea610beb85 3144 */
AnnaBridge 126:abea610beb85 3145 #define __HAL_RCC_GET_SDMMC2_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SDMMC2SEL)))
<> 139:856d2700e60b 3146 #endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
AnnaBridge 126:abea610beb85 3147
<> 139:856d2700e60b 3148 #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
AnnaBridge 126:abea610beb85 3149 /** @brief Macro to configure the DFSDM1 clock
AnnaBridge 126:abea610beb85 3150 * @param __DFSDM1_CLKSOURCE__: specifies the DFSDM1 clock source.
AnnaBridge 126:abea610beb85 3151 * This parameter can be one of the following values:
<> 139:856d2700e60b 3152 * @arg RCC_DFSDM1CLKSOURCE_PCLK2: PCLK2 Clock selected as DFSDM clock
AnnaBridge 126:abea610beb85 3153 * @arg RCC_DFSDMCLKSOURCE_SYSCLK: System Clock selected as DFSDM clock
AnnaBridge 126:abea610beb85 3154 */
AnnaBridge 126:abea610beb85 3155 #define __HAL_RCC_DFSDM1_CONFIG(__DFSDM1_CLKSOURCE__) \
AnnaBridge 126:abea610beb85 3156 MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_DFSDM1SEL, (uint32_t)(__DFSDM1_CLKSOURCE__))
AnnaBridge 126:abea610beb85 3157
AnnaBridge 126:abea610beb85 3158 /** @brief Macro to get the DFSDM1 clock source.
AnnaBridge 126:abea610beb85 3159 * @retval The clock source can be one of the following values:
<> 139:856d2700e60b 3160 * @arg RCC_DFSDM1CLKSOURCE_PCLK2: PCLK2 Clock selected as DFSDM1 clock
AnnaBridge 126:abea610beb85 3161 * @arg RCC_DFSDM1CLKSOURCE_SYSCLK: System Clock selected as DFSDM1 clock
AnnaBridge 126:abea610beb85 3162 */
AnnaBridge 126:abea610beb85 3163 #define __HAL_RCC_GET_DFSDM1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR1, RCC_DCKCFGR1_DFSDM1SEL)))
AnnaBridge 126:abea610beb85 3164
AnnaBridge 126:abea610beb85 3165 /** @brief Macro to configure the DFSDM1 Audio clock
AnnaBridge 126:abea610beb85 3166 * @param __DFSDM1AUDIO_CLKSOURCE__: specifies the DFSDM1 Audio clock source.
AnnaBridge 126:abea610beb85 3167 * This parameter can be one of the following values:
AnnaBridge 126:abea610beb85 3168 * @arg RCC_DFSDM1AUDIOCLKSOURCE_SAI1: SAI1 Clock selected as DFSDM1 Audio clock
AnnaBridge 126:abea610beb85 3169 * @arg RCC_DFSDM1AUDIOCLKSOURCE_SAI2: SAI2 Clock selected as DFSDM1 Audio clock
AnnaBridge 126:abea610beb85 3170 */
AnnaBridge 126:abea610beb85 3171 #define __HAL_RCC_DFSDM1AUDIO_CONFIG(__DFSDM1AUDIO_CLKSOURCE__) \
AnnaBridge 126:abea610beb85 3172 MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_ADFSDM1SEL, (uint32_t)(__DFSDM1AUDIO_CLKSOURCE__))
AnnaBridge 126:abea610beb85 3173
AnnaBridge 126:abea610beb85 3174 /** @brief Macro to get the DFSDM1 Audio clock source.
AnnaBridge 126:abea610beb85 3175 * @retval The clock source can be one of the following values:
AnnaBridge 126:abea610beb85 3176 * @arg RCC_DFSDM1AUDIOCLKSOURCE_SAI1: SAI1 Clock selected as DFSDM1 Audio clock
AnnaBridge 126:abea610beb85 3177 * @arg RCC_DFSDM1AUDIOCLKSOURCE_SAI2: SAI2 Clock selected as DFSDM1 Audio clock
AnnaBridge 126:abea610beb85 3178 */
AnnaBridge 126:abea610beb85 3179 #define __HAL_RCC_GET_DFSDM1AUDIO_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR1, RCC_DCKCFGR1_ADFSDM1SEL)))
AnnaBridge 126:abea610beb85 3180 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
AnnaBridge 126:abea610beb85 3181
AnnaBridge 126:abea610beb85 3182 #if defined (STM32F769xx) || defined (STM32F779xx)
AnnaBridge 126:abea610beb85 3183 /** @brief Macro to configure the DSI clock.
AnnaBridge 126:abea610beb85 3184 * @param __DSI_CLKSOURCE__: specifies the DSI clock source.
AnnaBridge 126:abea610beb85 3185 * This parameter can be one of the following values:
AnnaBridge 126:abea610beb85 3186 * @arg RCC_DSICLKSOURCE_PLLR: PLLR output used as DSI clock.
AnnaBridge 126:abea610beb85 3187 * @arg RCC_DSICLKSOURCE_DSIPHY: DSI-PHY output used as DSI clock.
AnnaBridge 126:abea610beb85 3188 */
AnnaBridge 126:abea610beb85 3189 #define __HAL_RCC_DSI_CONFIG(__DSI_CLKSOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_DSISEL, (uint32_t)(__DSI_CLKSOURCE__)))
AnnaBridge 126:abea610beb85 3190
AnnaBridge 126:abea610beb85 3191 /** @brief Macro to Get the DSI clock.
AnnaBridge 126:abea610beb85 3192 * @retval The clock source can be one of the following values:
AnnaBridge 126:abea610beb85 3193 * @arg RCC_DSICLKSOURCE_PLLR: PLLR output used as DSI clock.
AnnaBridge 126:abea610beb85 3194 * @arg RCC_DSICLKSOURCE_DSIPHY: DSI-PHY output used as DSI clock.
AnnaBridge 126:abea610beb85 3195 */
AnnaBridge 126:abea610beb85 3196 #define __HAL_RCC_GET_DSI_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_DSISEL))
AnnaBridge 126:abea610beb85 3197 #endif /* STM32F769xx || STM32F779xx */
AnnaBridge 126:abea610beb85 3198 /**
AnnaBridge 126:abea610beb85 3199 * @}
AnnaBridge 126:abea610beb85 3200 */
AnnaBridge 126:abea610beb85 3201
AnnaBridge 126:abea610beb85 3202 /* Exported functions --------------------------------------------------------*/
AnnaBridge 126:abea610beb85 3203 /** @addtogroup RCCEx_Exported_Functions_Group1
AnnaBridge 126:abea610beb85 3204 * @{
AnnaBridge 126:abea610beb85 3205 */
AnnaBridge 126:abea610beb85 3206 HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
AnnaBridge 126:abea610beb85 3207 void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
AnnaBridge 126:abea610beb85 3208 uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk);
AnnaBridge 126:abea610beb85 3209
AnnaBridge 126:abea610beb85 3210 /**
AnnaBridge 126:abea610beb85 3211 * @}
AnnaBridge 126:abea610beb85 3212 */
AnnaBridge 126:abea610beb85 3213 /* Private macros ------------------------------------------------------------*/
AnnaBridge 126:abea610beb85 3214 /** @addtogroup RCCEx_Private_Macros RCCEx Private Macros
AnnaBridge 126:abea610beb85 3215 * @{
AnnaBridge 126:abea610beb85 3216 */
AnnaBridge 126:abea610beb85 3217 /** @defgroup RCCEx_IS_RCC_Definitions RCC Private macros to check input parameters
AnnaBridge 126:abea610beb85 3218 * @{
AnnaBridge 126:abea610beb85 3219 */
AnnaBridge 126:abea610beb85 3220 #if defined(STM32F756xx) || defined(STM32F746xx)
AnnaBridge 126:abea610beb85 3221 #define IS_RCC_PERIPHCLOCK(SELECTION) \
AnnaBridge 126:abea610beb85 3222 ((((SELECTION) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || \
AnnaBridge 126:abea610beb85 3223 (((SELECTION) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC) || \
AnnaBridge 126:abea610beb85 3224 (((SELECTION) & RCC_PERIPHCLK_TIM) == RCC_PERIPHCLK_TIM) || \
AnnaBridge 126:abea610beb85 3225 (((SELECTION) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \
AnnaBridge 126:abea610beb85 3226 (((SELECTION) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \
AnnaBridge 126:abea610beb85 3227 (((SELECTION) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \
AnnaBridge 126:abea610beb85 3228 (((SELECTION) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \
AnnaBridge 126:abea610beb85 3229 (((SELECTION) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \
AnnaBridge 126:abea610beb85 3230 (((SELECTION) & RCC_PERIPHCLK_USART6) == RCC_PERIPHCLK_USART6) || \
AnnaBridge 126:abea610beb85 3231 (((SELECTION) & RCC_PERIPHCLK_UART7) == RCC_PERIPHCLK_UART7) || \
AnnaBridge 126:abea610beb85 3232 (((SELECTION) & RCC_PERIPHCLK_UART8) == RCC_PERIPHCLK_UART8) || \
AnnaBridge 126:abea610beb85 3233 (((SELECTION) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \
AnnaBridge 126:abea610beb85 3234 (((SELECTION) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \
AnnaBridge 126:abea610beb85 3235 (((SELECTION) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \
AnnaBridge 126:abea610beb85 3236 (((SELECTION) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) || \
AnnaBridge 126:abea610beb85 3237 (((SELECTION) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \
AnnaBridge 126:abea610beb85 3238 (((SELECTION) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \
AnnaBridge 126:abea610beb85 3239 (((SELECTION) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) || \
AnnaBridge 126:abea610beb85 3240 (((SELECTION) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) || \
AnnaBridge 126:abea610beb85 3241 (((SELECTION) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) || \
AnnaBridge 126:abea610beb85 3242 (((SELECTION) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1) || \
AnnaBridge 126:abea610beb85 3243 (((SELECTION) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) || \
AnnaBridge 126:abea610beb85 3244 (((SELECTION) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC))
AnnaBridge 126:abea610beb85 3245 #elif defined(STM32F745xx)
AnnaBridge 126:abea610beb85 3246 #define IS_RCC_PERIPHCLOCK(SELECTION) \
AnnaBridge 126:abea610beb85 3247 ((((SELECTION) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || \
AnnaBridge 126:abea610beb85 3248 (((SELECTION) & RCC_PERIPHCLK_TIM) == RCC_PERIPHCLK_TIM) || \
AnnaBridge 126:abea610beb85 3249 (((SELECTION) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \
AnnaBridge 126:abea610beb85 3250 (((SELECTION) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \
AnnaBridge 126:abea610beb85 3251 (((SELECTION) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \
AnnaBridge 126:abea610beb85 3252 (((SELECTION) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \
AnnaBridge 126:abea610beb85 3253 (((SELECTION) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \
AnnaBridge 126:abea610beb85 3254 (((SELECTION) & RCC_PERIPHCLK_USART6) == RCC_PERIPHCLK_USART6) || \
AnnaBridge 126:abea610beb85 3255 (((SELECTION) & RCC_PERIPHCLK_UART7) == RCC_PERIPHCLK_UART7) || \
AnnaBridge 126:abea610beb85 3256 (((SELECTION) & RCC_PERIPHCLK_UART8) == RCC_PERIPHCLK_UART8) || \
AnnaBridge 126:abea610beb85 3257 (((SELECTION) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \
AnnaBridge 126:abea610beb85 3258 (((SELECTION) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \
AnnaBridge 126:abea610beb85 3259 (((SELECTION) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \
AnnaBridge 126:abea610beb85 3260 (((SELECTION) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) || \
AnnaBridge 126:abea610beb85 3261 (((SELECTION) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \
AnnaBridge 126:abea610beb85 3262 (((SELECTION) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \
AnnaBridge 126:abea610beb85 3263 (((SELECTION) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) || \
AnnaBridge 126:abea610beb85 3264 (((SELECTION) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) || \
AnnaBridge 126:abea610beb85 3265 (((SELECTION) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) || \
AnnaBridge 126:abea610beb85 3266 (((SELECTION) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1) || \
AnnaBridge 126:abea610beb85 3267 (((SELECTION) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) || \
AnnaBridge 126:abea610beb85 3268 (((SELECTION) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC))
AnnaBridge 126:abea610beb85 3269 #elif defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
AnnaBridge 126:abea610beb85 3270 #define IS_RCC_PERIPHCLOCK(SELECTION) \
AnnaBridge 126:abea610beb85 3271 ((((SELECTION) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || \
AnnaBridge 126:abea610beb85 3272 (((SELECTION) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC) || \
AnnaBridge 126:abea610beb85 3273 (((SELECTION) & RCC_PERIPHCLK_TIM) == RCC_PERIPHCLK_TIM) || \
AnnaBridge 126:abea610beb85 3274 (((SELECTION) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \
AnnaBridge 126:abea610beb85 3275 (((SELECTION) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \
AnnaBridge 126:abea610beb85 3276 (((SELECTION) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \
AnnaBridge 126:abea610beb85 3277 (((SELECTION) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \
AnnaBridge 126:abea610beb85 3278 (((SELECTION) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \
AnnaBridge 126:abea610beb85 3279 (((SELECTION) & RCC_PERIPHCLK_USART6) == RCC_PERIPHCLK_USART6) || \
AnnaBridge 126:abea610beb85 3280 (((SELECTION) & RCC_PERIPHCLK_UART7) == RCC_PERIPHCLK_UART7) || \
AnnaBridge 126:abea610beb85 3281 (((SELECTION) & RCC_PERIPHCLK_UART8) == RCC_PERIPHCLK_UART8) || \
AnnaBridge 126:abea610beb85 3282 (((SELECTION) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \
AnnaBridge 126:abea610beb85 3283 (((SELECTION) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \
AnnaBridge 126:abea610beb85 3284 (((SELECTION) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \
AnnaBridge 126:abea610beb85 3285 (((SELECTION) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) || \
AnnaBridge 126:abea610beb85 3286 (((SELECTION) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \
AnnaBridge 126:abea610beb85 3287 (((SELECTION) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \
AnnaBridge 126:abea610beb85 3288 (((SELECTION) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) || \
AnnaBridge 126:abea610beb85 3289 (((SELECTION) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) || \
AnnaBridge 126:abea610beb85 3290 (((SELECTION) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) || \
AnnaBridge 126:abea610beb85 3291 (((SELECTION) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1) || \
AnnaBridge 126:abea610beb85 3292 (((SELECTION) & RCC_PERIPHCLK_SDMMC2) == RCC_PERIPHCLK_SDMMC2) || \
AnnaBridge 126:abea610beb85 3293 (((SELECTION) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1) || \
AnnaBridge 126:abea610beb85 3294 (((SELECTION) & RCC_PERIPHCLK_DFSDM1_AUDIO) == RCC_PERIPHCLK_DFSDM1_AUDIO) || \
AnnaBridge 126:abea610beb85 3295 (((SELECTION) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) || \
AnnaBridge 126:abea610beb85 3296 (((SELECTION) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC))
AnnaBridge 126:abea610beb85 3297 #elif defined (STM32F765xx)
AnnaBridge 126:abea610beb85 3298 #define IS_RCC_PERIPHCLOCK(SELECTION) \
AnnaBridge 126:abea610beb85 3299 ((((SELECTION) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || \
AnnaBridge 126:abea610beb85 3300 (((SELECTION) & RCC_PERIPHCLK_TIM) == RCC_PERIPHCLK_TIM) || \
AnnaBridge 126:abea610beb85 3301 (((SELECTION) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \
AnnaBridge 126:abea610beb85 3302 (((SELECTION) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \
AnnaBridge 126:abea610beb85 3303 (((SELECTION) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \
AnnaBridge 126:abea610beb85 3304 (((SELECTION) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \
AnnaBridge 126:abea610beb85 3305 (((SELECTION) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \
AnnaBridge 126:abea610beb85 3306 (((SELECTION) & RCC_PERIPHCLK_USART6) == RCC_PERIPHCLK_USART6) || \
AnnaBridge 126:abea610beb85 3307 (((SELECTION) & RCC_PERIPHCLK_UART7) == RCC_PERIPHCLK_UART7) || \
AnnaBridge 126:abea610beb85 3308 (((SELECTION) & RCC_PERIPHCLK_UART8) == RCC_PERIPHCLK_UART8) || \
AnnaBridge 126:abea610beb85 3309 (((SELECTION) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \
AnnaBridge 126:abea610beb85 3310 (((SELECTION) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \
AnnaBridge 126:abea610beb85 3311 (((SELECTION) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \
AnnaBridge 126:abea610beb85 3312 (((SELECTION) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) || \
AnnaBridge 126:abea610beb85 3313 (((SELECTION) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \
AnnaBridge 126:abea610beb85 3314 (((SELECTION) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \
AnnaBridge 126:abea610beb85 3315 (((SELECTION) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) || \
AnnaBridge 126:abea610beb85 3316 (((SELECTION) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) || \
AnnaBridge 126:abea610beb85 3317 (((SELECTION) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) || \
AnnaBridge 126:abea610beb85 3318 (((SELECTION) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1) || \
AnnaBridge 126:abea610beb85 3319 (((SELECTION) & RCC_PERIPHCLK_SDMMC2) == RCC_PERIPHCLK_SDMMC2) || \
AnnaBridge 126:abea610beb85 3320 (((SELECTION) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1) || \
AnnaBridge 126:abea610beb85 3321 (((SELECTION) & RCC_PERIPHCLK_DFSDM1_AUDIO) == RCC_PERIPHCLK_DFSDM1_AUDIO) || \
AnnaBridge 126:abea610beb85 3322 (((SELECTION) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) || \
AnnaBridge 126:abea610beb85 3323 (((SELECTION) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC))
<> 139:856d2700e60b 3324 #elif defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx)
<> 139:856d2700e60b 3325 #define IS_RCC_PERIPHCLOCK(SELECTION) \
<> 139:856d2700e60b 3326 ((((SELECTION) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || \
<> 139:856d2700e60b 3327 (((SELECTION) & RCC_PERIPHCLK_TIM) == RCC_PERIPHCLK_TIM) || \
<> 139:856d2700e60b 3328 (((SELECTION) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \
<> 139:856d2700e60b 3329 (((SELECTION) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \
<> 139:856d2700e60b 3330 (((SELECTION) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \
<> 139:856d2700e60b 3331 (((SELECTION) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \
<> 139:856d2700e60b 3332 (((SELECTION) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \
<> 139:856d2700e60b 3333 (((SELECTION) & RCC_PERIPHCLK_USART6) == RCC_PERIPHCLK_USART6) || \
<> 139:856d2700e60b 3334 (((SELECTION) & RCC_PERIPHCLK_UART7) == RCC_PERIPHCLK_UART7) || \
<> 139:856d2700e60b 3335 (((SELECTION) & RCC_PERIPHCLK_UART8) == RCC_PERIPHCLK_UART8) || \
<> 139:856d2700e60b 3336 (((SELECTION) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \
<> 139:856d2700e60b 3337 (((SELECTION) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \
<> 139:856d2700e60b 3338 (((SELECTION) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \
<> 139:856d2700e60b 3339 (((SELECTION) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \
<> 139:856d2700e60b 3340 (((SELECTION) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \
<> 139:856d2700e60b 3341 (((SELECTION) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) || \
<> 139:856d2700e60b 3342 (((SELECTION) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) || \
<> 139:856d2700e60b 3343 (((SELECTION) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1) || \
<> 139:856d2700e60b 3344 (((SELECTION) & RCC_PERIPHCLK_SDMMC2) == RCC_PERIPHCLK_SDMMC2) || \
<> 139:856d2700e60b 3345 (((SELECTION) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC))
<> 139:856d2700e60b 3346 #endif /* STM32F746xx || STM32F756xx */
AnnaBridge 126:abea610beb85 3347 #define IS_RCC_PLLI2SN_VALUE(VALUE) ((50 <= (VALUE)) && ((VALUE) <= 432))
<> 139:856d2700e60b 3348 #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) || defined (STM32F767xx) || \
<> 139:856d2700e60b 3349 defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
AnnaBridge 126:abea610beb85 3350 #define IS_RCC_PLLI2SP_VALUE(VALUE) (((VALUE) == RCC_PLLI2SP_DIV2) ||\
AnnaBridge 126:abea610beb85 3351 ((VALUE) == RCC_PLLI2SP_DIV4) ||\
AnnaBridge 126:abea610beb85 3352 ((VALUE) == RCC_PLLI2SP_DIV6) ||\
<> 139:856d2700e60b 3353 ((VALUE) == RCC_PLLI2SP_DIV8))
<> 139:856d2700e60b 3354 #endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
AnnaBridge 126:abea610beb85 3355 #define IS_RCC_PLLI2SQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15))
AnnaBridge 126:abea610beb85 3356 #define IS_RCC_PLLI2SR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))
AnnaBridge 126:abea610beb85 3357
AnnaBridge 126:abea610beb85 3358 #define IS_RCC_PLLSAIN_VALUE(VALUE) ((50 <= (VALUE)) && ((VALUE) <= 432))
AnnaBridge 126:abea610beb85 3359 #define IS_RCC_PLLSAIP_VALUE(VALUE) (((VALUE) == RCC_PLLSAIP_DIV2) ||\
AnnaBridge 126:abea610beb85 3360 ((VALUE) == RCC_PLLSAIP_DIV4) ||\
AnnaBridge 126:abea610beb85 3361 ((VALUE) == RCC_PLLSAIP_DIV6) ||\
AnnaBridge 126:abea610beb85 3362 ((VALUE) == RCC_PLLSAIP_DIV8))
AnnaBridge 126:abea610beb85 3363 #define IS_RCC_PLLSAIQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15))
AnnaBridge 126:abea610beb85 3364 #define IS_RCC_PLLSAIR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))
AnnaBridge 126:abea610beb85 3365
AnnaBridge 126:abea610beb85 3366 #define IS_RCC_PLLSAI_DIVQ_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32))
AnnaBridge 126:abea610beb85 3367
AnnaBridge 126:abea610beb85 3368 #define IS_RCC_PLLI2S_DIVQ_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32))
AnnaBridge 126:abea610beb85 3369
AnnaBridge 126:abea610beb85 3370 #define IS_RCC_PLLSAI_DIVR_VALUE(VALUE) (((VALUE) == RCC_PLLSAIDIVR_2) ||\
AnnaBridge 126:abea610beb85 3371 ((VALUE) == RCC_PLLSAIDIVR_4) ||\
AnnaBridge 126:abea610beb85 3372 ((VALUE) == RCC_PLLSAIDIVR_8) ||\
AnnaBridge 126:abea610beb85 3373 ((VALUE) == RCC_PLLSAIDIVR_16))
AnnaBridge 126:abea610beb85 3374 #define IS_RCC_I2SCLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SCLKSOURCE_PLLI2S) || \
AnnaBridge 126:abea610beb85 3375 ((SOURCE) == RCC_I2SCLKSOURCE_EXT))
AnnaBridge 126:abea610beb85 3376
AnnaBridge 126:abea610beb85 3377 #define IS_RCC_SDMMC1CLKSOURCE(SOURCE) (((SOURCE) == RCC_SDMMC1CLKSOURCE_SYSCLK) || \
AnnaBridge 126:abea610beb85 3378 ((SOURCE) == RCC_SDMMC1CLKSOURCE_CLK48))
AnnaBridge 126:abea610beb85 3379
AnnaBridge 126:abea610beb85 3380 #define IS_RCC_CECCLKSOURCE(SOURCE) (((SOURCE) == RCC_CECCLKSOURCE_HSI) || \
AnnaBridge 126:abea610beb85 3381 ((SOURCE) == RCC_CECCLKSOURCE_LSE))
AnnaBridge 126:abea610beb85 3382 #define IS_RCC_USART1CLKSOURCE(SOURCE) \
AnnaBridge 126:abea610beb85 3383 (((SOURCE) == RCC_USART1CLKSOURCE_PCLK2) || \
AnnaBridge 126:abea610beb85 3384 ((SOURCE) == RCC_USART1CLKSOURCE_SYSCLK) || \
AnnaBridge 126:abea610beb85 3385 ((SOURCE) == RCC_USART1CLKSOURCE_LSE) || \
AnnaBridge 126:abea610beb85 3386 ((SOURCE) == RCC_USART1CLKSOURCE_HSI))
AnnaBridge 126:abea610beb85 3387
AnnaBridge 126:abea610beb85 3388 #define IS_RCC_USART2CLKSOURCE(SOURCE) \
AnnaBridge 126:abea610beb85 3389 (((SOURCE) == RCC_USART2CLKSOURCE_PCLK1) || \
AnnaBridge 126:abea610beb85 3390 ((SOURCE) == RCC_USART2CLKSOURCE_SYSCLK) || \
AnnaBridge 126:abea610beb85 3391 ((SOURCE) == RCC_USART2CLKSOURCE_LSE) || \
AnnaBridge 126:abea610beb85 3392 ((SOURCE) == RCC_USART2CLKSOURCE_HSI))
AnnaBridge 126:abea610beb85 3393 #define IS_RCC_USART3CLKSOURCE(SOURCE) \
AnnaBridge 126:abea610beb85 3394 (((SOURCE) == RCC_USART3CLKSOURCE_PCLK1) || \
AnnaBridge 126:abea610beb85 3395 ((SOURCE) == RCC_USART3CLKSOURCE_SYSCLK) || \
AnnaBridge 126:abea610beb85 3396 ((SOURCE) == RCC_USART3CLKSOURCE_LSE) || \
AnnaBridge 126:abea610beb85 3397 ((SOURCE) == RCC_USART3CLKSOURCE_HSI))
AnnaBridge 126:abea610beb85 3398
AnnaBridge 126:abea610beb85 3399 #define IS_RCC_UART4CLKSOURCE(SOURCE) \
AnnaBridge 126:abea610beb85 3400 (((SOURCE) == RCC_UART4CLKSOURCE_PCLK1) || \
AnnaBridge 126:abea610beb85 3401 ((SOURCE) == RCC_UART4CLKSOURCE_SYSCLK) || \
AnnaBridge 126:abea610beb85 3402 ((SOURCE) == RCC_UART4CLKSOURCE_LSE) || \
AnnaBridge 126:abea610beb85 3403 ((SOURCE) == RCC_UART4CLKSOURCE_HSI))
AnnaBridge 126:abea610beb85 3404
AnnaBridge 126:abea610beb85 3405 #define IS_RCC_UART5CLKSOURCE(SOURCE) \
AnnaBridge 126:abea610beb85 3406 (((SOURCE) == RCC_UART5CLKSOURCE_PCLK1) || \
AnnaBridge 126:abea610beb85 3407 ((SOURCE) == RCC_UART5CLKSOURCE_SYSCLK) || \
AnnaBridge 126:abea610beb85 3408 ((SOURCE) == RCC_UART5CLKSOURCE_LSE) || \
AnnaBridge 126:abea610beb85 3409 ((SOURCE) == RCC_UART5CLKSOURCE_HSI))
AnnaBridge 126:abea610beb85 3410
AnnaBridge 126:abea610beb85 3411 #define IS_RCC_USART6CLKSOURCE(SOURCE) \
AnnaBridge 126:abea610beb85 3412 (((SOURCE) == RCC_USART6CLKSOURCE_PCLK2) || \
AnnaBridge 126:abea610beb85 3413 ((SOURCE) == RCC_USART6CLKSOURCE_SYSCLK) || \
AnnaBridge 126:abea610beb85 3414 ((SOURCE) == RCC_USART6CLKSOURCE_LSE) || \
AnnaBridge 126:abea610beb85 3415 ((SOURCE) == RCC_USART6CLKSOURCE_HSI))
AnnaBridge 126:abea610beb85 3416
AnnaBridge 126:abea610beb85 3417 #define IS_RCC_UART7CLKSOURCE(SOURCE) \
AnnaBridge 126:abea610beb85 3418 (((SOURCE) == RCC_UART7CLKSOURCE_PCLK1) || \
AnnaBridge 126:abea610beb85 3419 ((SOURCE) == RCC_UART7CLKSOURCE_SYSCLK) || \
AnnaBridge 126:abea610beb85 3420 ((SOURCE) == RCC_UART7CLKSOURCE_LSE) || \
AnnaBridge 126:abea610beb85 3421 ((SOURCE) == RCC_UART7CLKSOURCE_HSI))
AnnaBridge 126:abea610beb85 3422
AnnaBridge 126:abea610beb85 3423 #define IS_RCC_UART8CLKSOURCE(SOURCE) \
AnnaBridge 126:abea610beb85 3424 (((SOURCE) == RCC_UART8CLKSOURCE_PCLK1) || \
AnnaBridge 126:abea610beb85 3425 ((SOURCE) == RCC_UART8CLKSOURCE_SYSCLK) || \
AnnaBridge 126:abea610beb85 3426 ((SOURCE) == RCC_UART8CLKSOURCE_LSE) || \
AnnaBridge 126:abea610beb85 3427 ((SOURCE) == RCC_UART8CLKSOURCE_HSI))
AnnaBridge 126:abea610beb85 3428 #define IS_RCC_I2C1CLKSOURCE(SOURCE) \
AnnaBridge 126:abea610beb85 3429 (((SOURCE) == RCC_I2C1CLKSOURCE_PCLK1) || \
AnnaBridge 126:abea610beb85 3430 ((SOURCE) == RCC_I2C1CLKSOURCE_SYSCLK)|| \
AnnaBridge 126:abea610beb85 3431 ((SOURCE) == RCC_I2C1CLKSOURCE_HSI))
AnnaBridge 126:abea610beb85 3432 #define IS_RCC_I2C2CLKSOURCE(SOURCE) \
AnnaBridge 126:abea610beb85 3433 (((SOURCE) == RCC_I2C2CLKSOURCE_PCLK1) || \
AnnaBridge 126:abea610beb85 3434 ((SOURCE) == RCC_I2C2CLKSOURCE_SYSCLK)|| \
AnnaBridge 126:abea610beb85 3435 ((SOURCE) == RCC_I2C2CLKSOURCE_HSI))
AnnaBridge 126:abea610beb85 3436
AnnaBridge 126:abea610beb85 3437 #define IS_RCC_I2C3CLKSOURCE(SOURCE) \
AnnaBridge 126:abea610beb85 3438 (((SOURCE) == RCC_I2C3CLKSOURCE_PCLK1) || \
AnnaBridge 126:abea610beb85 3439 ((SOURCE) == RCC_I2C3CLKSOURCE_SYSCLK)|| \
AnnaBridge 126:abea610beb85 3440 ((SOURCE) == RCC_I2C3CLKSOURCE_HSI))
AnnaBridge 126:abea610beb85 3441 #define IS_RCC_I2C4CLKSOURCE(SOURCE) \
AnnaBridge 126:abea610beb85 3442 (((SOURCE) == RCC_I2C4CLKSOURCE_PCLK1) || \
AnnaBridge 126:abea610beb85 3443 ((SOURCE) == RCC_I2C4CLKSOURCE_SYSCLK)|| \
AnnaBridge 126:abea610beb85 3444 ((SOURCE) == RCC_I2C4CLKSOURCE_HSI))
AnnaBridge 126:abea610beb85 3445 #define IS_RCC_LPTIM1CLK(SOURCE) \
<> 139:856d2700e60b 3446 (((SOURCE) == RCC_LPTIM1CLKSOURCE_PCLK1) || \
AnnaBridge 126:abea610beb85 3447 ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSI) || \
AnnaBridge 126:abea610beb85 3448 ((SOURCE) == RCC_LPTIM1CLKSOURCE_HSI) || \
AnnaBridge 126:abea610beb85 3449 ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSE))
AnnaBridge 126:abea610beb85 3450 #define IS_RCC_CLK48SOURCE(SOURCE) \
AnnaBridge 126:abea610beb85 3451 (((SOURCE) == RCC_CLK48SOURCE_PLLSAIP) || \
AnnaBridge 126:abea610beb85 3452 ((SOURCE) == RCC_CLK48SOURCE_PLL))
AnnaBridge 126:abea610beb85 3453 #define IS_RCC_TIMPRES(VALUE) \
AnnaBridge 126:abea610beb85 3454 (((VALUE) == RCC_TIMPRES_DESACTIVATED) || \
AnnaBridge 126:abea610beb85 3455 ((VALUE) == RCC_TIMPRES_ACTIVATED))
AnnaBridge 126:abea610beb85 3456
<> 139:856d2700e60b 3457 #if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F745xx) ||\
<> 139:856d2700e60b 3458 defined (STM32F746xx) || defined (STM32F756xx)
AnnaBridge 126:abea610beb85 3459 #define IS_RCC_SAI1CLKSOURCE(SOURCE) (((SOURCE) == RCC_SAI1CLKSOURCE_PLLSAI) || \
AnnaBridge 126:abea610beb85 3460 ((SOURCE) == RCC_SAI1CLKSOURCE_PLLI2S) || \
AnnaBridge 126:abea610beb85 3461 ((SOURCE) == RCC_SAI1CLKSOURCE_PIN))
AnnaBridge 126:abea610beb85 3462 #define IS_RCC_SAI2CLKSOURCE(SOURCE) (((SOURCE) == RCC_SAI2CLKSOURCE_PLLSAI) || \
AnnaBridge 126:abea610beb85 3463 ((SOURCE) == RCC_SAI2CLKSOURCE_PLLI2S) || \
AnnaBridge 126:abea610beb85 3464 ((SOURCE) == RCC_SAI2CLKSOURCE_PIN))
<> 139:856d2700e60b 3465 #endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F745xx || STM32F746xx || STM32F756xx */
AnnaBridge 126:abea610beb85 3466
AnnaBridge 126:abea610beb85 3467 #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
AnnaBridge 126:abea610beb85 3468 #define IS_RCC_PLLR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))
AnnaBridge 126:abea610beb85 3469
AnnaBridge 126:abea610beb85 3470 #define IS_RCC_SAI1CLKSOURCE(SOURCE) (((SOURCE) == RCC_SAI1CLKSOURCE_PLLSAI) || \
AnnaBridge 126:abea610beb85 3471 ((SOURCE) == RCC_SAI1CLKSOURCE_PLLI2S) || \
AnnaBridge 126:abea610beb85 3472 ((SOURCE) == RCC_SAI1CLKSOURCE_PIN) || \
AnnaBridge 126:abea610beb85 3473 ((SOURCE) == RCC_SAI1CLKSOURCE_PLLSRC))
AnnaBridge 126:abea610beb85 3474
AnnaBridge 126:abea610beb85 3475 #define IS_RCC_SAI2CLKSOURCE(SOURCE) (((SOURCE) == RCC_SAI2CLKSOURCE_PLLSAI) || \
AnnaBridge 126:abea610beb85 3476 ((SOURCE) == RCC_SAI2CLKSOURCE_PLLI2S) || \
AnnaBridge 126:abea610beb85 3477 ((SOURCE) == RCC_SAI2CLKSOURCE_PIN) || \
AnnaBridge 126:abea610beb85 3478 ((SOURCE) == RCC_SAI2CLKSOURCE_PLLSRC))
AnnaBridge 126:abea610beb85 3479
<> 139:856d2700e60b 3480 #define IS_RCC_DFSDM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_DFSDM1CLKSOURCE_PCLK2) || \
AnnaBridge 126:abea610beb85 3481 ((SOURCE) == RCC_DFSDM1CLKSOURCE_SYSCLK))
AnnaBridge 126:abea610beb85 3482
AnnaBridge 126:abea610beb85 3483 #define IS_RCC_DFSDM1AUDIOCLKSOURCE(SOURCE) (((SOURCE) == RCC_DFSDM1AUDIOCLKSOURCE_SAI1) || \
AnnaBridge 126:abea610beb85 3484 ((SOURCE) == RCC_DFSDM1AUDIOCLKSOURCE_SAI2))
AnnaBridge 126:abea610beb85 3485 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
AnnaBridge 126:abea610beb85 3486
<> 139:856d2700e60b 3487 #if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\
<> 139:856d2700e60b 3488 defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
<> 139:856d2700e60b 3489 #define IS_RCC_SDMMC2CLKSOURCE(SOURCE) (((SOURCE) == RCC_SDMMC2CLKSOURCE_SYSCLK) || \
<> 139:856d2700e60b 3490 ((SOURCE) == RCC_SDMMC2CLKSOURCE_CLK48))
<> 139:856d2700e60b 3491 #endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
<> 139:856d2700e60b 3492
AnnaBridge 126:abea610beb85 3493 #if defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
AnnaBridge 126:abea610beb85 3494 #define IS_RCC_DSIBYTELANECLKSOURCE(SOURCE) (((SOURCE) == RCC_DSICLKSOURCE_PLLR) ||\
AnnaBridge 126:abea610beb85 3495 ((SOURCE) == RCC_DSICLKSOURCE_DSIPHY))
AnnaBridge 126:abea610beb85 3496 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
AnnaBridge 126:abea610beb85 3497
AnnaBridge 126:abea610beb85 3498 /**
AnnaBridge 126:abea610beb85 3499 * @}
AnnaBridge 126:abea610beb85 3500 */
AnnaBridge 126:abea610beb85 3501
AnnaBridge 126:abea610beb85 3502 /**
AnnaBridge 126:abea610beb85 3503 * @}
AnnaBridge 126:abea610beb85 3504 */
AnnaBridge 126:abea610beb85 3505
AnnaBridge 126:abea610beb85 3506 /**
AnnaBridge 126:abea610beb85 3507 * @}
AnnaBridge 126:abea610beb85 3508 */
AnnaBridge 126:abea610beb85 3509
AnnaBridge 126:abea610beb85 3510 /**
AnnaBridge 126:abea610beb85 3511 * @}
AnnaBridge 126:abea610beb85 3512 */
AnnaBridge 126:abea610beb85 3513 #ifdef __cplusplus
AnnaBridge 126:abea610beb85 3514 }
AnnaBridge 126:abea610beb85 3515 #endif
AnnaBridge 126:abea610beb85 3516
AnnaBridge 126:abea610beb85 3517 #endif /* __STM32F7xx_HAL_RCC_EX_H */
AnnaBridge 126:abea610beb85 3518
AnnaBridge 126:abea610beb85 3519 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/