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The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

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mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_K66F/core_cm7.h@124:2241e3a39974, 2016-08-19 (annotated)

Committer:
Kojto
Date:
Fri Aug 19 10:17:11 2016 +0100
Revision:
124:2241e3a39974
Child:
128:9bcdf88f62b0
Release 124 of the mbed library



Changes:



- new targets - KL27Z, K66F

- deprecate macro - add since argument

- override new and delete operators to trap errors

- Maxim - i2c and dac bugfixes

- STM - STM32F4 - serial flow enablement, enable async serial

      - pwm and analog definition clean-up

- Nordic - NRF51 - fix for overflow in the ticket

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Kojto 124:2241e3a39974 1 /**************************************************************************//**
Kojto 124:2241e3a39974 2 * @file core_cm7.h
Kojto 124:2241e3a39974 3 * @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File
Kojto 124:2241e3a39974 4 * @version V4.10
Kojto 124:2241e3a39974 5 * @date 18. March 2015
Kojto 124:2241e3a39974 6 *
Kojto 124:2241e3a39974 7 * @note
Kojto 124:2241e3a39974 8 *
Kojto 124:2241e3a39974 9 ******************************************************************************/
Kojto 124:2241e3a39974 10 /* Copyright (c) 2009 - 2015 ARM LIMITED
Kojto 124:2241e3a39974 11
Kojto 124:2241e3a39974 12 All rights reserved.
Kojto 124:2241e3a39974 13 Redistribution and use in source and binary forms, with or without
Kojto 124:2241e3a39974 14 modification, are permitted provided that the following conditions are met:
Kojto 124:2241e3a39974 15 - Redistributions of source code must retain the above copyright
Kojto 124:2241e3a39974 16 notice, this list of conditions and the following disclaimer.
Kojto 124:2241e3a39974 17 - Redistributions in binary form must reproduce the above copyright
Kojto 124:2241e3a39974 18 notice, this list of conditions and the following disclaimer in the
Kojto 124:2241e3a39974 19 documentation and/or other materials provided with the distribution.
Kojto 124:2241e3a39974 20 - Neither the name of ARM nor the names of its contributors may be used
Kojto 124:2241e3a39974 21 to endorse or promote products derived from this software without
Kojto 124:2241e3a39974 22 specific prior written permission.
Kojto 124:2241e3a39974 23 *
Kojto 124:2241e3a39974 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Kojto 124:2241e3a39974 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Kojto 124:2241e3a39974 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
Kojto 124:2241e3a39974 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
Kojto 124:2241e3a39974 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
Kojto 124:2241e3a39974 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
Kojto 124:2241e3a39974 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
Kojto 124:2241e3a39974 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
Kojto 124:2241e3a39974 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
Kojto 124:2241e3a39974 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
Kojto 124:2241e3a39974 34 POSSIBILITY OF SUCH DAMAGE.
Kojto 124:2241e3a39974 35 ---------------------------------------------------------------------------*/
Kojto 124:2241e3a39974 36
Kojto 124:2241e3a39974 37
Kojto 124:2241e3a39974 38 #if defined ( __ICCARM__ )
Kojto 124:2241e3a39974 39 #pragma system_include /* treat file as system include file for MISRA check */
Kojto 124:2241e3a39974 40 #endif
Kojto 124:2241e3a39974 41
Kojto 124:2241e3a39974 42 #ifndef __CORE_CM7_H_GENERIC
Kojto 124:2241e3a39974 43 #define __CORE_CM7_H_GENERIC
Kojto 124:2241e3a39974 44
Kojto 124:2241e3a39974 45 #ifdef __cplusplus
Kojto 124:2241e3a39974 46 extern "C" {
Kojto 124:2241e3a39974 47 #endif
Kojto 124:2241e3a39974 48
Kojto 124:2241e3a39974 49 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
Kojto 124:2241e3a39974 50 CMSIS violates the following MISRA-C:2004 rules:
Kojto 124:2241e3a39974 51
Kojto 124:2241e3a39974 52 \li Required Rule 8.5, object/function definition in header file.<br>
Kojto 124:2241e3a39974 53 Function definitions in header files are used to allow 'inlining'.
Kojto 124:2241e3a39974 54
Kojto 124:2241e3a39974 55 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
Kojto 124:2241e3a39974 56 Unions are used for effective representation of core registers.
Kojto 124:2241e3a39974 57
Kojto 124:2241e3a39974 58 \li Advisory Rule 19.7, Function-like macro defined.<br>
Kojto 124:2241e3a39974 59 Function-like macros are used to allow more efficient code.
Kojto 124:2241e3a39974 60 */
Kojto 124:2241e3a39974 61
Kojto 124:2241e3a39974 62
Kojto 124:2241e3a39974 63 /*******************************************************************************
Kojto 124:2241e3a39974 64 * CMSIS definitions
Kojto 124:2241e3a39974 65 ******************************************************************************/
Kojto 124:2241e3a39974 66 /** \ingroup Cortex_M7
Kojto 124:2241e3a39974 67 @{
Kojto 124:2241e3a39974 68 */
Kojto 124:2241e3a39974 69
Kojto 124:2241e3a39974 70 /* CMSIS CM7 definitions */
Kojto 124:2241e3a39974 71 #define __CM7_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */
Kojto 124:2241e3a39974 72 #define __CM7_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */
Kojto 124:2241e3a39974 73 #define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16) | \
Kojto 124:2241e3a39974 74 __CM7_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
Kojto 124:2241e3a39974 75
Kojto 124:2241e3a39974 76 #define __CORTEX_M (0x07) /*!< Cortex-M Core */
Kojto 124:2241e3a39974 77
Kojto 124:2241e3a39974 78
Kojto 124:2241e3a39974 79 #if defined ( __CC_ARM )
Kojto 124:2241e3a39974 80 #define __ASM __asm /*!< asm keyword for ARM Compiler */
Kojto 124:2241e3a39974 81 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
Kojto 124:2241e3a39974 82 #define __STATIC_INLINE static __inline
Kojto 124:2241e3a39974 83
Kojto 124:2241e3a39974 84 #elif defined ( __GNUC__ )
Kojto 124:2241e3a39974 85 #define __ASM __asm /*!< asm keyword for GNU Compiler */
Kojto 124:2241e3a39974 86 #define __INLINE inline /*!< inline keyword for GNU Compiler */
Kojto 124:2241e3a39974 87 #define __STATIC_INLINE static inline
Kojto 124:2241e3a39974 88
Kojto 124:2241e3a39974 89 #elif defined ( __ICCARM__ )
Kojto 124:2241e3a39974 90 #define __ASM __asm /*!< asm keyword for IAR Compiler */
Kojto 124:2241e3a39974 91 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
Kojto 124:2241e3a39974 92 #define __STATIC_INLINE static inline
Kojto 124:2241e3a39974 93
Kojto 124:2241e3a39974 94 #elif defined ( __TMS470__ )
Kojto 124:2241e3a39974 95 #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
Kojto 124:2241e3a39974 96 #define __STATIC_INLINE static inline
Kojto 124:2241e3a39974 97
Kojto 124:2241e3a39974 98 #elif defined ( __TASKING__ )
Kojto 124:2241e3a39974 99 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
Kojto 124:2241e3a39974 100 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
Kojto 124:2241e3a39974 101 #define __STATIC_INLINE static inline
Kojto 124:2241e3a39974 102
Kojto 124:2241e3a39974 103 #elif defined ( __CSMC__ )
Kojto 124:2241e3a39974 104 #define __packed
Kojto 124:2241e3a39974 105 #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
Kojto 124:2241e3a39974 106 #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */
Kojto 124:2241e3a39974 107 #define __STATIC_INLINE static inline
Kojto 124:2241e3a39974 108
Kojto 124:2241e3a39974 109 #endif
Kojto 124:2241e3a39974 110
Kojto 124:2241e3a39974 111 /** __FPU_USED indicates whether an FPU is used or not.
Kojto 124:2241e3a39974 112 For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
Kojto 124:2241e3a39974 113 */
Kojto 124:2241e3a39974 114 #if defined ( __CC_ARM )
Kojto 124:2241e3a39974 115 #if defined __TARGET_FPU_VFP
Kojto 124:2241e3a39974 116 #if (__FPU_PRESENT == 1)
Kojto 124:2241e3a39974 117 #define __FPU_USED 1
Kojto 124:2241e3a39974 118 #else
Kojto 124:2241e3a39974 119 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 124:2241e3a39974 120 #define __FPU_USED 0
Kojto 124:2241e3a39974 121 #endif
Kojto 124:2241e3a39974 122 #else
Kojto 124:2241e3a39974 123 #define __FPU_USED 0
Kojto 124:2241e3a39974 124 #endif
Kojto 124:2241e3a39974 125
Kojto 124:2241e3a39974 126 #elif defined ( __GNUC__ )
Kojto 124:2241e3a39974 127 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
Kojto 124:2241e3a39974 128 #if (__FPU_PRESENT == 1)
Kojto 124:2241e3a39974 129 #define __FPU_USED 1
Kojto 124:2241e3a39974 130 #else
Kojto 124:2241e3a39974 131 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 124:2241e3a39974 132 #define __FPU_USED 0
Kojto 124:2241e3a39974 133 #endif
Kojto 124:2241e3a39974 134 #else
Kojto 124:2241e3a39974 135 #define __FPU_USED 0
Kojto 124:2241e3a39974 136 #endif
Kojto 124:2241e3a39974 137
Kojto 124:2241e3a39974 138 #elif defined ( __ICCARM__ )
Kojto 124:2241e3a39974 139 #if defined __ARMVFP__
Kojto 124:2241e3a39974 140 #if (__FPU_PRESENT == 1)
Kojto 124:2241e3a39974 141 #define __FPU_USED 1
Kojto 124:2241e3a39974 142 #else
Kojto 124:2241e3a39974 143 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 124:2241e3a39974 144 #define __FPU_USED 0
Kojto 124:2241e3a39974 145 #endif
Kojto 124:2241e3a39974 146 #else
Kojto 124:2241e3a39974 147 #define __FPU_USED 0
Kojto 124:2241e3a39974 148 #endif
Kojto 124:2241e3a39974 149
Kojto 124:2241e3a39974 150 #elif defined ( __TMS470__ )
Kojto 124:2241e3a39974 151 #if defined __TI_VFP_SUPPORT__
Kojto 124:2241e3a39974 152 #if (__FPU_PRESENT == 1)
Kojto 124:2241e3a39974 153 #define __FPU_USED 1
Kojto 124:2241e3a39974 154 #else
Kojto 124:2241e3a39974 155 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 124:2241e3a39974 156 #define __FPU_USED 0
Kojto 124:2241e3a39974 157 #endif
Kojto 124:2241e3a39974 158 #else
Kojto 124:2241e3a39974 159 #define __FPU_USED 0
Kojto 124:2241e3a39974 160 #endif
Kojto 124:2241e3a39974 161
Kojto 124:2241e3a39974 162 #elif defined ( __TASKING__ )
Kojto 124:2241e3a39974 163 #if defined __FPU_VFP__
Kojto 124:2241e3a39974 164 #if (__FPU_PRESENT == 1)
Kojto 124:2241e3a39974 165 #define __FPU_USED 1
Kojto 124:2241e3a39974 166 #else
Kojto 124:2241e3a39974 167 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 124:2241e3a39974 168 #define __FPU_USED 0
Kojto 124:2241e3a39974 169 #endif
Kojto 124:2241e3a39974 170 #else
Kojto 124:2241e3a39974 171 #define __FPU_USED 0
Kojto 124:2241e3a39974 172 #endif
Kojto 124:2241e3a39974 173
Kojto 124:2241e3a39974 174 #elif defined ( __CSMC__ ) /* Cosmic */
Kojto 124:2241e3a39974 175 #if ( __CSMC__ & 0x400) // FPU present for parser
Kojto 124:2241e3a39974 176 #if (__FPU_PRESENT == 1)
Kojto 124:2241e3a39974 177 #define __FPU_USED 1
Kojto 124:2241e3a39974 178 #else
Kojto 124:2241e3a39974 179 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 124:2241e3a39974 180 #define __FPU_USED 0
Kojto 124:2241e3a39974 181 #endif
Kojto 124:2241e3a39974 182 #else
Kojto 124:2241e3a39974 183 #define __FPU_USED 0
Kojto 124:2241e3a39974 184 #endif
Kojto 124:2241e3a39974 185 #endif
Kojto 124:2241e3a39974 186
Kojto 124:2241e3a39974 187 #include <stdint.h> /* standard types definitions */
Kojto 124:2241e3a39974 188 #include <core_cmInstr.h> /* Core Instruction Access */
Kojto 124:2241e3a39974 189 #include <core_cmFunc.h> /* Core Function Access */
Kojto 124:2241e3a39974 190 #include <core_cmSimd.h> /* Compiler specific SIMD Intrinsics */
Kojto 124:2241e3a39974 191
Kojto 124:2241e3a39974 192 #ifdef __cplusplus
Kojto 124:2241e3a39974 193 }
Kojto 124:2241e3a39974 194 #endif
Kojto 124:2241e3a39974 195
Kojto 124:2241e3a39974 196 #endif /* __CORE_CM7_H_GENERIC */
Kojto 124:2241e3a39974 197
Kojto 124:2241e3a39974 198 #ifndef __CMSIS_GENERIC
Kojto 124:2241e3a39974 199
Kojto 124:2241e3a39974 200 #ifndef __CORE_CM7_H_DEPENDANT
Kojto 124:2241e3a39974 201 #define __CORE_CM7_H_DEPENDANT
Kojto 124:2241e3a39974 202
Kojto 124:2241e3a39974 203 #ifdef __cplusplus
Kojto 124:2241e3a39974 204 extern "C" {
Kojto 124:2241e3a39974 205 #endif
Kojto 124:2241e3a39974 206
Kojto 124:2241e3a39974 207 /* check device defines and use defaults */
Kojto 124:2241e3a39974 208 #if defined __CHECK_DEVICE_DEFINES
Kojto 124:2241e3a39974 209 #ifndef __CM7_REV
Kojto 124:2241e3a39974 210 #define __CM7_REV 0x0000
Kojto 124:2241e3a39974 211 #warning "__CM7_REV not defined in device header file; using default!"
Kojto 124:2241e3a39974 212 #endif
Kojto 124:2241e3a39974 213
Kojto 124:2241e3a39974 214 #ifndef __FPU_PRESENT
Kojto 124:2241e3a39974 215 #define __FPU_PRESENT 0
Kojto 124:2241e3a39974 216 #warning "__FPU_PRESENT not defined in device header file; using default!"
Kojto 124:2241e3a39974 217 #endif
Kojto 124:2241e3a39974 218
Kojto 124:2241e3a39974 219 #ifndef __MPU_PRESENT
Kojto 124:2241e3a39974 220 #define __MPU_PRESENT 0
Kojto 124:2241e3a39974 221 #warning "__MPU_PRESENT not defined in device header file; using default!"
Kojto 124:2241e3a39974 222 #endif
Kojto 124:2241e3a39974 223
Kojto 124:2241e3a39974 224 #ifndef __ICACHE_PRESENT
Kojto 124:2241e3a39974 225 #define __ICACHE_PRESENT 0
Kojto 124:2241e3a39974 226 #warning "__ICACHE_PRESENT not defined in device header file; using default!"
Kojto 124:2241e3a39974 227 #endif
Kojto 124:2241e3a39974 228
Kojto 124:2241e3a39974 229 #ifndef __DCACHE_PRESENT
Kojto 124:2241e3a39974 230 #define __DCACHE_PRESENT 0
Kojto 124:2241e3a39974 231 #warning "__DCACHE_PRESENT not defined in device header file; using default!"
Kojto 124:2241e3a39974 232 #endif
Kojto 124:2241e3a39974 233
Kojto 124:2241e3a39974 234 #ifndef __DTCM_PRESENT
Kojto 124:2241e3a39974 235 #define __DTCM_PRESENT 0
Kojto 124:2241e3a39974 236 #warning "__DTCM_PRESENT not defined in device header file; using default!"
Kojto 124:2241e3a39974 237 #endif
Kojto 124:2241e3a39974 238
Kojto 124:2241e3a39974 239 #ifndef __NVIC_PRIO_BITS
Kojto 124:2241e3a39974 240 #define __NVIC_PRIO_BITS 3
Kojto 124:2241e3a39974 241 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
Kojto 124:2241e3a39974 242 #endif
Kojto 124:2241e3a39974 243
Kojto 124:2241e3a39974 244 #ifndef __Vendor_SysTickConfig
Kojto 124:2241e3a39974 245 #define __Vendor_SysTickConfig 0
Kojto 124:2241e3a39974 246 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
Kojto 124:2241e3a39974 247 #endif
Kojto 124:2241e3a39974 248 #endif
Kojto 124:2241e3a39974 249
Kojto 124:2241e3a39974 250 /* IO definitions (access restrictions to peripheral registers) */
Kojto 124:2241e3a39974 251 /**
Kojto 124:2241e3a39974 252 \defgroup CMSIS_glob_defs CMSIS Global Defines
Kojto 124:2241e3a39974 253
Kojto 124:2241e3a39974 254 <strong>IO Type Qualifiers</strong> are used
Kojto 124:2241e3a39974 255 \li to specify the access to peripheral variables.
Kojto 124:2241e3a39974 256 \li for automatic generation of peripheral register debug information.
Kojto 124:2241e3a39974 257 */
Kojto 124:2241e3a39974 258 #ifdef __cplusplus
Kojto 124:2241e3a39974 259 #define __I volatile /*!< Defines 'read only' permissions */
Kojto 124:2241e3a39974 260 #else
Kojto 124:2241e3a39974 261 #define __I volatile const /*!< Defines 'read only' permissions */
Kojto 124:2241e3a39974 262 #endif
Kojto 124:2241e3a39974 263 #define __O volatile /*!< Defines 'write only' permissions */
Kojto 124:2241e3a39974 264 #define __IO volatile /*!< Defines 'read / write' permissions */
Kojto 124:2241e3a39974 265
Kojto 124:2241e3a39974 266 /*@} end of group Cortex_M7 */
Kojto 124:2241e3a39974 267
Kojto 124:2241e3a39974 268
Kojto 124:2241e3a39974 269
Kojto 124:2241e3a39974 270 /*******************************************************************************
Kojto 124:2241e3a39974 271 * Register Abstraction
Kojto 124:2241e3a39974 272 Core Register contain:
Kojto 124:2241e3a39974 273 - Core Register
Kojto 124:2241e3a39974 274 - Core NVIC Register
Kojto 124:2241e3a39974 275 - Core SCB Register
Kojto 124:2241e3a39974 276 - Core SysTick Register
Kojto 124:2241e3a39974 277 - Core Debug Register
Kojto 124:2241e3a39974 278 - Core MPU Register
Kojto 124:2241e3a39974 279 - Core FPU Register
Kojto 124:2241e3a39974 280 ******************************************************************************/
Kojto 124:2241e3a39974 281 /** \defgroup CMSIS_core_register Defines and Type Definitions
Kojto 124:2241e3a39974 282 \brief Type definitions and defines for Cortex-M processor based devices.
Kojto 124:2241e3a39974 283 */
Kojto 124:2241e3a39974 284
Kojto 124:2241e3a39974 285 /** \ingroup CMSIS_core_register
Kojto 124:2241e3a39974 286 \defgroup CMSIS_CORE Status and Control Registers
Kojto 124:2241e3a39974 287 \brief Core Register type definitions.
Kojto 124:2241e3a39974 288 @{
Kojto 124:2241e3a39974 289 */
Kojto 124:2241e3a39974 290
Kojto 124:2241e3a39974 291 /** \brief Union type to access the Application Program Status Register (APSR).
Kojto 124:2241e3a39974 292 */
Kojto 124:2241e3a39974 293 typedef union
Kojto 124:2241e3a39974 294 {
Kojto 124:2241e3a39974 295 struct
Kojto 124:2241e3a39974 296 {
Kojto 124:2241e3a39974 297 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
Kojto 124:2241e3a39974 298 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
Kojto 124:2241e3a39974 299 uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
Kojto 124:2241e3a39974 300 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
Kojto 124:2241e3a39974 301 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
Kojto 124:2241e3a39974 302 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
Kojto 124:2241e3a39974 303 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
Kojto 124:2241e3a39974 304 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
Kojto 124:2241e3a39974 305 } b; /*!< Structure used for bit access */
Kojto 124:2241e3a39974 306 uint32_t w; /*!< Type used for word access */
Kojto 124:2241e3a39974 307 } APSR_Type;
Kojto 124:2241e3a39974 308
Kojto 124:2241e3a39974 309 /* APSR Register Definitions */
Kojto 124:2241e3a39974 310 #define APSR_N_Pos 31 /*!< APSR: N Position */
Kojto 124:2241e3a39974 311 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
Kojto 124:2241e3a39974 312
Kojto 124:2241e3a39974 313 #define APSR_Z_Pos 30 /*!< APSR: Z Position */
Kojto 124:2241e3a39974 314 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
Kojto 124:2241e3a39974 315
Kojto 124:2241e3a39974 316 #define APSR_C_Pos 29 /*!< APSR: C Position */
Kojto 124:2241e3a39974 317 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
Kojto 124:2241e3a39974 318
Kojto 124:2241e3a39974 319 #define APSR_V_Pos 28 /*!< APSR: V Position */
Kojto 124:2241e3a39974 320 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
Kojto 124:2241e3a39974 321
Kojto 124:2241e3a39974 322 #define APSR_Q_Pos 27 /*!< APSR: Q Position */
Kojto 124:2241e3a39974 323 #define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
Kojto 124:2241e3a39974 324
Kojto 124:2241e3a39974 325 #define APSR_GE_Pos 16 /*!< APSR: GE Position */
Kojto 124:2241e3a39974 326 #define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */
Kojto 124:2241e3a39974 327
Kojto 124:2241e3a39974 328
Kojto 124:2241e3a39974 329 /** \brief Union type to access the Interrupt Program Status Register (IPSR).
Kojto 124:2241e3a39974 330 */
Kojto 124:2241e3a39974 331 typedef union
Kojto 124:2241e3a39974 332 {
Kojto 124:2241e3a39974 333 struct
Kojto 124:2241e3a39974 334 {
Kojto 124:2241e3a39974 335 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
Kojto 124:2241e3a39974 336 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
Kojto 124:2241e3a39974 337 } b; /*!< Structure used for bit access */
Kojto 124:2241e3a39974 338 uint32_t w; /*!< Type used for word access */
Kojto 124:2241e3a39974 339 } IPSR_Type;
Kojto 124:2241e3a39974 340
Kojto 124:2241e3a39974 341 /* IPSR Register Definitions */
Kojto 124:2241e3a39974 342 #define IPSR_ISR_Pos 0 /*!< IPSR: ISR Position */
Kojto 124:2241e3a39974 343 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
Kojto 124:2241e3a39974 344
Kojto 124:2241e3a39974 345
Kojto 124:2241e3a39974 346 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
Kojto 124:2241e3a39974 347 */
Kojto 124:2241e3a39974 348 typedef union
Kojto 124:2241e3a39974 349 {
Kojto 124:2241e3a39974 350 struct
Kojto 124:2241e3a39974 351 {
Kojto 124:2241e3a39974 352 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
Kojto 124:2241e3a39974 353 uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
Kojto 124:2241e3a39974 354 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
Kojto 124:2241e3a39974 355 uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
Kojto 124:2241e3a39974 356 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
Kojto 124:2241e3a39974 357 uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
Kojto 124:2241e3a39974 358 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
Kojto 124:2241e3a39974 359 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
Kojto 124:2241e3a39974 360 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
Kojto 124:2241e3a39974 361 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
Kojto 124:2241e3a39974 362 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
Kojto 124:2241e3a39974 363 } b; /*!< Structure used for bit access */
Kojto 124:2241e3a39974 364 uint32_t w; /*!< Type used for word access */
Kojto 124:2241e3a39974 365 } xPSR_Type;
Kojto 124:2241e3a39974 366
Kojto 124:2241e3a39974 367 /* xPSR Register Definitions */
Kojto 124:2241e3a39974 368 #define xPSR_N_Pos 31 /*!< xPSR: N Position */
Kojto 124:2241e3a39974 369 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
Kojto 124:2241e3a39974 370
Kojto 124:2241e3a39974 371 #define xPSR_Z_Pos 30 /*!< xPSR: Z Position */
Kojto 124:2241e3a39974 372 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
Kojto 124:2241e3a39974 373
Kojto 124:2241e3a39974 374 #define xPSR_C_Pos 29 /*!< xPSR: C Position */
Kojto 124:2241e3a39974 375 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
Kojto 124:2241e3a39974 376
Kojto 124:2241e3a39974 377 #define xPSR_V_Pos 28 /*!< xPSR: V Position */
Kojto 124:2241e3a39974 378 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
Kojto 124:2241e3a39974 379
Kojto 124:2241e3a39974 380 #define xPSR_Q_Pos 27 /*!< xPSR: Q Position */
Kojto 124:2241e3a39974 381 #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
Kojto 124:2241e3a39974 382
Kojto 124:2241e3a39974 383 #define xPSR_IT_Pos 25 /*!< xPSR: IT Position */
Kojto 124:2241e3a39974 384 #define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */
Kojto 124:2241e3a39974 385
Kojto 124:2241e3a39974 386 #define xPSR_T_Pos 24 /*!< xPSR: T Position */
Kojto 124:2241e3a39974 387 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
Kojto 124:2241e3a39974 388
Kojto 124:2241e3a39974 389 #define xPSR_GE_Pos 16 /*!< xPSR: GE Position */
Kojto 124:2241e3a39974 390 #define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */
Kojto 124:2241e3a39974 391
Kojto 124:2241e3a39974 392 #define xPSR_ISR_Pos 0 /*!< xPSR: ISR Position */
Kojto 124:2241e3a39974 393 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
Kojto 124:2241e3a39974 394
Kojto 124:2241e3a39974 395
Kojto 124:2241e3a39974 396 /** \brief Union type to access the Control Registers (CONTROL).
Kojto 124:2241e3a39974 397 */
Kojto 124:2241e3a39974 398 typedef union
Kojto 124:2241e3a39974 399 {
Kojto 124:2241e3a39974 400 struct
Kojto 124:2241e3a39974 401 {
Kojto 124:2241e3a39974 402 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
Kojto 124:2241e3a39974 403 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
Kojto 124:2241e3a39974 404 uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
Kojto 124:2241e3a39974 405 uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
Kojto 124:2241e3a39974 406 } b; /*!< Structure used for bit access */
Kojto 124:2241e3a39974 407 uint32_t w; /*!< Type used for word access */
Kojto 124:2241e3a39974 408 } CONTROL_Type;
Kojto 124:2241e3a39974 409
Kojto 124:2241e3a39974 410 /* CONTROL Register Definitions */
Kojto 124:2241e3a39974 411 #define CONTROL_FPCA_Pos 2 /*!< CONTROL: FPCA Position */
Kojto 124:2241e3a39974 412 #define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */
Kojto 124:2241e3a39974 413
Kojto 124:2241e3a39974 414 #define CONTROL_SPSEL_Pos 1 /*!< CONTROL: SPSEL Position */
Kojto 124:2241e3a39974 415 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
Kojto 124:2241e3a39974 416
Kojto 124:2241e3a39974 417 #define CONTROL_nPRIV_Pos 0 /*!< CONTROL: nPRIV Position */
Kojto 124:2241e3a39974 418 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
Kojto 124:2241e3a39974 419
Kojto 124:2241e3a39974 420 /*@} end of group CMSIS_CORE */
Kojto 124:2241e3a39974 421
Kojto 124:2241e3a39974 422
Kojto 124:2241e3a39974 423 /** \ingroup CMSIS_core_register
Kojto 124:2241e3a39974 424 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
Kojto 124:2241e3a39974 425 \brief Type definitions for the NVIC Registers
Kojto 124:2241e3a39974 426 @{
Kojto 124:2241e3a39974 427 */
Kojto 124:2241e3a39974 428
Kojto 124:2241e3a39974 429 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
Kojto 124:2241e3a39974 430 */
Kojto 124:2241e3a39974 431 typedef struct
Kojto 124:2241e3a39974 432 {
Kojto 124:2241e3a39974 433 __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
Kojto 124:2241e3a39974 434 uint32_t RESERVED0[24];
Kojto 124:2241e3a39974 435 __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
Kojto 124:2241e3a39974 436 uint32_t RSERVED1[24];
Kojto 124:2241e3a39974 437 __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
Kojto 124:2241e3a39974 438 uint32_t RESERVED2[24];
Kojto 124:2241e3a39974 439 __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
Kojto 124:2241e3a39974 440 uint32_t RESERVED3[24];
Kojto 124:2241e3a39974 441 __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
Kojto 124:2241e3a39974 442 uint32_t RESERVED4[56];
Kojto 124:2241e3a39974 443 __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
Kojto 124:2241e3a39974 444 uint32_t RESERVED5[644];
Kojto 124:2241e3a39974 445 __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
Kojto 124:2241e3a39974 446 } NVIC_Type;
Kojto 124:2241e3a39974 447
Kojto 124:2241e3a39974 448 /* Software Triggered Interrupt Register Definitions */
Kojto 124:2241e3a39974 449 #define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */
Kojto 124:2241e3a39974 450 #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
Kojto 124:2241e3a39974 451
Kojto 124:2241e3a39974 452 /*@} end of group CMSIS_NVIC */
Kojto 124:2241e3a39974 453
Kojto 124:2241e3a39974 454
Kojto 124:2241e3a39974 455 /** \ingroup CMSIS_core_register
Kojto 124:2241e3a39974 456 \defgroup CMSIS_SCB System Control Block (SCB)
Kojto 124:2241e3a39974 457 \brief Type definitions for the System Control Block Registers
Kojto 124:2241e3a39974 458 @{
Kojto 124:2241e3a39974 459 */
Kojto 124:2241e3a39974 460
Kojto 124:2241e3a39974 461 /** \brief Structure type to access the System Control Block (SCB).
Kojto 124:2241e3a39974 462 */
Kojto 124:2241e3a39974 463 typedef struct
Kojto 124:2241e3a39974 464 {
Kojto 124:2241e3a39974 465 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
Kojto 124:2241e3a39974 466 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
Kojto 124:2241e3a39974 467 __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
Kojto 124:2241e3a39974 468 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
Kojto 124:2241e3a39974 469 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
Kojto 124:2241e3a39974 470 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
Kojto 124:2241e3a39974 471 __IO uint8_t SHPR[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
Kojto 124:2241e3a39974 472 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
Kojto 124:2241e3a39974 473 __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
Kojto 124:2241e3a39974 474 __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
Kojto 124:2241e3a39974 475 __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
Kojto 124:2241e3a39974 476 __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
Kojto 124:2241e3a39974 477 __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
Kojto 124:2241e3a39974 478 __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
Kojto 124:2241e3a39974 479 __I uint32_t ID_PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
Kojto 124:2241e3a39974 480 __I uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
Kojto 124:2241e3a39974 481 __I uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
Kojto 124:2241e3a39974 482 __I uint32_t ID_MFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
Kojto 124:2241e3a39974 483 __I uint32_t ID_ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
Kojto 124:2241e3a39974 484 uint32_t RESERVED0[1];
Kojto 124:2241e3a39974 485 __I uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */
Kojto 124:2241e3a39974 486 __I uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */
Kojto 124:2241e3a39974 487 __I uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */
Kojto 124:2241e3a39974 488 __IO uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */
Kojto 124:2241e3a39974 489 __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
Kojto 124:2241e3a39974 490 uint32_t RESERVED3[93];
Kojto 124:2241e3a39974 491 __O uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */
Kojto 124:2241e3a39974 492 uint32_t RESERVED4[15];
Kojto 124:2241e3a39974 493 __I uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */
Kojto 124:2241e3a39974 494 __I uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */
Kojto 124:2241e3a39974 495 __I uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 1 */
Kojto 124:2241e3a39974 496 uint32_t RESERVED5[1];
Kojto 124:2241e3a39974 497 __O uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */
Kojto 124:2241e3a39974 498 uint32_t RESERVED6[1];
Kojto 124:2241e3a39974 499 __O uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */
Kojto 124:2241e3a39974 500 __O uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */
Kojto 124:2241e3a39974 501 __O uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */
Kojto 124:2241e3a39974 502 __O uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */
Kojto 124:2241e3a39974 503 __O uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */
Kojto 124:2241e3a39974 504 __O uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */
Kojto 124:2241e3a39974 505 __O uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */
Kojto 124:2241e3a39974 506 __O uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */
Kojto 124:2241e3a39974 507 uint32_t RESERVED7[6];
Kojto 124:2241e3a39974 508 __IO uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */
Kojto 124:2241e3a39974 509 __IO uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */
Kojto 124:2241e3a39974 510 __IO uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */
Kojto 124:2241e3a39974 511 __IO uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */
Kojto 124:2241e3a39974 512 __IO uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */
Kojto 124:2241e3a39974 513 uint32_t RESERVED8[1];
Kojto 124:2241e3a39974 514 __IO uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */
Kojto 124:2241e3a39974 515 } SCB_Type;
Kojto 124:2241e3a39974 516
Kojto 124:2241e3a39974 517 /* SCB CPUID Register Definitions */
Kojto 124:2241e3a39974 518 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
Kojto 124:2241e3a39974 519 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
Kojto 124:2241e3a39974 520
Kojto 124:2241e3a39974 521 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
Kojto 124:2241e3a39974 522 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
Kojto 124:2241e3a39974 523
Kojto 124:2241e3a39974 524 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
Kojto 124:2241e3a39974 525 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
Kojto 124:2241e3a39974 526
Kojto 124:2241e3a39974 527 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
Kojto 124:2241e3a39974 528 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
Kojto 124:2241e3a39974 529
Kojto 124:2241e3a39974 530 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
Kojto 124:2241e3a39974 531 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
Kojto 124:2241e3a39974 532
Kojto 124:2241e3a39974 533 /* SCB Interrupt Control State Register Definitions */
Kojto 124:2241e3a39974 534 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
Kojto 124:2241e3a39974 535 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
Kojto 124:2241e3a39974 536
Kojto 124:2241e3a39974 537 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
Kojto 124:2241e3a39974 538 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
Kojto 124:2241e3a39974 539
Kojto 124:2241e3a39974 540 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
Kojto 124:2241e3a39974 541 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
Kojto 124:2241e3a39974 542
Kojto 124:2241e3a39974 543 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
Kojto 124:2241e3a39974 544 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
Kojto 124:2241e3a39974 545
Kojto 124:2241e3a39974 546 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
Kojto 124:2241e3a39974 547 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
Kojto 124:2241e3a39974 548
Kojto 124:2241e3a39974 549 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
Kojto 124:2241e3a39974 550 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
Kojto 124:2241e3a39974 551
Kojto 124:2241e3a39974 552 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
Kojto 124:2241e3a39974 553 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
Kojto 124:2241e3a39974 554
Kojto 124:2241e3a39974 555 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
Kojto 124:2241e3a39974 556 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
Kojto 124:2241e3a39974 557
Kojto 124:2241e3a39974 558 #define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */
Kojto 124:2241e3a39974 559 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
Kojto 124:2241e3a39974 560
Kojto 124:2241e3a39974 561 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
Kojto 124:2241e3a39974 562 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
Kojto 124:2241e3a39974 563
Kojto 124:2241e3a39974 564 /* SCB Vector Table Offset Register Definitions */
Kojto 124:2241e3a39974 565 #define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
Kojto 124:2241e3a39974 566 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
Kojto 124:2241e3a39974 567
Kojto 124:2241e3a39974 568 /* SCB Application Interrupt and Reset Control Register Definitions */
Kojto 124:2241e3a39974 569 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
Kojto 124:2241e3a39974 570 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
Kojto 124:2241e3a39974 571
Kojto 124:2241e3a39974 572 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
Kojto 124:2241e3a39974 573 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
Kojto 124:2241e3a39974 574
Kojto 124:2241e3a39974 575 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
Kojto 124:2241e3a39974 576 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
Kojto 124:2241e3a39974 577
Kojto 124:2241e3a39974 578 #define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */
Kojto 124:2241e3a39974 579 #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
Kojto 124:2241e3a39974 580
Kojto 124:2241e3a39974 581 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
Kojto 124:2241e3a39974 582 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
Kojto 124:2241e3a39974 583
Kojto 124:2241e3a39974 584 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
Kojto 124:2241e3a39974 585 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
Kojto 124:2241e3a39974 586
Kojto 124:2241e3a39974 587 #define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */
Kojto 124:2241e3a39974 588 #define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */
Kojto 124:2241e3a39974 589
Kojto 124:2241e3a39974 590 /* SCB System Control Register Definitions */
Kojto 124:2241e3a39974 591 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
Kojto 124:2241e3a39974 592 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
Kojto 124:2241e3a39974 593
Kojto 124:2241e3a39974 594 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
Kojto 124:2241e3a39974 595 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
Kojto 124:2241e3a39974 596
Kojto 124:2241e3a39974 597 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
Kojto 124:2241e3a39974 598 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
Kojto 124:2241e3a39974 599
Kojto 124:2241e3a39974 600 /* SCB Configuration Control Register Definitions */
Kojto 124:2241e3a39974 601 #define SCB_CCR_BP_Pos 18 /*!< SCB CCR: Branch prediction enable bit Position */
Kojto 124:2241e3a39974 602 #define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: Branch prediction enable bit Mask */
Kojto 124:2241e3a39974 603
Kojto 124:2241e3a39974 604 #define SCB_CCR_IC_Pos 17 /*!< SCB CCR: Instruction cache enable bit Position */
Kojto 124:2241e3a39974 605 #define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: Instruction cache enable bit Mask */
Kojto 124:2241e3a39974 606
Kojto 124:2241e3a39974 607 #define SCB_CCR_DC_Pos 16 /*!< SCB CCR: Cache enable bit Position */
Kojto 124:2241e3a39974 608 #define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: Cache enable bit Mask */
Kojto 124:2241e3a39974 609
Kojto 124:2241e3a39974 610 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
Kojto 124:2241e3a39974 611 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
Kojto 124:2241e3a39974 612
Kojto 124:2241e3a39974 613 #define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */
Kojto 124:2241e3a39974 614 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
Kojto 124:2241e3a39974 615
Kojto 124:2241e3a39974 616 #define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */
Kojto 124:2241e3a39974 617 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
Kojto 124:2241e3a39974 618
Kojto 124:2241e3a39974 619 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
Kojto 124:2241e3a39974 620 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
Kojto 124:2241e3a39974 621
Kojto 124:2241e3a39974 622 #define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */
Kojto 124:2241e3a39974 623 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
Kojto 124:2241e3a39974 624
Kojto 124:2241e3a39974 625 #define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */
Kojto 124:2241e3a39974 626 #define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */
Kojto 124:2241e3a39974 627
Kojto 124:2241e3a39974 628 /* SCB System Handler Control and State Register Definitions */
Kojto 124:2241e3a39974 629 #define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */
Kojto 124:2241e3a39974 630 #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
Kojto 124:2241e3a39974 631
Kojto 124:2241e3a39974 632 #define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */
Kojto 124:2241e3a39974 633 #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
Kojto 124:2241e3a39974 634
Kojto 124:2241e3a39974 635 #define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */
Kojto 124:2241e3a39974 636 #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
Kojto 124:2241e3a39974 637
Kojto 124:2241e3a39974 638 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
Kojto 124:2241e3a39974 639 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
Kojto 124:2241e3a39974 640
Kojto 124:2241e3a39974 641 #define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */
Kojto 124:2241e3a39974 642 #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
Kojto 124:2241e3a39974 643
Kojto 124:2241e3a39974 644 #define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */
Kojto 124:2241e3a39974 645 #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
Kojto 124:2241e3a39974 646
Kojto 124:2241e3a39974 647 #define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */
Kojto 124:2241e3a39974 648 #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
Kojto 124:2241e3a39974 649
Kojto 124:2241e3a39974 650 #define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */
Kojto 124:2241e3a39974 651 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
Kojto 124:2241e3a39974 652
Kojto 124:2241e3a39974 653 #define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */
Kojto 124:2241e3a39974 654 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
Kojto 124:2241e3a39974 655
Kojto 124:2241e3a39974 656 #define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */
Kojto 124:2241e3a39974 657 #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
Kojto 124:2241e3a39974 658
Kojto 124:2241e3a39974 659 #define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */
Kojto 124:2241e3a39974 660 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
Kojto 124:2241e3a39974 661
Kojto 124:2241e3a39974 662 #define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */
Kojto 124:2241e3a39974 663 #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
Kojto 124:2241e3a39974 664
Kojto 124:2241e3a39974 665 #define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */
Kojto 124:2241e3a39974 666 #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
Kojto 124:2241e3a39974 667
Kojto 124:2241e3a39974 668 #define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */
Kojto 124:2241e3a39974 669 #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
Kojto 124:2241e3a39974 670
Kojto 124:2241e3a39974 671 /* SCB Configurable Fault Status Registers Definitions */
Kojto 124:2241e3a39974 672 #define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */
Kojto 124:2241e3a39974 673 #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
Kojto 124:2241e3a39974 674
Kojto 124:2241e3a39974 675 #define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */
Kojto 124:2241e3a39974 676 #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
Kojto 124:2241e3a39974 677
Kojto 124:2241e3a39974 678 #define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */
Kojto 124:2241e3a39974 679 #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
Kojto 124:2241e3a39974 680
Kojto 124:2241e3a39974 681 /* SCB Hard Fault Status Registers Definitions */
Kojto 124:2241e3a39974 682 #define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */
Kojto 124:2241e3a39974 683 #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
Kojto 124:2241e3a39974 684
Kojto 124:2241e3a39974 685 #define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */
Kojto 124:2241e3a39974 686 #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
Kojto 124:2241e3a39974 687
Kojto 124:2241e3a39974 688 #define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */
Kojto 124:2241e3a39974 689 #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
Kojto 124:2241e3a39974 690
Kojto 124:2241e3a39974 691 /* SCB Debug Fault Status Register Definitions */
Kojto 124:2241e3a39974 692 #define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */
Kojto 124:2241e3a39974 693 #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
Kojto 124:2241e3a39974 694
Kojto 124:2241e3a39974 695 #define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */
Kojto 124:2241e3a39974 696 #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
Kojto 124:2241e3a39974 697
Kojto 124:2241e3a39974 698 #define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */
Kojto 124:2241e3a39974 699 #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
Kojto 124:2241e3a39974 700
Kojto 124:2241e3a39974 701 #define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */
Kojto 124:2241e3a39974 702 #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
Kojto 124:2241e3a39974 703
Kojto 124:2241e3a39974 704 #define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */
Kojto 124:2241e3a39974 705 #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
Kojto 124:2241e3a39974 706
Kojto 124:2241e3a39974 707 /* Cache Level ID register */
Kojto 124:2241e3a39974 708 #define SCB_CLIDR_LOUU_Pos 27 /*!< SCB CLIDR: LoUU Position */
Kojto 124:2241e3a39974 709 #define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */
Kojto 124:2241e3a39974 710
Kojto 124:2241e3a39974 711 #define SCB_CLIDR_LOC_Pos 24 /*!< SCB CLIDR: LoC Position */
Kojto 124:2241e3a39974 712 #define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_FORMAT_Pos) /*!< SCB CLIDR: LoC Mask */
Kojto 124:2241e3a39974 713
Kojto 124:2241e3a39974 714 /* Cache Type register */
Kojto 124:2241e3a39974 715 #define SCB_CTR_FORMAT_Pos 29 /*!< SCB CTR: Format Position */
Kojto 124:2241e3a39974 716 #define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */
Kojto 124:2241e3a39974 717
Kojto 124:2241e3a39974 718 #define SCB_CTR_CWG_Pos 24 /*!< SCB CTR: CWG Position */
Kojto 124:2241e3a39974 719 #define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */
Kojto 124:2241e3a39974 720
Kojto 124:2241e3a39974 721 #define SCB_CTR_ERG_Pos 20 /*!< SCB CTR: ERG Position */
Kojto 124:2241e3a39974 722 #define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */
Kojto 124:2241e3a39974 723
Kojto 124:2241e3a39974 724 #define SCB_CTR_DMINLINE_Pos 16 /*!< SCB CTR: DminLine Position */
Kojto 124:2241e3a39974 725 #define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */
Kojto 124:2241e3a39974 726
Kojto 124:2241e3a39974 727 #define SCB_CTR_IMINLINE_Pos 0 /*!< SCB CTR: ImInLine Position */
Kojto 124:2241e3a39974 728 #define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */
Kojto 124:2241e3a39974 729
Kojto 124:2241e3a39974 730 /* Cache Size ID Register */
Kojto 124:2241e3a39974 731 #define SCB_CCSIDR_WT_Pos 31 /*!< SCB CCSIDR: WT Position */
Kojto 124:2241e3a39974 732 #define SCB_CCSIDR_WT_Msk (7UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */
Kojto 124:2241e3a39974 733
Kojto 124:2241e3a39974 734 #define SCB_CCSIDR_WB_Pos 30 /*!< SCB CCSIDR: WB Position */
Kojto 124:2241e3a39974 735 #define SCB_CCSIDR_WB_Msk (7UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */
Kojto 124:2241e3a39974 736
Kojto 124:2241e3a39974 737 #define SCB_CCSIDR_RA_Pos 29 /*!< SCB CCSIDR: RA Position */
Kojto 124:2241e3a39974 738 #define SCB_CCSIDR_RA_Msk (7UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */
Kojto 124:2241e3a39974 739
Kojto 124:2241e3a39974 740 #define SCB_CCSIDR_WA_Pos 28 /*!< SCB CCSIDR: WA Position */
Kojto 124:2241e3a39974 741 #define SCB_CCSIDR_WA_Msk (7UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */
Kojto 124:2241e3a39974 742
Kojto 124:2241e3a39974 743 #define SCB_CCSIDR_NUMSETS_Pos 13 /*!< SCB CCSIDR: NumSets Position */
Kojto 124:2241e3a39974 744 #define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */
Kojto 124:2241e3a39974 745
Kojto 124:2241e3a39974 746 #define SCB_CCSIDR_ASSOCIATIVITY_Pos 3 /*!< SCB CCSIDR: Associativity Position */
Kojto 124:2241e3a39974 747 #define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */
Kojto 124:2241e3a39974 748
Kojto 124:2241e3a39974 749 #define SCB_CCSIDR_LINESIZE_Pos 0 /*!< SCB CCSIDR: LineSize Position */
Kojto 124:2241e3a39974 750 #define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */
Kojto 124:2241e3a39974 751
Kojto 124:2241e3a39974 752 /* Cache Size Selection Register */
Kojto 124:2241e3a39974 753 #define SCB_CSSELR_LEVEL_Pos 1 /*!< SCB CSSELR: Level Position */
Kojto 124:2241e3a39974 754 #define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */
Kojto 124:2241e3a39974 755
Kojto 124:2241e3a39974 756 #define SCB_CSSELR_IND_Pos 0 /*!< SCB CSSELR: InD Position */
Kojto 124:2241e3a39974 757 #define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */
Kojto 124:2241e3a39974 758
Kojto 124:2241e3a39974 759 /* SCB Software Triggered Interrupt Register */
Kojto 124:2241e3a39974 760 #define SCB_STIR_INTID_Pos 0 /*!< SCB STIR: INTID Position */
Kojto 124:2241e3a39974 761 #define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */
Kojto 124:2241e3a39974 762
Kojto 124:2241e3a39974 763 /* Instruction Tightly-Coupled Memory Control Register*/
Kojto 124:2241e3a39974 764 #define SCB_ITCMCR_SZ_Pos 3 /*!< SCB ITCMCR: SZ Position */
Kojto 124:2241e3a39974 765 #define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */
Kojto 124:2241e3a39974 766
Kojto 124:2241e3a39974 767 #define SCB_ITCMCR_RETEN_Pos 2 /*!< SCB ITCMCR: RETEN Position */
Kojto 124:2241e3a39974 768 #define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */
Kojto 124:2241e3a39974 769
Kojto 124:2241e3a39974 770 #define SCB_ITCMCR_RMW_Pos 1 /*!< SCB ITCMCR: RMW Position */
Kojto 124:2241e3a39974 771 #define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */
Kojto 124:2241e3a39974 772
Kojto 124:2241e3a39974 773 #define SCB_ITCMCR_EN_Pos 0 /*!< SCB ITCMCR: EN Position */
Kojto 124:2241e3a39974 774 #define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */
Kojto 124:2241e3a39974 775
Kojto 124:2241e3a39974 776 /* Data Tightly-Coupled Memory Control Registers */
Kojto 124:2241e3a39974 777 #define SCB_DTCMCR_SZ_Pos 3 /*!< SCB DTCMCR: SZ Position */
Kojto 124:2241e3a39974 778 #define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */
Kojto 124:2241e3a39974 779
Kojto 124:2241e3a39974 780 #define SCB_DTCMCR_RETEN_Pos 2 /*!< SCB DTCMCR: RETEN Position */
Kojto 124:2241e3a39974 781 #define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */
Kojto 124:2241e3a39974 782
Kojto 124:2241e3a39974 783 #define SCB_DTCMCR_RMW_Pos 1 /*!< SCB DTCMCR: RMW Position */
Kojto 124:2241e3a39974 784 #define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */
Kojto 124:2241e3a39974 785
Kojto 124:2241e3a39974 786 #define SCB_DTCMCR_EN_Pos 0 /*!< SCB DTCMCR: EN Position */
Kojto 124:2241e3a39974 787 #define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */
Kojto 124:2241e3a39974 788
Kojto 124:2241e3a39974 789 /* AHBP Control Register */
Kojto 124:2241e3a39974 790 #define SCB_AHBPCR_SZ_Pos 1 /*!< SCB AHBPCR: SZ Position */
Kojto 124:2241e3a39974 791 #define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */
Kojto 124:2241e3a39974 792
Kojto 124:2241e3a39974 793 #define SCB_AHBPCR_EN_Pos 0 /*!< SCB AHBPCR: EN Position */
Kojto 124:2241e3a39974 794 #define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */
Kojto 124:2241e3a39974 795
Kojto 124:2241e3a39974 796 /* L1 Cache Control Register */
Kojto 124:2241e3a39974 797 #define SCB_CACR_FORCEWT_Pos 2 /*!< SCB CACR: FORCEWT Position */
Kojto 124:2241e3a39974 798 #define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */
Kojto 124:2241e3a39974 799
Kojto 124:2241e3a39974 800 #define SCB_CACR_ECCEN_Pos 1 /*!< SCB CACR: ECCEN Position */
Kojto 124:2241e3a39974 801 #define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */
Kojto 124:2241e3a39974 802
Kojto 124:2241e3a39974 803 #define SCB_CACR_SIWT_Pos 0 /*!< SCB CACR: SIWT Position */
Kojto 124:2241e3a39974 804 #define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */
Kojto 124:2241e3a39974 805
Kojto 124:2241e3a39974 806 /* AHBS control register */
Kojto 124:2241e3a39974 807 #define SCB_AHBSCR_INITCOUNT_Pos 11 /*!< SCB AHBSCR: INITCOUNT Position */
Kojto 124:2241e3a39974 808 #define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */
Kojto 124:2241e3a39974 809
Kojto 124:2241e3a39974 810 #define SCB_AHBSCR_TPRI_Pos 2 /*!< SCB AHBSCR: TPRI Position */
Kojto 124:2241e3a39974 811 #define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */
Kojto 124:2241e3a39974 812
Kojto 124:2241e3a39974 813 #define SCB_AHBSCR_CTL_Pos 0 /*!< SCB AHBSCR: CTL Position*/
Kojto 124:2241e3a39974 814 #define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */
Kojto 124:2241e3a39974 815
Kojto 124:2241e3a39974 816 /* Auxiliary Bus Fault Status Register */
Kojto 124:2241e3a39974 817 #define SCB_ABFSR_AXIMTYPE_Pos 8 /*!< SCB ABFSR: AXIMTYPE Position*/
Kojto 124:2241e3a39974 818 #define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */
Kojto 124:2241e3a39974 819
Kojto 124:2241e3a39974 820 #define SCB_ABFSR_EPPB_Pos 4 /*!< SCB ABFSR: EPPB Position*/
Kojto 124:2241e3a39974 821 #define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */
Kojto 124:2241e3a39974 822
Kojto 124:2241e3a39974 823 #define SCB_ABFSR_AXIM_Pos 3 /*!< SCB ABFSR: AXIM Position*/
Kojto 124:2241e3a39974 824 #define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */
Kojto 124:2241e3a39974 825
Kojto 124:2241e3a39974 826 #define SCB_ABFSR_AHBP_Pos 2 /*!< SCB ABFSR: AHBP Position*/
Kojto 124:2241e3a39974 827 #define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */
Kojto 124:2241e3a39974 828
Kojto 124:2241e3a39974 829 #define SCB_ABFSR_DTCM_Pos 1 /*!< SCB ABFSR: DTCM Position*/
Kojto 124:2241e3a39974 830 #define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */
Kojto 124:2241e3a39974 831
Kojto 124:2241e3a39974 832 #define SCB_ABFSR_ITCM_Pos 0 /*!< SCB ABFSR: ITCM Position*/
Kojto 124:2241e3a39974 833 #define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */
Kojto 124:2241e3a39974 834
Kojto 124:2241e3a39974 835 /*@} end of group CMSIS_SCB */
Kojto 124:2241e3a39974 836
Kojto 124:2241e3a39974 837
Kojto 124:2241e3a39974 838 /** \ingroup CMSIS_core_register
Kojto 124:2241e3a39974 839 \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
Kojto 124:2241e3a39974 840 \brief Type definitions for the System Control and ID Register not in the SCB
Kojto 124:2241e3a39974 841 @{
Kojto 124:2241e3a39974 842 */
Kojto 124:2241e3a39974 843
Kojto 124:2241e3a39974 844 /** \brief Structure type to access the System Control and ID Register not in the SCB.
Kojto 124:2241e3a39974 845 */
Kojto 124:2241e3a39974 846 typedef struct
Kojto 124:2241e3a39974 847 {
Kojto 124:2241e3a39974 848 uint32_t RESERVED0[1];
Kojto 124:2241e3a39974 849 __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
Kojto 124:2241e3a39974 850 __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
Kojto 124:2241e3a39974 851 } SCnSCB_Type;
Kojto 124:2241e3a39974 852
Kojto 124:2241e3a39974 853 /* Interrupt Controller Type Register Definitions */
Kojto 124:2241e3a39974 854 #define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */
Kojto 124:2241e3a39974 855 #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
Kojto 124:2241e3a39974 856
Kojto 124:2241e3a39974 857 /* Auxiliary Control Register Definitions */
Kojto 124:2241e3a39974 858 #define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12 /*!< ACTLR: DISITMATBFLUSH Position */
Kojto 124:2241e3a39974 859 #define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */
Kojto 124:2241e3a39974 860
Kojto 124:2241e3a39974 861 #define SCnSCB_ACTLR_DISRAMODE_Pos 11 /*!< ACTLR: DISRAMODE Position */
Kojto 124:2241e3a39974 862 #define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: DISRAMODE Mask */
Kojto 124:2241e3a39974 863
Kojto 124:2241e3a39974 864 #define SCnSCB_ACTLR_FPEXCODIS_Pos 10 /*!< ACTLR: FPEXCODIS Position */
Kojto 124:2241e3a39974 865 #define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */
Kojto 124:2241e3a39974 866
Kojto 124:2241e3a39974 867 #define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */
Kojto 124:2241e3a39974 868 #define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
Kojto 124:2241e3a39974 869
Kojto 124:2241e3a39974 870 #define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */
Kojto 124:2241e3a39974 871 #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
Kojto 124:2241e3a39974 872
Kojto 124:2241e3a39974 873 /*@} end of group CMSIS_SCnotSCB */
Kojto 124:2241e3a39974 874
Kojto 124:2241e3a39974 875
Kojto 124:2241e3a39974 876 /** \ingroup CMSIS_core_register
Kojto 124:2241e3a39974 877 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
Kojto 124:2241e3a39974 878 \brief Type definitions for the System Timer Registers.
Kojto 124:2241e3a39974 879 @{
Kojto 124:2241e3a39974 880 */
Kojto 124:2241e3a39974 881
Kojto 124:2241e3a39974 882 /** \brief Structure type to access the System Timer (SysTick).
Kojto 124:2241e3a39974 883 */
Kojto 124:2241e3a39974 884 typedef struct
Kojto 124:2241e3a39974 885 {
Kojto 124:2241e3a39974 886 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
Kojto 124:2241e3a39974 887 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
Kojto 124:2241e3a39974 888 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
Kojto 124:2241e3a39974 889 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
Kojto 124:2241e3a39974 890 } SysTick_Type;
Kojto 124:2241e3a39974 891
Kojto 124:2241e3a39974 892 /* SysTick Control / Status Register Definitions */
Kojto 124:2241e3a39974 893 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
Kojto 124:2241e3a39974 894 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
Kojto 124:2241e3a39974 895
Kojto 124:2241e3a39974 896 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
Kojto 124:2241e3a39974 897 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
Kojto 124:2241e3a39974 898
Kojto 124:2241e3a39974 899 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
Kojto 124:2241e3a39974 900 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
Kojto 124:2241e3a39974 901
Kojto 124:2241e3a39974 902 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
Kojto 124:2241e3a39974 903 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
Kojto 124:2241e3a39974 904
Kojto 124:2241e3a39974 905 /* SysTick Reload Register Definitions */
Kojto 124:2241e3a39974 906 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
Kojto 124:2241e3a39974 907 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
Kojto 124:2241e3a39974 908
Kojto 124:2241e3a39974 909 /* SysTick Current Register Definitions */
Kojto 124:2241e3a39974 910 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
Kojto 124:2241e3a39974 911 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
Kojto 124:2241e3a39974 912
Kojto 124:2241e3a39974 913 /* SysTick Calibration Register Definitions */
Kojto 124:2241e3a39974 914 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
Kojto 124:2241e3a39974 915 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
Kojto 124:2241e3a39974 916
Kojto 124:2241e3a39974 917 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
Kojto 124:2241e3a39974 918 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
Kojto 124:2241e3a39974 919
Kojto 124:2241e3a39974 920 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
Kojto 124:2241e3a39974 921 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
Kojto 124:2241e3a39974 922
Kojto 124:2241e3a39974 923 /*@} end of group CMSIS_SysTick */
Kojto 124:2241e3a39974 924
Kojto 124:2241e3a39974 925
Kojto 124:2241e3a39974 926 /** \ingroup CMSIS_core_register
Kojto 124:2241e3a39974 927 \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
Kojto 124:2241e3a39974 928 \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
Kojto 124:2241e3a39974 929 @{
Kojto 124:2241e3a39974 930 */
Kojto 124:2241e3a39974 931
Kojto 124:2241e3a39974 932 /** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
Kojto 124:2241e3a39974 933 */
Kojto 124:2241e3a39974 934 typedef struct
Kojto 124:2241e3a39974 935 {
Kojto 124:2241e3a39974 936 __O union
Kojto 124:2241e3a39974 937 {
Kojto 124:2241e3a39974 938 __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
Kojto 124:2241e3a39974 939 __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
Kojto 124:2241e3a39974 940 __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
Kojto 124:2241e3a39974 941 } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
Kojto 124:2241e3a39974 942 uint32_t RESERVED0[864];
Kojto 124:2241e3a39974 943 __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
Kojto 124:2241e3a39974 944 uint32_t RESERVED1[15];
Kojto 124:2241e3a39974 945 __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
Kojto 124:2241e3a39974 946 uint32_t RESERVED2[15];
Kojto 124:2241e3a39974 947 __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
Kojto 124:2241e3a39974 948 uint32_t RESERVED3[29];
Kojto 124:2241e3a39974 949 __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
Kojto 124:2241e3a39974 950 __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
Kojto 124:2241e3a39974 951 __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
Kojto 124:2241e3a39974 952 uint32_t RESERVED4[43];
Kojto 124:2241e3a39974 953 __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
Kojto 124:2241e3a39974 954 __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
Kojto 124:2241e3a39974 955 uint32_t RESERVED5[6];
Kojto 124:2241e3a39974 956 __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
Kojto 124:2241e3a39974 957 __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
Kojto 124:2241e3a39974 958 __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
Kojto 124:2241e3a39974 959 __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
Kojto 124:2241e3a39974 960 __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
Kojto 124:2241e3a39974 961 __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
Kojto 124:2241e3a39974 962 __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
Kojto 124:2241e3a39974 963 __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
Kojto 124:2241e3a39974 964 __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
Kojto 124:2241e3a39974 965 __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
Kojto 124:2241e3a39974 966 __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
Kojto 124:2241e3a39974 967 __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
Kojto 124:2241e3a39974 968 } ITM_Type;
Kojto 124:2241e3a39974 969
Kojto 124:2241e3a39974 970 /* ITM Trace Privilege Register Definitions */
Kojto 124:2241e3a39974 971 #define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */
Kojto 124:2241e3a39974 972 #define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
Kojto 124:2241e3a39974 973
Kojto 124:2241e3a39974 974 /* ITM Trace Control Register Definitions */
Kojto 124:2241e3a39974 975 #define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */
Kojto 124:2241e3a39974 976 #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
Kojto 124:2241e3a39974 977
Kojto 124:2241e3a39974 978 #define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */
Kojto 124:2241e3a39974 979 #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
Kojto 124:2241e3a39974 980
Kojto 124:2241e3a39974 981 #define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */
Kojto 124:2241e3a39974 982 #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
Kojto 124:2241e3a39974 983
Kojto 124:2241e3a39974 984 #define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */
Kojto 124:2241e3a39974 985 #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
Kojto 124:2241e3a39974 986
Kojto 124:2241e3a39974 987 #define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */
Kojto 124:2241e3a39974 988 #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
Kojto 124:2241e3a39974 989
Kojto 124:2241e3a39974 990 #define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */
Kojto 124:2241e3a39974 991 #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
Kojto 124:2241e3a39974 992
Kojto 124:2241e3a39974 993 #define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */
Kojto 124:2241e3a39974 994 #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
Kojto 124:2241e3a39974 995
Kojto 124:2241e3a39974 996 #define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */
Kojto 124:2241e3a39974 997 #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
Kojto 124:2241e3a39974 998
Kojto 124:2241e3a39974 999 #define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */
Kojto 124:2241e3a39974 1000 #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
Kojto 124:2241e3a39974 1001
Kojto 124:2241e3a39974 1002 /* ITM Integration Write Register Definitions */
Kojto 124:2241e3a39974 1003 #define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */
Kojto 124:2241e3a39974 1004 #define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */
Kojto 124:2241e3a39974 1005
Kojto 124:2241e3a39974 1006 /* ITM Integration Read Register Definitions */
Kojto 124:2241e3a39974 1007 #define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */
Kojto 124:2241e3a39974 1008 #define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */
Kojto 124:2241e3a39974 1009
Kojto 124:2241e3a39974 1010 /* ITM Integration Mode Control Register Definitions */
Kojto 124:2241e3a39974 1011 #define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */
Kojto 124:2241e3a39974 1012 #define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */
Kojto 124:2241e3a39974 1013
Kojto 124:2241e3a39974 1014 /* ITM Lock Status Register Definitions */
Kojto 124:2241e3a39974 1015 #define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */
Kojto 124:2241e3a39974 1016 #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
Kojto 124:2241e3a39974 1017
Kojto 124:2241e3a39974 1018 #define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */
Kojto 124:2241e3a39974 1019 #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
Kojto 124:2241e3a39974 1020
Kojto 124:2241e3a39974 1021 #define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */
Kojto 124:2241e3a39974 1022 #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
Kojto 124:2241e3a39974 1023
Kojto 124:2241e3a39974 1024 /*@}*/ /* end of group CMSIS_ITM */
Kojto 124:2241e3a39974 1025
Kojto 124:2241e3a39974 1026
Kojto 124:2241e3a39974 1027 /** \ingroup CMSIS_core_register
Kojto 124:2241e3a39974 1028 \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
Kojto 124:2241e3a39974 1029 \brief Type definitions for the Data Watchpoint and Trace (DWT)
Kojto 124:2241e3a39974 1030 @{
Kojto 124:2241e3a39974 1031 */
Kojto 124:2241e3a39974 1032
Kojto 124:2241e3a39974 1033 /** \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
Kojto 124:2241e3a39974 1034 */
Kojto 124:2241e3a39974 1035 typedef struct
Kojto 124:2241e3a39974 1036 {
Kojto 124:2241e3a39974 1037 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
Kojto 124:2241e3a39974 1038 __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
Kojto 124:2241e3a39974 1039 __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
Kojto 124:2241e3a39974 1040 __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
Kojto 124:2241e3a39974 1041 __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
Kojto 124:2241e3a39974 1042 __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
Kojto 124:2241e3a39974 1043 __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
Kojto 124:2241e3a39974 1044 __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
Kojto 124:2241e3a39974 1045 __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
Kojto 124:2241e3a39974 1046 __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
Kojto 124:2241e3a39974 1047 __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
Kojto 124:2241e3a39974 1048 uint32_t RESERVED0[1];
Kojto 124:2241e3a39974 1049 __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
Kojto 124:2241e3a39974 1050 __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
Kojto 124:2241e3a39974 1051 __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
Kojto 124:2241e3a39974 1052 uint32_t RESERVED1[1];
Kojto 124:2241e3a39974 1053 __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
Kojto 124:2241e3a39974 1054 __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
Kojto 124:2241e3a39974 1055 __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
Kojto 124:2241e3a39974 1056 uint32_t RESERVED2[1];
Kojto 124:2241e3a39974 1057 __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
Kojto 124:2241e3a39974 1058 __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
Kojto 124:2241e3a39974 1059 __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
Kojto 124:2241e3a39974 1060 uint32_t RESERVED3[981];
Kojto 124:2241e3a39974 1061 __O uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */
Kojto 124:2241e3a39974 1062 __I uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */
Kojto 124:2241e3a39974 1063 } DWT_Type;
Kojto 124:2241e3a39974 1064
Kojto 124:2241e3a39974 1065 /* DWT Control Register Definitions */
Kojto 124:2241e3a39974 1066 #define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */
Kojto 124:2241e3a39974 1067 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
Kojto 124:2241e3a39974 1068
Kojto 124:2241e3a39974 1069 #define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */
Kojto 124:2241e3a39974 1070 #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
Kojto 124:2241e3a39974 1071
Kojto 124:2241e3a39974 1072 #define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */
Kojto 124:2241e3a39974 1073 #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
Kojto 124:2241e3a39974 1074
Kojto 124:2241e3a39974 1075 #define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */
Kojto 124:2241e3a39974 1076 #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
Kojto 124:2241e3a39974 1077
Kojto 124:2241e3a39974 1078 #define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */
Kojto 124:2241e3a39974 1079 #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
Kojto 124:2241e3a39974 1080
Kojto 124:2241e3a39974 1081 #define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */
Kojto 124:2241e3a39974 1082 #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
Kojto 124:2241e3a39974 1083
Kojto 124:2241e3a39974 1084 #define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */
Kojto 124:2241e3a39974 1085 #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
Kojto 124:2241e3a39974 1086
Kojto 124:2241e3a39974 1087 #define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */
Kojto 124:2241e3a39974 1088 #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
Kojto 124:2241e3a39974 1089
Kojto 124:2241e3a39974 1090 #define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */
Kojto 124:2241e3a39974 1091 #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
Kojto 124:2241e3a39974 1092
Kojto 124:2241e3a39974 1093 #define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */
Kojto 124:2241e3a39974 1094 #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
Kojto 124:2241e3a39974 1095
Kojto 124:2241e3a39974 1096 #define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */
Kojto 124:2241e3a39974 1097 #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
Kojto 124:2241e3a39974 1098
Kojto 124:2241e3a39974 1099 #define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */
Kojto 124:2241e3a39974 1100 #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
Kojto 124:2241e3a39974 1101
Kojto 124:2241e3a39974 1102 #define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */
Kojto 124:2241e3a39974 1103 #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
Kojto 124:2241e3a39974 1104
Kojto 124:2241e3a39974 1105 #define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */
Kojto 124:2241e3a39974 1106 #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
Kojto 124:2241e3a39974 1107
Kojto 124:2241e3a39974 1108 #define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */
Kojto 124:2241e3a39974 1109 #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
Kojto 124:2241e3a39974 1110
Kojto 124:2241e3a39974 1111 #define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */
Kojto 124:2241e3a39974 1112 #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
Kojto 124:2241e3a39974 1113
Kojto 124:2241e3a39974 1114 #define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */
Kojto 124:2241e3a39974 1115 #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
Kojto 124:2241e3a39974 1116
Kojto 124:2241e3a39974 1117 #define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */
Kojto 124:2241e3a39974 1118 #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
Kojto 124:2241e3a39974 1119
Kojto 124:2241e3a39974 1120 /* DWT CPI Count Register Definitions */
Kojto 124:2241e3a39974 1121 #define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */
Kojto 124:2241e3a39974 1122 #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
Kojto 124:2241e3a39974 1123
Kojto 124:2241e3a39974 1124 /* DWT Exception Overhead Count Register Definitions */
Kojto 124:2241e3a39974 1125 #define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */
Kojto 124:2241e3a39974 1126 #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
Kojto 124:2241e3a39974 1127
Kojto 124:2241e3a39974 1128 /* DWT Sleep Count Register Definitions */
Kojto 124:2241e3a39974 1129 #define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */
Kojto 124:2241e3a39974 1130 #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
Kojto 124:2241e3a39974 1131
Kojto 124:2241e3a39974 1132 /* DWT LSU Count Register Definitions */
Kojto 124:2241e3a39974 1133 #define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */
Kojto 124:2241e3a39974 1134 #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
Kojto 124:2241e3a39974 1135
Kojto 124:2241e3a39974 1136 /* DWT Folded-instruction Count Register Definitions */
Kojto 124:2241e3a39974 1137 #define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */
Kojto 124:2241e3a39974 1138 #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
Kojto 124:2241e3a39974 1139
Kojto 124:2241e3a39974 1140 /* DWT Comparator Mask Register Definitions */
Kojto 124:2241e3a39974 1141 #define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */
Kojto 124:2241e3a39974 1142 #define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */
Kojto 124:2241e3a39974 1143
Kojto 124:2241e3a39974 1144 /* DWT Comparator Function Register Definitions */
Kojto 124:2241e3a39974 1145 #define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */
Kojto 124:2241e3a39974 1146 #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
Kojto 124:2241e3a39974 1147
Kojto 124:2241e3a39974 1148 #define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */
Kojto 124:2241e3a39974 1149 #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
Kojto 124:2241e3a39974 1150
Kojto 124:2241e3a39974 1151 #define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */
Kojto 124:2241e3a39974 1152 #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
Kojto 124:2241e3a39974 1153
Kojto 124:2241e3a39974 1154 #define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */
Kojto 124:2241e3a39974 1155 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
Kojto 124:2241e3a39974 1156
Kojto 124:2241e3a39974 1157 #define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */
Kojto 124:2241e3a39974 1158 #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
Kojto 124:2241e3a39974 1159
Kojto 124:2241e3a39974 1160 #define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */
Kojto 124:2241e3a39974 1161 #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
Kojto 124:2241e3a39974 1162
Kojto 124:2241e3a39974 1163 #define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */
Kojto 124:2241e3a39974 1164 #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
Kojto 124:2241e3a39974 1165
Kojto 124:2241e3a39974 1166 #define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */
Kojto 124:2241e3a39974 1167 #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
Kojto 124:2241e3a39974 1168
Kojto 124:2241e3a39974 1169 #define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */
Kojto 124:2241e3a39974 1170 #define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */
Kojto 124:2241e3a39974 1171
Kojto 124:2241e3a39974 1172 /*@}*/ /* end of group CMSIS_DWT */
Kojto 124:2241e3a39974 1173
Kojto 124:2241e3a39974 1174
Kojto 124:2241e3a39974 1175 /** \ingroup CMSIS_core_register
Kojto 124:2241e3a39974 1176 \defgroup CMSIS_TPI Trace Port Interface (TPI)
Kojto 124:2241e3a39974 1177 \brief Type definitions for the Trace Port Interface (TPI)
Kojto 124:2241e3a39974 1178 @{
Kojto 124:2241e3a39974 1179 */
Kojto 124:2241e3a39974 1180
Kojto 124:2241e3a39974 1181 /** \brief Structure type to access the Trace Port Interface Register (TPI).
Kojto 124:2241e3a39974 1182 */
Kojto 124:2241e3a39974 1183 typedef struct
Kojto 124:2241e3a39974 1184 {
Kojto 124:2241e3a39974 1185 __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
Kojto 124:2241e3a39974 1186 __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
Kojto 124:2241e3a39974 1187 uint32_t RESERVED0[2];
Kojto 124:2241e3a39974 1188 __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
Kojto 124:2241e3a39974 1189 uint32_t RESERVED1[55];
Kojto 124:2241e3a39974 1190 __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
Kojto 124:2241e3a39974 1191 uint32_t RESERVED2[131];
Kojto 124:2241e3a39974 1192 __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
Kojto 124:2241e3a39974 1193 __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
Kojto 124:2241e3a39974 1194 __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
Kojto 124:2241e3a39974 1195 uint32_t RESERVED3[759];
Kojto 124:2241e3a39974 1196 __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
Kojto 124:2241e3a39974 1197 __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
Kojto 124:2241e3a39974 1198 __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
Kojto 124:2241e3a39974 1199 uint32_t RESERVED4[1];
Kojto 124:2241e3a39974 1200 __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
Kojto 124:2241e3a39974 1201 __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
Kojto 124:2241e3a39974 1202 __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
Kojto 124:2241e3a39974 1203 uint32_t RESERVED5[39];
Kojto 124:2241e3a39974 1204 __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
Kojto 124:2241e3a39974 1205 __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
Kojto 124:2241e3a39974 1206 uint32_t RESERVED7[8];
Kojto 124:2241e3a39974 1207 __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
Kojto 124:2241e3a39974 1208 __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
Kojto 124:2241e3a39974 1209 } TPI_Type;
Kojto 124:2241e3a39974 1210
Kojto 124:2241e3a39974 1211 /* TPI Asynchronous Clock Prescaler Register Definitions */
Kojto 124:2241e3a39974 1212 #define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */
Kojto 124:2241e3a39974 1213 #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
Kojto 124:2241e3a39974 1214
Kojto 124:2241e3a39974 1215 /* TPI Selected Pin Protocol Register Definitions */
Kojto 124:2241e3a39974 1216 #define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */
Kojto 124:2241e3a39974 1217 #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
Kojto 124:2241e3a39974 1218
Kojto 124:2241e3a39974 1219 /* TPI Formatter and Flush Status Register Definitions */
Kojto 124:2241e3a39974 1220 #define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */
Kojto 124:2241e3a39974 1221 #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
Kojto 124:2241e3a39974 1222
Kojto 124:2241e3a39974 1223 #define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */
Kojto 124:2241e3a39974 1224 #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
Kojto 124:2241e3a39974 1225
Kojto 124:2241e3a39974 1226 #define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */
Kojto 124:2241e3a39974 1227 #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
Kojto 124:2241e3a39974 1228
Kojto 124:2241e3a39974 1229 #define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */
Kojto 124:2241e3a39974 1230 #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
Kojto 124:2241e3a39974 1231
Kojto 124:2241e3a39974 1232 /* TPI Formatter and Flush Control Register Definitions */
Kojto 124:2241e3a39974 1233 #define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */
Kojto 124:2241e3a39974 1234 #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
Kojto 124:2241e3a39974 1235
Kojto 124:2241e3a39974 1236 #define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */
Kojto 124:2241e3a39974 1237 #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
Kojto 124:2241e3a39974 1238
Kojto 124:2241e3a39974 1239 /* TPI TRIGGER Register Definitions */
Kojto 124:2241e3a39974 1240 #define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */
Kojto 124:2241e3a39974 1241 #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
Kojto 124:2241e3a39974 1242
Kojto 124:2241e3a39974 1243 /* TPI Integration ETM Data Register Definitions (FIFO0) */
Kojto 124:2241e3a39974 1244 #define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */
Kojto 124:2241e3a39974 1245 #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
Kojto 124:2241e3a39974 1246
Kojto 124:2241e3a39974 1247 #define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */
Kojto 124:2241e3a39974 1248 #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
Kojto 124:2241e3a39974 1249
Kojto 124:2241e3a39974 1250 #define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */
Kojto 124:2241e3a39974 1251 #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
Kojto 124:2241e3a39974 1252
Kojto 124:2241e3a39974 1253 #define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */
Kojto 124:2241e3a39974 1254 #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
Kojto 124:2241e3a39974 1255
Kojto 124:2241e3a39974 1256 #define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */
Kojto 124:2241e3a39974 1257 #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
Kojto 124:2241e3a39974 1258
Kojto 124:2241e3a39974 1259 #define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */
Kojto 124:2241e3a39974 1260 #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
Kojto 124:2241e3a39974 1261
Kojto 124:2241e3a39974 1262 #define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */
Kojto 124:2241e3a39974 1263 #define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
Kojto 124:2241e3a39974 1264
Kojto 124:2241e3a39974 1265 /* TPI ITATBCTR2 Register Definitions */
Kojto 124:2241e3a39974 1266 #define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */
Kojto 124:2241e3a39974 1267 #define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */
Kojto 124:2241e3a39974 1268
Kojto 124:2241e3a39974 1269 /* TPI Integration ITM Data Register Definitions (FIFO1) */
Kojto 124:2241e3a39974 1270 #define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */
Kojto 124:2241e3a39974 1271 #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
Kojto 124:2241e3a39974 1272
Kojto 124:2241e3a39974 1273 #define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */
Kojto 124:2241e3a39974 1274 #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
Kojto 124:2241e3a39974 1275
Kojto 124:2241e3a39974 1276 #define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */
Kojto 124:2241e3a39974 1277 #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
Kojto 124:2241e3a39974 1278
Kojto 124:2241e3a39974 1279 #define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */
Kojto 124:2241e3a39974 1280 #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
Kojto 124:2241e3a39974 1281
Kojto 124:2241e3a39974 1282 #define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */
Kojto 124:2241e3a39974 1283 #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
Kojto 124:2241e3a39974 1284
Kojto 124:2241e3a39974 1285 #define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */
Kojto 124:2241e3a39974 1286 #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
Kojto 124:2241e3a39974 1287
Kojto 124:2241e3a39974 1288 #define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */
Kojto 124:2241e3a39974 1289 #define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
Kojto 124:2241e3a39974 1290
Kojto 124:2241e3a39974 1291 /* TPI ITATBCTR0 Register Definitions */
Kojto 124:2241e3a39974 1292 #define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */
Kojto 124:2241e3a39974 1293 #define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */
Kojto 124:2241e3a39974 1294
Kojto 124:2241e3a39974 1295 /* TPI Integration Mode Control Register Definitions */
Kojto 124:2241e3a39974 1296 #define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */
Kojto 124:2241e3a39974 1297 #define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
Kojto 124:2241e3a39974 1298
Kojto 124:2241e3a39974 1299 /* TPI DEVID Register Definitions */
Kojto 124:2241e3a39974 1300 #define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */
Kojto 124:2241e3a39974 1301 #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
Kojto 124:2241e3a39974 1302
Kojto 124:2241e3a39974 1303 #define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */
Kojto 124:2241e3a39974 1304 #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
Kojto 124:2241e3a39974 1305
Kojto 124:2241e3a39974 1306 #define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */
Kojto 124:2241e3a39974 1307 #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
Kojto 124:2241e3a39974 1308
Kojto 124:2241e3a39974 1309 #define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */
Kojto 124:2241e3a39974 1310 #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
Kojto 124:2241e3a39974 1311
Kojto 124:2241e3a39974 1312 #define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */
Kojto 124:2241e3a39974 1313 #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
Kojto 124:2241e3a39974 1314
Kojto 124:2241e3a39974 1315 #define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */
Kojto 124:2241e3a39974 1316 #define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
Kojto 124:2241e3a39974 1317
Kojto 124:2241e3a39974 1318 /* TPI DEVTYPE Register Definitions */
Kojto 124:2241e3a39974 1319 #define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */
Kojto 124:2241e3a39974 1320 #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
Kojto 124:2241e3a39974 1321
Kojto 124:2241e3a39974 1322 #define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */
Kojto 124:2241e3a39974 1323 #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
Kojto 124:2241e3a39974 1324
Kojto 124:2241e3a39974 1325 /*@}*/ /* end of group CMSIS_TPI */
Kojto 124:2241e3a39974 1326
Kojto 124:2241e3a39974 1327
Kojto 124:2241e3a39974 1328 #if (__MPU_PRESENT == 1)
Kojto 124:2241e3a39974 1329 /** \ingroup CMSIS_core_register
Kojto 124:2241e3a39974 1330 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
Kojto 124:2241e3a39974 1331 \brief Type definitions for the Memory Protection Unit (MPU)
Kojto 124:2241e3a39974 1332 @{
Kojto 124:2241e3a39974 1333 */
Kojto 124:2241e3a39974 1334
Kojto 124:2241e3a39974 1335 /** \brief Structure type to access the Memory Protection Unit (MPU).
Kojto 124:2241e3a39974 1336 */
Kojto 124:2241e3a39974 1337 typedef struct
Kojto 124:2241e3a39974 1338 {
Kojto 124:2241e3a39974 1339 __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
Kojto 124:2241e3a39974 1340 __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
Kojto 124:2241e3a39974 1341 __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
Kojto 124:2241e3a39974 1342 __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
Kojto 124:2241e3a39974 1343 __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
Kojto 124:2241e3a39974 1344 __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
Kojto 124:2241e3a39974 1345 __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
Kojto 124:2241e3a39974 1346 __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
Kojto 124:2241e3a39974 1347 __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
Kojto 124:2241e3a39974 1348 __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
Kojto 124:2241e3a39974 1349 __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
Kojto 124:2241e3a39974 1350 } MPU_Type;
Kojto 124:2241e3a39974 1351
Kojto 124:2241e3a39974 1352 /* MPU Type Register */
Kojto 124:2241e3a39974 1353 #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
Kojto 124:2241e3a39974 1354 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
Kojto 124:2241e3a39974 1355
Kojto 124:2241e3a39974 1356 #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
Kojto 124:2241e3a39974 1357 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
Kojto 124:2241e3a39974 1358
Kojto 124:2241e3a39974 1359 #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
Kojto 124:2241e3a39974 1360 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
Kojto 124:2241e3a39974 1361
Kojto 124:2241e3a39974 1362 /* MPU Control Register */
Kojto 124:2241e3a39974 1363 #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
Kojto 124:2241e3a39974 1364 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
Kojto 124:2241e3a39974 1365
Kojto 124:2241e3a39974 1366 #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
Kojto 124:2241e3a39974 1367 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
Kojto 124:2241e3a39974 1368
Kojto 124:2241e3a39974 1369 #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
Kojto 124:2241e3a39974 1370 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
Kojto 124:2241e3a39974 1371
Kojto 124:2241e3a39974 1372 /* MPU Region Number Register */
Kojto 124:2241e3a39974 1373 #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
Kojto 124:2241e3a39974 1374 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
Kojto 124:2241e3a39974 1375
Kojto 124:2241e3a39974 1376 /* MPU Region Base Address Register */
Kojto 124:2241e3a39974 1377 #define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */
Kojto 124:2241e3a39974 1378 #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
Kojto 124:2241e3a39974 1379
Kojto 124:2241e3a39974 1380 #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
Kojto 124:2241e3a39974 1381 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
Kojto 124:2241e3a39974 1382
Kojto 124:2241e3a39974 1383 #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
Kojto 124:2241e3a39974 1384 #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
Kojto 124:2241e3a39974 1385
Kojto 124:2241e3a39974 1386 /* MPU Region Attribute and Size Register */
Kojto 124:2241e3a39974 1387 #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
Kojto 124:2241e3a39974 1388 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
Kojto 124:2241e3a39974 1389
Kojto 124:2241e3a39974 1390 #define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
Kojto 124:2241e3a39974 1391 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
Kojto 124:2241e3a39974 1392
Kojto 124:2241e3a39974 1393 #define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
Kojto 124:2241e3a39974 1394 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
Kojto 124:2241e3a39974 1395
Kojto 124:2241e3a39974 1396 #define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
Kojto 124:2241e3a39974 1397 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
Kojto 124:2241e3a39974 1398
Kojto 124:2241e3a39974 1399 #define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
Kojto 124:2241e3a39974 1400 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
Kojto 124:2241e3a39974 1401
Kojto 124:2241e3a39974 1402 #define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
Kojto 124:2241e3a39974 1403 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
Kojto 124:2241e3a39974 1404
Kojto 124:2241e3a39974 1405 #define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
Kojto 124:2241e3a39974 1406 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
Kojto 124:2241e3a39974 1407
Kojto 124:2241e3a39974 1408 #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
Kojto 124:2241e3a39974 1409 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
Kojto 124:2241e3a39974 1410
Kojto 124:2241e3a39974 1411 #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
Kojto 124:2241e3a39974 1412 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
Kojto 124:2241e3a39974 1413
Kojto 124:2241e3a39974 1414 #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
Kojto 124:2241e3a39974 1415 #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
Kojto 124:2241e3a39974 1416
Kojto 124:2241e3a39974 1417 /*@} end of group CMSIS_MPU */
Kojto 124:2241e3a39974 1418 #endif
Kojto 124:2241e3a39974 1419
Kojto 124:2241e3a39974 1420
Kojto 124:2241e3a39974 1421 #if (__FPU_PRESENT == 1)
Kojto 124:2241e3a39974 1422 /** \ingroup CMSIS_core_register
Kojto 124:2241e3a39974 1423 \defgroup CMSIS_FPU Floating Point Unit (FPU)
Kojto 124:2241e3a39974 1424 \brief Type definitions for the Floating Point Unit (FPU)
Kojto 124:2241e3a39974 1425 @{
Kojto 124:2241e3a39974 1426 */
Kojto 124:2241e3a39974 1427
Kojto 124:2241e3a39974 1428 /** \brief Structure type to access the Floating Point Unit (FPU).
Kojto 124:2241e3a39974 1429 */
Kojto 124:2241e3a39974 1430 typedef struct
Kojto 124:2241e3a39974 1431 {
Kojto 124:2241e3a39974 1432 uint32_t RESERVED0[1];
Kojto 124:2241e3a39974 1433 __IO uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
Kojto 124:2241e3a39974 1434 __IO uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
Kojto 124:2241e3a39974 1435 __IO uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
Kojto 124:2241e3a39974 1436 __I uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */
Kojto 124:2241e3a39974 1437 __I uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */
Kojto 124:2241e3a39974 1438 __I uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */
Kojto 124:2241e3a39974 1439 } FPU_Type;
Kojto 124:2241e3a39974 1440
Kojto 124:2241e3a39974 1441 /* Floating-Point Context Control Register */
Kojto 124:2241e3a39974 1442 #define FPU_FPCCR_ASPEN_Pos 31 /*!< FPCCR: ASPEN bit Position */
Kojto 124:2241e3a39974 1443 #define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
Kojto 124:2241e3a39974 1444
Kojto 124:2241e3a39974 1445 #define FPU_FPCCR_LSPEN_Pos 30 /*!< FPCCR: LSPEN Position */
Kojto 124:2241e3a39974 1446 #define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
Kojto 124:2241e3a39974 1447
Kojto 124:2241e3a39974 1448 #define FPU_FPCCR_MONRDY_Pos 8 /*!< FPCCR: MONRDY Position */
Kojto 124:2241e3a39974 1449 #define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
Kojto 124:2241e3a39974 1450
Kojto 124:2241e3a39974 1451 #define FPU_FPCCR_BFRDY_Pos 6 /*!< FPCCR: BFRDY Position */
Kojto 124:2241e3a39974 1452 #define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
Kojto 124:2241e3a39974 1453
Kojto 124:2241e3a39974 1454 #define FPU_FPCCR_MMRDY_Pos 5 /*!< FPCCR: MMRDY Position */
Kojto 124:2241e3a39974 1455 #define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
Kojto 124:2241e3a39974 1456
Kojto 124:2241e3a39974 1457 #define FPU_FPCCR_HFRDY_Pos 4 /*!< FPCCR: HFRDY Position */
Kojto 124:2241e3a39974 1458 #define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
Kojto 124:2241e3a39974 1459
Kojto 124:2241e3a39974 1460 #define FPU_FPCCR_THREAD_Pos 3 /*!< FPCCR: processor mode bit Position */
Kojto 124:2241e3a39974 1461 #define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
Kojto 124:2241e3a39974 1462
Kojto 124:2241e3a39974 1463 #define FPU_FPCCR_USER_Pos 1 /*!< FPCCR: privilege level bit Position */
Kojto 124:2241e3a39974 1464 #define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
Kojto 124:2241e3a39974 1465
Kojto 124:2241e3a39974 1466 #define FPU_FPCCR_LSPACT_Pos 0 /*!< FPCCR: Lazy state preservation active bit Position */
Kojto 124:2241e3a39974 1467 #define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */
Kojto 124:2241e3a39974 1468
Kojto 124:2241e3a39974 1469 /* Floating-Point Context Address Register */
Kojto 124:2241e3a39974 1470 #define FPU_FPCAR_ADDRESS_Pos 3 /*!< FPCAR: ADDRESS bit Position */
Kojto 124:2241e3a39974 1471 #define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
Kojto 124:2241e3a39974 1472
Kojto 124:2241e3a39974 1473 /* Floating-Point Default Status Control Register */
Kojto 124:2241e3a39974 1474 #define FPU_FPDSCR_AHP_Pos 26 /*!< FPDSCR: AHP bit Position */
Kojto 124:2241e3a39974 1475 #define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
Kojto 124:2241e3a39974 1476
Kojto 124:2241e3a39974 1477 #define FPU_FPDSCR_DN_Pos 25 /*!< FPDSCR: DN bit Position */
Kojto 124:2241e3a39974 1478 #define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
Kojto 124:2241e3a39974 1479
Kojto 124:2241e3a39974 1480 #define FPU_FPDSCR_FZ_Pos 24 /*!< FPDSCR: FZ bit Position */
Kojto 124:2241e3a39974 1481 #define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
Kojto 124:2241e3a39974 1482
Kojto 124:2241e3a39974 1483 #define FPU_FPDSCR_RMode_Pos 22 /*!< FPDSCR: RMode bit Position */
Kojto 124:2241e3a39974 1484 #define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
Kojto 124:2241e3a39974 1485
Kojto 124:2241e3a39974 1486 /* Media and FP Feature Register 0 */
Kojto 124:2241e3a39974 1487 #define FPU_MVFR0_FP_rounding_modes_Pos 28 /*!< MVFR0: FP rounding modes bits Position */
Kojto 124:2241e3a39974 1488 #define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */
Kojto 124:2241e3a39974 1489
Kojto 124:2241e3a39974 1490 #define FPU_MVFR0_Short_vectors_Pos 24 /*!< MVFR0: Short vectors bits Position */
Kojto 124:2241e3a39974 1491 #define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */
Kojto 124:2241e3a39974 1492
Kojto 124:2241e3a39974 1493 #define FPU_MVFR0_Square_root_Pos 20 /*!< MVFR0: Square root bits Position */
Kojto 124:2241e3a39974 1494 #define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */
Kojto 124:2241e3a39974 1495
Kojto 124:2241e3a39974 1496 #define FPU_MVFR0_Divide_Pos 16 /*!< MVFR0: Divide bits Position */
Kojto 124:2241e3a39974 1497 #define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */
Kojto 124:2241e3a39974 1498
Kojto 124:2241e3a39974 1499 #define FPU_MVFR0_FP_excep_trapping_Pos 12 /*!< MVFR0: FP exception trapping bits Position */
Kojto 124:2241e3a39974 1500 #define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */
Kojto 124:2241e3a39974 1501
Kojto 124:2241e3a39974 1502 #define FPU_MVFR0_Double_precision_Pos 8 /*!< MVFR0: Double-precision bits Position */
Kojto 124:2241e3a39974 1503 #define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */
Kojto 124:2241e3a39974 1504
Kojto 124:2241e3a39974 1505 #define FPU_MVFR0_Single_precision_Pos 4 /*!< MVFR0: Single-precision bits Position */
Kojto 124:2241e3a39974 1506 #define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */
Kojto 124:2241e3a39974 1507
Kojto 124:2241e3a39974 1508 #define FPU_MVFR0_A_SIMD_registers_Pos 0 /*!< MVFR0: A_SIMD registers bits Position */
Kojto 124:2241e3a39974 1509 #define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */
Kojto 124:2241e3a39974 1510
Kojto 124:2241e3a39974 1511 /* Media and FP Feature Register 1 */
Kojto 124:2241e3a39974 1512 #define FPU_MVFR1_FP_fused_MAC_Pos 28 /*!< MVFR1: FP fused MAC bits Position */
Kojto 124:2241e3a39974 1513 #define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */
Kojto 124:2241e3a39974 1514
Kojto 124:2241e3a39974 1515 #define FPU_MVFR1_FP_HPFP_Pos 24 /*!< MVFR1: FP HPFP bits Position */
Kojto 124:2241e3a39974 1516 #define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */
Kojto 124:2241e3a39974 1517
Kojto 124:2241e3a39974 1518 #define FPU_MVFR1_D_NaN_mode_Pos 4 /*!< MVFR1: D_NaN mode bits Position */
Kojto 124:2241e3a39974 1519 #define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */
Kojto 124:2241e3a39974 1520
Kojto 124:2241e3a39974 1521 #define FPU_MVFR1_FtZ_mode_Pos 0 /*!< MVFR1: FtZ mode bits Position */
Kojto 124:2241e3a39974 1522 #define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */
Kojto 124:2241e3a39974 1523
Kojto 124:2241e3a39974 1524 /* Media and FP Feature Register 2 */
Kojto 124:2241e3a39974 1525
Kojto 124:2241e3a39974 1526 /*@} end of group CMSIS_FPU */
Kojto 124:2241e3a39974 1527 #endif
Kojto 124:2241e3a39974 1528
Kojto 124:2241e3a39974 1529
Kojto 124:2241e3a39974 1530 /** \ingroup CMSIS_core_register
Kojto 124:2241e3a39974 1531 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
Kojto 124:2241e3a39974 1532 \brief Type definitions for the Core Debug Registers
Kojto 124:2241e3a39974 1533 @{
Kojto 124:2241e3a39974 1534 */
Kojto 124:2241e3a39974 1535
Kojto 124:2241e3a39974 1536 /** \brief Structure type to access the Core Debug Register (CoreDebug).
Kojto 124:2241e3a39974 1537 */
Kojto 124:2241e3a39974 1538 typedef struct
Kojto 124:2241e3a39974 1539 {
Kojto 124:2241e3a39974 1540 __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
Kojto 124:2241e3a39974 1541 __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
Kojto 124:2241e3a39974 1542 __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
Kojto 124:2241e3a39974 1543 __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
Kojto 124:2241e3a39974 1544 } CoreDebug_Type;
Kojto 124:2241e3a39974 1545
Kojto 124:2241e3a39974 1546 /* Debug Halting Control and Status Register */
Kojto 124:2241e3a39974 1547 #define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */
Kojto 124:2241e3a39974 1548 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
Kojto 124:2241e3a39974 1549
Kojto 124:2241e3a39974 1550 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */
Kojto 124:2241e3a39974 1551 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
Kojto 124:2241e3a39974 1552
Kojto 124:2241e3a39974 1553 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
Kojto 124:2241e3a39974 1554 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
Kojto 124:2241e3a39974 1555
Kojto 124:2241e3a39974 1556 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */
Kojto 124:2241e3a39974 1557 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
Kojto 124:2241e3a39974 1558
Kojto 124:2241e3a39974 1559 #define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */
Kojto 124:2241e3a39974 1560 #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
Kojto 124:2241e3a39974 1561
Kojto 124:2241e3a39974 1562 #define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */
Kojto 124:2241e3a39974 1563 #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
Kojto 124:2241e3a39974 1564
Kojto 124:2241e3a39974 1565 #define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */
Kojto 124:2241e3a39974 1566 #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
Kojto 124:2241e3a39974 1567
Kojto 124:2241e3a39974 1568 #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
Kojto 124:2241e3a39974 1569 #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
Kojto 124:2241e3a39974 1570
Kojto 124:2241e3a39974 1571 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */
Kojto 124:2241e3a39974 1572 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
Kojto 124:2241e3a39974 1573
Kojto 124:2241e3a39974 1574 #define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */
Kojto 124:2241e3a39974 1575 #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
Kojto 124:2241e3a39974 1576
Kojto 124:2241e3a39974 1577 #define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */
Kojto 124:2241e3a39974 1578 #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
Kojto 124:2241e3a39974 1579
Kojto 124:2241e3a39974 1580 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */
Kojto 124:2241e3a39974 1581 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
Kojto 124:2241e3a39974 1582
Kojto 124:2241e3a39974 1583 /* Debug Core Register Selector Register */
Kojto 124:2241e3a39974 1584 #define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */
Kojto 124:2241e3a39974 1585 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
Kojto 124:2241e3a39974 1586
Kojto 124:2241e3a39974 1587 #define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */
Kojto 124:2241e3a39974 1588 #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
Kojto 124:2241e3a39974 1589
Kojto 124:2241e3a39974 1590 /* Debug Exception and Monitor Control Register */
Kojto 124:2241e3a39974 1591 #define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */
Kojto 124:2241e3a39974 1592 #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
Kojto 124:2241e3a39974 1593
Kojto 124:2241e3a39974 1594 #define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */
Kojto 124:2241e3a39974 1595 #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
Kojto 124:2241e3a39974 1596
Kojto 124:2241e3a39974 1597 #define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */
Kojto 124:2241e3a39974 1598 #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
Kojto 124:2241e3a39974 1599
Kojto 124:2241e3a39974 1600 #define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */
Kojto 124:2241e3a39974 1601 #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
Kojto 124:2241e3a39974 1602
Kojto 124:2241e3a39974 1603 #define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */
Kojto 124:2241e3a39974 1604 #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
Kojto 124:2241e3a39974 1605
Kojto 124:2241e3a39974 1606 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */
Kojto 124:2241e3a39974 1607 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
Kojto 124:2241e3a39974 1608
Kojto 124:2241e3a39974 1609 #define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */
Kojto 124:2241e3a39974 1610 #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
Kojto 124:2241e3a39974 1611
Kojto 124:2241e3a39974 1612 #define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */
Kojto 124:2241e3a39974 1613 #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
Kojto 124:2241e3a39974 1614
Kojto 124:2241e3a39974 1615 #define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */
Kojto 124:2241e3a39974 1616 #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
Kojto 124:2241e3a39974 1617
Kojto 124:2241e3a39974 1618 #define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */
Kojto 124:2241e3a39974 1619 #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
Kojto 124:2241e3a39974 1620
Kojto 124:2241e3a39974 1621 #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */
Kojto 124:2241e3a39974 1622 #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
Kojto 124:2241e3a39974 1623
Kojto 124:2241e3a39974 1624 #define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */
Kojto 124:2241e3a39974 1625 #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
Kojto 124:2241e3a39974 1626
Kojto 124:2241e3a39974 1627 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */
Kojto 124:2241e3a39974 1628 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
Kojto 124:2241e3a39974 1629
Kojto 124:2241e3a39974 1630 /*@} end of group CMSIS_CoreDebug */
Kojto 124:2241e3a39974 1631
Kojto 124:2241e3a39974 1632
Kojto 124:2241e3a39974 1633 /** \ingroup CMSIS_core_register
Kojto 124:2241e3a39974 1634 \defgroup CMSIS_core_base Core Definitions
Kojto 124:2241e3a39974 1635 \brief Definitions for base addresses, unions, and structures.
Kojto 124:2241e3a39974 1636 @{
Kojto 124:2241e3a39974 1637 */
Kojto 124:2241e3a39974 1638
Kojto 124:2241e3a39974 1639 /* Memory mapping of Cortex-M4 Hardware */
Kojto 124:2241e3a39974 1640 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
Kojto 124:2241e3a39974 1641 #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
Kojto 124:2241e3a39974 1642 #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
Kojto 124:2241e3a39974 1643 #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
Kojto 124:2241e3a39974 1644 #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
Kojto 124:2241e3a39974 1645 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
Kojto 124:2241e3a39974 1646 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
Kojto 124:2241e3a39974 1647 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
Kojto 124:2241e3a39974 1648
Kojto 124:2241e3a39974 1649 #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
Kojto 124:2241e3a39974 1650 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
Kojto 124:2241e3a39974 1651 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
Kojto 124:2241e3a39974 1652 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
Kojto 124:2241e3a39974 1653 #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
Kojto 124:2241e3a39974 1654 #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
Kojto 124:2241e3a39974 1655 #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
Kojto 124:2241e3a39974 1656 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
Kojto 124:2241e3a39974 1657
Kojto 124:2241e3a39974 1658 #if (__MPU_PRESENT == 1)
Kojto 124:2241e3a39974 1659 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
Kojto 124:2241e3a39974 1660 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
Kojto 124:2241e3a39974 1661 #endif
Kojto 124:2241e3a39974 1662
Kojto 124:2241e3a39974 1663 #if (__FPU_PRESENT == 1)
Kojto 124:2241e3a39974 1664 #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
Kojto 124:2241e3a39974 1665 #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
Kojto 124:2241e3a39974 1666 #endif
Kojto 124:2241e3a39974 1667
Kojto 124:2241e3a39974 1668 /*@} */
Kojto 124:2241e3a39974 1669
Kojto 124:2241e3a39974 1670
Kojto 124:2241e3a39974 1671
Kojto 124:2241e3a39974 1672 /*******************************************************************************
Kojto 124:2241e3a39974 1673 * Hardware Abstraction Layer
Kojto 124:2241e3a39974 1674 Core Function Interface contains:
Kojto 124:2241e3a39974 1675 - Core NVIC Functions
Kojto 124:2241e3a39974 1676 - Core SysTick Functions
Kojto 124:2241e3a39974 1677 - Core Debug Functions
Kojto 124:2241e3a39974 1678 - Core Register Access Functions
Kojto 124:2241e3a39974 1679 ******************************************************************************/
Kojto 124:2241e3a39974 1680 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
Kojto 124:2241e3a39974 1681 */
Kojto 124:2241e3a39974 1682
Kojto 124:2241e3a39974 1683
Kojto 124:2241e3a39974 1684
Kojto 124:2241e3a39974 1685 /* ########################## NVIC functions #################################### */
Kojto 124:2241e3a39974 1686 /** \ingroup CMSIS_Core_FunctionInterface
Kojto 124:2241e3a39974 1687 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
Kojto 124:2241e3a39974 1688 \brief Functions that manage interrupts and exceptions via the NVIC.
Kojto 124:2241e3a39974 1689 @{
Kojto 124:2241e3a39974 1690 */
Kojto 124:2241e3a39974 1691
Kojto 124:2241e3a39974 1692 /** \brief Set Priority Grouping
Kojto 124:2241e3a39974 1693
Kojto 124:2241e3a39974 1694 The function sets the priority grouping field using the required unlock sequence.
Kojto 124:2241e3a39974 1695 The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
Kojto 124:2241e3a39974 1696 Only values from 0..7 are used.
Kojto 124:2241e3a39974 1697 In case of a conflict between priority grouping and available
Kojto 124:2241e3a39974 1698 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
Kojto 124:2241e3a39974 1699
Kojto 124:2241e3a39974 1700 \param [in] PriorityGroup Priority grouping field.
Kojto 124:2241e3a39974 1701 */
Kojto 124:2241e3a39974 1702 __STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
Kojto 124:2241e3a39974 1703 {
Kojto 124:2241e3a39974 1704 uint32_t reg_value;
Kojto 124:2241e3a39974 1705 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
Kojto 124:2241e3a39974 1706
Kojto 124:2241e3a39974 1707 reg_value = SCB->AIRCR; /* read old register configuration */
Kojto 124:2241e3a39974 1708 reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
Kojto 124:2241e3a39974 1709 reg_value = (reg_value |
Kojto 124:2241e3a39974 1710 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
Kojto 124:2241e3a39974 1711 (PriorityGroupTmp << 8) ); /* Insert write key and priorty group */
Kojto 124:2241e3a39974 1712 SCB->AIRCR = reg_value;
Kojto 124:2241e3a39974 1713 }
Kojto 124:2241e3a39974 1714
Kojto 124:2241e3a39974 1715
Kojto 124:2241e3a39974 1716 /** \brief Get Priority Grouping
Kojto 124:2241e3a39974 1717
Kojto 124:2241e3a39974 1718 The function reads the priority grouping field from the NVIC Interrupt Controller.
Kojto 124:2241e3a39974 1719
Kojto 124:2241e3a39974 1720 \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
Kojto 124:2241e3a39974 1721 */
Kojto 124:2241e3a39974 1722 __STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
Kojto 124:2241e3a39974 1723 {
Kojto 124:2241e3a39974 1724 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
Kojto 124:2241e3a39974 1725 }
Kojto 124:2241e3a39974 1726
Kojto 124:2241e3a39974 1727
Kojto 124:2241e3a39974 1728 /** \brief Enable External Interrupt
Kojto 124:2241e3a39974 1729
Kojto 124:2241e3a39974 1730 The function enables a device-specific interrupt in the NVIC interrupt controller.
Kojto 124:2241e3a39974 1731
Kojto 124:2241e3a39974 1732 \param [in] IRQn External interrupt number. Value cannot be negative.
Kojto 124:2241e3a39974 1733 */
Kojto 124:2241e3a39974 1734 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
Kojto 124:2241e3a39974 1735 {
Kojto 124:2241e3a39974 1736 NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
Kojto 124:2241e3a39974 1737 }
Kojto 124:2241e3a39974 1738
Kojto 124:2241e3a39974 1739
Kojto 124:2241e3a39974 1740 /** \brief Disable External Interrupt
Kojto 124:2241e3a39974 1741
Kojto 124:2241e3a39974 1742 The function disables a device-specific interrupt in the NVIC interrupt controller.
Kojto 124:2241e3a39974 1743
Kojto 124:2241e3a39974 1744 \param [in] IRQn External interrupt number. Value cannot be negative.
Kojto 124:2241e3a39974 1745 */
Kojto 124:2241e3a39974 1746 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
Kojto 124:2241e3a39974 1747 {
Kojto 124:2241e3a39974 1748 NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
Kojto 124:2241e3a39974 1749 }
Kojto 124:2241e3a39974 1750
Kojto 124:2241e3a39974 1751
Kojto 124:2241e3a39974 1752 /** \brief Get Pending Interrupt
Kojto 124:2241e3a39974 1753
Kojto 124:2241e3a39974 1754 The function reads the pending register in the NVIC and returns the pending bit
Kojto 124:2241e3a39974 1755 for the specified interrupt.
Kojto 124:2241e3a39974 1756
Kojto 124:2241e3a39974 1757 \param [in] IRQn Interrupt number.
Kojto 124:2241e3a39974 1758
Kojto 124:2241e3a39974 1759 \return 0 Interrupt status is not pending.
Kojto 124:2241e3a39974 1760 \return 1 Interrupt status is pending.
Kojto 124:2241e3a39974 1761 */
Kojto 124:2241e3a39974 1762 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
Kojto 124:2241e3a39974 1763 {
Kojto 124:2241e3a39974 1764 return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
Kojto 124:2241e3a39974 1765 }
Kojto 124:2241e3a39974 1766
Kojto 124:2241e3a39974 1767
Kojto 124:2241e3a39974 1768 /** \brief Set Pending Interrupt
Kojto 124:2241e3a39974 1769
Kojto 124:2241e3a39974 1770 The function sets the pending bit of an external interrupt.
Kojto 124:2241e3a39974 1771
Kojto 124:2241e3a39974 1772 \param [in] IRQn Interrupt number. Value cannot be negative.
Kojto 124:2241e3a39974 1773 */
Kojto 124:2241e3a39974 1774 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
Kojto 124:2241e3a39974 1775 {
Kojto 124:2241e3a39974 1776 NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
Kojto 124:2241e3a39974 1777 }
Kojto 124:2241e3a39974 1778
Kojto 124:2241e3a39974 1779
Kojto 124:2241e3a39974 1780 /** \brief Clear Pending Interrupt
Kojto 124:2241e3a39974 1781
Kojto 124:2241e3a39974 1782 The function clears the pending bit of an external interrupt.
Kojto 124:2241e3a39974 1783
Kojto 124:2241e3a39974 1784 \param [in] IRQn External interrupt number. Value cannot be negative.
Kojto 124:2241e3a39974 1785 */
Kojto 124:2241e3a39974 1786 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
Kojto 124:2241e3a39974 1787 {
Kojto 124:2241e3a39974 1788 NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
Kojto 124:2241e3a39974 1789 }
Kojto 124:2241e3a39974 1790
Kojto 124:2241e3a39974 1791
Kojto 124:2241e3a39974 1792 /** \brief Get Active Interrupt
Kojto 124:2241e3a39974 1793
Kojto 124:2241e3a39974 1794 The function reads the active register in NVIC and returns the active bit.
Kojto 124:2241e3a39974 1795
Kojto 124:2241e3a39974 1796 \param [in] IRQn Interrupt number.
Kojto 124:2241e3a39974 1797
Kojto 124:2241e3a39974 1798 \return 0 Interrupt status is not active.
Kojto 124:2241e3a39974 1799 \return 1 Interrupt status is active.
Kojto 124:2241e3a39974 1800 */
Kojto 124:2241e3a39974 1801 __STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
Kojto 124:2241e3a39974 1802 {
Kojto 124:2241e3a39974 1803 return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
Kojto 124:2241e3a39974 1804 }
Kojto 124:2241e3a39974 1805
Kojto 124:2241e3a39974 1806
Kojto 124:2241e3a39974 1807 /** \brief Set Interrupt Priority
Kojto 124:2241e3a39974 1808
Kojto 124:2241e3a39974 1809 The function sets the priority of an interrupt.
Kojto 124:2241e3a39974 1810
Kojto 124:2241e3a39974 1811 \note The priority cannot be set for every core interrupt.
Kojto 124:2241e3a39974 1812
Kojto 124:2241e3a39974 1813 \param [in] IRQn Interrupt number.
Kojto 124:2241e3a39974 1814 \param [in] priority Priority to set.
Kojto 124:2241e3a39974 1815 */
Kojto 124:2241e3a39974 1816 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
Kojto 124:2241e3a39974 1817 {
Kojto 124:2241e3a39974 1818 if((int32_t)IRQn < 0) {
Kojto 124:2241e3a39974 1819 SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
Kojto 124:2241e3a39974 1820 }
Kojto 124:2241e3a39974 1821 else {
Kojto 124:2241e3a39974 1822 NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
Kojto 124:2241e3a39974 1823 }
Kojto 124:2241e3a39974 1824 }
Kojto 124:2241e3a39974 1825
Kojto 124:2241e3a39974 1826
Kojto 124:2241e3a39974 1827 /** \brief Get Interrupt Priority
Kojto 124:2241e3a39974 1828
Kojto 124:2241e3a39974 1829 The function reads the priority of an interrupt. The interrupt
Kojto 124:2241e3a39974 1830 number can be positive to specify an external (device specific)
Kojto 124:2241e3a39974 1831 interrupt, or negative to specify an internal (core) interrupt.
Kojto 124:2241e3a39974 1832
Kojto 124:2241e3a39974 1833
Kojto 124:2241e3a39974 1834 \param [in] IRQn Interrupt number.
Kojto 124:2241e3a39974 1835 \return Interrupt Priority. Value is aligned automatically to the implemented
Kojto 124:2241e3a39974 1836 priority bits of the microcontroller.
Kojto 124:2241e3a39974 1837 */
Kojto 124:2241e3a39974 1838 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
Kojto 124:2241e3a39974 1839 {
Kojto 124:2241e3a39974 1840
Kojto 124:2241e3a39974 1841 if((int32_t)IRQn < 0) {
Kojto 124:2241e3a39974 1842 return(((uint32_t)SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8 - __NVIC_PRIO_BITS)));
Kojto 124:2241e3a39974 1843 }
Kojto 124:2241e3a39974 1844 else {
Kojto 124:2241e3a39974 1845 return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8 - __NVIC_PRIO_BITS)));
Kojto 124:2241e3a39974 1846 }
Kojto 124:2241e3a39974 1847 }
Kojto 124:2241e3a39974 1848
Kojto 124:2241e3a39974 1849
Kojto 124:2241e3a39974 1850 /** \brief Encode Priority
Kojto 124:2241e3a39974 1851
Kojto 124:2241e3a39974 1852 The function encodes the priority for an interrupt with the given priority group,
Kojto 124:2241e3a39974 1853 preemptive priority value, and subpriority value.
Kojto 124:2241e3a39974 1854 In case of a conflict between priority grouping and available
Kojto 124:2241e3a39974 1855 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
Kojto 124:2241e3a39974 1856
Kojto 124:2241e3a39974 1857 \param [in] PriorityGroup Used priority group.
Kojto 124:2241e3a39974 1858 \param [in] PreemptPriority Preemptive priority value (starting from 0).
Kojto 124:2241e3a39974 1859 \param [in] SubPriority Subpriority value (starting from 0).
Kojto 124:2241e3a39974 1860 \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
Kojto 124:2241e3a39974 1861 */
Kojto 124:2241e3a39974 1862 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
Kojto 124:2241e3a39974 1863 {
Kojto 124:2241e3a39974 1864 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
Kojto 124:2241e3a39974 1865 uint32_t PreemptPriorityBits;
Kojto 124:2241e3a39974 1866 uint32_t SubPriorityBits;
Kojto 124:2241e3a39974 1867
Kojto 124:2241e3a39974 1868 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
Kojto 124:2241e3a39974 1869 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
Kojto 124:2241e3a39974 1870
Kojto 124:2241e3a39974 1871 return (
Kojto 124:2241e3a39974 1872 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
Kojto 124:2241e3a39974 1873 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
Kojto 124:2241e3a39974 1874 );
Kojto 124:2241e3a39974 1875 }
Kojto 124:2241e3a39974 1876
Kojto 124:2241e3a39974 1877
Kojto 124:2241e3a39974 1878 /** \brief Decode Priority
Kojto 124:2241e3a39974 1879
Kojto 124:2241e3a39974 1880 The function decodes an interrupt priority value with a given priority group to
Kojto 124:2241e3a39974 1881 preemptive priority value and subpriority value.
Kojto 124:2241e3a39974 1882 In case of a conflict between priority grouping and available
Kojto 124:2241e3a39974 1883 priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
Kojto 124:2241e3a39974 1884
Kojto 124:2241e3a39974 1885 \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
Kojto 124:2241e3a39974 1886 \param [in] PriorityGroup Used priority group.
Kojto 124:2241e3a39974 1887 \param [out] pPreemptPriority Preemptive priority value (starting from 0).
Kojto 124:2241e3a39974 1888 \param [out] pSubPriority Subpriority value (starting from 0).
Kojto 124:2241e3a39974 1889 */
Kojto 124:2241e3a39974 1890 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
Kojto 124:2241e3a39974 1891 {
Kojto 124:2241e3a39974 1892 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
Kojto 124:2241e3a39974 1893 uint32_t PreemptPriorityBits;
Kojto 124:2241e3a39974 1894 uint32_t SubPriorityBits;
Kojto 124:2241e3a39974 1895
Kojto 124:2241e3a39974 1896 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
Kojto 124:2241e3a39974 1897 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
Kojto 124:2241e3a39974 1898
Kojto 124:2241e3a39974 1899 *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
Kojto 124:2241e3a39974 1900 *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
Kojto 124:2241e3a39974 1901 }
Kojto 124:2241e3a39974 1902
Kojto 124:2241e3a39974 1903
Kojto 124:2241e3a39974 1904 /** \brief System Reset
Kojto 124:2241e3a39974 1905
Kojto 124:2241e3a39974 1906 The function initiates a system reset request to reset the MCU.
Kojto 124:2241e3a39974 1907 */
Kojto 124:2241e3a39974 1908 __STATIC_INLINE void NVIC_SystemReset(void)
Kojto 124:2241e3a39974 1909 {
Kojto 124:2241e3a39974 1910 __DSB(); /* Ensure all outstanding memory accesses included
Kojto 124:2241e3a39974 1911 buffered write are completed before reset */
Kojto 124:2241e3a39974 1912 SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
Kojto 124:2241e3a39974 1913 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
Kojto 124:2241e3a39974 1914 SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
Kojto 124:2241e3a39974 1915 __DSB(); /* Ensure completion of memory access */
Kojto 124:2241e3a39974 1916 while(1) { __NOP(); } /* wait until reset */
Kojto 124:2241e3a39974 1917 }
Kojto 124:2241e3a39974 1918
Kojto 124:2241e3a39974 1919 /*@} end of CMSIS_Core_NVICFunctions */
Kojto 124:2241e3a39974 1920
Kojto 124:2241e3a39974 1921
Kojto 124:2241e3a39974 1922 /* ########################## FPU functions #################################### */
Kojto 124:2241e3a39974 1923 /** \ingroup CMSIS_Core_FunctionInterface
Kojto 124:2241e3a39974 1924 \defgroup CMSIS_Core_FpuFunctions FPU Functions
Kojto 124:2241e3a39974 1925 \brief Function that provides FPU type.
Kojto 124:2241e3a39974 1926 @{
Kojto 124:2241e3a39974 1927 */
Kojto 124:2241e3a39974 1928
Kojto 124:2241e3a39974 1929 /**
Kojto 124:2241e3a39974 1930 \fn uint32_t SCB_GetFPUType(void)
Kojto 124:2241e3a39974 1931 \brief get FPU type
Kojto 124:2241e3a39974 1932 \returns
Kojto 124:2241e3a39974 1933 - \b 0: No FPU
Kojto 124:2241e3a39974 1934 - \b 1: Single precision FPU
Kojto 124:2241e3a39974 1935 - \b 2: Double + Single precision FPU
Kojto 124:2241e3a39974 1936 */
Kojto 124:2241e3a39974 1937 __STATIC_INLINE uint32_t SCB_GetFPUType(void)
Kojto 124:2241e3a39974 1938 {
Kojto 124:2241e3a39974 1939 uint32_t mvfr0;
Kojto 124:2241e3a39974 1940
Kojto 124:2241e3a39974 1941 mvfr0 = SCB->MVFR0;
Kojto 124:2241e3a39974 1942 if ((mvfr0 & 0x00000FF0UL) == 0x220UL) {
Kojto 124:2241e3a39974 1943 return 2UL; // Double + Single precision FPU
Kojto 124:2241e3a39974 1944 } else if ((mvfr0 & 0x00000FF0UL) == 0x020UL) {
Kojto 124:2241e3a39974 1945 return 1UL; // Single precision FPU
Kojto 124:2241e3a39974 1946 } else {
Kojto 124:2241e3a39974 1947 return 0UL; // No FPU
Kojto 124:2241e3a39974 1948 }
Kojto 124:2241e3a39974 1949 }
Kojto 124:2241e3a39974 1950
Kojto 124:2241e3a39974 1951
Kojto 124:2241e3a39974 1952 /*@} end of CMSIS_Core_FpuFunctions */
Kojto 124:2241e3a39974 1953
Kojto 124:2241e3a39974 1954
Kojto 124:2241e3a39974 1955
Kojto 124:2241e3a39974 1956 /* ########################## Cache functions #################################### */
Kojto 124:2241e3a39974 1957 /** \ingroup CMSIS_Core_FunctionInterface
Kojto 124:2241e3a39974 1958 \defgroup CMSIS_Core_CacheFunctions Cache Functions
Kojto 124:2241e3a39974 1959 \brief Functions that configure Instruction and Data cache.
Kojto 124:2241e3a39974 1960 @{
Kojto 124:2241e3a39974 1961 */
Kojto 124:2241e3a39974 1962
Kojto 124:2241e3a39974 1963 /* Cache Size ID Register Macros */
Kojto 124:2241e3a39974 1964 #define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos)
Kojto 124:2241e3a39974 1965 #define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos )
Kojto 124:2241e3a39974 1966 #define CCSIDR_LSSHIFT(x) (((x) & SCB_CCSIDR_LINESIZE_Msk ) /*>> SCB_CCSIDR_LINESIZE_Pos*/ )
Kojto 124:2241e3a39974 1967
Kojto 124:2241e3a39974 1968
Kojto 124:2241e3a39974 1969 /** \brief Enable I-Cache
Kojto 124:2241e3a39974 1970
Kojto 124:2241e3a39974 1971 The function turns on I-Cache
Kojto 124:2241e3a39974 1972 */
Kojto 124:2241e3a39974 1973 __STATIC_INLINE void SCB_EnableICache (void)
Kojto 124:2241e3a39974 1974 {
Kojto 124:2241e3a39974 1975 #if (__ICACHE_PRESENT == 1)
Kojto 124:2241e3a39974 1976 __DSB();
Kojto 124:2241e3a39974 1977 __ISB();
Kojto 124:2241e3a39974 1978 SCB->ICIALLU = 0UL; // invalidate I-Cache
Kojto 124:2241e3a39974 1979 SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; // enable I-Cache
Kojto 124:2241e3a39974 1980 __DSB();
Kojto 124:2241e3a39974 1981 __ISB();
Kojto 124:2241e3a39974 1982 #endif
Kojto 124:2241e3a39974 1983 }
Kojto 124:2241e3a39974 1984
Kojto 124:2241e3a39974 1985
Kojto 124:2241e3a39974 1986 /** \brief Disable I-Cache
Kojto 124:2241e3a39974 1987
Kojto 124:2241e3a39974 1988 The function turns off I-Cache
Kojto 124:2241e3a39974 1989 */
Kojto 124:2241e3a39974 1990 __STATIC_INLINE void SCB_DisableICache (void)
Kojto 124:2241e3a39974 1991 {
Kojto 124:2241e3a39974 1992 #if (__ICACHE_PRESENT == 1)
Kojto 124:2241e3a39974 1993 __DSB();
Kojto 124:2241e3a39974 1994 __ISB();
Kojto 124:2241e3a39974 1995 SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; // disable I-Cache
Kojto 124:2241e3a39974 1996 SCB->ICIALLU = 0UL; // invalidate I-Cache
Kojto 124:2241e3a39974 1997 __DSB();
Kojto 124:2241e3a39974 1998 __ISB();
Kojto 124:2241e3a39974 1999 #endif
Kojto 124:2241e3a39974 2000 }
Kojto 124:2241e3a39974 2001
Kojto 124:2241e3a39974 2002
Kojto 124:2241e3a39974 2003 /** \brief Invalidate I-Cache
Kojto 124:2241e3a39974 2004
Kojto 124:2241e3a39974 2005 The function invalidates I-Cache
Kojto 124:2241e3a39974 2006 */
Kojto 124:2241e3a39974 2007 __STATIC_INLINE void SCB_InvalidateICache (void)
Kojto 124:2241e3a39974 2008 {
Kojto 124:2241e3a39974 2009 #if (__ICACHE_PRESENT == 1)
Kojto 124:2241e3a39974 2010 __DSB();
Kojto 124:2241e3a39974 2011 __ISB();
Kojto 124:2241e3a39974 2012 SCB->ICIALLU = 0UL;
Kojto 124:2241e3a39974 2013 __DSB();
Kojto 124:2241e3a39974 2014 __ISB();
Kojto 124:2241e3a39974 2015 #endif
Kojto 124:2241e3a39974 2016 }
Kojto 124:2241e3a39974 2017
Kojto 124:2241e3a39974 2018
Kojto 124:2241e3a39974 2019 /** \brief Enable D-Cache
Kojto 124:2241e3a39974 2020
Kojto 124:2241e3a39974 2021 The function turns on D-Cache
Kojto 124:2241e3a39974 2022 */
Kojto 124:2241e3a39974 2023 __STATIC_INLINE void SCB_EnableDCache (void)
Kojto 124:2241e3a39974 2024 {
Kojto 124:2241e3a39974 2025 #if (__DCACHE_PRESENT == 1)
Kojto 124:2241e3a39974 2026 uint32_t ccsidr, sshift, wshift, sw;
Kojto 124:2241e3a39974 2027 uint32_t sets, ways;
Kojto 124:2241e3a39974 2028
Kojto 124:2241e3a39974 2029 SCB->CSSELR = (0UL << 1) | 0UL; // Level 1 data cache
Kojto 124:2241e3a39974 2030 ccsidr = SCB->CCSIDR;
Kojto 124:2241e3a39974 2031 sets = (uint32_t)(CCSIDR_SETS(ccsidr));
Kojto 124:2241e3a39974 2032 sshift = (uint32_t)(CCSIDR_LSSHIFT(ccsidr) + 4UL);
Kojto 124:2241e3a39974 2033 ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
Kojto 124:2241e3a39974 2034 wshift = (uint32_t)((uint32_t)__CLZ(ways) & 0x1FUL);
Kojto 124:2241e3a39974 2035
Kojto 124:2241e3a39974 2036 __DSB();
Kojto 124:2241e3a39974 2037
Kojto 124:2241e3a39974 2038 do { // invalidate D-Cache
Kojto 124:2241e3a39974 2039 uint32_t tmpways = ways;
Kojto 124:2241e3a39974 2040 do {
Kojto 124:2241e3a39974 2041 sw = ((tmpways << wshift) | (sets << sshift));
Kojto 124:2241e3a39974 2042 SCB->DCISW = sw;
Kojto 124:2241e3a39974 2043 } while(tmpways--);
Kojto 124:2241e3a39974 2044 } while(sets--);
Kojto 124:2241e3a39974 2045 __DSB();
Kojto 124:2241e3a39974 2046
Kojto 124:2241e3a39974 2047 SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; // enable D-Cache
Kojto 124:2241e3a39974 2048
Kojto 124:2241e3a39974 2049 __DSB();
Kojto 124:2241e3a39974 2050 __ISB();
Kojto 124:2241e3a39974 2051 #endif
Kojto 124:2241e3a39974 2052 }
Kojto 124:2241e3a39974 2053
Kojto 124:2241e3a39974 2054
Kojto 124:2241e3a39974 2055 /** \brief Disable D-Cache
Kojto 124:2241e3a39974 2056
Kojto 124:2241e3a39974 2057 The function turns off D-Cache
Kojto 124:2241e3a39974 2058 */
Kojto 124:2241e3a39974 2059 __STATIC_INLINE void SCB_DisableDCache (void)
Kojto 124:2241e3a39974 2060 {
Kojto 124:2241e3a39974 2061 #if (__DCACHE_PRESENT == 1)
Kojto 124:2241e3a39974 2062 uint32_t ccsidr, sshift, wshift, sw;
Kojto 124:2241e3a39974 2063 uint32_t sets, ways;
Kojto 124:2241e3a39974 2064
Kojto 124:2241e3a39974 2065 SCB->CSSELR = (0UL << 1) | 0UL; // Level 1 data cache
Kojto 124:2241e3a39974 2066 ccsidr = SCB->CCSIDR;
Kojto 124:2241e3a39974 2067 sets = (uint32_t)(CCSIDR_SETS(ccsidr));
Kojto 124:2241e3a39974 2068 sshift = (uint32_t)(CCSIDR_LSSHIFT(ccsidr) + 4UL);
Kojto 124:2241e3a39974 2069 ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
Kojto 124:2241e3a39974 2070 wshift = (uint32_t)((uint32_t)__CLZ(ways) & 0x1FUL);
Kojto 124:2241e3a39974 2071
Kojto 124:2241e3a39974 2072 __DSB();
Kojto 124:2241e3a39974 2073
Kojto 124:2241e3a39974 2074 SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; // disable D-Cache
Kojto 124:2241e3a39974 2075
Kojto 124:2241e3a39974 2076 do { // clean & invalidate D-Cache
Kojto 124:2241e3a39974 2077 uint32_t tmpways = ways;
Kojto 124:2241e3a39974 2078 do {
Kojto 124:2241e3a39974 2079 sw = ((tmpways << wshift) | (sets << sshift));
Kojto 124:2241e3a39974 2080 SCB->DCCISW = sw;
Kojto 124:2241e3a39974 2081 } while(tmpways--);
Kojto 124:2241e3a39974 2082 } while(sets--);
Kojto 124:2241e3a39974 2083
Kojto 124:2241e3a39974 2084
Kojto 124:2241e3a39974 2085 __DSB();
Kojto 124:2241e3a39974 2086 __ISB();
Kojto 124:2241e3a39974 2087 #endif
Kojto 124:2241e3a39974 2088 }
Kojto 124:2241e3a39974 2089
Kojto 124:2241e3a39974 2090
Kojto 124:2241e3a39974 2091 /** \brief Invalidate D-Cache
Kojto 124:2241e3a39974 2092
Kojto 124:2241e3a39974 2093 The function invalidates D-Cache
Kojto 124:2241e3a39974 2094 */
Kojto 124:2241e3a39974 2095 __STATIC_INLINE void SCB_InvalidateDCache (void)
Kojto 124:2241e3a39974 2096 {
Kojto 124:2241e3a39974 2097 #if (__DCACHE_PRESENT == 1)
Kojto 124:2241e3a39974 2098 uint32_t ccsidr, sshift, wshift, sw;
Kojto 124:2241e3a39974 2099 uint32_t sets, ways;
Kojto 124:2241e3a39974 2100
Kojto 124:2241e3a39974 2101 SCB->CSSELR = (0UL << 1) | 0UL; // Level 1 data cache
Kojto 124:2241e3a39974 2102 ccsidr = SCB->CCSIDR;
Kojto 124:2241e3a39974 2103 sets = (uint32_t)(CCSIDR_SETS(ccsidr));
Kojto 124:2241e3a39974 2104 sshift = (uint32_t)(CCSIDR_LSSHIFT(ccsidr) + 4UL);
Kojto 124:2241e3a39974 2105 ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
Kojto 124:2241e3a39974 2106 wshift = (uint32_t)((uint32_t)__CLZ(ways) & 0x1FUL);
Kojto 124:2241e3a39974 2107
Kojto 124:2241e3a39974 2108 __DSB();
Kojto 124:2241e3a39974 2109
Kojto 124:2241e3a39974 2110 do { // invalidate D-Cache
Kojto 124:2241e3a39974 2111 uint32_t tmpways = ways;
Kojto 124:2241e3a39974 2112 do {
Kojto 124:2241e3a39974 2113 sw = ((tmpways << wshift) | (sets << sshift));
Kojto 124:2241e3a39974 2114 SCB->DCISW = sw;
Kojto 124:2241e3a39974 2115 } while(tmpways--);
Kojto 124:2241e3a39974 2116 } while(sets--);
Kojto 124:2241e3a39974 2117
Kojto 124:2241e3a39974 2118 __DSB();
Kojto 124:2241e3a39974 2119 __ISB();
Kojto 124:2241e3a39974 2120 #endif
Kojto 124:2241e3a39974 2121 }
Kojto 124:2241e3a39974 2122
Kojto 124:2241e3a39974 2123
Kojto 124:2241e3a39974 2124 /** \brief Clean D-Cache
Kojto 124:2241e3a39974 2125
Kojto 124:2241e3a39974 2126 The function cleans D-Cache
Kojto 124:2241e3a39974 2127 */
Kojto 124:2241e3a39974 2128 __STATIC_INLINE void SCB_CleanDCache (void)
Kojto 124:2241e3a39974 2129 {
Kojto 124:2241e3a39974 2130 #if (__DCACHE_PRESENT == 1)
Kojto 124:2241e3a39974 2131 uint32_t ccsidr, sshift, wshift, sw;
Kojto 124:2241e3a39974 2132 uint32_t sets, ways;
Kojto 124:2241e3a39974 2133
Kojto 124:2241e3a39974 2134 SCB->CSSELR = (0UL << 1) | 0UL; // Level 1 data cache
Kojto 124:2241e3a39974 2135 ccsidr = SCB->CCSIDR;
Kojto 124:2241e3a39974 2136 sets = (uint32_t)(CCSIDR_SETS(ccsidr));
Kojto 124:2241e3a39974 2137 sshift = (uint32_t)(CCSIDR_LSSHIFT(ccsidr) + 4UL);
Kojto 124:2241e3a39974 2138 ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
Kojto 124:2241e3a39974 2139 wshift = (uint32_t)((uint32_t)__CLZ(ways) & 0x1FUL);
Kojto 124:2241e3a39974 2140
Kojto 124:2241e3a39974 2141 __DSB();
Kojto 124:2241e3a39974 2142
Kojto 124:2241e3a39974 2143 do { // clean D-Cache
Kojto 124:2241e3a39974 2144 uint32_t tmpways = ways;
Kojto 124:2241e3a39974 2145 do {
Kojto 124:2241e3a39974 2146 sw = ((tmpways << wshift) | (sets << sshift));
Kojto 124:2241e3a39974 2147 SCB->DCCSW = sw;
Kojto 124:2241e3a39974 2148 } while(tmpways--);
Kojto 124:2241e3a39974 2149 } while(sets--);
Kojto 124:2241e3a39974 2150
Kojto 124:2241e3a39974 2151 __DSB();
Kojto 124:2241e3a39974 2152 __ISB();
Kojto 124:2241e3a39974 2153 #endif
Kojto 124:2241e3a39974 2154 }
Kojto 124:2241e3a39974 2155
Kojto 124:2241e3a39974 2156
Kojto 124:2241e3a39974 2157 /** \brief Clean & Invalidate D-Cache
Kojto 124:2241e3a39974 2158
Kojto 124:2241e3a39974 2159 The function cleans and Invalidates D-Cache
Kojto 124:2241e3a39974 2160 */
Kojto 124:2241e3a39974 2161 __STATIC_INLINE void SCB_CleanInvalidateDCache (void)
Kojto 124:2241e3a39974 2162 {
Kojto 124:2241e3a39974 2163 #if (__DCACHE_PRESENT == 1)
Kojto 124:2241e3a39974 2164 uint32_t ccsidr, sshift, wshift, sw;
Kojto 124:2241e3a39974 2165 uint32_t sets, ways;
Kojto 124:2241e3a39974 2166
Kojto 124:2241e3a39974 2167 SCB->CSSELR = (0UL << 1) | 0UL; // Level 1 data cache
Kojto 124:2241e3a39974 2168 ccsidr = SCB->CCSIDR;
Kojto 124:2241e3a39974 2169 sets = (uint32_t)(CCSIDR_SETS(ccsidr));
Kojto 124:2241e3a39974 2170 sshift = (uint32_t)(CCSIDR_LSSHIFT(ccsidr) + 4UL);
Kojto 124:2241e3a39974 2171 ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
Kojto 124:2241e3a39974 2172 wshift = (uint32_t)((uint32_t)__CLZ(ways) & 0x1FUL);
Kojto 124:2241e3a39974 2173
Kojto 124:2241e3a39974 2174 __DSB();
Kojto 124:2241e3a39974 2175
Kojto 124:2241e3a39974 2176 do { // clean & invalidate D-Cache
Kojto 124:2241e3a39974 2177 uint32_t tmpways = ways;
Kojto 124:2241e3a39974 2178 do {
Kojto 124:2241e3a39974 2179 sw = ((tmpways << wshift) | (sets << sshift));
Kojto 124:2241e3a39974 2180 SCB->DCCISW = sw;
Kojto 124:2241e3a39974 2181 } while(tmpways--);
Kojto 124:2241e3a39974 2182 } while(sets--);
Kojto 124:2241e3a39974 2183
Kojto 124:2241e3a39974 2184 __DSB();
Kojto 124:2241e3a39974 2185 __ISB();
Kojto 124:2241e3a39974 2186 #endif
Kojto 124:2241e3a39974 2187 }
Kojto 124:2241e3a39974 2188
Kojto 124:2241e3a39974 2189
Kojto 124:2241e3a39974 2190 /**
Kojto 124:2241e3a39974 2191 \fn void SCB_InvalidateDCache_by_Addr(volatile uint32_t *addr, int32_t dsize)
Kojto 124:2241e3a39974 2192 \brief D-Cache Invalidate by address
Kojto 124:2241e3a39974 2193 \param[in] addr address (aligned to 32-byte boundary)
Kojto 124:2241e3a39974 2194 \param[in] dsize size of memory block (in number of bytes)
Kojto 124:2241e3a39974 2195 */
Kojto 124:2241e3a39974 2196 __STATIC_INLINE void SCB_InvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
Kojto 124:2241e3a39974 2197 {
Kojto 124:2241e3a39974 2198 #if (__DCACHE_PRESENT == 1)
Kojto 124:2241e3a39974 2199 int32_t op_size = dsize;
Kojto 124:2241e3a39974 2200 uint32_t op_addr = (uint32_t)addr;
Kojto 124:2241e3a39974 2201 uint32_t linesize = 32UL; // in Cortex-M7 size of cache line is fixed to 8 words (32 bytes)
Kojto 124:2241e3a39974 2202
Kojto 124:2241e3a39974 2203 __DSB();
Kojto 124:2241e3a39974 2204
Kojto 124:2241e3a39974 2205 while (op_size > 0) {
Kojto 124:2241e3a39974 2206 SCB->DCIMVAC = op_addr;
Kojto 124:2241e3a39974 2207 op_addr += linesize;
Kojto 124:2241e3a39974 2208 op_size -= (int32_t)linesize;
Kojto 124:2241e3a39974 2209 }
Kojto 124:2241e3a39974 2210
Kojto 124:2241e3a39974 2211 __DSB();
Kojto 124:2241e3a39974 2212 __ISB();
Kojto 124:2241e3a39974 2213 #endif
Kojto 124:2241e3a39974 2214 }
Kojto 124:2241e3a39974 2215
Kojto 124:2241e3a39974 2216
Kojto 124:2241e3a39974 2217 /**
Kojto 124:2241e3a39974 2218 \fn void SCB_CleanDCache_by_Addr(volatile uint32_t *addr, int32_t dsize)
Kojto 124:2241e3a39974 2219 \brief D-Cache Clean by address
Kojto 124:2241e3a39974 2220 \param[in] addr address (aligned to 32-byte boundary)
Kojto 124:2241e3a39974 2221 \param[in] dsize size of memory block (in number of bytes)
Kojto 124:2241e3a39974 2222 */
Kojto 124:2241e3a39974 2223 __STATIC_INLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize)
Kojto 124:2241e3a39974 2224 {
Kojto 124:2241e3a39974 2225 #if (__DCACHE_PRESENT == 1)
Kojto 124:2241e3a39974 2226 int32_t op_size = dsize;
Kojto 124:2241e3a39974 2227 uint32_t op_addr = (uint32_t) addr;
Kojto 124:2241e3a39974 2228 uint32_t linesize = 32UL; // in Cortex-M7 size of cache line is fixed to 8 words (32 bytes)
Kojto 124:2241e3a39974 2229
Kojto 124:2241e3a39974 2230 __DSB();
Kojto 124:2241e3a39974 2231
Kojto 124:2241e3a39974 2232 while (op_size > 0) {
Kojto 124:2241e3a39974 2233 SCB->DCCMVAC = op_addr;
Kojto 124:2241e3a39974 2234 op_addr += linesize;
Kojto 124:2241e3a39974 2235 op_size -= (int32_t)linesize;
Kojto 124:2241e3a39974 2236 }
Kojto 124:2241e3a39974 2237
Kojto 124:2241e3a39974 2238 __DSB();
Kojto 124:2241e3a39974 2239 __ISB();
Kojto 124:2241e3a39974 2240 #endif
Kojto 124:2241e3a39974 2241 }
Kojto 124:2241e3a39974 2242
Kojto 124:2241e3a39974 2243
Kojto 124:2241e3a39974 2244 /**
Kojto 124:2241e3a39974 2245 \fn void SCB_CleanInvalidateDCache_by_Addr(volatile uint32_t *addr, int32_t dsize)
Kojto 124:2241e3a39974 2246 \brief D-Cache Clean and Invalidate by address
Kojto 124:2241e3a39974 2247 \param[in] addr address (aligned to 32-byte boundary)
Kojto 124:2241e3a39974 2248 \param[in] dsize size of memory block (in number of bytes)
Kojto 124:2241e3a39974 2249 */
Kojto 124:2241e3a39974 2250 __STATIC_INLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
Kojto 124:2241e3a39974 2251 {
Kojto 124:2241e3a39974 2252 #if (__DCACHE_PRESENT == 1)
Kojto 124:2241e3a39974 2253 int32_t op_size = dsize;
Kojto 124:2241e3a39974 2254 uint32_t op_addr = (uint32_t) addr;
Kojto 124:2241e3a39974 2255 uint32_t linesize = 32UL; // in Cortex-M7 size of cache line is fixed to 8 words (32 bytes)
Kojto 124:2241e3a39974 2256
Kojto 124:2241e3a39974 2257 __DSB();
Kojto 124:2241e3a39974 2258
Kojto 124:2241e3a39974 2259 while (op_size > 0) {
Kojto 124:2241e3a39974 2260 SCB->DCCIMVAC = op_addr;
Kojto 124:2241e3a39974 2261 op_addr += linesize;
Kojto 124:2241e3a39974 2262 op_size -= (int32_t)linesize;
Kojto 124:2241e3a39974 2263 }
Kojto 124:2241e3a39974 2264
Kojto 124:2241e3a39974 2265 __DSB();
Kojto 124:2241e3a39974 2266 __ISB();
Kojto 124:2241e3a39974 2267 #endif
Kojto 124:2241e3a39974 2268 }
Kojto 124:2241e3a39974 2269
Kojto 124:2241e3a39974 2270
Kojto 124:2241e3a39974 2271 /*@} end of CMSIS_Core_CacheFunctions */
Kojto 124:2241e3a39974 2272
Kojto 124:2241e3a39974 2273
Kojto 124:2241e3a39974 2274
Kojto 124:2241e3a39974 2275 /* ################################## SysTick function ############################################ */
Kojto 124:2241e3a39974 2276 /** \ingroup CMSIS_Core_FunctionInterface
Kojto 124:2241e3a39974 2277 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
Kojto 124:2241e3a39974 2278 \brief Functions that configure the System.
Kojto 124:2241e3a39974 2279 @{
Kojto 124:2241e3a39974 2280 */
Kojto 124:2241e3a39974 2281
Kojto 124:2241e3a39974 2282 #if (__Vendor_SysTickConfig == 0)
Kojto 124:2241e3a39974 2283
Kojto 124:2241e3a39974 2284 /** \brief System Tick Configuration
Kojto 124:2241e3a39974 2285
Kojto 124:2241e3a39974 2286 The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
Kojto 124:2241e3a39974 2287 Counter is in free running mode to generate periodic interrupts.
Kojto 124:2241e3a39974 2288
Kojto 124:2241e3a39974 2289 \param [in] ticks Number of ticks between two interrupts.
Kojto 124:2241e3a39974 2290
Kojto 124:2241e3a39974 2291 \return 0 Function succeeded.
Kojto 124:2241e3a39974 2292 \return 1 Function failed.
Kojto 124:2241e3a39974 2293
Kojto 124:2241e3a39974 2294 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
Kojto 124:2241e3a39974 2295 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
Kojto 124:2241e3a39974 2296 must contain a vendor-specific implementation of this function.
Kojto 124:2241e3a39974 2297
Kojto 124:2241e3a39974 2298 */
Kojto 124:2241e3a39974 2299 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
Kojto 124:2241e3a39974 2300 {
Kojto 124:2241e3a39974 2301 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); } /* Reload value impossible */
Kojto 124:2241e3a39974 2302
Kojto 124:2241e3a39974 2303 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
Kojto 124:2241e3a39974 2304 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
Kojto 124:2241e3a39974 2305 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
Kojto 124:2241e3a39974 2306 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
Kojto 124:2241e3a39974 2307 SysTick_CTRL_TICKINT_Msk |
Kojto 124:2241e3a39974 2308 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
Kojto 124:2241e3a39974 2309 return (0UL); /* Function successful */
Kojto 124:2241e3a39974 2310 }
Kojto 124:2241e3a39974 2311
Kojto 124:2241e3a39974 2312 #endif
Kojto 124:2241e3a39974 2313
Kojto 124:2241e3a39974 2314 /*@} end of CMSIS_Core_SysTickFunctions */
Kojto 124:2241e3a39974 2315
Kojto 124:2241e3a39974 2316
Kojto 124:2241e3a39974 2317
Kojto 124:2241e3a39974 2318 /* ##################################### Debug In/Output function ########################################### */
Kojto 124:2241e3a39974 2319 /** \ingroup CMSIS_Core_FunctionInterface
Kojto 124:2241e3a39974 2320 \defgroup CMSIS_core_DebugFunctions ITM Functions
Kojto 124:2241e3a39974 2321 \brief Functions that access the ITM debug interface.
Kojto 124:2241e3a39974 2322 @{
Kojto 124:2241e3a39974 2323 */
Kojto 124:2241e3a39974 2324
Kojto 124:2241e3a39974 2325 extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
Kojto 124:2241e3a39974 2326 #define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
Kojto 124:2241e3a39974 2327
Kojto 124:2241e3a39974 2328
Kojto 124:2241e3a39974 2329 /** \brief ITM Send Character
Kojto 124:2241e3a39974 2330
Kojto 124:2241e3a39974 2331 The function transmits a character via the ITM channel 0, and
Kojto 124:2241e3a39974 2332 \li Just returns when no debugger is connected that has booked the output.
Kojto 124:2241e3a39974 2333 \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
Kojto 124:2241e3a39974 2334
Kojto 124:2241e3a39974 2335 \param [in] ch Character to transmit.
Kojto 124:2241e3a39974 2336
Kojto 124:2241e3a39974 2337 \returns Character to transmit.
Kojto 124:2241e3a39974 2338 */
Kojto 124:2241e3a39974 2339 __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
Kojto 124:2241e3a39974 2340 {
Kojto 124:2241e3a39974 2341 if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
Kojto 124:2241e3a39974 2342 ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
Kojto 124:2241e3a39974 2343 {
Kojto 124:2241e3a39974 2344 while (ITM->PORT[0].u32 == 0UL) { __NOP(); }
Kojto 124:2241e3a39974 2345 ITM->PORT[0].u8 = (uint8_t)ch;
Kojto 124:2241e3a39974 2346 }
Kojto 124:2241e3a39974 2347 return (ch);
Kojto 124:2241e3a39974 2348 }
Kojto 124:2241e3a39974 2349
Kojto 124:2241e3a39974 2350
Kojto 124:2241e3a39974 2351 /** \brief ITM Receive Character
Kojto 124:2241e3a39974 2352
Kojto 124:2241e3a39974 2353 The function inputs a character via the external variable \ref ITM_RxBuffer.
Kojto 124:2241e3a39974 2354
Kojto 124:2241e3a39974 2355 \return Received character.
Kojto 124:2241e3a39974 2356 \return -1 No character pending.
Kojto 124:2241e3a39974 2357 */
Kojto 124:2241e3a39974 2358 __STATIC_INLINE int32_t ITM_ReceiveChar (void) {
Kojto 124:2241e3a39974 2359 int32_t ch = -1; /* no character available */
Kojto 124:2241e3a39974 2360
Kojto 124:2241e3a39974 2361 if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
Kojto 124:2241e3a39974 2362 ch = ITM_RxBuffer;
Kojto 124:2241e3a39974 2363 ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
Kojto 124:2241e3a39974 2364 }
Kojto 124:2241e3a39974 2365
Kojto 124:2241e3a39974 2366 return (ch);
Kojto 124:2241e3a39974 2367 }
Kojto 124:2241e3a39974 2368
Kojto 124:2241e3a39974 2369
Kojto 124:2241e3a39974 2370 /** \brief ITM Check Character
Kojto 124:2241e3a39974 2371
Kojto 124:2241e3a39974 2372 The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
Kojto 124:2241e3a39974 2373
Kojto 124:2241e3a39974 2374 \return 0 No character available.
Kojto 124:2241e3a39974 2375 \return 1 Character available.
Kojto 124:2241e3a39974 2376 */
Kojto 124:2241e3a39974 2377 __STATIC_INLINE int32_t ITM_CheckChar (void) {
Kojto 124:2241e3a39974 2378
Kojto 124:2241e3a39974 2379 if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
Kojto 124:2241e3a39974 2380 return (0); /* no character available */
Kojto 124:2241e3a39974 2381 } else {
Kojto 124:2241e3a39974 2382 return (1); /* character available */
Kojto 124:2241e3a39974 2383 }
Kojto 124:2241e3a39974 2384 }
Kojto 124:2241e3a39974 2385
Kojto 124:2241e3a39974 2386 /*@} end of CMSIS_core_DebugFunctions */
Kojto 124:2241e3a39974 2387
Kojto 124:2241e3a39974 2388
Kojto 124:2241e3a39974 2389
Kojto 124:2241e3a39974 2390
Kojto 124:2241e3a39974 2391 #ifdef __cplusplus
Kojto 124:2241e3a39974 2392 }
Kojto 124:2241e3a39974 2393 #endif
Kojto 124:2241e3a39974 2394
Kojto 124:2241e3a39974 2395 #endif /* __CORE_CM7_H_DEPENDANT */
Kojto 124:2241e3a39974 2396
Kojto 124:2241e3a39974 2397 #endif /* __CMSIS_GENERIC */