mbed official / mbed

The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

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mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_NUCLEO_F334R8/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_ll_fmc.h@135:176b8275d35d, 2017-02-02 (annotated)

Committer:
<>
Date:
Thu Feb 02 16:02:30 2017 +0000
Revision:
135:176b8275d35d
Parent:
128:9bcdf88f62b0 
Release 135 of the mbed library



Ports for Upcoming Targets



3571: DISCO_F769NI introduction https://github.com/ARMmbed/mbed-os/pull/3571

3605: Add DELTA_DFCM_NNN50 platform https://github.com/ARMmbed/mbed-os/pull/3605

3640: [MAX32630FTHR] Adding new platform https://github.com/ARMmbed/mbed-os/pull/3640



Fixes and Changes



3397: Add uVisor support for the DISCO_F429ZI https://github.com/ARMmbed/mbed-os/pull/3397

3573: fix failing RTC initialization for MTS_DRAGONFLY_F411RE https://github.com/ARMmbed/mbed-os/pull/3573

3575: Dev stm factorize gpio https://github.com/ARMmbed/mbed-os/pull/3575

3584: STM32: make PeripheralPins.h a common file https://github.com/ARMmbed/mbed-os/pull/3584

3583: STM32F7 Cube FW new release v1.5.1 https://github.com/ARMmbed/mbed-os/pull/3583

3578: Target system - Inherit names from target parents https://github.com/ARMmbed/mbed-os/pull/3578

3599: K22F: Enable TRNG https://github.com/ARMmbed/mbed-os/pull/3599

3614: STM32: make PortNames.h a common file https://github.com/ARMmbed/mbed-os/pull/3614

3617: EFM32GG: Fix GCC_ARM linker script https://github.com/ARMmbed/mbed-os/pull/3617

3618: STM32: Move types definitions to a common file https://github.com/ARMmbed/mbed-os/pull/3618

3631: F3 CUBE update V1.7.0 https://github.com/ARMmbed/mbed-os/pull/3631

3635: STM32 I2C : Fix bug in i2c_byte_read function https://github.com/ARMmbed/mbed-os/pull/3635

3651: Max32630 - fix LED4 https://github.com/ARMmbed/mbed-os/pull/3651

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 92:4fc01daae5a5 1 /**
bogdanm 92:4fc01daae5a5 2 ******************************************************************************
bogdanm 92:4fc01daae5a5 3 * @file stm32f3xx_ll_fmc.h
bogdanm 92:4fc01daae5a5 4 * @author MCD Application Team
<> 135:176b8275d35d 5 * @version V1.4.0
<> 135:176b8275d35d 6 * @date 16-December-2016
bogdanm 92:4fc01daae5a5 7 * @brief Header file of FMC HAL module.
bogdanm 92:4fc01daae5a5 8 ******************************************************************************
bogdanm 92:4fc01daae5a5 9 * @attention
bogdanm 92:4fc01daae5a5 10 *
<> 135:176b8275d35d 11 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
bogdanm 92:4fc01daae5a5 12 *
bogdanm 92:4fc01daae5a5 13 * Redistribution and use in source and binary forms, with or without modification,
bogdanm 92:4fc01daae5a5 14 * are permitted provided that the following conditions are met:
bogdanm 92:4fc01daae5a5 15 * 1. Redistributions of source code must retain the above copyright notice,
bogdanm 92:4fc01daae5a5 16 * this list of conditions and the following disclaimer.
bogdanm 92:4fc01daae5a5 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm 92:4fc01daae5a5 18 * this list of conditions and the following disclaimer in the documentation
bogdanm 92:4fc01daae5a5 19 * and/or other materials provided with the distribution.
bogdanm 92:4fc01daae5a5 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm 92:4fc01daae5a5 21 * may be used to endorse or promote products derived from this software
bogdanm 92:4fc01daae5a5 22 * without specific prior written permission.
bogdanm 92:4fc01daae5a5 23 *
bogdanm 92:4fc01daae5a5 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 92:4fc01daae5a5 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 92:4fc01daae5a5 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 92:4fc01daae5a5 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm 92:4fc01daae5a5 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm 92:4fc01daae5a5 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm 92:4fc01daae5a5 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm 92:4fc01daae5a5 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm 92:4fc01daae5a5 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm 92:4fc01daae5a5 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm 92:4fc01daae5a5 34 *
bogdanm 92:4fc01daae5a5 35 ******************************************************************************
<> 135:176b8275d35d 36 */
bogdanm 92:4fc01daae5a5 37
bogdanm 92:4fc01daae5a5 38 /* Define to prevent recursive inclusion -------------------------------------*/
bogdanm 92:4fc01daae5a5 39 #ifndef __STM32F3xx_LL_FMC_H
bogdanm 92:4fc01daae5a5 40 #define __STM32F3xx_LL_FMC_H
bogdanm 92:4fc01daae5a5 41
bogdanm 92:4fc01daae5a5 42 #ifdef __cplusplus
<> 135:176b8275d35d 43 extern "C" {
bogdanm 92:4fc01daae5a5 44 #endif
bogdanm 92:4fc01daae5a5 45
bogdanm 92:4fc01daae5a5 46 /* Includes ------------------------------------------------------------------*/
bogdanm 92:4fc01daae5a5 47 #include "stm32f3xx_hal_def.h"
bogdanm 92:4fc01daae5a5 48
bogdanm 92:4fc01daae5a5 49 /** @addtogroup STM32F3xx_HAL_Driver
bogdanm 92:4fc01daae5a5 50 * @{
bogdanm 92:4fc01daae5a5 51 */
bogdanm 92:4fc01daae5a5 52
<> 135:176b8275d35d 53 #if defined(FMC_BANK1)
<> 135:176b8275d35d 54
<> 135:176b8275d35d 55 /** @addtogroup FMC_LL
<> 135:176b8275d35d 56 * @{
<> 135:176b8275d35d 57 */
<> 135:176b8275d35d 58
<> 135:176b8275d35d 59 /** @addtogroup FMC_LL_Private_Macros
<> 135:176b8275d35d 60 * @{
<> 135:176b8275d35d 61 */
<> 135:176b8275d35d 62
<> 135:176b8275d35d 63 #define IS_FMC_NORSRAM_BANK(__BANK__) (((__BANK__) == FMC_NORSRAM_BANK1) || \
<> 135:176b8275d35d 64 ((__BANK__) == FMC_NORSRAM_BANK2) || \
<> 135:176b8275d35d 65 ((__BANK__) == FMC_NORSRAM_BANK3) || \
<> 135:176b8275d35d 66 ((__BANK__) == FMC_NORSRAM_BANK4))
<> 135:176b8275d35d 67
<> 135:176b8275d35d 68 #define IS_FMC_MUX(__MUX__) (((__MUX__) == FMC_DATA_ADDRESS_MUX_DISABLE) || \
<> 135:176b8275d35d 69 ((__MUX__) == FMC_DATA_ADDRESS_MUX_ENABLE))
<> 135:176b8275d35d 70
<> 135:176b8275d35d 71 #define IS_FMC_MEMORY(__MEMORY__) (((__MEMORY__) == FMC_MEMORY_TYPE_SRAM) || \
<> 135:176b8275d35d 72 ((__MEMORY__) == FMC_MEMORY_TYPE_PSRAM)|| \
<> 135:176b8275d35d 73 ((__MEMORY__) == FMC_MEMORY_TYPE_NOR))
<> 135:176b8275d35d 74
<> 135:176b8275d35d 75 #define IS_FMC_NORSRAM_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_8) || \
<> 135:176b8275d35d 76 ((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_16) || \
<> 135:176b8275d35d 77 ((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_32))
<> 135:176b8275d35d 78
<> 135:176b8275d35d 79 #define IS_FMC_WRITE_BURST(__BURST__) (((__BURST__) == FMC_WRITE_BURST_DISABLE) || \
<> 135:176b8275d35d 80 ((__BURST__) == FMC_WRITE_BURST_ENABLE))
<> 135:176b8275d35d 81
<> 135:176b8275d35d 82 #define IS_FMC_CONTINOUS_CLOCK(__CCLOCK__) (((__CCLOCK__) == FMC_CONTINUOUS_CLOCK_SYNC_ONLY) || \
<> 135:176b8275d35d 83 ((__CCLOCK__) == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC))
<> 135:176b8275d35d 84
<> 135:176b8275d35d 85 #define IS_FMC_ACCESS_MODE(__MODE__) (((__MODE__) == FMC_ACCESS_MODE_A) || \
<> 135:176b8275d35d 86 ((__MODE__) == FMC_ACCESS_MODE_B) || \
<> 135:176b8275d35d 87 ((__MODE__) == FMC_ACCESS_MODE_C) || \
<> 135:176b8275d35d 88 ((__MODE__) == FMC_ACCESS_MODE_D))
<> 135:176b8275d35d 89
<> 135:176b8275d35d 90 #define IS_FMC_NAND_BANK(__BANK__) (((__BANK__) == FMC_NAND_BANK2) || \
<> 135:176b8275d35d 91 ((__BANK__) == FMC_NAND_BANK3))
<> 135:176b8275d35d 92
<> 135:176b8275d35d 93 #define IS_FMC_WAIT_FEATURE(__FEATURE__) (((__FEATURE__) == FMC_NAND_PCC_WAIT_FEATURE_DISABLE) || \
<> 135:176b8275d35d 94 ((__FEATURE__) == FMC_NAND_PCC_WAIT_FEATURE_ENABLE))
<> 135:176b8275d35d 95
<> 135:176b8275d35d 96 #define IS_FMC_NAND_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FMC_NAND_PCC_MEM_BUS_WIDTH_8) || \
<> 135:176b8275d35d 97 ((__WIDTH__) == FMC_NAND_PCC_MEM_BUS_WIDTH_16))
<> 135:176b8275d35d 98
<> 135:176b8275d35d 99 #define IS_FMC_ECC_STATE(__STATE__) (((__STATE__) == FMC_NAND_ECC_DISABLE) || \
<> 135:176b8275d35d 100 ((__STATE__) == FMC_NAND_ECC_ENABLE))
<> 135:176b8275d35d 101
<> 135:176b8275d35d 102 #define IS_FMC_ECCPAGE_SIZE(__SIZE__) (((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_256BYTE) || \
<> 135:176b8275d35d 103 ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_512BYTE) || \
<> 135:176b8275d35d 104 ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_1024BYTE) || \
<> 135:176b8275d35d 105 ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_2048BYTE) || \
<> 135:176b8275d35d 106 ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_4096BYTE) || \
<> 135:176b8275d35d 107 ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_8192BYTE))
<> 135:176b8275d35d 108
<> 135:176b8275d35d 109 /** @defgroup FMC_TCLR_Setup_Time FMC_TCLR_Setup_Time
<> 135:176b8275d35d 110 * @{
<> 135:176b8275d35d 111 */
<> 135:176b8275d35d 112 #define IS_FMC_TCLR_TIME(__TIME__) ((__TIME__) <= 255)
<> 135:176b8275d35d 113 /**
<> 135:176b8275d35d 114 * @}
<> 135:176b8275d35d 115 */
<> 135:176b8275d35d 116
<> 135:176b8275d35d 117 /** @defgroup FMC_TAR_Setup_Time FMC_TAR_Setup_Time
<> 135:176b8275d35d 118 * @{
<> 135:176b8275d35d 119 */
<> 135:176b8275d35d 120 #define IS_FMC_TAR_TIME(__TIME__) ((__TIME__) <= 255)
<> 135:176b8275d35d 121 /**
<> 135:176b8275d35d 122 * @}
<> 135:176b8275d35d 123 */
<> 135:176b8275d35d 124
<> 135:176b8275d35d 125 /** @defgroup FMC_Setup_Time FMC_Setup_Time
<> 135:176b8275d35d 126 * @{
<> 135:176b8275d35d 127 */
<> 135:176b8275d35d 128 #define IS_FMC_SETUP_TIME(__TIME__) ((__TIME__) <= 255)
<> 135:176b8275d35d 129 /**
<> 135:176b8275d35d 130 * @}
<> 135:176b8275d35d 131 */
<> 135:176b8275d35d 132
<> 135:176b8275d35d 133 /** @defgroup FMC_Wait_Setup_Time FMC_Wait_Setup_Time
<> 135:176b8275d35d 134 * @{
<> 135:176b8275d35d 135 */
<> 135:176b8275d35d 136 #define IS_FMC_WAIT_TIME(__TIME__) ((__TIME__) <= 255)
<> 135:176b8275d35d 137 /**
<> 135:176b8275d35d 138 * @}
<> 135:176b8275d35d 139 */
<> 135:176b8275d35d 140
<> 135:176b8275d35d 141 /** @defgroup FMC_Hold_Setup_Time FMC_Hold_Setup_Time
<> 135:176b8275d35d 142 * @{
<> 135:176b8275d35d 143 */
<> 135:176b8275d35d 144 #define IS_FMC_HOLD_TIME(__TIME__) ((__TIME__) <= 255)
<> 135:176b8275d35d 145 /**
<> 135:176b8275d35d 146 * @}
<> 135:176b8275d35d 147 */
<> 135:176b8275d35d 148
<> 135:176b8275d35d 149 /** @defgroup FMC_HiZ_Setup_Time FMC_HiZ_Setup_Time
<> 135:176b8275d35d 150 * @{
<> 135:176b8275d35d 151 */
<> 135:176b8275d35d 152 #define IS_FMC_HIZ_TIME(__TIME__) ((__TIME__) <= 255)
<> 135:176b8275d35d 153 /**
<> 135:176b8275d35d 154 * @}
<> 135:176b8275d35d 155 */
<> 135:176b8275d35d 156
<> 135:176b8275d35d 157 /** @defgroup FMC_NORSRAM_Device_Instance FMC NOR/SRAM Device Instance
bogdanm 92:4fc01daae5a5 158 * @{
<> 135:176b8275d35d 159 */
<> 135:176b8275d35d 160
<> 135:176b8275d35d 161 #define IS_FMC_NORSRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_DEVICE)
<> 135:176b8275d35d 162
<> 135:176b8275d35d 163 /**
<> 135:176b8275d35d 164 * @}
<> 135:176b8275d35d 165 */
<> 135:176b8275d35d 166
<> 135:176b8275d35d 167 /** @defgroup FMC_NORSRAM_EXTENDED_Device_Instance FMC NOR/SRAM EXTENDED Device Instance
<> 135:176b8275d35d 168 * @{
<> 135:176b8275d35d 169 */
<> 135:176b8275d35d 170
<> 135:176b8275d35d 171 #define IS_FMC_NORSRAM_EXTENDED_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_EXTENDED_DEVICE)
<> 135:176b8275d35d 172
<> 135:176b8275d35d 173 /**
<> 135:176b8275d35d 174 * @}
<> 135:176b8275d35d 175 */
<> 135:176b8275d35d 176
<> 135:176b8275d35d 177 /** @defgroup FMC_NAND_Device_Instance FMC NAND Device Instance
<> 135:176b8275d35d 178 * @{
<> 135:176b8275d35d 179 */
<> 135:176b8275d35d 180 #define IS_FMC_NAND_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NAND_DEVICE)
<> 135:176b8275d35d 181 /**
<> 135:176b8275d35d 182 * @}
<> 135:176b8275d35d 183 */
<> 135:176b8275d35d 184
<> 135:176b8275d35d 185 /** @defgroup FMC_PCCARD_Device_Instance FMC PCCARD Device Instance
<> 135:176b8275d35d 186 * @{
<> 135:176b8275d35d 187 */
<> 135:176b8275d35d 188 #define IS_FMC_PCCARD_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_PCCARD_DEVICE)
<> 135:176b8275d35d 189
<> 135:176b8275d35d 190 /**
<> 135:176b8275d35d 191 * @}
<> 135:176b8275d35d 192 */
<> 135:176b8275d35d 193 #define IS_FMC_BURSTMODE(__STATE__) (((__STATE__) == FMC_BURST_ACCESS_MODE_DISABLE) || \
<> 135:176b8275d35d 194 ((__STATE__) == FMC_BURST_ACCESS_MODE_ENABLE))
<> 135:176b8275d35d 195
<> 135:176b8275d35d 196 #define IS_FMC_WAIT_POLARITY(__POLARITY__) (((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_LOW) || \
<> 135:176b8275d35d 197 ((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_HIGH))
<> 135:176b8275d35d 198
<> 135:176b8275d35d 199 #define IS_FMC_WRAP_MODE(__MODE__) (((__MODE__) == FMC_WRAP_MODE_DISABLE) || \
<> 135:176b8275d35d 200 ((__MODE__) == FMC_WRAP_MODE_ENABLE))
<> 135:176b8275d35d 201
<> 135:176b8275d35d 202 #define IS_FMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__) (((__ACTIVE__) == FMC_WAIT_TIMING_BEFORE_WS) || \
<> 135:176b8275d35d 203 ((__ACTIVE__) == FMC_WAIT_TIMING_DURING_WS))
<> 135:176b8275d35d 204
<> 135:176b8275d35d 205 #define IS_FMC_WRITE_OPERATION(__OPERATION__) (((__OPERATION__) == FMC_WRITE_OPERATION_DISABLE) || \
<> 135:176b8275d35d 206 ((__OPERATION__) == FMC_WRITE_OPERATION_ENABLE))
<> 135:176b8275d35d 207
<> 135:176b8275d35d 208 #define IS_FMC_WAITE_SIGNAL(__SIGNAL__) (((__SIGNAL__) == FMC_WAIT_SIGNAL_DISABLE) || \
<> 135:176b8275d35d 209 ((__SIGNAL__) == FMC_WAIT_SIGNAL_ENABLE))
<> 135:176b8275d35d 210
<> 135:176b8275d35d 211 #define IS_FMC_EXTENDED_MODE(__MODE__) (((__MODE__) == FMC_EXTENDED_MODE_DISABLE) || \
<> 135:176b8275d35d 212 ((__MODE__) == FMC_EXTENDED_MODE_ENABLE))
bogdanm 92:4fc01daae5a5 213
<> 135:176b8275d35d 214 #define IS_FMC_ASYNWAIT(__STATE__) (((__STATE__) == FMC_ASYNCHRONOUS_WAIT_DISABLE) || \
<> 135:176b8275d35d 215 ((__STATE__) == FMC_ASYNCHRONOUS_WAIT_ENABLE))
<> 135:176b8275d35d 216
<> 135:176b8275d35d 217 #define IS_FMC_CLK_DIV(__DIV__) (((__DIV__) > 1) && ((__DIV__) <= 16))
<> 135:176b8275d35d 218
<> 135:176b8275d35d 219 /** @defgroup FMC_Data_Latency FMC Data Latency
<> 135:176b8275d35d 220 * @{
<> 135:176b8275d35d 221 */
<> 135:176b8275d35d 222 #define IS_FMC_DATA_LATENCY(__LATENCY__) (((__LATENCY__) > 1) && ((__LATENCY__) <= 17))
<> 135:176b8275d35d 223 /**
<> 135:176b8275d35d 224 * @}
<> 135:176b8275d35d 225 */
<> 135:176b8275d35d 226
<> 135:176b8275d35d 227 /** @defgroup FMC_Address_Setup_Time FMC Address Setup Time
<> 135:176b8275d35d 228 * @{
<> 135:176b8275d35d 229 */
<> 135:176b8275d35d 230 #define IS_FMC_ADDRESS_SETUP_TIME(__TIME__) ((__TIME__) <= 15)
<> 135:176b8275d35d 231 /**
<> 135:176b8275d35d 232 * @}
<> 135:176b8275d35d 233 */
<> 135:176b8275d35d 234
<> 135:176b8275d35d 235 /** @defgroup FMC_Address_Hold_Time FMC Address Hold Time
<> 135:176b8275d35d 236 * @{
<> 135:176b8275d35d 237 */
<> 135:176b8275d35d 238 #define IS_FMC_ADDRESS_HOLD_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 15))
<> 135:176b8275d35d 239 /**
<> 135:176b8275d35d 240 * @}
<> 135:176b8275d35d 241 */
<> 135:176b8275d35d 242
<> 135:176b8275d35d 243 /** @defgroup FMC_Data_Setup_Time FMC Data Setup Time
<> 135:176b8275d35d 244 * @{
<> 135:176b8275d35d 245 */
<> 135:176b8275d35d 246 #define IS_FMC_DATASETUP_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 255))
<> 135:176b8275d35d 247 /**
<> 135:176b8275d35d 248 * @}
<> 135:176b8275d35d 249 */
<> 135:176b8275d35d 250
<> 135:176b8275d35d 251 /** @defgroup FMC_Bus_Turn_around_Duration FMC Bus Turn around Duration
<> 135:176b8275d35d 252 * @{
<> 135:176b8275d35d 253 */
<> 135:176b8275d35d 254 #define IS_FMC_TURNAROUND_TIME(__TIME__) ((__TIME__) <= 15)
<> 135:176b8275d35d 255 /**
<> 135:176b8275d35d 256 * @}
<> 135:176b8275d35d 257 */
<> 135:176b8275d35d 258
<> 135:176b8275d35d 259 /**
<> 135:176b8275d35d 260 * @}
<> 135:176b8275d35d 261 */
<> 135:176b8275d35d 262
<> 135:176b8275d35d 263 /* Exported typedef ----------------------------------------------------------*/
<> 135:176b8275d35d 264
<> 135:176b8275d35d 265 /** @defgroup FMC_NORSRAM_Exported_typedef FMC Low Layer Exported Types
<> 135:176b8275d35d 266 * @{
<> 135:176b8275d35d 267 */
<> 135:176b8275d35d 268
bogdanm 92:4fc01daae5a5 269 #define FMC_NORSRAM_TypeDef FMC_Bank1_TypeDef
bogdanm 92:4fc01daae5a5 270 #define FMC_NORSRAM_EXTENDED_TypeDef FMC_Bank1E_TypeDef
bogdanm 92:4fc01daae5a5 271 #define FMC_NAND_TypeDef FMC_Bank2_3_TypeDef
bogdanm 92:4fc01daae5a5 272 #define FMC_PCCARD_TypeDef FMC_Bank4_TypeDef
bogdanm 92:4fc01daae5a5 273
<> 135:176b8275d35d 274 #define FMC_NORSRAM_DEVICE FMC_Bank1
<> 135:176b8275d35d 275 #define FMC_NORSRAM_EXTENDED_DEVICE FMC_Bank1E
<> 135:176b8275d35d 276 #define FMC_NAND_DEVICE FMC_Bank2_3
<> 135:176b8275d35d 277 #define FMC_PCCARD_DEVICE FMC_Bank4
bogdanm 92:4fc01daae5a5 278
<> 135:176b8275d35d 279 /**
<> 135:176b8275d35d 280 * @brief FMC_NORSRAM Configuration Structure definition
<> 135:176b8275d35d 281 */
bogdanm 92:4fc01daae5a5 282 typedef struct
bogdanm 92:4fc01daae5a5 283 {
bogdanm 92:4fc01daae5a5 284 uint32_t NSBank; /*!< Specifies the NORSRAM memory device that will be used.
<> 135:176b8275d35d 285 This parameter can be a value of @ref FMC_NORSRAM_Bank */
<> 135:176b8275d35d 286
bogdanm 92:4fc01daae5a5 287 uint32_t DataAddressMux; /*!< Specifies whether the address and data values are
<> 135:176b8275d35d 288 multiplexed on the data bus or not.
bogdanm 92:4fc01daae5a5 289 This parameter can be a value of @ref FMC_Data_Address_Bus_Multiplexing */
<> 135:176b8275d35d 290
bogdanm 92:4fc01daae5a5 291 uint32_t MemoryType; /*!< Specifies the type of external memory attached to
bogdanm 92:4fc01daae5a5 292 the corresponding memory device.
bogdanm 92:4fc01daae5a5 293 This parameter can be a value of @ref FMC_Memory_Type */
<> 135:176b8275d35d 294
bogdanm 92:4fc01daae5a5 295 uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
bogdanm 92:4fc01daae5a5 296 This parameter can be a value of @ref FMC_NORSRAM_Data_Width */
<> 135:176b8275d35d 297
bogdanm 92:4fc01daae5a5 298 uint32_t BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory,
bogdanm 92:4fc01daae5a5 299 valid only with synchronous burst Flash memories.
bogdanm 92:4fc01daae5a5 300 This parameter can be a value of @ref FMC_Burst_Access_Mode */
<> 135:176b8275d35d 301
bogdanm 92:4fc01daae5a5 302 uint32_t WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing
bogdanm 92:4fc01daae5a5 303 the Flash memory in burst mode.
bogdanm 92:4fc01daae5a5 304 This parameter can be a value of @ref FMC_Wait_Signal_Polarity */
<> 135:176b8275d35d 305
bogdanm 92:4fc01daae5a5 306 uint32_t WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash
bogdanm 92:4fc01daae5a5 307 memory, valid only when accessing Flash memories in burst mode.
bogdanm 92:4fc01daae5a5 308 This parameter can be a value of @ref FMC_Wrap_Mode */
<> 135:176b8275d35d 309
bogdanm 92:4fc01daae5a5 310 uint32_t WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one
bogdanm 92:4fc01daae5a5 311 clock cycle before the wait state or during the wait state,
<> 135:176b8275d35d 312 valid only when accessing memories in burst mode.
bogdanm 92:4fc01daae5a5 313 This parameter can be a value of @ref FMC_Wait_Timing */
<> 135:176b8275d35d 314
<> 135:176b8275d35d 315 uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device by the FMC.
bogdanm 92:4fc01daae5a5 316 This parameter can be a value of @ref FMC_Write_Operation */
<> 135:176b8275d35d 317
bogdanm 92:4fc01daae5a5 318 uint32_t WaitSignal; /*!< Enables or disables the wait state insertion via wait
<> 135:176b8275d35d 319 signal, valid for Flash memory access in burst mode.
bogdanm 92:4fc01daae5a5 320 This parameter can be a value of @ref FMC_Wait_Signal */
<> 135:176b8275d35d 321
bogdanm 92:4fc01daae5a5 322 uint32_t ExtendedMode; /*!< Enables or disables the extended mode.
bogdanm 92:4fc01daae5a5 323 This parameter can be a value of @ref FMC_Extended_Mode */
<> 135:176b8275d35d 324
bogdanm 92:4fc01daae5a5 325 uint32_t AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers,
bogdanm 92:4fc01daae5a5 326 valid only with asynchronous Flash memories.
bogdanm 92:4fc01daae5a5 327 This parameter can be a value of @ref FMC_AsynchronousWait */
<> 135:176b8275d35d 328
bogdanm 92:4fc01daae5a5 329 uint32_t WriteBurst; /*!< Enables or disables the write burst operation.
<> 135:176b8275d35d 330 This parameter can be a value of @ref FMC_Write_Burst */
bogdanm 92:4fc01daae5a5 331
bogdanm 92:4fc01daae5a5 332 uint32_t ContinuousClock; /*!< Enables or disables the FMC clock output to external memory devices.
<> 135:176b8275d35d 333 This parameter is only enabled through the FMC_BCR1 register, and don't care
bogdanm 92:4fc01daae5a5 334 through FMC_BCR2..4 registers.
bogdanm 92:4fc01daae5a5 335 This parameter can be a value of @ref FMC_Continous_Clock */
bogdanm 92:4fc01daae5a5 336
bogdanm 92:4fc01daae5a5 337 }FMC_NORSRAM_InitTypeDef;
bogdanm 92:4fc01daae5a5 338
<> 135:176b8275d35d 339 /**
<> 135:176b8275d35d 340 * @brief FMC_NORSRAM Timing parameters structure definition
bogdanm 92:4fc01daae5a5 341 */
bogdanm 92:4fc01daae5a5 342 typedef struct
bogdanm 92:4fc01daae5a5 343 {
bogdanm 92:4fc01daae5a5 344 uint32_t AddressSetupTime; /*!< Defines the number of HCLK cycles to configure
<> 135:176b8275d35d 345 the duration of the address setup time.
bogdanm 92:4fc01daae5a5 346 This parameter can be a value between Min_Data = 0 and Max_Data = 15.
bogdanm 92:4fc01daae5a5 347 @note This parameter is not used with synchronous NOR Flash memories. */
<> 135:176b8275d35d 348
bogdanm 92:4fc01daae5a5 349 uint32_t AddressHoldTime; /*!< Defines the number of HCLK cycles to configure
bogdanm 92:4fc01daae5a5 350 the duration of the address hold time.
<> 135:176b8275d35d 351 This parameter can be a value between Min_Data = 1 and Max_Data = 15.
bogdanm 92:4fc01daae5a5 352 @note This parameter is not used with synchronous NOR Flash memories. */
<> 135:176b8275d35d 353
bogdanm 92:4fc01daae5a5 354 uint32_t DataSetupTime; /*!< Defines the number of HCLK cycles to configure
bogdanm 92:4fc01daae5a5 355 the duration of the data setup time.
bogdanm 92:4fc01daae5a5 356 This parameter can be a value between Min_Data = 1 and Max_Data = 255.
<> 135:176b8275d35d 357 @note This parameter is used for SRAMs, ROMs and asynchronous multiplexed
bogdanm 92:4fc01daae5a5 358 NOR Flash memories. */
<> 135:176b8275d35d 359
bogdanm 92:4fc01daae5a5 360 uint32_t BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure
bogdanm 92:4fc01daae5a5 361 the duration of the bus turnaround.
bogdanm 92:4fc01daae5a5 362 This parameter can be a value between Min_Data = 0 and Max_Data = 15.
bogdanm 92:4fc01daae5a5 363 @note This parameter is only used for multiplexed NOR Flash memories. */
<> 135:176b8275d35d 364
<> 135:176b8275d35d 365 uint32_t CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of
bogdanm 92:4fc01daae5a5 366 HCLK cycles. This parameter can be a value between Min_Data = 2 and Max_Data = 16.
<> 135:176b8275d35d 367 @note This parameter is not used for asynchronous NOR Flash, SRAM or ROM
bogdanm 92:4fc01daae5a5 368 accesses. */
<> 135:176b8275d35d 369
bogdanm 92:4fc01daae5a5 370 uint32_t DataLatency; /*!< Defines the number of memory clock cycles to issue
bogdanm 92:4fc01daae5a5 371 to the memory before getting the first data.
bogdanm 92:4fc01daae5a5 372 The parameter value depends on the memory type as shown below:
bogdanm 92:4fc01daae5a5 373 - It must be set to 0 in case of a CRAM
bogdanm 92:4fc01daae5a5 374 - It is don't care in asynchronous NOR, SRAM or ROM accesses
bogdanm 92:4fc01daae5a5 375 - It may assume a value between Min_Data = 2 and Max_Data = 17 in NOR Flash memories
bogdanm 92:4fc01daae5a5 376 with synchronous burst mode enable */
<> 135:176b8275d35d 377
<> 135:176b8275d35d 378 uint32_t AccessMode; /*!< Specifies the asynchronous access mode.
bogdanm 92:4fc01daae5a5 379 This parameter can be a value of @ref FMC_Access_Mode */
bogdanm 92:4fc01daae5a5 380
bogdanm 92:4fc01daae5a5 381 }FMC_NORSRAM_TimingTypeDef;
bogdanm 92:4fc01daae5a5 382
<> 135:176b8275d35d 383 /**
<> 135:176b8275d35d 384 * @brief FMC_NAND Configuration Structure definition
<> 135:176b8275d35d 385 */
bogdanm 92:4fc01daae5a5 386 typedef struct
bogdanm 92:4fc01daae5a5 387 {
bogdanm 92:4fc01daae5a5 388 uint32_t NandBank; /*!< Specifies the NAND memory device that will be used.
<> 135:176b8275d35d 389 This parameter can be a value of @ref FMC_NAND_Bank */
<> 135:176b8275d35d 390
bogdanm 92:4fc01daae5a5 391 uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory device.
bogdanm 92:4fc01daae5a5 392 This parameter can be any value of @ref FMC_Wait_feature */
<> 135:176b8275d35d 393
bogdanm 92:4fc01daae5a5 394 uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
bogdanm 92:4fc01daae5a5 395 This parameter can be any value of @ref FMC_NAND_Data_Width */
<> 135:176b8275d35d 396
bogdanm 92:4fc01daae5a5 397 uint32_t EccComputation; /*!< Enables or disables the ECC computation.
bogdanm 92:4fc01daae5a5 398 This parameter can be any value of @ref FMC_ECC */
<> 135:176b8275d35d 399
bogdanm 92:4fc01daae5a5 400 uint32_t ECCPageSize; /*!< Defines the page size for the extended ECC.
bogdanm 92:4fc01daae5a5 401 This parameter can be any value of @ref FMC_ECC_Page_Size */
<> 135:176b8275d35d 402
bogdanm 92:4fc01daae5a5 403 uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
bogdanm 92:4fc01daae5a5 404 delay between CLE low and RE low.
bogdanm 92:4fc01daae5a5 405 This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
<> 135:176b8275d35d 406
bogdanm 92:4fc01daae5a5 407 uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
bogdanm 92:4fc01daae5a5 408 delay between ALE low and RE low.
bogdanm 92:4fc01daae5a5 409 This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
<> 135:176b8275d35d 410
<> 135:176b8275d35d 411 }FMC_NAND_InitTypeDef;
bogdanm 92:4fc01daae5a5 412
<> 135:176b8275d35d 413 /**
<> 135:176b8275d35d 414 * @brief FMC_NAND_PCC Timing parameters structure definition
bogdanm 92:4fc01daae5a5 415 */
bogdanm 92:4fc01daae5a5 416 typedef struct
bogdanm 92:4fc01daae5a5 417 {
bogdanm 92:4fc01daae5a5 418 uint32_t SetupTime; /*!< Defines the number of HCLK cycles to setup address before
bogdanm 92:4fc01daae5a5 419 the command assertion for NAND-Flash read or write access
bogdanm 92:4fc01daae5a5 420 to common/Attribute or I/O memory space (depending on
bogdanm 92:4fc01daae5a5 421 the memory space timing to be configured).
bogdanm 92:4fc01daae5a5 422 This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
<> 135:176b8275d35d 423
bogdanm 92:4fc01daae5a5 424 uint32_t WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the
bogdanm 92:4fc01daae5a5 425 command for NAND-Flash read or write access to
bogdanm 92:4fc01daae5a5 426 common/Attribute or I/O memory space (depending on the
<> 135:176b8275d35d 427 memory space timing to be configured).
bogdanm 92:4fc01daae5a5 428 This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
<> 135:176b8275d35d 429
bogdanm 92:4fc01daae5a5 430 uint32_t HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address
bogdanm 92:4fc01daae5a5 431 (and data for write access) after the command de-assertion
bogdanm 92:4fc01daae5a5 432 for NAND-Flash read or write access to common/Attribute
bogdanm 92:4fc01daae5a5 433 or I/O memory space (depending on the memory space timing
bogdanm 92:4fc01daae5a5 434 to be configured).
bogdanm 92:4fc01daae5a5 435 This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
<> 135:176b8275d35d 436
bogdanm 92:4fc01daae5a5 437 uint32_t HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the
bogdanm 92:4fc01daae5a5 438 data bus is kept in HiZ after the start of a NAND-Flash
bogdanm 92:4fc01daae5a5 439 write access to common/Attribute or I/O memory space (depending
bogdanm 92:4fc01daae5a5 440 on the memory space timing to be configured).
bogdanm 92:4fc01daae5a5 441 This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
<> 135:176b8275d35d 442
bogdanm 92:4fc01daae5a5 443 }FMC_NAND_PCC_TimingTypeDef;
bogdanm 92:4fc01daae5a5 444
<> 135:176b8275d35d 445 /**
<> 135:176b8275d35d 446 * @brief FMC_NAND Configuration Structure definition
<> 135:176b8275d35d 447 */
bogdanm 92:4fc01daae5a5 448 typedef struct
bogdanm 92:4fc01daae5a5 449 {
bogdanm 92:4fc01daae5a5 450 uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the PCCARD Memory device.
bogdanm 92:4fc01daae5a5 451 This parameter can be any value of @ref FMC_Wait_feature */
<> 135:176b8275d35d 452
bogdanm 92:4fc01daae5a5 453 uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
bogdanm 92:4fc01daae5a5 454 delay between CLE low and RE low.
bogdanm 92:4fc01daae5a5 455 This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
<> 135:176b8275d35d 456
bogdanm 92:4fc01daae5a5 457 uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
bogdanm 92:4fc01daae5a5 458 delay between ALE low and RE low.
bogdanm 92:4fc01daae5a5 459 This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
<> 135:176b8275d35d 460
<> 135:176b8275d35d 461 }FMC_PCCARD_InitTypeDef;
<> 135:176b8275d35d 462
<> 135:176b8275d35d 463 /**
<> 135:176b8275d35d 464 * @}
<> 135:176b8275d35d 465 */
bogdanm 92:4fc01daae5a5 466
bogdanm 92:4fc01daae5a5 467 /* Exported constants --------------------------------------------------------*/
bogdanm 92:4fc01daae5a5 468
<> 135:176b8275d35d 469 /** @defgroup FMC_Exported_Constants FMC Low Layer Exported Constants
bogdanm 92:4fc01daae5a5 470 * @{
<> 135:176b8275d35d 471 */
<> 135:176b8275d35d 472
<> 135:176b8275d35d 473 /** @defgroup FMC_NORSRAM_Exported_constants FMC NOR/SRAM Exported constants
<> 135:176b8275d35d 474 * @{
<> 135:176b8275d35d 475 */
<> 135:176b8275d35d 476
<> 135:176b8275d35d 477 /** @defgroup FMC_NORSRAM_Bank FMC NOR/SRAM Bank
bogdanm 92:4fc01daae5a5 478 * @{
bogdanm 92:4fc01daae5a5 479 */
bogdanm 92:4fc01daae5a5 480 #define FMC_NORSRAM_BANK1 ((uint32_t)0x00000000)
bogdanm 92:4fc01daae5a5 481 #define FMC_NORSRAM_BANK2 ((uint32_t)0x00000002)
bogdanm 92:4fc01daae5a5 482 #define FMC_NORSRAM_BANK3 ((uint32_t)0x00000004)
bogdanm 92:4fc01daae5a5 483 #define FMC_NORSRAM_BANK4 ((uint32_t)0x00000006)
bogdanm 92:4fc01daae5a5 484
bogdanm 92:4fc01daae5a5 485 /**
bogdanm 92:4fc01daae5a5 486 * @}
bogdanm 92:4fc01daae5a5 487 */
bogdanm 92:4fc01daae5a5 488
<> 135:176b8275d35d 489 /** @defgroup FMC_Data_Address_Bus_Multiplexing FMC Data Address Bus Multiplexing
bogdanm 92:4fc01daae5a5 490 * @{
bogdanm 92:4fc01daae5a5 491 */
bogdanm 92:4fc01daae5a5 492
<> 135:176b8275d35d 493 #define FMC_DATA_ADDRESS_MUX_DISABLE ((uint32_t)0x00000000)
<> 135:176b8275d35d 494 #define FMC_DATA_ADDRESS_MUX_ENABLE ((uint32_t)FMC_BCRx_MUXEN)
<> 135:176b8275d35d 495
bogdanm 92:4fc01daae5a5 496 /**
bogdanm 92:4fc01daae5a5 497 * @}
bogdanm 92:4fc01daae5a5 498 */
bogdanm 92:4fc01daae5a5 499
<> 135:176b8275d35d 500 /** @defgroup FMC_Memory_Type FMC Memory Type
bogdanm 92:4fc01daae5a5 501 * @{
bogdanm 92:4fc01daae5a5 502 */
bogdanm 92:4fc01daae5a5 503
<> 135:176b8275d35d 504 #define FMC_MEMORY_TYPE_SRAM ((uint32_t)0x00000000)
<> 135:176b8275d35d 505 #define FMC_MEMORY_TYPE_PSRAM ((uint32_t)FMC_BCRx_MTYP_0)
<> 135:176b8275d35d 506 #define FMC_MEMORY_TYPE_NOR ((uint32_t)FMC_BCRx_MTYP_1)
<> 135:176b8275d35d 507
bogdanm 92:4fc01daae5a5 508 /**
bogdanm 92:4fc01daae5a5 509 * @}
bogdanm 92:4fc01daae5a5 510 */
bogdanm 92:4fc01daae5a5 511
<> 135:176b8275d35d 512 /** @defgroup FMC_NORSRAM_Data_Width FMC NOR/SRAM Data Width
bogdanm 92:4fc01daae5a5 513 * @{
bogdanm 92:4fc01daae5a5 514 */
bogdanm 92:4fc01daae5a5 515
<> 135:176b8275d35d 516 #define FMC_NORSRAM_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000)
<> 135:176b8275d35d 517 #define FMC_NORSRAM_MEM_BUS_WIDTH_16 ((uint32_t)FMC_BCRx_MWID_0)
<> 135:176b8275d35d 518 #define FMC_NORSRAM_MEM_BUS_WIDTH_32 ((uint32_t)FMC_BCRx_MWID_1)
<> 135:176b8275d35d 519
bogdanm 92:4fc01daae5a5 520 /**
bogdanm 92:4fc01daae5a5 521 * @}
bogdanm 92:4fc01daae5a5 522 */
bogdanm 92:4fc01daae5a5 523
<> 135:176b8275d35d 524 /** @defgroup FMC_NORSRAM_Flash_Access FMC NOR/SRAM Flash Access
bogdanm 92:4fc01daae5a5 525 * @{
bogdanm 92:4fc01daae5a5 526 */
<> 135:176b8275d35d 527
<> 135:176b8275d35d 528 #define FMC_NORSRAM_FLASH_ACCESS_ENABLE ((uint32_t)FMC_BCRx_FACCEN)
bogdanm 92:4fc01daae5a5 529 #define FMC_NORSRAM_FLASH_ACCESS_DISABLE ((uint32_t)0x00000000)
bogdanm 92:4fc01daae5a5 530 /**
bogdanm 92:4fc01daae5a5 531 * @}
bogdanm 92:4fc01daae5a5 532 */
bogdanm 92:4fc01daae5a5 533
<> 135:176b8275d35d 534 /** @defgroup FMC_Burst_Access_Mode FMC Burst Access Mode
bogdanm 92:4fc01daae5a5 535 * @{
bogdanm 92:4fc01daae5a5 536 */
bogdanm 92:4fc01daae5a5 537
<> 135:176b8275d35d 538 #define FMC_BURST_ACCESS_MODE_DISABLE ((uint32_t)0x00000000)
<> 135:176b8275d35d 539 #define FMC_BURST_ACCESS_MODE_ENABLE ((uint32_t)FMC_BCRx_BURSTEN)
bogdanm 92:4fc01daae5a5 540
bogdanm 92:4fc01daae5a5 541 /**
bogdanm 92:4fc01daae5a5 542 * @}
bogdanm 92:4fc01daae5a5 543 */
bogdanm 92:4fc01daae5a5 544
<> 135:176b8275d35d 545
<> 135:176b8275d35d 546 /** @defgroup FMC_Wait_Signal_Polarity FMC Wait Signal Polarity
bogdanm 92:4fc01daae5a5 547 * @{
bogdanm 92:4fc01daae5a5 548 */
bogdanm 92:4fc01daae5a5 549
<> 135:176b8275d35d 550 #define FMC_WAIT_SIGNAL_POLARITY_LOW ((uint32_t)0x00000000)
<> 135:176b8275d35d 551 #define FMC_WAIT_SIGNAL_POLARITY_HIGH ((uint32_t)FMC_BCRx_WAITPOL)
<> 135:176b8275d35d 552
bogdanm 92:4fc01daae5a5 553 /**
bogdanm 92:4fc01daae5a5 554 * @}
bogdanm 92:4fc01daae5a5 555 */
bogdanm 92:4fc01daae5a5 556
<> 135:176b8275d35d 557 /** @defgroup FMC_Wrap_Mode FMC Wrap Mode
bogdanm 92:4fc01daae5a5 558 * @{
bogdanm 92:4fc01daae5a5 559 */
bogdanm 92:4fc01daae5a5 560
<> 135:176b8275d35d 561 #define FMC_WRAP_MODE_DISABLE ((uint32_t)0x00000000)
<> 135:176b8275d35d 562 #define FMC_WRAP_MODE_ENABLE ((uint32_t)FMC_BCRx_WRAPMOD)
<> 135:176b8275d35d 563
bogdanm 92:4fc01daae5a5 564 /**
bogdanm 92:4fc01daae5a5 565 * @}
bogdanm 92:4fc01daae5a5 566 */
bogdanm 92:4fc01daae5a5 567
<> 135:176b8275d35d 568 /** @defgroup FMC_Wait_Timing FMC Wait Timing
bogdanm 92:4fc01daae5a5 569 * @{
bogdanm 92:4fc01daae5a5 570 */
bogdanm 92:4fc01daae5a5 571
<> 135:176b8275d35d 572 #define FMC_WAIT_TIMING_BEFORE_WS ((uint32_t)0x00000000)
<> 135:176b8275d35d 573 #define FMC_WAIT_TIMING_DURING_WS ((uint32_t)FMC_BCRx_WAITCFG)
bogdanm 92:4fc01daae5a5 574
bogdanm 92:4fc01daae5a5 575 /**
bogdanm 92:4fc01daae5a5 576 * @}
bogdanm 92:4fc01daae5a5 577 */
bogdanm 92:4fc01daae5a5 578
<> 135:176b8275d35d 579 /** @defgroup FMC_Write_Operation FMC Write Operation
bogdanm 92:4fc01daae5a5 580 * @{
bogdanm 92:4fc01daae5a5 581 */
<> 135:176b8275d35d 582
<> 135:176b8275d35d 583 #define FMC_WRITE_OPERATION_DISABLE ((uint32_t)0x00000000)
<> 135:176b8275d35d 584 #define FMC_WRITE_OPERATION_ENABLE ((uint32_t)FMC_BCRx_WREN)
<> 135:176b8275d35d 585
<> 135:176b8275d35d 586 /**
<> 135:176b8275d35d 587 * @}
<> 135:176b8275d35d 588 */
bogdanm 92:4fc01daae5a5 589
<> 135:176b8275d35d 590 /** @defgroup FMC_Wait_Signal FMC Wait Signal
<> 135:176b8275d35d 591 * @{
<> 135:176b8275d35d 592 */
<> 135:176b8275d35d 593
<> 135:176b8275d35d 594 #define FMC_WAIT_SIGNAL_DISABLE ((uint32_t)0x00000000)
<> 135:176b8275d35d 595 #define FMC_WAIT_SIGNAL_ENABLE ((uint32_t)FMC_BCRx_WAITEN)
<> 135:176b8275d35d 596
bogdanm 92:4fc01daae5a5 597 /**
bogdanm 92:4fc01daae5a5 598 * @}
bogdanm 92:4fc01daae5a5 599 */
bogdanm 92:4fc01daae5a5 600
<> 135:176b8275d35d 601 /** @defgroup FMC_Extended_Mode FMC Extended Mode
bogdanm 92:4fc01daae5a5 602 * @{
bogdanm 92:4fc01daae5a5 603 */
bogdanm 92:4fc01daae5a5 604
<> 135:176b8275d35d 605 #define FMC_EXTENDED_MODE_DISABLE ((uint32_t)0x00000000)
<> 135:176b8275d35d 606 #define FMC_EXTENDED_MODE_ENABLE ((uint32_t)FMC_BCRx_EXTMOD)
bogdanm 92:4fc01daae5a5 607
bogdanm 92:4fc01daae5a5 608 /**
bogdanm 92:4fc01daae5a5 609 * @}
bogdanm 92:4fc01daae5a5 610 */
bogdanm 92:4fc01daae5a5 611
<> 135:176b8275d35d 612 /** @defgroup FMC_AsynchronousWait FMC Asynchronous Wait
bogdanm 92:4fc01daae5a5 613 * @{
bogdanm 92:4fc01daae5a5 614 */
<> 135:176b8275d35d 615
<> 135:176b8275d35d 616 #define FMC_ASYNCHRONOUS_WAIT_DISABLE ((uint32_t)0x00000000)
<> 135:176b8275d35d 617 #define FMC_ASYNCHRONOUS_WAIT_ENABLE ((uint32_t)FMC_BCRx_ASYNCWAIT)
<> 135:176b8275d35d 618
bogdanm 92:4fc01daae5a5 619 /**
bogdanm 92:4fc01daae5a5 620 * @}
bogdanm 92:4fc01daae5a5 621 */
bogdanm 92:4fc01daae5a5 622
<> 135:176b8275d35d 623 /** @defgroup FMC_Write_Burst FMC Write Burst
bogdanm 92:4fc01daae5a5 624 * @{
bogdanm 92:4fc01daae5a5 625 */
<> 135:176b8275d35d 626
<> 135:176b8275d35d 627 #define FMC_WRITE_BURST_DISABLE ((uint32_t)0x00000000)
<> 135:176b8275d35d 628 #define FMC_WRITE_BURST_ENABLE ((uint32_t)FMC_BCRx_CBURSTRW)
<> 135:176b8275d35d 629
bogdanm 92:4fc01daae5a5 630 /**
bogdanm 92:4fc01daae5a5 631 * @}
bogdanm 92:4fc01daae5a5 632 */
bogdanm 92:4fc01daae5a5 633
<> 135:176b8275d35d 634 /** @defgroup FMC_Continous_Clock FMC Continous Clock
bogdanm 92:4fc01daae5a5 635 * @{
bogdanm 92:4fc01daae5a5 636 */
<> 135:176b8275d35d 637 #define FMC_CONTINUOUS_CLOCK_SYNC_ONLY ((uint32_t)0x00000000)
<> 135:176b8275d35d 638 #define FMC_CONTINUOUS_CLOCK_SYNC_ASYNC ((uint32_t)FMC_BCR1_CCLKEN)
bogdanm 92:4fc01daae5a5 639 /**
bogdanm 92:4fc01daae5a5 640 * @}
bogdanm 92:4fc01daae5a5 641 */
bogdanm 92:4fc01daae5a5 642
<> 135:176b8275d35d 643 /** @defgroup FMC_Access_Mode FMC Access Mode
bogdanm 92:4fc01daae5a5 644 * @{
bogdanm 92:4fc01daae5a5 645 */
bogdanm 92:4fc01daae5a5 646
bogdanm 92:4fc01daae5a5 647 #define FMC_ACCESS_MODE_A ((uint32_t)0x00000000)
<> 135:176b8275d35d 648 #define FMC_ACCESS_MODE_B ((uint32_t)FMC_BTRx_ACCMOD_0)
<> 135:176b8275d35d 649 #define FMC_ACCESS_MODE_C ((uint32_t)FMC_BTRx_ACCMOD_1)
<> 135:176b8275d35d 650 #define FMC_ACCESS_MODE_D ((uint32_t)(FMC_BTRx_ACCMOD_0 | FMC_BTRx_ACCMOD_1))
bogdanm 92:4fc01daae5a5 651
bogdanm 92:4fc01daae5a5 652 /**
bogdanm 92:4fc01daae5a5 653 * @}
bogdanm 92:4fc01daae5a5 654 */
bogdanm 92:4fc01daae5a5 655
bogdanm 92:4fc01daae5a5 656 /**
bogdanm 92:4fc01daae5a5 657 * @}
bogdanm 92:4fc01daae5a5 658 */
bogdanm 92:4fc01daae5a5 659
<> 135:176b8275d35d 660 /** @defgroup FMC_NAND_Controller FMC NAND and PCCARD Controller
bogdanm 92:4fc01daae5a5 661 * @{
bogdanm 92:4fc01daae5a5 662 */
bogdanm 92:4fc01daae5a5 663
<> 135:176b8275d35d 664 /** @defgroup FMC_NAND_Bank FMC NAND Bank
bogdanm 92:4fc01daae5a5 665 * @{
bogdanm 92:4fc01daae5a5 666 */
<> 135:176b8275d35d 667 #define FMC_NAND_BANK2 ((uint32_t)0x00000010)
<> 135:176b8275d35d 668 #define FMC_NAND_BANK3 ((uint32_t)0x00000100)
<> 135:176b8275d35d 669
bogdanm 92:4fc01daae5a5 670 /**
bogdanm 92:4fc01daae5a5 671 * @}
bogdanm 92:4fc01daae5a5 672 */
bogdanm 92:4fc01daae5a5 673
<> 135:176b8275d35d 674 /** @defgroup FMC_Wait_feature FMC Wait feature
bogdanm 92:4fc01daae5a5 675 * @{
bogdanm 92:4fc01daae5a5 676 */
<> 135:176b8275d35d 677 #define FMC_NAND_PCC_WAIT_FEATURE_DISABLE ((uint32_t)0x00000000)
<> 135:176b8275d35d 678 #define FMC_NAND_PCC_WAIT_FEATURE_ENABLE ((uint32_t)FMC_PCRx_PWAITEN)
bogdanm 92:4fc01daae5a5 679
bogdanm 92:4fc01daae5a5 680 /**
bogdanm 92:4fc01daae5a5 681 * @}
bogdanm 92:4fc01daae5a5 682 */
bogdanm 92:4fc01daae5a5 683
<> 135:176b8275d35d 684 /** @defgroup FMC_PCR_Memory_Type FMC PCR Memory Type
bogdanm 92:4fc01daae5a5 685 * @{
bogdanm 92:4fc01daae5a5 686 */
<> 135:176b8275d35d 687 #define FMC_PCR_MEMORY_TYPE_PCCARD ((uint32_t)0x00000000)
<> 135:176b8275d35d 688 #define FMC_PCR_MEMORY_TYPE_NAND ((uint32_t)FMC_PCRx_PTYP)
bogdanm 92:4fc01daae5a5 689 /**
bogdanm 92:4fc01daae5a5 690 * @}
bogdanm 92:4fc01daae5a5 691 */
bogdanm 92:4fc01daae5a5 692
<> 135:176b8275d35d 693 /** @defgroup FMC_NAND_Data_Width FMC NAND Data Width
bogdanm 92:4fc01daae5a5 694 * @{
bogdanm 92:4fc01daae5a5 695 */
<> 135:176b8275d35d 696 #define FMC_NAND_PCC_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000)
<> 135:176b8275d35d 697 #define FMC_NAND_PCC_MEM_BUS_WIDTH_16 ((uint32_t)FMC_PCRx_PWID_0)
bogdanm 92:4fc01daae5a5 698
bogdanm 92:4fc01daae5a5 699 /**
bogdanm 92:4fc01daae5a5 700 * @}
bogdanm 92:4fc01daae5a5 701 */
bogdanm 92:4fc01daae5a5 702
<> 135:176b8275d35d 703 /** @defgroup FMC_ECC FMC NAND ECC
bogdanm 92:4fc01daae5a5 704 * @{
bogdanm 92:4fc01daae5a5 705 */
<> 135:176b8275d35d 706 #define FMC_NAND_ECC_DISABLE ((uint32_t)0x00000000)
<> 135:176b8275d35d 707 #define FMC_NAND_ECC_ENABLE ((uint32_t)FMC_PCRx_ECCEN)
bogdanm 92:4fc01daae5a5 708
bogdanm 92:4fc01daae5a5 709 /**
bogdanm 92:4fc01daae5a5 710 * @}
bogdanm 92:4fc01daae5a5 711 */
bogdanm 92:4fc01daae5a5 712
<> 135:176b8275d35d 713 /** @defgroup FMC_ECC_Page_Size FMC ECC Page Size
bogdanm 92:4fc01daae5a5 714 * @{
bogdanm 92:4fc01daae5a5 715 */
<> 135:176b8275d35d 716 #define FMC_NAND_ECC_PAGE_SIZE_256BYTE ((uint32_t)0x00000000)
<> 135:176b8275d35d 717 #define FMC_NAND_ECC_PAGE_SIZE_512BYTE ((uint32_t)FMC_PCRx_ECCPS_0)
<> 135:176b8275d35d 718 #define FMC_NAND_ECC_PAGE_SIZE_1024BYTE ((uint32_t)FMC_PCRx_ECCPS_1)
<> 135:176b8275d35d 719 #define FMC_NAND_ECC_PAGE_SIZE_2048BYTE ((uint32_t)FMC_PCRx_ECCPS_0|FMC_PCRx_ECCPS_1)
<> 135:176b8275d35d 720 #define FMC_NAND_ECC_PAGE_SIZE_4096BYTE ((uint32_t)FMC_PCRx_ECCPS_2)
<> 135:176b8275d35d 721 #define FMC_NAND_ECC_PAGE_SIZE_8192BYTE ((uint32_t)FMC_PCRx_ECCPS_0|FMC_PCRx_ECCPS_2)
bogdanm 92:4fc01daae5a5 722
bogdanm 92:4fc01daae5a5 723 /**
bogdanm 92:4fc01daae5a5 724 * @}
<> 135:176b8275d35d 725 */
bogdanm 92:4fc01daae5a5 726
<> 135:176b8275d35d 727 /** @defgroup FMC_Interrupt_definition FMC Interrupt definition
bogdanm 92:4fc01daae5a5 728 * @brief FMC Interrupt definition
bogdanm 92:4fc01daae5a5 729 * @{
<> 135:176b8275d35d 730 */
<> 135:176b8275d35d 731 #define FMC_IT_RISING_EDGE ((uint32_t)FMC_SRx_IREN)
<> 135:176b8275d35d 732 #define FMC_IT_LEVEL ((uint32_t)FMC_SRx_ILEN)
<> 135:176b8275d35d 733 #define FMC_IT_FALLING_EDGE ((uint32_t)FMC_SRx_IFEN)
bogdanm 92:4fc01daae5a5 734
bogdanm 92:4fc01daae5a5 735 /**
bogdanm 92:4fc01daae5a5 736 * @}
bogdanm 92:4fc01daae5a5 737 */
<> 135:176b8275d35d 738
<> 135:176b8275d35d 739 /** @defgroup FMC_Flag_definition FMC Flag definition
bogdanm 92:4fc01daae5a5 740 * @brief FMC Flag definition
bogdanm 92:4fc01daae5a5 741 * @{
<> 135:176b8275d35d 742 */
<> 135:176b8275d35d 743 #define FMC_FLAG_RISING_EDGE ((uint32_t)FMC_SRx_IRS)
<> 135:176b8275d35d 744 #define FMC_FLAG_LEVEL ((uint32_t)FMC_SRx_ILS)
<> 135:176b8275d35d 745 #define FMC_FLAG_FALLING_EDGE ((uint32_t)FMC_SRx_IFS)
<> 135:176b8275d35d 746 #define FMC_FLAG_FEMPT ((uint32_t)FMC_SRx_FEMPT)
bogdanm 92:4fc01daae5a5 747
<> 135:176b8275d35d 748 /**
<> 135:176b8275d35d 749 * @}
<> 135:176b8275d35d 750 */
bogdanm 92:4fc01daae5a5 751
<> 135:176b8275d35d 752 /**
<> 135:176b8275d35d 753 * @}
<> 135:176b8275d35d 754 */
<> 135:176b8275d35d 755
bogdanm 92:4fc01daae5a5 756 /**
bogdanm 92:4fc01daae5a5 757 * @}
bogdanm 92:4fc01daae5a5 758 */
bogdanm 92:4fc01daae5a5 759
bogdanm 92:4fc01daae5a5 760 /* Exported macro ------------------------------------------------------------*/
bogdanm 92:4fc01daae5a5 761
<> 135:176b8275d35d 762 /** @defgroup FMC_Exported_Macros FMC Low Layer Exported Macros
<> 135:176b8275d35d 763 * @{
<> 135:176b8275d35d 764 */
<> 135:176b8275d35d 765
<> 135:176b8275d35d 766 /** @defgroup FMC_NOR_Macros FMC NOR/SRAM Exported Macros
bogdanm 92:4fc01daae5a5 767 * @brief macros to handle NOR device enable/disable and read/write operations
bogdanm 92:4fc01daae5a5 768 * @{
bogdanm 92:4fc01daae5a5 769 */
<> 135:176b8275d35d 770
bogdanm 92:4fc01daae5a5 771 /**
bogdanm 92:4fc01daae5a5 772 * @brief Enable the NORSRAM device access.
<> 135:176b8275d35d 773 * @param __INSTANCE__ FMC_NORSRAM Instance
<> 135:176b8275d35d 774 * @param __BANK__ FMC_NORSRAM Bank
<> 135:176b8275d35d 775 * @retval none
<> 135:176b8275d35d 776 */
<> 135:176b8275d35d 777 #define __FMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) SET_BIT((__INSTANCE__)->BTCR[(__BANK__)], FMC_BCRx_MBKEN)
bogdanm 92:4fc01daae5a5 778
bogdanm 92:4fc01daae5a5 779 /**
bogdanm 92:4fc01daae5a5 780 * @brief Disable the NORSRAM device access.
<> 135:176b8275d35d 781 * @param __INSTANCE__ FMC_NORSRAM Instance
<> 135:176b8275d35d 782 * @param __BANK__ FMC_NORSRAM Bank
<> 135:176b8275d35d 783 * @retval none
<> 135:176b8275d35d 784 */
<> 135:176b8275d35d 785 #define __FMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) CLEAR_BIT((__INSTANCE__)->BTCR[(__BANK__)], FMC_BCRx_MBKEN)
bogdanm 92:4fc01daae5a5 786
bogdanm 92:4fc01daae5a5 787 /**
bogdanm 92:4fc01daae5a5 788 * @}
<> 135:176b8275d35d 789 */
bogdanm 92:4fc01daae5a5 790
<> 135:176b8275d35d 791 /** @defgroup FMC_NAND_Macros FMC NAND Macros
bogdanm 92:4fc01daae5a5 792 * @brief macros to handle NAND device enable/disable
bogdanm 92:4fc01daae5a5 793 * @{
bogdanm 92:4fc01daae5a5 794 */
<> 135:176b8275d35d 795
bogdanm 92:4fc01daae5a5 796 /**
bogdanm 92:4fc01daae5a5 797 * @brief Enable the NAND device access.
<> 135:176b8275d35d 798 * @param __INSTANCE__ FMC_NAND Instance
<> 135:176b8275d35d 799 * @param __BANK__ FMC_NAND Bank
bogdanm 92:4fc01daae5a5 800 * @retval None
<> 135:176b8275d35d 801 */
<> 135:176b8275d35d 802 #define __FMC_NAND_ENABLE(__INSTANCE__, __BANK__) (((__BANK__) == FMC_NAND_BANK2)? SET_BIT((__INSTANCE__)->PCR2, FMC_PCRx_PBKEN): \
<> 135:176b8275d35d 803 SET_BIT((__INSTANCE__)->PCR3, FMC_PCRx_PBKEN))
bogdanm 92:4fc01daae5a5 804
bogdanm 92:4fc01daae5a5 805 /**
bogdanm 92:4fc01daae5a5 806 * @brief Disable the NAND device access.
<> 135:176b8275d35d 807 * @param __INSTANCE__ FMC_NAND Instance
<> 135:176b8275d35d 808 * @param __BANK__ FMC_NAND Bank
bogdanm 92:4fc01daae5a5 809 * @retval None
<> 135:176b8275d35d 810 */
<> 135:176b8275d35d 811 #define __FMC_NAND_DISABLE(__INSTANCE__, __BANK__) (((__BANK__) == FMC_NAND_BANK2)? CLEAR_BIT((__INSTANCE__)->PCR2, FMC_PCRx_PBKEN): \
<> 135:176b8275d35d 812 CLEAR_BIT((__INSTANCE__)->PCR3, FMC_PCRx_PBKEN))
<> 135:176b8275d35d 813
bogdanm 92:4fc01daae5a5 814 /**
bogdanm 92:4fc01daae5a5 815 * @}
<> 135:176b8275d35d 816 */
<> 135:176b8275d35d 817
<> 135:176b8275d35d 818 /** @defgroup FMC_PCCARD_Macros FMC PCCARD Macros
<> 135:176b8275d35d 819 * @brief macros to handle PCCARD read/write operations
bogdanm 92:4fc01daae5a5 820 * @{
bogdanm 92:4fc01daae5a5 821 */
bogdanm 92:4fc01daae5a5 822
bogdanm 92:4fc01daae5a5 823 /**
bogdanm 92:4fc01daae5a5 824 * @brief Enable the PCCARD device access.
<> 135:176b8275d35d 825 * @param __INSTANCE__ FMC_PCCARD Instance
bogdanm 92:4fc01daae5a5 826 * @retval None
<> 135:176b8275d35d 827 */
<> 135:176b8275d35d 828 #define __FMC_PCCARD_ENABLE(__INSTANCE__) SET_BIT((__INSTANCE__)->PCR4, FMC_PCRx_PBKEN)
bogdanm 92:4fc01daae5a5 829
bogdanm 92:4fc01daae5a5 830 /**
bogdanm 92:4fc01daae5a5 831 * @brief Disable the PCCARD device access.
<> 135:176b8275d35d 832 * @param __INSTANCE__ FMC_PCCARD Instance
bogdanm 92:4fc01daae5a5 833 * @retval None
<> 135:176b8275d35d 834 */
<> 135:176b8275d35d 835 #define __FMC_PCCARD_DISABLE(__INSTANCE__) CLEAR_BIT((__INSTANCE__)->PCR4, FMC_PCRx_PBKEN)
bogdanm 92:4fc01daae5a5 836 /**
bogdanm 92:4fc01daae5a5 837 * @}
bogdanm 92:4fc01daae5a5 838 */
<> 135:176b8275d35d 839
<> 135:176b8275d35d 840 /** @defgroup FMC_Interrupt FMC Interrupt
bogdanm 92:4fc01daae5a5 841 * @brief macros to handle FMC interrupts
bogdanm 92:4fc01daae5a5 842 * @{
<> 135:176b8275d35d 843 */
bogdanm 92:4fc01daae5a5 844
bogdanm 92:4fc01daae5a5 845 /**
bogdanm 92:4fc01daae5a5 846 * @brief Enable the NAND device interrupt.
<> 135:176b8275d35d 847 * @param __INSTANCE__ FMC_NAND Instance
<> 135:176b8275d35d 848 * @param __BANK__ FMC_NAND Bank
<> 135:176b8275d35d 849 * @param __INTERRUPT__ FMC_NAND interrupt
bogdanm 92:4fc01daae5a5 850 * This parameter can be any combination of the following values:
<> 135:176b8275d35d 851 * @arg FMC_IT_RISING_EDGE Interrupt rising edge.
<> 135:176b8275d35d 852 * @arg FMC_IT_LEVEL Interrupt level.
<> 135:176b8275d35d 853 * @arg FMC_IT_FALLING_EDGE Interrupt falling edge.
bogdanm 92:4fc01daae5a5 854 * @retval None
<> 135:176b8275d35d 855 */
<> 135:176b8275d35d 856 #define __FMC_NAND_ENABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FMC_NAND_BANK2)? SET_BIT((__INSTANCE__)->SR2, (__INTERRUPT__)): \
<> 135:176b8275d35d 857 SET_BIT((__INSTANCE__)->SR3, (__INTERRUPT__)))
bogdanm 92:4fc01daae5a5 858
bogdanm 92:4fc01daae5a5 859 /**
bogdanm 92:4fc01daae5a5 860 * @brief Disable the NAND device interrupt.
<> 135:176b8275d35d 861 * @param __INSTANCE__ FMC_NAND Instance
<> 135:176b8275d35d 862 * @param __BANK__ FMC_NAND Bank
<> 135:176b8275d35d 863 * @param __INTERRUPT__ FMC_NAND interrupt
bogdanm 92:4fc01daae5a5 864 * This parameter can be any combination of the following values:
<> 135:176b8275d35d 865 * @arg FMC_IT_RISING_EDGE Interrupt rising edge.
<> 135:176b8275d35d 866 * @arg FMC_IT_LEVEL Interrupt level.
<> 135:176b8275d35d 867 * @arg FMC_IT_FALLING_EDGE Interrupt falling edge.
bogdanm 92:4fc01daae5a5 868 * @retval None
bogdanm 92:4fc01daae5a5 869 */
<> 135:176b8275d35d 870 #define __FMC_NAND_DISABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FMC_NAND_BANK2)? CLEAR_BIT((__INSTANCE__)->SR2, (__INTERRUPT__)): \
<> 135:176b8275d35d 871 CLEAR_BIT((__INSTANCE__)->SR3, (__INTERRUPT__)))
<> 135:176b8275d35d 872
bogdanm 92:4fc01daae5a5 873 /**
bogdanm 92:4fc01daae5a5 874 * @brief Get flag status of the NAND device.
<> 135:176b8275d35d 875 * @param __INSTANCE__ FMC_NAND Instance
<> 135:176b8275d35d 876 * @param __BANK__ FMC_NAND Bank
<> 135:176b8275d35d 877 * @param __FLAG__ FMC_NAND flag
bogdanm 92:4fc01daae5a5 878 * This parameter can be any combination of the following values:
<> 135:176b8275d35d 879 * @arg FMC_FLAG_RISING_EDGE Interrupt rising edge flag.
<> 135:176b8275d35d 880 * @arg FMC_FLAG_LEVEL Interrupt level edge flag.
<> 135:176b8275d35d 881 * @arg FMC_FLAG_FALLING_EDGE Interrupt falling edge flag.
<> 135:176b8275d35d 882 * @arg FMC_FLAG_FEMPT FIFO empty flag.
bogdanm 92:4fc01daae5a5 883 * @retval The state of FLAG (SET or RESET).
bogdanm 92:4fc01daae5a5 884 */
bogdanm 92:4fc01daae5a5 885 #define __FMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FMC_NAND_BANK2)? (((__INSTANCE__)->SR2 &(__FLAG__)) == (__FLAG__)): \
<> 135:176b8275d35d 886 (((__INSTANCE__)->SR3 &(__FLAG__)) == (__FLAG__)))
<> 135:176b8275d35d 887
bogdanm 92:4fc01daae5a5 888 /**
bogdanm 92:4fc01daae5a5 889 * @brief Clear flag status of the NAND device.
<> 135:176b8275d35d 890 * @param __INSTANCE__ FMC_NAND Instance
<> 135:176b8275d35d 891 * @param __BANK__ FMC_NAND Bank
<> 135:176b8275d35d 892 * @param __FLAG__ FMC_NAND flag
bogdanm 92:4fc01daae5a5 893 * This parameter can be any combination of the following values:
<> 135:176b8275d35d 894 * @arg FMC_FLAG_RISING_EDGE Interrupt rising edge flag.
<> 135:176b8275d35d 895 * @arg FMC_FLAG_LEVEL Interrupt level edge flag.
<> 135:176b8275d35d 896 * @arg FMC_FLAG_FALLING_EDGE Interrupt falling edge flag.
<> 135:176b8275d35d 897 * @arg FMC_FLAG_FEMPT FIFO empty flag.
bogdanm 92:4fc01daae5a5 898 * @retval None
bogdanm 92:4fc01daae5a5 899 */
<> 135:176b8275d35d 900 #define __FMC_NAND_CLEAR_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FMC_NAND_BANK2)? CLEAR_BIT((__INSTANCE__)->SR2, (__FLAG__)): \
<> 135:176b8275d35d 901 CLEAR_BIT((__INSTANCE__)->SR3, (__FLAG__)))
<> 135:176b8275d35d 902
bogdanm 92:4fc01daae5a5 903 /**
bogdanm 92:4fc01daae5a5 904 * @brief Enable the PCCARD device interrupt.
<> 135:176b8275d35d 905 * @param __INSTANCE__ FMC_PCCARD Instance
<> 135:176b8275d35d 906 * @param __INTERRUPT__ FMC_PCCARD interrupt
bogdanm 92:4fc01daae5a5 907 * This parameter can be any combination of the following values:
<> 135:176b8275d35d 908 * @arg FMC_IT_RISING_EDGE Interrupt rising edge.
<> 135:176b8275d35d 909 * @arg FMC_IT_LEVEL Interrupt level.
<> 135:176b8275d35d 910 * @arg FMC_IT_FALLING_EDGE Interrupt falling edge.
bogdanm 92:4fc01daae5a5 911 * @retval None
<> 135:176b8275d35d 912 */
<> 135:176b8275d35d 913 #define __FMC_PCCARD_ENABLE_IT(__INSTANCE__, __INTERRUPT__) SET_BIT((__INSTANCE__)->SR4, (__INTERRUPT__))
bogdanm 92:4fc01daae5a5 914
bogdanm 92:4fc01daae5a5 915 /**
bogdanm 92:4fc01daae5a5 916 * @brief Disable the PCCARD device interrupt.
<> 135:176b8275d35d 917 * @param __INSTANCE__ FMC_PCCARD Instance
<> 135:176b8275d35d 918 * @param __INTERRUPT__ FMC_PCCARD interrupt
bogdanm 92:4fc01daae5a5 919 * This parameter can be any combination of the following values:
<> 135:176b8275d35d 920 * @arg FMC_IT_RISING_EDGE Interrupt rising edge.
<> 135:176b8275d35d 921 * @arg FMC_IT_LEVEL Interrupt level.
<> 135:176b8275d35d 922 * @arg FMC_IT_FALLING_EDGE Interrupt falling edge.
bogdanm 92:4fc01daae5a5 923 * @retval None
<> 135:176b8275d35d 924 */
<> 135:176b8275d35d 925 #define __FMC_PCCARD_DISABLE_IT(__INSTANCE__, __INTERRUPT__) CLEAR_BIT((__INSTANCE__)->SR4, (__INTERRUPT__))
bogdanm 92:4fc01daae5a5 926
bogdanm 92:4fc01daae5a5 927 /**
bogdanm 92:4fc01daae5a5 928 * @brief Get flag status of the PCCARD device.
<> 135:176b8275d35d 929 * @param __INSTANCE__ FMC_PCCARD Instance
<> 135:176b8275d35d 930 * @param __FLAG__ FMC_PCCARD flag
bogdanm 92:4fc01daae5a5 931 * This parameter can be any combination of the following values:
<> 135:176b8275d35d 932 * @arg FMC_FLAG_RISING_EDGE Interrupt rising edge flag.
<> 135:176b8275d35d 933 * @arg FMC_FLAG_LEVEL Interrupt level edge flag.
<> 135:176b8275d35d 934 * @arg FMC_FLAG_FALLING_EDGE Interrupt falling edge flag.
<> 135:176b8275d35d 935 * @arg FMC_FLAG_FEMPT FIFO empty flag.
bogdanm 92:4fc01daae5a5 936 * @retval The state of FLAG (SET or RESET).
bogdanm 92:4fc01daae5a5 937 */
bogdanm 92:4fc01daae5a5 938 #define __FMC_PCCARD_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->SR4 &(__FLAG__)) == (__FLAG__))
bogdanm 92:4fc01daae5a5 939
bogdanm 92:4fc01daae5a5 940 /**
bogdanm 92:4fc01daae5a5 941 * @brief Clear flag status of the PCCARD device.
<> 135:176b8275d35d 942 * @param __INSTANCE__ FMC_PCCARD Instance
<> 135:176b8275d35d 943 * @param __FLAG__ FMC_PCCARD flag
bogdanm 92:4fc01daae5a5 944 * This parameter can be any combination of the following values:
<> 135:176b8275d35d 945 * @arg FMC_FLAG_RISING_EDGE Interrupt rising edge flag.
<> 135:176b8275d35d 946 * @arg FMC_FLAG_LEVEL Interrupt level edge flag.
<> 135:176b8275d35d 947 * @arg FMC_FLAG_FALLING_EDGE Interrupt falling edge flag.
<> 135:176b8275d35d 948 * @arg FMC_FLAG_FEMPT FIFO empty flag.
bogdanm 92:4fc01daae5a5 949 * @retval None
bogdanm 92:4fc01daae5a5 950 */
<> 135:176b8275d35d 951 #define __FMC_PCCARD_CLEAR_FLAG(__INSTANCE__, __FLAG__) CLEAR_BIT((__INSTANCE__)->SR4, (__FLAG__))
<> 135:176b8275d35d 952
bogdanm 92:4fc01daae5a5 953 /**
bogdanm 92:4fc01daae5a5 954 * @}
<> 135:176b8275d35d 955 */
<> 135:176b8275d35d 956
<> 135:176b8275d35d 957
<> 135:176b8275d35d 958 /**
<> 135:176b8275d35d 959 * @}
<> 135:176b8275d35d 960 */
bogdanm 92:4fc01daae5a5 961
bogdanm 92:4fc01daae5a5 962 /* Exported functions --------------------------------------------------------*/
bogdanm 92:4fc01daae5a5 963
<> 135:176b8275d35d 964 /** @addtogroup FMC_LL_Exported_Functions
<> 135:176b8275d35d 965 * @{
<> 135:176b8275d35d 966 */
<> 135:176b8275d35d 967
<> 135:176b8275d35d 968 /** @addtogroup FMC_NORSRAM
<> 135:176b8275d35d 969 * @{
<> 135:176b8275d35d 970 */
<> 135:176b8275d35d 971
<> 135:176b8275d35d 972 /** @addtogroup FMC_NORSRAM_Group1
<> 135:176b8275d35d 973 * @{
<> 135:176b8275d35d 974 */
<> 135:176b8275d35d 975
<> 135:176b8275d35d 976 /* FMC_NORSRAM Controller functions ******************************************/
bogdanm 92:4fc01daae5a5 977 /* Initialization/de-initialization functions */
bogdanm 92:4fc01daae5a5 978 HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_InitTypeDef *Init);
bogdanm 92:4fc01daae5a5 979 HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank);
bogdanm 92:4fc01daae5a5 980 HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode);
bogdanm 92:4fc01daae5a5 981 HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank);
bogdanm 92:4fc01daae5a5 982
<> 135:176b8275d35d 983 /**
<> 135:176b8275d35d 984 * @}
<> 135:176b8275d35d 985 */
<> 135:176b8275d35d 986
<> 135:176b8275d35d 987 /** @addtogroup FMC_NORSRAM_Group2
<> 135:176b8275d35d 988 * @{
<> 135:176b8275d35d 989 */
<> 135:176b8275d35d 990
bogdanm 92:4fc01daae5a5 991 /* FMC_NORSRAM Control functions */
bogdanm 92:4fc01daae5a5 992 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank);
bogdanm 92:4fc01daae5a5 993 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank);
bogdanm 92:4fc01daae5a5 994
<> 135:176b8275d35d 995 /**
<> 135:176b8275d35d 996 * @}
<> 135:176b8275d35d 997 */
<> 135:176b8275d35d 998
<> 135:176b8275d35d 999 /**
<> 135:176b8275d35d 1000 * @}
<> 135:176b8275d35d 1001 */
<> 135:176b8275d35d 1002
<> 135:176b8275d35d 1003 /** @addtogroup FMC_NAND
<> 135:176b8275d35d 1004 * @{
<> 135:176b8275d35d 1005 */
<> 135:176b8275d35d 1006
bogdanm 92:4fc01daae5a5 1007 /* FMC_NAND Controller functions **********************************************/
bogdanm 92:4fc01daae5a5 1008 /* Initialization/de-initialization functions */
<> 135:176b8275d35d 1009 /** @addtogroup FMC_NAND_Exported_Functions_Group1
<> 135:176b8275d35d 1010 * @{
<> 135:176b8275d35d 1011 */
<> 135:176b8275d35d 1012
bogdanm 92:4fc01daae5a5 1013 HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init);
bogdanm 92:4fc01daae5a5 1014 HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
bogdanm 92:4fc01daae5a5 1015 HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
bogdanm 92:4fc01daae5a5 1016 HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank);
bogdanm 92:4fc01daae5a5 1017
<> 135:176b8275d35d 1018 /**
<> 135:176b8275d35d 1019 * @}
<> 135:176b8275d35d 1020 */
<> 135:176b8275d35d 1021
bogdanm 92:4fc01daae5a5 1022 /* FMC_NAND Control functions */
<> 135:176b8275d35d 1023 /** @addtogroup FMC_NAND_Exported_Functions_Group2
<> 135:176b8275d35d 1024 * @{
<> 135:176b8275d35d 1025 */
<> 135:176b8275d35d 1026
bogdanm 92:4fc01daae5a5 1027 HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank);
bogdanm 92:4fc01daae5a5 1028 HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank);
bogdanm 92:4fc01daae5a5 1029 HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout);
bogdanm 92:4fc01daae5a5 1030
<> 135:176b8275d35d 1031 /**
<> 135:176b8275d35d 1032 * @}
<> 135:176b8275d35d 1033 */
<> 135:176b8275d35d 1034
<> 135:176b8275d35d 1035 /**
<> 135:176b8275d35d 1036 * @}
<> 135:176b8275d35d 1037 */
<> 135:176b8275d35d 1038
<> 135:176b8275d35d 1039 /** @addtogroup FMC_PCCARD
<> 135:176b8275d35d 1040 * @{
<> 135:176b8275d35d 1041 */
<> 135:176b8275d35d 1042
bogdanm 92:4fc01daae5a5 1043 /* FMC_PCCARD Controller functions ********************************************/
bogdanm 92:4fc01daae5a5 1044 /* Initialization/de-initialization functions */
<> 135:176b8275d35d 1045 /** @addtogroup FMC_PCCARD_Exported_Functions_Group1
<> 135:176b8275d35d 1046 * @{
<> 135:176b8275d35d 1047 */
<> 135:176b8275d35d 1048
bogdanm 92:4fc01daae5a5 1049 HAL_StatusTypeDef FMC_PCCARD_Init(FMC_PCCARD_TypeDef *Device, FMC_PCCARD_InitTypeDef *Init);
bogdanm 92:4fc01daae5a5 1050 HAL_StatusTypeDef FMC_PCCARD_CommonSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing);
bogdanm 92:4fc01daae5a5 1051 HAL_StatusTypeDef FMC_PCCARD_AttributeSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing);
bogdanm 92:4fc01daae5a5 1052 HAL_StatusTypeDef FMC_PCCARD_IOSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing);
bogdanm 92:4fc01daae5a5 1053 HAL_StatusTypeDef FMC_PCCARD_DeInit(FMC_PCCARD_TypeDef *Device);
bogdanm 92:4fc01daae5a5 1054
bogdanm 92:4fc01daae5a5 1055 /**
bogdanm 92:4fc01daae5a5 1056 * @}
<> 135:176b8275d35d 1057 */
<> 135:176b8275d35d 1058
<> 135:176b8275d35d 1059 /**
<> 135:176b8275d35d 1060 * @}
<> 135:176b8275d35d 1061 */
bogdanm 92:4fc01daae5a5 1062
bogdanm 92:4fc01daae5a5 1063 /**
bogdanm 92:4fc01daae5a5 1064 * @}
bogdanm 92:4fc01daae5a5 1065 */
<> 135:176b8275d35d 1066
<> 135:176b8275d35d 1067 /**
<> 135:176b8275d35d 1068 * @}
<> 135:176b8275d35d 1069 */
<> 135:176b8275d35d 1070
<> 135:176b8275d35d 1071 #endif /* FMC_BANK1 */
<> 135:176b8275d35d 1072
<> 135:176b8275d35d 1073 /**
<> 135:176b8275d35d 1074 * @}
<> 135:176b8275d35d 1075 */
<> 135:176b8275d35d 1076
bogdanm 92:4fc01daae5a5 1077 #ifdef __cplusplus
bogdanm 92:4fc01daae5a5 1078 }
bogdanm 92:4fc01daae5a5 1079 #endif
bogdanm 92:4fc01daae5a5 1080
bogdanm 92:4fc01daae5a5 1081 #endif /* __STM32F3xx_LL_FMC_H */
bogdanm 92:4fc01daae5a5 1082
bogdanm 92:4fc01daae5a5 1083 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
<> 135:176b8275d35d 1084