mbed official / mbed

The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

Dependents:   hello SerialTestv11 SerialTestv12 Sierpinski ... more

mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_NUCLEO_F401RE/core_cm0plus.h@110:165afa46840b, 2015-11-25 (annotated)

Committer:
Kojto
Date:
Wed Nov 25 13:21:40 2015 +0000
Revision:
110:165afa46840b
Parent:
77:869cf507173a
Child:
128:9bcdf88f62b0
Release 110  of the mbed library



Changes:

- new platforms - STM32F410R, DISCO_F429ZI, DISCO_F469NI

- Nucleo L476 - gcc and uvision template

- k22,k64f targets - ADC channels A addition

- EFM32 - bugfixes in sleep, serial and spi

- Delta DFCM NNN40 - pinnames update

Who changed what in which revision?

UserRevisionLine numberNew contents of line
emilmont 77:869cf507173a 1 /**************************************************************************//**
emilmont 77:869cf507173a 2 * @file core_cm0plus.h
emilmont 77:869cf507173a 3 * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
Kojto 110:165afa46840b 4 * @version V4.10
Kojto 110:165afa46840b 5 * @date 18. March 2015
emilmont 77:869cf507173a 6 *
emilmont 77:869cf507173a 7 * @note
emilmont 77:869cf507173a 8 *
emilmont 77:869cf507173a 9 ******************************************************************************/
Kojto 110:165afa46840b 10 /* Copyright (c) 2009 - 2015 ARM LIMITED
emilmont 77:869cf507173a 11
emilmont 77:869cf507173a 12 All rights reserved.
emilmont 77:869cf507173a 13 Redistribution and use in source and binary forms, with or without
emilmont 77:869cf507173a 14 modification, are permitted provided that the following conditions are met:
emilmont 77:869cf507173a 15 - Redistributions of source code must retain the above copyright
emilmont 77:869cf507173a 16 notice, this list of conditions and the following disclaimer.
emilmont 77:869cf507173a 17 - Redistributions in binary form must reproduce the above copyright
emilmont 77:869cf507173a 18 notice, this list of conditions and the following disclaimer in the
emilmont 77:869cf507173a 19 documentation and/or other materials provided with the distribution.
emilmont 77:869cf507173a 20 - Neither the name of ARM nor the names of its contributors may be used
emilmont 77:869cf507173a 21 to endorse or promote products derived from this software without
emilmont 77:869cf507173a 22 specific prior written permission.
emilmont 77:869cf507173a 23 *
emilmont 77:869cf507173a 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
emilmont 77:869cf507173a 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
emilmont 77:869cf507173a 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
emilmont 77:869cf507173a 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
emilmont 77:869cf507173a 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
emilmont 77:869cf507173a 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
emilmont 77:869cf507173a 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
emilmont 77:869cf507173a 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
emilmont 77:869cf507173a 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
emilmont 77:869cf507173a 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
emilmont 77:869cf507173a 34 POSSIBILITY OF SUCH DAMAGE.
emilmont 77:869cf507173a 35 ---------------------------------------------------------------------------*/
emilmont 77:869cf507173a 36
emilmont 77:869cf507173a 37
emilmont 77:869cf507173a 38 #if defined ( __ICCARM__ )
emilmont 77:869cf507173a 39 #pragma system_include /* treat file as system include file for MISRA check */
emilmont 77:869cf507173a 40 #endif
emilmont 77:869cf507173a 41
Kojto 110:165afa46840b 42 #ifndef __CORE_CM0PLUS_H_GENERIC
Kojto 110:165afa46840b 43 #define __CORE_CM0PLUS_H_GENERIC
Kojto 110:165afa46840b 44
emilmont 77:869cf507173a 45 #ifdef __cplusplus
emilmont 77:869cf507173a 46 extern "C" {
emilmont 77:869cf507173a 47 #endif
emilmont 77:869cf507173a 48
emilmont 77:869cf507173a 49 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
emilmont 77:869cf507173a 50 CMSIS violates the following MISRA-C:2004 rules:
emilmont 77:869cf507173a 51
emilmont 77:869cf507173a 52 \li Required Rule 8.5, object/function definition in header file.<br>
emilmont 77:869cf507173a 53 Function definitions in header files are used to allow 'inlining'.
emilmont 77:869cf507173a 54
emilmont 77:869cf507173a 55 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
emilmont 77:869cf507173a 56 Unions are used for effective representation of core registers.
emilmont 77:869cf507173a 57
emilmont 77:869cf507173a 58 \li Advisory Rule 19.7, Function-like macro defined.<br>
emilmont 77:869cf507173a 59 Function-like macros are used to allow more efficient code.
emilmont 77:869cf507173a 60 */
emilmont 77:869cf507173a 61
emilmont 77:869cf507173a 62
emilmont 77:869cf507173a 63 /*******************************************************************************
emilmont 77:869cf507173a 64 * CMSIS definitions
emilmont 77:869cf507173a 65 ******************************************************************************/
emilmont 77:869cf507173a 66 /** \ingroup Cortex-M0+
emilmont 77:869cf507173a 67 @{
emilmont 77:869cf507173a 68 */
emilmont 77:869cf507173a 69
emilmont 77:869cf507173a 70 /* CMSIS CM0P definitions */
Kojto 110:165afa46840b 71 #define __CM0PLUS_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */
Kojto 110:165afa46840b 72 #define __CM0PLUS_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */
emilmont 77:869cf507173a 73 #define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16) | \
emilmont 77:869cf507173a 74 __CM0PLUS_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */
emilmont 77:869cf507173a 75
emilmont 77:869cf507173a 76 #define __CORTEX_M (0x00) /*!< Cortex-M Core */
emilmont 77:869cf507173a 77
emilmont 77:869cf507173a 78
emilmont 77:869cf507173a 79 #if defined ( __CC_ARM )
emilmont 77:869cf507173a 80 #define __ASM __asm /*!< asm keyword for ARM Compiler */
emilmont 77:869cf507173a 81 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
emilmont 77:869cf507173a 82 #define __STATIC_INLINE static __inline
emilmont 77:869cf507173a 83
Kojto 110:165afa46840b 84 #elif defined ( __GNUC__ )
Kojto 110:165afa46840b 85 #define __ASM __asm /*!< asm keyword for GNU Compiler */
Kojto 110:165afa46840b 86 #define __INLINE inline /*!< inline keyword for GNU Compiler */
Kojto 110:165afa46840b 87 #define __STATIC_INLINE static inline
Kojto 110:165afa46840b 88
emilmont 77:869cf507173a 89 #elif defined ( __ICCARM__ )
emilmont 77:869cf507173a 90 #define __ASM __asm /*!< asm keyword for IAR Compiler */
emilmont 77:869cf507173a 91 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
emilmont 77:869cf507173a 92 #define __STATIC_INLINE static inline
emilmont 77:869cf507173a 93
Kojto 110:165afa46840b 94 #elif defined ( __TMS470__ )
Kojto 110:165afa46840b 95 #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
emilmont 77:869cf507173a 96 #define __STATIC_INLINE static inline
emilmont 77:869cf507173a 97
emilmont 77:869cf507173a 98 #elif defined ( __TASKING__ )
emilmont 77:869cf507173a 99 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
emilmont 77:869cf507173a 100 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
emilmont 77:869cf507173a 101 #define __STATIC_INLINE static inline
emilmont 77:869cf507173a 102
Kojto 110:165afa46840b 103 #elif defined ( __CSMC__ )
Kojto 110:165afa46840b 104 #define __packed
Kojto 110:165afa46840b 105 #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
Kojto 110:165afa46840b 106 #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */
Kojto 110:165afa46840b 107 #define __STATIC_INLINE static inline
Kojto 110:165afa46840b 108
emilmont 77:869cf507173a 109 #endif
emilmont 77:869cf507173a 110
Kojto 110:165afa46840b 111 /** __FPU_USED indicates whether an FPU is used or not.
Kojto 110:165afa46840b 112 This core does not support an FPU at all
emilmont 77:869cf507173a 113 */
emilmont 77:869cf507173a 114 #define __FPU_USED 0
emilmont 77:869cf507173a 115
emilmont 77:869cf507173a 116 #if defined ( __CC_ARM )
emilmont 77:869cf507173a 117 #if defined __TARGET_FPU_VFP
emilmont 77:869cf507173a 118 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
emilmont 77:869cf507173a 119 #endif
emilmont 77:869cf507173a 120
Kojto 110:165afa46840b 121 #elif defined ( __GNUC__ )
Kojto 110:165afa46840b 122 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
Kojto 110:165afa46840b 123 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 110:165afa46840b 124 #endif
Kojto 110:165afa46840b 125
emilmont 77:869cf507173a 126 #elif defined ( __ICCARM__ )
emilmont 77:869cf507173a 127 #if defined __ARMVFP__
emilmont 77:869cf507173a 128 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
emilmont 77:869cf507173a 129 #endif
emilmont 77:869cf507173a 130
Kojto 110:165afa46840b 131 #elif defined ( __TMS470__ )
Kojto 110:165afa46840b 132 #if defined __TI__VFP_SUPPORT____
emilmont 77:869cf507173a 133 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
emilmont 77:869cf507173a 134 #endif
emilmont 77:869cf507173a 135
emilmont 77:869cf507173a 136 #elif defined ( __TASKING__ )
emilmont 77:869cf507173a 137 #if defined __FPU_VFP__
emilmont 77:869cf507173a 138 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
emilmont 77:869cf507173a 139 #endif
Kojto 110:165afa46840b 140
Kojto 110:165afa46840b 141 #elif defined ( __CSMC__ ) /* Cosmic */
Kojto 110:165afa46840b 142 #if ( __CSMC__ & 0x400) // FPU present for parser
Kojto 110:165afa46840b 143 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 110:165afa46840b 144 #endif
emilmont 77:869cf507173a 145 #endif
emilmont 77:869cf507173a 146
emilmont 77:869cf507173a 147 #include <stdint.h> /* standard types definitions */
emilmont 77:869cf507173a 148 #include <core_cmInstr.h> /* Core Instruction Access */
emilmont 77:869cf507173a 149 #include <core_cmFunc.h> /* Core Function Access */
emilmont 77:869cf507173a 150
Kojto 110:165afa46840b 151 #ifdef __cplusplus
Kojto 110:165afa46840b 152 }
Kojto 110:165afa46840b 153 #endif
Kojto 110:165afa46840b 154
emilmont 77:869cf507173a 155 #endif /* __CORE_CM0PLUS_H_GENERIC */
emilmont 77:869cf507173a 156
emilmont 77:869cf507173a 157 #ifndef __CMSIS_GENERIC
emilmont 77:869cf507173a 158
emilmont 77:869cf507173a 159 #ifndef __CORE_CM0PLUS_H_DEPENDANT
emilmont 77:869cf507173a 160 #define __CORE_CM0PLUS_H_DEPENDANT
emilmont 77:869cf507173a 161
Kojto 110:165afa46840b 162 #ifdef __cplusplus
Kojto 110:165afa46840b 163 extern "C" {
Kojto 110:165afa46840b 164 #endif
Kojto 110:165afa46840b 165
emilmont 77:869cf507173a 166 /* check device defines and use defaults */
emilmont 77:869cf507173a 167 #if defined __CHECK_DEVICE_DEFINES
emilmont 77:869cf507173a 168 #ifndef __CM0PLUS_REV
emilmont 77:869cf507173a 169 #define __CM0PLUS_REV 0x0000
emilmont 77:869cf507173a 170 #warning "__CM0PLUS_REV not defined in device header file; using default!"
emilmont 77:869cf507173a 171 #endif
emilmont 77:869cf507173a 172
emilmont 77:869cf507173a 173 #ifndef __MPU_PRESENT
emilmont 77:869cf507173a 174 #define __MPU_PRESENT 0
emilmont 77:869cf507173a 175 #warning "__MPU_PRESENT not defined in device header file; using default!"
emilmont 77:869cf507173a 176 #endif
emilmont 77:869cf507173a 177
emilmont 77:869cf507173a 178 #ifndef __VTOR_PRESENT
emilmont 77:869cf507173a 179 #define __VTOR_PRESENT 0
emilmont 77:869cf507173a 180 #warning "__VTOR_PRESENT not defined in device header file; using default!"
emilmont 77:869cf507173a 181 #endif
emilmont 77:869cf507173a 182
emilmont 77:869cf507173a 183 #ifndef __NVIC_PRIO_BITS
emilmont 77:869cf507173a 184 #define __NVIC_PRIO_BITS 2
emilmont 77:869cf507173a 185 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
emilmont 77:869cf507173a 186 #endif
emilmont 77:869cf507173a 187
emilmont 77:869cf507173a 188 #ifndef __Vendor_SysTickConfig
emilmont 77:869cf507173a 189 #define __Vendor_SysTickConfig 0
emilmont 77:869cf507173a 190 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
emilmont 77:869cf507173a 191 #endif
emilmont 77:869cf507173a 192 #endif
emilmont 77:869cf507173a 193
emilmont 77:869cf507173a 194 /* IO definitions (access restrictions to peripheral registers) */
emilmont 77:869cf507173a 195 /**
emilmont 77:869cf507173a 196 \defgroup CMSIS_glob_defs CMSIS Global Defines
emilmont 77:869cf507173a 197
emilmont 77:869cf507173a 198 <strong>IO Type Qualifiers</strong> are used
emilmont 77:869cf507173a 199 \li to specify the access to peripheral variables.
emilmont 77:869cf507173a 200 \li for automatic generation of peripheral register debug information.
emilmont 77:869cf507173a 201 */
emilmont 77:869cf507173a 202 #ifdef __cplusplus
emilmont 77:869cf507173a 203 #define __I volatile /*!< Defines 'read only' permissions */
emilmont 77:869cf507173a 204 #else
emilmont 77:869cf507173a 205 #define __I volatile const /*!< Defines 'read only' permissions */
emilmont 77:869cf507173a 206 #endif
emilmont 77:869cf507173a 207 #define __O volatile /*!< Defines 'write only' permissions */
emilmont 77:869cf507173a 208 #define __IO volatile /*!< Defines 'read / write' permissions */
emilmont 77:869cf507173a 209
emilmont 77:869cf507173a 210 /*@} end of group Cortex-M0+ */
emilmont 77:869cf507173a 211
emilmont 77:869cf507173a 212
emilmont 77:869cf507173a 213
emilmont 77:869cf507173a 214 /*******************************************************************************
emilmont 77:869cf507173a 215 * Register Abstraction
emilmont 77:869cf507173a 216 Core Register contain:
emilmont 77:869cf507173a 217 - Core Register
emilmont 77:869cf507173a 218 - Core NVIC Register
emilmont 77:869cf507173a 219 - Core SCB Register
emilmont 77:869cf507173a 220 - Core SysTick Register
emilmont 77:869cf507173a 221 - Core MPU Register
emilmont 77:869cf507173a 222 ******************************************************************************/
emilmont 77:869cf507173a 223 /** \defgroup CMSIS_core_register Defines and Type Definitions
emilmont 77:869cf507173a 224 \brief Type definitions and defines for Cortex-M processor based devices.
emilmont 77:869cf507173a 225 */
emilmont 77:869cf507173a 226
emilmont 77:869cf507173a 227 /** \ingroup CMSIS_core_register
emilmont 77:869cf507173a 228 \defgroup CMSIS_CORE Status and Control Registers
emilmont 77:869cf507173a 229 \brief Core Register type definitions.
emilmont 77:869cf507173a 230 @{
emilmont 77:869cf507173a 231 */
emilmont 77:869cf507173a 232
emilmont 77:869cf507173a 233 /** \brief Union type to access the Application Program Status Register (APSR).
emilmont 77:869cf507173a 234 */
emilmont 77:869cf507173a 235 typedef union
emilmont 77:869cf507173a 236 {
emilmont 77:869cf507173a 237 struct
emilmont 77:869cf507173a 238 {
Kojto 110:165afa46840b 239 uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
emilmont 77:869cf507173a 240 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
emilmont 77:869cf507173a 241 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
emilmont 77:869cf507173a 242 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
emilmont 77:869cf507173a 243 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
emilmont 77:869cf507173a 244 } b; /*!< Structure used for bit access */
emilmont 77:869cf507173a 245 uint32_t w; /*!< Type used for word access */
emilmont 77:869cf507173a 246 } APSR_Type;
emilmont 77:869cf507173a 247
Kojto 110:165afa46840b 248 /* APSR Register Definitions */
Kojto 110:165afa46840b 249 #define APSR_N_Pos 31 /*!< APSR: N Position */
Kojto 110:165afa46840b 250 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
Kojto 110:165afa46840b 251
Kojto 110:165afa46840b 252 #define APSR_Z_Pos 30 /*!< APSR: Z Position */
Kojto 110:165afa46840b 253 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
Kojto 110:165afa46840b 254
Kojto 110:165afa46840b 255 #define APSR_C_Pos 29 /*!< APSR: C Position */
Kojto 110:165afa46840b 256 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
Kojto 110:165afa46840b 257
Kojto 110:165afa46840b 258 #define APSR_V_Pos 28 /*!< APSR: V Position */
Kojto 110:165afa46840b 259 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
Kojto 110:165afa46840b 260
emilmont 77:869cf507173a 261
emilmont 77:869cf507173a 262 /** \brief Union type to access the Interrupt Program Status Register (IPSR).
emilmont 77:869cf507173a 263 */
emilmont 77:869cf507173a 264 typedef union
emilmont 77:869cf507173a 265 {
emilmont 77:869cf507173a 266 struct
emilmont 77:869cf507173a 267 {
emilmont 77:869cf507173a 268 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
emilmont 77:869cf507173a 269 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
emilmont 77:869cf507173a 270 } b; /*!< Structure used for bit access */
emilmont 77:869cf507173a 271 uint32_t w; /*!< Type used for word access */
emilmont 77:869cf507173a 272 } IPSR_Type;
emilmont 77:869cf507173a 273
Kojto 110:165afa46840b 274 /* IPSR Register Definitions */
Kojto 110:165afa46840b 275 #define IPSR_ISR_Pos 0 /*!< IPSR: ISR Position */
Kojto 110:165afa46840b 276 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
Kojto 110:165afa46840b 277
emilmont 77:869cf507173a 278
emilmont 77:869cf507173a 279 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
emilmont 77:869cf507173a 280 */
emilmont 77:869cf507173a 281 typedef union
emilmont 77:869cf507173a 282 {
emilmont 77:869cf507173a 283 struct
emilmont 77:869cf507173a 284 {
emilmont 77:869cf507173a 285 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
emilmont 77:869cf507173a 286 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
emilmont 77:869cf507173a 287 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
Kojto 110:165afa46840b 288 uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
emilmont 77:869cf507173a 289 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
emilmont 77:869cf507173a 290 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
emilmont 77:869cf507173a 291 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
emilmont 77:869cf507173a 292 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
emilmont 77:869cf507173a 293 } b; /*!< Structure used for bit access */
emilmont 77:869cf507173a 294 uint32_t w; /*!< Type used for word access */
emilmont 77:869cf507173a 295 } xPSR_Type;
emilmont 77:869cf507173a 296
Kojto 110:165afa46840b 297 /* xPSR Register Definitions */
Kojto 110:165afa46840b 298 #define xPSR_N_Pos 31 /*!< xPSR: N Position */
Kojto 110:165afa46840b 299 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
Kojto 110:165afa46840b 300
Kojto 110:165afa46840b 301 #define xPSR_Z_Pos 30 /*!< xPSR: Z Position */
Kojto 110:165afa46840b 302 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
Kojto 110:165afa46840b 303
Kojto 110:165afa46840b 304 #define xPSR_C_Pos 29 /*!< xPSR: C Position */
Kojto 110:165afa46840b 305 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
Kojto 110:165afa46840b 306
Kojto 110:165afa46840b 307 #define xPSR_V_Pos 28 /*!< xPSR: V Position */
Kojto 110:165afa46840b 308 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
Kojto 110:165afa46840b 309
Kojto 110:165afa46840b 310 #define xPSR_T_Pos 24 /*!< xPSR: T Position */
Kojto 110:165afa46840b 311 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
Kojto 110:165afa46840b 312
Kojto 110:165afa46840b 313 #define xPSR_ISR_Pos 0 /*!< xPSR: ISR Position */
Kojto 110:165afa46840b 314 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
Kojto 110:165afa46840b 315
emilmont 77:869cf507173a 316
emilmont 77:869cf507173a 317 /** \brief Union type to access the Control Registers (CONTROL).
emilmont 77:869cf507173a 318 */
emilmont 77:869cf507173a 319 typedef union
emilmont 77:869cf507173a 320 {
emilmont 77:869cf507173a 321 struct
emilmont 77:869cf507173a 322 {
emilmont 77:869cf507173a 323 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
emilmont 77:869cf507173a 324 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
Kojto 110:165afa46840b 325 uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
emilmont 77:869cf507173a 326 } b; /*!< Structure used for bit access */
emilmont 77:869cf507173a 327 uint32_t w; /*!< Type used for word access */
emilmont 77:869cf507173a 328 } CONTROL_Type;
emilmont 77:869cf507173a 329
Kojto 110:165afa46840b 330 /* CONTROL Register Definitions */
Kojto 110:165afa46840b 331 #define CONTROL_SPSEL_Pos 1 /*!< CONTROL: SPSEL Position */
Kojto 110:165afa46840b 332 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
Kojto 110:165afa46840b 333
Kojto 110:165afa46840b 334 #define CONTROL_nPRIV_Pos 0 /*!< CONTROL: nPRIV Position */
Kojto 110:165afa46840b 335 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
Kojto 110:165afa46840b 336
emilmont 77:869cf507173a 337 /*@} end of group CMSIS_CORE */
emilmont 77:869cf507173a 338
emilmont 77:869cf507173a 339
emilmont 77:869cf507173a 340 /** \ingroup CMSIS_core_register
emilmont 77:869cf507173a 341 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
emilmont 77:869cf507173a 342 \brief Type definitions for the NVIC Registers
emilmont 77:869cf507173a 343 @{
emilmont 77:869cf507173a 344 */
emilmont 77:869cf507173a 345
emilmont 77:869cf507173a 346 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
emilmont 77:869cf507173a 347 */
emilmont 77:869cf507173a 348 typedef struct
emilmont 77:869cf507173a 349 {
emilmont 77:869cf507173a 350 __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
emilmont 77:869cf507173a 351 uint32_t RESERVED0[31];
emilmont 77:869cf507173a 352 __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
emilmont 77:869cf507173a 353 uint32_t RSERVED1[31];
emilmont 77:869cf507173a 354 __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
emilmont 77:869cf507173a 355 uint32_t RESERVED2[31];
emilmont 77:869cf507173a 356 __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
emilmont 77:869cf507173a 357 uint32_t RESERVED3[31];
emilmont 77:869cf507173a 358 uint32_t RESERVED4[64];
emilmont 77:869cf507173a 359 __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
emilmont 77:869cf507173a 360 } NVIC_Type;
emilmont 77:869cf507173a 361
emilmont 77:869cf507173a 362 /*@} end of group CMSIS_NVIC */
emilmont 77:869cf507173a 363
emilmont 77:869cf507173a 364
emilmont 77:869cf507173a 365 /** \ingroup CMSIS_core_register
emilmont 77:869cf507173a 366 \defgroup CMSIS_SCB System Control Block (SCB)
emilmont 77:869cf507173a 367 \brief Type definitions for the System Control Block Registers
emilmont 77:869cf507173a 368 @{
emilmont 77:869cf507173a 369 */
emilmont 77:869cf507173a 370
emilmont 77:869cf507173a 371 /** \brief Structure type to access the System Control Block (SCB).
emilmont 77:869cf507173a 372 */
emilmont 77:869cf507173a 373 typedef struct
emilmont 77:869cf507173a 374 {
emilmont 77:869cf507173a 375 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
emilmont 77:869cf507173a 376 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
emilmont 77:869cf507173a 377 #if (__VTOR_PRESENT == 1)
emilmont 77:869cf507173a 378 __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
emilmont 77:869cf507173a 379 #else
emilmont 77:869cf507173a 380 uint32_t RESERVED0;
emilmont 77:869cf507173a 381 #endif
emilmont 77:869cf507173a 382 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
emilmont 77:869cf507173a 383 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
emilmont 77:869cf507173a 384 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
emilmont 77:869cf507173a 385 uint32_t RESERVED1;
emilmont 77:869cf507173a 386 __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
emilmont 77:869cf507173a 387 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
emilmont 77:869cf507173a 388 } SCB_Type;
emilmont 77:869cf507173a 389
emilmont 77:869cf507173a 390 /* SCB CPUID Register Definitions */
emilmont 77:869cf507173a 391 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
emilmont 77:869cf507173a 392 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
emilmont 77:869cf507173a 393
emilmont 77:869cf507173a 394 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
emilmont 77:869cf507173a 395 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
emilmont 77:869cf507173a 396
emilmont 77:869cf507173a 397 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
emilmont 77:869cf507173a 398 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
emilmont 77:869cf507173a 399
emilmont 77:869cf507173a 400 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
emilmont 77:869cf507173a 401 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
emilmont 77:869cf507173a 402
emilmont 77:869cf507173a 403 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
Kojto 110:165afa46840b 404 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
emilmont 77:869cf507173a 405
emilmont 77:869cf507173a 406 /* SCB Interrupt Control State Register Definitions */
emilmont 77:869cf507173a 407 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
emilmont 77:869cf507173a 408 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
emilmont 77:869cf507173a 409
emilmont 77:869cf507173a 410 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
emilmont 77:869cf507173a 411 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
emilmont 77:869cf507173a 412
emilmont 77:869cf507173a 413 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
emilmont 77:869cf507173a 414 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
emilmont 77:869cf507173a 415
emilmont 77:869cf507173a 416 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
emilmont 77:869cf507173a 417 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
emilmont 77:869cf507173a 418
emilmont 77:869cf507173a 419 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
emilmont 77:869cf507173a 420 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
emilmont 77:869cf507173a 421
emilmont 77:869cf507173a 422 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
emilmont 77:869cf507173a 423 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
emilmont 77:869cf507173a 424
emilmont 77:869cf507173a 425 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
emilmont 77:869cf507173a 426 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
emilmont 77:869cf507173a 427
emilmont 77:869cf507173a 428 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
emilmont 77:869cf507173a 429 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
emilmont 77:869cf507173a 430
emilmont 77:869cf507173a 431 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
Kojto 110:165afa46840b 432 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
emilmont 77:869cf507173a 433
emilmont 77:869cf507173a 434 #if (__VTOR_PRESENT == 1)
emilmont 77:869cf507173a 435 /* SCB Interrupt Control State Register Definitions */
emilmont 77:869cf507173a 436 #define SCB_VTOR_TBLOFF_Pos 8 /*!< SCB VTOR: TBLOFF Position */
emilmont 77:869cf507173a 437 #define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
emilmont 77:869cf507173a 438 #endif
emilmont 77:869cf507173a 439
emilmont 77:869cf507173a 440 /* SCB Application Interrupt and Reset Control Register Definitions */
emilmont 77:869cf507173a 441 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
emilmont 77:869cf507173a 442 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
emilmont 77:869cf507173a 443
emilmont 77:869cf507173a 444 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
emilmont 77:869cf507173a 445 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
emilmont 77:869cf507173a 446
emilmont 77:869cf507173a 447 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
emilmont 77:869cf507173a 448 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
emilmont 77:869cf507173a 449
emilmont 77:869cf507173a 450 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
emilmont 77:869cf507173a 451 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
emilmont 77:869cf507173a 452
emilmont 77:869cf507173a 453 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
emilmont 77:869cf507173a 454 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
emilmont 77:869cf507173a 455
emilmont 77:869cf507173a 456 /* SCB System Control Register Definitions */
emilmont 77:869cf507173a 457 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
emilmont 77:869cf507173a 458 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
emilmont 77:869cf507173a 459
emilmont 77:869cf507173a 460 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
emilmont 77:869cf507173a 461 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
emilmont 77:869cf507173a 462
emilmont 77:869cf507173a 463 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
emilmont 77:869cf507173a 464 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
emilmont 77:869cf507173a 465
emilmont 77:869cf507173a 466 /* SCB Configuration Control Register Definitions */
emilmont 77:869cf507173a 467 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
emilmont 77:869cf507173a 468 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
emilmont 77:869cf507173a 469
emilmont 77:869cf507173a 470 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
emilmont 77:869cf507173a 471 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
emilmont 77:869cf507173a 472
emilmont 77:869cf507173a 473 /* SCB System Handler Control and State Register Definitions */
emilmont 77:869cf507173a 474 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
emilmont 77:869cf507173a 475 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
emilmont 77:869cf507173a 476
emilmont 77:869cf507173a 477 /*@} end of group CMSIS_SCB */
emilmont 77:869cf507173a 478
emilmont 77:869cf507173a 479
emilmont 77:869cf507173a 480 /** \ingroup CMSIS_core_register
emilmont 77:869cf507173a 481 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
emilmont 77:869cf507173a 482 \brief Type definitions for the System Timer Registers.
emilmont 77:869cf507173a 483 @{
emilmont 77:869cf507173a 484 */
emilmont 77:869cf507173a 485
emilmont 77:869cf507173a 486 /** \brief Structure type to access the System Timer (SysTick).
emilmont 77:869cf507173a 487 */
emilmont 77:869cf507173a 488 typedef struct
emilmont 77:869cf507173a 489 {
emilmont 77:869cf507173a 490 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
emilmont 77:869cf507173a 491 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
emilmont 77:869cf507173a 492 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
emilmont 77:869cf507173a 493 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
emilmont 77:869cf507173a 494 } SysTick_Type;
emilmont 77:869cf507173a 495
emilmont 77:869cf507173a 496 /* SysTick Control / Status Register Definitions */
emilmont 77:869cf507173a 497 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
emilmont 77:869cf507173a 498 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
emilmont 77:869cf507173a 499
emilmont 77:869cf507173a 500 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
emilmont 77:869cf507173a 501 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
emilmont 77:869cf507173a 502
emilmont 77:869cf507173a 503 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
emilmont 77:869cf507173a 504 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
emilmont 77:869cf507173a 505
emilmont 77:869cf507173a 506 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
Kojto 110:165afa46840b 507 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
emilmont 77:869cf507173a 508
emilmont 77:869cf507173a 509 /* SysTick Reload Register Definitions */
emilmont 77:869cf507173a 510 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
Kojto 110:165afa46840b 511 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
emilmont 77:869cf507173a 512
emilmont 77:869cf507173a 513 /* SysTick Current Register Definitions */
emilmont 77:869cf507173a 514 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
Kojto 110:165afa46840b 515 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
emilmont 77:869cf507173a 516
emilmont 77:869cf507173a 517 /* SysTick Calibration Register Definitions */
emilmont 77:869cf507173a 518 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
emilmont 77:869cf507173a 519 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
emilmont 77:869cf507173a 520
emilmont 77:869cf507173a 521 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
emilmont 77:869cf507173a 522 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
emilmont 77:869cf507173a 523
emilmont 77:869cf507173a 524 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
Kojto 110:165afa46840b 525 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
emilmont 77:869cf507173a 526
emilmont 77:869cf507173a 527 /*@} end of group CMSIS_SysTick */
emilmont 77:869cf507173a 528
emilmont 77:869cf507173a 529 #if (__MPU_PRESENT == 1)
emilmont 77:869cf507173a 530 /** \ingroup CMSIS_core_register
emilmont 77:869cf507173a 531 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
emilmont 77:869cf507173a 532 \brief Type definitions for the Memory Protection Unit (MPU)
emilmont 77:869cf507173a 533 @{
emilmont 77:869cf507173a 534 */
emilmont 77:869cf507173a 535
emilmont 77:869cf507173a 536 /** \brief Structure type to access the Memory Protection Unit (MPU).
emilmont 77:869cf507173a 537 */
emilmont 77:869cf507173a 538 typedef struct
emilmont 77:869cf507173a 539 {
emilmont 77:869cf507173a 540 __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
emilmont 77:869cf507173a 541 __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
emilmont 77:869cf507173a 542 __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
emilmont 77:869cf507173a 543 __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
emilmont 77:869cf507173a 544 __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
emilmont 77:869cf507173a 545 } MPU_Type;
emilmont 77:869cf507173a 546
emilmont 77:869cf507173a 547 /* MPU Type Register */
emilmont 77:869cf507173a 548 #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
emilmont 77:869cf507173a 549 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
emilmont 77:869cf507173a 550
emilmont 77:869cf507173a 551 #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
emilmont 77:869cf507173a 552 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
emilmont 77:869cf507173a 553
emilmont 77:869cf507173a 554 #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
Kojto 110:165afa46840b 555 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
emilmont 77:869cf507173a 556
emilmont 77:869cf507173a 557 /* MPU Control Register */
emilmont 77:869cf507173a 558 #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
emilmont 77:869cf507173a 559 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
emilmont 77:869cf507173a 560
emilmont 77:869cf507173a 561 #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
emilmont 77:869cf507173a 562 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
emilmont 77:869cf507173a 563
emilmont 77:869cf507173a 564 #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
Kojto 110:165afa46840b 565 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
emilmont 77:869cf507173a 566
emilmont 77:869cf507173a 567 /* MPU Region Number Register */
emilmont 77:869cf507173a 568 #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
Kojto 110:165afa46840b 569 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
emilmont 77:869cf507173a 570
emilmont 77:869cf507173a 571 /* MPU Region Base Address Register */
emilmont 77:869cf507173a 572 #define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */
emilmont 77:869cf507173a 573 #define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
emilmont 77:869cf507173a 574
emilmont 77:869cf507173a 575 #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
emilmont 77:869cf507173a 576 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
emilmont 77:869cf507173a 577
emilmont 77:869cf507173a 578 #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
Kojto 110:165afa46840b 579 #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
emilmont 77:869cf507173a 580
emilmont 77:869cf507173a 581 /* MPU Region Attribute and Size Register */
emilmont 77:869cf507173a 582 #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
emilmont 77:869cf507173a 583 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
emilmont 77:869cf507173a 584
emilmont 77:869cf507173a 585 #define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
emilmont 77:869cf507173a 586 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
emilmont 77:869cf507173a 587
emilmont 77:869cf507173a 588 #define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
emilmont 77:869cf507173a 589 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
emilmont 77:869cf507173a 590
emilmont 77:869cf507173a 591 #define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
emilmont 77:869cf507173a 592 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
emilmont 77:869cf507173a 593
emilmont 77:869cf507173a 594 #define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
emilmont 77:869cf507173a 595 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
emilmont 77:869cf507173a 596
emilmont 77:869cf507173a 597 #define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
emilmont 77:869cf507173a 598 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
emilmont 77:869cf507173a 599
emilmont 77:869cf507173a 600 #define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
emilmont 77:869cf507173a 601 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
emilmont 77:869cf507173a 602
emilmont 77:869cf507173a 603 #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
emilmont 77:869cf507173a 604 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
emilmont 77:869cf507173a 605
emilmont 77:869cf507173a 606 #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
emilmont 77:869cf507173a 607 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
emilmont 77:869cf507173a 608
emilmont 77:869cf507173a 609 #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
Kojto 110:165afa46840b 610 #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
emilmont 77:869cf507173a 611
emilmont 77:869cf507173a 612 /*@} end of group CMSIS_MPU */
emilmont 77:869cf507173a 613 #endif
emilmont 77:869cf507173a 614
emilmont 77:869cf507173a 615
emilmont 77:869cf507173a 616 /** \ingroup CMSIS_core_register
emilmont 77:869cf507173a 617 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
emilmont 77:869cf507173a 618 \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR)
emilmont 77:869cf507173a 619 are only accessible over DAP and not via processor. Therefore
emilmont 77:869cf507173a 620 they are not covered by the Cortex-M0 header file.
emilmont 77:869cf507173a 621 @{
emilmont 77:869cf507173a 622 */
emilmont 77:869cf507173a 623 /*@} end of group CMSIS_CoreDebug */
emilmont 77:869cf507173a 624
emilmont 77:869cf507173a 625
emilmont 77:869cf507173a 626 /** \ingroup CMSIS_core_register
emilmont 77:869cf507173a 627 \defgroup CMSIS_core_base Core Definitions
emilmont 77:869cf507173a 628 \brief Definitions for base addresses, unions, and structures.
emilmont 77:869cf507173a 629 @{
emilmont 77:869cf507173a 630 */
emilmont 77:869cf507173a 631
emilmont 77:869cf507173a 632 /* Memory mapping of Cortex-M0+ Hardware */
emilmont 77:869cf507173a 633 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
emilmont 77:869cf507173a 634 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
emilmont 77:869cf507173a 635 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
emilmont 77:869cf507173a 636 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
emilmont 77:869cf507173a 637
emilmont 77:869cf507173a 638 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
emilmont 77:869cf507173a 639 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
emilmont 77:869cf507173a 640 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
emilmont 77:869cf507173a 641
emilmont 77:869cf507173a 642 #if (__MPU_PRESENT == 1)
emilmont 77:869cf507173a 643 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
emilmont 77:869cf507173a 644 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
emilmont 77:869cf507173a 645 #endif
emilmont 77:869cf507173a 646
emilmont 77:869cf507173a 647 /*@} */
emilmont 77:869cf507173a 648
emilmont 77:869cf507173a 649
emilmont 77:869cf507173a 650
emilmont 77:869cf507173a 651 /*******************************************************************************
emilmont 77:869cf507173a 652 * Hardware Abstraction Layer
emilmont 77:869cf507173a 653 Core Function Interface contains:
emilmont 77:869cf507173a 654 - Core NVIC Functions
emilmont 77:869cf507173a 655 - Core SysTick Functions
emilmont 77:869cf507173a 656 - Core Register Access Functions
emilmont 77:869cf507173a 657 ******************************************************************************/
emilmont 77:869cf507173a 658 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
emilmont 77:869cf507173a 659 */
emilmont 77:869cf507173a 660
emilmont 77:869cf507173a 661
emilmont 77:869cf507173a 662
emilmont 77:869cf507173a 663 /* ########################## NVIC functions #################################### */
emilmont 77:869cf507173a 664 /** \ingroup CMSIS_Core_FunctionInterface
emilmont 77:869cf507173a 665 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
emilmont 77:869cf507173a 666 \brief Functions that manage interrupts and exceptions via the NVIC.
emilmont 77:869cf507173a 667 @{
emilmont 77:869cf507173a 668 */
emilmont 77:869cf507173a 669
emilmont 77:869cf507173a 670 /* Interrupt Priorities are WORD accessible only under ARMv6M */
emilmont 77:869cf507173a 671 /* The following MACROS handle generation of the register offset and byte masks */
Kojto 110:165afa46840b 672 #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
Kojto 110:165afa46840b 673 #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
Kojto 110:165afa46840b 674 #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
emilmont 77:869cf507173a 675
emilmont 77:869cf507173a 676
emilmont 77:869cf507173a 677 /** \brief Enable External Interrupt
emilmont 77:869cf507173a 678
emilmont 77:869cf507173a 679 The function enables a device-specific interrupt in the NVIC interrupt controller.
emilmont 77:869cf507173a 680
emilmont 77:869cf507173a 681 \param [in] IRQn External interrupt number. Value cannot be negative.
emilmont 77:869cf507173a 682 */
emilmont 77:869cf507173a 683 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
emilmont 77:869cf507173a 684 {
Kojto 110:165afa46840b 685 NVIC->ISER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
emilmont 77:869cf507173a 686 }
emilmont 77:869cf507173a 687
emilmont 77:869cf507173a 688
emilmont 77:869cf507173a 689 /** \brief Disable External Interrupt
emilmont 77:869cf507173a 690
emilmont 77:869cf507173a 691 The function disables a device-specific interrupt in the NVIC interrupt controller.
emilmont 77:869cf507173a 692
emilmont 77:869cf507173a 693 \param [in] IRQn External interrupt number. Value cannot be negative.
emilmont 77:869cf507173a 694 */
emilmont 77:869cf507173a 695 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
emilmont 77:869cf507173a 696 {
Kojto 110:165afa46840b 697 NVIC->ICER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
emilmont 77:869cf507173a 698 }
emilmont 77:869cf507173a 699
emilmont 77:869cf507173a 700
emilmont 77:869cf507173a 701 /** \brief Get Pending Interrupt
emilmont 77:869cf507173a 702
emilmont 77:869cf507173a 703 The function reads the pending register in the NVIC and returns the pending bit
emilmont 77:869cf507173a 704 for the specified interrupt.
emilmont 77:869cf507173a 705
emilmont 77:869cf507173a 706 \param [in] IRQn Interrupt number.
emilmont 77:869cf507173a 707
emilmont 77:869cf507173a 708 \return 0 Interrupt status is not pending.
emilmont 77:869cf507173a 709 \return 1 Interrupt status is pending.
emilmont 77:869cf507173a 710 */
emilmont 77:869cf507173a 711 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
emilmont 77:869cf507173a 712 {
Kojto 110:165afa46840b 713 return((uint32_t)(((NVIC->ISPR[0] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
emilmont 77:869cf507173a 714 }
emilmont 77:869cf507173a 715
emilmont 77:869cf507173a 716
emilmont 77:869cf507173a 717 /** \brief Set Pending Interrupt
emilmont 77:869cf507173a 718
emilmont 77:869cf507173a 719 The function sets the pending bit of an external interrupt.
emilmont 77:869cf507173a 720
emilmont 77:869cf507173a 721 \param [in] IRQn Interrupt number. Value cannot be negative.
emilmont 77:869cf507173a 722 */
emilmont 77:869cf507173a 723 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
emilmont 77:869cf507173a 724 {
Kojto 110:165afa46840b 725 NVIC->ISPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
emilmont 77:869cf507173a 726 }
emilmont 77:869cf507173a 727
emilmont 77:869cf507173a 728
emilmont 77:869cf507173a 729 /** \brief Clear Pending Interrupt
emilmont 77:869cf507173a 730
emilmont 77:869cf507173a 731 The function clears the pending bit of an external interrupt.
emilmont 77:869cf507173a 732
emilmont 77:869cf507173a 733 \param [in] IRQn External interrupt number. Value cannot be negative.
emilmont 77:869cf507173a 734 */
emilmont 77:869cf507173a 735 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
emilmont 77:869cf507173a 736 {
Kojto 110:165afa46840b 737 NVIC->ICPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
emilmont 77:869cf507173a 738 }
emilmont 77:869cf507173a 739
emilmont 77:869cf507173a 740
emilmont 77:869cf507173a 741 /** \brief Set Interrupt Priority
emilmont 77:869cf507173a 742
emilmont 77:869cf507173a 743 The function sets the priority of an interrupt.
emilmont 77:869cf507173a 744
emilmont 77:869cf507173a 745 \note The priority cannot be set for every core interrupt.
emilmont 77:869cf507173a 746
emilmont 77:869cf507173a 747 \param [in] IRQn Interrupt number.
emilmont 77:869cf507173a 748 \param [in] priority Priority to set.
emilmont 77:869cf507173a 749 */
emilmont 77:869cf507173a 750 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
emilmont 77:869cf507173a 751 {
Kojto 110:165afa46840b 752 if((int32_t)(IRQn) < 0) {
Kojto 110:165afa46840b 753 SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
Kojto 110:165afa46840b 754 (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
Kojto 110:165afa46840b 755 }
emilmont 77:869cf507173a 756 else {
Kojto 110:165afa46840b 757 NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
Kojto 110:165afa46840b 758 (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
Kojto 110:165afa46840b 759 }
emilmont 77:869cf507173a 760 }
emilmont 77:869cf507173a 761
emilmont 77:869cf507173a 762
emilmont 77:869cf507173a 763 /** \brief Get Interrupt Priority
emilmont 77:869cf507173a 764
emilmont 77:869cf507173a 765 The function reads the priority of an interrupt. The interrupt
emilmont 77:869cf507173a 766 number can be positive to specify an external (device specific)
emilmont 77:869cf507173a 767 interrupt, or negative to specify an internal (core) interrupt.
emilmont 77:869cf507173a 768
emilmont 77:869cf507173a 769
emilmont 77:869cf507173a 770 \param [in] IRQn Interrupt number.
emilmont 77:869cf507173a 771 \return Interrupt Priority. Value is aligned automatically to the implemented
emilmont 77:869cf507173a 772 priority bits of the microcontroller.
emilmont 77:869cf507173a 773 */
emilmont 77:869cf507173a 774 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
emilmont 77:869cf507173a 775 {
emilmont 77:869cf507173a 776
Kojto 110:165afa46840b 777 if((int32_t)(IRQn) < 0) {
Kojto 110:165afa46840b 778 return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));
Kojto 110:165afa46840b 779 }
emilmont 77:869cf507173a 780 else {
Kojto 110:165afa46840b 781 return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));
Kojto 110:165afa46840b 782 }
emilmont 77:869cf507173a 783 }
emilmont 77:869cf507173a 784
emilmont 77:869cf507173a 785
emilmont 77:869cf507173a 786 /** \brief System Reset
emilmont 77:869cf507173a 787
emilmont 77:869cf507173a 788 The function initiates a system reset request to reset the MCU.
emilmont 77:869cf507173a 789 */
emilmont 77:869cf507173a 790 __STATIC_INLINE void NVIC_SystemReset(void)
emilmont 77:869cf507173a 791 {
emilmont 77:869cf507173a 792 __DSB(); /* Ensure all outstanding memory accesses included
emilmont 77:869cf507173a 793 buffered write are completed before reset */
Kojto 110:165afa46840b 794 SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
emilmont 77:869cf507173a 795 SCB_AIRCR_SYSRESETREQ_Msk);
emilmont 77:869cf507173a 796 __DSB(); /* Ensure completion of memory access */
Kojto 110:165afa46840b 797 while(1) { __NOP(); } /* wait until reset */
emilmont 77:869cf507173a 798 }
emilmont 77:869cf507173a 799
emilmont 77:869cf507173a 800 /*@} end of CMSIS_Core_NVICFunctions */
emilmont 77:869cf507173a 801
emilmont 77:869cf507173a 802
emilmont 77:869cf507173a 803
emilmont 77:869cf507173a 804 /* ################################## SysTick function ############################################ */
emilmont 77:869cf507173a 805 /** \ingroup CMSIS_Core_FunctionInterface
emilmont 77:869cf507173a 806 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
emilmont 77:869cf507173a 807 \brief Functions that configure the System.
emilmont 77:869cf507173a 808 @{
emilmont 77:869cf507173a 809 */
emilmont 77:869cf507173a 810
emilmont 77:869cf507173a 811 #if (__Vendor_SysTickConfig == 0)
emilmont 77:869cf507173a 812
emilmont 77:869cf507173a 813 /** \brief System Tick Configuration
emilmont 77:869cf507173a 814
emilmont 77:869cf507173a 815 The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
emilmont 77:869cf507173a 816 Counter is in free running mode to generate periodic interrupts.
emilmont 77:869cf507173a 817
emilmont 77:869cf507173a 818 \param [in] ticks Number of ticks between two interrupts.
emilmont 77:869cf507173a 819
emilmont 77:869cf507173a 820 \return 0 Function succeeded.
emilmont 77:869cf507173a 821 \return 1 Function failed.
emilmont 77:869cf507173a 822
emilmont 77:869cf507173a 823 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
emilmont 77:869cf507173a 824 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
emilmont 77:869cf507173a 825 must contain a vendor-specific implementation of this function.
emilmont 77:869cf507173a 826
emilmont 77:869cf507173a 827 */
emilmont 77:869cf507173a 828 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
emilmont 77:869cf507173a 829 {
Kojto 110:165afa46840b 830 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {return (1UL);} /* Reload value impossible */
emilmont 77:869cf507173a 831
Kojto 110:165afa46840b 832 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
Kojto 110:165afa46840b 833 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
Kojto 110:165afa46840b 834 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
emilmont 77:869cf507173a 835 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
emilmont 77:869cf507173a 836 SysTick_CTRL_TICKINT_Msk |
Kojto 110:165afa46840b 837 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
Kojto 110:165afa46840b 838 return (0UL); /* Function successful */
emilmont 77:869cf507173a 839 }
emilmont 77:869cf507173a 840
emilmont 77:869cf507173a 841 #endif
emilmont 77:869cf507173a 842
emilmont 77:869cf507173a 843 /*@} end of CMSIS_Core_SysTickFunctions */
emilmont 77:869cf507173a 844
emilmont 77:869cf507173a 845
emilmont 77:869cf507173a 846
emilmont 77:869cf507173a 847
Kojto 110:165afa46840b 848 #ifdef __cplusplus
Kojto 110:165afa46840b 849 }
Kojto 110:165afa46840b 850 #endif
Kojto 110:165afa46840b 851
emilmont 77:869cf507173a 852 #endif /* __CORE_CM0PLUS_H_DEPENDANT */
emilmont 77:869cf507173a 853
emilmont 77:869cf507173a 854 #endif /* __CMSIS_GENERIC */