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The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

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mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_NUCLEO_F756ZG/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_sram.h@138:093f2bd7b9eb, 2017-03-14 (annotated)

Committer:
<>
Date:
Tue Mar 14 16:20:51 2017 +0000
Revision:
138:093f2bd7b9eb
Parent:
135:176b8275d35d
Child:
139:856d2700e60b
Release 138 of the mbed library



Ports for Upcoming Targets





Fixes and Changes



3716: fix for issue #3715: correction in startup files for ARM and IAR, alignment of system_stm32f429xx.c files https://github.com/ARMmbed/mbed-os/pull/3716

3741: STM32 remove warning in hal_tick_32b.c file https://github.com/ARMmbed/mbed-os/pull/3741

3780: STM32L4 : Fix GPIO G port compatibility https://github.com/ARMmbed/mbed-os/pull/3780

3831: NCS36510: SPISLAVE enabled (Conflict resolved) https://github.com/ARMmbed/mbed-os/pull/3831

3836: Allow to redefine nRF's PSTORAGE_NUM_OF_PAGES outside of the mbed-os https://github.com/ARMmbed/mbed-os/pull/3836

3840: STM32: gpio SPEED - always set High Speed by default https://github.com/ARMmbed/mbed-os/pull/3840

3844: STM32 GPIO: Typo correction. Update comment (GPIO_IP_WITHOUT_BRR) https://github.com/ARMmbed/mbed-os/pull/3844

3850: STM32: change spi error to debug warning https://github.com/ARMmbed/mbed-os/pull/3850

3860: Define GPIO_IP_WITHOUT_BRR for xDot platform https://github.com/ARMmbed/mbed-os/pull/3860

3880: DISCO_F469NI: allow the use of CAN2 instance when CAN1 is not activated https://github.com/ARMmbed/mbed-os/pull/3880

3795: Fix pwm period calc https://github.com/ARMmbed/mbed-os/pull/3795

3828: STM32 CAN API: correct format and type https://github.com/ARMmbed/mbed-os/pull/3828

3842: TARGET_NRF: corrected spi_init() to properly handle re-initialization https://github.com/ARMmbed/mbed-os/pull/3842

3843: STM32L476xG: set APB2 clock to 80MHz (instead of 40MHz) https://github.com/ARMmbed/mbed-os/pull/3843

3879: NUCLEO_F446ZE: Add missing AnalogIn pins on PF_3, PF_5 and PF_10. https://github.com/ARMmbed/mbed-os/pull/3879

3902: Fix heap and stack size for NUCLEO_F746ZG https://github.com/ARMmbed/mbed-os/pull/3902

3829: can_write(): return error code when no tx mailboxes are available https://github.com/ARMmbed/mbed-os/pull/3829

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 126:abea610beb85 1 /**
AnnaBridge 126:abea610beb85 2 ******************************************************************************
AnnaBridge 126:abea610beb85 3 * @file stm32f7xx_hal_sram.h
AnnaBridge 126:abea610beb85 4 * @author MCD Application Team
<> 135:176b8275d35d 5 * @version V1.1.2
<> 135:176b8275d35d 6 * @date 23-September-2016
AnnaBridge 126:abea610beb85 7 * @brief Header file of SRAM HAL module.
AnnaBridge 126:abea610beb85 8 ******************************************************************************
AnnaBridge 126:abea610beb85 9 * @attention
AnnaBridge 126:abea610beb85 10 *
AnnaBridge 126:abea610beb85 11 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
AnnaBridge 126:abea610beb85 12 *
AnnaBridge 126:abea610beb85 13 * Redistribution and use in source and binary forms, with or without modification,
AnnaBridge 126:abea610beb85 14 * are permitted provided that the following conditions are met:
AnnaBridge 126:abea610beb85 15 * 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge 126:abea610beb85 16 * this list of conditions and the following disclaimer.
AnnaBridge 126:abea610beb85 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge 126:abea610beb85 18 * this list of conditions and the following disclaimer in the documentation
AnnaBridge 126:abea610beb85 19 * and/or other materials provided with the distribution.
AnnaBridge 126:abea610beb85 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
AnnaBridge 126:abea610beb85 21 * may be used to endorse or promote products derived from this software
AnnaBridge 126:abea610beb85 22 * without specific prior written permission.
AnnaBridge 126:abea610beb85 23 *
AnnaBridge 126:abea610beb85 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge 126:abea610beb85 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge 126:abea610beb85 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge 126:abea610beb85 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge 126:abea610beb85 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge 126:abea610beb85 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge 126:abea610beb85 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge 126:abea610beb85 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge 126:abea610beb85 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge 126:abea610beb85 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge 126:abea610beb85 34 *
AnnaBridge 126:abea610beb85 35 ******************************************************************************
AnnaBridge 126:abea610beb85 36 */
AnnaBridge 126:abea610beb85 37
AnnaBridge 126:abea610beb85 38 /* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge 126:abea610beb85 39 #ifndef __STM32F7xx_HAL_SRAM_H
AnnaBridge 126:abea610beb85 40 #define __STM32F7xx_HAL_SRAM_H
AnnaBridge 126:abea610beb85 41
AnnaBridge 126:abea610beb85 42 #ifdef __cplusplus
AnnaBridge 126:abea610beb85 43 extern "C" {
AnnaBridge 126:abea610beb85 44 #endif
AnnaBridge 126:abea610beb85 45
AnnaBridge 126:abea610beb85 46 /* Includes ------------------------------------------------------------------*/
AnnaBridge 126:abea610beb85 47 #include "stm32f7xx_ll_fmc.h"
AnnaBridge 126:abea610beb85 48
AnnaBridge 126:abea610beb85 49 /** @addtogroup STM32F7xx_HAL_Driver
AnnaBridge 126:abea610beb85 50 * @{
AnnaBridge 126:abea610beb85 51 */
AnnaBridge 126:abea610beb85 52 /** @addtogroup SRAM
AnnaBridge 126:abea610beb85 53 * @{
AnnaBridge 126:abea610beb85 54 */
AnnaBridge 126:abea610beb85 55
AnnaBridge 126:abea610beb85 56 /* Exported typedef ----------------------------------------------------------*/
AnnaBridge 126:abea610beb85 57
AnnaBridge 126:abea610beb85 58 /** @defgroup SRAM_Exported_Types SRAM Exported Types
AnnaBridge 126:abea610beb85 59 * @{
AnnaBridge 126:abea610beb85 60 */
AnnaBridge 126:abea610beb85 61 /**
AnnaBridge 126:abea610beb85 62 * @brief HAL SRAM State structures definition
AnnaBridge 126:abea610beb85 63 */
AnnaBridge 126:abea610beb85 64 typedef enum
AnnaBridge 126:abea610beb85 65 {
AnnaBridge 126:abea610beb85 66 HAL_SRAM_STATE_RESET = 0x00U, /*!< SRAM not yet initialized or disabled */
AnnaBridge 126:abea610beb85 67 HAL_SRAM_STATE_READY = 0x01U, /*!< SRAM initialized and ready for use */
AnnaBridge 126:abea610beb85 68 HAL_SRAM_STATE_BUSY = 0x02U, /*!< SRAM internal process is ongoing */
AnnaBridge 126:abea610beb85 69 HAL_SRAM_STATE_ERROR = 0x03U, /*!< SRAM error state */
AnnaBridge 126:abea610beb85 70 HAL_SRAM_STATE_PROTECTED = 0x04U /*!< SRAM peripheral NORSRAM device write protected */
AnnaBridge 126:abea610beb85 71
AnnaBridge 126:abea610beb85 72 }HAL_SRAM_StateTypeDef;
AnnaBridge 126:abea610beb85 73
AnnaBridge 126:abea610beb85 74 /**
AnnaBridge 126:abea610beb85 75 * @brief SRAM handle Structure definition
AnnaBridge 126:abea610beb85 76 */
AnnaBridge 126:abea610beb85 77 typedef struct
AnnaBridge 126:abea610beb85 78 {
AnnaBridge 126:abea610beb85 79 FMC_NORSRAM_TypeDef *Instance; /*!< Register base address */
AnnaBridge 126:abea610beb85 80
AnnaBridge 126:abea610beb85 81 FMC_NORSRAM_EXTENDED_TypeDef *Extended; /*!< Extended mode register base address */
AnnaBridge 126:abea610beb85 82
AnnaBridge 126:abea610beb85 83 FMC_NORSRAM_InitTypeDef Init; /*!< SRAM device control configuration parameters */
AnnaBridge 126:abea610beb85 84
AnnaBridge 126:abea610beb85 85 HAL_LockTypeDef Lock; /*!< SRAM locking object */
AnnaBridge 126:abea610beb85 86
AnnaBridge 126:abea610beb85 87 __IO HAL_SRAM_StateTypeDef State; /*!< SRAM device access state */
AnnaBridge 126:abea610beb85 88
AnnaBridge 126:abea610beb85 89 DMA_HandleTypeDef *hdma; /*!< Pointer DMA handler */
AnnaBridge 126:abea610beb85 90
AnnaBridge 126:abea610beb85 91 }SRAM_HandleTypeDef;
AnnaBridge 126:abea610beb85 92
AnnaBridge 126:abea610beb85 93 /**
AnnaBridge 126:abea610beb85 94 * @}
AnnaBridge 126:abea610beb85 95 */
AnnaBridge 126:abea610beb85 96
AnnaBridge 126:abea610beb85 97 /* Exported constants --------------------------------------------------------*/
AnnaBridge 126:abea610beb85 98 /* Exported macro ------------------------------------------------------------*/
AnnaBridge 126:abea610beb85 99
AnnaBridge 126:abea610beb85 100 /** @defgroup SRAM_Exported_Macros SRAM Exported Macros
AnnaBridge 126:abea610beb85 101 * @{
AnnaBridge 126:abea610beb85 102 */
AnnaBridge 126:abea610beb85 103
AnnaBridge 126:abea610beb85 104 /** @brief Reset SRAM handle state
AnnaBridge 126:abea610beb85 105 * @param __HANDLE__: SRAM handle
AnnaBridge 126:abea610beb85 106 * @retval None
AnnaBridge 126:abea610beb85 107 */
AnnaBridge 126:abea610beb85 108 #define __HAL_SRAM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SRAM_STATE_RESET)
AnnaBridge 126:abea610beb85 109
AnnaBridge 126:abea610beb85 110 /**
AnnaBridge 126:abea610beb85 111 * @}
AnnaBridge 126:abea610beb85 112 */
AnnaBridge 126:abea610beb85 113
AnnaBridge 126:abea610beb85 114 /* Exported functions --------------------------------------------------------*/
AnnaBridge 126:abea610beb85 115 /** @addtogroup SRAM_Exported_Functions SRAM Exported Functions
AnnaBridge 126:abea610beb85 116 * @{
AnnaBridge 126:abea610beb85 117 */
AnnaBridge 126:abea610beb85 118
AnnaBridge 126:abea610beb85 119 /** @addtogroup SRAM_Exported_Functions_Group1 Initialization and de-initialization functions
AnnaBridge 126:abea610beb85 120 * @{
AnnaBridge 126:abea610beb85 121 */
AnnaBridge 126:abea610beb85 122
AnnaBridge 126:abea610beb85 123 /* Initialization/de-initialization functions ********************************/
AnnaBridge 126:abea610beb85 124 HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming);
AnnaBridge 126:abea610beb85 125 HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram);
AnnaBridge 126:abea610beb85 126 void HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram);
AnnaBridge 126:abea610beb85 127 void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram);
AnnaBridge 126:abea610beb85 128
AnnaBridge 126:abea610beb85 129 /**
AnnaBridge 126:abea610beb85 130 * @}
AnnaBridge 126:abea610beb85 131 */
AnnaBridge 126:abea610beb85 132
AnnaBridge 126:abea610beb85 133 /** @addtogroup SRAM_Exported_Functions_Group2 Input Output and memory control functions
AnnaBridge 126:abea610beb85 134 * @{
AnnaBridge 126:abea610beb85 135 */
AnnaBridge 126:abea610beb85 136
AnnaBridge 126:abea610beb85 137 /* I/O operation functions ***************************************************/
AnnaBridge 126:abea610beb85 138 HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize);
AnnaBridge 126:abea610beb85 139 HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize);
AnnaBridge 126:abea610beb85 140 HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize);
AnnaBridge 126:abea610beb85 141 HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize);
AnnaBridge 126:abea610beb85 142 HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize);
AnnaBridge 126:abea610beb85 143 HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize);
AnnaBridge 126:abea610beb85 144 HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize);
AnnaBridge 126:abea610beb85 145 HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize);
AnnaBridge 126:abea610beb85 146
AnnaBridge 126:abea610beb85 147 void HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma);
AnnaBridge 126:abea610beb85 148 void HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma);
AnnaBridge 126:abea610beb85 149
AnnaBridge 126:abea610beb85 150 /**
AnnaBridge 126:abea610beb85 151 * @}
AnnaBridge 126:abea610beb85 152 */
AnnaBridge 126:abea610beb85 153
AnnaBridge 126:abea610beb85 154 /** @addtogroup SRAM_Exported_Functions_Group3 Control functions
AnnaBridge 126:abea610beb85 155 * @{
AnnaBridge 126:abea610beb85 156 */
AnnaBridge 126:abea610beb85 157
AnnaBridge 126:abea610beb85 158 /* SRAM Control functions ****************************************************/
AnnaBridge 126:abea610beb85 159 HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram);
AnnaBridge 126:abea610beb85 160 HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram);
AnnaBridge 126:abea610beb85 161
AnnaBridge 126:abea610beb85 162 /**
AnnaBridge 126:abea610beb85 163 * @}
AnnaBridge 126:abea610beb85 164 */
AnnaBridge 126:abea610beb85 165
AnnaBridge 126:abea610beb85 166 /** @addtogroup SRAM_Exported_Functions_Group4 Peripheral State functions
AnnaBridge 126:abea610beb85 167 * @{
AnnaBridge 126:abea610beb85 168 */
AnnaBridge 126:abea610beb85 169
AnnaBridge 126:abea610beb85 170 /* SRAM State functions ******************************************************/
AnnaBridge 126:abea610beb85 171 HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram);
AnnaBridge 126:abea610beb85 172
AnnaBridge 126:abea610beb85 173 /**
AnnaBridge 126:abea610beb85 174 * @}
AnnaBridge 126:abea610beb85 175 */
AnnaBridge 126:abea610beb85 176
AnnaBridge 126:abea610beb85 177 /**
AnnaBridge 126:abea610beb85 178 * @}
AnnaBridge 126:abea610beb85 179 */
AnnaBridge 126:abea610beb85 180
AnnaBridge 126:abea610beb85 181 /**
AnnaBridge 126:abea610beb85 182 * @}
AnnaBridge 126:abea610beb85 183 */
AnnaBridge 126:abea610beb85 184
AnnaBridge 126:abea610beb85 185 /**
AnnaBridge 126:abea610beb85 186 * @}
AnnaBridge 126:abea610beb85 187 */
AnnaBridge 126:abea610beb85 188
AnnaBridge 126:abea610beb85 189 #ifdef __cplusplus
AnnaBridge 126:abea610beb85 190 }
AnnaBridge 126:abea610beb85 191 #endif
AnnaBridge 126:abea610beb85 192
AnnaBridge 126:abea610beb85 193 #endif /* __STM32F7xx_HAL_SRAM_H */
AnnaBridge 126:abea610beb85 194
AnnaBridge 126:abea610beb85 195 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/