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Dependents: Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more
Diff: targets/TARGET_STM/TARGET_STM32F7/TARGET_F746_F756/TARGET_NUCLEO_F756ZG/device/stm32f756xx.h
- Revision:
- 157:ff67d9f36b67
- Parent:
- 149:156823d33999
diff -r 95d6b41a828b -r ff67d9f36b67 targets/TARGET_STM/TARGET_STM32F7/TARGET_F746_F756/TARGET_NUCLEO_F756ZG/device/stm32f756xx.h
--- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_F746_F756/TARGET_NUCLEO_F756ZG/device/stm32f756xx.h Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_F746_F756/TARGET_NUCLEO_F756ZG/device/stm32f756xx.h Thu Feb 02 17:01:33 2017 +0000
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f756xx.h
* @author MCD Application Team
- * @version V1.1.0
- * @date 22-April-2016
+ * @version V1.1.2
+ * @date 23-September-2016
* @brief CMSIS Cortex-M7 Device Peripheral Access Layer Header File.
*
* This file contains:
@@ -315,7 +315,6 @@
__IO uint32_t IER; /*!< CEC interrupt enable register, Address offset:0x14 */
}CEC_TypeDef;
-
/**
* @brief CRC calculation unit
*/
@@ -408,7 +407,6 @@
__IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
} DMA_TypeDef;
-
/**
* @brief DMA2D Controller
*/
@@ -855,7 +853,6 @@
__IO uint32_t DIR; /*!< Debug Information register, Address offset: 0x18 */
} SPDIFRX_TypeDef;
-
/**
* @brief SD host Interface
*/
@@ -1394,7 +1391,7 @@
#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
#define SPI3 ((SPI_TypeDef *) SPI3_BASE)
-#define SPDIFRX ((SPDIFRX_TypeDef *) SPDIFRX_BASE)
+#define SPDIFRX ((SPDIFRX_TypeDef *) SPDIFRX_BASE)
#define USART2 ((USART_TypeDef *) USART2_BASE)
#define USART3 ((USART_TypeDef *) USART3_BASE)
#define UART4 ((USART_TypeDef *) UART4_BASE)
@@ -3795,7 +3792,6 @@
/******************** Bit definition for DMA2D_BGCLUT register **************/
-
/******************************************************************************/
/* */
/* External Interrupt/Event Controller */
@@ -4105,6 +4101,7 @@
#define FLASH_OPTCR1_BOOT_ADD0 0x0000FFFFU
#define FLASH_OPTCR1_BOOT_ADD1 0xFFFF0000U
+
/******************************************************************************/
/* */
/* Flexible Memory Controller */
@@ -6231,7 +6228,7 @@
#define RTC_CR_OSEL_1 0x00400000U
#define RTC_CR_POL 0x00100000U
#define RTC_CR_COSEL 0x00080000U
-#define RTC_CR_BCK 0x00040000U
+#define RTC_CR_BKP 0x00040000U
#define RTC_CR_SUB1H 0x00020000U
#define RTC_CR_ADD1H 0x00010000U
#define RTC_CR_TSIE 0x00008000U
@@ -6251,6 +6248,9 @@
#define RTC_CR_WUCKSEL_1 0x00000002U
#define RTC_CR_WUCKSEL_2 0x00000004U
+/* Legacy define */
+#define RTC_CR_BCK RTC_CR_BKP
+
/******************** Bits definition for RTC_ISR register ******************/
#define RTC_ISR_ITSF 0x00020000U
#define RTC_ISR_RECALPF 0x00010000U
@@ -6826,7 +6826,6 @@
#define SPDIFRX_DIR_THI 0x000013FFU /*!<Threshold LOW */
#define SPDIFRX_DIR_TLO 0x1FFF0000U /*!<Threshold HIGH */
-
/******************************************************************************/
/* */
/* SD host Interface */
@@ -9161,6 +9160,7 @@
+
/**
* @}
*/
@@ -9214,28 +9214,28 @@
/******************************* GPIO Instances *******************************/
#define IS_GPIO_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == GPIOA) || \
- ((__INSTANCE__) == GPIOB) || \
- ((__INSTANCE__) == GPIOC) || \
- ((__INSTANCE__) == GPIOD) || \
- ((__INSTANCE__) == GPIOE) || \
- ((__INSTANCE__) == GPIOF) || \
- ((__INSTANCE__) == GPIOG) || \
- ((__INSTANCE__) == GPIOH) || \
- ((__INSTANCE__) == GPIOI) || \
- ((__INSTANCE__) == GPIOJ) || \
- ((__INSTANCE__) == GPIOK))
+ ((__INSTANCE__) == GPIOB) || \
+ ((__INSTANCE__) == GPIOC) || \
+ ((__INSTANCE__) == GPIOD) || \
+ ((__INSTANCE__) == GPIOE) || \
+ ((__INSTANCE__) == GPIOF) || \
+ ((__INSTANCE__) == GPIOG) || \
+ ((__INSTANCE__) == GPIOH) || \
+ ((__INSTANCE__) == GPIOI) || \
+ ((__INSTANCE__) == GPIOJ) || \
+ ((__INSTANCE__) == GPIOK))
#define IS_GPIO_AF_INSTANCE(__INSTANCE__) (((__INSTANCE__) == GPIOA) || \
- ((__INSTANCE__) == GPIOB) || \
- ((__INSTANCE__) == GPIOC) || \
- ((__INSTANCE__) == GPIOD) || \
- ((__INSTANCE__) == GPIOE) || \
- ((__INSTANCE__) == GPIOF) || \
- ((__INSTANCE__) == GPIOG) || \
- ((__INSTANCE__) == GPIOH) || \
- ((__INSTANCE__) == GPIOI) || \
- ((__INSTANCE__) == GPIOJ) || \
- ((__INSTANCE__) == GPIOK))
+ ((__INSTANCE__) == GPIOB) || \
+ ((__INSTANCE__) == GPIOC) || \
+ ((__INSTANCE__) == GPIOD) || \
+ ((__INSTANCE__) == GPIOE) || \
+ ((__INSTANCE__) == GPIOF) || \
+ ((__INSTANCE__) == GPIOG) || \
+ ((__INSTANCE__) == GPIOH) || \
+ ((__INSTANCE__) == GPIOI) || \
+ ((__INSTANCE__) == GPIOJ) || \
+ ((__INSTANCE__) == GPIOK))
/****************************** CEC Instances *********************************/
#define IS_CEC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == CEC)
@@ -9246,14 +9246,14 @@
/******************************** I2C Instances *******************************/
#define IS_I2C_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == I2C1) || \
- ((__INSTANCE__) == I2C2) || \
- ((__INSTANCE__) == I2C3) || \
- ((__INSTANCE__) == I2C4))
+ ((__INSTANCE__) == I2C2) || \
+ ((__INSTANCE__) == I2C3) || \
+ ((__INSTANCE__) == I2C4))
/******************************** I2S Instances *******************************/
#define IS_I2S_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == SPI1) || \
- ((__INSTANCE__) == SPI2) || \
- ((__INSTANCE__) == SPI3))
+ ((__INSTANCE__) == SPI2) || \
+ ((__INSTANCE__) == SPI3))
/******************************* LPTIM Instances ********************************/
#define IS_LPTIM_INSTANCE(__INSTANCE__) ((__INSTANCE__) == LPTIM1)
@@ -9263,6 +9263,7 @@
+
/******************************* RNG Instances ********************************/
#define IS_RNG_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == RNG)
@@ -9285,11 +9286,11 @@
/******************************** SPI Instances *******************************/
#define IS_SPI_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == SPI1) || \
- ((__INSTANCE__) == SPI2) || \
- ((__INSTANCE__) == SPI3) || \
- ((__INSTANCE__) == SPI4) || \
- ((__INSTANCE__) == SPI5) || \
- ((__INSTANCE__) == SPI6))
+ ((__INSTANCE__) == SPI2) || \
+ ((__INSTANCE__) == SPI3) || \
+ ((__INSTANCE__) == SPI4) || \
+ ((__INSTANCE__) == SPI5) || \
+ ((__INSTANCE__) == SPI6))
/****************** TIM Instances : All supported instances *******************/
#define IS_TIM_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
