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Dependents: Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more
Diff: targets/TARGET_NUVOTON/TARGET_M451/mbed_overrides.c
- Revision:
- 187:0387e8f68319
- Parent:
- 172:7d866c31b3c5
diff -r 707f6e361f3e -r 0387e8f68319 targets/TARGET_NUVOTON/TARGET_M451/mbed_overrides.c --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/TARGET_NUVOTON/TARGET_M451/mbed_overrides.c Thu Sep 06 13:40:20 2018 +0100 @@ -0,0 +1,69 @@ +/* mbed Microcontroller Library + * Copyright (c) 2015-2016 Nuvoton + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "analogin_api.h" + +void mbed_sdk_init(void) +{ + // NOTE: Support singleton semantics to be called from other init functions + static int inited = 0; + if (inited) { + return; + } + inited = 1; + + /*---------------------------------------------------------------------------------------------------------*/ + /* Init System Clock */ + /*---------------------------------------------------------------------------------------------------------*/ + /* Unlock protected registers */ + SYS_UnlockReg(); + + /* Enable HIRC clock (Internal RC 22.1184MHz) */ + CLK_EnableXtalRC(CLK_PWRCTL_HIRCEN_Msk); + /* Enable HXT clock (external XTAL 12MHz) */ + CLK_EnableXtalRC(CLK_PWRCTL_HXTEN_Msk); + /* Enable LIRC for lp_ticker */ + CLK_EnableXtalRC(CLK_PWRCTL_LIRCEN_Msk); + /* Enable LXT for RTC */ + CLK_EnableXtalRC(CLK_PWRCTL_LXTEN_Msk); + + /* Wait for HIRC clock ready */ + CLK_WaitClockReady(CLK_STATUS_HIRCSTB_Msk); + /* Wait for HXT clock ready */ + CLK_WaitClockReady(CLK_STATUS_HXTSTB_Msk); + /* Wait for LIRC clock ready */ + CLK_WaitClockReady(CLK_STATUS_LIRCSTB_Msk); + /* Wait for LXT clock ready */ + CLK_WaitClockReady(CLK_STATUS_LXTSTB_Msk); + + /* Select HCLK clock source as HIRC and HCLK clock divider as 1 */ + CLK_SetHCLK(CLK_CLKSEL0_HCLKSEL_HIRC, CLK_CLKDIV0_HCLK(1)); + + /* Set core clock as 72000000 from PLL */ + CLK_SetCoreClock(72000000); + +#if DEVICE_ANALOGIN + /* Vref connect to internal */ + SYS->VREFCTL = (SYS->VREFCTL & ~SYS_VREFCTL_VREFCTL_Msk) | SYS_VREFCTL_VREF_3_072V; +#endif + + /* Update System Core Clock */ + /* User can use SystemCoreClockUpdate() to calculate SystemCoreClock. */ + SystemCoreClockUpdate(); + + /* Lock protected registers */ + SYS_LockReg(); +}