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targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_cec.h@153:fa9ff456f731, 2016-12-20 (annotated)

Committer:
<>
Date:
Tue Dec 20 17:27:56 2016 +0000
Revision:
153:fa9ff456f731
Parent:
149:156823d33999
Child:
157:ff67d9f36b67
This updates the lib to the mbed lib v132

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f7xx_hal_cec.h
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @version V1.1.0
<> 144:ef7eb2e8f9f7 6 * @date 22-April-2016
<> 144:ef7eb2e8f9f7 7 * @brief Header file of CEC HAL module.
<> 144:ef7eb2e8f9f7 8 ******************************************************************************
<> 144:ef7eb2e8f9f7 9 * @attention
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 12 *
<> 144:ef7eb2e8f9f7 13 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 14 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 15 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 16 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 18 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 19 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 21 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 22 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 23 *
<> 144:ef7eb2e8f9f7 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 34 *
<> 144:ef7eb2e8f9f7 35 ******************************************************************************
<> 144:ef7eb2e8f9f7 36 */
<> 144:ef7eb2e8f9f7 37
<> 144:ef7eb2e8f9f7 38 /* Define to prevent recursive inclusion -------------------------------------*/
<> 144:ef7eb2e8f9f7 39 #ifndef __STM32F7xx_HAL_CEC_H
<> 144:ef7eb2e8f9f7 40 #define __STM32F7xx_HAL_CEC_H
<> 144:ef7eb2e8f9f7 41
<> 144:ef7eb2e8f9f7 42 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 43 extern "C" {
<> 144:ef7eb2e8f9f7 44 #endif
<> 144:ef7eb2e8f9f7 45
<> 144:ef7eb2e8f9f7 46 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 47 #include "stm32f7xx_hal_def.h"
<> 144:ef7eb2e8f9f7 48
<> 144:ef7eb2e8f9f7 49 /** @addtogroup STM32F7xx_HAL_Driver
<> 144:ef7eb2e8f9f7 50 * @{
<> 144:ef7eb2e8f9f7 51 */
<> 144:ef7eb2e8f9f7 52
<> 144:ef7eb2e8f9f7 53 /** @addtogroup CEC
<> 144:ef7eb2e8f9f7 54 * @{
<> 144:ef7eb2e8f9f7 55 */
<> 144:ef7eb2e8f9f7 56
<> 144:ef7eb2e8f9f7 57 /* Exported types ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 58 /** @defgroup CEC_Exported_Types CEC Exported Types
<> 144:ef7eb2e8f9f7 59 * @{
<> 144:ef7eb2e8f9f7 60 */
<> 144:ef7eb2e8f9f7 61
<> 144:ef7eb2e8f9f7 62 /**
<> 144:ef7eb2e8f9f7 63 * @brief CEC Init Structure definition
<> 144:ef7eb2e8f9f7 64 */
<> 144:ef7eb2e8f9f7 65 typedef struct
<> 144:ef7eb2e8f9f7 66 {
<> 144:ef7eb2e8f9f7 67 uint32_t SignalFreeTime; /*!< Set SFT field, specifies the Signal Free Time.
<> 144:ef7eb2e8f9f7 68 It can be one of @ref CEC_Signal_Free_Time
<> 144:ef7eb2e8f9f7 69 and belongs to the set {0,...,7} where
<> 144:ef7eb2e8f9f7 70 0x0 is the default configuration
<> 144:ef7eb2e8f9f7 71 else means 0.5 + (SignalFreeTime - 1) nominal data bit periods */
<> 144:ef7eb2e8f9f7 72
<> 144:ef7eb2e8f9f7 73 uint32_t Tolerance; /*!< Set RXTOL bit, specifies the tolerance accepted on the received waveforms,
<> 144:ef7eb2e8f9f7 74 it can be a value of @ref CEC_Tolerance : it is either CEC_STANDARD_TOLERANCE
<> 144:ef7eb2e8f9f7 75 or CEC_EXTENDED_TOLERANCE */
<> 144:ef7eb2e8f9f7 76
<> 144:ef7eb2e8f9f7 77 uint32_t BRERxStop; /*!< Set BRESTP bit @ref CEC_BRERxStop : specifies whether or not a Bit Rising Error stops the reception.
<> 144:ef7eb2e8f9f7 78 CEC_NO_RX_STOP_ON_BRE: reception is not stopped.
<> 144:ef7eb2e8f9f7 79 CEC_RX_STOP_ON_BRE: reception is stopped. */
<> 144:ef7eb2e8f9f7 80
<> 144:ef7eb2e8f9f7 81 uint32_t BREErrorBitGen; /*!< Set BREGEN bit @ref CEC_BREErrorBitGen : specifies whether or not an Error-Bit is generated on the
<> 144:ef7eb2e8f9f7 82 CEC line upon Bit Rising Error detection.
<> 144:ef7eb2e8f9f7 83 CEC_BRE_ERRORBIT_NO_GENERATION: no error-bit generation.
<> 144:ef7eb2e8f9f7 84 CEC_BRE_ERRORBIT_GENERATION: error-bit generation if BRESTP is set. */
<> 144:ef7eb2e8f9f7 85
<> 144:ef7eb2e8f9f7 86 uint32_t LBPEErrorBitGen; /*!< Set LBPEGEN bit @ref CEC_LBPEErrorBitGen : specifies whether or not an Error-Bit is generated on the
<> 144:ef7eb2e8f9f7 87 CEC line upon Long Bit Period Error detection.
<> 144:ef7eb2e8f9f7 88 CEC_LBPE_ERRORBIT_NO_GENERATION: no error-bit generation.
<> 144:ef7eb2e8f9f7 89 CEC_LBPE_ERRORBIT_GENERATION: error-bit generation. */
<> 144:ef7eb2e8f9f7 90
<> 144:ef7eb2e8f9f7 91 uint32_t BroadcastMsgNoErrorBitGen; /*!< Set BRDNOGEN bit @ref CEC_BroadCastMsgErrorBitGen : allows to avoid an Error-Bit generation on the CEC line
<> 144:ef7eb2e8f9f7 92 upon an error detected on a broadcast message.
<> 144:ef7eb2e8f9f7 93
<> 144:ef7eb2e8f9f7 94 It supersedes BREGEN and LBPEGEN bits for a broadcast message error handling. It can take two values:
<> 144:ef7eb2e8f9f7 95
<> 144:ef7eb2e8f9f7 96 1) CEC_BROADCASTERROR_ERRORBIT_GENERATION.
<> 144:ef7eb2e8f9f7 97 a) BRE detection: error-bit generation on the CEC line if BRESTP=CEC_RX_STOP_ON_BRE
<> 144:ef7eb2e8f9f7 98 and BREGEN=CEC_BRE_ERRORBIT_NO_GENERATION.
<> 144:ef7eb2e8f9f7 99 b) LBPE detection: error-bit generation on the CEC line
<> 144:ef7eb2e8f9f7 100 if LBPGEN=CEC_LBPE_ERRORBIT_NO_GENERATION.
<> 144:ef7eb2e8f9f7 101
<> 144:ef7eb2e8f9f7 102 2) CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION.
<> 144:ef7eb2e8f9f7 103 no error-bit generation in case neither a) nor b) are satisfied. Additionally,
<> 144:ef7eb2e8f9f7 104 there is no error-bit generation in case of Short Bit Period Error detection in
<> 144:ef7eb2e8f9f7 105 a broadcast message while LSTN bit is set. */
<> 144:ef7eb2e8f9f7 106
<> 144:ef7eb2e8f9f7 107 uint32_t SignalFreeTimeOption; /*!< Set SFTOP bit @ref CEC_SFT_Option : specifies when SFT timer starts.
<> 144:ef7eb2e8f9f7 108 CEC_SFT_START_ON_TXSOM SFT: timer starts when TXSOM is set by software.
<> 144:ef7eb2e8f9f7 109 CEC_SFT_START_ON_TX_RX_END: SFT timer starts automatically at the end of message transmission/reception. */
<> 144:ef7eb2e8f9f7 110
<> 144:ef7eb2e8f9f7 111 uint32_t ListenMode; /*!< Set LSTN bit @ref CEC_Listening_Mode : specifies device listening mode. It can take two values:
<> 144:ef7eb2e8f9f7 112
<> 144:ef7eb2e8f9f7 113 CEC_REDUCED_LISTENING_MODE: CEC peripheral receives only message addressed to its
<> 144:ef7eb2e8f9f7 114 own address (OAR). Messages addressed to different destination are ignored.
<> 144:ef7eb2e8f9f7 115 Broadcast messages are always received.
<> 144:ef7eb2e8f9f7 116
<> 144:ef7eb2e8f9f7 117 CEC_FULL_LISTENING_MODE: CEC peripheral receives messages addressed to its own
<> 144:ef7eb2e8f9f7 118 address (OAR) with positive acknowledge. Messages addressed to different destination
<> 144:ef7eb2e8f9f7 119 are received, but without interfering with the CEC bus: no acknowledge sent. */
<> 144:ef7eb2e8f9f7 120
<> 144:ef7eb2e8f9f7 121 uint16_t OwnAddress; /*!< Own addresses configuration
<> 144:ef7eb2e8f9f7 122 This parameter can be a value of @ref CEC_OWN_ADDRESS */
<> 144:ef7eb2e8f9f7 123
<> 144:ef7eb2e8f9f7 124 uint8_t *RxBuffer; /*!< CEC Rx buffer pointeur */
<> 144:ef7eb2e8f9f7 125
<> 144:ef7eb2e8f9f7 126
<> 144:ef7eb2e8f9f7 127 }CEC_InitTypeDef;
<> 144:ef7eb2e8f9f7 128
<> 144:ef7eb2e8f9f7 129 /**
<> 144:ef7eb2e8f9f7 130 * @brief HAL CEC State structures definition
<> 144:ef7eb2e8f9f7 131 * @note HAL CEC State value is a combination of 2 different substates: gState and RxState.
<> 144:ef7eb2e8f9f7 132 * - gState contains CEC state information related to global Handle management
<> 144:ef7eb2e8f9f7 133 * and also information related to Tx operations.
<> 144:ef7eb2e8f9f7 134 * gState value coding follow below described bitmap :
<> 144:ef7eb2e8f9f7 135 * b7 (not used)
<> 144:ef7eb2e8f9f7 136 * x : Should be set to 0
<> 144:ef7eb2e8f9f7 137 * b6 Error information
<> 144:ef7eb2e8f9f7 138 * 0 : No Error
<> 144:ef7eb2e8f9f7 139 * 1 : Error
<> 144:ef7eb2e8f9f7 140 * b5 IP initilisation status
<> 144:ef7eb2e8f9f7 141 * 0 : Reset (IP not initialized)
<> 144:ef7eb2e8f9f7 142 * 1 : Init done (IP initialized. HAL CEC Init function already called)
<> 144:ef7eb2e8f9f7 143 * b4-b3 (not used)
<> 144:ef7eb2e8f9f7 144 * xx : Should be set to 00
<> 144:ef7eb2e8f9f7 145 * b2 Intrinsic process state
<> 144:ef7eb2e8f9f7 146 * 0 : Ready
<> 144:ef7eb2e8f9f7 147 * 1 : Busy (IP busy with some configuration or internal operations)
<> 144:ef7eb2e8f9f7 148 * b1 (not used)
<> 144:ef7eb2e8f9f7 149 * x : Should be set to 0
<> 144:ef7eb2e8f9f7 150 * b0 Tx state
<> 144:ef7eb2e8f9f7 151 * 0 : Ready (no Tx operation ongoing)
<> 144:ef7eb2e8f9f7 152 * 1 : Busy (Tx operation ongoing)
<> 144:ef7eb2e8f9f7 153 * - RxState contains information related to Rx operations.
<> 144:ef7eb2e8f9f7 154 * RxState value coding follow below described bitmap :
<> 144:ef7eb2e8f9f7 155 * b7-b6 (not used)
<> 144:ef7eb2e8f9f7 156 * xx : Should be set to 00
<> 144:ef7eb2e8f9f7 157 * b5 IP initilisation status
<> 144:ef7eb2e8f9f7 158 * 0 : Reset (IP not initialized)
<> 144:ef7eb2e8f9f7 159 * 1 : Init done (IP initialized)
<> 144:ef7eb2e8f9f7 160 * b4-b2 (not used)
<> 144:ef7eb2e8f9f7 161 * xxx : Should be set to 000
<> 144:ef7eb2e8f9f7 162 * b1 Rx state
<> 144:ef7eb2e8f9f7 163 * 0 : Ready (no Rx operation ongoing)
<> 144:ef7eb2e8f9f7 164 * 1 : Busy (Rx operation ongoing)
<> 144:ef7eb2e8f9f7 165 * b0 (not used)
<> 144:ef7eb2e8f9f7 166 * x : Should be set to 0.
<> 144:ef7eb2e8f9f7 167 */
<> 144:ef7eb2e8f9f7 168 typedef enum
<> 144:ef7eb2e8f9f7 169 {
<> 144:ef7eb2e8f9f7 170 HAL_CEC_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized
<> 144:ef7eb2e8f9f7 171 Value is allowed for gState and RxState */
<> 144:ef7eb2e8f9f7 172 HAL_CEC_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use
<> 144:ef7eb2e8f9f7 173 Value is allowed for gState and RxState */
<> 144:ef7eb2e8f9f7 174 HAL_CEC_STATE_BUSY = 0x24U, /*!< an internal process is ongoing
<> 144:ef7eb2e8f9f7 175 Value is allowed for gState only */
<> 144:ef7eb2e8f9f7 176 HAL_CEC_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing
<> 144:ef7eb2e8f9f7 177 Value is allowed for RxState only */
<> 144:ef7eb2e8f9f7 178 HAL_CEC_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing
<> 144:ef7eb2e8f9f7 179 Value is allowed for gState only */
<> 144:ef7eb2e8f9f7 180 HAL_CEC_STATE_BUSY_RX_TX = 0x23U, /*!< an internal process is ongoing
<> 144:ef7eb2e8f9f7 181 Value is allowed for gState only */
<> 144:ef7eb2e8f9f7 182 HAL_CEC_STATE_ERROR = 0x60U /*!< Error Value is allowed for gState only */
<> 144:ef7eb2e8f9f7 183 }HAL_CEC_StateTypeDef;
<> 144:ef7eb2e8f9f7 184
<> 144:ef7eb2e8f9f7 185 /**
<> 144:ef7eb2e8f9f7 186 * @brief CEC handle Structure definition
<> 144:ef7eb2e8f9f7 187 */
<> 144:ef7eb2e8f9f7 188 typedef struct
<> 144:ef7eb2e8f9f7 189 {
<> 144:ef7eb2e8f9f7 190 CEC_TypeDef *Instance; /*!< CEC registers base address */
<> 144:ef7eb2e8f9f7 191
<> 144:ef7eb2e8f9f7 192 CEC_InitTypeDef Init; /*!< CEC communication parameters */
<> 144:ef7eb2e8f9f7 193
<> 144:ef7eb2e8f9f7 194 uint8_t *pTxBuffPtr; /*!< Pointer to CEC Tx transfer Buffer */
<> 144:ef7eb2e8f9f7 195
<> 144:ef7eb2e8f9f7 196 uint16_t TxXferCount; /*!< CEC Tx Transfer Counter */
<> 144:ef7eb2e8f9f7 197
<> 144:ef7eb2e8f9f7 198 uint16_t RxXferSize; /*!< CEC Rx Transfer size, 0: header received only */
<> 144:ef7eb2e8f9f7 199
<> 144:ef7eb2e8f9f7 200 HAL_LockTypeDef Lock; /*!< Locking object */
<> 144:ef7eb2e8f9f7 201
<> 144:ef7eb2e8f9f7 202 HAL_CEC_StateTypeDef gState; /*!< CEC state information related to global Handle management
<> 144:ef7eb2e8f9f7 203 and also related to Tx operations.
<> 144:ef7eb2e8f9f7 204 This parameter can be a value of @ref HAL_CEC_StateTypeDef */
<> 144:ef7eb2e8f9f7 205
<> 144:ef7eb2e8f9f7 206 HAL_CEC_StateTypeDef RxState; /*!< CEC state information related to Rx operations.
<> 144:ef7eb2e8f9f7 207 This parameter can be a value of @ref HAL_CEC_StateTypeDef */
<> 144:ef7eb2e8f9f7 208
<> 144:ef7eb2e8f9f7 209 uint32_t ErrorCode; /*!< For errors handling purposes, copy of ISR register
<> 144:ef7eb2e8f9f7 210 in case error is reported */
<> 144:ef7eb2e8f9f7 211 }CEC_HandleTypeDef;
<> 144:ef7eb2e8f9f7 212 /**
<> 144:ef7eb2e8f9f7 213 * @}
<> 144:ef7eb2e8f9f7 214 */
<> 144:ef7eb2e8f9f7 215
<> 144:ef7eb2e8f9f7 216 /* Exported constants --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 217 /** @defgroup CEC_Exported_Constants CEC Exported Constants
<> 144:ef7eb2e8f9f7 218 * @{
<> 144:ef7eb2e8f9f7 219 */
<> 144:ef7eb2e8f9f7 220
<> 144:ef7eb2e8f9f7 221 /** @defgroup CEC_Error_Code CEC Error Code
<> 144:ef7eb2e8f9f7 222 * @{
<> 144:ef7eb2e8f9f7 223 */
<> 144:ef7eb2e8f9f7 224 #define HAL_CEC_ERROR_NONE (uint32_t) 0x0000U /*!< no error */
<> 144:ef7eb2e8f9f7 225 #define HAL_CEC_ERROR_RXOVR CEC_ISR_RXOVR /*!< CEC Rx-Overrun */
<> 144:ef7eb2e8f9f7 226 #define HAL_CEC_ERROR_BRE CEC_ISR_BRE /*!< CEC Rx Bit Rising Error */
<> 144:ef7eb2e8f9f7 227 #define HAL_CEC_ERROR_SBPE CEC_ISR_SBPE /*!< CEC Rx Short Bit period Error */
<> 144:ef7eb2e8f9f7 228 #define HAL_CEC_ERROR_LBPE CEC_ISR_LBPE /*!< CEC Rx Long Bit period Error */
<> 144:ef7eb2e8f9f7 229 #define HAL_CEC_ERROR_RXACKE CEC_ISR_RXACKE /*!< CEC Rx Missing Acknowledge */
<> 144:ef7eb2e8f9f7 230 #define HAL_CEC_ERROR_ARBLST CEC_ISR_ARBLST /*!< CEC Arbitration Lost */
<> 144:ef7eb2e8f9f7 231 #define HAL_CEC_ERROR_TXUDR CEC_ISR_TXUDR /*!< CEC Tx-Buffer Underrun */
<> 144:ef7eb2e8f9f7 232 #define HAL_CEC_ERROR_TXERR CEC_ISR_TXERR /*!< CEC Tx-Error */
<> 144:ef7eb2e8f9f7 233 #define HAL_CEC_ERROR_TXACKE CEC_ISR_TXACKE /*!< CEC Tx Missing Acknowledge */
<> 144:ef7eb2e8f9f7 234 /**
<> 144:ef7eb2e8f9f7 235 * @}
<> 144:ef7eb2e8f9f7 236 */
<> 144:ef7eb2e8f9f7 237
<> 144:ef7eb2e8f9f7 238 /** @defgroup CEC_Signal_Free_Time CEC Signal Free Time setting parameter
<> 144:ef7eb2e8f9f7 239 * @{
<> 144:ef7eb2e8f9f7 240 */
<> 144:ef7eb2e8f9f7 241 #define CEC_DEFAULT_SFT ((uint32_t)0x00000000U)
<> 144:ef7eb2e8f9f7 242 #define CEC_0_5_BITPERIOD_SFT ((uint32_t)0x00000001U)
<> 144:ef7eb2e8f9f7 243 #define CEC_1_5_BITPERIOD_SFT ((uint32_t)0x00000002U)
<> 144:ef7eb2e8f9f7 244 #define CEC_2_5_BITPERIOD_SFT ((uint32_t)0x00000003U)
<> 144:ef7eb2e8f9f7 245 #define CEC_3_5_BITPERIOD_SFT ((uint32_t)0x00000004U)
<> 144:ef7eb2e8f9f7 246 #define CEC_4_5_BITPERIOD_SFT ((uint32_t)0x00000005U)
<> 144:ef7eb2e8f9f7 247 #define CEC_5_5_BITPERIOD_SFT ((uint32_t)0x00000006U)
<> 144:ef7eb2e8f9f7 248 #define CEC_6_5_BITPERIOD_SFT ((uint32_t)0x00000007U)
<> 144:ef7eb2e8f9f7 249 /**
<> 144:ef7eb2e8f9f7 250 * @}
<> 144:ef7eb2e8f9f7 251 */
<> 144:ef7eb2e8f9f7 252
<> 144:ef7eb2e8f9f7 253 /** @defgroup CEC_Tolerance CEC Receiver Tolerance
<> 144:ef7eb2e8f9f7 254 * @{
<> 144:ef7eb2e8f9f7 255 */
<> 144:ef7eb2e8f9f7 256 #define CEC_STANDARD_TOLERANCE ((uint32_t)0x00000000U)
<> 144:ef7eb2e8f9f7 257 #define CEC_EXTENDED_TOLERANCE ((uint32_t)CEC_CFGR_RXTOL)
<> 144:ef7eb2e8f9f7 258 /**
<> 144:ef7eb2e8f9f7 259 * @}
<> 144:ef7eb2e8f9f7 260 */
<> 144:ef7eb2e8f9f7 261
<> 144:ef7eb2e8f9f7 262 /** @defgroup CEC_BRERxStop CEC Reception Stop on Error
<> 144:ef7eb2e8f9f7 263 * @{
<> 144:ef7eb2e8f9f7 264 */
<> 144:ef7eb2e8f9f7 265 #define CEC_NO_RX_STOP_ON_BRE ((uint32_t)0x00000000U)
<> 144:ef7eb2e8f9f7 266 #define CEC_RX_STOP_ON_BRE ((uint32_t)CEC_CFGR_BRESTP)
<> 144:ef7eb2e8f9f7 267 /**
<> 144:ef7eb2e8f9f7 268 * @}
<> 144:ef7eb2e8f9f7 269 */
<> 144:ef7eb2e8f9f7 270
<> 144:ef7eb2e8f9f7 271 /** @defgroup CEC_BREErrorBitGen CEC Error Bit Generation if Bit Rise Error reported
<> 144:ef7eb2e8f9f7 272 * @{
<> 144:ef7eb2e8f9f7 273 */
<> 144:ef7eb2e8f9f7 274 #define CEC_BRE_ERRORBIT_NO_GENERATION ((uint32_t)0x00000000U)
<> 144:ef7eb2e8f9f7 275 #define CEC_BRE_ERRORBIT_GENERATION ((uint32_t)CEC_CFGR_BREGEN)
<> 144:ef7eb2e8f9f7 276 /**
<> 144:ef7eb2e8f9f7 277 * @}
<> 144:ef7eb2e8f9f7 278 */
<> 144:ef7eb2e8f9f7 279
<> 144:ef7eb2e8f9f7 280 /** @defgroup CEC_LBPEErrorBitGen CEC Error Bit Generation if Long Bit Period Error reported
<> 144:ef7eb2e8f9f7 281 * @{
<> 144:ef7eb2e8f9f7 282 */
<> 144:ef7eb2e8f9f7 283 #define CEC_LBPE_ERRORBIT_NO_GENERATION ((uint32_t)0x00000000U)
<> 144:ef7eb2e8f9f7 284 #define CEC_LBPE_ERRORBIT_GENERATION ((uint32_t)CEC_CFGR_LBPEGEN)
<> 144:ef7eb2e8f9f7 285 /**
<> 144:ef7eb2e8f9f7 286 * @}
<> 144:ef7eb2e8f9f7 287 */
<> 144:ef7eb2e8f9f7 288
<> 144:ef7eb2e8f9f7 289 /** @defgroup CEC_BroadCastMsgErrorBitGen CEC Error Bit Generation on Broadcast message
<> 144:ef7eb2e8f9f7 290 * @{
<> 144:ef7eb2e8f9f7 291 */
<> 144:ef7eb2e8f9f7 292 #define CEC_BROADCASTERROR_ERRORBIT_GENERATION ((uint32_t)0x00000000U)
<> 144:ef7eb2e8f9f7 293 #define CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION ((uint32_t)CEC_CFGR_BRDNOGEN)
<> 144:ef7eb2e8f9f7 294 /**
<> 144:ef7eb2e8f9f7 295 * @}
<> 144:ef7eb2e8f9f7 296 */
<> 144:ef7eb2e8f9f7 297
<> 144:ef7eb2e8f9f7 298 /** @defgroup CEC_SFT_Option CEC Signal Free Time start option
<> 144:ef7eb2e8f9f7 299 * @{
<> 144:ef7eb2e8f9f7 300 */
<> 144:ef7eb2e8f9f7 301 #define CEC_SFT_START_ON_TXSOM ((uint32_t)0x00000000U)
<> 144:ef7eb2e8f9f7 302 #define CEC_SFT_START_ON_TX_RX_END ((uint32_t)CEC_CFGR_SFTOPT)
<> 144:ef7eb2e8f9f7 303 /**
<> 144:ef7eb2e8f9f7 304 * @}
<> 144:ef7eb2e8f9f7 305 */
<> 144:ef7eb2e8f9f7 306
<> 144:ef7eb2e8f9f7 307 /** @defgroup CEC_Listening_Mode CEC Listening mode option
<> 144:ef7eb2e8f9f7 308 * @{
<> 144:ef7eb2e8f9f7 309 */
<> 144:ef7eb2e8f9f7 310 #define CEC_REDUCED_LISTENING_MODE ((uint32_t)0x00000000U)
<> 144:ef7eb2e8f9f7 311 #define CEC_FULL_LISTENING_MODE ((uint32_t)CEC_CFGR_LSTN)
<> 144:ef7eb2e8f9f7 312 /**
<> 144:ef7eb2e8f9f7 313 * @}
<> 144:ef7eb2e8f9f7 314 */
<> 144:ef7eb2e8f9f7 315
<> 144:ef7eb2e8f9f7 316 /** @defgroup CEC_OAR_Position CEC Device Own Address position in CEC CFGR register
<> 144:ef7eb2e8f9f7 317 * @{
<> 144:ef7eb2e8f9f7 318 */
<> 144:ef7eb2e8f9f7 319 #define CEC_CFGR_OAR_LSB_POS ((uint32_t) 16U)
<> 144:ef7eb2e8f9f7 320 /**
<> 144:ef7eb2e8f9f7 321 * @}
<> 144:ef7eb2e8f9f7 322 */
<> 144:ef7eb2e8f9f7 323
<> 144:ef7eb2e8f9f7 324 /** @defgroup CEC_Initiator_Position CEC Initiator logical address position in message header
<> 144:ef7eb2e8f9f7 325 * @{
<> 144:ef7eb2e8f9f7 326 */
<> 144:ef7eb2e8f9f7 327 #define CEC_INITIATOR_LSB_POS ((uint32_t) 4U)
<> 144:ef7eb2e8f9f7 328 /**
<> 144:ef7eb2e8f9f7 329 * @}
<> 144:ef7eb2e8f9f7 330 */
<> 144:ef7eb2e8f9f7 331
<> 144:ef7eb2e8f9f7 332 /** @defgroup CEC_OWN_ADDRESS CEC Own Address
<> 144:ef7eb2e8f9f7 333 * @{
<> 144:ef7eb2e8f9f7 334 */
<> 144:ef7eb2e8f9f7 335 #define CEC_OWN_ADDRESS_NONE ((uint16_t) 0x0000U) /* Reset value */
<> 144:ef7eb2e8f9f7 336 #define CEC_OWN_ADDRESS_0 ((uint16_t) 0x0001U) /* Logical Address 0 */
<> 144:ef7eb2e8f9f7 337 #define CEC_OWN_ADDRESS_1 ((uint16_t) 0x0002U) /* Logical Address 1 */
<> 144:ef7eb2e8f9f7 338 #define CEC_OWN_ADDRESS_2 ((uint16_t) 0x0004U) /* Logical Address 2 */
<> 144:ef7eb2e8f9f7 339 #define CEC_OWN_ADDRESS_3 ((uint16_t) 0x0008U) /* Logical Address 3 */
<> 144:ef7eb2e8f9f7 340 #define CEC_OWN_ADDRESS_4 ((uint16_t) 0x0010U) /* Logical Address 4 */
<> 144:ef7eb2e8f9f7 341 #define CEC_OWN_ADDRESS_5 ((uint16_t) 0x0020U) /* Logical Address 5 */
<> 144:ef7eb2e8f9f7 342 #define CEC_OWN_ADDRESS_6 ((uint16_t) 0x0040U) /* Logical Address 6 */
<> 144:ef7eb2e8f9f7 343 #define CEC_OWN_ADDRESS_7 ((uint16_t) 0x0080U) /* Logical Address 7 */
<> 144:ef7eb2e8f9f7 344 #define CEC_OWN_ADDRESS_8 ((uint16_t) 0x0100U) /* Logical Address 9 */
<> 144:ef7eb2e8f9f7 345 #define CEC_OWN_ADDRESS_9 ((uint16_t) 0x0200U) /* Logical Address 10 */
<> 144:ef7eb2e8f9f7 346 #define CEC_OWN_ADDRESS_10 ((uint16_t) 0x0400U) /* Logical Address 11 */
<> 144:ef7eb2e8f9f7 347 #define CEC_OWN_ADDRESS_11 ((uint16_t) 0x0800U) /* Logical Address 12 */
<> 144:ef7eb2e8f9f7 348 #define CEC_OWN_ADDRESS_12 ((uint16_t) 0x1000U) /* Logical Address 13 */
<> 144:ef7eb2e8f9f7 349 #define CEC_OWN_ADDRESS_13 ((uint16_t) 0x2000U) /* Logical Address 14 */
<> 144:ef7eb2e8f9f7 350 #define CEC_OWN_ADDRESS_14 ((uint16_t) 0x4000U) /* Logical Address 15 */
<> 144:ef7eb2e8f9f7 351 /**
<> 144:ef7eb2e8f9f7 352 * @}
<> 144:ef7eb2e8f9f7 353 */
<> 144:ef7eb2e8f9f7 354
<> 144:ef7eb2e8f9f7 355 /** @defgroup CEC_Interrupts_Definitions CEC Interrupts definition
<> 144:ef7eb2e8f9f7 356 * @{
<> 144:ef7eb2e8f9f7 357 */
<> 144:ef7eb2e8f9f7 358 #define CEC_IT_TXACKE CEC_IER_TXACKEIE
<> 144:ef7eb2e8f9f7 359 #define CEC_IT_TXERR CEC_IER_TXERRIE
<> 144:ef7eb2e8f9f7 360 #define CEC_IT_TXUDR CEC_IER_TXUDRIE
<> 144:ef7eb2e8f9f7 361 #define CEC_IT_TXEND CEC_IER_TXENDIE
<> 144:ef7eb2e8f9f7 362 #define CEC_IT_TXBR CEC_IER_TXBRIE
<> 144:ef7eb2e8f9f7 363 #define CEC_IT_ARBLST CEC_IER_ARBLSTIE
<> 144:ef7eb2e8f9f7 364 #define CEC_IT_RXACKE CEC_IER_RXACKEIE
<> 144:ef7eb2e8f9f7 365 #define CEC_IT_LBPE CEC_IER_LBPEIE
<> 144:ef7eb2e8f9f7 366 #define CEC_IT_SBPE CEC_IER_SBPEIE
<> 144:ef7eb2e8f9f7 367 #define CEC_IT_BRE CEC_IER_BREIE
<> 144:ef7eb2e8f9f7 368 #define CEC_IT_RXOVR CEC_IER_RXOVRIE
<> 144:ef7eb2e8f9f7 369 #define CEC_IT_RXEND CEC_IER_RXENDIE
<> 144:ef7eb2e8f9f7 370 #define CEC_IT_RXBR CEC_IER_RXBRIE
<> 144:ef7eb2e8f9f7 371 /**
<> 144:ef7eb2e8f9f7 372 * @}
<> 144:ef7eb2e8f9f7 373 */
<> 144:ef7eb2e8f9f7 374
<> 144:ef7eb2e8f9f7 375 /** @defgroup CEC_Flags_Definitions CEC Flags definition
<> 144:ef7eb2e8f9f7 376 * @{
<> 144:ef7eb2e8f9f7 377 */
<> 144:ef7eb2e8f9f7 378 #define CEC_FLAG_TXACKE CEC_ISR_TXACKE
<> 144:ef7eb2e8f9f7 379 #define CEC_FLAG_TXERR CEC_ISR_TXERR
<> 144:ef7eb2e8f9f7 380 #define CEC_FLAG_TXUDR CEC_ISR_TXUDR
<> 144:ef7eb2e8f9f7 381 #define CEC_FLAG_TXEND CEC_ISR_TXEND
<> 144:ef7eb2e8f9f7 382 #define CEC_FLAG_TXBR CEC_ISR_TXBR
<> 144:ef7eb2e8f9f7 383 #define CEC_FLAG_ARBLST CEC_ISR_ARBLST
<> 144:ef7eb2e8f9f7 384 #define CEC_FLAG_RXACKE CEC_ISR_RXACKE
<> 144:ef7eb2e8f9f7 385 #define CEC_FLAG_LBPE CEC_ISR_LBPE
<> 144:ef7eb2e8f9f7 386 #define CEC_FLAG_SBPE CEC_ISR_SBPE
<> 144:ef7eb2e8f9f7 387 #define CEC_FLAG_BRE CEC_ISR_BRE
<> 144:ef7eb2e8f9f7 388 #define CEC_FLAG_RXOVR CEC_ISR_RXOVR
<> 144:ef7eb2e8f9f7 389 #define CEC_FLAG_RXEND CEC_ISR_RXEND
<> 144:ef7eb2e8f9f7 390 #define CEC_FLAG_RXBR CEC_ISR_RXBR
<> 144:ef7eb2e8f9f7 391 /**
<> 144:ef7eb2e8f9f7 392 * @}
<> 144:ef7eb2e8f9f7 393 */
<> 144:ef7eb2e8f9f7 394
<> 144:ef7eb2e8f9f7 395 /** @defgroup CEC_ALL_ERROR CEC all RX or TX errors flags
<> 144:ef7eb2e8f9f7 396 * @{
<> 144:ef7eb2e8f9f7 397 */
<> 144:ef7eb2e8f9f7 398 #define CEC_ISR_ALL_ERROR ((uint32_t)CEC_ISR_RXOVR|CEC_ISR_BRE|CEC_ISR_SBPE|CEC_ISR_LBPE|CEC_ISR_RXACKE|\
<> 144:ef7eb2e8f9f7 399 CEC_ISR_ARBLST|CEC_ISR_TXUDR|CEC_ISR_TXERR|CEC_ISR_TXACKE)
<> 144:ef7eb2e8f9f7 400 /**
<> 144:ef7eb2e8f9f7 401 * @}
<> 144:ef7eb2e8f9f7 402 */
<> 144:ef7eb2e8f9f7 403
<> 144:ef7eb2e8f9f7 404 /** @defgroup CEC_IER_ALL_RX CEC all RX errors interrupts enabling flag
<> 144:ef7eb2e8f9f7 405 * @{
<> 144:ef7eb2e8f9f7 406 */
<> 144:ef7eb2e8f9f7 407 #define CEC_IER_RX_ALL_ERR ((uint32_t)CEC_IER_RXACKEIE|CEC_IER_LBPEIE|CEC_IER_SBPEIE|CEC_IER_BREIE|CEC_IER_RXOVRIE)
<> 144:ef7eb2e8f9f7 408 /**
<> 144:ef7eb2e8f9f7 409 * @}
<> 144:ef7eb2e8f9f7 410 */
<> 144:ef7eb2e8f9f7 411
<> 144:ef7eb2e8f9f7 412 /** @defgroup CEC_IER_ALL_TX CEC all TX errors interrupts enabling flag
<> 144:ef7eb2e8f9f7 413 * @{
<> 144:ef7eb2e8f9f7 414 */
<> 144:ef7eb2e8f9f7 415 #define CEC_IER_TX_ALL_ERR ((uint32_t)CEC_IER_TXACKEIE|CEC_IER_TXERRIE|CEC_IER_TXUDRIE|CEC_IER_ARBLSTIE)
<> 144:ef7eb2e8f9f7 416 /**
<> 144:ef7eb2e8f9f7 417 * @}
<> 144:ef7eb2e8f9f7 418 */
<> 144:ef7eb2e8f9f7 419
<> 144:ef7eb2e8f9f7 420 /**
<> 144:ef7eb2e8f9f7 421 * @}
<> 144:ef7eb2e8f9f7 422 */
<> 144:ef7eb2e8f9f7 423
<> 144:ef7eb2e8f9f7 424 /* Exported macros -----------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 425 /** @defgroup CEC_Exported_Macros CEC Exported Macros
<> 144:ef7eb2e8f9f7 426 * @{
<> 144:ef7eb2e8f9f7 427 */
<> 144:ef7eb2e8f9f7 428
<> 144:ef7eb2e8f9f7 429 /** @brief Reset CEC handle gstate & RxState
<> 144:ef7eb2e8f9f7 430 * @param __HANDLE__: CEC handle.
<> 144:ef7eb2e8f9f7 431 * @retval None
<> 144:ef7eb2e8f9f7 432 */
<> 144:ef7eb2e8f9f7 433 #define __HAL_CEC_RESET_HANDLE_STATE(__HANDLE__) do{ \
<> 144:ef7eb2e8f9f7 434 (__HANDLE__)->gState = HAL_CEC_STATE_RESET; \
<> 144:ef7eb2e8f9f7 435 (__HANDLE__)->RxState = HAL_CEC_STATE_RESET; \
<> 144:ef7eb2e8f9f7 436 } while(0)
<> 144:ef7eb2e8f9f7 437
<> 144:ef7eb2e8f9f7 438 /** @brief Checks whether or not the specified CEC interrupt flag is set.
<> 144:ef7eb2e8f9f7 439 * @param __HANDLE__: specifies the CEC Handle.
<> 144:ef7eb2e8f9f7 440 * @param __FLAG__: specifies the flag to check.
<> 144:ef7eb2e8f9f7 441 * @arg CEC_FLAG_TXACKE: Tx Missing acknowledge Error
<> 144:ef7eb2e8f9f7 442 * @arg CEC_FLAG_TXERR: Tx Error.
<> 144:ef7eb2e8f9f7 443 * @arg CEC_FLAG_TXUDR: Tx-Buffer Underrun.
<> 144:ef7eb2e8f9f7 444 * @arg CEC_FLAG_TXEND: End of transmission (successful transmission of the last byte).
<> 144:ef7eb2e8f9f7 445 * @arg CEC_FLAG_TXBR: Tx-Byte Request.
<> 144:ef7eb2e8f9f7 446 * @arg CEC_FLAG_ARBLST: Arbitration Lost
<> 144:ef7eb2e8f9f7 447 * @arg CEC_FLAG_RXACKE: Rx-Missing Acknowledge
<> 144:ef7eb2e8f9f7 448 * @arg CEC_FLAG_LBPE: Rx Long period Error
<> 144:ef7eb2e8f9f7 449 * @arg CEC_FLAG_SBPE: Rx Short period Error
<> 144:ef7eb2e8f9f7 450 * @arg CEC_FLAG_BRE: Rx Bit Rising Error
<> 144:ef7eb2e8f9f7 451 * @arg CEC_FLAG_RXOVR: Rx Overrun.
<> 144:ef7eb2e8f9f7 452 * @arg CEC_FLAG_RXEND: End Of Reception.
<> 144:ef7eb2e8f9f7 453 * @arg CEC_FLAG_RXBR: Rx-Byte Received.
<> 144:ef7eb2e8f9f7 454 * @retval ITStatus
<> 144:ef7eb2e8f9f7 455 */
<> 144:ef7eb2e8f9f7 456 #define __HAL_CEC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR & (__FLAG__))
<> 144:ef7eb2e8f9f7 457
<> 144:ef7eb2e8f9f7 458 /** @brief Clears the interrupt or status flag when raised (write at 1)
<> 144:ef7eb2e8f9f7 459 * @param __HANDLE__: specifies the CEC Handle.
<> 144:ef7eb2e8f9f7 460 * @param __FLAG__: specifies the interrupt/status flag to clear.
<> 144:ef7eb2e8f9f7 461 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 462 * @arg CEC_FLAG_TXACKE: Tx Missing acknowledge Error
<> 144:ef7eb2e8f9f7 463 * @arg CEC_FLAG_TXERR: Tx Error.
<> 144:ef7eb2e8f9f7 464 * @arg CEC_FLAG_TXUDR: Tx-Buffer Underrun.
<> 144:ef7eb2e8f9f7 465 * @arg CEC_FLAG_TXEND: End of transmission (successful transmission of the last byte).
<> 144:ef7eb2e8f9f7 466 * @arg CEC_FLAG_TXBR: Tx-Byte Request.
<> 144:ef7eb2e8f9f7 467 * @arg CEC_FLAG_ARBLST: Arbitration Lost
<> 144:ef7eb2e8f9f7 468 * @arg CEC_FLAG_RXACKE: Rx-Missing Acknowledge
<> 144:ef7eb2e8f9f7 469 * @arg CEC_FLAG_LBPE: Rx Long period Error
<> 144:ef7eb2e8f9f7 470 * @arg CEC_FLAG_SBPE: Rx Short period Error
<> 144:ef7eb2e8f9f7 471 * @arg CEC_FLAG_BRE: Rx Bit Rising Error
<> 144:ef7eb2e8f9f7 472 * @arg CEC_FLAG_RXOVR: Rx Overrun.
<> 144:ef7eb2e8f9f7 473 * @arg CEC_FLAG_RXEND: End Of Reception.
<> 144:ef7eb2e8f9f7 474 * @arg CEC_FLAG_RXBR: Rx-Byte Received.
<> 144:ef7eb2e8f9f7 475 * @retval none
<> 144:ef7eb2e8f9f7 476 */
<> 144:ef7eb2e8f9f7 477 #define __HAL_CEC_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR |= (__FLAG__))
<> 144:ef7eb2e8f9f7 478
<> 144:ef7eb2e8f9f7 479 /** @brief Enables the specified CEC interrupt.
<> 144:ef7eb2e8f9f7 480 * @param __HANDLE__: specifies the CEC Handle.
<> 144:ef7eb2e8f9f7 481 * @param __INTERRUPT__: specifies the CEC interrupt to enable.
<> 144:ef7eb2e8f9f7 482 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 483 * @arg CEC_IT_TXACKE: Tx Missing acknowledge Error IT Enable
<> 144:ef7eb2e8f9f7 484 * @arg CEC_IT_TXERR: Tx Error IT Enable
<> 144:ef7eb2e8f9f7 485 * @arg CEC_IT_TXUDR: Tx-Buffer Underrun IT Enable
<> 144:ef7eb2e8f9f7 486 * @arg CEC_IT_TXEND: End of transmission IT Enable
<> 144:ef7eb2e8f9f7 487 * @arg CEC_IT_TXBR: Tx-Byte Request IT Enable
<> 144:ef7eb2e8f9f7 488 * @arg CEC_IT_ARBLST: Arbitration Lost IT Enable
<> 144:ef7eb2e8f9f7 489 * @arg CEC_IT_RXACKE: Rx-Missing Acknowledge IT Enable
<> 144:ef7eb2e8f9f7 490 * @arg CEC_IT_LBPE: Rx Long period Error IT Enable
<> 144:ef7eb2e8f9f7 491 * @arg CEC_IT_SBPE: Rx Short period Error IT Enable
<> 144:ef7eb2e8f9f7 492 * @arg CEC_IT_BRE: Rx Bit Rising Error IT Enable
<> 144:ef7eb2e8f9f7 493 * @arg CEC_IT_RXOVR: Rx Overrun IT Enable
<> 144:ef7eb2e8f9f7 494 * @arg CEC_IT_RXEND: End Of Reception IT Enable
<> 144:ef7eb2e8f9f7 495 * @arg CEC_IT_RXBR: Rx-Byte Received IT Enable
<> 144:ef7eb2e8f9f7 496 * @retval none
<> 144:ef7eb2e8f9f7 497 */
<> 144:ef7eb2e8f9f7 498 #define __HAL_CEC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
<> 144:ef7eb2e8f9f7 499
<> 144:ef7eb2e8f9f7 500 /** @brief Disables the specified CEC interrupt.
<> 144:ef7eb2e8f9f7 501 * @param __HANDLE__: specifies the CEC Handle.
<> 144:ef7eb2e8f9f7 502 * @param __INTERRUPT__: specifies the CEC interrupt to disable.
<> 144:ef7eb2e8f9f7 503 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 504 * @arg CEC_IT_TXACKE: Tx Missing acknowledge Error IT Enable
<> 144:ef7eb2e8f9f7 505 * @arg CEC_IT_TXERR: Tx Error IT Enable
<> 144:ef7eb2e8f9f7 506 * @arg CEC_IT_TXUDR: Tx-Buffer Underrun IT Enable
<> 144:ef7eb2e8f9f7 507 * @arg CEC_IT_TXEND: End of transmission IT Enable
<> 144:ef7eb2e8f9f7 508 * @arg CEC_IT_TXBR: Tx-Byte Request IT Enable
<> 144:ef7eb2e8f9f7 509 * @arg CEC_IT_ARBLST: Arbitration Lost IT Enable
<> 144:ef7eb2e8f9f7 510 * @arg CEC_IT_RXACKE: Rx-Missing Acknowledge IT Enable
<> 144:ef7eb2e8f9f7 511 * @arg CEC_IT_LBPE: Rx Long period Error IT Enable
<> 144:ef7eb2e8f9f7 512 * @arg CEC_IT_SBPE: Rx Short period Error IT Enable
<> 144:ef7eb2e8f9f7 513 * @arg CEC_IT_BRE: Rx Bit Rising Error IT Enable
<> 144:ef7eb2e8f9f7 514 * @arg CEC_IT_RXOVR: Rx Overrun IT Enable
<> 144:ef7eb2e8f9f7 515 * @arg CEC_IT_RXEND: End Of Reception IT Enable
<> 144:ef7eb2e8f9f7 516 * @arg CEC_IT_RXBR: Rx-Byte Received IT Enable
<> 144:ef7eb2e8f9f7 517 * @retval none
<> 144:ef7eb2e8f9f7 518 */
<> 144:ef7eb2e8f9f7 519 #define __HAL_CEC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__)))
<> 144:ef7eb2e8f9f7 520
<> 144:ef7eb2e8f9f7 521 /** @brief Checks whether or not the specified CEC interrupt is enabled.
<> 144:ef7eb2e8f9f7 522 * @param __HANDLE__: specifies the CEC Handle.
<> 144:ef7eb2e8f9f7 523 * @param __INTERRUPT__: specifies the CEC interrupt to check.
<> 144:ef7eb2e8f9f7 524 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 525 * @arg CEC_IT_TXACKE: Tx Missing acknowledge Error IT Enable
<> 144:ef7eb2e8f9f7 526 * @arg CEC_IT_TXERR: Tx Error IT Enable
<> 144:ef7eb2e8f9f7 527 * @arg CEC_IT_TXUDR: Tx-Buffer Underrun IT Enable
<> 144:ef7eb2e8f9f7 528 * @arg CEC_IT_TXEND: End of transmission IT Enable
<> 144:ef7eb2e8f9f7 529 * @arg CEC_IT_TXBR: Tx-Byte Request IT Enable
<> 144:ef7eb2e8f9f7 530 * @arg CEC_IT_ARBLST: Arbitration Lost IT Enable
<> 144:ef7eb2e8f9f7 531 * @arg CEC_IT_RXACKE: Rx-Missing Acknowledge IT Enable
<> 144:ef7eb2e8f9f7 532 * @arg CEC_IT_LBPE: Rx Long period Error IT Enable
<> 144:ef7eb2e8f9f7 533 * @arg CEC_IT_SBPE: Rx Short period Error IT Enable
<> 144:ef7eb2e8f9f7 534 * @arg CEC_IT_BRE: Rx Bit Rising Error IT Enable
<> 144:ef7eb2e8f9f7 535 * @arg CEC_IT_RXOVR: Rx Overrun IT Enable
<> 144:ef7eb2e8f9f7 536 * @arg CEC_IT_RXEND: End Of Reception IT Enable
<> 144:ef7eb2e8f9f7 537 * @arg CEC_IT_RXBR: Rx-Byte Received IT Enable
<> 144:ef7eb2e8f9f7 538 * @retval FlagStatus
<> 144:ef7eb2e8f9f7 539 */
<> 144:ef7eb2e8f9f7 540 #define __HAL_CEC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER & (__INTERRUPT__))
<> 144:ef7eb2e8f9f7 541
<> 144:ef7eb2e8f9f7 542 /** @brief Enables the CEC device
<> 144:ef7eb2e8f9f7 543 * @param __HANDLE__: specifies the CEC Handle.
<> 144:ef7eb2e8f9f7 544 * @retval none
<> 144:ef7eb2e8f9f7 545 */
<> 144:ef7eb2e8f9f7 546 #define __HAL_CEC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= CEC_CR_CECEN)
<> 144:ef7eb2e8f9f7 547
<> 144:ef7eb2e8f9f7 548 /** @brief Disables the CEC device
<> 144:ef7eb2e8f9f7 549 * @param __HANDLE__: specifies the CEC Handle.
<> 144:ef7eb2e8f9f7 550 * @retval none
<> 144:ef7eb2e8f9f7 551 */
<> 144:ef7eb2e8f9f7 552 #define __HAL_CEC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~CEC_CR_CECEN)
<> 144:ef7eb2e8f9f7 553
<> 144:ef7eb2e8f9f7 554 /** @brief Set Transmission Start flag
<> 144:ef7eb2e8f9f7 555 * @param __HANDLE__: specifies the CEC Handle.
<> 144:ef7eb2e8f9f7 556 * @retval none
<> 144:ef7eb2e8f9f7 557 */
<> 144:ef7eb2e8f9f7 558 #define __HAL_CEC_FIRST_BYTE_TX_SET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CEC_CR_TXSOM)
<> 144:ef7eb2e8f9f7 559
<> 144:ef7eb2e8f9f7 560 /** @brief Set Transmission End flag
<> 144:ef7eb2e8f9f7 561 * @param __HANDLE__: specifies the CEC Handle.
<> 144:ef7eb2e8f9f7 562 * @retval none
<> 144:ef7eb2e8f9f7 563 * If the CEC message consists of only one byte, TXEOM must be set before of TXSOM.
<> 144:ef7eb2e8f9f7 564 */
<> 144:ef7eb2e8f9f7 565 #define __HAL_CEC_LAST_BYTE_TX_SET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CEC_CR_TXEOM)
<> 144:ef7eb2e8f9f7 566
<> 144:ef7eb2e8f9f7 567 /** @brief Get Transmission Start flag
<> 144:ef7eb2e8f9f7 568 * @param __HANDLE__: specifies the CEC Handle.
<> 144:ef7eb2e8f9f7 569 * @retval FlagStatus
<> 144:ef7eb2e8f9f7 570 */
<> 144:ef7eb2e8f9f7 571 #define __HAL_CEC_GET_TRANSMISSION_START_FLAG(__HANDLE__) ((__HANDLE__)->Instance->CR & CEC_CR_TXSOM)
<> 144:ef7eb2e8f9f7 572
<> 144:ef7eb2e8f9f7 573 /** @brief Get Transmission End flag
<> 144:ef7eb2e8f9f7 574 * @param __HANDLE__: specifies the CEC Handle.
<> 144:ef7eb2e8f9f7 575 * @retval FlagStatus
<> 144:ef7eb2e8f9f7 576 */
<> 144:ef7eb2e8f9f7 577 #define __HAL_CEC_GET_TRANSMISSION_END_FLAG(__HANDLE__) ((__HANDLE__)->Instance->CR & CEC_CR_TXEOM)
<> 144:ef7eb2e8f9f7 578
<> 144:ef7eb2e8f9f7 579 /** @brief Clear OAR register
<> 144:ef7eb2e8f9f7 580 * @param __HANDLE__: specifies the CEC Handle.
<> 144:ef7eb2e8f9f7 581 * @retval none
<> 144:ef7eb2e8f9f7 582 */
<> 144:ef7eb2e8f9f7 583 #define __HAL_CEC_CLEAR_OAR(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CFGR, CEC_CFGR_OAR)
<> 144:ef7eb2e8f9f7 584
<> 144:ef7eb2e8f9f7 585 /** @brief Set OAR register (without resetting previously set address in case of multi-address mode)
<> 144:ef7eb2e8f9f7 586 * To reset OAR, __HAL_CEC_CLEAR_OAR() needs to be called beforehand
<> 144:ef7eb2e8f9f7 587 * @param __HANDLE__: specifies the CEC Handle.
<> 144:ef7eb2e8f9f7 588 * @param __ADDRESS__: Own Address value (CEC logical address is identified by bit position)
<> 144:ef7eb2e8f9f7 589 * @retval none
<> 144:ef7eb2e8f9f7 590 */
<> 144:ef7eb2e8f9f7 591 #define __HAL_CEC_SET_OAR(__HANDLE__,__ADDRESS__) SET_BIT((__HANDLE__)->Instance->CFGR, (__ADDRESS__)<< CEC_CFGR_OAR_LSB_POS)
<> 144:ef7eb2e8f9f7 592
<> 144:ef7eb2e8f9f7 593 /**
<> 144:ef7eb2e8f9f7 594 * @}
<> 144:ef7eb2e8f9f7 595 */
<> 144:ef7eb2e8f9f7 596
<> 144:ef7eb2e8f9f7 597 /* Exported functions --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 598 /** @addtogroup CEC_Exported_Functions
<> 144:ef7eb2e8f9f7 599 * @{
<> 144:ef7eb2e8f9f7 600 */
<> 144:ef7eb2e8f9f7 601
<> 144:ef7eb2e8f9f7 602 /** @addtogroup CEC_Exported_Functions_Group1
<> 144:ef7eb2e8f9f7 603 * @{
<> 144:ef7eb2e8f9f7 604 */
<> 144:ef7eb2e8f9f7 605 /* Initialization and de-initialization functions ****************************/
<> 144:ef7eb2e8f9f7 606 HAL_StatusTypeDef HAL_CEC_Init(CEC_HandleTypeDef *hcec);
<> 144:ef7eb2e8f9f7 607 HAL_StatusTypeDef HAL_CEC_DeInit(CEC_HandleTypeDef *hcec);
<> 144:ef7eb2e8f9f7 608 HAL_StatusTypeDef HAL_CEC_SetDeviceAddress(CEC_HandleTypeDef *hcec, uint16_t CEC_OwnAddress);
<> 144:ef7eb2e8f9f7 609 void HAL_CEC_MspInit(CEC_HandleTypeDef *hcec);
<> 144:ef7eb2e8f9f7 610 void HAL_CEC_MspDeInit(CEC_HandleTypeDef *hcec);
<> 144:ef7eb2e8f9f7 611 /**
<> 144:ef7eb2e8f9f7 612 * @}
<> 144:ef7eb2e8f9f7 613 */
<> 144:ef7eb2e8f9f7 614
<> 144:ef7eb2e8f9f7 615 /** @addtogroup CEC_Exported_Functions_Group2
<> 144:ef7eb2e8f9f7 616 * @{
<> 144:ef7eb2e8f9f7 617 */
<> 144:ef7eb2e8f9f7 618 /* I/O operation functions ***************************************************/
<> 144:ef7eb2e8f9f7 619 HAL_StatusTypeDef HAL_CEC_Transmit_IT(CEC_HandleTypeDef *hcec, uint8_t InitiatorAddress,uint8_t DestinationAddress, uint8_t *pData, uint32_t Size);
<> 144:ef7eb2e8f9f7 620 uint32_t HAL_CEC_GetLastReceivedFrameSize(CEC_HandleTypeDef *hcec);
<> 144:ef7eb2e8f9f7 621 void HAL_CEC_ChangeRxBuffer(CEC_HandleTypeDef *hcec, uint8_t* Rxbuffer);
<> 144:ef7eb2e8f9f7 622 void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec);
<> 144:ef7eb2e8f9f7 623 void HAL_CEC_TxCpltCallback(CEC_HandleTypeDef *hcec);
<> 144:ef7eb2e8f9f7 624 void HAL_CEC_RxCpltCallback(CEC_HandleTypeDef *hcec, uint32_t RxFrameSize);
<> 144:ef7eb2e8f9f7 625 void HAL_CEC_ErrorCallback(CEC_HandleTypeDef *hcec);
<> 144:ef7eb2e8f9f7 626 /**
<> 144:ef7eb2e8f9f7 627 * @}
<> 144:ef7eb2e8f9f7 628 */
<> 144:ef7eb2e8f9f7 629
<> 144:ef7eb2e8f9f7 630 /** @addtogroup CEC_Exported_Functions_Group3
<> 144:ef7eb2e8f9f7 631 * @{
<> 144:ef7eb2e8f9f7 632 */
<> 144:ef7eb2e8f9f7 633 /* Peripheral State functions ************************************************/
<> 144:ef7eb2e8f9f7 634 HAL_CEC_StateTypeDef HAL_CEC_GetState(CEC_HandleTypeDef *hcec);
<> 144:ef7eb2e8f9f7 635 uint32_t HAL_CEC_GetError(CEC_HandleTypeDef *hcec);
<> 144:ef7eb2e8f9f7 636 /**
<> 144:ef7eb2e8f9f7 637 * @}
<> 144:ef7eb2e8f9f7 638 */
<> 144:ef7eb2e8f9f7 639
<> 144:ef7eb2e8f9f7 640 /**
<> 144:ef7eb2e8f9f7 641 * @}
<> 144:ef7eb2e8f9f7 642 */
<> 144:ef7eb2e8f9f7 643
<> 144:ef7eb2e8f9f7 644 /* Private types -------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 645 /** @defgroup CEC_Private_Types CEC Private Types
<> 144:ef7eb2e8f9f7 646 * @{
<> 144:ef7eb2e8f9f7 647 */
<> 144:ef7eb2e8f9f7 648
<> 144:ef7eb2e8f9f7 649 /**
<> 144:ef7eb2e8f9f7 650 * @}
<> 144:ef7eb2e8f9f7 651 */
<> 144:ef7eb2e8f9f7 652
<> 144:ef7eb2e8f9f7 653 /* Private variables ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 654 /** @defgroup CEC_Private_Variables CEC Private Variables
<> 144:ef7eb2e8f9f7 655 * @{
<> 144:ef7eb2e8f9f7 656 */
<> 144:ef7eb2e8f9f7 657
<> 144:ef7eb2e8f9f7 658 /**
<> 144:ef7eb2e8f9f7 659 * @}
<> 144:ef7eb2e8f9f7 660 */
<> 144:ef7eb2e8f9f7 661
<> 144:ef7eb2e8f9f7 662 /* Private constants ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 663 /** @defgroup CEC_Private_Constants CEC Private Constants
<> 144:ef7eb2e8f9f7 664 * @{
<> 144:ef7eb2e8f9f7 665 */
<> 144:ef7eb2e8f9f7 666
<> 144:ef7eb2e8f9f7 667 /**
<> 144:ef7eb2e8f9f7 668 * @}
<> 144:ef7eb2e8f9f7 669 */
<> 144:ef7eb2e8f9f7 670
<> 144:ef7eb2e8f9f7 671 /* Private macros ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 672 /** @defgroup CEC_Private_Macros CEC Private Macros
<> 144:ef7eb2e8f9f7 673 * @{
<> 144:ef7eb2e8f9f7 674 */
<> 144:ef7eb2e8f9f7 675
<> 144:ef7eb2e8f9f7 676 #define IS_CEC_SIGNALFREETIME(__SFT__) ((__SFT__) <= CEC_CFGR_SFT)
<> 144:ef7eb2e8f9f7 677
<> 144:ef7eb2e8f9f7 678 #define IS_CEC_TOLERANCE(__RXTOL__) (((__RXTOL__) == CEC_STANDARD_TOLERANCE) || \
<> 144:ef7eb2e8f9f7 679 ((__RXTOL__) == CEC_EXTENDED_TOLERANCE))
<> 144:ef7eb2e8f9f7 680
<> 144:ef7eb2e8f9f7 681 #define IS_CEC_BRERXSTOP(__BRERXSTOP__) (((__BRERXSTOP__) == CEC_NO_RX_STOP_ON_BRE) || \
<> 144:ef7eb2e8f9f7 682 ((__BRERXSTOP__) == CEC_RX_STOP_ON_BRE))
<> 144:ef7eb2e8f9f7 683
<> 144:ef7eb2e8f9f7 684 #define IS_CEC_BREERRORBITGEN(__ERRORBITGEN__) (((__ERRORBITGEN__) == CEC_BRE_ERRORBIT_NO_GENERATION) || \
<> 144:ef7eb2e8f9f7 685 ((__ERRORBITGEN__) == CEC_BRE_ERRORBIT_GENERATION))
<> 144:ef7eb2e8f9f7 686
<> 144:ef7eb2e8f9f7 687 #define IS_CEC_LBPEERRORBITGEN(__ERRORBITGEN__) (((__ERRORBITGEN__) == CEC_LBPE_ERRORBIT_NO_GENERATION) || \
<> 144:ef7eb2e8f9f7 688 ((__ERRORBITGEN__) == CEC_LBPE_ERRORBIT_GENERATION))
<> 144:ef7eb2e8f9f7 689
<> 144:ef7eb2e8f9f7 690 #define IS_CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION(__ERRORBITGEN__) (((__ERRORBITGEN__) == CEC_BROADCASTERROR_ERRORBIT_GENERATION) || \
<> 144:ef7eb2e8f9f7 691 ((__ERRORBITGEN__) == CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION))
<> 144:ef7eb2e8f9f7 692
<> 144:ef7eb2e8f9f7 693 #define IS_CEC_SFTOP(__SFTOP__) (((__SFTOP__) == CEC_SFT_START_ON_TXSOM) || \
<> 144:ef7eb2e8f9f7 694 ((__SFTOP__) == CEC_SFT_START_ON_TX_RX_END))
<> 144:ef7eb2e8f9f7 695
<> 144:ef7eb2e8f9f7 696 #define IS_CEC_LISTENING_MODE(__MODE__) (((__MODE__) == CEC_REDUCED_LISTENING_MODE) || \
<> 144:ef7eb2e8f9f7 697 ((__MODE__) == CEC_FULL_LISTENING_MODE))
<> 144:ef7eb2e8f9f7 698
<> 144:ef7eb2e8f9f7 699 /** @brief Check CEC message size.
<> 144:ef7eb2e8f9f7 700 * The message size is the payload size: without counting the header,
<> 144:ef7eb2e8f9f7 701 * it varies from 0 byte (ping operation, one header only, no payload) to
<> 144:ef7eb2e8f9f7 702 * 15 bytes (1 opcode and up to 14 operands following the header).
<> 144:ef7eb2e8f9f7 703 * @param __SIZE__: CEC message size.
<> 144:ef7eb2e8f9f7 704 * @retval Test result (TRUE or FALSE).
<> 144:ef7eb2e8f9f7 705 */
<> 144:ef7eb2e8f9f7 706 #define IS_CEC_MSGSIZE(__SIZE__) ((__SIZE__) <= 0x10)
<> 144:ef7eb2e8f9f7 707
<> 144:ef7eb2e8f9f7 708 /** @brief Check CEC device Own Address Register (OAR) setting.
<> 144:ef7eb2e8f9f7 709 * OAR address is written in a 15-bit field within CEC_CFGR register.
<> 144:ef7eb2e8f9f7 710 * @param __ADDRESS__: CEC own address.
<> 144:ef7eb2e8f9f7 711 * @retval Test result (TRUE or FALSE).
<> 144:ef7eb2e8f9f7 712 */
<> 144:ef7eb2e8f9f7 713 #define IS_CEC_OWN_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0x7FFF)
<> 144:ef7eb2e8f9f7 714
<> 144:ef7eb2e8f9f7 715 /** @brief Check CEC initiator or destination logical address setting.
<> 144:ef7eb2e8f9f7 716 * Initiator and destination addresses are coded over 4 bits.
<> 144:ef7eb2e8f9f7 717 * @param __ADDRESS__: CEC initiator or logical address.
<> 144:ef7eb2e8f9f7 718 * @retval Test result (TRUE or FALSE).
<> 144:ef7eb2e8f9f7 719 */
<> 144:ef7eb2e8f9f7 720 #define IS_CEC_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0xF)
<> 144:ef7eb2e8f9f7 721 /**
<> 144:ef7eb2e8f9f7 722 * @}
<> 144:ef7eb2e8f9f7 723 */
<> 144:ef7eb2e8f9f7 724 /* Private functions ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 725 /** @defgroup CEC_Private_Functions CEC Private Functions
<> 144:ef7eb2e8f9f7 726 * @{
<> 144:ef7eb2e8f9f7 727 */
<> 144:ef7eb2e8f9f7 728
<> 144:ef7eb2e8f9f7 729 /**
<> 144:ef7eb2e8f9f7 730 * @}
<> 144:ef7eb2e8f9f7 731 */
<> 144:ef7eb2e8f9f7 732
<> 144:ef7eb2e8f9f7 733 /**
<> 144:ef7eb2e8f9f7 734 * @}
<> 144:ef7eb2e8f9f7 735 */
<> 144:ef7eb2e8f9f7 736
<> 144:ef7eb2e8f9f7 737 /**
<> 144:ef7eb2e8f9f7 738 * @}
<> 144:ef7eb2e8f9f7 739 */
<> 144:ef7eb2e8f9f7 740
<> 144:ef7eb2e8f9f7 741 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 742 }
<> 144:ef7eb2e8f9f7 743 #endif
<> 144:ef7eb2e8f9f7 744
<> 144:ef7eb2e8f9f7 745 #endif /* __STM32F7xx_HAL_CEC_H */
<> 144:ef7eb2e8f9f7 746
<> 144:ef7eb2e8f9f7 747 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/