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targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_rng.h@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
Parent:
181:57724642e740 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32l4xx_ll_rng.h
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @brief Header file of RNG LL module.
<> 144:ef7eb2e8f9f7 6 ******************************************************************************
<> 144:ef7eb2e8f9f7 7 * @attention
<> 144:ef7eb2e8f9f7 8 *
AnnaBridge 167:e84263d55307 9 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 12 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 13 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 14 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 15 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 16 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 17 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 18 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 19 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 20 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 21 *
<> 144:ef7eb2e8f9f7 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 32 *
<> 144:ef7eb2e8f9f7 33 ******************************************************************************
<> 144:ef7eb2e8f9f7 34 */
<> 144:ef7eb2e8f9f7 35
<> 144:ef7eb2e8f9f7 36 /* Define to prevent recursive inclusion -------------------------------------*/
<> 144:ef7eb2e8f9f7 37 #ifndef __STM32L4xx_LL_RNG_H
<> 144:ef7eb2e8f9f7 38 #define __STM32L4xx_LL_RNG_H
<> 144:ef7eb2e8f9f7 39
<> 144:ef7eb2e8f9f7 40 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 41 extern "C" {
<> 144:ef7eb2e8f9f7 42 #endif
<> 144:ef7eb2e8f9f7 43
<> 144:ef7eb2e8f9f7 44 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 45 #include "stm32l4xx.h"
<> 144:ef7eb2e8f9f7 46
<> 144:ef7eb2e8f9f7 47 /** @addtogroup STM32L4xx_LL_Driver
<> 144:ef7eb2e8f9f7 48 * @{
<> 144:ef7eb2e8f9f7 49 */
<> 144:ef7eb2e8f9f7 50
<> 144:ef7eb2e8f9f7 51 #if defined(RNG)
<> 144:ef7eb2e8f9f7 52
<> 144:ef7eb2e8f9f7 53 /** @defgroup RNG_LL RNG
<> 144:ef7eb2e8f9f7 54 * @{
<> 144:ef7eb2e8f9f7 55 */
<> 144:ef7eb2e8f9f7 56
<> 144:ef7eb2e8f9f7 57 /* Private types -------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 58 /* Private variables ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 59 /* Private constants ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 60 /* Private macros ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 61
<> 144:ef7eb2e8f9f7 62 /* Exported types ------------------------------------------------------------*/
AnnaBridge 181:57724642e740 63 #if defined(USE_FULL_LL_DRIVER)
AnnaBridge 181:57724642e740 64 /** @defgroup RNG_LL_ES_Init_Struct RNG Exported Init structures
AnnaBridge 181:57724642e740 65 * @{
AnnaBridge 181:57724642e740 66 */
AnnaBridge 181:57724642e740 67
AnnaBridge 181:57724642e740 68
AnnaBridge 181:57724642e740 69 #if defined(RNG_CR_CED)
AnnaBridge 181:57724642e740 70 /**
AnnaBridge 181:57724642e740 71 * @brief LL RNG Init Structure Definition
AnnaBridge 181:57724642e740 72 */
AnnaBridge 181:57724642e740 73 typedef struct
AnnaBridge 181:57724642e740 74 {
AnnaBridge 181:57724642e740 75 uint32_t ClockErrorDetection; /*!< Clock error detection.
AnnaBridge 181:57724642e740 76 This parameter can be one value of @ref RNG_LL_CED.
AnnaBridge 181:57724642e740 77
AnnaBridge 181:57724642e740 78 This parameter can be modified using unitary functions @ref LL_RNG_EnableClkErrorDetect(). */
AnnaBridge 181:57724642e740 79 }LL_RNG_InitTypeDef;
AnnaBridge 181:57724642e740 80 #endif /* defined(RNG_CR_CED) */
AnnaBridge 181:57724642e740 81
AnnaBridge 181:57724642e740 82 /**
AnnaBridge 181:57724642e740 83 * @}
AnnaBridge 181:57724642e740 84 */
AnnaBridge 181:57724642e740 85 #endif /* USE_FULL_LL_DRIVER */
AnnaBridge 181:57724642e740 86
<> 144:ef7eb2e8f9f7 87 /* Exported constants --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 88 /** @defgroup RNG_LL_Exported_Constants RNG Exported Constants
<> 144:ef7eb2e8f9f7 89 * @{
<> 144:ef7eb2e8f9f7 90 */
AnnaBridge 181:57724642e740 91
AnnaBridge 181:57724642e740 92 #if defined(RNG_CR_CED)
AnnaBridge 181:57724642e740 93 /** @defgroup RNG_LL_CED Clock Error Detection
AnnaBridge 181:57724642e740 94 * @{
AnnaBridge 181:57724642e740 95 */
AnnaBridge 181:57724642e740 96 #define LL_RNG_CED_ENABLE 0x00000000U /*!< Clock error detection enabled */
AnnaBridge 181:57724642e740 97 #define LL_RNG_CED_DISABLE RNG_CR_CED /*!< Clock error detection disabled */
AnnaBridge 181:57724642e740 98 /**
AnnaBridge 181:57724642e740 99 * @}
AnnaBridge 181:57724642e740 100 */
AnnaBridge 181:57724642e740 101 #endif /* defined(RNG_CR_CED) */
<> 144:ef7eb2e8f9f7 102
AnnaBridge 181:57724642e740 103
<> 144:ef7eb2e8f9f7 104 /** @defgroup RNG_LL_EC_GET_FLAG Get Flags Defines
<> 144:ef7eb2e8f9f7 105 * @brief Flags defines which can be used with LL_RNG_ReadReg function
<> 144:ef7eb2e8f9f7 106 * @{
<> 144:ef7eb2e8f9f7 107 */
<> 144:ef7eb2e8f9f7 108 #define LL_RNG_SR_DRDY RNG_SR_DRDY /*!< Register contains valid random data */
<> 144:ef7eb2e8f9f7 109 #define LL_RNG_SR_CECS RNG_SR_CECS /*!< Clock error current status */
<> 144:ef7eb2e8f9f7 110 #define LL_RNG_SR_SECS RNG_SR_SECS /*!< Seed error current status */
<> 144:ef7eb2e8f9f7 111 #define LL_RNG_SR_CEIS RNG_SR_CEIS /*!< Clock error interrupt status */
<> 144:ef7eb2e8f9f7 112 #define LL_RNG_SR_SEIS RNG_SR_SEIS /*!< Seed error interrupt status */
<> 144:ef7eb2e8f9f7 113 /**
<> 144:ef7eb2e8f9f7 114 * @}
<> 144:ef7eb2e8f9f7 115 */
<> 144:ef7eb2e8f9f7 116
<> 144:ef7eb2e8f9f7 117 /** @defgroup RNG_LL_EC_IT IT Defines
<> 144:ef7eb2e8f9f7 118 * @brief IT defines which can be used with LL_RNG_ReadReg and LL_RNG_WriteReg macros
<> 144:ef7eb2e8f9f7 119 * @{
<> 144:ef7eb2e8f9f7 120 */
<> 144:ef7eb2e8f9f7 121 #define LL_RNG_CR_IE RNG_CR_IE /*!< RNG Interrupt enable */
<> 144:ef7eb2e8f9f7 122 /**
<> 144:ef7eb2e8f9f7 123 * @}
<> 144:ef7eb2e8f9f7 124 */
<> 144:ef7eb2e8f9f7 125
<> 144:ef7eb2e8f9f7 126 /**
<> 144:ef7eb2e8f9f7 127 * @}
<> 144:ef7eb2e8f9f7 128 */
<> 144:ef7eb2e8f9f7 129
<> 144:ef7eb2e8f9f7 130 /* Exported macro ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 131 /** @defgroup RNG_LL_Exported_Macros RNG Exported Macros
<> 144:ef7eb2e8f9f7 132 * @{
<> 144:ef7eb2e8f9f7 133 */
<> 144:ef7eb2e8f9f7 134
<> 144:ef7eb2e8f9f7 135 /** @defgroup RNG_LL_EM_WRITE_READ Common Write and read registers Macros
<> 144:ef7eb2e8f9f7 136 * @{
<> 144:ef7eb2e8f9f7 137 */
<> 144:ef7eb2e8f9f7 138
<> 144:ef7eb2e8f9f7 139 /**
<> 144:ef7eb2e8f9f7 140 * @brief Write a value in RNG register
<> 144:ef7eb2e8f9f7 141 * @param __INSTANCE__ RNG Instance
<> 144:ef7eb2e8f9f7 142 * @param __REG__ Register to be written
<> 144:ef7eb2e8f9f7 143 * @param __VALUE__ Value to be written in the register
<> 144:ef7eb2e8f9f7 144 * @retval None
<> 144:ef7eb2e8f9f7 145 */
<> 144:ef7eb2e8f9f7 146 #define LL_RNG_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
<> 144:ef7eb2e8f9f7 147
<> 144:ef7eb2e8f9f7 148 /**
<> 144:ef7eb2e8f9f7 149 * @brief Read a value in RNG register
<> 144:ef7eb2e8f9f7 150 * @param __INSTANCE__ RNG Instance
<> 144:ef7eb2e8f9f7 151 * @param __REG__ Register to be read
<> 144:ef7eb2e8f9f7 152 * @retval Register value
<> 144:ef7eb2e8f9f7 153 */
<> 144:ef7eb2e8f9f7 154 #define LL_RNG_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
<> 144:ef7eb2e8f9f7 155 /**
<> 144:ef7eb2e8f9f7 156 * @}
<> 144:ef7eb2e8f9f7 157 */
<> 144:ef7eb2e8f9f7 158
<> 144:ef7eb2e8f9f7 159 /**
<> 144:ef7eb2e8f9f7 160 * @}
<> 144:ef7eb2e8f9f7 161 */
<> 144:ef7eb2e8f9f7 162
<> 144:ef7eb2e8f9f7 163
<> 144:ef7eb2e8f9f7 164 /* Exported functions --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 165 /** @defgroup RNG_LL_Exported_Functions RNG Exported Functions
<> 144:ef7eb2e8f9f7 166 * @{
<> 144:ef7eb2e8f9f7 167 */
<> 144:ef7eb2e8f9f7 168 /** @defgroup RNG_LL_EF_Configuration RNG Configuration functions
<> 144:ef7eb2e8f9f7 169 * @{
<> 144:ef7eb2e8f9f7 170 */
<> 144:ef7eb2e8f9f7 171
<> 144:ef7eb2e8f9f7 172 /**
<> 144:ef7eb2e8f9f7 173 * @brief Enable Random Number Generation
<> 144:ef7eb2e8f9f7 174 * @rmtoll CR RNGEN LL_RNG_Enable
<> 144:ef7eb2e8f9f7 175 * @param RNGx RNG Instance
<> 144:ef7eb2e8f9f7 176 * @retval None
<> 144:ef7eb2e8f9f7 177 */
<> 144:ef7eb2e8f9f7 178 __STATIC_INLINE void LL_RNG_Enable(RNG_TypeDef *RNGx)
<> 144:ef7eb2e8f9f7 179 {
<> 144:ef7eb2e8f9f7 180 SET_BIT(RNGx->CR, RNG_CR_RNGEN);
<> 144:ef7eb2e8f9f7 181 }
<> 144:ef7eb2e8f9f7 182
<> 144:ef7eb2e8f9f7 183 /**
<> 144:ef7eb2e8f9f7 184 * @brief Disable Random Number Generation
<> 144:ef7eb2e8f9f7 185 * @rmtoll CR RNGEN LL_RNG_Disable
<> 144:ef7eb2e8f9f7 186 * @param RNGx RNG Instance
<> 144:ef7eb2e8f9f7 187 * @retval None
<> 144:ef7eb2e8f9f7 188 */
<> 144:ef7eb2e8f9f7 189 __STATIC_INLINE void LL_RNG_Disable(RNG_TypeDef *RNGx)
<> 144:ef7eb2e8f9f7 190 {
<> 144:ef7eb2e8f9f7 191 CLEAR_BIT(RNGx->CR, RNG_CR_RNGEN);
<> 144:ef7eb2e8f9f7 192 }
<> 144:ef7eb2e8f9f7 193
<> 144:ef7eb2e8f9f7 194 /**
<> 144:ef7eb2e8f9f7 195 * @brief Check if Random Number Generator is enabled
<> 144:ef7eb2e8f9f7 196 * @rmtoll CR RNGEN LL_RNG_IsEnabled
<> 144:ef7eb2e8f9f7 197 * @param RNGx RNG Instance
<> 144:ef7eb2e8f9f7 198 * @retval State of bit (1 or 0).
<> 144:ef7eb2e8f9f7 199 */
<> 144:ef7eb2e8f9f7 200 __STATIC_INLINE uint32_t LL_RNG_IsEnabled(RNG_TypeDef *RNGx)
<> 144:ef7eb2e8f9f7 201 {
<> 144:ef7eb2e8f9f7 202 return (READ_BIT(RNGx->CR, RNG_CR_RNGEN) == (RNG_CR_RNGEN));
<> 144:ef7eb2e8f9f7 203 }
<> 144:ef7eb2e8f9f7 204
AnnaBridge 181:57724642e740 205 #if defined(RNG_CR_CED)
AnnaBridge 181:57724642e740 206 /**
AnnaBridge 181:57724642e740 207 * @brief Enable RNG Clock Error Detection
AnnaBridge 181:57724642e740 208 * @rmtoll CR CED LL_RNG_EnableClkErrorDetect
AnnaBridge 181:57724642e740 209 * @param RNGx RNG Instance
AnnaBridge 181:57724642e740 210 * @retval None
AnnaBridge 181:57724642e740 211 */
AnnaBridge 181:57724642e740 212 __STATIC_INLINE void LL_RNG_EnableClkErrorDetect(RNG_TypeDef *RNGx)
AnnaBridge 181:57724642e740 213 {
AnnaBridge 181:57724642e740 214 CLEAR_BIT(RNGx->CR, RNG_CR_CED);
AnnaBridge 181:57724642e740 215 }
AnnaBridge 181:57724642e740 216
AnnaBridge 181:57724642e740 217 /**
AnnaBridge 181:57724642e740 218 * @brief Disable RNG Clock Error Detection
AnnaBridge 181:57724642e740 219 * @rmtoll CR CED LL_RNG_DisableClkErrorDetect
AnnaBridge 181:57724642e740 220 * @param RNGx RNG Instance
AnnaBridge 181:57724642e740 221 * @retval None
AnnaBridge 181:57724642e740 222 */
AnnaBridge 181:57724642e740 223 __STATIC_INLINE void LL_RNG_DisableClkErrorDetect(RNG_TypeDef *RNGx)
AnnaBridge 181:57724642e740 224 {
AnnaBridge 181:57724642e740 225 SET_BIT(RNGx->CR, RNG_CR_CED);
AnnaBridge 181:57724642e740 226 }
AnnaBridge 181:57724642e740 227
AnnaBridge 181:57724642e740 228 /**
AnnaBridge 181:57724642e740 229 * @brief Check if RNG Clock Error Detection is enabled
AnnaBridge 181:57724642e740 230 * @rmtoll CR CED LL_RNG_IsEnabledClkErrorDetect
AnnaBridge 181:57724642e740 231 * @param RNGx RNG Instance
AnnaBridge 181:57724642e740 232 * @retval State of bit (1 or 0).
AnnaBridge 181:57724642e740 233 */
AnnaBridge 181:57724642e740 234 __STATIC_INLINE uint32_t LL_RNG_IsEnabledClkErrorDetect(RNG_TypeDef *RNGx)
AnnaBridge 181:57724642e740 235 {
AnnaBridge 181:57724642e740 236 return (!(READ_BIT(RNGx->CR, RNG_CR_CED) == (RNG_CR_CED)));
AnnaBridge 181:57724642e740 237 }
AnnaBridge 181:57724642e740 238 #endif /* defined(RNG_CR_CED) */
AnnaBridge 181:57724642e740 239
AnnaBridge 181:57724642e740 240
<> 144:ef7eb2e8f9f7 241 /**
<> 144:ef7eb2e8f9f7 242 * @}
<> 144:ef7eb2e8f9f7 243 */
<> 144:ef7eb2e8f9f7 244
<> 144:ef7eb2e8f9f7 245 /** @defgroup RNG_LL_EF_FLAG_Management FLAG Management
<> 144:ef7eb2e8f9f7 246 * @{
<> 144:ef7eb2e8f9f7 247 */
<> 144:ef7eb2e8f9f7 248
<> 144:ef7eb2e8f9f7 249 /**
<> 144:ef7eb2e8f9f7 250 * @brief Indicate if the RNG Data ready Flag is set or not
<> 144:ef7eb2e8f9f7 251 * @rmtoll SR DRDY LL_RNG_IsActiveFlag_DRDY
<> 144:ef7eb2e8f9f7 252 * @param RNGx RNG Instance
<> 144:ef7eb2e8f9f7 253 * @retval State of bit (1 or 0).
<> 144:ef7eb2e8f9f7 254 */
<> 144:ef7eb2e8f9f7 255 __STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_DRDY(RNG_TypeDef *RNGx)
<> 144:ef7eb2e8f9f7 256 {
<> 144:ef7eb2e8f9f7 257 return (READ_BIT(RNGx->SR, RNG_SR_DRDY) == (RNG_SR_DRDY));
<> 144:ef7eb2e8f9f7 258 }
<> 144:ef7eb2e8f9f7 259
<> 144:ef7eb2e8f9f7 260 /**
<> 144:ef7eb2e8f9f7 261 * @brief Indicate if the Clock Error Current Status Flag is set or not
<> 144:ef7eb2e8f9f7 262 * @rmtoll SR CECS LL_RNG_IsActiveFlag_CECS
<> 144:ef7eb2e8f9f7 263 * @param RNGx RNG Instance
<> 144:ef7eb2e8f9f7 264 * @retval State of bit (1 or 0).
<> 144:ef7eb2e8f9f7 265 */
<> 144:ef7eb2e8f9f7 266 __STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_CECS(RNG_TypeDef *RNGx)
<> 144:ef7eb2e8f9f7 267 {
<> 144:ef7eb2e8f9f7 268 return (READ_BIT(RNGx->SR, RNG_SR_CECS) == (RNG_SR_CECS));
<> 144:ef7eb2e8f9f7 269 }
<> 144:ef7eb2e8f9f7 270
<> 144:ef7eb2e8f9f7 271 /**
<> 144:ef7eb2e8f9f7 272 * @brief Indicate if the Seed Error Current Status Flag is set or not
<> 144:ef7eb2e8f9f7 273 * @rmtoll SR SECS LL_RNG_IsActiveFlag_SECS
<> 144:ef7eb2e8f9f7 274 * @param RNGx RNG Instance
<> 144:ef7eb2e8f9f7 275 * @retval State of bit (1 or 0).
<> 144:ef7eb2e8f9f7 276 */
<> 144:ef7eb2e8f9f7 277 __STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_SECS(RNG_TypeDef *RNGx)
<> 144:ef7eb2e8f9f7 278 {
<> 144:ef7eb2e8f9f7 279 return (READ_BIT(RNGx->SR, RNG_SR_SECS) == (RNG_SR_SECS));
<> 144:ef7eb2e8f9f7 280 }
<> 144:ef7eb2e8f9f7 281
<> 144:ef7eb2e8f9f7 282 /**
<> 144:ef7eb2e8f9f7 283 * @brief Indicate if the Clock Error Interrupt Status Flag is set or not
<> 144:ef7eb2e8f9f7 284 * @rmtoll SR CEIS LL_RNG_IsActiveFlag_CEIS
<> 144:ef7eb2e8f9f7 285 * @param RNGx RNG Instance
<> 144:ef7eb2e8f9f7 286 * @retval State of bit (1 or 0).
<> 144:ef7eb2e8f9f7 287 */
<> 144:ef7eb2e8f9f7 288 __STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_CEIS(RNG_TypeDef *RNGx)
<> 144:ef7eb2e8f9f7 289 {
<> 144:ef7eb2e8f9f7 290 return (READ_BIT(RNGx->SR, RNG_SR_CEIS) == (RNG_SR_CEIS));
<> 144:ef7eb2e8f9f7 291 }
<> 144:ef7eb2e8f9f7 292
<> 144:ef7eb2e8f9f7 293 /**
<> 144:ef7eb2e8f9f7 294 * @brief Indicate if the Seed Error Interrupt Status Flag is set or not
<> 144:ef7eb2e8f9f7 295 * @rmtoll SR SEIS LL_RNG_IsActiveFlag_SEIS
<> 144:ef7eb2e8f9f7 296 * @param RNGx RNG Instance
<> 144:ef7eb2e8f9f7 297 * @retval State of bit (1 or 0).
<> 144:ef7eb2e8f9f7 298 */
<> 144:ef7eb2e8f9f7 299 __STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_SEIS(RNG_TypeDef *RNGx)
<> 144:ef7eb2e8f9f7 300 {
<> 144:ef7eb2e8f9f7 301 return (READ_BIT(RNGx->SR, RNG_SR_SEIS) == (RNG_SR_SEIS));
<> 144:ef7eb2e8f9f7 302 }
<> 144:ef7eb2e8f9f7 303
<> 144:ef7eb2e8f9f7 304 /**
<> 144:ef7eb2e8f9f7 305 * @brief Clear Clock Error interrupt Status (CEIS) Flag
<> 144:ef7eb2e8f9f7 306 * @rmtoll SR CEIS LL_RNG_ClearFlag_CEIS
<> 144:ef7eb2e8f9f7 307 * @param RNGx RNG Instance
<> 144:ef7eb2e8f9f7 308 * @retval None
<> 144:ef7eb2e8f9f7 309 */
<> 144:ef7eb2e8f9f7 310 __STATIC_INLINE void LL_RNG_ClearFlag_CEIS(RNG_TypeDef *RNGx)
<> 144:ef7eb2e8f9f7 311 {
<> 144:ef7eb2e8f9f7 312 WRITE_REG(RNGx->SR, ~RNG_SR_CEIS);
<> 144:ef7eb2e8f9f7 313 }
<> 144:ef7eb2e8f9f7 314
<> 144:ef7eb2e8f9f7 315 /**
<> 144:ef7eb2e8f9f7 316 * @brief Clear Seed Error interrupt Status (SEIS) Flag
<> 144:ef7eb2e8f9f7 317 * @rmtoll SR SEIS LL_RNG_ClearFlag_SEIS
<> 144:ef7eb2e8f9f7 318 * @param RNGx RNG Instance
<> 144:ef7eb2e8f9f7 319 * @retval None
<> 144:ef7eb2e8f9f7 320 */
<> 144:ef7eb2e8f9f7 321 __STATIC_INLINE void LL_RNG_ClearFlag_SEIS(RNG_TypeDef *RNGx)
<> 144:ef7eb2e8f9f7 322 {
<> 144:ef7eb2e8f9f7 323 WRITE_REG(RNGx->SR, ~RNG_SR_SEIS);
<> 144:ef7eb2e8f9f7 324 }
<> 144:ef7eb2e8f9f7 325
<> 144:ef7eb2e8f9f7 326 /**
<> 144:ef7eb2e8f9f7 327 * @}
<> 144:ef7eb2e8f9f7 328 */
<> 144:ef7eb2e8f9f7 329
<> 144:ef7eb2e8f9f7 330 /** @defgroup RNG_LL_EF_IT_Management IT Management
<> 144:ef7eb2e8f9f7 331 * @{
<> 144:ef7eb2e8f9f7 332 */
<> 144:ef7eb2e8f9f7 333
<> 144:ef7eb2e8f9f7 334 /**
<> 144:ef7eb2e8f9f7 335 * @brief Enable Random Number Generator Interrupt
<> 144:ef7eb2e8f9f7 336 * (applies for either Seed error, Clock Error or Data ready interrupts)
<> 144:ef7eb2e8f9f7 337 * @rmtoll CR IE LL_RNG_EnableIT
<> 144:ef7eb2e8f9f7 338 * @param RNGx RNG Instance
<> 144:ef7eb2e8f9f7 339 * @retval None
<> 144:ef7eb2e8f9f7 340 */
<> 144:ef7eb2e8f9f7 341 __STATIC_INLINE void LL_RNG_EnableIT(RNG_TypeDef *RNGx)
<> 144:ef7eb2e8f9f7 342 {
<> 144:ef7eb2e8f9f7 343 SET_BIT(RNGx->CR, RNG_CR_IE);
<> 144:ef7eb2e8f9f7 344 }
<> 144:ef7eb2e8f9f7 345
<> 144:ef7eb2e8f9f7 346 /**
<> 144:ef7eb2e8f9f7 347 * @brief Disable Random Number Generator Interrupt
<> 144:ef7eb2e8f9f7 348 * (applies for either Seed error, Clock Error or Data ready interrupts)
<> 144:ef7eb2e8f9f7 349 * @rmtoll CR IE LL_RNG_DisableIT
<> 144:ef7eb2e8f9f7 350 * @param RNGx RNG Instance
<> 144:ef7eb2e8f9f7 351 * @retval None
<> 144:ef7eb2e8f9f7 352 */
<> 144:ef7eb2e8f9f7 353 __STATIC_INLINE void LL_RNG_DisableIT(RNG_TypeDef *RNGx)
<> 144:ef7eb2e8f9f7 354 {
<> 144:ef7eb2e8f9f7 355 CLEAR_BIT(RNGx->CR, RNG_CR_IE);
<> 144:ef7eb2e8f9f7 356 }
<> 144:ef7eb2e8f9f7 357
<> 144:ef7eb2e8f9f7 358 /**
<> 144:ef7eb2e8f9f7 359 * @brief Check if Random Number Generator Interrupt is enabled
<> 144:ef7eb2e8f9f7 360 * (applies for either Seed error, Clock Error or Data ready interrupts)
<> 144:ef7eb2e8f9f7 361 * @rmtoll CR IE LL_RNG_IsEnabledIT
<> 144:ef7eb2e8f9f7 362 * @param RNGx RNG Instance
<> 144:ef7eb2e8f9f7 363 * @retval State of bit (1 or 0).
<> 144:ef7eb2e8f9f7 364 */
<> 144:ef7eb2e8f9f7 365 __STATIC_INLINE uint32_t LL_RNG_IsEnabledIT(RNG_TypeDef *RNGx)
<> 144:ef7eb2e8f9f7 366 {
<> 144:ef7eb2e8f9f7 367 return (READ_BIT(RNGx->CR, RNG_CR_IE) == (RNG_CR_IE));
<> 144:ef7eb2e8f9f7 368 }
<> 144:ef7eb2e8f9f7 369
<> 144:ef7eb2e8f9f7 370 /**
<> 144:ef7eb2e8f9f7 371 * @}
<> 144:ef7eb2e8f9f7 372 */
<> 144:ef7eb2e8f9f7 373
<> 144:ef7eb2e8f9f7 374 /** @defgroup RNG_LL_EF_Data_Management Data Management
<> 144:ef7eb2e8f9f7 375 * @{
<> 144:ef7eb2e8f9f7 376 */
<> 144:ef7eb2e8f9f7 377
<> 144:ef7eb2e8f9f7 378 /**
<> 144:ef7eb2e8f9f7 379 * @brief Return32-bit Random Number value
<> 144:ef7eb2e8f9f7 380 * @rmtoll DR RNDATA LL_RNG_ReadRandData32
<> 144:ef7eb2e8f9f7 381 * @param RNGx RNG Instance
<> 144:ef7eb2e8f9f7 382 * @retval Generated 32-bit random value
<> 144:ef7eb2e8f9f7 383 */
<> 144:ef7eb2e8f9f7 384 __STATIC_INLINE uint32_t LL_RNG_ReadRandData32(RNG_TypeDef *RNGx)
<> 144:ef7eb2e8f9f7 385 {
<> 144:ef7eb2e8f9f7 386 return (uint32_t)(READ_REG(RNGx->DR));
<> 144:ef7eb2e8f9f7 387 }
<> 144:ef7eb2e8f9f7 388
<> 144:ef7eb2e8f9f7 389 /**
<> 144:ef7eb2e8f9f7 390 * @}
<> 144:ef7eb2e8f9f7 391 */
<> 144:ef7eb2e8f9f7 392
<> 144:ef7eb2e8f9f7 393 #if defined(USE_FULL_LL_DRIVER)
<> 144:ef7eb2e8f9f7 394 /** @defgroup RNG_LL_EF_Init Initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 395 * @{
<> 144:ef7eb2e8f9f7 396 */
AnnaBridge 181:57724642e740 397 #if defined(RNG_CR_CED)
AnnaBridge 181:57724642e740 398 ErrorStatus LL_RNG_Init(RNG_TypeDef *RNGx, LL_RNG_InitTypeDef *RNG_InitStruct);
AnnaBridge 181:57724642e740 399 void LL_RNG_StructInit(LL_RNG_InitTypeDef *RNG_InitStruct);
AnnaBridge 181:57724642e740 400 #endif /* defined(RNG_CR_CED) */
<> 144:ef7eb2e8f9f7 401 ErrorStatus LL_RNG_DeInit(RNG_TypeDef *RNGx);
<> 144:ef7eb2e8f9f7 402
<> 144:ef7eb2e8f9f7 403 /**
<> 144:ef7eb2e8f9f7 404 * @}
<> 144:ef7eb2e8f9f7 405 */
<> 144:ef7eb2e8f9f7 406 #endif /* USE_FULL_LL_DRIVER */
<> 144:ef7eb2e8f9f7 407
<> 144:ef7eb2e8f9f7 408 /**
<> 144:ef7eb2e8f9f7 409 * @}
<> 144:ef7eb2e8f9f7 410 */
<> 144:ef7eb2e8f9f7 411
<> 144:ef7eb2e8f9f7 412 /**
<> 144:ef7eb2e8f9f7 413 * @}
<> 144:ef7eb2e8f9f7 414 */
<> 144:ef7eb2e8f9f7 415
<> 144:ef7eb2e8f9f7 416 #endif /* defined(RNG) */
<> 144:ef7eb2e8f9f7 417
<> 144:ef7eb2e8f9f7 418 /**
<> 144:ef7eb2e8f9f7 419 * @}
<> 144:ef7eb2e8f9f7 420 */
<> 144:ef7eb2e8f9f7 421
<> 144:ef7eb2e8f9f7 422 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 423 }
<> 144:ef7eb2e8f9f7 424 #endif
<> 144:ef7eb2e8f9f7 425
<> 144:ef7eb2e8f9f7 426 #endif /* __STM32L4xx_LL_RNG_H */
<> 144:ef7eb2e8f9f7 427
<> 144:ef7eb2e8f9f7 428 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/