mbed official / mbed-dev

Important changes to repositories hosted on mbed.com

Mbed hosted mercurial repositories are deprecated and are due to be permanently deleted in July 2026.

To keep a copy of this software download the repository Zip archive or clone locally using Mercurial.

It is also possible to export all your personal repositories from the account settings page.

Dependents:   Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

targets/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088/i2c_api.c@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
Parent:
149:156823d33999 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /* mbed Microcontroller Library
<> 144:ef7eb2e8f9f7 2 * Copyright (c) 2006-2013 ARM Limited
<> 144:ef7eb2e8f9f7 3 *
<> 144:ef7eb2e8f9f7 4 * Licensed under the Apache License, Version 2.0 (the "License");
<> 144:ef7eb2e8f9f7 5 * you may not use this file except in compliance with the License.
<> 144:ef7eb2e8f9f7 6 * You may obtain a copy of the License at
<> 144:ef7eb2e8f9f7 7 *
<> 144:ef7eb2e8f9f7 8 * http://www.apache.org/licenses/LICENSE-2.0
<> 144:ef7eb2e8f9f7 9 *
<> 144:ef7eb2e8f9f7 10 * Unless required by applicable law or agreed to in writing, software
<> 144:ef7eb2e8f9f7 11 * distributed under the License is distributed on an "AS IS" BASIS,
<> 144:ef7eb2e8f9f7 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
<> 144:ef7eb2e8f9f7 13 * See the License for the specific language governing permissions and
<> 144:ef7eb2e8f9f7 14 * limitations under the License.
<> 144:ef7eb2e8f9f7 15 */
<> 144:ef7eb2e8f9f7 16 #include "mbed_assert.h"
<> 144:ef7eb2e8f9f7 17 #include "i2c_api.h"
<> 144:ef7eb2e8f9f7 18 #include "cmsis.h"
<> 144:ef7eb2e8f9f7 19 #include "pinmap.h"
<> 144:ef7eb2e8f9f7 20
<> 144:ef7eb2e8f9f7 21 static const PinMap PinMap_I2C_SDA[] = {
<> 144:ef7eb2e8f9f7 22 {P0_0 , I2C_1, 3},
<> 144:ef7eb2e8f9f7 23 {P0_10, I2C_2, 2},
<> 144:ef7eb2e8f9f7 24 {P0_19, I2C_1, 3},
<> 144:ef7eb2e8f9f7 25 {P0_27, I2C_0, 1},
<> 144:ef7eb2e8f9f7 26 {P1_15, I2C_2, 3},
<> 144:ef7eb2e8f9f7 27 {P1_30, I2C_0, 4},
<> 144:ef7eb2e8f9f7 28 {P2_14, I2C_1, 2},
<> 144:ef7eb2e8f9f7 29 {P2_30, I2C_2, 2},
<> 144:ef7eb2e8f9f7 30 {P4_20, I2C_2, 4},
<> 144:ef7eb2e8f9f7 31 {P5_2, I2C_0, 5},
<> 144:ef7eb2e8f9f7 32 {NC , NC , 0}
<> 144:ef7eb2e8f9f7 33 };
<> 144:ef7eb2e8f9f7 34
<> 144:ef7eb2e8f9f7 35 static const PinMap PinMap_I2C_SCL[] = {
<> 144:ef7eb2e8f9f7 36 {P0_1 , I2C_1, 3},
<> 144:ef7eb2e8f9f7 37 {P0_11, I2C_2, 2},
<> 144:ef7eb2e8f9f7 38 {P0_20, I2C_1, 3},
<> 144:ef7eb2e8f9f7 39 {P0_28, I2C_0, 1},
<> 144:ef7eb2e8f9f7 40 {P1_31, I2C_0, 4},
<> 144:ef7eb2e8f9f7 41 {P2_15, I2C_1, 2},
<> 144:ef7eb2e8f9f7 42 {P2_31, I2C_2, 2},
<> 144:ef7eb2e8f9f7 43 {P4_21, I2C_2, 2},
<> 144:ef7eb2e8f9f7 44 {P4_29, I2C_2, 4},
<> 144:ef7eb2e8f9f7 45 {P5_3, I2C_0, 5},
<> 144:ef7eb2e8f9f7 46 {NC , NC, 0}
<> 144:ef7eb2e8f9f7 47 };
<> 144:ef7eb2e8f9f7 48
<> 144:ef7eb2e8f9f7 49 #define I2C_CONSET(x) (x->i2c->CONSET)
<> 144:ef7eb2e8f9f7 50 #define I2C_CONCLR(x) (x->i2c->CONCLR)
<> 144:ef7eb2e8f9f7 51 #define I2C_STAT(x) (x->i2c->STAT)
<> 144:ef7eb2e8f9f7 52 #define I2C_DAT(x) (x->i2c->DAT)
<> 144:ef7eb2e8f9f7 53 #define I2C_SCLL(x, val) (x->i2c->SCLL = val)
<> 144:ef7eb2e8f9f7 54 #define I2C_SCLH(x, val) (x->i2c->SCLH = val)
<> 144:ef7eb2e8f9f7 55
<> 144:ef7eb2e8f9f7 56 static const uint32_t I2C_addr_offset[2][4] = {
<> 144:ef7eb2e8f9f7 57 {0x0C, 0x20, 0x24, 0x28},
<> 144:ef7eb2e8f9f7 58 {0x30, 0x34, 0x38, 0x3C}
<> 144:ef7eb2e8f9f7 59 };
<> 144:ef7eb2e8f9f7 60
<> 144:ef7eb2e8f9f7 61 static inline void i2c_conclr(i2c_t *obj, int start, int stop, int interrupt, int acknowledge) {
<> 144:ef7eb2e8f9f7 62 I2C_CONCLR(obj) = (start << 5)
<> 144:ef7eb2e8f9f7 63 | (stop << 4)
<> 144:ef7eb2e8f9f7 64 | (interrupt << 3)
<> 144:ef7eb2e8f9f7 65 | (acknowledge << 2);
<> 144:ef7eb2e8f9f7 66 }
<> 144:ef7eb2e8f9f7 67
<> 144:ef7eb2e8f9f7 68 static inline void i2c_conset(i2c_t *obj, int start, int stop, int interrupt, int acknowledge) {
<> 144:ef7eb2e8f9f7 69 I2C_CONSET(obj) = (start << 5)
<> 144:ef7eb2e8f9f7 70 | (stop << 4)
<> 144:ef7eb2e8f9f7 71 | (interrupt << 3)
<> 144:ef7eb2e8f9f7 72 | (acknowledge << 2);
<> 144:ef7eb2e8f9f7 73 }
<> 144:ef7eb2e8f9f7 74
<> 144:ef7eb2e8f9f7 75 // Clear the Serial Interrupt (SI)
<> 144:ef7eb2e8f9f7 76 static inline void i2c_clear_SI(i2c_t *obj) {
<> 144:ef7eb2e8f9f7 77 i2c_conclr(obj, 0, 0, 1, 0);
<> 144:ef7eb2e8f9f7 78 }
<> 144:ef7eb2e8f9f7 79
<> 144:ef7eb2e8f9f7 80 static inline int i2c_status(i2c_t *obj) {
<> 144:ef7eb2e8f9f7 81 return I2C_STAT(obj);
<> 144:ef7eb2e8f9f7 82 }
<> 144:ef7eb2e8f9f7 83
<> 144:ef7eb2e8f9f7 84 // Wait until the Serial Interrupt (SI) is set
<> 144:ef7eb2e8f9f7 85 static int i2c_wait_SI(i2c_t *obj) {
<> 144:ef7eb2e8f9f7 86 int timeout = 0;
<> 144:ef7eb2e8f9f7 87 while (!(I2C_CONSET(obj) & (1 << 3))) {
<> 144:ef7eb2e8f9f7 88 timeout++;
<> 144:ef7eb2e8f9f7 89 if (timeout > 100000) return -1;
<> 144:ef7eb2e8f9f7 90 }
<> 144:ef7eb2e8f9f7 91 return 0;
<> 144:ef7eb2e8f9f7 92 }
<> 144:ef7eb2e8f9f7 93
<> 144:ef7eb2e8f9f7 94 static inline void i2c_interface_enable(i2c_t *obj) {
<> 144:ef7eb2e8f9f7 95 I2C_CONSET(obj) = 0x40;
<> 144:ef7eb2e8f9f7 96 }
<> 144:ef7eb2e8f9f7 97
<> 144:ef7eb2e8f9f7 98 static inline void i2c_power_enable(i2c_t *obj) {
<> 144:ef7eb2e8f9f7 99 switch ((int)obj->i2c) {
<> 144:ef7eb2e8f9f7 100 case I2C_0: LPC_SC->PCONP |= 1 << 7; break;
<> 144:ef7eb2e8f9f7 101 case I2C_1: LPC_SC->PCONP |= 1 << 19; break;
<> 144:ef7eb2e8f9f7 102 case I2C_2: LPC_SC->PCONP |= 1 << 26; break;
<> 144:ef7eb2e8f9f7 103 }
<> 144:ef7eb2e8f9f7 104 }
<> 144:ef7eb2e8f9f7 105
<> 144:ef7eb2e8f9f7 106 void i2c_init(i2c_t *obj, PinName sda, PinName scl) {
<> 144:ef7eb2e8f9f7 107 // determine the SPI to use
<> 144:ef7eb2e8f9f7 108 I2CName i2c_sda = (I2CName)pinmap_peripheral(sda, PinMap_I2C_SDA);
<> 144:ef7eb2e8f9f7 109 I2CName i2c_scl = (I2CName)pinmap_peripheral(scl, PinMap_I2C_SCL);
<> 144:ef7eb2e8f9f7 110 obj->i2c = (LPC_I2C_TypeDef *)pinmap_merge(i2c_sda, i2c_scl);
<> 144:ef7eb2e8f9f7 111 MBED_ASSERT((int)obj->i2c != NC);
<> 144:ef7eb2e8f9f7 112
<> 144:ef7eb2e8f9f7 113 // enable power
<> 144:ef7eb2e8f9f7 114 i2c_power_enable(obj);
<> 144:ef7eb2e8f9f7 115
<> 144:ef7eb2e8f9f7 116 // set default frequency at 100k
<> 144:ef7eb2e8f9f7 117 i2c_frequency(obj, 100000);
<> 144:ef7eb2e8f9f7 118 i2c_conclr(obj, 1, 1, 1, 1);
<> 144:ef7eb2e8f9f7 119 i2c_interface_enable(obj);
<> 144:ef7eb2e8f9f7 120
<> 144:ef7eb2e8f9f7 121 pinmap_pinout(sda, PinMap_I2C_SDA);
<> 144:ef7eb2e8f9f7 122 pinmap_pinout(scl, PinMap_I2C_SCL);
<> 144:ef7eb2e8f9f7 123
<> 144:ef7eb2e8f9f7 124 // OpenDrain must explicitly be enabled for p0.0 and p0.1
<> 144:ef7eb2e8f9f7 125 if (sda == P0_0) {
<> 144:ef7eb2e8f9f7 126 pin_mode(sda, OpenDrain);
<> 144:ef7eb2e8f9f7 127 }
<> 144:ef7eb2e8f9f7 128 if (scl == P0_1) {
<> 144:ef7eb2e8f9f7 129 pin_mode(scl, OpenDrain);
<> 144:ef7eb2e8f9f7 130 }
<> 144:ef7eb2e8f9f7 131
<> 144:ef7eb2e8f9f7 132 }
<> 144:ef7eb2e8f9f7 133
<> 144:ef7eb2e8f9f7 134 inline int i2c_start(i2c_t *obj) {
<> 144:ef7eb2e8f9f7 135 int status = 0;
<> 144:ef7eb2e8f9f7 136 int isInterrupted = I2C_CONSET(obj) & (1 << 3);
<> 144:ef7eb2e8f9f7 137
<> 144:ef7eb2e8f9f7 138 // 8.1 Before master mode can be entered, I2CON must be initialised to:
<> 144:ef7eb2e8f9f7 139 // - I2EN STA STO SI AA - -
<> 144:ef7eb2e8f9f7 140 // - 1 0 0 x x - -
<> 144:ef7eb2e8f9f7 141 // if AA = 0, it can't enter slave mode
<> 144:ef7eb2e8f9f7 142 i2c_conclr(obj, 1, 1, 0, 1);
<> 144:ef7eb2e8f9f7 143
<> 144:ef7eb2e8f9f7 144 // The master mode may now be entered by setting the STA bit
<> 144:ef7eb2e8f9f7 145 // this will generate a start condition when the bus becomes free
<> 144:ef7eb2e8f9f7 146 i2c_conset(obj, 1, 0, 0, 1);
<> 144:ef7eb2e8f9f7 147 // Clearing SI bit when it wasn't set on entry can jump past state
<> 144:ef7eb2e8f9f7 148 // 0x10 or 0x08 and erroneously send uninitialized slave address.
<> 144:ef7eb2e8f9f7 149 if (isInterrupted)
<> 144:ef7eb2e8f9f7 150 i2c_clear_SI(obj);
<> 144:ef7eb2e8f9f7 151
<> 144:ef7eb2e8f9f7 152 i2c_wait_SI(obj);
<> 144:ef7eb2e8f9f7 153 status = i2c_status(obj);
<> 144:ef7eb2e8f9f7 154
<> 144:ef7eb2e8f9f7 155 // Clear start bit now that it's transmitted
<> 144:ef7eb2e8f9f7 156 i2c_conclr(obj, 1, 0, 0, 0);
<> 144:ef7eb2e8f9f7 157 return status;
<> 144:ef7eb2e8f9f7 158 }
<> 144:ef7eb2e8f9f7 159
<> 144:ef7eb2e8f9f7 160 inline int i2c_stop(i2c_t *obj) {
<> 144:ef7eb2e8f9f7 161 int timeout = 0;
<> 144:ef7eb2e8f9f7 162
<> 144:ef7eb2e8f9f7 163 // write the stop bit
<> 144:ef7eb2e8f9f7 164 i2c_conset(obj, 0, 1, 0, 0);
<> 144:ef7eb2e8f9f7 165 i2c_clear_SI(obj);
<> 144:ef7eb2e8f9f7 166
<> 144:ef7eb2e8f9f7 167 // wait for STO bit to reset
<> 144:ef7eb2e8f9f7 168 while(I2C_CONSET(obj) & (1 << 4)) {
<> 144:ef7eb2e8f9f7 169 timeout ++;
<> 144:ef7eb2e8f9f7 170 if (timeout > 100000) return 1;
<> 144:ef7eb2e8f9f7 171 }
<> 144:ef7eb2e8f9f7 172
<> 144:ef7eb2e8f9f7 173 return 0;
<> 144:ef7eb2e8f9f7 174 }
<> 144:ef7eb2e8f9f7 175
<> 144:ef7eb2e8f9f7 176
<> 144:ef7eb2e8f9f7 177 static inline int i2c_do_write(i2c_t *obj, int value, uint8_t addr) {
<> 144:ef7eb2e8f9f7 178 // write the data
<> 144:ef7eb2e8f9f7 179 I2C_DAT(obj) = value;
<> 144:ef7eb2e8f9f7 180
<> 144:ef7eb2e8f9f7 181 // clear SI to init a send
<> 144:ef7eb2e8f9f7 182 i2c_clear_SI(obj);
<> 144:ef7eb2e8f9f7 183
<> 144:ef7eb2e8f9f7 184 // wait and return status
<> 144:ef7eb2e8f9f7 185 i2c_wait_SI(obj);
<> 144:ef7eb2e8f9f7 186 return i2c_status(obj);
<> 144:ef7eb2e8f9f7 187 }
<> 144:ef7eb2e8f9f7 188
<> 144:ef7eb2e8f9f7 189 static inline int i2c_do_read(i2c_t *obj, int last) {
<> 144:ef7eb2e8f9f7 190 // we are in state 0x40 (SLA+R tx'd) or 0x50 (data rx'd and ack)
<> 144:ef7eb2e8f9f7 191 if(last) {
<> 144:ef7eb2e8f9f7 192 i2c_conclr(obj, 0, 0, 0, 1); // send a NOT ACK
<> 144:ef7eb2e8f9f7 193 } else {
<> 144:ef7eb2e8f9f7 194 i2c_conset(obj, 0, 0, 0, 1); // send a ACK
<> 144:ef7eb2e8f9f7 195 }
<> 144:ef7eb2e8f9f7 196
<> 144:ef7eb2e8f9f7 197 // accept byte
<> 144:ef7eb2e8f9f7 198 i2c_clear_SI(obj);
<> 144:ef7eb2e8f9f7 199
<> 144:ef7eb2e8f9f7 200 // wait for it to arrive
<> 144:ef7eb2e8f9f7 201 i2c_wait_SI(obj);
<> 144:ef7eb2e8f9f7 202
<> 144:ef7eb2e8f9f7 203 // return the data
<> 144:ef7eb2e8f9f7 204 return (I2C_DAT(obj) & 0xFF);
<> 144:ef7eb2e8f9f7 205 }
<> 144:ef7eb2e8f9f7 206
<> 144:ef7eb2e8f9f7 207 void i2c_frequency(i2c_t *obj, int hz) {
<> 144:ef7eb2e8f9f7 208 uint32_t PCLK = PeripheralClock;
<> 144:ef7eb2e8f9f7 209 uint32_t pulse = PCLK / (hz * 2);
<> 144:ef7eb2e8f9f7 210
<> 144:ef7eb2e8f9f7 211 // I2C Rate
<> 144:ef7eb2e8f9f7 212 I2C_SCLL(obj, pulse);
<> 144:ef7eb2e8f9f7 213 I2C_SCLH(obj, pulse);
<> 144:ef7eb2e8f9f7 214 }
<> 144:ef7eb2e8f9f7 215
<> 144:ef7eb2e8f9f7 216 // The I2C does a read or a write as a whole operation
<> 144:ef7eb2e8f9f7 217 // There are two types of error conditions it can encounter
<> 144:ef7eb2e8f9f7 218 // 1) it can not obtain the bus
<> 144:ef7eb2e8f9f7 219 // 2) it gets error responses at part of the transmission
<> 144:ef7eb2e8f9f7 220 //
<> 144:ef7eb2e8f9f7 221 // We tackle them as follows:
<> 144:ef7eb2e8f9f7 222 // 1) we retry until we get the bus. we could have a "timeout" if we can not get it
<> 144:ef7eb2e8f9f7 223 // which basically turns it in to a 2)
<> 144:ef7eb2e8f9f7 224 // 2) on error, we use the standard error mechanisms to report/debug
<> 144:ef7eb2e8f9f7 225 //
<> 144:ef7eb2e8f9f7 226 // Therefore an I2C transaction should always complete. If it doesn't it is usually
<> 144:ef7eb2e8f9f7 227 // because something is setup wrong (e.g. wiring), and we don't need to programatically
<> 144:ef7eb2e8f9f7 228 // check for that
<> 144:ef7eb2e8f9f7 229 int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) {
<> 144:ef7eb2e8f9f7 230 int count, status;
<> 144:ef7eb2e8f9f7 231
<> 144:ef7eb2e8f9f7 232 status = i2c_start(obj);
<> 144:ef7eb2e8f9f7 233
<> 144:ef7eb2e8f9f7 234 if ((status != 0x10) && (status != 0x08)) {
<> 144:ef7eb2e8f9f7 235 i2c_stop(obj);
<> 144:ef7eb2e8f9f7 236 return I2C_ERROR_BUS_BUSY;
<> 144:ef7eb2e8f9f7 237 }
<> 144:ef7eb2e8f9f7 238
<> 144:ef7eb2e8f9f7 239 status = i2c_do_write(obj, (address | 0x01), 1);
<> 144:ef7eb2e8f9f7 240 if (status != 0x40) {
<> 144:ef7eb2e8f9f7 241 i2c_stop(obj);
<> 144:ef7eb2e8f9f7 242 return I2C_ERROR_NO_SLAVE;
<> 144:ef7eb2e8f9f7 243 }
<> 144:ef7eb2e8f9f7 244
<> 144:ef7eb2e8f9f7 245 // Read in all except last byte
<> 144:ef7eb2e8f9f7 246 for (count = 0; count < (length - 1); count++) {
<> 144:ef7eb2e8f9f7 247 int value = i2c_do_read(obj, 0);
<> 144:ef7eb2e8f9f7 248 status = i2c_status(obj);
<> 144:ef7eb2e8f9f7 249 if (status != 0x50) {
<> 144:ef7eb2e8f9f7 250 i2c_stop(obj);
<> 144:ef7eb2e8f9f7 251 return count;
<> 144:ef7eb2e8f9f7 252 }
<> 144:ef7eb2e8f9f7 253 data[count] = (char) value;
<> 144:ef7eb2e8f9f7 254 }
<> 144:ef7eb2e8f9f7 255
<> 144:ef7eb2e8f9f7 256 // read in last byte
<> 144:ef7eb2e8f9f7 257 int value = i2c_do_read(obj, 1);
<> 144:ef7eb2e8f9f7 258 status = i2c_status(obj);
<> 144:ef7eb2e8f9f7 259 if (status != 0x58) {
<> 144:ef7eb2e8f9f7 260 i2c_stop(obj);
<> 144:ef7eb2e8f9f7 261 return length - 1;
<> 144:ef7eb2e8f9f7 262 }
<> 144:ef7eb2e8f9f7 263
<> 144:ef7eb2e8f9f7 264 data[count] = (char) value;
<> 144:ef7eb2e8f9f7 265
<> 144:ef7eb2e8f9f7 266 // If not repeated start, send stop.
<> 144:ef7eb2e8f9f7 267 if (stop) {
<> 144:ef7eb2e8f9f7 268 i2c_stop(obj);
<> 144:ef7eb2e8f9f7 269 }
<> 144:ef7eb2e8f9f7 270
<> 144:ef7eb2e8f9f7 271 return length;
<> 144:ef7eb2e8f9f7 272 }
<> 144:ef7eb2e8f9f7 273
<> 144:ef7eb2e8f9f7 274 int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) {
<> 144:ef7eb2e8f9f7 275 int i, status;
<> 144:ef7eb2e8f9f7 276
<> 144:ef7eb2e8f9f7 277 status = i2c_start(obj);
<> 144:ef7eb2e8f9f7 278
<> 144:ef7eb2e8f9f7 279 if ((status != 0x10) && (status != 0x08)) {
<> 144:ef7eb2e8f9f7 280 i2c_stop(obj);
<> 144:ef7eb2e8f9f7 281 return I2C_ERROR_BUS_BUSY;
<> 144:ef7eb2e8f9f7 282 }
<> 144:ef7eb2e8f9f7 283
<> 144:ef7eb2e8f9f7 284 status = i2c_do_write(obj, (address & 0xFE), 1);
<> 144:ef7eb2e8f9f7 285 if (status != 0x18) {
<> 144:ef7eb2e8f9f7 286 i2c_stop(obj);
<> 144:ef7eb2e8f9f7 287 return I2C_ERROR_NO_SLAVE;
<> 144:ef7eb2e8f9f7 288 }
<> 144:ef7eb2e8f9f7 289
<> 144:ef7eb2e8f9f7 290 for (i=0; i<length; i++) {
<> 144:ef7eb2e8f9f7 291 status = i2c_do_write(obj, data[i], 0);
<> 144:ef7eb2e8f9f7 292 if (status != 0x28) {
<> 144:ef7eb2e8f9f7 293 i2c_stop(obj);
<> 144:ef7eb2e8f9f7 294 return i;
<> 144:ef7eb2e8f9f7 295 }
<> 144:ef7eb2e8f9f7 296 }
<> 144:ef7eb2e8f9f7 297
<> 144:ef7eb2e8f9f7 298 // clearing the serial interrupt here might cause an unintended rewrite of the last byte
<> 144:ef7eb2e8f9f7 299 // see also issue report https://mbed.org/users/mbed_official/code/mbed/issues/1
<> 144:ef7eb2e8f9f7 300 // i2c_clear_SI(obj);
<> 144:ef7eb2e8f9f7 301
<> 144:ef7eb2e8f9f7 302 // If not repeated start, send stop.
<> 144:ef7eb2e8f9f7 303 if (stop) {
<> 144:ef7eb2e8f9f7 304 i2c_stop(obj);
<> 144:ef7eb2e8f9f7 305 }
<> 144:ef7eb2e8f9f7 306
<> 144:ef7eb2e8f9f7 307 return length;
<> 144:ef7eb2e8f9f7 308 }
<> 144:ef7eb2e8f9f7 309
<> 144:ef7eb2e8f9f7 310 void i2c_reset(i2c_t *obj) {
<> 144:ef7eb2e8f9f7 311 i2c_stop(obj);
<> 144:ef7eb2e8f9f7 312 }
<> 144:ef7eb2e8f9f7 313
<> 144:ef7eb2e8f9f7 314 int i2c_byte_read(i2c_t *obj, int last) {
<> 144:ef7eb2e8f9f7 315 return (i2c_do_read(obj, last) & 0xFF);
<> 144:ef7eb2e8f9f7 316 }
<> 144:ef7eb2e8f9f7 317
<> 144:ef7eb2e8f9f7 318 int i2c_byte_write(i2c_t *obj, int data) {
<> 144:ef7eb2e8f9f7 319 int ack;
<> 144:ef7eb2e8f9f7 320 int status = i2c_do_write(obj, (data & 0xFF), 0);
<> 144:ef7eb2e8f9f7 321
<> 144:ef7eb2e8f9f7 322 switch(status) {
<> 144:ef7eb2e8f9f7 323 case 0x18: case 0x28: // Master transmit ACKs
<> 144:ef7eb2e8f9f7 324 ack = 1;
<> 144:ef7eb2e8f9f7 325 break;
<> 144:ef7eb2e8f9f7 326
<> 144:ef7eb2e8f9f7 327 case 0x40: // Master receive address transmitted ACK
<> 144:ef7eb2e8f9f7 328 ack = 1;
<> 144:ef7eb2e8f9f7 329 break;
<> 144:ef7eb2e8f9f7 330
<> 144:ef7eb2e8f9f7 331 case 0xB8: // Slave transmit ACK
<> 144:ef7eb2e8f9f7 332 ack = 1;
<> 144:ef7eb2e8f9f7 333 break;
<> 144:ef7eb2e8f9f7 334
<> 144:ef7eb2e8f9f7 335 default:
<> 144:ef7eb2e8f9f7 336 ack = 0;
<> 144:ef7eb2e8f9f7 337 break;
<> 144:ef7eb2e8f9f7 338 }
<> 144:ef7eb2e8f9f7 339
<> 144:ef7eb2e8f9f7 340 return ack;
<> 144:ef7eb2e8f9f7 341 }
<> 144:ef7eb2e8f9f7 342
<> 144:ef7eb2e8f9f7 343 void i2c_slave_mode(i2c_t *obj, int enable_slave) {
<> 144:ef7eb2e8f9f7 344 if (enable_slave != 0) {
<> 144:ef7eb2e8f9f7 345 i2c_conclr(obj, 1, 1, 1, 0);
<> 144:ef7eb2e8f9f7 346 i2c_conset(obj, 0, 0, 0, 1);
<> 144:ef7eb2e8f9f7 347 } else {
<> 144:ef7eb2e8f9f7 348 i2c_conclr(obj, 1, 1, 1, 1);
<> 144:ef7eb2e8f9f7 349 }
<> 144:ef7eb2e8f9f7 350 }
<> 144:ef7eb2e8f9f7 351
<> 144:ef7eb2e8f9f7 352 int i2c_slave_receive(i2c_t *obj) {
<> 144:ef7eb2e8f9f7 353 int status;
<> 144:ef7eb2e8f9f7 354 int retval;
<> 144:ef7eb2e8f9f7 355
<> 144:ef7eb2e8f9f7 356 status = i2c_status(obj);
<> 144:ef7eb2e8f9f7 357 switch(status) {
<> 144:ef7eb2e8f9f7 358 case 0x60: retval = 3; break;
<> 144:ef7eb2e8f9f7 359 case 0x70: retval = 2; break;
<> 144:ef7eb2e8f9f7 360 case 0xA8: retval = 1; break;
<> 144:ef7eb2e8f9f7 361 default : retval = 0; break;
<> 144:ef7eb2e8f9f7 362 }
<> 144:ef7eb2e8f9f7 363
<> 144:ef7eb2e8f9f7 364 return(retval);
<> 144:ef7eb2e8f9f7 365 }
<> 144:ef7eb2e8f9f7 366
<> 144:ef7eb2e8f9f7 367 int i2c_slave_read(i2c_t *obj, char *data, int length) {
<> 144:ef7eb2e8f9f7 368 int count = 0;
<> 144:ef7eb2e8f9f7 369 int status;
<> 144:ef7eb2e8f9f7 370
<> 144:ef7eb2e8f9f7 371 do {
<> 144:ef7eb2e8f9f7 372 i2c_clear_SI(obj);
<> 144:ef7eb2e8f9f7 373 i2c_wait_SI(obj);
<> 144:ef7eb2e8f9f7 374 status = i2c_status(obj);
<> 144:ef7eb2e8f9f7 375 if((status == 0x80) || (status == 0x90)) {
<> 144:ef7eb2e8f9f7 376 data[count] = I2C_DAT(obj) & 0xFF;
<> 144:ef7eb2e8f9f7 377 }
<> 144:ef7eb2e8f9f7 378 count++;
<> 144:ef7eb2e8f9f7 379 } while (((status == 0x80) || (status == 0x90) ||
<> 144:ef7eb2e8f9f7 380 (status == 0x060) || (status == 0x70)) && (count < length));
<> 144:ef7eb2e8f9f7 381
<> 144:ef7eb2e8f9f7 382 if(status != 0xA0) {
<> 144:ef7eb2e8f9f7 383 i2c_stop(obj);
<> 144:ef7eb2e8f9f7 384 }
<> 144:ef7eb2e8f9f7 385
<> 144:ef7eb2e8f9f7 386 i2c_clear_SI(obj);
<> 144:ef7eb2e8f9f7 387
<> 144:ef7eb2e8f9f7 388 return count;
<> 144:ef7eb2e8f9f7 389 }
<> 144:ef7eb2e8f9f7 390
<> 144:ef7eb2e8f9f7 391 int i2c_slave_write(i2c_t *obj, const char *data, int length) {
<> 144:ef7eb2e8f9f7 392 int count = 0;
<> 144:ef7eb2e8f9f7 393 int status;
<> 144:ef7eb2e8f9f7 394
<> 144:ef7eb2e8f9f7 395 if(length <= 0) {
<> 144:ef7eb2e8f9f7 396 return(0);
<> 144:ef7eb2e8f9f7 397 }
<> 144:ef7eb2e8f9f7 398
<> 144:ef7eb2e8f9f7 399 do {
<> 144:ef7eb2e8f9f7 400 status = i2c_do_write(obj, data[count], 0);
<> 144:ef7eb2e8f9f7 401 count++;
<> 144:ef7eb2e8f9f7 402 } while ((count < length) && (status == 0xB8));
<> 144:ef7eb2e8f9f7 403
<> 144:ef7eb2e8f9f7 404 if((status != 0xC0) && (status != 0xC8)) {
<> 144:ef7eb2e8f9f7 405 i2c_stop(obj);
<> 144:ef7eb2e8f9f7 406 }
<> 144:ef7eb2e8f9f7 407
<> 144:ef7eb2e8f9f7 408 i2c_clear_SI(obj);
<> 144:ef7eb2e8f9f7 409
<> 144:ef7eb2e8f9f7 410 return(count);
<> 144:ef7eb2e8f9f7 411 }
<> 144:ef7eb2e8f9f7 412
<> 144:ef7eb2e8f9f7 413 void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask) {
<> 144:ef7eb2e8f9f7 414 uint32_t addr;
<> 144:ef7eb2e8f9f7 415
<> 144:ef7eb2e8f9f7 416 if ((idx >= 0) && (idx <= 3)) {
<> 144:ef7eb2e8f9f7 417 addr = ((uint32_t)obj->i2c) + I2C_addr_offset[0][idx];
<> 144:ef7eb2e8f9f7 418 *((uint32_t *) addr) = address & 0xFF;
<> 144:ef7eb2e8f9f7 419 addr = ((uint32_t)obj->i2c) + I2C_addr_offset[1][idx];
<> 144:ef7eb2e8f9f7 420 *((uint32_t *) addr) = mask & 0xFE;
<> 144:ef7eb2e8f9f7 421 }
<> 144:ef7eb2e8f9f7 422 }