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targets/TARGET_GigaDevice/TARGET_GD32F30X/GD32F30x_standard_peripheral/Include/gd32f30x_can.h@189:f392fc9709a3, 2019-02-20 (annotated)
- Committer:
- AnnaBridge
- Date:
- Wed Feb 20 22:31:08 2019 +0000
- Revision:
- 189:f392fc9709a3
mbed library release version 165
Who changed what in which revision?
| User | Revision | Line number | New contents of line | 
|---|---|---|---|
| AnnaBridge | 189:f392fc9709a3 | 1 | /*! | 
| AnnaBridge | 189:f392fc9709a3 | 2 | \file gd32f30x_can.h | 
| AnnaBridge | 189:f392fc9709a3 | 3 | \brief definitions for the CAN | 
| AnnaBridge | 189:f392fc9709a3 | 4 | |
| AnnaBridge | 189:f392fc9709a3 | 5 | \version 2018-10-10, V1.1.0, firmware for GD32F30x (The version is for mbed) | 
| AnnaBridge | 189:f392fc9709a3 | 6 | */ | 
| AnnaBridge | 189:f392fc9709a3 | 7 | |
| AnnaBridge | 189:f392fc9709a3 | 8 | /* | 
| AnnaBridge | 189:f392fc9709a3 | 9 | Copyright (c) 2018, GigaDevice Semiconductor Inc. | 
| AnnaBridge | 189:f392fc9709a3 | 10 | |
| AnnaBridge | 189:f392fc9709a3 | 11 | All rights reserved. | 
| AnnaBridge | 189:f392fc9709a3 | 12 | |
| AnnaBridge | 189:f392fc9709a3 | 13 | Redistribution and use in source and binary forms, with or without modification, | 
| AnnaBridge | 189:f392fc9709a3 | 14 | are permitted provided that the following conditions are met: | 
| AnnaBridge | 189:f392fc9709a3 | 15 | |
| AnnaBridge | 189:f392fc9709a3 | 16 | 1. Redistributions of source code must retain the above copyright notice, this | 
| AnnaBridge | 189:f392fc9709a3 | 17 | list of conditions and the following disclaimer. | 
| AnnaBridge | 189:f392fc9709a3 | 18 | 2. Redistributions in binary form must reproduce the above copyright notice, | 
| AnnaBridge | 189:f392fc9709a3 | 19 | this list of conditions and the following disclaimer in the documentation | 
| AnnaBridge | 189:f392fc9709a3 | 20 | and/or other materials provided with the distribution. | 
| AnnaBridge | 189:f392fc9709a3 | 21 | 3. Neither the name of the copyright holder nor the names of its contributors | 
| AnnaBridge | 189:f392fc9709a3 | 22 | may be used to endorse or promote products derived from this software without | 
| AnnaBridge | 189:f392fc9709a3 | 23 | specific prior written permission. | 
| AnnaBridge | 189:f392fc9709a3 | 24 | |
| AnnaBridge | 189:f392fc9709a3 | 25 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" | 
| AnnaBridge | 189:f392fc9709a3 | 26 | AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED | 
| AnnaBridge | 189:f392fc9709a3 | 27 | WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. | 
| AnnaBridge | 189:f392fc9709a3 | 28 | IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, | 
| AnnaBridge | 189:f392fc9709a3 | 29 | INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT | 
| AnnaBridge | 189:f392fc9709a3 | 30 | NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR | 
| AnnaBridge | 189:f392fc9709a3 | 31 | PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, | 
| AnnaBridge | 189:f392fc9709a3 | 32 | WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) | 
| AnnaBridge | 189:f392fc9709a3 | 33 | ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY | 
| AnnaBridge | 189:f392fc9709a3 | 34 | OF SUCH DAMAGE. | 
| AnnaBridge | 189:f392fc9709a3 | 35 | */ | 
| AnnaBridge | 189:f392fc9709a3 | 36 | |
| AnnaBridge | 189:f392fc9709a3 | 37 | #ifndef GD32F30X_CAN_H | 
| AnnaBridge | 189:f392fc9709a3 | 38 | #define GD32F30X_CAN_H | 
| AnnaBridge | 189:f392fc9709a3 | 39 | |
| AnnaBridge | 189:f392fc9709a3 | 40 | #include "gd32f30x.h" | 
| AnnaBridge | 189:f392fc9709a3 | 41 | |
| AnnaBridge | 189:f392fc9709a3 | 42 | /* CAN definitions */ | 
| AnnaBridge | 189:f392fc9709a3 | 43 | #define CAN0 CAN_BASE /*!< CAN0 base address */ | 
| AnnaBridge | 189:f392fc9709a3 | 44 | #define CAN1 (CAN0 + 0x00000400U) /*!< CAN1 base address */ | 
| AnnaBridge | 189:f392fc9709a3 | 45 | |
| AnnaBridge | 189:f392fc9709a3 | 46 | /* registers definitions */ | 
| AnnaBridge | 189:f392fc9709a3 | 47 | #define CAN_CTL(canx) REG32((canx) + 0x00U) /*!< CAN control register */ | 
| AnnaBridge | 189:f392fc9709a3 | 48 | #define CAN_STAT(canx) REG32((canx) + 0x04U) /*!< CAN status register */ | 
| AnnaBridge | 189:f392fc9709a3 | 49 | #define CAN_TSTAT(canx) REG32((canx) + 0x08U) /*!< CAN transmit status register*/ | 
| AnnaBridge | 189:f392fc9709a3 | 50 | #define CAN_RFIFO0(canx) REG32((canx) + 0x0CU) /*!< CAN receive FIFO0 register */ | 
| AnnaBridge | 189:f392fc9709a3 | 51 | #define CAN_RFIFO1(canx) REG32((canx) + 0x10U) /*!< CAN receive FIFO1 register */ | 
| AnnaBridge | 189:f392fc9709a3 | 52 | #define CAN_INTEN(canx) REG32((canx) + 0x14U) /*!< CAN interrupt enable register */ | 
| AnnaBridge | 189:f392fc9709a3 | 53 | #define CAN_ERR(canx) REG32((canx) + 0x18U) /*!< CAN error register */ | 
| AnnaBridge | 189:f392fc9709a3 | 54 | #define CAN_BT(canx) REG32((canx) + 0x1CU) /*!< CAN bit timing register */ | 
| AnnaBridge | 189:f392fc9709a3 | 55 | #define CAN_TMI0(canx) REG32((canx) + 0x180U) /*!< CAN transmit mailbox0 identifier register */ | 
| AnnaBridge | 189:f392fc9709a3 | 56 | #define CAN_TMP0(canx) REG32((canx) + 0x184U) /*!< CAN transmit mailbox0 property register */ | 
| AnnaBridge | 189:f392fc9709a3 | 57 | #define CAN_TMDATA00(canx) REG32((canx) + 0x188U) /*!< CAN transmit mailbox0 data0 register */ | 
| AnnaBridge | 189:f392fc9709a3 | 58 | #define CAN_TMDATA10(canx) REG32((canx) + 0x18CU) /*!< CAN transmit mailbox0 data1 register */ | 
| AnnaBridge | 189:f392fc9709a3 | 59 | #define CAN_TMI1(canx) REG32((canx) + 0x190U) /*!< CAN transmit mailbox1 identifier register */ | 
| AnnaBridge | 189:f392fc9709a3 | 60 | #define CAN_TMP1(canx) REG32((canx) + 0x194U) /*!< CAN transmit mailbox1 property register */ | 
| AnnaBridge | 189:f392fc9709a3 | 61 | #define CAN_TMDATA01(canx) REG32((canx) + 0x198U) /*!< CAN transmit mailbox1 data0 register */ | 
| AnnaBridge | 189:f392fc9709a3 | 62 | #define CAN_TMDATA11(canx) REG32((canx) + 0x19CU) /*!< CAN transmit mailbox1 data1 register */ | 
| AnnaBridge | 189:f392fc9709a3 | 63 | #define CAN_TMI2(canx) REG32((canx) + 0x1A0U) /*!< CAN transmit mailbox2 identifier register */ | 
| AnnaBridge | 189:f392fc9709a3 | 64 | #define CAN_TMP2(canx) REG32((canx) + 0x1A4U) /*!< CAN transmit mailbox2 property register */ | 
| AnnaBridge | 189:f392fc9709a3 | 65 | #define CAN_TMDATA02(canx) REG32((canx) + 0x1A8U) /*!< CAN transmit mailbox2 data0 register */ | 
| AnnaBridge | 189:f392fc9709a3 | 66 | #define CAN_TMDATA12(canx) REG32((canx) + 0x1ACU) /*!< CAN transmit mailbox2 data1 register */ | 
| AnnaBridge | 189:f392fc9709a3 | 67 | #define CAN_RFIFOMI0(canx) REG32((canx) + 0x1B0U) /*!< CAN receive FIFO0 mailbox identifier register */ | 
| AnnaBridge | 189:f392fc9709a3 | 68 | #define CAN_RFIFOMP0(canx) REG32((canx) + 0x1B4U) /*!< CAN receive FIFO0 mailbox property register */ | 
| AnnaBridge | 189:f392fc9709a3 | 69 | #define CAN_RFIFOMDATA00(canx) REG32((canx) + 0x1B8U) /*!< CAN receive FIFO0 mailbox data0 register */ | 
| AnnaBridge | 189:f392fc9709a3 | 70 | #define CAN_RFIFOMDATA10(canx) REG32((canx) + 0x1BCU) /*!< CAN receive FIFO0 mailbox data1 register */ | 
| AnnaBridge | 189:f392fc9709a3 | 71 | #define CAN_RFIFOMI1(canx) REG32((canx) + 0x1C0U) /*!< CAN receive FIFO1 mailbox identifier register */ | 
| AnnaBridge | 189:f392fc9709a3 | 72 | #define CAN_RFIFOMP1(canx) REG32((canx) + 0x1C4U) /*!< CAN receive FIFO1 mailbox property register */ | 
| AnnaBridge | 189:f392fc9709a3 | 73 | #define CAN_RFIFOMDATA01(canx) REG32((canx) + 0x1C8U) /*!< CAN receive FIFO1 mailbox data0 register */ | 
| AnnaBridge | 189:f392fc9709a3 | 74 | #define CAN_RFIFOMDATA11(canx) REG32((canx) + 0x1CCU) /*!< CAN receive FIFO1 mailbox data1 register */ | 
| AnnaBridge | 189:f392fc9709a3 | 75 | #define CAN_FCTL(canx) REG32((canx) + 0x200U) /*!< CAN filter control register */ | 
| AnnaBridge | 189:f392fc9709a3 | 76 | #define CAN_FMCFG(canx) REG32((canx) + 0x204U) /*!< CAN filter mode register */ | 
| AnnaBridge | 189:f392fc9709a3 | 77 | #define CAN_FSCFG(canx) REG32((canx) + 0x20CU) /*!< CAN filter scale register */ | 
| AnnaBridge | 189:f392fc9709a3 | 78 | #define CAN_FAFIFO(canx) REG32((canx) + 0x214U) /*!< CAN filter associated FIFO register */ | 
| AnnaBridge | 189:f392fc9709a3 | 79 | #define CAN_FW(canx) REG32((canx) + 0x21CU) /*!< CAN filter working register */ | 
| AnnaBridge | 189:f392fc9709a3 | 80 | #define CAN_F0DATA0(canx) REG32((canx) + 0x240U) /*!< CAN filter 0 data 0 register */ | 
| AnnaBridge | 189:f392fc9709a3 | 81 | #define CAN_F1DATA0(canx) REG32((canx) + 0x248U) /*!< CAN filter 1 data 0 register */ | 
| AnnaBridge | 189:f392fc9709a3 | 82 | #define CAN_F2DATA0(canx) REG32((canx) + 0x250U) /*!< CAN filter 2 data 0 register */ | 
| AnnaBridge | 189:f392fc9709a3 | 83 | #define CAN_F3DATA0(canx) REG32((canx) + 0x258U) /*!< CAN filter 3 data 0 register */ | 
| AnnaBridge | 189:f392fc9709a3 | 84 | #define CAN_F4DATA0(canx) REG32((canx) + 0x260U) /*!< CAN filter 4 data 0 register */ | 
| AnnaBridge | 189:f392fc9709a3 | 85 | #define CAN_F5DATA0(canx) REG32((canx) + 0x268U) /*!< CAN filter 5 data 0 register */ | 
| AnnaBridge | 189:f392fc9709a3 | 86 | #define CAN_F6DATA0(canx) REG32((canx) + 0x270U) /*!< CAN filter 6 data 0 register */ | 
| AnnaBridge | 189:f392fc9709a3 | 87 | #define CAN_F7DATA0(canx) REG32((canx) + 0x278U) /*!< CAN filter 7 data 0 register */ | 
| AnnaBridge | 189:f392fc9709a3 | 88 | #define CAN_F8DATA0(canx) REG32((canx) + 0x280U) /*!< CAN filter 8 data 0 register */ | 
| AnnaBridge | 189:f392fc9709a3 | 89 | #define CAN_F9DATA0(canx) REG32((canx) + 0x288U) /*!< CAN filter 9 data 0 register */ | 
| AnnaBridge | 189:f392fc9709a3 | 90 | #define CAN_F10DATA0(canx) REG32((canx) + 0x290U) /*!< CAN filter 10 data 0 register */ | 
| AnnaBridge | 189:f392fc9709a3 | 91 | #define CAN_F11DATA0(canx) REG32((canx) + 0x298U) /*!< CAN filter 11 data 0 register */ | 
| AnnaBridge | 189:f392fc9709a3 | 92 | #define CAN_F12DATA0(canx) REG32((canx) + 0x2A0U) /*!< CAN filter 12 data 0 register */ | 
| AnnaBridge | 189:f392fc9709a3 | 93 | #define CAN_F13DATA0(canx) REG32((canx) + 0x2A8U) /*!< CAN filter 13 data 0 register */ | 
| AnnaBridge | 189:f392fc9709a3 | 94 | #define CAN_F14DATA0(canx) REG32((canx) + 0x2B0U) /*!< CAN filter 14 data 0 register */ | 
| AnnaBridge | 189:f392fc9709a3 | 95 | #define CAN_F15DATA0(canx) REG32((canx) + 0x2B8U) /*!< CAN filter 15 data 0 register */ | 
| AnnaBridge | 189:f392fc9709a3 | 96 | #define CAN_F16DATA0(canx) REG32((canx) + 0x2C0U) /*!< CAN filter 16 data 0 register */ | 
| AnnaBridge | 189:f392fc9709a3 | 97 | #define CAN_F17DATA0(canx) REG32((canx) + 0x2C8U) /*!< CAN filter 17 data 0 register */ | 
| AnnaBridge | 189:f392fc9709a3 | 98 | #define CAN_F18DATA0(canx) REG32((canx) + 0x2D0U) /*!< CAN filter 18 data 0 register */ | 
| AnnaBridge | 189:f392fc9709a3 | 99 | #define CAN_F19DATA0(canx) REG32((canx) + 0x2D8U) /*!< CAN filter 19 data 0 register */ | 
| AnnaBridge | 189:f392fc9709a3 | 100 | #define CAN_F20DATA0(canx) REG32((canx) + 0x2E0U) /*!< CAN filter 20 data 0 register */ | 
| AnnaBridge | 189:f392fc9709a3 | 101 | #define CAN_F21DATA0(canx) REG32((canx) + 0x2E8U) /*!< CAN filter 21 data 0 register */ | 
| AnnaBridge | 189:f392fc9709a3 | 102 | #define CAN_F22DATA0(canx) REG32((canx) + 0x2F0U) /*!< CAN filter 22 data 0 register */ | 
| AnnaBridge | 189:f392fc9709a3 | 103 | #define CAN_F23DATA0(canx) REG32((canx) + 0x3F8U) /*!< CAN filter 23 data 0 register */ | 
| AnnaBridge | 189:f392fc9709a3 | 104 | #define CAN_F24DATA0(canx) REG32((canx) + 0x300U) /*!< CAN filter 24 data 0 register */ | 
| AnnaBridge | 189:f392fc9709a3 | 105 | #define CAN_F25DATA0(canx) REG32((canx) + 0x308U) /*!< CAN filter 25 data 0 register */ | 
| AnnaBridge | 189:f392fc9709a3 | 106 | #define CAN_F26DATA0(canx) REG32((canx) + 0x310U) /*!< CAN filter 26 data 0 register */ | 
| AnnaBridge | 189:f392fc9709a3 | 107 | #define CAN_F27DATA0(canx) REG32((canx) + 0x318U) /*!< CAN filter 27 data 0 register */ | 
| AnnaBridge | 189:f392fc9709a3 | 108 | #define CAN_F0DATA1(canx) REG32((canx) + 0x244U) /*!< CAN filter 0 data 1 register */ | 
| AnnaBridge | 189:f392fc9709a3 | 109 | #define CAN_F1DATA1(canx) REG32((canx) + 0x24CU) /*!< CAN filter 1 data 1 register */ | 
| AnnaBridge | 189:f392fc9709a3 | 110 | #define CAN_F2DATA1(canx) REG32((canx) + 0x254U) /*!< CAN filter 2 data 1 register */ | 
| AnnaBridge | 189:f392fc9709a3 | 111 | #define CAN_F3DATA1(canx) REG32((canx) + 0x25CU) /*!< CAN filter 3 data 1 register */ | 
| AnnaBridge | 189:f392fc9709a3 | 112 | #define CAN_F4DATA1(canx) REG32((canx) + 0x264U) /*!< CAN filter 4 data 1 register */ | 
| AnnaBridge | 189:f392fc9709a3 | 113 | #define CAN_F5DATA1(canx) REG32((canx) + 0x26CU) /*!< CAN filter 5 data 1 register */ | 
| AnnaBridge | 189:f392fc9709a3 | 114 | #define CAN_F6DATA1(canx) REG32((canx) + 0x274U) /*!< CAN filter 6 data 1 register */ | 
| AnnaBridge | 189:f392fc9709a3 | 115 | #define CAN_F7DATA1(canx) REG32((canx) + 0x27CU) /*!< CAN filter 7 data 1 register */ | 
| AnnaBridge | 189:f392fc9709a3 | 116 | #define CAN_F8DATA1(canx) REG32((canx) + 0x284U) /*!< CAN filter 8 data 1 register */ | 
| AnnaBridge | 189:f392fc9709a3 | 117 | #define CAN_F9DATA1(canx) REG32((canx) + 0x28CU) /*!< CAN filter 9 data 1 register */ | 
| AnnaBridge | 189:f392fc9709a3 | 118 | #define CAN_F10DATA1(canx) REG32((canx) + 0x294U) /*!< CAN filter 10 data 1 register */ | 
| AnnaBridge | 189:f392fc9709a3 | 119 | #define CAN_F11DATA1(canx) REG32((canx) + 0x29CU) /*!< CAN filter 11 data 1 register */ | 
| AnnaBridge | 189:f392fc9709a3 | 120 | #define CAN_F12DATA1(canx) REG32((canx) + 0x2A4U) /*!< CAN filter 12 data 1 register */ | 
| AnnaBridge | 189:f392fc9709a3 | 121 | #define CAN_F13DATA1(canx) REG32((canx) + 0x2ACU) /*!< CAN filter 13 data 1 register */ | 
| AnnaBridge | 189:f392fc9709a3 | 122 | #define CAN_F14DATA1(canx) REG32((canx) + 0x2B4U) /*!< CAN filter 14 data 1 register */ | 
| AnnaBridge | 189:f392fc9709a3 | 123 | #define CAN_F15DATA1(canx) REG32((canx) + 0x2BCU) /*!< CAN filter 15 data 1 register */ | 
| AnnaBridge | 189:f392fc9709a3 | 124 | #define CAN_F16DATA1(canx) REG32((canx) + 0x2C4U) /*!< CAN filter 16 data 1 register */ | 
| AnnaBridge | 189:f392fc9709a3 | 125 | #define CAN_F17DATA1(canx) REG32((canx) + 0x24CU) /*!< CAN filter 17 data 1 register */ | 
| AnnaBridge | 189:f392fc9709a3 | 126 | #define CAN_F18DATA1(canx) REG32((canx) + 0x2D4U) /*!< CAN filter 18 data 1 register */ | 
| AnnaBridge | 189:f392fc9709a3 | 127 | #define CAN_F19DATA1(canx) REG32((canx) + 0x2DCU) /*!< CAN filter 19 data 1 register */ | 
| AnnaBridge | 189:f392fc9709a3 | 128 | #define CAN_F20DATA1(canx) REG32((canx) + 0x2E4U) /*!< CAN filter 20 data 1 register */ | 
| AnnaBridge | 189:f392fc9709a3 | 129 | #define CAN_F21DATA1(canx) REG32((canx) + 0x2ECU) /*!< CAN filter 21 data 1 register */ | 
| AnnaBridge | 189:f392fc9709a3 | 130 | #define CAN_F22DATA1(canx) REG32((canx) + 0x2F4U) /*!< CAN filter 22 data 1 register */ | 
| AnnaBridge | 189:f392fc9709a3 | 131 | #define CAN_F23DATA1(canx) REG32((canx) + 0x2FCU) /*!< CAN filter 23 data 1 register */ | 
| AnnaBridge | 189:f392fc9709a3 | 132 | #define CAN_F24DATA1(canx) REG32((canx) + 0x304U) /*!< CAN filter 24 data 1 register */ | 
| AnnaBridge | 189:f392fc9709a3 | 133 | #define CAN_F25DATA1(canx) REG32((canx) + 0x30CU) /*!< CAN filter 25 data 1 register */ | 
| AnnaBridge | 189:f392fc9709a3 | 134 | #define CAN_F26DATA1(canx) REG32((canx) + 0x314U) /*!< CAN filter 26 data 1 register */ | 
| AnnaBridge | 189:f392fc9709a3 | 135 | #define CAN_F27DATA1(canx) REG32((canx) + 0x31CU) /*!< CAN filter 27 data 1 register */ | 
| AnnaBridge | 189:f392fc9709a3 | 136 | |
| AnnaBridge | 189:f392fc9709a3 | 137 | /* CAN transmit mailbox bank */ | 
| AnnaBridge | 189:f392fc9709a3 | 138 | #define CAN_TMI(canx, bank) REG32((canx) + 0x180U + ((bank) * 0x10U)) /*!< CAN transmit mailbox identifier register */ | 
| AnnaBridge | 189:f392fc9709a3 | 139 | #define CAN_TMP(canx, bank) REG32((canx) + 0x184U + ((bank) * 0x10U)) /*!< CAN transmit mailbox property register */ | 
| AnnaBridge | 189:f392fc9709a3 | 140 | #define CAN_TMDATA0(canx, bank) REG32((canx) + 0x188U + ((bank) * 0x10U)) /*!< CAN transmit mailbox data0 register */ | 
| AnnaBridge | 189:f392fc9709a3 | 141 | #define CAN_TMDATA1(canx, bank) REG32((canx) + 0x18CU + ((bank) * 0x10U)) /*!< CAN transmit mailbox data1 register */ | 
| AnnaBridge | 189:f392fc9709a3 | 142 | |
| AnnaBridge | 189:f392fc9709a3 | 143 | /* CAN filter bank */ | 
| AnnaBridge | 189:f392fc9709a3 | 144 | #define CAN_FDATA0(canx, bank) REG32((canx) + 0x240U + ((bank) * 0x8U) + 0x0U) /*!< CAN filter data 0 register */ | 
| AnnaBridge | 189:f392fc9709a3 | 145 | #define CAN_FDATA1(canx, bank) REG32((canx) + 0x240U + ((bank) * 0x8U) + 0x4U) /*!< CAN filter data 1 register */ | 
| AnnaBridge | 189:f392fc9709a3 | 146 | |
| AnnaBridge | 189:f392fc9709a3 | 147 | /* CAN receive fifo mailbox bank */ | 
| AnnaBridge | 189:f392fc9709a3 | 148 | #define CAN_RFIFOMI(canx, bank) REG32((canx) + 0x1B0U + ((bank) * 0x10U)) /*!< CAN receive FIFO mailbox identifier register */ | 
| AnnaBridge | 189:f392fc9709a3 | 149 | #define CAN_RFIFOMP(canx, bank) REG32((canx) + 0x1B4U + ((bank) * 0x10U)) /*!< CAN receive FIFO mailbox property register */ | 
| AnnaBridge | 189:f392fc9709a3 | 150 | #define CAN_RFIFOMDATA0(canx, bank) REG32((canx) + 0x1B8U + ((bank) * 0x10U)) /*!< CAN receive FIFO mailbox data0 register */ | 
| AnnaBridge | 189:f392fc9709a3 | 151 | #define CAN_RFIFOMDATA1(canx, bank) REG32((canx) + 0x1BCU + ((bank) * 0x10U)) /*!< CAN receive FIFO mailbox data1 register */ | 
| AnnaBridge | 189:f392fc9709a3 | 152 | |
| AnnaBridge | 189:f392fc9709a3 | 153 | /* bits definitions */ | 
| AnnaBridge | 189:f392fc9709a3 | 154 | /* CAN_CTL */ | 
| AnnaBridge | 189:f392fc9709a3 | 155 | #define CAN_CTL_IWMOD BIT(0) /*!< initial working mode */ | 
| AnnaBridge | 189:f392fc9709a3 | 156 | #define CAN_CTL_SLPWMOD BIT(1) /*!< sleep working mode */ | 
| AnnaBridge | 189:f392fc9709a3 | 157 | #define CAN_CTL_TFO BIT(2) /*!< transmit FIFO order */ | 
| AnnaBridge | 189:f392fc9709a3 | 158 | #define CAN_CTL_RFOD BIT(3) /*!< receive FIFO overwrite disable */ | 
| AnnaBridge | 189:f392fc9709a3 | 159 | #define CAN_CTL_ARD BIT(4) /*!< automatic retransmission disable */ | 
| AnnaBridge | 189:f392fc9709a3 | 160 | #define CAN_CTL_AWU BIT(5) /*!< automatic wakeup */ | 
| AnnaBridge | 189:f392fc9709a3 | 161 | #define CAN_CTL_ABOR BIT(6) /*!< automatic bus-off recovery */ | 
| AnnaBridge | 189:f392fc9709a3 | 162 | #define CAN_CTL_TTC BIT(7) /*!< time triggered communication */ | 
| AnnaBridge | 189:f392fc9709a3 | 163 | #define CAN_CTL_SWRST BIT(15) /*!< CAN software reset */ | 
| AnnaBridge | 189:f392fc9709a3 | 164 | #define CAN_CTL_DFZ BIT(16) /*!< CAN debug freeze */ | 
| AnnaBridge | 189:f392fc9709a3 | 165 | |
| AnnaBridge | 189:f392fc9709a3 | 166 | /* CAN_STAT */ | 
| AnnaBridge | 189:f392fc9709a3 | 167 | #define CAN_STAT_IWS BIT(0) /*!< initial working state */ | 
| AnnaBridge | 189:f392fc9709a3 | 168 | #define CAN_STAT_SLPWS BIT(1) /*!< sleep working state */ | 
| AnnaBridge | 189:f392fc9709a3 | 169 | #define CAN_STAT_ERRIF BIT(2) /*!< error interrupt flag*/ | 
| AnnaBridge | 189:f392fc9709a3 | 170 | #define CAN_STAT_WUIF BIT(3) /*!< status change interrupt flag of wakeup from sleep working mode */ | 
| AnnaBridge | 189:f392fc9709a3 | 171 | #define CAN_STAT_SLPIF BIT(4) /*!< status change interrupt flag of sleep working mode entering */ | 
| AnnaBridge | 189:f392fc9709a3 | 172 | #define CAN_STAT_TS BIT(8) /*!< transmitting state */ | 
| AnnaBridge | 189:f392fc9709a3 | 173 | #define CAN_STAT_RS BIT(9) /*!< receiving state */ | 
| AnnaBridge | 189:f392fc9709a3 | 174 | #define CAN_STAT_LASTRX BIT(10) /*!< last sample value of rx pin */ | 
| AnnaBridge | 189:f392fc9709a3 | 175 | #define CAN_STAT_RXL BIT(11) /*!< CAN rx signal */ | 
| AnnaBridge | 189:f392fc9709a3 | 176 | |
| AnnaBridge | 189:f392fc9709a3 | 177 | /* CAN_TSTAT */ | 
| AnnaBridge | 189:f392fc9709a3 | 178 | #define CAN_TSTAT_MTF0 BIT(0) /*!< mailbox0 transmit finished */ | 
| AnnaBridge | 189:f392fc9709a3 | 179 | #define CAN_TSTAT_MTFNERR0 BIT(1) /*!< mailbox0 transmit finished and no error */ | 
| AnnaBridge | 189:f392fc9709a3 | 180 | #define CAN_TSTAT_MAL0 BIT(2) /*!< mailbox0 arbitration lost */ | 
| AnnaBridge | 189:f392fc9709a3 | 181 | #define CAN_TSTAT_MTE0 BIT(3) /*!< mailbox0 transmit error */ | 
| AnnaBridge | 189:f392fc9709a3 | 182 | #define CAN_TSTAT_MST0 BIT(7) /*!< mailbox0 stop transmitting */ | 
| AnnaBridge | 189:f392fc9709a3 | 183 | #define CAN_TSTAT_MTF1 BIT(8) /*!< mailbox1 transmit finished */ | 
| AnnaBridge | 189:f392fc9709a3 | 184 | #define CAN_TSTAT_MTFNERR1 BIT(9) /*!< mailbox1 transmit finished and no error */ | 
| AnnaBridge | 189:f392fc9709a3 | 185 | #define CAN_TSTAT_MAL1 BIT(10) /*!< mailbox1 arbitration lost */ | 
| AnnaBridge | 189:f392fc9709a3 | 186 | #define CAN_TSTAT_MTE1 BIT(11) /*!< mailbox1 transmit error */ | 
| AnnaBridge | 189:f392fc9709a3 | 187 | #define CAN_TSTAT_MST1 BIT(15) /*!< mailbox1 stop transmitting */ | 
| AnnaBridge | 189:f392fc9709a3 | 188 | #define CAN_TSTAT_MTF2 BIT(16) /*!< mailbox2 transmit finished */ | 
| AnnaBridge | 189:f392fc9709a3 | 189 | #define CAN_TSTAT_MTFNERR2 BIT(17) /*!< mailbox2 transmit finished and no error */ | 
| AnnaBridge | 189:f392fc9709a3 | 190 | #define CAN_TSTAT_MAL2 BIT(18) /*!< mailbox2 arbitration lost */ | 
| AnnaBridge | 189:f392fc9709a3 | 191 | #define CAN_TSTAT_MTE2 BIT(19) /*!< mailbox2 transmit error */ | 
| AnnaBridge | 189:f392fc9709a3 | 192 | #define CAN_TSTAT_MST2 BIT(23) /*!< mailbox2 stop transmitting */ | 
| AnnaBridge | 189:f392fc9709a3 | 193 | #define CAN_TSTAT_NUM BITS(24,25) /*!< mailbox number */ | 
| AnnaBridge | 189:f392fc9709a3 | 194 | #define CAN_TSTAT_TME0 BIT(26) /*!< transmit mailbox0 empty */ | 
| AnnaBridge | 189:f392fc9709a3 | 195 | #define CAN_TSTAT_TME1 BIT(27) /*!< transmit mailbox1 empty */ | 
| AnnaBridge | 189:f392fc9709a3 | 196 | #define CAN_TSTAT_TME2 BIT(28) /*!< transmit mailbox2 empty */ | 
| AnnaBridge | 189:f392fc9709a3 | 197 | #define CAN_TSTAT_TMLS0 BIT(29) /*!< last sending priority flag for mailbox0 */ | 
| AnnaBridge | 189:f392fc9709a3 | 198 | #define CAN_TSTAT_TMLS1 BIT(30) /*!< last sending priority flag for mailbox1 */ | 
| AnnaBridge | 189:f392fc9709a3 | 199 | #define CAN_TSTAT_TMLS2 BIT(31) /*!< last sending priority flag for mailbox2 */ | 
| AnnaBridge | 189:f392fc9709a3 | 200 | |
| AnnaBridge | 189:f392fc9709a3 | 201 | /* CAN_RFIFO0 */ | 
| AnnaBridge | 189:f392fc9709a3 | 202 | #define CAN_RFIFO0_RFL0 BITS(0,1) /*!< receive FIFO0 length */ | 
| AnnaBridge | 189:f392fc9709a3 | 203 | #define CAN_RFIFO0_RFF0 BIT(3) /*!< receive FIFO0 full */ | 
| AnnaBridge | 189:f392fc9709a3 | 204 | #define CAN_RFIFO0_RFO0 BIT(4) /*!< receive FIFO0 overfull */ | 
| AnnaBridge | 189:f392fc9709a3 | 205 | #define CAN_RFIFO0_RFD0 BIT(5) /*!< receive FIFO0 dequeue */ | 
| AnnaBridge | 189:f392fc9709a3 | 206 | |
| AnnaBridge | 189:f392fc9709a3 | 207 | /* CAN_RFIFO1 */ | 
| AnnaBridge | 189:f392fc9709a3 | 208 | #define CAN_RFIFO1_RFL1 BITS(0,1) /*!< receive FIFO1 length */ | 
| AnnaBridge | 189:f392fc9709a3 | 209 | #define CAN_RFIFO1_RFF1 BIT(3) /*!< receive FIFO1 full */ | 
| AnnaBridge | 189:f392fc9709a3 | 210 | #define CAN_RFIFO1_RFO1 BIT(4) /*!< receive FIFO1 overfull */ | 
| AnnaBridge | 189:f392fc9709a3 | 211 | #define CAN_RFIFO1_RFD1 BIT(5) /*!< receive FIFO1 dequeue */ | 
| AnnaBridge | 189:f392fc9709a3 | 212 | |
| AnnaBridge | 189:f392fc9709a3 | 213 | /* CAN_INTEN */ | 
| AnnaBridge | 189:f392fc9709a3 | 214 | #define CAN_INTEN_TMEIE BIT(0) /*!< transmit mailbox empty interrupt enable */ | 
| AnnaBridge | 189:f392fc9709a3 | 215 | #define CAN_INTEN_RFNEIE0 BIT(1) /*!< receive FIFO0 not empty interrupt enable */ | 
| AnnaBridge | 189:f392fc9709a3 | 216 | #define CAN_INTEN_RFFIE0 BIT(2) /*!< receive FIFO0 full interrupt enable */ | 
| AnnaBridge | 189:f392fc9709a3 | 217 | #define CAN_INTEN_RFOIE0 BIT(3) /*!< receive FIFO0 overfull interrupt enable */ | 
| AnnaBridge | 189:f392fc9709a3 | 218 | #define CAN_INTEN_RFNEIE1 BIT(4) /*!< receive FIFO1 not empty interrupt enable */ | 
| AnnaBridge | 189:f392fc9709a3 | 219 | #define CAN_INTEN_RFFIE1 BIT(5) /*!< receive FIFO1 full interrupt enable */ | 
| AnnaBridge | 189:f392fc9709a3 | 220 | #define CAN_INTEN_RFOIE1 BIT(6) /*!< receive FIFO1 overfull interrupt enable */ | 
| AnnaBridge | 189:f392fc9709a3 | 221 | #define CAN_INTEN_WERRIE BIT(8) /*!< warning error interrupt enable */ | 
| AnnaBridge | 189:f392fc9709a3 | 222 | #define CAN_INTEN_PERRIE BIT(9) /*!< passive error interrupt enable */ | 
| AnnaBridge | 189:f392fc9709a3 | 223 | #define CAN_INTEN_BOIE BIT(10) /*!< bus-off interrupt enable */ | 
| AnnaBridge | 189:f392fc9709a3 | 224 | #define CAN_INTEN_ERRNIE BIT(11) /*!< error number interrupt enable */ | 
| AnnaBridge | 189:f392fc9709a3 | 225 | #define CAN_INTEN_ERRIE BIT(15) /*!< error interrupt enable */ | 
| AnnaBridge | 189:f392fc9709a3 | 226 | #define CAN_INTEN_WIE BIT(16) /*!< wakeup interrupt enable */ | 
| AnnaBridge | 189:f392fc9709a3 | 227 | #define CAN_INTEN_SLPWIE BIT(17) /*!< sleep working interrupt enable */ | 
| AnnaBridge | 189:f392fc9709a3 | 228 | |
| AnnaBridge | 189:f392fc9709a3 | 229 | /* CAN_ERR */ | 
| AnnaBridge | 189:f392fc9709a3 | 230 | #define CAN_ERR_WERR BIT(0) /*!< warning error */ | 
| AnnaBridge | 189:f392fc9709a3 | 231 | #define CAN_ERR_PERR BIT(1) /*!< passive error */ | 
| AnnaBridge | 189:f392fc9709a3 | 232 | #define CAN_ERR_BOERR BIT(2) /*!< bus-off error */ | 
| AnnaBridge | 189:f392fc9709a3 | 233 | #define CAN_ERR_ERRN BITS(4,6) /*!< error number */ | 
| AnnaBridge | 189:f392fc9709a3 | 234 | #define CAN_ERR_TECNT BITS(16,23) /*!< transmit error count */ | 
| AnnaBridge | 189:f392fc9709a3 | 235 | #define CAN_ERR_RECNT BITS(24,31) /*!< receive error count */ | 
| AnnaBridge | 189:f392fc9709a3 | 236 | |
| AnnaBridge | 189:f392fc9709a3 | 237 | /* CAN_BT */ | 
| AnnaBridge | 189:f392fc9709a3 | 238 | #define CAN_BT_BAUDPSC BITS(0,9) /*!< baudrate prescaler */ | 
| AnnaBridge | 189:f392fc9709a3 | 239 | #define CAN_BT_BS1 BITS(16,19) /*!< bit segment 1 */ | 
| AnnaBridge | 189:f392fc9709a3 | 240 | #define CAN_BT_BS2 BITS(20,22) /*!< bit segment 2 */ | 
| AnnaBridge | 189:f392fc9709a3 | 241 | #define CAN_BT_SJW BITS(24,25) /*!< resynchronization jump width */ | 
| AnnaBridge | 189:f392fc9709a3 | 242 | #define CAN_BT_LCMOD BIT(30) /*!< loopback communication mode */ | 
| AnnaBridge | 189:f392fc9709a3 | 243 | #define CAN_BT_SCMOD BIT(31) /*!< silent communication mode */ | 
| AnnaBridge | 189:f392fc9709a3 | 244 | |
| AnnaBridge | 189:f392fc9709a3 | 245 | /* CAN_TMIx */ | 
| AnnaBridge | 189:f392fc9709a3 | 246 | #define CAN_TMI_TEN BIT(0) /*!< transmit enable */ | 
| AnnaBridge | 189:f392fc9709a3 | 247 | #define CAN_TMI_FT BIT(1) /*!< frame type */ | 
| AnnaBridge | 189:f392fc9709a3 | 248 | #define CAN_TMI_FF BIT(2) /*!< frame format */ | 
| AnnaBridge | 189:f392fc9709a3 | 249 | #define CAN_TMI_EFID BITS(3,31) /*!< the frame identifier */ | 
| AnnaBridge | 189:f392fc9709a3 | 250 | #define CAN_TMI_SFID BITS(21,31) /*!< the frame identifier */ | 
| AnnaBridge | 189:f392fc9709a3 | 251 | |
| AnnaBridge | 189:f392fc9709a3 | 252 | /* CAN_TMPx */ | 
| AnnaBridge | 189:f392fc9709a3 | 253 | #define CAN_TMP_DLENC BITS(0,3) /*!< data length code */ | 
| AnnaBridge | 189:f392fc9709a3 | 254 | #define CAN_TMP_TSEN BIT(8) /*!< time stamp enable */ | 
| AnnaBridge | 189:f392fc9709a3 | 255 | #define CAN_TMP_TS BITS(16,31) /*!< time stamp */ | 
| AnnaBridge | 189:f392fc9709a3 | 256 | |
| AnnaBridge | 189:f392fc9709a3 | 257 | /* CAN_TMDATA0x */ | 
| AnnaBridge | 189:f392fc9709a3 | 258 | #define CAN_TMDATA0_DB0 BITS(0,7) /*!< transmit data byte 0 */ | 
| AnnaBridge | 189:f392fc9709a3 | 259 | #define CAN_TMDATA0_DB1 BITS(8,15) /*!< transmit data byte 1 */ | 
| AnnaBridge | 189:f392fc9709a3 | 260 | #define CAN_TMDATA0_DB2 BITS(16,23) /*!< transmit data byte 2 */ | 
| AnnaBridge | 189:f392fc9709a3 | 261 | #define CAN_TMDATA0_DB3 BITS(24,31) /*!< transmit data byte 3 */ | 
| AnnaBridge | 189:f392fc9709a3 | 262 | |
| AnnaBridge | 189:f392fc9709a3 | 263 | /* CAN_TMDATA1x */ | 
| AnnaBridge | 189:f392fc9709a3 | 264 | #define CAN_TMDATA1_DB4 BITS(0,7) /*!< transmit data byte 4 */ | 
| AnnaBridge | 189:f392fc9709a3 | 265 | #define CAN_TMDATA1_DB5 BITS(8,15) /*!< transmit data byte 5 */ | 
| AnnaBridge | 189:f392fc9709a3 | 266 | #define CAN_TMDATA1_DB6 BITS(16,23) /*!< transmit data byte 6 */ | 
| AnnaBridge | 189:f392fc9709a3 | 267 | #define CAN_TMDATA1_DB7 BITS(24,31) /*!< transmit data byte 7 */ | 
| AnnaBridge | 189:f392fc9709a3 | 268 | |
| AnnaBridge | 189:f392fc9709a3 | 269 | /* CAN_RFIFOMIx */ | 
| AnnaBridge | 189:f392fc9709a3 | 270 | #define CAN_RFIFOMI_FT BIT(1) /*!< frame type */ | 
| AnnaBridge | 189:f392fc9709a3 | 271 | #define CAN_RFIFOMI_FF BIT(2) /*!< frame format */ | 
| AnnaBridge | 189:f392fc9709a3 | 272 | #define CAN_RFIFOMI_EFID BITS(3,31) /*!< the frame identifier */ | 
| AnnaBridge | 189:f392fc9709a3 | 273 | #define CAN_RFIFOMI_SFID BITS(21,31) /*!< the frame identifier */ | 
| AnnaBridge | 189:f392fc9709a3 | 274 | |
| AnnaBridge | 189:f392fc9709a3 | 275 | /* CAN_RFIFOMPx */ | 
| AnnaBridge | 189:f392fc9709a3 | 276 | #define CAN_RFIFOMP_DLENC BITS(0,3) /*!< receive data length code */ | 
| AnnaBridge | 189:f392fc9709a3 | 277 | #define CAN_RFIFOMP_FI BITS(8,15) /*!< filter index */ | 
| AnnaBridge | 189:f392fc9709a3 | 278 | #define CAN_RFIFOMP_TS BITS(16,31) /*!< time stamp */ | 
| AnnaBridge | 189:f392fc9709a3 | 279 | |
| AnnaBridge | 189:f392fc9709a3 | 280 | /* CAN_RFIFOMDATA0x */ | 
| AnnaBridge | 189:f392fc9709a3 | 281 | #define CAN_RFIFOMDATA0_DB0 BITS(0,7) /*!< receive data byte 0 */ | 
| AnnaBridge | 189:f392fc9709a3 | 282 | #define CAN_RFIFOMDATA0_DB1 BITS(8,15) /*!< receive data byte 1 */ | 
| AnnaBridge | 189:f392fc9709a3 | 283 | #define CAN_RFIFOMDATA0_DB2 BITS(16,23) /*!< receive data byte 2 */ | 
| AnnaBridge | 189:f392fc9709a3 | 284 | #define CAN_RFIFOMDATA0_DB3 BITS(24,31) /*!< receive data byte 3 */ | 
| AnnaBridge | 189:f392fc9709a3 | 285 | |
| AnnaBridge | 189:f392fc9709a3 | 286 | /* CAN_RFIFOMDATA1x */ | 
| AnnaBridge | 189:f392fc9709a3 | 287 | #define CAN_RFIFOMDATA1_DB4 BITS(0,7) /*!< receive data byte 4 */ | 
| AnnaBridge | 189:f392fc9709a3 | 288 | #define CAN_RFIFOMDATA1_DB5 BITS(8,15) /*!< receive data byte 5 */ | 
| AnnaBridge | 189:f392fc9709a3 | 289 | #define CAN_RFIFOMDATA1_DB6 BITS(16,23) /*!< receive data byte 6 */ | 
| AnnaBridge | 189:f392fc9709a3 | 290 | #define CAN_RFIFOMDATA1_DB7 BITS(24,31) /*!< receive data byte 7 */ | 
| AnnaBridge | 189:f392fc9709a3 | 291 | |
| AnnaBridge | 189:f392fc9709a3 | 292 | /* CAN_FCTL */ | 
| AnnaBridge | 189:f392fc9709a3 | 293 | #define CAN_FCTL_FLD BIT(0) /*!< filter lock disable */ | 
| AnnaBridge | 189:f392fc9709a3 | 294 | #define CAN_FCTL_HBC1F BITS(8,13) /*!< header bank of CAN1 filter */ | 
| AnnaBridge | 189:f392fc9709a3 | 295 | |
| AnnaBridge | 189:f392fc9709a3 | 296 | /* CAN_FMCFG */ | 
| AnnaBridge | 189:f392fc9709a3 | 297 | #define CAN_FMCFG_FMOD(regval) BIT(regval) /*!< filter mode, list or mask*/ | 
| AnnaBridge | 189:f392fc9709a3 | 298 | |
| AnnaBridge | 189:f392fc9709a3 | 299 | /* CAN_FSCFG */ | 
| AnnaBridge | 189:f392fc9709a3 | 300 | #define CAN_FSCFG_FS(regval) BIT(regval) /*!< filter scale, 32 bits or 16 bits*/ | 
| AnnaBridge | 189:f392fc9709a3 | 301 | |
| AnnaBridge | 189:f392fc9709a3 | 302 | /* CAN_FAFIFO */ | 
| AnnaBridge | 189:f392fc9709a3 | 303 | #define CAN_FAFIFOR_FAF(regval) BIT(regval) /*!< filter associated with FIFO */ | 
| AnnaBridge | 189:f392fc9709a3 | 304 | |
| AnnaBridge | 189:f392fc9709a3 | 305 | /* CAN_FW */ | 
| AnnaBridge | 189:f392fc9709a3 | 306 | #define CAN_FW_FW(regval) BIT(regval) /*!< filter working */ | 
| AnnaBridge | 189:f392fc9709a3 | 307 | |
| AnnaBridge | 189:f392fc9709a3 | 308 | /* CAN_FxDATAy */ | 
| AnnaBridge | 189:f392fc9709a3 | 309 | #define CAN_FDATA_FD BITS(0,31) /*!< filter data */ | 
| AnnaBridge | 189:f392fc9709a3 | 310 | |
| AnnaBridge | 189:f392fc9709a3 | 311 | /* consts definitions */ | 
| AnnaBridge | 189:f392fc9709a3 | 312 | /* define the CAN bit position and its register index offset */ | 
| AnnaBridge | 189:f392fc9709a3 | 313 | #define CAN_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos)) | 
| AnnaBridge | 189:f392fc9709a3 | 314 | #define CAN_REG_VAL(canx, offset) (REG32((canx) + ((uint32_t)(offset) >> 6))) | 
| AnnaBridge | 189:f392fc9709a3 | 315 | #define CAN_BIT_POS(val) ((uint32_t)(val) & 0x1FU) | 
| AnnaBridge | 189:f392fc9709a3 | 316 | |
| AnnaBridge | 189:f392fc9709a3 | 317 | #define CAN_REGIDX_BITS(regidx, bitpos0, bitpos1) (((uint32_t)(regidx) << 12) | ((uint32_t)(bitpos0) << 6) | (uint32_t)(bitpos1)) | 
| AnnaBridge | 189:f392fc9709a3 | 318 | #define CAN_REG_VALS(canx, offset) (REG32((canx) + ((uint32_t)(offset) >> 12))) | 
| AnnaBridge | 189:f392fc9709a3 | 319 | #define CAN_BIT_POS0(val) (((uint32_t)(val) >> 6) & 0x1FU) | 
| AnnaBridge | 189:f392fc9709a3 | 320 | #define CAN_BIT_POS1(val) ((uint32_t)(val) & 0x1FU) | 
| AnnaBridge | 189:f392fc9709a3 | 321 | |
| AnnaBridge | 189:f392fc9709a3 | 322 | /* register offset */ | 
| AnnaBridge | 189:f392fc9709a3 | 323 | #define STAT_REG_OFFSET ((uint8_t)0x04U) /*!< STAT register offset */ | 
| AnnaBridge | 189:f392fc9709a3 | 324 | #define TSTAT_REG_OFFSET ((uint8_t)0x08U) /*!< TSTAT register offset */ | 
| AnnaBridge | 189:f392fc9709a3 | 325 | #define RFIFO0_REG_OFFSET ((uint8_t)0x0CU) /*!< RFIFO0 register offset */ | 
| AnnaBridge | 189:f392fc9709a3 | 326 | #define RFIFO1_REG_OFFSET ((uint8_t)0x10U) /*!< RFIFO1 register offset */ | 
| AnnaBridge | 189:f392fc9709a3 | 327 | #define ERR_REG_OFFSET ((uint8_t)0x18U) /*!< ERR register offset */ | 
| AnnaBridge | 189:f392fc9709a3 | 328 | |
| AnnaBridge | 189:f392fc9709a3 | 329 | /* CAN flags */ | 
| AnnaBridge | 189:f392fc9709a3 | 330 | typedef enum { | 
| AnnaBridge | 189:f392fc9709a3 | 331 | /* flags in TSTAT register */ | 
| AnnaBridge | 189:f392fc9709a3 | 332 | CAN_FLAG_MTE2 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 19U), /*!< mailbox 2 transmit error */ | 
| AnnaBridge | 189:f392fc9709a3 | 333 | CAN_FLAG_MTE1 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 11U), /*!< mailbox 1 transmit error */ | 
| AnnaBridge | 189:f392fc9709a3 | 334 | CAN_FLAG_MTE0 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 3U), /*!< mailbox 0 transmit error */ | 
| AnnaBridge | 189:f392fc9709a3 | 335 | CAN_FLAG_MTF2 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 16U), /*!< mailbox 2 transmit finished */ | 
| AnnaBridge | 189:f392fc9709a3 | 336 | CAN_FLAG_MTF1 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 8U), /*!< mailbox 1 transmit finished */ | 
| AnnaBridge | 189:f392fc9709a3 | 337 | CAN_FLAG_MTF0 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 0U), /*!< mailbox 0 transmit finished */ | 
| AnnaBridge | 189:f392fc9709a3 | 338 | /* flags in RFIFO0 register */ | 
| AnnaBridge | 189:f392fc9709a3 | 339 | CAN_FLAG_RFO0 = CAN_REGIDX_BIT(RFIFO0_REG_OFFSET, 4U), /*!< receive FIFO0 overfull */ | 
| AnnaBridge | 189:f392fc9709a3 | 340 | CAN_FLAG_RFF0 = CAN_REGIDX_BIT(RFIFO0_REG_OFFSET, 3U), /*!< receive FIFO0 full */ | 
| AnnaBridge | 189:f392fc9709a3 | 341 | /* flags in RFIFO1 register */ | 
| AnnaBridge | 189:f392fc9709a3 | 342 | CAN_FLAG_RFO1 = CAN_REGIDX_BIT(RFIFO1_REG_OFFSET, 4U), /*!< receive FIFO1 overfull */ | 
| AnnaBridge | 189:f392fc9709a3 | 343 | CAN_FLAG_RFF1 = CAN_REGIDX_BIT(RFIFO1_REG_OFFSET, 3U), /*!< receive FIFO1 full */ | 
| AnnaBridge | 189:f392fc9709a3 | 344 | /* flags in ERR register */ | 
| AnnaBridge | 189:f392fc9709a3 | 345 | CAN_FLAG_BOERR = CAN_REGIDX_BIT(ERR_REG_OFFSET, 2U), /*!< bus-off error */ | 
| AnnaBridge | 189:f392fc9709a3 | 346 | CAN_FLAG_PERR = CAN_REGIDX_BIT(ERR_REG_OFFSET, 1U), /*!< passive error */ | 
| AnnaBridge | 189:f392fc9709a3 | 347 | CAN_FLAG_WERR = CAN_REGIDX_BIT(ERR_REG_OFFSET, 0U), /*!< warning error */ | 
| AnnaBridge | 189:f392fc9709a3 | 348 | } can_flag_enum; | 
| AnnaBridge | 189:f392fc9709a3 | 349 | |
| AnnaBridge | 189:f392fc9709a3 | 350 | /* CAN interrupt flags */ | 
| AnnaBridge | 189:f392fc9709a3 | 351 | typedef enum { | 
| AnnaBridge | 189:f392fc9709a3 | 352 | /* interrupt flags in STAT register */ | 
| AnnaBridge | 189:f392fc9709a3 | 353 | CAN_INT_FLAG_SLPIF = CAN_REGIDX_BITS(STAT_REG_OFFSET, 4U, 17U), /*!< status change interrupt flag of sleep working mode entering */ | 
| AnnaBridge | 189:f392fc9709a3 | 354 | CAN_INT_FLAG_WUIF = CAN_REGIDX_BITS(STAT_REG_OFFSET, 3U, 16), /*!< status change interrupt flag of wakeup from sleep working mode */ | 
| AnnaBridge | 189:f392fc9709a3 | 355 | CAN_INT_FLAG_ERRIF = CAN_REGIDX_BITS(STAT_REG_OFFSET, 2U, 15), /*!< error interrupt flag */ | 
| AnnaBridge | 189:f392fc9709a3 | 356 | /* interrupt flags in TSTAT register */ | 
| AnnaBridge | 189:f392fc9709a3 | 357 | CAN_INT_FLAG_MTF2 = CAN_REGIDX_BITS(TSTAT_REG_OFFSET, 16U, 0U), /*!< mailbox 2 transmit finished interrupt flag */ | 
| AnnaBridge | 189:f392fc9709a3 | 358 | CAN_INT_FLAG_MTF1 = CAN_REGIDX_BITS(TSTAT_REG_OFFSET, 8U, 0U), /*!< mailbox 1 transmit finished interrupt flag */ | 
| AnnaBridge | 189:f392fc9709a3 | 359 | CAN_INT_FLAG_MTF0 = CAN_REGIDX_BITS(TSTAT_REG_OFFSET, 0U, 0U), /*!< mailbox 0 transmit finished interrupt flag */ | 
| AnnaBridge | 189:f392fc9709a3 | 360 | /* interrupt flags in RFIFO0 register */ | 
| AnnaBridge | 189:f392fc9709a3 | 361 | CAN_INT_FLAG_RFO0 = CAN_REGIDX_BITS(RFIFO0_REG_OFFSET, 4U, 3U), /*!< receive FIFO0 overfull interrupt flag */ | 
| AnnaBridge | 189:f392fc9709a3 | 362 | CAN_INT_FLAG_RFF0 = CAN_REGIDX_BITS(RFIFO0_REG_OFFSET, 3U, 2U), /*!< receive FIFO0 full interrupt flag */ | 
| AnnaBridge | 189:f392fc9709a3 | 363 | /* interrupt flags in RFIFO0 register */ | 
| AnnaBridge | 189:f392fc9709a3 | 364 | CAN_INT_FLAG_RFO1 = CAN_REGIDX_BITS(RFIFO1_REG_OFFSET, 4U, 6U), /*!< receive FIFO1 overfull interrupt flag */ | 
| AnnaBridge | 189:f392fc9709a3 | 365 | CAN_INT_FLAG_RFF1 = CAN_REGIDX_BITS(RFIFO1_REG_OFFSET, 3U, 5U), /*!< receive FIFO1 full interrupt flag */ | 
| AnnaBridge | 189:f392fc9709a3 | 366 | } can_interrupt_flag_enum; | 
| AnnaBridge | 189:f392fc9709a3 | 367 | |
| AnnaBridge | 189:f392fc9709a3 | 368 | /* CAN initiliaze parameters struct */ | 
| AnnaBridge | 189:f392fc9709a3 | 369 | typedef struct { | 
| AnnaBridge | 189:f392fc9709a3 | 370 | uint8_t working_mode; /*!< CAN working mode */ | 
| AnnaBridge | 189:f392fc9709a3 | 371 | uint8_t resync_jump_width; /*!< CAN resynchronization jump width */ | 
| AnnaBridge | 189:f392fc9709a3 | 372 | uint8_t time_segment_1; /*!< time segment 1 */ | 
| AnnaBridge | 189:f392fc9709a3 | 373 | uint8_t time_segment_2; /*!< time segment 2 */ | 
| AnnaBridge | 189:f392fc9709a3 | 374 | ControlStatus time_triggered; /*!< time triggered communication mode */ | 
| AnnaBridge | 189:f392fc9709a3 | 375 | ControlStatus auto_bus_off_recovery; /*!< automatic bus-off recovery */ | 
| AnnaBridge | 189:f392fc9709a3 | 376 | ControlStatus auto_wake_up; /*!< automatic wake-up mode */ | 
| AnnaBridge | 189:f392fc9709a3 | 377 | ControlStatus auto_retrans; /*!< automatic retransmission mode */ | 
| AnnaBridge | 189:f392fc9709a3 | 378 | ControlStatus rec_fifo_overwrite; /*!< receive FIFO overwrite mode */ | 
| AnnaBridge | 189:f392fc9709a3 | 379 | ControlStatus trans_fifo_order; /*!< transmit FIFO order */ | 
| AnnaBridge | 189:f392fc9709a3 | 380 | uint16_t prescaler; /*!< baudrate prescaler */ | 
| AnnaBridge | 189:f392fc9709a3 | 381 | } can_parameter_struct; | 
| AnnaBridge | 189:f392fc9709a3 | 382 | |
| AnnaBridge | 189:f392fc9709a3 | 383 | /* CAN transmit message struct */ | 
| AnnaBridge | 189:f392fc9709a3 | 384 | typedef struct { | 
| AnnaBridge | 189:f392fc9709a3 | 385 | uint32_t tx_sfid; /*!< standard format frame identifier */ | 
| AnnaBridge | 189:f392fc9709a3 | 386 | uint32_t tx_efid; /*!< extended format frame identifier */ | 
| AnnaBridge | 189:f392fc9709a3 | 387 | uint8_t tx_ff; /*!< format of frame, standard or extended format */ | 
| AnnaBridge | 189:f392fc9709a3 | 388 | uint8_t tx_ft; /*!< type of frame, data or remote */ | 
| AnnaBridge | 189:f392fc9709a3 | 389 | uint8_t tx_dlen; /*!< data length */ | 
| AnnaBridge | 189:f392fc9709a3 | 390 | uint8_t tx_data[8]; /*!< transmit data */ | 
| AnnaBridge | 189:f392fc9709a3 | 391 | } can_trasnmit_message_struct; | 
| AnnaBridge | 189:f392fc9709a3 | 392 | |
| AnnaBridge | 189:f392fc9709a3 | 393 | /* CAN receive message struct */ | 
| AnnaBridge | 189:f392fc9709a3 | 394 | typedef struct { | 
| AnnaBridge | 189:f392fc9709a3 | 395 | uint32_t rx_sfid; /*!< standard format frame identifier */ | 
| AnnaBridge | 189:f392fc9709a3 | 396 | uint32_t rx_efid; /*!< extended format frame identifier */ | 
| AnnaBridge | 189:f392fc9709a3 | 397 | uint8_t rx_ff; /*!< format of frame, standard or extended format */ | 
| AnnaBridge | 189:f392fc9709a3 | 398 | uint8_t rx_ft; /*!< type of frame, data or remote */ | 
| AnnaBridge | 189:f392fc9709a3 | 399 | uint8_t rx_dlen; /*!< data length */ | 
| AnnaBridge | 189:f392fc9709a3 | 400 | uint8_t rx_data[8]; /*!< receive data */ | 
| AnnaBridge | 189:f392fc9709a3 | 401 | uint8_t rx_fi; /*!< filtering index */ | 
| AnnaBridge | 189:f392fc9709a3 | 402 | } can_receive_message_struct; | 
| AnnaBridge | 189:f392fc9709a3 | 403 | |
| AnnaBridge | 189:f392fc9709a3 | 404 | /* CAN filter parameters struct */ | 
| AnnaBridge | 189:f392fc9709a3 | 405 | typedef struct { | 
| AnnaBridge | 189:f392fc9709a3 | 406 | uint16_t filter_list_high; /*!< filter list number high bits*/ | 
| AnnaBridge | 189:f392fc9709a3 | 407 | uint16_t filter_list_low; /*!< filter list number low bits */ | 
| AnnaBridge | 189:f392fc9709a3 | 408 | uint16_t filter_mask_high; /*!< filter mask number high bits */ | 
| AnnaBridge | 189:f392fc9709a3 | 409 | uint16_t filter_mask_low; /*!< filter mask number low bits */ | 
| AnnaBridge | 189:f392fc9709a3 | 410 | uint16_t filter_fifo_number; /*!< receive FIFO associated with the filter */ | 
| AnnaBridge | 189:f392fc9709a3 | 411 | uint16_t filter_number; /*!< filter number */ | 
| AnnaBridge | 189:f392fc9709a3 | 412 | uint16_t filter_mode; /*!< filter mode, list or mask */ | 
| AnnaBridge | 189:f392fc9709a3 | 413 | uint16_t filter_bits; /*!< filter scale */ | 
| AnnaBridge | 189:f392fc9709a3 | 414 | ControlStatus filter_enable; /*!< filter work or not */ | 
| AnnaBridge | 189:f392fc9709a3 | 415 | } can_filter_parameter_struct; | 
| AnnaBridge | 189:f392fc9709a3 | 416 | |
| AnnaBridge | 189:f392fc9709a3 | 417 | /* CAN errors */ | 
| AnnaBridge | 189:f392fc9709a3 | 418 | typedef enum { | 
| AnnaBridge | 189:f392fc9709a3 | 419 | CAN_ERROR_NONE = 0, /*!< no error */ | 
| AnnaBridge | 189:f392fc9709a3 | 420 | CAN_ERROR_FILL, /*!< fill error */ | 
| AnnaBridge | 189:f392fc9709a3 | 421 | CAN_ERROR_FORMATE, /*!< format error */ | 
| AnnaBridge | 189:f392fc9709a3 | 422 | CAN_ERROR_ACK, /*!< ACK error */ | 
| AnnaBridge | 189:f392fc9709a3 | 423 | CAN_ERROR_BITRECESSIVE, /*!< bit recessive error */ | 
| AnnaBridge | 189:f392fc9709a3 | 424 | CAN_ERROR_BITDOMINANTER, /*!< bit dominant error */ | 
| AnnaBridge | 189:f392fc9709a3 | 425 | CAN_ERROR_CRC, /*!< CRC error */ | 
| AnnaBridge | 189:f392fc9709a3 | 426 | CAN_ERROR_SOFTWARECFG, /*!< software configure */ | 
| AnnaBridge | 189:f392fc9709a3 | 427 | } can_error_enum; | 
| AnnaBridge | 189:f392fc9709a3 | 428 | |
| AnnaBridge | 189:f392fc9709a3 | 429 | /* transmit states */ | 
| AnnaBridge | 189:f392fc9709a3 | 430 | typedef enum { | 
| AnnaBridge | 189:f392fc9709a3 | 431 | CAN_TRANSMIT_FAILED = 0, /*!< CAN transmitted failure */ | 
| AnnaBridge | 189:f392fc9709a3 | 432 | CAN_TRANSMIT_OK = 1, /*!< CAN transmitted success */ | 
| AnnaBridge | 189:f392fc9709a3 | 433 | CAN_TRANSMIT_PENDING = 2, /*!< CAN transmitted pending */ | 
| AnnaBridge | 189:f392fc9709a3 | 434 | CAN_TRANSMIT_NOMAILBOX = 4, /*!< no empty mailbox to be used for CAN */ | 
| AnnaBridge | 189:f392fc9709a3 | 435 | } can_transmit_state_enum; | 
| AnnaBridge | 189:f392fc9709a3 | 436 | |
| AnnaBridge | 189:f392fc9709a3 | 437 | /* CAN baudrate prescaler*/ | 
| AnnaBridge | 189:f392fc9709a3 | 438 | #define BT_BAUDPSC(regval) (BITS(0,9) & ((uint32_t)(regval) << 0)) | 
| AnnaBridge | 189:f392fc9709a3 | 439 | |
| AnnaBridge | 189:f392fc9709a3 | 440 | /* CAN bit segment 1*/ | 
| AnnaBridge | 189:f392fc9709a3 | 441 | #define BT_BS1(regval) (BITS(16,19) & ((uint32_t)(regval) << 16)) | 
| AnnaBridge | 189:f392fc9709a3 | 442 | |
| AnnaBridge | 189:f392fc9709a3 | 443 | /* CAN bit segment 2*/ | 
| AnnaBridge | 189:f392fc9709a3 | 444 | #define BT_BS2(regval) (BITS(20,22) & ((uint32_t)(regval) << 20)) | 
| AnnaBridge | 189:f392fc9709a3 | 445 | |
| AnnaBridge | 189:f392fc9709a3 | 446 | /* CAN resynchronization jump width*/ | 
| AnnaBridge | 189:f392fc9709a3 | 447 | #define BT_SJW(regval) (BITS(24,25) & ((uint32_t)(regval) << 24)) | 
| AnnaBridge | 189:f392fc9709a3 | 448 | |
| AnnaBridge | 189:f392fc9709a3 | 449 | /* CAN communication mode*/ | 
| AnnaBridge | 189:f392fc9709a3 | 450 | #define BT_MODE(regval) (BITS(30,31) & ((uint32_t)(regval) << 30)) | 
| AnnaBridge | 189:f392fc9709a3 | 451 | |
| AnnaBridge | 189:f392fc9709a3 | 452 | /* CAN FDATA high 16 bits */ | 
| AnnaBridge | 189:f392fc9709a3 | 453 | #define FDATA_MASK_HIGH(regval) (BITS(16,31) & ((uint32_t)(regval) << 16)) | 
| AnnaBridge | 189:f392fc9709a3 | 454 | |
| AnnaBridge | 189:f392fc9709a3 | 455 | /* CAN FDATA low 16 bits */ | 
| AnnaBridge | 189:f392fc9709a3 | 456 | #define FDATA_MASK_LOW(regval) (BITS(0,15) & ((uint32_t)(regval) << 0)) | 
| AnnaBridge | 189:f392fc9709a3 | 457 | |
| AnnaBridge | 189:f392fc9709a3 | 458 | /* CAN1 filter start bank_number*/ | 
| AnnaBridge | 189:f392fc9709a3 | 459 | #define FCTL_HBC1F(regval) (BITS(8,13) & ((uint32_t)(regval) << 8)) | 
| AnnaBridge | 189:f392fc9709a3 | 460 | |
| AnnaBridge | 189:f392fc9709a3 | 461 | /* CAN transmit mailbox extended identifier*/ | 
| AnnaBridge | 189:f392fc9709a3 | 462 | #define TMI_EFID(regval) (BITS(3,31) & ((uint32_t)(regval) << 3)) | 
| AnnaBridge | 189:f392fc9709a3 | 463 | |
| AnnaBridge | 189:f392fc9709a3 | 464 | /* CAN transmit mailbox standard identifier*/ | 
| AnnaBridge | 189:f392fc9709a3 | 465 | #define TMI_SFID(regval) (BITS(21,31) & ((uint32_t)(regval) << 21)) | 
| AnnaBridge | 189:f392fc9709a3 | 466 | |
| AnnaBridge | 189:f392fc9709a3 | 467 | /* transmit data byte 0 */ | 
| AnnaBridge | 189:f392fc9709a3 | 468 | #define TMDATA0_DB0(regval) (BITS(0,7) & ((uint32_t)(regval) << 0)) | 
| AnnaBridge | 189:f392fc9709a3 | 469 | |
| AnnaBridge | 189:f392fc9709a3 | 470 | /* transmit data byte 1 */ | 
| AnnaBridge | 189:f392fc9709a3 | 471 | #define TMDATA0_DB1(regval) (BITS(8,15) & ((uint32_t)(regval) << 8)) | 
| AnnaBridge | 189:f392fc9709a3 | 472 | |
| AnnaBridge | 189:f392fc9709a3 | 473 | /* transmit data byte 2 */ | 
| AnnaBridge | 189:f392fc9709a3 | 474 | #define TMDATA0_DB2(regval) (BITS(16,23) & ((uint32_t)(regval) << 16)) | 
| AnnaBridge | 189:f392fc9709a3 | 475 | |
| AnnaBridge | 189:f392fc9709a3 | 476 | /* transmit data byte 3 */ | 
| AnnaBridge | 189:f392fc9709a3 | 477 | #define TMDATA0_DB3(regval) (BITS(24,31) & ((uint32_t)(regval) << 24)) | 
| AnnaBridge | 189:f392fc9709a3 | 478 | |
| AnnaBridge | 189:f392fc9709a3 | 479 | /* transmit data byte 4 */ | 
| AnnaBridge | 189:f392fc9709a3 | 480 | #define TMDATA1_DB4(regval) (BITS(0,7) & ((uint32_t)(regval) << 0)) | 
| AnnaBridge | 189:f392fc9709a3 | 481 | |
| AnnaBridge | 189:f392fc9709a3 | 482 | /* transmit data byte 5 */ | 
| AnnaBridge | 189:f392fc9709a3 | 483 | #define TMDATA1_DB5(regval) (BITS(8,15) & ((uint32_t)(regval) << 8)) | 
| AnnaBridge | 189:f392fc9709a3 | 484 | |
| AnnaBridge | 189:f392fc9709a3 | 485 | /* transmit data byte 6 */ | 
| AnnaBridge | 189:f392fc9709a3 | 486 | #define TMDATA1_DB6(regval) (BITS(16,23) & ((uint32_t)(regval) << 16)) | 
| AnnaBridge | 189:f392fc9709a3 | 487 | |
| AnnaBridge | 189:f392fc9709a3 | 488 | /* transmit data byte 7 */ | 
| AnnaBridge | 189:f392fc9709a3 | 489 | #define TMDATA1_DB7(regval) (BITS(24,31) & ((uint32_t)(regval) << 24)) | 
| AnnaBridge | 189:f392fc9709a3 | 490 | |
| AnnaBridge | 189:f392fc9709a3 | 491 | /* receive mailbox extended identifier*/ | 
| AnnaBridge | 189:f392fc9709a3 | 492 | #define RFIFOMI_EFID(regval) GET_BITS((uint32_t)(regval), 3, 31) | 
| AnnaBridge | 189:f392fc9709a3 | 493 | |
| AnnaBridge | 189:f392fc9709a3 | 494 | /* receive mailbox standrad identifier*/ | 
| AnnaBridge | 189:f392fc9709a3 | 495 | #define RFIFOMI_SFID(regval) GET_BITS((uint32_t)(regval), 21, 31) | 
| AnnaBridge | 189:f392fc9709a3 | 496 | |
| AnnaBridge | 189:f392fc9709a3 | 497 | /* receive data length */ | 
| AnnaBridge | 189:f392fc9709a3 | 498 | #define RFIFOMP_DLENC(regval) GET_BITS((uint32_t)(regval), 0, 3) | 
| AnnaBridge | 189:f392fc9709a3 | 499 | |
| AnnaBridge | 189:f392fc9709a3 | 500 | /* the index of the filter by which the frame is passed */ | 
| AnnaBridge | 189:f392fc9709a3 | 501 | #define RFIFOMP_FI(regval) GET_BITS((uint32_t)(regval), 8, 15) | 
| AnnaBridge | 189:f392fc9709a3 | 502 | |
| AnnaBridge | 189:f392fc9709a3 | 503 | /* receive data byte 0 */ | 
| AnnaBridge | 189:f392fc9709a3 | 504 | #define RFIFOMDATA0_DB0(regval) GET_BITS((uint32_t)(regval), 0, 7) | 
| AnnaBridge | 189:f392fc9709a3 | 505 | |
| AnnaBridge | 189:f392fc9709a3 | 506 | /* receive data byte 1 */ | 
| AnnaBridge | 189:f392fc9709a3 | 507 | #define RFIFOMDATA0_DB1(regval) GET_BITS((uint32_t)(regval), 8, 15) | 
| AnnaBridge | 189:f392fc9709a3 | 508 | |
| AnnaBridge | 189:f392fc9709a3 | 509 | /* receive data byte 2 */ | 
| AnnaBridge | 189:f392fc9709a3 | 510 | #define RFIFOMDATA0_DB2(regval) GET_BITS((uint32_t)(regval), 16, 23) | 
| AnnaBridge | 189:f392fc9709a3 | 511 | |
| AnnaBridge | 189:f392fc9709a3 | 512 | /* receive data byte 3 */ | 
| AnnaBridge | 189:f392fc9709a3 | 513 | #define RFIFOMDATA0_DB3(regval) GET_BITS((uint32_t)(regval), 24, 31) | 
| AnnaBridge | 189:f392fc9709a3 | 514 | |
| AnnaBridge | 189:f392fc9709a3 | 515 | /* receive data byte 4 */ | 
| AnnaBridge | 189:f392fc9709a3 | 516 | #define RFIFOMDATA1_DB4(regval) GET_BITS((uint32_t)(regval), 0, 7) | 
| AnnaBridge | 189:f392fc9709a3 | 517 | |
| AnnaBridge | 189:f392fc9709a3 | 518 | /* receive data byte 5 */ | 
| AnnaBridge | 189:f392fc9709a3 | 519 | #define RFIFOMDATA1_DB5(regval) GET_BITS((uint32_t)(regval), 8, 15) | 
| AnnaBridge | 189:f392fc9709a3 | 520 | |
| AnnaBridge | 189:f392fc9709a3 | 521 | /* receive data byte 6 */ | 
| AnnaBridge | 189:f392fc9709a3 | 522 | #define RFIFOMDATA1_DB6(regval) GET_BITS((uint32_t)(regval), 16, 23) | 
| AnnaBridge | 189:f392fc9709a3 | 523 | |
| AnnaBridge | 189:f392fc9709a3 | 524 | /* receive data byte 7 */ | 
| AnnaBridge | 189:f392fc9709a3 | 525 | #define RFIFOMDATA1_DB7(regval) GET_BITS((uint32_t)(regval), 24, 31) | 
| AnnaBridge | 189:f392fc9709a3 | 526 | |
| AnnaBridge | 189:f392fc9709a3 | 527 | /* CAN errors */ | 
| AnnaBridge | 189:f392fc9709a3 | 528 | #define ERR_ERRN(regval) (BITS(4,6) & ((uint32_t)(regval) << 4)) | 
| AnnaBridge | 189:f392fc9709a3 | 529 | #define CAN_ERRN_0 ERR_ERRN(0) /* no error */ | 
| AnnaBridge | 189:f392fc9709a3 | 530 | #define CAN_ERRN_1 ERR_ERRN(1) /*!< fill error */ | 
| AnnaBridge | 189:f392fc9709a3 | 531 | #define CAN_ERRN_2 ERR_ERRN(2) /*!< format error */ | 
| AnnaBridge | 189:f392fc9709a3 | 532 | #define CAN_ERRN_3 ERR_ERRN(3) /*!< ACK error */ | 
| AnnaBridge | 189:f392fc9709a3 | 533 | #define CAN_ERRN_4 ERR_ERRN(4) /*!< bit recessive error */ | 
| AnnaBridge | 189:f392fc9709a3 | 534 | #define CAN_ERRN_5 ERR_ERRN(5) /*!< bit dominant error */ | 
| AnnaBridge | 189:f392fc9709a3 | 535 | #define CAN_ERRN_6 ERR_ERRN(6) /*!< CRC error */ | 
| AnnaBridge | 189:f392fc9709a3 | 536 | #define CAN_ERRN_7 ERR_ERRN(7) /*!< software error */ | 
| AnnaBridge | 189:f392fc9709a3 | 537 | |
| AnnaBridge | 189:f392fc9709a3 | 538 | #define CAN_STATE_PENDING ((uint32_t)0x00000000U) /*!< CAN pending */ | 
| AnnaBridge | 189:f392fc9709a3 | 539 | |
| AnnaBridge | 189:f392fc9709a3 | 540 | /* CAN communication mode */ | 
| AnnaBridge | 189:f392fc9709a3 | 541 | #define CAN_NORMAL_MODE ((uint8_t)0x00U) /*!< normal communication mode */ | 
| AnnaBridge | 189:f392fc9709a3 | 542 | #define CAN_LOOPBACK_MODE ((uint8_t)0x01U) /*!< loopback communication mode */ | 
| AnnaBridge | 189:f392fc9709a3 | 543 | #define CAN_SILENT_MODE ((uint8_t)0x02U) /*!< silent communication mode */ | 
| AnnaBridge | 189:f392fc9709a3 | 544 | #define CAN_SILENT_LOOPBACK_MODE ((uint8_t)0x03U) /*!< loopback and silent communication mode */ | 
| AnnaBridge | 189:f392fc9709a3 | 545 | |
| AnnaBridge | 189:f392fc9709a3 | 546 | /* CAN resynchronisation jump width */ | 
| AnnaBridge | 189:f392fc9709a3 | 547 | #define CAN_BT_SJW_1TQ ((uint8_t)0x00U) /*!< 1 time quanta */ | 
| AnnaBridge | 189:f392fc9709a3 | 548 | #define CAN_BT_SJW_2TQ ((uint8_t)0x01U) /*!< 2 time quanta */ | 
| AnnaBridge | 189:f392fc9709a3 | 549 | #define CAN_BT_SJW_3TQ ((uint8_t)0x02U) /*!< 3 time quanta */ | 
| AnnaBridge | 189:f392fc9709a3 | 550 | #define CAN_BT_SJW_4TQ ((uint8_t)0x03U) /*!< 4 time quanta */ | 
| AnnaBridge | 189:f392fc9709a3 | 551 | |
| AnnaBridge | 189:f392fc9709a3 | 552 | /* CAN time segment 1 */ | 
| AnnaBridge | 189:f392fc9709a3 | 553 | #define CAN_BT_BS1_1TQ ((uint8_t)0x00U) /*!< 1 time quanta */ | 
| AnnaBridge | 189:f392fc9709a3 | 554 | #define CAN_BT_BS1_2TQ ((uint8_t)0x01U) /*!< 2 time quanta */ | 
| AnnaBridge | 189:f392fc9709a3 | 555 | #define CAN_BT_BS1_3TQ ((uint8_t)0x02U) /*!< 3 time quanta */ | 
| AnnaBridge | 189:f392fc9709a3 | 556 | #define CAN_BT_BS1_4TQ ((uint8_t)0x03U) /*!< 4 time quanta */ | 
| AnnaBridge | 189:f392fc9709a3 | 557 | #define CAN_BT_BS1_5TQ ((uint8_t)0x04U) /*!< 5 time quanta */ | 
| AnnaBridge | 189:f392fc9709a3 | 558 | #define CAN_BT_BS1_6TQ ((uint8_t)0x05U) /*!< 6 time quanta */ | 
| AnnaBridge | 189:f392fc9709a3 | 559 | #define CAN_BT_BS1_7TQ ((uint8_t)0x06U) /*!< 7 time quanta */ | 
| AnnaBridge | 189:f392fc9709a3 | 560 | #define CAN_BT_BS1_8TQ ((uint8_t)0x07U) /*!< 8 time quanta */ | 
| AnnaBridge | 189:f392fc9709a3 | 561 | #define CAN_BT_BS1_9TQ ((uint8_t)0x08U) /*!< 9 time quanta */ | 
| AnnaBridge | 189:f392fc9709a3 | 562 | #define CAN_BT_BS1_10TQ ((uint8_t)0x09U) /*!< 10 time quanta */ | 
| AnnaBridge | 189:f392fc9709a3 | 563 | #define CAN_BT_BS1_11TQ ((uint8_t)0x0AU) /*!< 11 time quanta */ | 
| AnnaBridge | 189:f392fc9709a3 | 564 | #define CAN_BT_BS1_12TQ ((uint8_t)0x0BU) /*!< 12 time quanta */ | 
| AnnaBridge | 189:f392fc9709a3 | 565 | #define CAN_BT_BS1_13TQ ((uint8_t)0x0CU) /*!< 13 time quanta */ | 
| AnnaBridge | 189:f392fc9709a3 | 566 | #define CAN_BT_BS1_14TQ ((uint8_t)0x0DU) /*!< 14 time quanta */ | 
| AnnaBridge | 189:f392fc9709a3 | 567 | #define CAN_BT_BS1_15TQ ((uint8_t)0x0EU) /*!< 15 time quanta */ | 
| AnnaBridge | 189:f392fc9709a3 | 568 | #define CAN_BT_BS1_16TQ ((uint8_t)0x0FU) /*!< 16 time quanta */ | 
| AnnaBridge | 189:f392fc9709a3 | 569 | |
| AnnaBridge | 189:f392fc9709a3 | 570 | /* CAN time segment 2 */ | 
| AnnaBridge | 189:f392fc9709a3 | 571 | #define CAN_BT_BS2_1TQ ((uint8_t)0x00U) /*!< 1 time quanta */ | 
| AnnaBridge | 189:f392fc9709a3 | 572 | #define CAN_BT_BS2_2TQ ((uint8_t)0x01U) /*!< 2 time quanta */ | 
| AnnaBridge | 189:f392fc9709a3 | 573 | #define CAN_BT_BS2_3TQ ((uint8_t)0x02U) /*!< 3 time quanta */ | 
| AnnaBridge | 189:f392fc9709a3 | 574 | #define CAN_BT_BS2_4TQ ((uint8_t)0x03U) /*!< 4 time quanta */ | 
| AnnaBridge | 189:f392fc9709a3 | 575 | #define CAN_BT_BS2_5TQ ((uint8_t)0x04U) /*!< 5 time quanta */ | 
| AnnaBridge | 189:f392fc9709a3 | 576 | #define CAN_BT_BS2_6TQ ((uint8_t)0x05U) /*!< 6 time quanta */ | 
| AnnaBridge | 189:f392fc9709a3 | 577 | #define CAN_BT_BS2_7TQ ((uint8_t)0x06U) /*!< 7 time quanta */ | 
| AnnaBridge | 189:f392fc9709a3 | 578 | #define CAN_BT_BS2_8TQ ((uint8_t)0x07U) /*!< 8 time quanta */ | 
| AnnaBridge | 189:f392fc9709a3 | 579 | |
| AnnaBridge | 189:f392fc9709a3 | 580 | /* CAN mailbox number */ | 
| AnnaBridge | 189:f392fc9709a3 | 581 | #define CAN_MAILBOX0 ((uint8_t)0x00U) /*!< mailbox0 */ | 
| AnnaBridge | 189:f392fc9709a3 | 582 | #define CAN_MAILBOX1 ((uint8_t)0x01U) /*!< mailbox1 */ | 
| AnnaBridge | 189:f392fc9709a3 | 583 | #define CAN_MAILBOX2 ((uint8_t)0x02U) /*!< mailbox2 */ | 
| AnnaBridge | 189:f392fc9709a3 | 584 | #define CAN_NOMAILBOX ((uint8_t)0x03U) /*!< no mailbox empty */ | 
| AnnaBridge | 189:f392fc9709a3 | 585 | |
| AnnaBridge | 189:f392fc9709a3 | 586 | /* CAN frame format */ | 
| AnnaBridge | 189:f392fc9709a3 | 587 | #define CAN_FF_STANDARD ((uint32_t)0x00000000U) /*!< standard frame */ | 
| AnnaBridge | 189:f392fc9709a3 | 588 | #define CAN_FF_EXTENDED ((uint32_t)0x00000004U) /*!< extended frame */ | 
| AnnaBridge | 189:f392fc9709a3 | 589 | |
| AnnaBridge | 189:f392fc9709a3 | 590 | /* CAN receive fifo */ | 
| AnnaBridge | 189:f392fc9709a3 | 591 | #define CAN_FIFO0 ((uint8_t)0x00U) /*!< receive FIFO0 */ | 
| AnnaBridge | 189:f392fc9709a3 | 592 | #define CAN_FIFO1 ((uint8_t)0x01U) /*!< receive FIFO1 */ | 
| AnnaBridge | 189:f392fc9709a3 | 593 | |
| AnnaBridge | 189:f392fc9709a3 | 594 | /* frame number of receive fifo */ | 
| AnnaBridge | 189:f392fc9709a3 | 595 | #define CAN_RFIF_RFL_MASK ((uint32_t)0x00000003U) /*!< mask for frame number in receive FIFOx */ | 
| AnnaBridge | 189:f392fc9709a3 | 596 | |
| AnnaBridge | 189:f392fc9709a3 | 597 | #define CAN_SFID_MASK ((uint32_t)0x000007FFU) /*!< mask of standard identifier */ | 
| AnnaBridge | 189:f392fc9709a3 | 598 | #define CAN_EFID_MASK ((uint32_t)0x1FFFFFFFU) /*!< mask of extended identifier */ | 
| AnnaBridge | 189:f392fc9709a3 | 599 | |
| AnnaBridge | 189:f392fc9709a3 | 600 | /* CAN working mode */ | 
| AnnaBridge | 189:f392fc9709a3 | 601 | #define CAN_MODE_INITIALIZE ((uint8_t)0x01U) /*!< CAN initialize mode */ | 
| AnnaBridge | 189:f392fc9709a3 | 602 | #define CAN_MODE_NORMAL ((uint8_t)0x02U) /*!< CAN normal mode */ | 
| AnnaBridge | 189:f392fc9709a3 | 603 | #define CAN_MODE_SLEEP ((uint8_t)0x04U) /*!< CAN sleep mode */ | 
| AnnaBridge | 189:f392fc9709a3 | 604 | |
| AnnaBridge | 189:f392fc9709a3 | 605 | /* filter bits */ | 
| AnnaBridge | 189:f392fc9709a3 | 606 | #define CAN_FILTERBITS_16BIT ((uint8_t)0x00U) /*!< CAN filter 16 bits */ | 
| AnnaBridge | 189:f392fc9709a3 | 607 | #define CAN_FILTERBITS_32BIT ((uint8_t)0x01U) /*!< CAN filter 32 bits */ | 
| AnnaBridge | 189:f392fc9709a3 | 608 | |
| AnnaBridge | 189:f392fc9709a3 | 609 | /* filter mode */ | 
| AnnaBridge | 189:f392fc9709a3 | 610 | #define CAN_FILTERMODE_MASK ((uint8_t)0x00U) /*!< mask mode */ | 
| AnnaBridge | 189:f392fc9709a3 | 611 | #define CAN_FILTERMODE_LIST ((uint8_t)0x01U) /*!< list mode */ | 
| AnnaBridge | 189:f392fc9709a3 | 612 | |
| AnnaBridge | 189:f392fc9709a3 | 613 | /* filter 16 bits mask */ | 
| AnnaBridge | 189:f392fc9709a3 | 614 | #define CAN_FILTER_MASK_16BITS ((uint32_t)0x0000FFFFU) | 
| AnnaBridge | 189:f392fc9709a3 | 615 | |
| AnnaBridge | 189:f392fc9709a3 | 616 | /* frame type */ | 
| AnnaBridge | 189:f392fc9709a3 | 617 | #define CAN_FT_DATA ((uint32_t)0x00000000U) /*!< data frame */ | 
| AnnaBridge | 189:f392fc9709a3 | 618 | #define CAN_FT_REMOTE ((uint32_t)0x00000002U) /*!< remote frame */ | 
| AnnaBridge | 189:f392fc9709a3 | 619 | |
| AnnaBridge | 189:f392fc9709a3 | 620 | /* CAN timeout */ | 
| AnnaBridge | 189:f392fc9709a3 | 621 | #define CAN_TIMEOUT ((uint32_t)0x0000FFFFU) /*!< timeout value */ | 
| AnnaBridge | 189:f392fc9709a3 | 622 | |
| AnnaBridge | 189:f392fc9709a3 | 623 | /* interrupt enable bits */ | 
| AnnaBridge | 189:f392fc9709a3 | 624 | #define CAN_INT_TME CAN_INTEN_TMEIE /*!< transmit mailbox empty interrupt enable */ | 
| AnnaBridge | 189:f392fc9709a3 | 625 | #define CAN_INT_RFNE0 CAN_INTEN_RFNEIE0 /*!< receive FIFO0 not empty interrupt enable */ | 
| AnnaBridge | 189:f392fc9709a3 | 626 | #define CAN_INT_RFF0 CAN_INTEN_RFFIE0 /*!< receive FIFO0 full interrupt enable */ | 
| AnnaBridge | 189:f392fc9709a3 | 627 | #define CAN_INT_RFO0 CAN_INTEN_RFOIE0 /*!< receive FIFO0 overfull interrupt enable */ | 
| AnnaBridge | 189:f392fc9709a3 | 628 | #define CAN_INT_RFNE1 CAN_INTEN_RFNEIE1 /*!< receive FIFO1 not empty interrupt enable */ | 
| AnnaBridge | 189:f392fc9709a3 | 629 | #define CAN_INT_RFF1 CAN_INTEN_RFFIE1 /*!< receive FIFO1 full interrupt enable */ | 
| AnnaBridge | 189:f392fc9709a3 | 630 | #define CAN_INT_RFO1 CAN_INTEN_RFOIE1 /*!< receive FIFO1 overfull interrupt enable */ | 
| AnnaBridge | 189:f392fc9709a3 | 631 | #define CAN_INT_WERR CAN_INTEN_WERRIE /*!< warning error interrupt enable */ | 
| AnnaBridge | 189:f392fc9709a3 | 632 | #define CAN_INT_PERR CAN_INTEN_PERRIE /*!< passive error interrupt enable */ | 
| AnnaBridge | 189:f392fc9709a3 | 633 | #define CAN_INT_BO CAN_INTEN_BOIE /*!< bus-off interrupt enable */ | 
| AnnaBridge | 189:f392fc9709a3 | 634 | #define CAN_INT_ERRN CAN_INTEN_ERRNIE /*!< error number interrupt enable */ | 
| AnnaBridge | 189:f392fc9709a3 | 635 | #define CAN_INT_ERR CAN_INTEN_ERRIE /*!< error interrupt enable */ | 
| AnnaBridge | 189:f392fc9709a3 | 636 | #define CAN_INT_WAKEUP CAN_INTEN_WIE /*!< wakeup interrupt enable */ | 
| AnnaBridge | 189:f392fc9709a3 | 637 | #define CAN_INT_SLPW CAN_INTEN_SLPWIE /*!< sleep working interrupt enable */ | 
| AnnaBridge | 189:f392fc9709a3 | 638 | |
| AnnaBridge | 189:f392fc9709a3 | 639 | /* function declarations */ | 
| AnnaBridge | 189:f392fc9709a3 | 640 | /* deinitialize CAN */ | 
| AnnaBridge | 189:f392fc9709a3 | 641 | void can_deinit(uint32_t can_periph); | 
| AnnaBridge | 189:f392fc9709a3 | 642 | /* initialize CAN */ | 
| AnnaBridge | 189:f392fc9709a3 | 643 | #ifdef GD_MBED_USED | 
| AnnaBridge | 189:f392fc9709a3 | 644 | ErrStatus can_para_init(uint32_t can_periph, can_parameter_struct *can_parameter_init); | 
| AnnaBridge | 189:f392fc9709a3 | 645 | #else | 
| AnnaBridge | 189:f392fc9709a3 | 646 | ErrStatus can_init(uint32_t can_periph, can_parameter_struct *can_parameter_init); | 
| AnnaBridge | 189:f392fc9709a3 | 647 | #endif | 
| AnnaBridge | 189:f392fc9709a3 | 648 | /* CAN filter init */ | 
| AnnaBridge | 189:f392fc9709a3 | 649 | void can_filter_init(can_filter_parameter_struct *can_filter_parameter_init); | 
| AnnaBridge | 189:f392fc9709a3 | 650 | |
| AnnaBridge | 189:f392fc9709a3 | 651 | /* set can1 fliter start bank number */ | 
| AnnaBridge | 189:f392fc9709a3 | 652 | void can1_filter_start_bank(uint8_t start_bank); | 
| AnnaBridge | 189:f392fc9709a3 | 653 | /* enable functions */ | 
| AnnaBridge | 189:f392fc9709a3 | 654 | /* CAN debug freeze enable */ | 
| AnnaBridge | 189:f392fc9709a3 | 655 | void can_debug_freeze_enable(uint32_t can_periph); | 
| AnnaBridge | 189:f392fc9709a3 | 656 | /* CAN debug freeze disable */ | 
| AnnaBridge | 189:f392fc9709a3 | 657 | void can_debug_freeze_disable(uint32_t can_periph); | 
| AnnaBridge | 189:f392fc9709a3 | 658 | /* CAN time triggle mode enable */ | 
| AnnaBridge | 189:f392fc9709a3 | 659 | void can_time_trigger_mode_enable(uint32_t can_periph); | 
| AnnaBridge | 189:f392fc9709a3 | 660 | /* CAN time triggle mode disable */ | 
| AnnaBridge | 189:f392fc9709a3 | 661 | void can_time_trigger_mode_disable(uint32_t can_periph); | 
| AnnaBridge | 189:f392fc9709a3 | 662 | |
| AnnaBridge | 189:f392fc9709a3 | 663 | /* transmit functions */ | 
| AnnaBridge | 189:f392fc9709a3 | 664 | /* transmit CAN message */ | 
| AnnaBridge | 189:f392fc9709a3 | 665 | uint8_t can_message_transmit(uint32_t can_periph, can_trasnmit_message_struct *transmit_message); | 
| AnnaBridge | 189:f392fc9709a3 | 666 | /* get CAN transmit state */ | 
| AnnaBridge | 189:f392fc9709a3 | 667 | can_transmit_state_enum can_transmit_states(uint32_t can_periph, uint8_t mailbox_number); | 
| AnnaBridge | 189:f392fc9709a3 | 668 | /* stop CAN transmission */ | 
| AnnaBridge | 189:f392fc9709a3 | 669 | void can_transmission_stop(uint32_t can_periph, uint8_t mailbox_number); | 
| AnnaBridge | 189:f392fc9709a3 | 670 | /* CAN receive message */ | 
| AnnaBridge | 189:f392fc9709a3 | 671 | void can_message_receive(uint32_t can_periph, uint8_t fifo_number, can_receive_message_struct *receive_message); | 
| AnnaBridge | 189:f392fc9709a3 | 672 | /* CAN release fifo */ | 
| AnnaBridge | 189:f392fc9709a3 | 673 | void can_fifo_release(uint32_t can_periph, uint8_t fifo_number); | 
| AnnaBridge | 189:f392fc9709a3 | 674 | /* CAN receive message length */ | 
| AnnaBridge | 189:f392fc9709a3 | 675 | uint8_t can_receive_message_length_get(uint32_t can_periph, uint8_t fifo_number); | 
| AnnaBridge | 189:f392fc9709a3 | 676 | /* CAN working mode */ | 
| AnnaBridge | 189:f392fc9709a3 | 677 | ErrStatus can_working_mode_set(uint32_t can_periph, uint8_t working_mode); | 
| AnnaBridge | 189:f392fc9709a3 | 678 | /* CAN wakeup from sleep mode */ | 
| AnnaBridge | 189:f392fc9709a3 | 679 | ErrStatus can_wakeup(uint32_t can_periph); | 
| AnnaBridge | 189:f392fc9709a3 | 680 | |
| AnnaBridge | 189:f392fc9709a3 | 681 | /* CAN get error */ | 
| AnnaBridge | 189:f392fc9709a3 | 682 | can_error_enum can_error_get(uint32_t can_periph); | 
| AnnaBridge | 189:f392fc9709a3 | 683 | /* get CAN receive error number */ | 
| AnnaBridge | 189:f392fc9709a3 | 684 | uint8_t can_receive_error_number_get(uint32_t can_periph); | 
| AnnaBridge | 189:f392fc9709a3 | 685 | /* get CAN transmit error number */ | 
| AnnaBridge | 189:f392fc9709a3 | 686 | uint8_t can_transmit_error_number_get(uint32_t can_periph); | 
| AnnaBridge | 189:f392fc9709a3 | 687 | |
| AnnaBridge | 189:f392fc9709a3 | 688 | /* CAN interrupt enable */ | 
| AnnaBridge | 189:f392fc9709a3 | 689 | void can_interrupt_enable(uint32_t can_periph, uint32_t interrupt); | 
| AnnaBridge | 189:f392fc9709a3 | 690 | /* CAN interrupt disable */ | 
| AnnaBridge | 189:f392fc9709a3 | 691 | void can_interrupt_disable(uint32_t can_periph, uint32_t interrupt); | 
| AnnaBridge | 189:f392fc9709a3 | 692 | /* CAN get flag state */ | 
| AnnaBridge | 189:f392fc9709a3 | 693 | FlagStatus can_flag_get(uint32_t can_periph, can_flag_enum flag); | 
| AnnaBridge | 189:f392fc9709a3 | 694 | /* CAN clear flag state */ | 
| AnnaBridge | 189:f392fc9709a3 | 695 | void can_flag_clear(uint32_t can_periph, can_flag_enum flag); | 
| AnnaBridge | 189:f392fc9709a3 | 696 | /* CAN get interrupt flag state */ | 
| AnnaBridge | 189:f392fc9709a3 | 697 | FlagStatus can_interrupt_flag_get(uint32_t can_periph, can_interrupt_flag_enum flag); | 
| AnnaBridge | 189:f392fc9709a3 | 698 | /* CAN clear interrupt flag state */ | 
| AnnaBridge | 189:f392fc9709a3 | 699 | void can_interrupt_flag_clear(uint32_t can_periph, can_interrupt_flag_enum flag); | 
| AnnaBridge | 189:f392fc9709a3 | 700 | |
| AnnaBridge | 189:f392fc9709a3 | 701 | #endif /* GD32F30X_CAN_H */ | 


