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targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/system_CMSDK_CM3DS.c@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
Parent:
186:707f6e361f3e 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 167:e84263d55307 1 /*
Anna Bridge 186:707f6e361f3e 2 * Copyright (c) 2009-2018 ARM Limited. All rights reserved.
AnnaBridge 167:e84263d55307 3 *
AnnaBridge 167:e84263d55307 4 * SPDX-License-Identifier: Apache-2.0
AnnaBridge 167:e84263d55307 5 *
AnnaBridge 167:e84263d55307 6 * Licensed under the Apache License, Version 2.0 (the License); you may
AnnaBridge 167:e84263d55307 7 * not use this file except in compliance with the License.
AnnaBridge 167:e84263d55307 8 * You may obtain a copy of the License at
AnnaBridge 167:e84263d55307 9 *
AnnaBridge 167:e84263d55307 10 * http://www.apache.org/licenses/LICENSE-2.0
AnnaBridge 167:e84263d55307 11 *
AnnaBridge 167:e84263d55307 12 * Unless required by applicable law or agreed to in writing, software
AnnaBridge 167:e84263d55307 13 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
AnnaBridge 167:e84263d55307 14 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
AnnaBridge 167:e84263d55307 15 * See the License for the specific language governing permissions and
AnnaBridge 167:e84263d55307 16 * limitations under the License.
Anna Bridge 186:707f6e361f3e 17 */
Anna Bridge 186:707f6e361f3e 18
Anna Bridge 186:707f6e361f3e 19 /*
AnnaBridge 167:e84263d55307 20 * This file is derivative of CMSIS V5.00 system_ARMCM3.c
AnnaBridge 167:e84263d55307 21 */
AnnaBridge 167:e84263d55307 22
AnnaBridge 167:e84263d55307 23 #include "cmsis.h"
AnnaBridge 167:e84263d55307 24
AnnaBridge 167:e84263d55307 25 /*----------------------------------------------------------------------------
AnnaBridge 167:e84263d55307 26 * Define clocks
AnnaBridge 167:e84263d55307 27 *----------------------------------------------------------------------------*/
Anna Bridge 186:707f6e361f3e 28 #define __XTAL (50000000UL) /* Oscillator frequency */
AnnaBridge 167:e84263d55307 29
AnnaBridge 167:e84263d55307 30 #define __SYSTEM_CLOCK (__XTAL / 2)
AnnaBridge 167:e84263d55307 31
AnnaBridge 167:e84263d55307 32 /*----------------------------------------------------------------------------
AnnaBridge 167:e84263d55307 33 * Clock Variable definitions
AnnaBridge 167:e84263d55307 34 *----------------------------------------------------------------------------*/
AnnaBridge 167:e84263d55307 35 /* !< System Clock Frequency (Core Clock) */
AnnaBridge 167:e84263d55307 36 uint32_t SystemCoreClock = __SYSTEM_CLOCK;
AnnaBridge 167:e84263d55307 37
AnnaBridge 167:e84263d55307 38 /* APB System Core Clocks */
AnnaBridge 167:e84263d55307 39 #define SYSTEM_CORE_TIMER0 (1 << 0)
AnnaBridge 167:e84263d55307 40 #define SYSTEM_CORE_TIMER1 (1 << 1)
AnnaBridge 167:e84263d55307 41 #define SYSTEM_CORE_DUALTIMER0 (1 << 2)
AnnaBridge 167:e84263d55307 42 #define SYSTEM_CORE_UART0 (1 << 4)
AnnaBridge 167:e84263d55307 43 #define SYSTEM_CORE_UART1 (1 << 5)
AnnaBridge 167:e84263d55307 44 #define SYSTEM_CORE_I2C0 (1 << 7)
AnnaBridge 167:e84263d55307 45 #define SYSTEM_CORE_WDOG (1 << 8)
AnnaBridge 167:e84263d55307 46 #define SYSTEM_CORE_QSPI (1 << 11)
AnnaBridge 167:e84263d55307 47 #define SYSTEM_CORE_SPI0 (1 << 12)
AnnaBridge 167:e84263d55307 48 #define SYSTEM_CORE_SPI1 (1 << 13)
AnnaBridge 167:e84263d55307 49 #define SYSTEM_CORE_I2C1 (1 << 14)
AnnaBridge 167:e84263d55307 50 #define SYSTEM_CORE_TRNG (1 << 15) /* TRNG can not be a wakeup source */
AnnaBridge 167:e84263d55307 51
AnnaBridge 167:e84263d55307 52 /*----------------------------------------------------------------------------
AnnaBridge 167:e84263d55307 53 * Clock functions
AnnaBridge 167:e84263d55307 54 *----------------------------------------------------------------------------*/
AnnaBridge 167:e84263d55307 55 /**
AnnaBridge 167:e84263d55307 56 * Update SystemCoreClock variable
AnnaBridge 167:e84263d55307 57 *
AnnaBridge 167:e84263d55307 58 * @param none
AnnaBridge 167:e84263d55307 59 * @return none
AnnaBridge 167:e84263d55307 60 *
AnnaBridge 167:e84263d55307 61 * @brief Updates the SystemCoreClock with current core Clock
AnnaBridge 167:e84263d55307 62 * retrieved from cpu registers.
AnnaBridge 167:e84263d55307 63 */
AnnaBridge 167:e84263d55307 64 void SystemCoreClockUpdate (void)
AnnaBridge 167:e84263d55307 65 {
AnnaBridge 167:e84263d55307 66 SystemCoreClock = __SYSTEM_CLOCK;
AnnaBridge 167:e84263d55307 67 }
AnnaBridge 167:e84263d55307 68
AnnaBridge 167:e84263d55307 69 /**
AnnaBridge 167:e84263d55307 70 * Initialize the system
AnnaBridge 167:e84263d55307 71 *
AnnaBridge 167:e84263d55307 72 * @param none
AnnaBridge 167:e84263d55307 73 * @return none
AnnaBridge 167:e84263d55307 74 *
AnnaBridge 167:e84263d55307 75 * @brief Setup the microcontroller system.
AnnaBridge 167:e84263d55307 76 * Initialize the System.
AnnaBridge 167:e84263d55307 77 */
AnnaBridge 167:e84263d55307 78 void SystemInit (void)
AnnaBridge 167:e84263d55307 79 {
AnnaBridge 167:e84263d55307 80
AnnaBridge 167:e84263d55307 81 #ifdef UNALIGNED_SUPPORT_DISABLE
AnnaBridge 167:e84263d55307 82 SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;
AnnaBridge 167:e84263d55307 83 #endif
AnnaBridge 167:e84263d55307 84
AnnaBridge 167:e84263d55307 85 SystemCoreClock = __SYSTEM_CLOCK;
AnnaBridge 167:e84263d55307 86
AnnaBridge 167:e84263d55307 87 // Enable AHB and APB clock
AnnaBridge 167:e84263d55307 88 /* GPIO */
AnnaBridge 167:e84263d55307 89 CMSDK_SYSCON->AHBCLKCFG0SET = 0xF;
AnnaBridge 167:e84263d55307 90 /*
AnnaBridge 167:e84263d55307 91 * Activate clock for: I2C1, SPI1, SPIO, QUADSPI, WDOG,
AnnaBridge 167:e84263d55307 92 * I2C0, UART0, UART1, TIMER0, TIMER1, DUAL TIMER, TRNG
AnnaBridge 167:e84263d55307 93 */
AnnaBridge 167:e84263d55307 94 CMSDK_SYSCON->APBCLKCFG0SET = SYSTEM_CORE_TIMER0
AnnaBridge 167:e84263d55307 95 | SYSTEM_CORE_TIMER1
AnnaBridge 167:e84263d55307 96 | SYSTEM_CORE_DUALTIMER0
AnnaBridge 167:e84263d55307 97 | SYSTEM_CORE_UART0
AnnaBridge 167:e84263d55307 98 | SYSTEM_CORE_UART1
AnnaBridge 167:e84263d55307 99 | SYSTEM_CORE_I2C0
AnnaBridge 167:e84263d55307 100 | SYSTEM_CORE_WDOG
AnnaBridge 167:e84263d55307 101 | SYSTEM_CORE_QSPI
AnnaBridge 167:e84263d55307 102 | SYSTEM_CORE_SPI0
AnnaBridge 167:e84263d55307 103 | SYSTEM_CORE_SPI1
AnnaBridge 167:e84263d55307 104 | SYSTEM_CORE_I2C1
AnnaBridge 167:e84263d55307 105 | SYSTEM_CORE_TRNG;
AnnaBridge 167:e84263d55307 106 }