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cmsis/BUILD/mbed/TARGET_SAMR21G18A/TOOLCHAIN_ARM_STD/ins_sercom2.h@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 189:f392fc9709a3 1 /**
AnnaBridge 189:f392fc9709a3 2 * \file
AnnaBridge 189:f392fc9709a3 3 *
AnnaBridge 189:f392fc9709a3 4 * \brief Instance description for SERCOM2
AnnaBridge 189:f392fc9709a3 5 *
AnnaBridge 189:f392fc9709a3 6 * Copyright (c) 2015 Atmel Corporation. All rights reserved.
AnnaBridge 189:f392fc9709a3 7 *
AnnaBridge 189:f392fc9709a3 8 * \asf_license_start
AnnaBridge 189:f392fc9709a3 9 *
AnnaBridge 189:f392fc9709a3 10 * \page License
AnnaBridge 189:f392fc9709a3 11 *
AnnaBridge 189:f392fc9709a3 12 * Redistribution and use in source and binary forms, with or without
AnnaBridge 189:f392fc9709a3 13 * modification, are permitted provided that the following conditions are met:
AnnaBridge 189:f392fc9709a3 14 *
AnnaBridge 189:f392fc9709a3 15 * 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge 189:f392fc9709a3 16 * this list of conditions and the following disclaimer.
AnnaBridge 189:f392fc9709a3 17 *
AnnaBridge 189:f392fc9709a3 18 * 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge 189:f392fc9709a3 19 * this list of conditions and the following disclaimer in the documentation
AnnaBridge 189:f392fc9709a3 20 * and/or other materials provided with the distribution.
AnnaBridge 189:f392fc9709a3 21 *
AnnaBridge 189:f392fc9709a3 22 * 3. The name of Atmel may not be used to endorse or promote products derived
AnnaBridge 189:f392fc9709a3 23 * from this software without specific prior written permission.
AnnaBridge 189:f392fc9709a3 24 *
AnnaBridge 189:f392fc9709a3 25 * 4. This software may only be redistributed and used in connection with an
AnnaBridge 189:f392fc9709a3 26 * Atmel microcontroller product.
AnnaBridge 189:f392fc9709a3 27 *
AnnaBridge 189:f392fc9709a3 28 * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
AnnaBridge 189:f392fc9709a3 29 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
AnnaBridge 189:f392fc9709a3 30 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
AnnaBridge 189:f392fc9709a3 31 * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
AnnaBridge 189:f392fc9709a3 32 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge 189:f392fc9709a3 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
AnnaBridge 189:f392fc9709a3 34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
AnnaBridge 189:f392fc9709a3 35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
AnnaBridge 189:f392fc9709a3 36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
AnnaBridge 189:f392fc9709a3 37 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
AnnaBridge 189:f392fc9709a3 38 * POSSIBILITY OF SUCH DAMAGE.
AnnaBridge 189:f392fc9709a3 39 *
AnnaBridge 189:f392fc9709a3 40 * \asf_license_stop
AnnaBridge 189:f392fc9709a3 41 *
AnnaBridge 189:f392fc9709a3 42 */
AnnaBridge 189:f392fc9709a3 43
AnnaBridge 189:f392fc9709a3 44 #ifndef _SAMR21_SERCOM2_INSTANCE_
AnnaBridge 189:f392fc9709a3 45 #define _SAMR21_SERCOM2_INSTANCE_
AnnaBridge 189:f392fc9709a3 46
AnnaBridge 189:f392fc9709a3 47 /* ========== Register definition for SERCOM2 peripheral ========== */
AnnaBridge 189:f392fc9709a3 48 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 189:f392fc9709a3 49 #define REG_SERCOM2_I2CM_CTRLA (0x42001000U) /**< \brief (SERCOM2) I2CM Control A */
AnnaBridge 189:f392fc9709a3 50 #define REG_SERCOM2_I2CM_CTRLB (0x42001004U) /**< \brief (SERCOM2) I2CM Control B */
AnnaBridge 189:f392fc9709a3 51 #define REG_SERCOM2_I2CM_BAUD (0x4200100CU) /**< \brief (SERCOM2) I2CM Baud Rate */
AnnaBridge 189:f392fc9709a3 52 #define REG_SERCOM2_I2CM_INTENCLR (0x42001014U) /**< \brief (SERCOM2) I2CM Interrupt Enable Clear */
AnnaBridge 189:f392fc9709a3 53 #define REG_SERCOM2_I2CM_INTENSET (0x42001016U) /**< \brief (SERCOM2) I2CM Interrupt Enable Set */
AnnaBridge 189:f392fc9709a3 54 #define REG_SERCOM2_I2CM_INTFLAG (0x42001018U) /**< \brief (SERCOM2) I2CM Interrupt Flag Status and Clear */
AnnaBridge 189:f392fc9709a3 55 #define REG_SERCOM2_I2CM_STATUS (0x4200101AU) /**< \brief (SERCOM2) I2CM Status */
AnnaBridge 189:f392fc9709a3 56 #define REG_SERCOM2_I2CM_SYNCBUSY (0x4200101CU) /**< \brief (SERCOM2) I2CM Syncbusy */
AnnaBridge 189:f392fc9709a3 57 #define REG_SERCOM2_I2CM_ADDR (0x42001024U) /**< \brief (SERCOM2) I2CM Address */
AnnaBridge 189:f392fc9709a3 58 #define REG_SERCOM2_I2CM_DATA (0x42001028U) /**< \brief (SERCOM2) I2CM Data */
AnnaBridge 189:f392fc9709a3 59 #define REG_SERCOM2_I2CM_DBGCTRL (0x42001030U) /**< \brief (SERCOM2) I2CM Debug Control */
AnnaBridge 189:f392fc9709a3 60 #define REG_SERCOM2_I2CS_CTRLA (0x42001000U) /**< \brief (SERCOM2) I2CS Control A */
AnnaBridge 189:f392fc9709a3 61 #define REG_SERCOM2_I2CS_CTRLB (0x42001004U) /**< \brief (SERCOM2) I2CS Control B */
AnnaBridge 189:f392fc9709a3 62 #define REG_SERCOM2_I2CS_INTENCLR (0x42001014U) /**< \brief (SERCOM2) I2CS Interrupt Enable Clear */
AnnaBridge 189:f392fc9709a3 63 #define REG_SERCOM2_I2CS_INTENSET (0x42001016U) /**< \brief (SERCOM2) I2CS Interrupt Enable Set */
AnnaBridge 189:f392fc9709a3 64 #define REG_SERCOM2_I2CS_INTFLAG (0x42001018U) /**< \brief (SERCOM2) I2CS Interrupt Flag Status and Clear */
AnnaBridge 189:f392fc9709a3 65 #define REG_SERCOM2_I2CS_STATUS (0x4200101AU) /**< \brief (SERCOM2) I2CS Status */
AnnaBridge 189:f392fc9709a3 66 #define REG_SERCOM2_I2CS_SYNCBUSY (0x4200101CU) /**< \brief (SERCOM2) I2CS Syncbusy */
AnnaBridge 189:f392fc9709a3 67 #define REG_SERCOM2_I2CS_ADDR (0x42001024U) /**< \brief (SERCOM2) I2CS Address */
AnnaBridge 189:f392fc9709a3 68 #define REG_SERCOM2_I2CS_DATA (0x42001028U) /**< \brief (SERCOM2) I2CS Data */
AnnaBridge 189:f392fc9709a3 69 #define REG_SERCOM2_SPI_CTRLA (0x42001000U) /**< \brief (SERCOM2) SPI Control A */
AnnaBridge 189:f392fc9709a3 70 #define REG_SERCOM2_SPI_CTRLB (0x42001004U) /**< \brief (SERCOM2) SPI Control B */
AnnaBridge 189:f392fc9709a3 71 #define REG_SERCOM2_SPI_BAUD (0x4200100CU) /**< \brief (SERCOM2) SPI Baud Rate */
AnnaBridge 189:f392fc9709a3 72 #define REG_SERCOM2_SPI_INTENCLR (0x42001014U) /**< \brief (SERCOM2) SPI Interrupt Enable Clear */
AnnaBridge 189:f392fc9709a3 73 #define REG_SERCOM2_SPI_INTENSET (0x42001016U) /**< \brief (SERCOM2) SPI Interrupt Enable Set */
AnnaBridge 189:f392fc9709a3 74 #define REG_SERCOM2_SPI_INTFLAG (0x42001018U) /**< \brief (SERCOM2) SPI Interrupt Flag Status and Clear */
AnnaBridge 189:f392fc9709a3 75 #define REG_SERCOM2_SPI_STATUS (0x4200101AU) /**< \brief (SERCOM2) SPI Status */
AnnaBridge 189:f392fc9709a3 76 #define REG_SERCOM2_SPI_SYNCBUSY (0x4200101CU) /**< \brief (SERCOM2) SPI Syncbusy */
AnnaBridge 189:f392fc9709a3 77 #define REG_SERCOM2_SPI_ADDR (0x42001024U) /**< \brief (SERCOM2) SPI Address */
AnnaBridge 189:f392fc9709a3 78 #define REG_SERCOM2_SPI_DATA (0x42001028U) /**< \brief (SERCOM2) SPI Data */
AnnaBridge 189:f392fc9709a3 79 #define REG_SERCOM2_SPI_DBGCTRL (0x42001030U) /**< \brief (SERCOM2) SPI Debug Control */
AnnaBridge 189:f392fc9709a3 80 #define REG_SERCOM2_USART_CTRLA (0x42001000U) /**< \brief (SERCOM2) USART Control A */
AnnaBridge 189:f392fc9709a3 81 #define REG_SERCOM2_USART_CTRLB (0x42001004U) /**< \brief (SERCOM2) USART Control B */
AnnaBridge 189:f392fc9709a3 82 #define REG_SERCOM2_USART_BAUD (0x4200100CU) /**< \brief (SERCOM2) USART Baud Rate */
AnnaBridge 189:f392fc9709a3 83 #define REG_SERCOM2_USART_RXPL (0x4200100EU) /**< \brief (SERCOM2) USART Receive Pulse Length */
AnnaBridge 189:f392fc9709a3 84 #define REG_SERCOM2_USART_INTENCLR (0x42001014U) /**< \brief (SERCOM2) USART Interrupt Enable Clear */
AnnaBridge 189:f392fc9709a3 85 #define REG_SERCOM2_USART_INTENSET (0x42001016U) /**< \brief (SERCOM2) USART Interrupt Enable Set */
AnnaBridge 189:f392fc9709a3 86 #define REG_SERCOM2_USART_INTFLAG (0x42001018U) /**< \brief (SERCOM2) USART Interrupt Flag Status and Clear */
AnnaBridge 189:f392fc9709a3 87 #define REG_SERCOM2_USART_STATUS (0x4200101AU) /**< \brief (SERCOM2) USART Status */
AnnaBridge 189:f392fc9709a3 88 #define REG_SERCOM2_USART_SYNCBUSY (0x4200101CU) /**< \brief (SERCOM2) USART Syncbusy */
AnnaBridge 189:f392fc9709a3 89 #define REG_SERCOM2_USART_DATA (0x42001028U) /**< \brief (SERCOM2) USART Data */
AnnaBridge 189:f392fc9709a3 90 #define REG_SERCOM2_USART_DBGCTRL (0x42001030U) /**< \brief (SERCOM2) USART Debug Control */
AnnaBridge 189:f392fc9709a3 91 #else
AnnaBridge 189:f392fc9709a3 92 #define REG_SERCOM2_I2CM_CTRLA (*(RwReg *)0x42001000U) /**< \brief (SERCOM2) I2CM Control A */
AnnaBridge 189:f392fc9709a3 93 #define REG_SERCOM2_I2CM_CTRLB (*(RwReg *)0x42001004U) /**< \brief (SERCOM2) I2CM Control B */
AnnaBridge 189:f392fc9709a3 94 #define REG_SERCOM2_I2CM_BAUD (*(RwReg *)0x4200100CU) /**< \brief (SERCOM2) I2CM Baud Rate */
AnnaBridge 189:f392fc9709a3 95 #define REG_SERCOM2_I2CM_INTENCLR (*(RwReg8 *)0x42001014U) /**< \brief (SERCOM2) I2CM Interrupt Enable Clear */
AnnaBridge 189:f392fc9709a3 96 #define REG_SERCOM2_I2CM_INTENSET (*(RwReg8 *)0x42001016U) /**< \brief (SERCOM2) I2CM Interrupt Enable Set */
AnnaBridge 189:f392fc9709a3 97 #define REG_SERCOM2_I2CM_INTFLAG (*(RwReg8 *)0x42001018U) /**< \brief (SERCOM2) I2CM Interrupt Flag Status and Clear */
AnnaBridge 189:f392fc9709a3 98 #define REG_SERCOM2_I2CM_STATUS (*(RwReg16*)0x4200101AU) /**< \brief (SERCOM2) I2CM Status */
AnnaBridge 189:f392fc9709a3 99 #define REG_SERCOM2_I2CM_SYNCBUSY (*(RoReg *)0x4200101CU) /**< \brief (SERCOM2) I2CM Syncbusy */
AnnaBridge 189:f392fc9709a3 100 #define REG_SERCOM2_I2CM_ADDR (*(RwReg *)0x42001024U) /**< \brief (SERCOM2) I2CM Address */
AnnaBridge 189:f392fc9709a3 101 #define REG_SERCOM2_I2CM_DATA (*(RwReg8 *)0x42001028U) /**< \brief (SERCOM2) I2CM Data */
AnnaBridge 189:f392fc9709a3 102 #define REG_SERCOM2_I2CM_DBGCTRL (*(RwReg8 *)0x42001030U) /**< \brief (SERCOM2) I2CM Debug Control */
AnnaBridge 189:f392fc9709a3 103 #define REG_SERCOM2_I2CS_CTRLA (*(RwReg *)0x42001000U) /**< \brief (SERCOM2) I2CS Control A */
AnnaBridge 189:f392fc9709a3 104 #define REG_SERCOM2_I2CS_CTRLB (*(RwReg *)0x42001004U) /**< \brief (SERCOM2) I2CS Control B */
AnnaBridge 189:f392fc9709a3 105 #define REG_SERCOM2_I2CS_INTENCLR (*(RwReg8 *)0x42001014U) /**< \brief (SERCOM2) I2CS Interrupt Enable Clear */
AnnaBridge 189:f392fc9709a3 106 #define REG_SERCOM2_I2CS_INTENSET (*(RwReg8 *)0x42001016U) /**< \brief (SERCOM2) I2CS Interrupt Enable Set */
AnnaBridge 189:f392fc9709a3 107 #define REG_SERCOM2_I2CS_INTFLAG (*(RwReg8 *)0x42001018U) /**< \brief (SERCOM2) I2CS Interrupt Flag Status and Clear */
AnnaBridge 189:f392fc9709a3 108 #define REG_SERCOM2_I2CS_STATUS (*(RwReg16*)0x4200101AU) /**< \brief (SERCOM2) I2CS Status */
AnnaBridge 189:f392fc9709a3 109 #define REG_SERCOM2_I2CS_SYNCBUSY (*(RoReg *)0x4200101CU) /**< \brief (SERCOM2) I2CS Syncbusy */
AnnaBridge 189:f392fc9709a3 110 #define REG_SERCOM2_I2CS_ADDR (*(RwReg *)0x42001024U) /**< \brief (SERCOM2) I2CS Address */
AnnaBridge 189:f392fc9709a3 111 #define REG_SERCOM2_I2CS_DATA (*(RwReg8 *)0x42001028U) /**< \brief (SERCOM2) I2CS Data */
AnnaBridge 189:f392fc9709a3 112 #define REG_SERCOM2_SPI_CTRLA (*(RwReg *)0x42001000U) /**< \brief (SERCOM2) SPI Control A */
AnnaBridge 189:f392fc9709a3 113 #define REG_SERCOM2_SPI_CTRLB (*(RwReg *)0x42001004U) /**< \brief (SERCOM2) SPI Control B */
AnnaBridge 189:f392fc9709a3 114 #define REG_SERCOM2_SPI_BAUD (*(RwReg8 *)0x4200100CU) /**< \brief (SERCOM2) SPI Baud Rate */
AnnaBridge 189:f392fc9709a3 115 #define REG_SERCOM2_SPI_INTENCLR (*(RwReg8 *)0x42001014U) /**< \brief (SERCOM2) SPI Interrupt Enable Clear */
AnnaBridge 189:f392fc9709a3 116 #define REG_SERCOM2_SPI_INTENSET (*(RwReg8 *)0x42001016U) /**< \brief (SERCOM2) SPI Interrupt Enable Set */
AnnaBridge 189:f392fc9709a3 117 #define REG_SERCOM2_SPI_INTFLAG (*(RwReg8 *)0x42001018U) /**< \brief (SERCOM2) SPI Interrupt Flag Status and Clear */
AnnaBridge 189:f392fc9709a3 118 #define REG_SERCOM2_SPI_STATUS (*(RwReg16*)0x4200101AU) /**< \brief (SERCOM2) SPI Status */
AnnaBridge 189:f392fc9709a3 119 #define REG_SERCOM2_SPI_SYNCBUSY (*(RoReg *)0x4200101CU) /**< \brief (SERCOM2) SPI Syncbusy */
AnnaBridge 189:f392fc9709a3 120 #define REG_SERCOM2_SPI_ADDR (*(RwReg *)0x42001024U) /**< \brief (SERCOM2) SPI Address */
AnnaBridge 189:f392fc9709a3 121 #define REG_SERCOM2_SPI_DATA (*(RwReg *)0x42001028U) /**< \brief (SERCOM2) SPI Data */
AnnaBridge 189:f392fc9709a3 122 #define REG_SERCOM2_SPI_DBGCTRL (*(RwReg8 *)0x42001030U) /**< \brief (SERCOM2) SPI Debug Control */
AnnaBridge 189:f392fc9709a3 123 #define REG_SERCOM2_USART_CTRLA (*(RwReg *)0x42001000U) /**< \brief (SERCOM2) USART Control A */
AnnaBridge 189:f392fc9709a3 124 #define REG_SERCOM2_USART_CTRLB (*(RwReg *)0x42001004U) /**< \brief (SERCOM2) USART Control B */
AnnaBridge 189:f392fc9709a3 125 #define REG_SERCOM2_USART_BAUD (*(RwReg16*)0x4200100CU) /**< \brief (SERCOM2) USART Baud Rate */
AnnaBridge 189:f392fc9709a3 126 #define REG_SERCOM2_USART_RXPL (*(RwReg8 *)0x4200100EU) /**< \brief (SERCOM2) USART Receive Pulse Length */
AnnaBridge 189:f392fc9709a3 127 #define REG_SERCOM2_USART_INTENCLR (*(RwReg8 *)0x42001014U) /**< \brief (SERCOM2) USART Interrupt Enable Clear */
AnnaBridge 189:f392fc9709a3 128 #define REG_SERCOM2_USART_INTENSET (*(RwReg8 *)0x42001016U) /**< \brief (SERCOM2) USART Interrupt Enable Set */
AnnaBridge 189:f392fc9709a3 129 #define REG_SERCOM2_USART_INTFLAG (*(RwReg8 *)0x42001018U) /**< \brief (SERCOM2) USART Interrupt Flag Status and Clear */
AnnaBridge 189:f392fc9709a3 130 #define REG_SERCOM2_USART_STATUS (*(RwReg16*)0x4200101AU) /**< \brief (SERCOM2) USART Status */
AnnaBridge 189:f392fc9709a3 131 #define REG_SERCOM2_USART_SYNCBUSY (*(RoReg *)0x4200101CU) /**< \brief (SERCOM2) USART Syncbusy */
AnnaBridge 189:f392fc9709a3 132 #define REG_SERCOM2_USART_DATA (*(RwReg16*)0x42001028U) /**< \brief (SERCOM2) USART Data */
AnnaBridge 189:f392fc9709a3 133 #define REG_SERCOM2_USART_DBGCTRL (*(RwReg8 *)0x42001030U) /**< \brief (SERCOM2) USART Debug Control */
AnnaBridge 189:f392fc9709a3 134 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 189:f392fc9709a3 135
AnnaBridge 189:f392fc9709a3 136 /* ========== Instance parameters for SERCOM2 peripheral ========== */
AnnaBridge 189:f392fc9709a3 137 #define SERCOM2_DMAC_ID_RX 5 // Index of DMA RX trigger
AnnaBridge 189:f392fc9709a3 138 #define SERCOM2_DMAC_ID_TX 6 // Index of DMA TX trigger
AnnaBridge 189:f392fc9709a3 139 #define SERCOM2_GCLK_ID_CORE 22 // Index of Generic Clock for Core
AnnaBridge 189:f392fc9709a3 140 #define SERCOM2_GCLK_ID_SLOW 19 // Index of Generic Clock for SMbus timeout
AnnaBridge 189:f392fc9709a3 141 #define SERCOM2_INT_MSB 6
AnnaBridge 189:f392fc9709a3 142
AnnaBridge 189:f392fc9709a3 143 #endif /* _SAMR21_SERCOM2_INSTANCE_ */