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cmsis/BUILD/mbed/TARGET_NUCLEO_F303RE/TOOLCHAIN_ARM_STD/stm32f3xx_hal_rcc.h@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 189:f392fc9709a3 1 /**
AnnaBridge 189:f392fc9709a3 2 ******************************************************************************
AnnaBridge 189:f392fc9709a3 3 * @file stm32f3xx_hal_rcc.h
AnnaBridge 189:f392fc9709a3 4 * @author MCD Application Team
AnnaBridge 189:f392fc9709a3 5 * @brief Header file of RCC HAL module.
AnnaBridge 189:f392fc9709a3 6 ******************************************************************************
AnnaBridge 189:f392fc9709a3 7 * @attention
AnnaBridge 189:f392fc9709a3 8 *
AnnaBridge 189:f392fc9709a3 9 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
AnnaBridge 189:f392fc9709a3 10 *
AnnaBridge 189:f392fc9709a3 11 * Redistribution and use in source and binary forms, with or without modification,
AnnaBridge 189:f392fc9709a3 12 * are permitted provided that the following conditions are met:
AnnaBridge 189:f392fc9709a3 13 * 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge 189:f392fc9709a3 14 * this list of conditions and the following disclaimer.
AnnaBridge 189:f392fc9709a3 15 * 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge 189:f392fc9709a3 16 * this list of conditions and the following disclaimer in the documentation
AnnaBridge 189:f392fc9709a3 17 * and/or other materials provided with the distribution.
AnnaBridge 189:f392fc9709a3 18 * 3. Neither the name of STMicroelectronics nor the names of its contributors
AnnaBridge 189:f392fc9709a3 19 * may be used to endorse or promote products derived from this software
AnnaBridge 189:f392fc9709a3 20 * without specific prior written permission.
AnnaBridge 189:f392fc9709a3 21 *
AnnaBridge 189:f392fc9709a3 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge 189:f392fc9709a3 23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge 189:f392fc9709a3 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge 189:f392fc9709a3 25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge 189:f392fc9709a3 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge 189:f392fc9709a3 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge 189:f392fc9709a3 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge 189:f392fc9709a3 29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge 189:f392fc9709a3 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge 189:f392fc9709a3 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge 189:f392fc9709a3 32 *
AnnaBridge 189:f392fc9709a3 33 ******************************************************************************
AnnaBridge 189:f392fc9709a3 34 */
AnnaBridge 189:f392fc9709a3 35
AnnaBridge 189:f392fc9709a3 36 /* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge 189:f392fc9709a3 37 #ifndef __STM32F3xx_HAL_RCC_H
AnnaBridge 189:f392fc9709a3 38 #define __STM32F3xx_HAL_RCC_H
AnnaBridge 189:f392fc9709a3 39
AnnaBridge 189:f392fc9709a3 40 #ifdef __cplusplus
AnnaBridge 189:f392fc9709a3 41 extern "C" {
AnnaBridge 189:f392fc9709a3 42 #endif
AnnaBridge 189:f392fc9709a3 43
AnnaBridge 189:f392fc9709a3 44 /* Includes ------------------------------------------------------------------*/
AnnaBridge 189:f392fc9709a3 45 #include "stm32f3xx_hal_def.h"
AnnaBridge 189:f392fc9709a3 46
AnnaBridge 189:f392fc9709a3 47 /** @addtogroup STM32F3xx_HAL_Driver
AnnaBridge 189:f392fc9709a3 48 * @{
AnnaBridge 189:f392fc9709a3 49 */
AnnaBridge 189:f392fc9709a3 50
AnnaBridge 189:f392fc9709a3 51 /** @addtogroup RCC
AnnaBridge 189:f392fc9709a3 52 * @{
AnnaBridge 189:f392fc9709a3 53 */
AnnaBridge 189:f392fc9709a3 54
AnnaBridge 189:f392fc9709a3 55 /** @addtogroup RCC_Private_Constants
AnnaBridge 189:f392fc9709a3 56 * @{
AnnaBridge 189:f392fc9709a3 57 */
AnnaBridge 189:f392fc9709a3 58
AnnaBridge 189:f392fc9709a3 59 /** @defgroup RCC_Timeout RCC Timeout
AnnaBridge 189:f392fc9709a3 60 * @{
AnnaBridge 189:f392fc9709a3 61 */
AnnaBridge 189:f392fc9709a3 62
AnnaBridge 189:f392fc9709a3 63 /* Disable Backup domain write protection state change timeout */
AnnaBridge 189:f392fc9709a3 64 #define RCC_DBP_TIMEOUT_VALUE (100U) /* 100 ms */
AnnaBridge 189:f392fc9709a3 65 /* LSE state change timeout */
AnnaBridge 189:f392fc9709a3 66 #define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT
AnnaBridge 189:f392fc9709a3 67 #define CLOCKSWITCH_TIMEOUT_VALUE (5000U) /* 5 s */
AnnaBridge 189:f392fc9709a3 68 #define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT
AnnaBridge 189:f392fc9709a3 69 #define HSI_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1U) */
AnnaBridge 189:f392fc9709a3 70 #define LSI_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1U) */
AnnaBridge 189:f392fc9709a3 71 #define PLL_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1U) */
AnnaBridge 189:f392fc9709a3 72 /**
AnnaBridge 189:f392fc9709a3 73 * @}
AnnaBridge 189:f392fc9709a3 74 */
AnnaBridge 189:f392fc9709a3 75
AnnaBridge 189:f392fc9709a3 76 /** @defgroup RCC_Register_Offset Register offsets
AnnaBridge 189:f392fc9709a3 77 * @{
AnnaBridge 189:f392fc9709a3 78 */
AnnaBridge 189:f392fc9709a3 79 #define RCC_OFFSET (RCC_BASE - PERIPH_BASE)
AnnaBridge 189:f392fc9709a3 80 #define RCC_CR_OFFSET 0x00
AnnaBridge 189:f392fc9709a3 81 #define RCC_CFGR_OFFSET 0x04
AnnaBridge 189:f392fc9709a3 82 #define RCC_CIR_OFFSET 0x08
AnnaBridge 189:f392fc9709a3 83 #define RCC_BDCR_OFFSET 0x20
AnnaBridge 189:f392fc9709a3 84 #define RCC_CSR_OFFSET 0x24
AnnaBridge 189:f392fc9709a3 85
AnnaBridge 189:f392fc9709a3 86 /**
AnnaBridge 189:f392fc9709a3 87 * @}
AnnaBridge 189:f392fc9709a3 88 */
AnnaBridge 189:f392fc9709a3 89
AnnaBridge 189:f392fc9709a3 90 /** @defgroup RCC_BitAddress_AliasRegion BitAddress AliasRegion
AnnaBridge 189:f392fc9709a3 91 * @brief RCC registers bit address in the alias region
AnnaBridge 189:f392fc9709a3 92 * @{
AnnaBridge 189:f392fc9709a3 93 */
AnnaBridge 189:f392fc9709a3 94 #define RCC_CR_OFFSET_BB (RCC_OFFSET + RCC_CR_OFFSET)
AnnaBridge 189:f392fc9709a3 95 #define RCC_CFGR_OFFSET_BB (RCC_OFFSET + RCC_CFGR_OFFSET)
AnnaBridge 189:f392fc9709a3 96 #define RCC_CIR_OFFSET_BB (RCC_OFFSET + RCC_CIR_OFFSET)
AnnaBridge 189:f392fc9709a3 97 #define RCC_BDCR_OFFSET_BB (RCC_OFFSET + RCC_BDCR_OFFSET)
AnnaBridge 189:f392fc9709a3 98 #define RCC_CSR_OFFSET_BB (RCC_OFFSET + RCC_CSR_OFFSET)
AnnaBridge 189:f392fc9709a3 99
AnnaBridge 189:f392fc9709a3 100 /* --- CR Register ---*/
AnnaBridge 189:f392fc9709a3 101 /* Alias word address of HSION bit */
AnnaBridge 189:f392fc9709a3 102 #define RCC_HSION_BIT_NUMBER POSITION_VAL(RCC_CR_HSION)
AnnaBridge 189:f392fc9709a3 103 #define RCC_CR_HSION_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_HSION_BIT_NUMBER * 4U)))
AnnaBridge 189:f392fc9709a3 104 /* Alias word address of HSEON bit */
AnnaBridge 189:f392fc9709a3 105 #define RCC_HSEON_BIT_NUMBER POSITION_VAL(RCC_CR_HSEON)
AnnaBridge 189:f392fc9709a3 106 #define RCC_CR_HSEON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_HSEON_BIT_NUMBER * 4U)))
AnnaBridge 189:f392fc9709a3 107 /* Alias word address of CSSON bit */
AnnaBridge 189:f392fc9709a3 108 #define RCC_CSSON_BIT_NUMBER POSITION_VAL(RCC_CR_CSSON)
AnnaBridge 189:f392fc9709a3 109 #define RCC_CR_CSSON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_CSSON_BIT_NUMBER * 4U)))
AnnaBridge 189:f392fc9709a3 110 /* Alias word address of PLLON bit */
AnnaBridge 189:f392fc9709a3 111 #define RCC_PLLON_BIT_NUMBER POSITION_VAL(RCC_CR_PLLON)
AnnaBridge 189:f392fc9709a3 112 #define RCC_CR_PLLON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_PLLON_BIT_NUMBER * 4U)))
AnnaBridge 189:f392fc9709a3 113
AnnaBridge 189:f392fc9709a3 114 /* --- CSR Register ---*/
AnnaBridge 189:f392fc9709a3 115 /* Alias word address of LSION bit */
AnnaBridge 189:f392fc9709a3 116 #define RCC_LSION_BIT_NUMBER POSITION_VAL(RCC_CSR_LSION)
AnnaBridge 189:f392fc9709a3 117 #define RCC_CSR_LSION_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32U) + (RCC_LSION_BIT_NUMBER * 4U)))
AnnaBridge 189:f392fc9709a3 118
AnnaBridge 189:f392fc9709a3 119 /* Alias word address of RMVF bit */
AnnaBridge 189:f392fc9709a3 120 #define RCC_RMVF_BIT_NUMBER POSITION_VAL(RCC_CSR_RMVF)
AnnaBridge 189:f392fc9709a3 121 #define RCC_CSR_RMVF_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32U) + (RCC_RMVF_BIT_NUMBER * 4U)))
AnnaBridge 189:f392fc9709a3 122
AnnaBridge 189:f392fc9709a3 123 /* --- BDCR Registers ---*/
AnnaBridge 189:f392fc9709a3 124 /* Alias word address of LSEON bit */
AnnaBridge 189:f392fc9709a3 125 #define RCC_LSEON_BIT_NUMBER POSITION_VAL(RCC_BDCR_LSEON)
AnnaBridge 189:f392fc9709a3 126 #define RCC_BDCR_LSEON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32U) + (RCC_LSEON_BIT_NUMBER * 4U)))
AnnaBridge 189:f392fc9709a3 127
AnnaBridge 189:f392fc9709a3 128 /* Alias word address of LSEON bit */
AnnaBridge 189:f392fc9709a3 129 #define RCC_LSEBYP_BIT_NUMBER POSITION_VAL(RCC_BDCR_LSEBYP)
AnnaBridge 189:f392fc9709a3 130 #define RCC_BDCR_LSEBYP_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32U) + (RCC_LSEBYP_BIT_NUMBER * 4U)))
AnnaBridge 189:f392fc9709a3 131
AnnaBridge 189:f392fc9709a3 132 /* Alias word address of RTCEN bit */
AnnaBridge 189:f392fc9709a3 133 #define RCC_RTCEN_BIT_NUMBER POSITION_VAL(RCC_BDCR_RTCEN)
AnnaBridge 189:f392fc9709a3 134 #define RCC_BDCR_RTCEN_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32U) + (RCC_RTCEN_BIT_NUMBER * 4U)))
AnnaBridge 189:f392fc9709a3 135
AnnaBridge 189:f392fc9709a3 136 /* Alias word address of BDRST bit */
AnnaBridge 189:f392fc9709a3 137 #define RCC_BDRST_BIT_NUMBER POSITION_VAL(RCC_BDCR_BDRST)
AnnaBridge 189:f392fc9709a3 138 #define RCC_BDCR_BDRST_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32U) + (RCC_BDRST_BIT_NUMBER * 4U)))
AnnaBridge 189:f392fc9709a3 139
AnnaBridge 189:f392fc9709a3 140 /**
AnnaBridge 189:f392fc9709a3 141 * @}
AnnaBridge 189:f392fc9709a3 142 */
AnnaBridge 189:f392fc9709a3 143
AnnaBridge 189:f392fc9709a3 144 /* CR register byte 2 (Bits[23:16]) base address */
AnnaBridge 189:f392fc9709a3 145 #define RCC_CR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CR_OFFSET + 0x02U))
AnnaBridge 189:f392fc9709a3 146
AnnaBridge 189:f392fc9709a3 147 /* CIR register byte 1 (Bits[15:8]) base address */
AnnaBridge 189:f392fc9709a3 148 #define RCC_CIR_BYTE1_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x01U))
AnnaBridge 189:f392fc9709a3 149
AnnaBridge 189:f392fc9709a3 150 /* CIR register byte 2 (Bits[23:16]) base address */
AnnaBridge 189:f392fc9709a3 151 #define RCC_CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x02U))
AnnaBridge 189:f392fc9709a3 152
AnnaBridge 189:f392fc9709a3 153 /* Defines used for Flags */
AnnaBridge 189:f392fc9709a3 154 #define CR_REG_INDEX ((uint8_t)1U)
AnnaBridge 189:f392fc9709a3 155 #define BDCR_REG_INDEX ((uint8_t)2U)
AnnaBridge 189:f392fc9709a3 156 #define CSR_REG_INDEX ((uint8_t)3U)
AnnaBridge 189:f392fc9709a3 157 #define CFGR_REG_INDEX ((uint8_t)4U)
AnnaBridge 189:f392fc9709a3 158
AnnaBridge 189:f392fc9709a3 159 #define RCC_FLAG_MASK ((uint8_t)0x1FU)
AnnaBridge 189:f392fc9709a3 160
AnnaBridge 189:f392fc9709a3 161 /**
AnnaBridge 189:f392fc9709a3 162 * @}
AnnaBridge 189:f392fc9709a3 163 */
AnnaBridge 189:f392fc9709a3 164
AnnaBridge 189:f392fc9709a3 165 /** @addtogroup RCC_Private_Macros
AnnaBridge 189:f392fc9709a3 166 * @{
AnnaBridge 189:f392fc9709a3 167 */
AnnaBridge 189:f392fc9709a3 168 #define IS_RCC_PLLSOURCE(__SOURCE__) (((__SOURCE__) == RCC_PLLSOURCE_HSI) || \
AnnaBridge 189:f392fc9709a3 169 ((__SOURCE__) == RCC_PLLSOURCE_HSE))
AnnaBridge 189:f392fc9709a3 170 #define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE) || \
AnnaBridge 189:f392fc9709a3 171 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \
AnnaBridge 189:f392fc9709a3 172 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \
AnnaBridge 189:f392fc9709a3 173 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \
AnnaBridge 189:f392fc9709a3 174 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE))
AnnaBridge 189:f392fc9709a3 175 #define IS_RCC_HSE(__HSE__) (((__HSE__) == RCC_HSE_OFF) || ((__HSE__) == RCC_HSE_ON) || \
AnnaBridge 189:f392fc9709a3 176 ((__HSE__) == RCC_HSE_BYPASS))
AnnaBridge 189:f392fc9709a3 177 #define IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) || ((__LSE__) == RCC_LSE_ON) || \
AnnaBridge 189:f392fc9709a3 178 ((__LSE__) == RCC_LSE_BYPASS))
AnnaBridge 189:f392fc9709a3 179 #define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON))
AnnaBridge 189:f392fc9709a3 180 #define IS_RCC_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 0x1FU)
AnnaBridge 189:f392fc9709a3 181 #define IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) || ((__LSI__) == RCC_LSI_ON))
AnnaBridge 189:f392fc9709a3 182 #define IS_RCC_PLL(__PLL__) (((__PLL__) == RCC_PLL_NONE) || ((__PLL__) == RCC_PLL_OFF) || \
AnnaBridge 189:f392fc9709a3 183 ((__PLL__) == RCC_PLL_ON))
AnnaBridge 189:f392fc9709a3 184 #if defined(RCC_CFGR_PLLSRC_HSI_PREDIV)
AnnaBridge 189:f392fc9709a3 185 #define IS_RCC_PREDIV(__PREDIV__) (((__PREDIV__) == RCC_PREDIV_DIV1) || ((__PREDIV__) == RCC_PREDIV_DIV2) || \
AnnaBridge 189:f392fc9709a3 186 ((__PREDIV__) == RCC_PREDIV_DIV3) || ((__PREDIV__) == RCC_PREDIV_DIV4) || \
AnnaBridge 189:f392fc9709a3 187 ((__PREDIV__) == RCC_PREDIV_DIV5) || ((__PREDIV__) == RCC_PREDIV_DIV6) || \
AnnaBridge 189:f392fc9709a3 188 ((__PREDIV__) == RCC_PREDIV_DIV7) || ((__PREDIV__) == RCC_PREDIV_DIV8) || \
AnnaBridge 189:f392fc9709a3 189 ((__PREDIV__) == RCC_PREDIV_DIV9) || ((__PREDIV__) == RCC_PREDIV_DIV10) || \
AnnaBridge 189:f392fc9709a3 190 ((__PREDIV__) == RCC_PREDIV_DIV11) || ((__PREDIV__) == RCC_PREDIV_DIV12) || \
AnnaBridge 189:f392fc9709a3 191 ((__PREDIV__) == RCC_PREDIV_DIV13) || ((__PREDIV__) == RCC_PREDIV_DIV14) || \
AnnaBridge 189:f392fc9709a3 192 ((__PREDIV__) == RCC_PREDIV_DIV15) || ((__PREDIV__) == RCC_PREDIV_DIV16))
AnnaBridge 189:f392fc9709a3 193 #else
AnnaBridge 189:f392fc9709a3 194 #define IS_RCC_PLL_DIV(__DIV__) (((__DIV__) == RCC_PLL_DIV2) || \
AnnaBridge 189:f392fc9709a3 195 ((__DIV__) == RCC_PLL_DIV3) || ((__DIV__) == RCC_PLL_DIV4))
AnnaBridge 189:f392fc9709a3 196 #endif
AnnaBridge 189:f392fc9709a3 197 #if defined(RCC_CFGR_PLLSRC_HSI_DIV2)
AnnaBridge 189:f392fc9709a3 198 #define IS_RCC_HSE_PREDIV(DIV) (((DIV) == RCC_HSE_PREDIV_DIV1) || ((DIV) == RCC_HSE_PREDIV_DIV2) || \
AnnaBridge 189:f392fc9709a3 199 ((DIV) == RCC_HSE_PREDIV_DIV3) || ((DIV) == RCC_HSE_PREDIV_DIV4) || \
AnnaBridge 189:f392fc9709a3 200 ((DIV) == RCC_HSE_PREDIV_DIV5) || ((DIV) == RCC_HSE_PREDIV_DIV6) || \
AnnaBridge 189:f392fc9709a3 201 ((DIV) == RCC_HSE_PREDIV_DIV7) || ((DIV) == RCC_HSE_PREDIV_DIV8) || \
AnnaBridge 189:f392fc9709a3 202 ((DIV) == RCC_HSE_PREDIV_DIV9) || ((DIV) == RCC_HSE_PREDIV_DIV10) || \
AnnaBridge 189:f392fc9709a3 203 ((DIV) == RCC_HSE_PREDIV_DIV11) || ((DIV) == RCC_HSE_PREDIV_DIV12) || \
AnnaBridge 189:f392fc9709a3 204 ((DIV) == RCC_HSE_PREDIV_DIV13) || ((DIV) == RCC_HSE_PREDIV_DIV14) || \
AnnaBridge 189:f392fc9709a3 205 ((DIV) == RCC_HSE_PREDIV_DIV15) || ((DIV) == RCC_HSE_PREDIV_DIV16))
AnnaBridge 189:f392fc9709a3 206 #endif /* RCC_CFGR_PLLSRC_HSI_DIV2 */
AnnaBridge 189:f392fc9709a3 207
AnnaBridge 189:f392fc9709a3 208 #define IS_RCC_PLL_MUL(__MUL__) (((__MUL__) == RCC_PLL_MUL2) || ((__MUL__) == RCC_PLL_MUL3) || \
AnnaBridge 189:f392fc9709a3 209 ((__MUL__) == RCC_PLL_MUL4) || ((__MUL__) == RCC_PLL_MUL5) || \
AnnaBridge 189:f392fc9709a3 210 ((__MUL__) == RCC_PLL_MUL6) || ((__MUL__) == RCC_PLL_MUL7) || \
AnnaBridge 189:f392fc9709a3 211 ((__MUL__) == RCC_PLL_MUL8) || ((__MUL__) == RCC_PLL_MUL9) || \
AnnaBridge 189:f392fc9709a3 212 ((__MUL__) == RCC_PLL_MUL10) || ((__MUL__) == RCC_PLL_MUL11) || \
AnnaBridge 189:f392fc9709a3 213 ((__MUL__) == RCC_PLL_MUL12) || ((__MUL__) == RCC_PLL_MUL13) || \
AnnaBridge 189:f392fc9709a3 214 ((__MUL__) == RCC_PLL_MUL14) || ((__MUL__) == RCC_PLL_MUL15) || \
AnnaBridge 189:f392fc9709a3 215 ((__MUL__) == RCC_PLL_MUL16))
AnnaBridge 189:f392fc9709a3 216 #define IS_RCC_CLOCKTYPE(CLK) ((((CLK) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) || \
AnnaBridge 189:f392fc9709a3 217 (((CLK) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) || \
AnnaBridge 189:f392fc9709a3 218 (((CLK) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) || \
AnnaBridge 189:f392fc9709a3 219 (((CLK) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2))
AnnaBridge 189:f392fc9709a3 220 #define IS_RCC_SYSCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_HSI) || \
AnnaBridge 189:f392fc9709a3 221 ((__SOURCE__) == RCC_SYSCLKSOURCE_HSE) || \
AnnaBridge 189:f392fc9709a3 222 ((__SOURCE__) == RCC_SYSCLKSOURCE_PLLCLK))
AnnaBridge 189:f392fc9709a3 223 #define IS_RCC_SYSCLKSOURCE_STATUS(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_HSI) || \
AnnaBridge 189:f392fc9709a3 224 ((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_HSE) || \
AnnaBridge 189:f392fc9709a3 225 ((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_PLLCLK))
AnnaBridge 189:f392fc9709a3 226 #define IS_RCC_HCLK(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1) || ((__HCLK__) == RCC_SYSCLK_DIV2) || \
AnnaBridge 189:f392fc9709a3 227 ((__HCLK__) == RCC_SYSCLK_DIV4) || ((__HCLK__) == RCC_SYSCLK_DIV8) || \
AnnaBridge 189:f392fc9709a3 228 ((__HCLK__) == RCC_SYSCLK_DIV16) || ((__HCLK__) == RCC_SYSCLK_DIV64) || \
AnnaBridge 189:f392fc9709a3 229 ((__HCLK__) == RCC_SYSCLK_DIV128) || ((__HCLK__) == RCC_SYSCLK_DIV256) || \
AnnaBridge 189:f392fc9709a3 230 ((__HCLK__) == RCC_SYSCLK_DIV512))
AnnaBridge 189:f392fc9709a3 231 #define IS_RCC_PCLK(__PCLK__) (((__PCLK__) == RCC_HCLK_DIV1) || ((__PCLK__) == RCC_HCLK_DIV2) || \
AnnaBridge 189:f392fc9709a3 232 ((__PCLK__) == RCC_HCLK_DIV4) || ((__PCLK__) == RCC_HCLK_DIV8) || \
AnnaBridge 189:f392fc9709a3 233 ((__PCLK__) == RCC_HCLK_DIV16))
AnnaBridge 189:f392fc9709a3 234 #define IS_RCC_MCO(__MCO__) ((__MCO__) == RCC_MCO)
AnnaBridge 189:f392fc9709a3 235 #define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_NO_CLK) || \
AnnaBridge 189:f392fc9709a3 236 ((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) || \
AnnaBridge 189:f392fc9709a3 237 ((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) || \
AnnaBridge 189:f392fc9709a3 238 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV32))
AnnaBridge 189:f392fc9709a3 239 #if defined(RCC_CFGR3_USART2SW)
AnnaBridge 189:f392fc9709a3 240 #define IS_RCC_USART2CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_USART2CLKSOURCE_PCLK1) || \
AnnaBridge 189:f392fc9709a3 241 ((__SOURCE__) == RCC_USART2CLKSOURCE_SYSCLK) || \
AnnaBridge 189:f392fc9709a3 242 ((__SOURCE__) == RCC_USART2CLKSOURCE_LSE) || \
AnnaBridge 189:f392fc9709a3 243 ((__SOURCE__) == RCC_USART2CLKSOURCE_HSI))
AnnaBridge 189:f392fc9709a3 244 #endif /* RCC_CFGR3_USART2SW */
AnnaBridge 189:f392fc9709a3 245 #if defined(RCC_CFGR3_USART3SW)
AnnaBridge 189:f392fc9709a3 246 #define IS_RCC_USART3CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_USART3CLKSOURCE_PCLK1) || \
AnnaBridge 189:f392fc9709a3 247 ((__SOURCE__) == RCC_USART3CLKSOURCE_SYSCLK) || \
AnnaBridge 189:f392fc9709a3 248 ((__SOURCE__) == RCC_USART3CLKSOURCE_LSE) || \
AnnaBridge 189:f392fc9709a3 249 ((__SOURCE__) == RCC_USART3CLKSOURCE_HSI))
AnnaBridge 189:f392fc9709a3 250 #endif /* RCC_CFGR3_USART3SW */
AnnaBridge 189:f392fc9709a3 251 #define IS_RCC_I2C1CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_I2C1CLKSOURCE_HSI) || \
AnnaBridge 189:f392fc9709a3 252 ((__SOURCE__) == RCC_I2C1CLKSOURCE_SYSCLK))
AnnaBridge 189:f392fc9709a3 253
AnnaBridge 189:f392fc9709a3 254 /**
AnnaBridge 189:f392fc9709a3 255 * @}
AnnaBridge 189:f392fc9709a3 256 */
AnnaBridge 189:f392fc9709a3 257
AnnaBridge 189:f392fc9709a3 258 /* Exported types ------------------------------------------------------------*/
AnnaBridge 189:f392fc9709a3 259
AnnaBridge 189:f392fc9709a3 260 /** @defgroup RCC_Exported_Types RCC Exported Types
AnnaBridge 189:f392fc9709a3 261 * @{
AnnaBridge 189:f392fc9709a3 262 */
AnnaBridge 189:f392fc9709a3 263
AnnaBridge 189:f392fc9709a3 264 /**
AnnaBridge 189:f392fc9709a3 265 * @brief RCC PLL configuration structure definition
AnnaBridge 189:f392fc9709a3 266 */
AnnaBridge 189:f392fc9709a3 267 typedef struct
AnnaBridge 189:f392fc9709a3 268 {
AnnaBridge 189:f392fc9709a3 269 uint32_t PLLState; /*!< PLLState: The new state of the PLL.
AnnaBridge 189:f392fc9709a3 270 This parameter can be a value of @ref RCC_PLL_Config */
AnnaBridge 189:f392fc9709a3 271
AnnaBridge 189:f392fc9709a3 272 uint32_t PLLSource; /*!< PLLSource: PLL entry clock source.
AnnaBridge 189:f392fc9709a3 273 This parameter must be a value of @ref RCC_PLL_Clock_Source */
AnnaBridge 189:f392fc9709a3 274
AnnaBridge 189:f392fc9709a3 275 uint32_t PLLMUL; /*!< PLLMUL: Multiplication factor for PLL VCO input clock
AnnaBridge 189:f392fc9709a3 276 This parameter must be a value of @ref RCC_PLL_Multiplication_Factor*/
AnnaBridge 189:f392fc9709a3 277
AnnaBridge 189:f392fc9709a3 278 #if defined(RCC_CFGR_PLLSRC_HSI_PREDIV)
AnnaBridge 189:f392fc9709a3 279 uint32_t PREDIV; /*!< PREDIV: Predivision factor for PLL VCO input clock
AnnaBridge 189:f392fc9709a3 280 This parameter must be a value of @ref RCC_PLL_Prediv_Factor */
AnnaBridge 189:f392fc9709a3 281
AnnaBridge 189:f392fc9709a3 282 #endif
AnnaBridge 189:f392fc9709a3 283 } RCC_PLLInitTypeDef;
AnnaBridge 189:f392fc9709a3 284
AnnaBridge 189:f392fc9709a3 285 /**
AnnaBridge 189:f392fc9709a3 286 * @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition
AnnaBridge 189:f392fc9709a3 287 */
AnnaBridge 189:f392fc9709a3 288 typedef struct
AnnaBridge 189:f392fc9709a3 289 {
AnnaBridge 189:f392fc9709a3 290 uint32_t OscillatorType; /*!< The oscillators to be configured.
AnnaBridge 189:f392fc9709a3 291 This parameter can be a value of @ref RCC_Oscillator_Type */
AnnaBridge 189:f392fc9709a3 292
AnnaBridge 189:f392fc9709a3 293 uint32_t HSEState; /*!< The new state of the HSE.
AnnaBridge 189:f392fc9709a3 294 This parameter can be a value of @ref RCC_HSE_Config */
AnnaBridge 189:f392fc9709a3 295
AnnaBridge 189:f392fc9709a3 296 #if defined(RCC_CFGR_PLLSRC_HSI_DIV2)
AnnaBridge 189:f392fc9709a3 297 uint32_t HSEPredivValue; /*!< The HSE predivision factor value.
AnnaBridge 189:f392fc9709a3 298 This parameter can be a value of @ref RCC_PLL_HSE_Prediv_Factor */
AnnaBridge 189:f392fc9709a3 299
AnnaBridge 189:f392fc9709a3 300 #endif /* RCC_CFGR_PLLSRC_HSI_DIV2 */
AnnaBridge 189:f392fc9709a3 301 uint32_t LSEState; /*!< The new state of the LSE.
AnnaBridge 189:f392fc9709a3 302 This parameter can be a value of @ref RCC_LSE_Config */
AnnaBridge 189:f392fc9709a3 303
AnnaBridge 189:f392fc9709a3 304 uint32_t HSIState; /*!< The new state of the HSI.
AnnaBridge 189:f392fc9709a3 305 This parameter can be a value of @ref RCC_HSI_Config */
AnnaBridge 189:f392fc9709a3 306
AnnaBridge 189:f392fc9709a3 307 uint32_t HSICalibrationValue; /*!< The HSI calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT).
AnnaBridge 189:f392fc9709a3 308 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1FU */
AnnaBridge 189:f392fc9709a3 309
AnnaBridge 189:f392fc9709a3 310 uint32_t LSIState; /*!< The new state of the LSI.
AnnaBridge 189:f392fc9709a3 311 This parameter can be a value of @ref RCC_LSI_Config */
AnnaBridge 189:f392fc9709a3 312
AnnaBridge 189:f392fc9709a3 313 RCC_PLLInitTypeDef PLL; /*!< PLL structure parameters */
AnnaBridge 189:f392fc9709a3 314
AnnaBridge 189:f392fc9709a3 315 } RCC_OscInitTypeDef;
AnnaBridge 189:f392fc9709a3 316
AnnaBridge 189:f392fc9709a3 317 /**
AnnaBridge 189:f392fc9709a3 318 * @brief RCC System, AHB and APB busses clock configuration structure definition
AnnaBridge 189:f392fc9709a3 319 */
AnnaBridge 189:f392fc9709a3 320 typedef struct
AnnaBridge 189:f392fc9709a3 321 {
AnnaBridge 189:f392fc9709a3 322 uint32_t ClockType; /*!< The clock to be configured.
AnnaBridge 189:f392fc9709a3 323 This parameter can be a value of @ref RCC_System_Clock_Type */
AnnaBridge 189:f392fc9709a3 324
AnnaBridge 189:f392fc9709a3 325 uint32_t SYSCLKSource; /*!< The clock source (SYSCLKS) used as system clock.
AnnaBridge 189:f392fc9709a3 326 This parameter can be a value of @ref RCC_System_Clock_Source */
AnnaBridge 189:f392fc9709a3 327
AnnaBridge 189:f392fc9709a3 328 uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
AnnaBridge 189:f392fc9709a3 329 This parameter can be a value of @ref RCC_AHB_Clock_Source */
AnnaBridge 189:f392fc9709a3 330
AnnaBridge 189:f392fc9709a3 331 uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
AnnaBridge 189:f392fc9709a3 332 This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
AnnaBridge 189:f392fc9709a3 333
AnnaBridge 189:f392fc9709a3 334 uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
AnnaBridge 189:f392fc9709a3 335 This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
AnnaBridge 189:f392fc9709a3 336 } RCC_ClkInitTypeDef;
AnnaBridge 189:f392fc9709a3 337
AnnaBridge 189:f392fc9709a3 338 /**
AnnaBridge 189:f392fc9709a3 339 * @}
AnnaBridge 189:f392fc9709a3 340 */
AnnaBridge 189:f392fc9709a3 341
AnnaBridge 189:f392fc9709a3 342 /* Exported constants --------------------------------------------------------*/
AnnaBridge 189:f392fc9709a3 343 /** @defgroup RCC_Exported_Constants RCC Exported Constants
AnnaBridge 189:f392fc9709a3 344 * @{
AnnaBridge 189:f392fc9709a3 345 */
AnnaBridge 189:f392fc9709a3 346
AnnaBridge 189:f392fc9709a3 347 /** @defgroup RCC_PLL_Clock_Source PLL Clock Source
AnnaBridge 189:f392fc9709a3 348 * @{
AnnaBridge 189:f392fc9709a3 349 */
AnnaBridge 189:f392fc9709a3 350
AnnaBridge 189:f392fc9709a3 351 #if defined(RCC_CFGR_PLLSRC_HSI_PREDIV)
AnnaBridge 189:f392fc9709a3 352 #define RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI_PREDIV /*!< HSI clock selected as PLL entry clock source */
AnnaBridge 189:f392fc9709a3 353 #endif /* RCC_CFGR_PLLSRC_HSI_PREDIV */
AnnaBridge 189:f392fc9709a3 354 #if defined(RCC_CFGR_PLLSRC_HSI_DIV2)
AnnaBridge 189:f392fc9709a3 355 #define RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI_DIV2 /*!< HSI clock divided by 2 selected as PLL entry clock source */
AnnaBridge 189:f392fc9709a3 356 #endif /* RCC_CFGR_PLLSRC_HSI_DIV2 */
AnnaBridge 189:f392fc9709a3 357 #define RCC_PLLSOURCE_HSE RCC_CFGR_PLLSRC_HSE_PREDIV /*!< HSE clock selected as PLL entry clock source */
AnnaBridge 189:f392fc9709a3 358
AnnaBridge 189:f392fc9709a3 359 /**
AnnaBridge 189:f392fc9709a3 360 * @}
AnnaBridge 189:f392fc9709a3 361 */
AnnaBridge 189:f392fc9709a3 362
AnnaBridge 189:f392fc9709a3 363 /** @defgroup RCC_Oscillator_Type Oscillator Type
AnnaBridge 189:f392fc9709a3 364 * @{
AnnaBridge 189:f392fc9709a3 365 */
AnnaBridge 189:f392fc9709a3 366 #define RCC_OSCILLATORTYPE_NONE (0x00000000U)
AnnaBridge 189:f392fc9709a3 367 #define RCC_OSCILLATORTYPE_HSE (0x00000001U)
AnnaBridge 189:f392fc9709a3 368 #define RCC_OSCILLATORTYPE_HSI (0x00000002U)
AnnaBridge 189:f392fc9709a3 369 #define RCC_OSCILLATORTYPE_LSE (0x00000004U)
AnnaBridge 189:f392fc9709a3 370 #define RCC_OSCILLATORTYPE_LSI (0x00000008U)
AnnaBridge 189:f392fc9709a3 371 /**
AnnaBridge 189:f392fc9709a3 372 * @}
AnnaBridge 189:f392fc9709a3 373 */
AnnaBridge 189:f392fc9709a3 374
AnnaBridge 189:f392fc9709a3 375 /** @defgroup RCC_HSE_Config HSE Config
AnnaBridge 189:f392fc9709a3 376 * @{
AnnaBridge 189:f392fc9709a3 377 */
AnnaBridge 189:f392fc9709a3 378 #define RCC_HSE_OFF (0x00000000U) /*!< HSE clock deactivation */
AnnaBridge 189:f392fc9709a3 379 #define RCC_HSE_ON RCC_CR_HSEON /*!< HSE clock activation */
AnnaBridge 189:f392fc9709a3 380 #define RCC_HSE_BYPASS ((uint32_t)(RCC_CR_HSEBYP | RCC_CR_HSEON)) /*!< External clock source for HSE clock */
AnnaBridge 189:f392fc9709a3 381 /**
AnnaBridge 189:f392fc9709a3 382 * @}
AnnaBridge 189:f392fc9709a3 383 */
AnnaBridge 189:f392fc9709a3 384
AnnaBridge 189:f392fc9709a3 385 /** @defgroup RCC_LSE_Config LSE Config
AnnaBridge 189:f392fc9709a3 386 * @{
AnnaBridge 189:f392fc9709a3 387 */
AnnaBridge 189:f392fc9709a3 388 #define RCC_LSE_OFF (0x00000000U) /*!< LSE clock deactivation */
AnnaBridge 189:f392fc9709a3 389 #define RCC_LSE_ON RCC_BDCR_LSEON /*!< LSE clock activation */
AnnaBridge 189:f392fc9709a3 390 #define RCC_LSE_BYPASS ((uint32_t)(RCC_BDCR_LSEBYP | RCC_BDCR_LSEON)) /*!< External clock source for LSE clock */
AnnaBridge 189:f392fc9709a3 391
AnnaBridge 189:f392fc9709a3 392 /**
AnnaBridge 189:f392fc9709a3 393 * @}
AnnaBridge 189:f392fc9709a3 394 */
AnnaBridge 189:f392fc9709a3 395
AnnaBridge 189:f392fc9709a3 396 /** @defgroup RCC_HSI_Config HSI Config
AnnaBridge 189:f392fc9709a3 397 * @{
AnnaBridge 189:f392fc9709a3 398 */
AnnaBridge 189:f392fc9709a3 399 #define RCC_HSI_OFF (0x00000000U) /*!< HSI clock deactivation */
AnnaBridge 189:f392fc9709a3 400 #define RCC_HSI_ON RCC_CR_HSION /*!< HSI clock activation */
AnnaBridge 189:f392fc9709a3 401
AnnaBridge 189:f392fc9709a3 402 #define RCC_HSICALIBRATION_DEFAULT (0x10U) /* Default HSI calibration trimming value */
AnnaBridge 189:f392fc9709a3 403
AnnaBridge 189:f392fc9709a3 404 /**
AnnaBridge 189:f392fc9709a3 405 * @}
AnnaBridge 189:f392fc9709a3 406 */
AnnaBridge 189:f392fc9709a3 407
AnnaBridge 189:f392fc9709a3 408 /** @defgroup RCC_LSI_Config LSI Config
AnnaBridge 189:f392fc9709a3 409 * @{
AnnaBridge 189:f392fc9709a3 410 */
AnnaBridge 189:f392fc9709a3 411 #define RCC_LSI_OFF (0x00000000U) /*!< LSI clock deactivation */
AnnaBridge 189:f392fc9709a3 412 #define RCC_LSI_ON RCC_CSR_LSION /*!< LSI clock activation */
AnnaBridge 189:f392fc9709a3 413
AnnaBridge 189:f392fc9709a3 414 /**
AnnaBridge 189:f392fc9709a3 415 * @}
AnnaBridge 189:f392fc9709a3 416 */
AnnaBridge 189:f392fc9709a3 417
AnnaBridge 189:f392fc9709a3 418 /** @defgroup RCC_PLL_Config PLL Config
AnnaBridge 189:f392fc9709a3 419 * @{
AnnaBridge 189:f392fc9709a3 420 */
AnnaBridge 189:f392fc9709a3 421 #define RCC_PLL_NONE (0x00000000U) /*!< PLL is not configured */
AnnaBridge 189:f392fc9709a3 422 #define RCC_PLL_OFF (0x00000001U) /*!< PLL deactivation */
AnnaBridge 189:f392fc9709a3 423 #define RCC_PLL_ON (0x00000002U) /*!< PLL activation */
AnnaBridge 189:f392fc9709a3 424
AnnaBridge 189:f392fc9709a3 425 /**
AnnaBridge 189:f392fc9709a3 426 * @}
AnnaBridge 189:f392fc9709a3 427 */
AnnaBridge 189:f392fc9709a3 428
AnnaBridge 189:f392fc9709a3 429 /** @defgroup RCC_System_Clock_Type System Clock Type
AnnaBridge 189:f392fc9709a3 430 * @{
AnnaBridge 189:f392fc9709a3 431 */
AnnaBridge 189:f392fc9709a3 432 #define RCC_CLOCKTYPE_SYSCLK (0x00000001U) /*!< SYSCLK to configure */
AnnaBridge 189:f392fc9709a3 433 #define RCC_CLOCKTYPE_HCLK (0x00000002U) /*!< HCLK to configure */
AnnaBridge 189:f392fc9709a3 434 #define RCC_CLOCKTYPE_PCLK1 (0x00000004U) /*!< PCLK1 to configure */
AnnaBridge 189:f392fc9709a3 435 #define RCC_CLOCKTYPE_PCLK2 (0x00000008U) /*!< PCLK2 to configure */
AnnaBridge 189:f392fc9709a3 436
AnnaBridge 189:f392fc9709a3 437 /**
AnnaBridge 189:f392fc9709a3 438 * @}
AnnaBridge 189:f392fc9709a3 439 */
AnnaBridge 189:f392fc9709a3 440
AnnaBridge 189:f392fc9709a3 441 /** @defgroup RCC_System_Clock_Source System Clock Source
AnnaBridge 189:f392fc9709a3 442 * @{
AnnaBridge 189:f392fc9709a3 443 */
AnnaBridge 189:f392fc9709a3 444 #define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI /*!< HSI selected as system clock */
AnnaBridge 189:f392fc9709a3 445 #define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE /*!< HSE selected as system clock */
AnnaBridge 189:f392fc9709a3 446 #define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL /*!< PLL selected as system clock */
AnnaBridge 189:f392fc9709a3 447
AnnaBridge 189:f392fc9709a3 448 /**
AnnaBridge 189:f392fc9709a3 449 * @}
AnnaBridge 189:f392fc9709a3 450 */
AnnaBridge 189:f392fc9709a3 451
AnnaBridge 189:f392fc9709a3 452 /** @defgroup RCC_System_Clock_Source_Status System Clock Source Status
AnnaBridge 189:f392fc9709a3 453 * @{
AnnaBridge 189:f392fc9709a3 454 */
AnnaBridge 189:f392fc9709a3 455 #define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */
AnnaBridge 189:f392fc9709a3 456 #define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */
AnnaBridge 189:f392fc9709a3 457 #define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL /*!< PLL used as system clock */
AnnaBridge 189:f392fc9709a3 458
AnnaBridge 189:f392fc9709a3 459 /**
AnnaBridge 189:f392fc9709a3 460 * @}
AnnaBridge 189:f392fc9709a3 461 */
AnnaBridge 189:f392fc9709a3 462
AnnaBridge 189:f392fc9709a3 463 /** @defgroup RCC_AHB_Clock_Source AHB Clock Source
AnnaBridge 189:f392fc9709a3 464 * @{
AnnaBridge 189:f392fc9709a3 465 */
AnnaBridge 189:f392fc9709a3 466 #define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1 /*!< SYSCLK not divided */
AnnaBridge 189:f392fc9709a3 467 #define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2 /*!< SYSCLK divided by 2 */
AnnaBridge 189:f392fc9709a3 468 #define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4 /*!< SYSCLK divided by 4 */
AnnaBridge 189:f392fc9709a3 469 #define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8 /*!< SYSCLK divided by 8 */
AnnaBridge 189:f392fc9709a3 470 #define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16 /*!< SYSCLK divided by 16 */
AnnaBridge 189:f392fc9709a3 471 #define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64 /*!< SYSCLK divided by 64 */
AnnaBridge 189:f392fc9709a3 472 #define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128 /*!< SYSCLK divided by 128 */
AnnaBridge 189:f392fc9709a3 473 #define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256 /*!< SYSCLK divided by 256 */
AnnaBridge 189:f392fc9709a3 474 #define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512 /*!< SYSCLK divided by 512 */
AnnaBridge 189:f392fc9709a3 475
AnnaBridge 189:f392fc9709a3 476 /**
AnnaBridge 189:f392fc9709a3 477 * @}
AnnaBridge 189:f392fc9709a3 478 */
AnnaBridge 189:f392fc9709a3 479
AnnaBridge 189:f392fc9709a3 480 /** @defgroup RCC_APB1_APB2_Clock_Source APB1 APB2 Clock Source
AnnaBridge 189:f392fc9709a3 481 * @{
AnnaBridge 189:f392fc9709a3 482 */
AnnaBridge 189:f392fc9709a3 483 #define RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1 /*!< HCLK not divided */
AnnaBridge 189:f392fc9709a3 484 #define RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2 /*!< HCLK divided by 2 */
AnnaBridge 189:f392fc9709a3 485 #define RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4 /*!< HCLK divided by 4 */
AnnaBridge 189:f392fc9709a3 486 #define RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8 /*!< HCLK divided by 8 */
AnnaBridge 189:f392fc9709a3 487 #define RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16 /*!< HCLK divided by 16 */
AnnaBridge 189:f392fc9709a3 488
AnnaBridge 189:f392fc9709a3 489 /**
AnnaBridge 189:f392fc9709a3 490 * @}
AnnaBridge 189:f392fc9709a3 491 */
AnnaBridge 189:f392fc9709a3 492
AnnaBridge 189:f392fc9709a3 493 /** @defgroup RCC_RTC_Clock_Source RTC Clock Source
AnnaBridge 189:f392fc9709a3 494 * @{
AnnaBridge 189:f392fc9709a3 495 */
AnnaBridge 189:f392fc9709a3 496 #define RCC_RTCCLKSOURCE_NO_CLK RCC_BDCR_RTCSEL_NOCLOCK /*!< No clock */
AnnaBridge 189:f392fc9709a3 497 #define RCC_RTCCLKSOURCE_LSE RCC_BDCR_RTCSEL_LSE /*!< LSE oscillator clock used as RTC clock */
AnnaBridge 189:f392fc9709a3 498 #define RCC_RTCCLKSOURCE_LSI RCC_BDCR_RTCSEL_LSI /*!< LSI oscillator clock used as RTC clock */
AnnaBridge 189:f392fc9709a3 499 #define RCC_RTCCLKSOURCE_HSE_DIV32 RCC_BDCR_RTCSEL_HSE /*!< HSE oscillator clock divided by 32 used as RTC clock */
AnnaBridge 189:f392fc9709a3 500 /**
AnnaBridge 189:f392fc9709a3 501 * @}
AnnaBridge 189:f392fc9709a3 502 */
AnnaBridge 189:f392fc9709a3 503
AnnaBridge 189:f392fc9709a3 504 /** @defgroup RCC_PLL_Multiplication_Factor RCC PLL Multiplication Factor
AnnaBridge 189:f392fc9709a3 505 * @{
AnnaBridge 189:f392fc9709a3 506 */
AnnaBridge 189:f392fc9709a3 507 #define RCC_PLL_MUL2 RCC_CFGR_PLLMUL2
AnnaBridge 189:f392fc9709a3 508 #define RCC_PLL_MUL3 RCC_CFGR_PLLMUL3
AnnaBridge 189:f392fc9709a3 509 #define RCC_PLL_MUL4 RCC_CFGR_PLLMUL4
AnnaBridge 189:f392fc9709a3 510 #define RCC_PLL_MUL5 RCC_CFGR_PLLMUL5
AnnaBridge 189:f392fc9709a3 511 #define RCC_PLL_MUL6 RCC_CFGR_PLLMUL6
AnnaBridge 189:f392fc9709a3 512 #define RCC_PLL_MUL7 RCC_CFGR_PLLMUL7
AnnaBridge 189:f392fc9709a3 513 #define RCC_PLL_MUL8 RCC_CFGR_PLLMUL8
AnnaBridge 189:f392fc9709a3 514 #define RCC_PLL_MUL9 RCC_CFGR_PLLMUL9
AnnaBridge 189:f392fc9709a3 515 #define RCC_PLL_MUL10 RCC_CFGR_PLLMUL10
AnnaBridge 189:f392fc9709a3 516 #define RCC_PLL_MUL11 RCC_CFGR_PLLMUL11
AnnaBridge 189:f392fc9709a3 517 #define RCC_PLL_MUL12 RCC_CFGR_PLLMUL12
AnnaBridge 189:f392fc9709a3 518 #define RCC_PLL_MUL13 RCC_CFGR_PLLMUL13
AnnaBridge 189:f392fc9709a3 519 #define RCC_PLL_MUL14 RCC_CFGR_PLLMUL14
AnnaBridge 189:f392fc9709a3 520 #define RCC_PLL_MUL15 RCC_CFGR_PLLMUL15
AnnaBridge 189:f392fc9709a3 521 #define RCC_PLL_MUL16 RCC_CFGR_PLLMUL16
AnnaBridge 189:f392fc9709a3 522
AnnaBridge 189:f392fc9709a3 523 /**
AnnaBridge 189:f392fc9709a3 524 * @}
AnnaBridge 189:f392fc9709a3 525 */
AnnaBridge 189:f392fc9709a3 526
AnnaBridge 189:f392fc9709a3 527 #if defined(RCC_CFGR_PLLSRC_HSI_PREDIV)
AnnaBridge 189:f392fc9709a3 528 /** @defgroup RCC_PLL_Prediv_Factor RCC PLL Prediv Factor
AnnaBridge 189:f392fc9709a3 529 * @{
AnnaBridge 189:f392fc9709a3 530 */
AnnaBridge 189:f392fc9709a3 531
AnnaBridge 189:f392fc9709a3 532 #define RCC_PREDIV_DIV1 RCC_CFGR2_PREDIV_DIV1
AnnaBridge 189:f392fc9709a3 533 #define RCC_PREDIV_DIV2 RCC_CFGR2_PREDIV_DIV2
AnnaBridge 189:f392fc9709a3 534 #define RCC_PREDIV_DIV3 RCC_CFGR2_PREDIV_DIV3
AnnaBridge 189:f392fc9709a3 535 #define RCC_PREDIV_DIV4 RCC_CFGR2_PREDIV_DIV4
AnnaBridge 189:f392fc9709a3 536 #define RCC_PREDIV_DIV5 RCC_CFGR2_PREDIV_DIV5
AnnaBridge 189:f392fc9709a3 537 #define RCC_PREDIV_DIV6 RCC_CFGR2_PREDIV_DIV6
AnnaBridge 189:f392fc9709a3 538 #define RCC_PREDIV_DIV7 RCC_CFGR2_PREDIV_DIV7
AnnaBridge 189:f392fc9709a3 539 #define RCC_PREDIV_DIV8 RCC_CFGR2_PREDIV_DIV8
AnnaBridge 189:f392fc9709a3 540 #define RCC_PREDIV_DIV9 RCC_CFGR2_PREDIV_DIV9
AnnaBridge 189:f392fc9709a3 541 #define RCC_PREDIV_DIV10 RCC_CFGR2_PREDIV_DIV10
AnnaBridge 189:f392fc9709a3 542 #define RCC_PREDIV_DIV11 RCC_CFGR2_PREDIV_DIV11
AnnaBridge 189:f392fc9709a3 543 #define RCC_PREDIV_DIV12 RCC_CFGR2_PREDIV_DIV12
AnnaBridge 189:f392fc9709a3 544 #define RCC_PREDIV_DIV13 RCC_CFGR2_PREDIV_DIV13
AnnaBridge 189:f392fc9709a3 545 #define RCC_PREDIV_DIV14 RCC_CFGR2_PREDIV_DIV14
AnnaBridge 189:f392fc9709a3 546 #define RCC_PREDIV_DIV15 RCC_CFGR2_PREDIV_DIV15
AnnaBridge 189:f392fc9709a3 547 #define RCC_PREDIV_DIV16 RCC_CFGR2_PREDIV_DIV16
AnnaBridge 189:f392fc9709a3 548
AnnaBridge 189:f392fc9709a3 549 /**
AnnaBridge 189:f392fc9709a3 550 * @}
AnnaBridge 189:f392fc9709a3 551 */
AnnaBridge 189:f392fc9709a3 552
AnnaBridge 189:f392fc9709a3 553 #endif
AnnaBridge 189:f392fc9709a3 554 #if defined(RCC_CFGR_PLLSRC_HSI_DIV2)
AnnaBridge 189:f392fc9709a3 555 /** @defgroup RCC_PLL_HSE_Prediv_Factor RCC PLL HSE Prediv Factor
AnnaBridge 189:f392fc9709a3 556 * @{
AnnaBridge 189:f392fc9709a3 557 */
AnnaBridge 189:f392fc9709a3 558
AnnaBridge 189:f392fc9709a3 559 #define RCC_HSE_PREDIV_DIV1 RCC_CFGR2_PREDIV_DIV1
AnnaBridge 189:f392fc9709a3 560 #define RCC_HSE_PREDIV_DIV2 RCC_CFGR2_PREDIV_DIV2
AnnaBridge 189:f392fc9709a3 561 #define RCC_HSE_PREDIV_DIV3 RCC_CFGR2_PREDIV_DIV3
AnnaBridge 189:f392fc9709a3 562 #define RCC_HSE_PREDIV_DIV4 RCC_CFGR2_PREDIV_DIV4
AnnaBridge 189:f392fc9709a3 563 #define RCC_HSE_PREDIV_DIV5 RCC_CFGR2_PREDIV_DIV5
AnnaBridge 189:f392fc9709a3 564 #define RCC_HSE_PREDIV_DIV6 RCC_CFGR2_PREDIV_DIV6
AnnaBridge 189:f392fc9709a3 565 #define RCC_HSE_PREDIV_DIV7 RCC_CFGR2_PREDIV_DIV7
AnnaBridge 189:f392fc9709a3 566 #define RCC_HSE_PREDIV_DIV8 RCC_CFGR2_PREDIV_DIV8
AnnaBridge 189:f392fc9709a3 567 #define RCC_HSE_PREDIV_DIV9 RCC_CFGR2_PREDIV_DIV9
AnnaBridge 189:f392fc9709a3 568 #define RCC_HSE_PREDIV_DIV10 RCC_CFGR2_PREDIV_DIV10
AnnaBridge 189:f392fc9709a3 569 #define RCC_HSE_PREDIV_DIV11 RCC_CFGR2_PREDIV_DIV11
AnnaBridge 189:f392fc9709a3 570 #define RCC_HSE_PREDIV_DIV12 RCC_CFGR2_PREDIV_DIV12
AnnaBridge 189:f392fc9709a3 571 #define RCC_HSE_PREDIV_DIV13 RCC_CFGR2_PREDIV_DIV13
AnnaBridge 189:f392fc9709a3 572 #define RCC_HSE_PREDIV_DIV14 RCC_CFGR2_PREDIV_DIV14
AnnaBridge 189:f392fc9709a3 573 #define RCC_HSE_PREDIV_DIV15 RCC_CFGR2_PREDIV_DIV15
AnnaBridge 189:f392fc9709a3 574 #define RCC_HSE_PREDIV_DIV16 RCC_CFGR2_PREDIV_DIV16
AnnaBridge 189:f392fc9709a3 575
AnnaBridge 189:f392fc9709a3 576 /**
AnnaBridge 189:f392fc9709a3 577 * @}
AnnaBridge 189:f392fc9709a3 578 */
AnnaBridge 189:f392fc9709a3 579 #endif /* RCC_CFGR_PLLSRC_HSI_DIV2 */
AnnaBridge 189:f392fc9709a3 580
AnnaBridge 189:f392fc9709a3 581 #if defined(RCC_CFGR3_USART2SW)
AnnaBridge 189:f392fc9709a3 582 /** @defgroup RCC_USART2_Clock_Source RCC USART2 Clock Source
AnnaBridge 189:f392fc9709a3 583 * @{
AnnaBridge 189:f392fc9709a3 584 */
AnnaBridge 189:f392fc9709a3 585 #define RCC_USART2CLKSOURCE_PCLK1 RCC_CFGR3_USART2SW_PCLK
AnnaBridge 189:f392fc9709a3 586 #define RCC_USART2CLKSOURCE_SYSCLK RCC_CFGR3_USART2SW_SYSCLK
AnnaBridge 189:f392fc9709a3 587 #define RCC_USART2CLKSOURCE_LSE RCC_CFGR3_USART2SW_LSE
AnnaBridge 189:f392fc9709a3 588 #define RCC_USART2CLKSOURCE_HSI RCC_CFGR3_USART2SW_HSI
AnnaBridge 189:f392fc9709a3 589
AnnaBridge 189:f392fc9709a3 590 /**
AnnaBridge 189:f392fc9709a3 591 * @}
AnnaBridge 189:f392fc9709a3 592 */
AnnaBridge 189:f392fc9709a3 593 #endif /* RCC_CFGR3_USART2SW */
AnnaBridge 189:f392fc9709a3 594
AnnaBridge 189:f392fc9709a3 595 #if defined(RCC_CFGR3_USART3SW)
AnnaBridge 189:f392fc9709a3 596 /** @defgroup RCC_USART3_Clock_Source RCC USART3 Clock Source
AnnaBridge 189:f392fc9709a3 597 * @{
AnnaBridge 189:f392fc9709a3 598 */
AnnaBridge 189:f392fc9709a3 599 #define RCC_USART3CLKSOURCE_PCLK1 RCC_CFGR3_USART3SW_PCLK
AnnaBridge 189:f392fc9709a3 600 #define RCC_USART3CLKSOURCE_SYSCLK RCC_CFGR3_USART3SW_SYSCLK
AnnaBridge 189:f392fc9709a3 601 #define RCC_USART3CLKSOURCE_LSE RCC_CFGR3_USART3SW_LSE
AnnaBridge 189:f392fc9709a3 602 #define RCC_USART3CLKSOURCE_HSI RCC_CFGR3_USART3SW_HSI
AnnaBridge 189:f392fc9709a3 603
AnnaBridge 189:f392fc9709a3 604 /**
AnnaBridge 189:f392fc9709a3 605 * @}
AnnaBridge 189:f392fc9709a3 606 */
AnnaBridge 189:f392fc9709a3 607 #endif /* RCC_CFGR3_USART3SW */
AnnaBridge 189:f392fc9709a3 608
AnnaBridge 189:f392fc9709a3 609 /** @defgroup RCC_I2C1_Clock_Source RCC I2C1 Clock Source
AnnaBridge 189:f392fc9709a3 610 * @{
AnnaBridge 189:f392fc9709a3 611 */
AnnaBridge 189:f392fc9709a3 612 #define RCC_I2C1CLKSOURCE_HSI RCC_CFGR3_I2C1SW_HSI
AnnaBridge 189:f392fc9709a3 613 #define RCC_I2C1CLKSOURCE_SYSCLK RCC_CFGR3_I2C1SW_SYSCLK
AnnaBridge 189:f392fc9709a3 614
AnnaBridge 189:f392fc9709a3 615 /**
AnnaBridge 189:f392fc9709a3 616 * @}
AnnaBridge 189:f392fc9709a3 617 */
AnnaBridge 189:f392fc9709a3 618 /** @defgroup RCC_MCO_Index MCO Index
AnnaBridge 189:f392fc9709a3 619 * @{
AnnaBridge 189:f392fc9709a3 620 */
AnnaBridge 189:f392fc9709a3 621 #define RCC_MCO1 (0x00000000U)
AnnaBridge 189:f392fc9709a3 622 #define RCC_MCO RCC_MCO1 /*!< MCO1 to be compliant with other families with 2 MCOs*/
AnnaBridge 189:f392fc9709a3 623
AnnaBridge 189:f392fc9709a3 624 /**
AnnaBridge 189:f392fc9709a3 625 * @}
AnnaBridge 189:f392fc9709a3 626 */
AnnaBridge 189:f392fc9709a3 627
AnnaBridge 189:f392fc9709a3 628 /** @defgroup RCC_Interrupt Interrupts
AnnaBridge 189:f392fc9709a3 629 * @{
AnnaBridge 189:f392fc9709a3 630 */
AnnaBridge 189:f392fc9709a3 631 #define RCC_IT_LSIRDY ((uint8_t)RCC_CIR_LSIRDYF) /*!< LSI Ready Interrupt flag */
AnnaBridge 189:f392fc9709a3 632 #define RCC_IT_LSERDY ((uint8_t)RCC_CIR_LSERDYF) /*!< LSE Ready Interrupt flag */
AnnaBridge 189:f392fc9709a3 633 #define RCC_IT_HSIRDY ((uint8_t)RCC_CIR_HSIRDYF) /*!< HSI Ready Interrupt flag */
AnnaBridge 189:f392fc9709a3 634 #define RCC_IT_HSERDY ((uint8_t)RCC_CIR_HSERDYF) /*!< HSE Ready Interrupt flag */
AnnaBridge 189:f392fc9709a3 635 #define RCC_IT_PLLRDY ((uint8_t)RCC_CIR_PLLRDYF) /*!< PLL Ready Interrupt flag */
AnnaBridge 189:f392fc9709a3 636 #define RCC_IT_CSS ((uint8_t)RCC_CIR_CSSF) /*!< Clock Security System Interrupt flag */
AnnaBridge 189:f392fc9709a3 637 /**
AnnaBridge 189:f392fc9709a3 638 * @}
AnnaBridge 189:f392fc9709a3 639 */
AnnaBridge 189:f392fc9709a3 640
AnnaBridge 189:f392fc9709a3 641 /** @defgroup RCC_Flag Flags
AnnaBridge 189:f392fc9709a3 642 * Elements values convention: XXXYYYYYb
AnnaBridge 189:f392fc9709a3 643 * - YYYYY : Flag position in the register
AnnaBridge 189:f392fc9709a3 644 * - XXX : Register index
AnnaBridge 189:f392fc9709a3 645 * - 001: CR register
AnnaBridge 189:f392fc9709a3 646 * - 010: BDCR register
AnnaBridge 189:f392fc9709a3 647 * - 011: CSR register
AnnaBridge 189:f392fc9709a3 648 * - 100: CFGR register
AnnaBridge 189:f392fc9709a3 649 * @{
AnnaBridge 189:f392fc9709a3 650 */
AnnaBridge 189:f392fc9709a3 651 /* Flags in the CR register */
AnnaBridge 189:f392fc9709a3 652 #define RCC_FLAG_HSIRDY ((uint8_t)((CR_REG_INDEX << 5U) | POSITION_VAL(RCC_CR_HSIRDY))) /*!< Internal High Speed clock ready flag */
AnnaBridge 189:f392fc9709a3 653 #define RCC_FLAG_HSERDY ((uint8_t)((CR_REG_INDEX << 5U) | POSITION_VAL(RCC_CR_HSERDY))) /*!< External High Speed clock ready flag */
AnnaBridge 189:f392fc9709a3 654 #define RCC_FLAG_PLLRDY ((uint8_t)((CR_REG_INDEX << 5U) | POSITION_VAL(RCC_CR_PLLRDY))) /*!< PLL clock ready flag */
AnnaBridge 189:f392fc9709a3 655
AnnaBridge 189:f392fc9709a3 656 /* Flags in the CSR register */
AnnaBridge 189:f392fc9709a3 657 #define RCC_FLAG_LSIRDY ((uint8_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_LSIRDY))) /*!< Internal Low Speed oscillator Ready */
AnnaBridge 189:f392fc9709a3 658 #if defined(RCC_CSR_V18PWRRSTF)
AnnaBridge 189:f392fc9709a3 659 #define RCC_FLAG_V18PWRRST ((uint8_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_V18PWRRSTF)))
AnnaBridge 189:f392fc9709a3 660 #endif
AnnaBridge 189:f392fc9709a3 661 #define RCC_FLAG_OBLRST ((uint8_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_OBLRSTF))) /*!< Options bytes loading reset flag */
AnnaBridge 189:f392fc9709a3 662 #define RCC_FLAG_PINRST ((uint8_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_PINRSTF))) /*!< PIN reset flag */
AnnaBridge 189:f392fc9709a3 663 #define RCC_FLAG_PORRST ((uint8_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_PORRSTF))) /*!< POR/PDR reset flag */
AnnaBridge 189:f392fc9709a3 664 #define RCC_FLAG_SFTRST ((uint8_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_SFTRSTF))) /*!< Software Reset flag */
AnnaBridge 189:f392fc9709a3 665 #define RCC_FLAG_IWDGRST ((uint8_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_IWDGRSTF))) /*!< Independent Watchdog reset flag */
AnnaBridge 189:f392fc9709a3 666 #define RCC_FLAG_WWDGRST ((uint8_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_WWDGRSTF))) /*!< Window watchdog reset flag */
AnnaBridge 189:f392fc9709a3 667 #define RCC_FLAG_LPWRRST ((uint8_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_LPWRRSTF))) /*!< Low-Power reset flag */
AnnaBridge 189:f392fc9709a3 668
AnnaBridge 189:f392fc9709a3 669 /* Flags in the BDCR register */
AnnaBridge 189:f392fc9709a3 670 #define RCC_FLAG_LSERDY ((uint8_t)((BDCR_REG_INDEX << 5U) | POSITION_VAL(RCC_BDCR_LSERDY))) /*!< External Low Speed oscillator Ready */
AnnaBridge 189:f392fc9709a3 671
AnnaBridge 189:f392fc9709a3 672 /* Flags in the CFGR register */
AnnaBridge 189:f392fc9709a3 673 #if defined(RCC_CFGR_MCOF)
AnnaBridge 189:f392fc9709a3 674 #define RCC_FLAG_MCO ((uint8_t)((CFGR_REG_INDEX << 5U) | POSITION_VAL(RCC_CFGR_MCOF))) /*!< Microcontroller Clock Output Flag */
AnnaBridge 189:f392fc9709a3 675 #endif /* RCC_CFGR_MCOF */
AnnaBridge 189:f392fc9709a3 676
AnnaBridge 189:f392fc9709a3 677 /**
AnnaBridge 189:f392fc9709a3 678 * @}
AnnaBridge 189:f392fc9709a3 679 */
AnnaBridge 189:f392fc9709a3 680
AnnaBridge 189:f392fc9709a3 681 /**
AnnaBridge 189:f392fc9709a3 682 * @}
AnnaBridge 189:f392fc9709a3 683 */
AnnaBridge 189:f392fc9709a3 684
AnnaBridge 189:f392fc9709a3 685 /* Exported macro ------------------------------------------------------------*/
AnnaBridge 189:f392fc9709a3 686
AnnaBridge 189:f392fc9709a3 687 /** @defgroup RCC_Exported_Macros RCC Exported Macros
AnnaBridge 189:f392fc9709a3 688 * @{
AnnaBridge 189:f392fc9709a3 689 */
AnnaBridge 189:f392fc9709a3 690
AnnaBridge 189:f392fc9709a3 691 /** @defgroup RCC_AHB_Clock_Enable_Disable RCC AHB Clock Enable Disable
AnnaBridge 189:f392fc9709a3 692 * @brief Enable or disable the AHB peripheral clock.
AnnaBridge 189:f392fc9709a3 693 * @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge 189:f392fc9709a3 694 * is disabled and the application software has to enable this clock before
AnnaBridge 189:f392fc9709a3 695 * using it.
AnnaBridge 189:f392fc9709a3 696 * @{
AnnaBridge 189:f392fc9709a3 697 */
AnnaBridge 189:f392fc9709a3 698 #define __HAL_RCC_GPIOA_CLK_ENABLE() do { \
AnnaBridge 189:f392fc9709a3 699 __IO uint32_t tmpreg; \
AnnaBridge 189:f392fc9709a3 700 SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOAEN);\
AnnaBridge 189:f392fc9709a3 701 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 189:f392fc9709a3 702 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOAEN);\
AnnaBridge 189:f392fc9709a3 703 UNUSED(tmpreg); \
AnnaBridge 189:f392fc9709a3 704 } while(0U)
AnnaBridge 189:f392fc9709a3 705 #define __HAL_RCC_GPIOB_CLK_ENABLE() do { \
AnnaBridge 189:f392fc9709a3 706 __IO uint32_t tmpreg; \
AnnaBridge 189:f392fc9709a3 707 SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOBEN);\
AnnaBridge 189:f392fc9709a3 708 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 189:f392fc9709a3 709 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOBEN);\
AnnaBridge 189:f392fc9709a3 710 UNUSED(tmpreg); \
AnnaBridge 189:f392fc9709a3 711 } while(0U)
AnnaBridge 189:f392fc9709a3 712 #define __HAL_RCC_GPIOC_CLK_ENABLE() do { \
AnnaBridge 189:f392fc9709a3 713 __IO uint32_t tmpreg; \
AnnaBridge 189:f392fc9709a3 714 SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOCEN);\
AnnaBridge 189:f392fc9709a3 715 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 189:f392fc9709a3 716 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOCEN);\
AnnaBridge 189:f392fc9709a3 717 UNUSED(tmpreg); \
AnnaBridge 189:f392fc9709a3 718 } while(0U)
AnnaBridge 189:f392fc9709a3 719 #define __HAL_RCC_GPIOD_CLK_ENABLE() do { \
AnnaBridge 189:f392fc9709a3 720 __IO uint32_t tmpreg; \
AnnaBridge 189:f392fc9709a3 721 SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIODEN);\
AnnaBridge 189:f392fc9709a3 722 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 189:f392fc9709a3 723 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIODEN);\
AnnaBridge 189:f392fc9709a3 724 UNUSED(tmpreg); \
AnnaBridge 189:f392fc9709a3 725 } while(0U)
AnnaBridge 189:f392fc9709a3 726 #define __HAL_RCC_GPIOF_CLK_ENABLE() do { \
AnnaBridge 189:f392fc9709a3 727 __IO uint32_t tmpreg; \
AnnaBridge 189:f392fc9709a3 728 SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOFEN);\
AnnaBridge 189:f392fc9709a3 729 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 189:f392fc9709a3 730 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOFEN);\
AnnaBridge 189:f392fc9709a3 731 UNUSED(tmpreg); \
AnnaBridge 189:f392fc9709a3 732 } while(0U)
AnnaBridge 189:f392fc9709a3 733 #define __HAL_RCC_CRC_CLK_ENABLE() do { \
AnnaBridge 189:f392fc9709a3 734 __IO uint32_t tmpreg; \
AnnaBridge 189:f392fc9709a3 735 SET_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\
AnnaBridge 189:f392fc9709a3 736 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 189:f392fc9709a3 737 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\
AnnaBridge 189:f392fc9709a3 738 UNUSED(tmpreg); \
AnnaBridge 189:f392fc9709a3 739 } while(0U)
AnnaBridge 189:f392fc9709a3 740 #define __HAL_RCC_DMA1_CLK_ENABLE() do { \
AnnaBridge 189:f392fc9709a3 741 __IO uint32_t tmpreg; \
AnnaBridge 189:f392fc9709a3 742 SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\
AnnaBridge 189:f392fc9709a3 743 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 189:f392fc9709a3 744 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\
AnnaBridge 189:f392fc9709a3 745 UNUSED(tmpreg); \
AnnaBridge 189:f392fc9709a3 746 } while(0U)
AnnaBridge 189:f392fc9709a3 747 #define __HAL_RCC_SRAM_CLK_ENABLE() do { \
AnnaBridge 189:f392fc9709a3 748 __IO uint32_t tmpreg; \
AnnaBridge 189:f392fc9709a3 749 SET_BIT(RCC->AHBENR, RCC_AHBENR_SRAMEN);\
AnnaBridge 189:f392fc9709a3 750 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 189:f392fc9709a3 751 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_SRAMEN);\
AnnaBridge 189:f392fc9709a3 752 UNUSED(tmpreg); \
AnnaBridge 189:f392fc9709a3 753 } while(0U)
AnnaBridge 189:f392fc9709a3 754 #define __HAL_RCC_FLITF_CLK_ENABLE() do { \
AnnaBridge 189:f392fc9709a3 755 __IO uint32_t tmpreg; \
AnnaBridge 189:f392fc9709a3 756 SET_BIT(RCC->AHBENR, RCC_AHBENR_FLITFEN);\
AnnaBridge 189:f392fc9709a3 757 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 189:f392fc9709a3 758 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FLITFEN);\
AnnaBridge 189:f392fc9709a3 759 UNUSED(tmpreg); \
AnnaBridge 189:f392fc9709a3 760 } while(0U)
AnnaBridge 189:f392fc9709a3 761 #define __HAL_RCC_TSC_CLK_ENABLE() do { \
AnnaBridge 189:f392fc9709a3 762 __IO uint32_t tmpreg; \
AnnaBridge 189:f392fc9709a3 763 SET_BIT(RCC->AHBENR, RCC_AHBENR_TSCEN);\
AnnaBridge 189:f392fc9709a3 764 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 189:f392fc9709a3 765 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_TSCEN);\
AnnaBridge 189:f392fc9709a3 766 UNUSED(tmpreg); \
AnnaBridge 189:f392fc9709a3 767 } while(0U)
AnnaBridge 189:f392fc9709a3 768
AnnaBridge 189:f392fc9709a3 769 #define __HAL_RCC_GPIOA_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOAEN))
AnnaBridge 189:f392fc9709a3 770 #define __HAL_RCC_GPIOB_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOBEN))
AnnaBridge 189:f392fc9709a3 771 #define __HAL_RCC_GPIOC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOCEN))
AnnaBridge 189:f392fc9709a3 772 #define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIODEN))
AnnaBridge 189:f392fc9709a3 773 #define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOFEN))
AnnaBridge 189:f392fc9709a3 774 #define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_CRCEN))
AnnaBridge 189:f392fc9709a3 775 #define __HAL_RCC_DMA1_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA1EN))
AnnaBridge 189:f392fc9709a3 776 #define __HAL_RCC_SRAM_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_SRAMEN))
AnnaBridge 189:f392fc9709a3 777 #define __HAL_RCC_FLITF_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_FLITFEN))
AnnaBridge 189:f392fc9709a3 778 #define __HAL_RCC_TSC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_TSCEN))
AnnaBridge 189:f392fc9709a3 779 /**
AnnaBridge 189:f392fc9709a3 780 * @}
AnnaBridge 189:f392fc9709a3 781 */
AnnaBridge 189:f392fc9709a3 782
AnnaBridge 189:f392fc9709a3 783 /** @defgroup RCC_APB1_Clock_Enable_Disable RCC APB1 Clock Enable Disable
AnnaBridge 189:f392fc9709a3 784 * @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
AnnaBridge 189:f392fc9709a3 785 * @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge 189:f392fc9709a3 786 * is disabled and the application software has to enable this clock before
AnnaBridge 189:f392fc9709a3 787 * using it.
AnnaBridge 189:f392fc9709a3 788 * @{
AnnaBridge 189:f392fc9709a3 789 */
AnnaBridge 189:f392fc9709a3 790 #define __HAL_RCC_TIM2_CLK_ENABLE() do { \
AnnaBridge 189:f392fc9709a3 791 __IO uint32_t tmpreg; \
AnnaBridge 189:f392fc9709a3 792 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
AnnaBridge 189:f392fc9709a3 793 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 189:f392fc9709a3 794 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
AnnaBridge 189:f392fc9709a3 795 UNUSED(tmpreg); \
AnnaBridge 189:f392fc9709a3 796 } while(0U)
AnnaBridge 189:f392fc9709a3 797 #define __HAL_RCC_TIM6_CLK_ENABLE() do { \
AnnaBridge 189:f392fc9709a3 798 __IO uint32_t tmpreg; \
AnnaBridge 189:f392fc9709a3 799 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
AnnaBridge 189:f392fc9709a3 800 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 189:f392fc9709a3 801 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
AnnaBridge 189:f392fc9709a3 802 UNUSED(tmpreg); \
AnnaBridge 189:f392fc9709a3 803 } while(0U)
AnnaBridge 189:f392fc9709a3 804 #define __HAL_RCC_WWDG_CLK_ENABLE() do { \
AnnaBridge 189:f392fc9709a3 805 __IO uint32_t tmpreg; \
AnnaBridge 189:f392fc9709a3 806 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
AnnaBridge 189:f392fc9709a3 807 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 189:f392fc9709a3 808 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
AnnaBridge 189:f392fc9709a3 809 UNUSED(tmpreg); \
AnnaBridge 189:f392fc9709a3 810 } while(0U)
AnnaBridge 189:f392fc9709a3 811 #define __HAL_RCC_USART2_CLK_ENABLE() do { \
AnnaBridge 189:f392fc9709a3 812 __IO uint32_t tmpreg; \
AnnaBridge 189:f392fc9709a3 813 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
AnnaBridge 189:f392fc9709a3 814 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 189:f392fc9709a3 815 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
AnnaBridge 189:f392fc9709a3 816 UNUSED(tmpreg); \
AnnaBridge 189:f392fc9709a3 817 } while(0U)
AnnaBridge 189:f392fc9709a3 818 #define __HAL_RCC_USART3_CLK_ENABLE() do { \
AnnaBridge 189:f392fc9709a3 819 __IO uint32_t tmpreg; \
AnnaBridge 189:f392fc9709a3 820 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
AnnaBridge 189:f392fc9709a3 821 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 189:f392fc9709a3 822 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
AnnaBridge 189:f392fc9709a3 823 UNUSED(tmpreg); \
AnnaBridge 189:f392fc9709a3 824 } while(0U)
AnnaBridge 189:f392fc9709a3 825 #define __HAL_RCC_I2C1_CLK_ENABLE() do { \
AnnaBridge 189:f392fc9709a3 826 __IO uint32_t tmpreg; \
AnnaBridge 189:f392fc9709a3 827 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
AnnaBridge 189:f392fc9709a3 828 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 189:f392fc9709a3 829 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
AnnaBridge 189:f392fc9709a3 830 UNUSED(tmpreg); \
AnnaBridge 189:f392fc9709a3 831 } while(0U)
AnnaBridge 189:f392fc9709a3 832 #define __HAL_RCC_PWR_CLK_ENABLE() do { \
AnnaBridge 189:f392fc9709a3 833 __IO uint32_t tmpreg; \
AnnaBridge 189:f392fc9709a3 834 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
AnnaBridge 189:f392fc9709a3 835 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 189:f392fc9709a3 836 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
AnnaBridge 189:f392fc9709a3 837 UNUSED(tmpreg); \
AnnaBridge 189:f392fc9709a3 838 } while(0U)
AnnaBridge 189:f392fc9709a3 839 #define __HAL_RCC_DAC1_CLK_ENABLE() do { \
AnnaBridge 189:f392fc9709a3 840 __IO uint32_t tmpreg; \
AnnaBridge 189:f392fc9709a3 841 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DAC1EN);\
AnnaBridge 189:f392fc9709a3 842 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 189:f392fc9709a3 843 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DAC1EN);\
AnnaBridge 189:f392fc9709a3 844 UNUSED(tmpreg); \
AnnaBridge 189:f392fc9709a3 845 } while(0U)
AnnaBridge 189:f392fc9709a3 846
AnnaBridge 189:f392fc9709a3 847 #define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
AnnaBridge 189:f392fc9709a3 848 #define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
AnnaBridge 189:f392fc9709a3 849 #define __HAL_RCC_WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))
AnnaBridge 189:f392fc9709a3 850 #define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))
AnnaBridge 189:f392fc9709a3 851 #define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
AnnaBridge 189:f392fc9709a3 852 #define __HAL_RCC_I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))
AnnaBridge 189:f392fc9709a3 853 #define __HAL_RCC_PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN))
AnnaBridge 189:f392fc9709a3 854 #define __HAL_RCC_DAC1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DAC1EN))
AnnaBridge 189:f392fc9709a3 855 /**
AnnaBridge 189:f392fc9709a3 856 * @}
AnnaBridge 189:f392fc9709a3 857 */
AnnaBridge 189:f392fc9709a3 858
AnnaBridge 189:f392fc9709a3 859 /** @defgroup RCC_APB2_Clock_Enable_Disable RCC APB2 Clock Enable Disable
AnnaBridge 189:f392fc9709a3 860 * @brief Enable or disable the High Speed APB (APB2) peripheral clock.
AnnaBridge 189:f392fc9709a3 861 * @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge 189:f392fc9709a3 862 * is disabled and the application software has to enable this clock before
AnnaBridge 189:f392fc9709a3 863 * using it.
AnnaBridge 189:f392fc9709a3 864 * @{
AnnaBridge 189:f392fc9709a3 865 */
AnnaBridge 189:f392fc9709a3 866 #define __HAL_RCC_SYSCFG_CLK_ENABLE() do { \
AnnaBridge 189:f392fc9709a3 867 __IO uint32_t tmpreg; \
AnnaBridge 189:f392fc9709a3 868 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\
AnnaBridge 189:f392fc9709a3 869 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 189:f392fc9709a3 870 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\
AnnaBridge 189:f392fc9709a3 871 UNUSED(tmpreg); \
AnnaBridge 189:f392fc9709a3 872 } while(0U)
AnnaBridge 189:f392fc9709a3 873 #define __HAL_RCC_TIM15_CLK_ENABLE() do { \
AnnaBridge 189:f392fc9709a3 874 __IO uint32_t tmpreg; \
AnnaBridge 189:f392fc9709a3 875 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN);\
AnnaBridge 189:f392fc9709a3 876 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 189:f392fc9709a3 877 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN);\
AnnaBridge 189:f392fc9709a3 878 UNUSED(tmpreg); \
AnnaBridge 189:f392fc9709a3 879 } while(0U)
AnnaBridge 189:f392fc9709a3 880 #define __HAL_RCC_TIM16_CLK_ENABLE() do { \
AnnaBridge 189:f392fc9709a3 881 __IO uint32_t tmpreg; \
AnnaBridge 189:f392fc9709a3 882 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN);\
AnnaBridge 189:f392fc9709a3 883 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 189:f392fc9709a3 884 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN);\
AnnaBridge 189:f392fc9709a3 885 UNUSED(tmpreg); \
AnnaBridge 189:f392fc9709a3 886 } while(0U)
AnnaBridge 189:f392fc9709a3 887 #define __HAL_RCC_TIM17_CLK_ENABLE() do { \
AnnaBridge 189:f392fc9709a3 888 __IO uint32_t tmpreg; \
AnnaBridge 189:f392fc9709a3 889 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN);\
AnnaBridge 189:f392fc9709a3 890 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 189:f392fc9709a3 891 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN);\
AnnaBridge 189:f392fc9709a3 892 UNUSED(tmpreg); \
AnnaBridge 189:f392fc9709a3 893 } while(0U)
AnnaBridge 189:f392fc9709a3 894 #define __HAL_RCC_USART1_CLK_ENABLE() do { \
AnnaBridge 189:f392fc9709a3 895 __IO uint32_t tmpreg; \
AnnaBridge 189:f392fc9709a3 896 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
AnnaBridge 189:f392fc9709a3 897 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 189:f392fc9709a3 898 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
AnnaBridge 189:f392fc9709a3 899 UNUSED(tmpreg); \
AnnaBridge 189:f392fc9709a3 900 } while(0U)
AnnaBridge 189:f392fc9709a3 901
AnnaBridge 189:f392fc9709a3 902 #define __HAL_RCC_SYSCFG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN))
AnnaBridge 189:f392fc9709a3 903 #define __HAL_RCC_TIM15_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM15EN))
AnnaBridge 189:f392fc9709a3 904 #define __HAL_RCC_TIM16_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM16EN))
AnnaBridge 189:f392fc9709a3 905 #define __HAL_RCC_TIM17_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM17EN))
AnnaBridge 189:f392fc9709a3 906 #define __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN))
AnnaBridge 189:f392fc9709a3 907 /**
AnnaBridge 189:f392fc9709a3 908 * @}
AnnaBridge 189:f392fc9709a3 909 */
AnnaBridge 189:f392fc9709a3 910
AnnaBridge 189:f392fc9709a3 911 /** @defgroup RCC_AHB_Peripheral_Clock_Enable_Disable_Status AHB Peripheral Clock Enable Disable Status
AnnaBridge 189:f392fc9709a3 912 * @brief Get the enable or disable status of the AHB peripheral clock.
AnnaBridge 189:f392fc9709a3 913 * @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge 189:f392fc9709a3 914 * is disabled and the application software has to enable this clock before
AnnaBridge 189:f392fc9709a3 915 * using it.
AnnaBridge 189:f392fc9709a3 916 * @{
AnnaBridge 189:f392fc9709a3 917 */
AnnaBridge 189:f392fc9709a3 918 #define __HAL_RCC_GPIOA_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOAEN)) != RESET)
AnnaBridge 189:f392fc9709a3 919 #define __HAL_RCC_GPIOB_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOBEN)) != RESET)
AnnaBridge 189:f392fc9709a3 920 #define __HAL_RCC_GPIOC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOCEN)) != RESET)
AnnaBridge 189:f392fc9709a3 921 #define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIODEN)) != RESET)
AnnaBridge 189:f392fc9709a3 922 #define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOFEN)) != RESET)
AnnaBridge 189:f392fc9709a3 923 #define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_CRCEN)) != RESET)
AnnaBridge 189:f392fc9709a3 924 #define __HAL_RCC_DMA1_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA1EN)) != RESET)
AnnaBridge 189:f392fc9709a3 925 #define __HAL_RCC_SRAM_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_SRAMEN)) != RESET)
AnnaBridge 189:f392fc9709a3 926 #define __HAL_RCC_FLITF_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_FLITFEN)) != RESET)
AnnaBridge 189:f392fc9709a3 927 #define __HAL_RCC_TSC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_TSCEN)) != RESET)
AnnaBridge 189:f392fc9709a3 928
AnnaBridge 189:f392fc9709a3 929 #define __HAL_RCC_GPIOA_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOAEN)) == RESET)
AnnaBridge 189:f392fc9709a3 930 #define __HAL_RCC_GPIOB_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOBEN)) == RESET)
AnnaBridge 189:f392fc9709a3 931 #define __HAL_RCC_GPIOC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOCEN)) == RESET)
AnnaBridge 189:f392fc9709a3 932 #define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIODEN)) == RESET)
AnnaBridge 189:f392fc9709a3 933 #define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOFEN)) == RESET)
AnnaBridge 189:f392fc9709a3 934 #define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_CRCEN)) == RESET)
AnnaBridge 189:f392fc9709a3 935 #define __HAL_RCC_DMA1_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA1EN)) == RESET)
AnnaBridge 189:f392fc9709a3 936 #define __HAL_RCC_SRAM_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_SRAMEN)) == RESET)
AnnaBridge 189:f392fc9709a3 937 #define __HAL_RCC_FLITF_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_FLITFEN)) == RESET)
AnnaBridge 189:f392fc9709a3 938 #define __HAL_RCC_TSC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_TSCEN)) == RESET)
AnnaBridge 189:f392fc9709a3 939 /**
AnnaBridge 189:f392fc9709a3 940 * @}
AnnaBridge 189:f392fc9709a3 941 */
AnnaBridge 189:f392fc9709a3 942
AnnaBridge 189:f392fc9709a3 943 /** @defgroup RCC_APB1_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status
AnnaBridge 189:f392fc9709a3 944 * @brief Get the enable or disable status of the APB1 peripheral clock.
AnnaBridge 189:f392fc9709a3 945 * @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge 189:f392fc9709a3 946 * is disabled and the application software has to enable this clock before
AnnaBridge 189:f392fc9709a3 947 * using it.
AnnaBridge 189:f392fc9709a3 948 * @{
AnnaBridge 189:f392fc9709a3 949 */
AnnaBridge 189:f392fc9709a3 950 #define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET)
AnnaBridge 189:f392fc9709a3 951 #define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET)
AnnaBridge 189:f392fc9709a3 952 #define __HAL_RCC_WWDG_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) != RESET)
AnnaBridge 189:f392fc9709a3 953 #define __HAL_RCC_USART2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) != RESET)
AnnaBridge 189:f392fc9709a3 954 #define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET)
AnnaBridge 189:f392fc9709a3 955 #define __HAL_RCC_I2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) != RESET)
AnnaBridge 189:f392fc9709a3 956 #define __HAL_RCC_PWR_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) != RESET)
AnnaBridge 189:f392fc9709a3 957 #define __HAL_RCC_DAC1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DAC1EN)) != RESET)
AnnaBridge 189:f392fc9709a3 958
AnnaBridge 189:f392fc9709a3 959 #define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET)
AnnaBridge 189:f392fc9709a3 960 #define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET)
AnnaBridge 189:f392fc9709a3 961 #define __HAL_RCC_WWDG_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) == RESET)
AnnaBridge 189:f392fc9709a3 962 #define __HAL_RCC_USART2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) == RESET)
AnnaBridge 189:f392fc9709a3 963 #define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET)
AnnaBridge 189:f392fc9709a3 964 #define __HAL_RCC_I2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) == RESET)
AnnaBridge 189:f392fc9709a3 965 #define __HAL_RCC_PWR_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) == RESET)
AnnaBridge 189:f392fc9709a3 966 #define __HAL_RCC_DAC1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DAC1EN)) == RESET)
AnnaBridge 189:f392fc9709a3 967 /**
AnnaBridge 189:f392fc9709a3 968 * @}
AnnaBridge 189:f392fc9709a3 969 */
AnnaBridge 189:f392fc9709a3 970
AnnaBridge 189:f392fc9709a3 971 /** @defgroup RCC_APB2_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
AnnaBridge 189:f392fc9709a3 972 * @brief EGet the enable or disable status of the APB2 peripheral clock.
AnnaBridge 189:f392fc9709a3 973 * @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge 189:f392fc9709a3 974 * is disabled and the application software has to enable this clock before
AnnaBridge 189:f392fc9709a3 975 * using it.
AnnaBridge 189:f392fc9709a3 976 * @{
AnnaBridge 189:f392fc9709a3 977 */
AnnaBridge 189:f392fc9709a3 978 #define __HAL_RCC_SYSCFG_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) != RESET)
AnnaBridge 189:f392fc9709a3 979 #define __HAL_RCC_TIM15_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM15EN)) != RESET)
AnnaBridge 189:f392fc9709a3 980 #define __HAL_RCC_TIM16_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM16EN)) != RESET)
AnnaBridge 189:f392fc9709a3 981 #define __HAL_RCC_TIM17_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM17EN)) != RESET)
AnnaBridge 189:f392fc9709a3 982 #define __HAL_RCC_USART1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) != RESET)
AnnaBridge 189:f392fc9709a3 983
AnnaBridge 189:f392fc9709a3 984 #define __HAL_RCC_SYSCFG_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) == RESET)
AnnaBridge 189:f392fc9709a3 985 #define __HAL_RCC_TIM15_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM15EN)) == RESET)
AnnaBridge 189:f392fc9709a3 986 #define __HAL_RCC_TIM16_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM16EN)) == RESET)
AnnaBridge 189:f392fc9709a3 987 #define __HAL_RCC_TIM17_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM17EN)) == RESET)
AnnaBridge 189:f392fc9709a3 988 #define __HAL_RCC_USART1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) == RESET)
AnnaBridge 189:f392fc9709a3 989 /**
AnnaBridge 189:f392fc9709a3 990 * @}
AnnaBridge 189:f392fc9709a3 991 */
AnnaBridge 189:f392fc9709a3 992
AnnaBridge 189:f392fc9709a3 993 /** @defgroup RCC_AHB_Force_Release_Reset RCC AHB Force Release Reset
AnnaBridge 189:f392fc9709a3 994 * @brief Force or release AHB peripheral reset.
AnnaBridge 189:f392fc9709a3 995 * @{
AnnaBridge 189:f392fc9709a3 996 */
AnnaBridge 189:f392fc9709a3 997 #define __HAL_RCC_AHB_FORCE_RESET() (RCC->AHBRSTR = 0xFFFFFFFFU)
AnnaBridge 189:f392fc9709a3 998 #define __HAL_RCC_GPIOA_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOARST))
AnnaBridge 189:f392fc9709a3 999 #define __HAL_RCC_GPIOB_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOBRST))
AnnaBridge 189:f392fc9709a3 1000 #define __HAL_RCC_GPIOC_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOCRST))
AnnaBridge 189:f392fc9709a3 1001 #define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIODRST))
AnnaBridge 189:f392fc9709a3 1002 #define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOFRST))
AnnaBridge 189:f392fc9709a3 1003 #define __HAL_RCC_TSC_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_TSCRST))
AnnaBridge 189:f392fc9709a3 1004
AnnaBridge 189:f392fc9709a3 1005 #define __HAL_RCC_AHB_RELEASE_RESET() (RCC->AHBRSTR = 0x00000000U)
AnnaBridge 189:f392fc9709a3 1006 #define __HAL_RCC_GPIOA_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOARST))
AnnaBridge 189:f392fc9709a3 1007 #define __HAL_RCC_GPIOB_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOBRST))
AnnaBridge 189:f392fc9709a3 1008 #define __HAL_RCC_GPIOC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOCRST))
AnnaBridge 189:f392fc9709a3 1009 #define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIODRST))
AnnaBridge 189:f392fc9709a3 1010 #define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOFRST))
AnnaBridge 189:f392fc9709a3 1011 #define __HAL_RCC_TSC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_TSCRST))
AnnaBridge 189:f392fc9709a3 1012 /**
AnnaBridge 189:f392fc9709a3 1013 * @}
AnnaBridge 189:f392fc9709a3 1014 */
AnnaBridge 189:f392fc9709a3 1015
AnnaBridge 189:f392fc9709a3 1016 /** @defgroup RCC_APB1_Force_Release_Reset RCC APB1 Force Release Reset
AnnaBridge 189:f392fc9709a3 1017 * @brief Force or release APB1 peripheral reset.
AnnaBridge 189:f392fc9709a3 1018 * @{
AnnaBridge 189:f392fc9709a3 1019 */
AnnaBridge 189:f392fc9709a3 1020 #define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFFU)
AnnaBridge 189:f392fc9709a3 1021 #define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST))
AnnaBridge 189:f392fc9709a3 1022 #define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST))
AnnaBridge 189:f392fc9709a3 1023 #define __HAL_RCC_WWDG_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_WWDGRST))
AnnaBridge 189:f392fc9709a3 1024 #define __HAL_RCC_USART2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART2RST))
AnnaBridge 189:f392fc9709a3 1025 #define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST))
AnnaBridge 189:f392fc9709a3 1026 #define __HAL_RCC_I2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C1RST))
AnnaBridge 189:f392fc9709a3 1027 #define __HAL_RCC_PWR_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_PWRRST))
AnnaBridge 189:f392fc9709a3 1028 #define __HAL_RCC_DAC1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DAC1RST))
AnnaBridge 189:f392fc9709a3 1029
AnnaBridge 189:f392fc9709a3 1030 #define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00000000U)
AnnaBridge 189:f392fc9709a3 1031 #define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
AnnaBridge 189:f392fc9709a3 1032 #define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
AnnaBridge 189:f392fc9709a3 1033 #define __HAL_RCC_WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST))
AnnaBridge 189:f392fc9709a3 1034 #define __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST))
AnnaBridge 189:f392fc9709a3 1035 #define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
AnnaBridge 189:f392fc9709a3 1036 #define __HAL_RCC_I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST))
AnnaBridge 189:f392fc9709a3 1037 #define __HAL_RCC_PWR_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST))
AnnaBridge 189:f392fc9709a3 1038 #define __HAL_RCC_DAC1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DAC1RST))
AnnaBridge 189:f392fc9709a3 1039 /**
AnnaBridge 189:f392fc9709a3 1040 * @}
AnnaBridge 189:f392fc9709a3 1041 */
AnnaBridge 189:f392fc9709a3 1042
AnnaBridge 189:f392fc9709a3 1043 /** @defgroup RCC_APB2_Force_Release_Reset RCC APB2 Force Release Reset
AnnaBridge 189:f392fc9709a3 1044 * @brief Force or release APB2 peripheral reset.
AnnaBridge 189:f392fc9709a3 1045 * @{
AnnaBridge 189:f392fc9709a3 1046 */
AnnaBridge 189:f392fc9709a3 1047 #define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFFU)
AnnaBridge 189:f392fc9709a3 1048 #define __HAL_RCC_SYSCFG_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SYSCFGRST))
AnnaBridge 189:f392fc9709a3 1049 #define __HAL_RCC_TIM15_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM15RST))
AnnaBridge 189:f392fc9709a3 1050 #define __HAL_RCC_TIM16_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM16RST))
AnnaBridge 189:f392fc9709a3 1051 #define __HAL_RCC_TIM17_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM17RST))
AnnaBridge 189:f392fc9709a3 1052 #define __HAL_RCC_USART1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART1RST))
AnnaBridge 189:f392fc9709a3 1053
AnnaBridge 189:f392fc9709a3 1054 #define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00000000U)
AnnaBridge 189:f392fc9709a3 1055 #define __HAL_RCC_SYSCFG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SYSCFGRST))
AnnaBridge 189:f392fc9709a3 1056 #define __HAL_RCC_TIM15_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM15RST))
AnnaBridge 189:f392fc9709a3 1057 #define __HAL_RCC_TIM16_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM16RST))
AnnaBridge 189:f392fc9709a3 1058 #define __HAL_RCC_TIM17_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM17RST))
AnnaBridge 189:f392fc9709a3 1059 #define __HAL_RCC_USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST))
AnnaBridge 189:f392fc9709a3 1060 /**
AnnaBridge 189:f392fc9709a3 1061 * @}
AnnaBridge 189:f392fc9709a3 1062 */
AnnaBridge 189:f392fc9709a3 1063
AnnaBridge 189:f392fc9709a3 1064 /** @defgroup RCC_HSI_Configuration HSI Configuration
AnnaBridge 189:f392fc9709a3 1065 * @{
AnnaBridge 189:f392fc9709a3 1066 */
AnnaBridge 189:f392fc9709a3 1067
AnnaBridge 189:f392fc9709a3 1068 /** @brief Macros to enable or disable the Internal High Speed oscillator (HSI).
AnnaBridge 189:f392fc9709a3 1069 * @note The HSI is stopped by hardware when entering STOP and STANDBY modes.
AnnaBridge 189:f392fc9709a3 1070 * It is used (enabled by hardware) as system clock source after startup
AnnaBridge 189:f392fc9709a3 1071 * from Reset, wakeup from STOP and STANDBY mode, or in case of failure
AnnaBridge 189:f392fc9709a3 1072 * of the HSE used directly or indirectly as system clock (if the Clock
AnnaBridge 189:f392fc9709a3 1073 * Security System CSS is enabled).
AnnaBridge 189:f392fc9709a3 1074 * @note HSI can not be stopped if it is used as system clock source. In this case,
AnnaBridge 189:f392fc9709a3 1075 * you have to select another source of the system clock then stop the HSI.
AnnaBridge 189:f392fc9709a3 1076 * @note After enabling the HSI, the application software should wait on HSIRDY
AnnaBridge 189:f392fc9709a3 1077 * flag to be set indicating that HSI clock is stable and can be used as
AnnaBridge 189:f392fc9709a3 1078 * system clock source.
AnnaBridge 189:f392fc9709a3 1079 * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
AnnaBridge 189:f392fc9709a3 1080 * clock cycles.
AnnaBridge 189:f392fc9709a3 1081 */
AnnaBridge 189:f392fc9709a3 1082 #define __HAL_RCC_HSI_ENABLE() (*(__IO uint32_t *) RCC_CR_HSION_BB = ENABLE)
AnnaBridge 189:f392fc9709a3 1083 #define __HAL_RCC_HSI_DISABLE() (*(__IO uint32_t *) RCC_CR_HSION_BB = DISABLE)
AnnaBridge 189:f392fc9709a3 1084
AnnaBridge 189:f392fc9709a3 1085 /** @brief Macro to adjust the Internal High Speed oscillator (HSI) calibration value.
AnnaBridge 189:f392fc9709a3 1086 * @note The calibration is used to compensate for the variations in voltage
AnnaBridge 189:f392fc9709a3 1087 * and temperature that influence the frequency of the internal HSI RC.
AnnaBridge 189:f392fc9709a3 1088 * @param _HSICALIBRATIONVALUE_ specifies the calibration trimming value.
AnnaBridge 189:f392fc9709a3 1089 * (default is RCC_HSICALIBRATION_DEFAULT).
AnnaBridge 189:f392fc9709a3 1090 * This parameter must be a number between 0 and 0x1F.
AnnaBridge 189:f392fc9709a3 1091 */
AnnaBridge 189:f392fc9709a3 1092 #define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(_HSICALIBRATIONVALUE_) \
AnnaBridge 189:f392fc9709a3 1093 (MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, (uint32_t)(_HSICALIBRATIONVALUE_) << POSITION_VAL(RCC_CR_HSITRIM)))
AnnaBridge 189:f392fc9709a3 1094
AnnaBridge 189:f392fc9709a3 1095 /**
AnnaBridge 189:f392fc9709a3 1096 * @}
AnnaBridge 189:f392fc9709a3 1097 */
AnnaBridge 189:f392fc9709a3 1098
AnnaBridge 189:f392fc9709a3 1099 /** @defgroup RCC_LSI_Configuration LSI Configuration
AnnaBridge 189:f392fc9709a3 1100 * @{
AnnaBridge 189:f392fc9709a3 1101 */
AnnaBridge 189:f392fc9709a3 1102
AnnaBridge 189:f392fc9709a3 1103 /** @brief Macro to enable the Internal Low Speed oscillator (LSI).
AnnaBridge 189:f392fc9709a3 1104 * @note After enabling the LSI, the application software should wait on
AnnaBridge 189:f392fc9709a3 1105 * LSIRDY flag to be set indicating that LSI clock is stable and can
AnnaBridge 189:f392fc9709a3 1106 * be used to clock the IWDG and/or the RTC.
AnnaBridge 189:f392fc9709a3 1107 */
AnnaBridge 189:f392fc9709a3 1108 #define __HAL_RCC_LSI_ENABLE() (*(__IO uint32_t *) RCC_CSR_LSION_BB = ENABLE)
AnnaBridge 189:f392fc9709a3 1109
AnnaBridge 189:f392fc9709a3 1110 /** @brief Macro to disable the Internal Low Speed oscillator (LSI).
AnnaBridge 189:f392fc9709a3 1111 * @note LSI can not be disabled if the IWDG is running.
AnnaBridge 189:f392fc9709a3 1112 * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
AnnaBridge 189:f392fc9709a3 1113 * clock cycles.
AnnaBridge 189:f392fc9709a3 1114 */
AnnaBridge 189:f392fc9709a3 1115 #define __HAL_RCC_LSI_DISABLE() (*(__IO uint32_t *) RCC_CSR_LSION_BB = DISABLE)
AnnaBridge 189:f392fc9709a3 1116
AnnaBridge 189:f392fc9709a3 1117 /**
AnnaBridge 189:f392fc9709a3 1118 * @}
AnnaBridge 189:f392fc9709a3 1119 */
AnnaBridge 189:f392fc9709a3 1120
AnnaBridge 189:f392fc9709a3 1121 /** @defgroup RCC_HSE_Configuration HSE Configuration
AnnaBridge 189:f392fc9709a3 1122 * @{
AnnaBridge 189:f392fc9709a3 1123 */
AnnaBridge 189:f392fc9709a3 1124
AnnaBridge 189:f392fc9709a3 1125 /**
AnnaBridge 189:f392fc9709a3 1126 * @brief Macro to configure the External High Speed oscillator (HSE).
AnnaBridge 189:f392fc9709a3 1127 * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not
AnnaBridge 189:f392fc9709a3 1128 * supported by this macro. User should request a transition to HSE Off
AnnaBridge 189:f392fc9709a3 1129 * first and then HSE On or HSE Bypass.
AnnaBridge 189:f392fc9709a3 1130 * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
AnnaBridge 189:f392fc9709a3 1131 * software should wait on HSERDY flag to be set indicating that HSE clock
AnnaBridge 189:f392fc9709a3 1132 * is stable and can be used to clock the PLL and/or system clock.
AnnaBridge 189:f392fc9709a3 1133 * @note HSE state can not be changed if it is used directly or through the
AnnaBridge 189:f392fc9709a3 1134 * PLL as system clock. In this case, you have to select another source
AnnaBridge 189:f392fc9709a3 1135 * of the system clock then change the HSE state (ex. disable it).
AnnaBridge 189:f392fc9709a3 1136 * @note The HSE is stopped by hardware when entering STOP and STANDBY modes.
AnnaBridge 189:f392fc9709a3 1137 * @note This function reset the CSSON bit, so if the clock security system(CSS)
AnnaBridge 189:f392fc9709a3 1138 * was previously enabled you have to enable it again after calling this
AnnaBridge 189:f392fc9709a3 1139 * function.
AnnaBridge 189:f392fc9709a3 1140 * @param __STATE__ specifies the new state of the HSE.
AnnaBridge 189:f392fc9709a3 1141 * This parameter can be one of the following values:
AnnaBridge 189:f392fc9709a3 1142 * @arg @ref RCC_HSE_OFF turn OFF the HSE oscillator, HSERDY flag goes low after
AnnaBridge 189:f392fc9709a3 1143 * 6 HSE oscillator clock cycles.
AnnaBridge 189:f392fc9709a3 1144 * @arg @ref RCC_HSE_ON turn ON the HSE oscillator
AnnaBridge 189:f392fc9709a3 1145 * @arg @ref RCC_HSE_BYPASS HSE oscillator bypassed with external clock
AnnaBridge 189:f392fc9709a3 1146 */
AnnaBridge 189:f392fc9709a3 1147 #define __HAL_RCC_HSE_CONFIG(__STATE__) \
AnnaBridge 189:f392fc9709a3 1148 do{ \
AnnaBridge 189:f392fc9709a3 1149 if ((__STATE__) == RCC_HSE_ON) \
AnnaBridge 189:f392fc9709a3 1150 { \
AnnaBridge 189:f392fc9709a3 1151 SET_BIT(RCC->CR, RCC_CR_HSEON); \
AnnaBridge 189:f392fc9709a3 1152 } \
AnnaBridge 189:f392fc9709a3 1153 else if ((__STATE__) == RCC_HSE_OFF) \
AnnaBridge 189:f392fc9709a3 1154 { \
AnnaBridge 189:f392fc9709a3 1155 CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \
AnnaBridge 189:f392fc9709a3 1156 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \
AnnaBridge 189:f392fc9709a3 1157 } \
AnnaBridge 189:f392fc9709a3 1158 else if ((__STATE__) == RCC_HSE_BYPASS) \
AnnaBridge 189:f392fc9709a3 1159 { \
AnnaBridge 189:f392fc9709a3 1160 SET_BIT(RCC->CR, RCC_CR_HSEBYP); \
AnnaBridge 189:f392fc9709a3 1161 SET_BIT(RCC->CR, RCC_CR_HSEON); \
AnnaBridge 189:f392fc9709a3 1162 } \
AnnaBridge 189:f392fc9709a3 1163 else \
AnnaBridge 189:f392fc9709a3 1164 { \
AnnaBridge 189:f392fc9709a3 1165 CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \
AnnaBridge 189:f392fc9709a3 1166 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \
AnnaBridge 189:f392fc9709a3 1167 } \
AnnaBridge 189:f392fc9709a3 1168 }while(0U)
AnnaBridge 189:f392fc9709a3 1169
AnnaBridge 189:f392fc9709a3 1170 /**
AnnaBridge 189:f392fc9709a3 1171 * @}
AnnaBridge 189:f392fc9709a3 1172 */
AnnaBridge 189:f392fc9709a3 1173
AnnaBridge 189:f392fc9709a3 1174 /** @defgroup RCC_LSE_Configuration LSE Configuration
AnnaBridge 189:f392fc9709a3 1175 * @{
AnnaBridge 189:f392fc9709a3 1176 */
AnnaBridge 189:f392fc9709a3 1177
AnnaBridge 189:f392fc9709a3 1178 /**
AnnaBridge 189:f392fc9709a3 1179 * @brief Macro to configure the External Low Speed oscillator (LSE).
AnnaBridge 189:f392fc9709a3 1180 * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro.
AnnaBridge 189:f392fc9709a3 1181 * @note As the LSE is in the Backup domain and write access is denied to
AnnaBridge 189:f392fc9709a3 1182 * this domain after reset, you have to enable write access using
AnnaBridge 189:f392fc9709a3 1183 * @ref HAL_PWR_EnableBkUpAccess() function before to configure the LSE
AnnaBridge 189:f392fc9709a3 1184 * (to be done once after reset).
AnnaBridge 189:f392fc9709a3 1185 * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application
AnnaBridge 189:f392fc9709a3 1186 * software should wait on LSERDY flag to be set indicating that LSE clock
AnnaBridge 189:f392fc9709a3 1187 * is stable and can be used to clock the RTC.
AnnaBridge 189:f392fc9709a3 1188 * @param __STATE__ specifies the new state of the LSE.
AnnaBridge 189:f392fc9709a3 1189 * This parameter can be one of the following values:
AnnaBridge 189:f392fc9709a3 1190 * @arg @ref RCC_LSE_OFF turn OFF the LSE oscillator, LSERDY flag goes low after
AnnaBridge 189:f392fc9709a3 1191 * 6 LSE oscillator clock cycles.
AnnaBridge 189:f392fc9709a3 1192 * @arg @ref RCC_LSE_ON turn ON the LSE oscillator.
AnnaBridge 189:f392fc9709a3 1193 * @arg @ref RCC_LSE_BYPASS LSE oscillator bypassed with external clock.
AnnaBridge 189:f392fc9709a3 1194 */
AnnaBridge 189:f392fc9709a3 1195 #define __HAL_RCC_LSE_CONFIG(__STATE__) \
AnnaBridge 189:f392fc9709a3 1196 do{ \
AnnaBridge 189:f392fc9709a3 1197 if ((__STATE__) == RCC_LSE_ON) \
AnnaBridge 189:f392fc9709a3 1198 { \
AnnaBridge 189:f392fc9709a3 1199 SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
AnnaBridge 189:f392fc9709a3 1200 } \
AnnaBridge 189:f392fc9709a3 1201 else if ((__STATE__) == RCC_LSE_OFF) \
AnnaBridge 189:f392fc9709a3 1202 { \
AnnaBridge 189:f392fc9709a3 1203 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
AnnaBridge 189:f392fc9709a3 1204 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
AnnaBridge 189:f392fc9709a3 1205 } \
AnnaBridge 189:f392fc9709a3 1206 else if ((__STATE__) == RCC_LSE_BYPASS) \
AnnaBridge 189:f392fc9709a3 1207 { \
AnnaBridge 189:f392fc9709a3 1208 SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
AnnaBridge 189:f392fc9709a3 1209 SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
AnnaBridge 189:f392fc9709a3 1210 } \
AnnaBridge 189:f392fc9709a3 1211 else \
AnnaBridge 189:f392fc9709a3 1212 { \
AnnaBridge 189:f392fc9709a3 1213 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
AnnaBridge 189:f392fc9709a3 1214 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
AnnaBridge 189:f392fc9709a3 1215 } \
AnnaBridge 189:f392fc9709a3 1216 }while(0U)
AnnaBridge 189:f392fc9709a3 1217
AnnaBridge 189:f392fc9709a3 1218 /**
AnnaBridge 189:f392fc9709a3 1219 * @}
AnnaBridge 189:f392fc9709a3 1220 */
AnnaBridge 189:f392fc9709a3 1221
AnnaBridge 189:f392fc9709a3 1222 /** @defgroup RCC_USARTx_Clock_Config RCC USARTx Clock Config
AnnaBridge 189:f392fc9709a3 1223 * @{
AnnaBridge 189:f392fc9709a3 1224 */
AnnaBridge 189:f392fc9709a3 1225
AnnaBridge 189:f392fc9709a3 1226 /** @brief Macro to configure the USART1 clock (USART1CLK).
AnnaBridge 189:f392fc9709a3 1227 * @param __USART1CLKSOURCE__ specifies the USART1 clock source.
AnnaBridge 189:f392fc9709a3 1228 * This parameter can be one of the following values:
AnnaBridge 189:f392fc9709a3 1229 @if STM32F302xC
AnnaBridge 189:f392fc9709a3 1230 * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock
AnnaBridge 189:f392fc9709a3 1231 @endif
AnnaBridge 189:f392fc9709a3 1232 @if STM32F303xC
AnnaBridge 189:f392fc9709a3 1233 * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock
AnnaBridge 189:f392fc9709a3 1234 @endif
AnnaBridge 189:f392fc9709a3 1235 @if STM32F358xx
AnnaBridge 189:f392fc9709a3 1236 * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock
AnnaBridge 189:f392fc9709a3 1237 @endif
AnnaBridge 189:f392fc9709a3 1238 @if STM32F302xE
AnnaBridge 189:f392fc9709a3 1239 * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock
AnnaBridge 189:f392fc9709a3 1240 @endif
AnnaBridge 189:f392fc9709a3 1241 @if STM32F303xE
AnnaBridge 189:f392fc9709a3 1242 * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock
AnnaBridge 189:f392fc9709a3 1243 @endif
AnnaBridge 189:f392fc9709a3 1244 @if STM32F398xx
AnnaBridge 189:f392fc9709a3 1245 * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock
AnnaBridge 189:f392fc9709a3 1246 @endif
AnnaBridge 189:f392fc9709a3 1247 @if STM32F373xC
AnnaBridge 189:f392fc9709a3 1248 * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock
AnnaBridge 189:f392fc9709a3 1249 @endif
AnnaBridge 189:f392fc9709a3 1250 @if STM32F378xx
AnnaBridge 189:f392fc9709a3 1251 * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock
AnnaBridge 189:f392fc9709a3 1252 @endif
AnnaBridge 189:f392fc9709a3 1253 @if STM32F301x8
AnnaBridge 189:f392fc9709a3 1254 * @arg @ref RCC_USART1CLKSOURCE_PCLK1 PCLK1 selected as USART1 clock
AnnaBridge 189:f392fc9709a3 1255 @endif
AnnaBridge 189:f392fc9709a3 1256 @if STM32F302x8
AnnaBridge 189:f392fc9709a3 1257 * @arg @ref RCC_USART1CLKSOURCE_PCLK1 PCLK1 selected as USART1 clock
AnnaBridge 189:f392fc9709a3 1258 @endif
AnnaBridge 189:f392fc9709a3 1259 @if STM32F318xx
AnnaBridge 189:f392fc9709a3 1260 * @arg @ref RCC_USART1CLKSOURCE_PCLK1 PCLK1 selected as USART1 clock
AnnaBridge 189:f392fc9709a3 1261 @endif
AnnaBridge 189:f392fc9709a3 1262 @if STM32F303x8
AnnaBridge 189:f392fc9709a3 1263 * @arg @ref RCC_USART1CLKSOURCE_PCLK1 PCLK1 selected as USART1 clock
AnnaBridge 189:f392fc9709a3 1264 @endif
AnnaBridge 189:f392fc9709a3 1265 @if STM32F334x8
AnnaBridge 189:f392fc9709a3 1266 * @arg @ref RCC_USART1CLKSOURCE_PCLK1 PCLK1 selected as USART1 clock
AnnaBridge 189:f392fc9709a3 1267 @endif
AnnaBridge 189:f392fc9709a3 1268 @if STM32F328xx
AnnaBridge 189:f392fc9709a3 1269 * @arg @ref RCC_USART1CLKSOURCE_PCLK1 PCLK1 selected as USART1 clock
AnnaBridge 189:f392fc9709a3 1270 @endif
AnnaBridge 189:f392fc9709a3 1271 * @arg @ref RCC_USART1CLKSOURCE_HSI HSI selected as USART1 clock
AnnaBridge 189:f392fc9709a3 1272 * @arg @ref RCC_USART1CLKSOURCE_SYSCLK System Clock selected as USART1 clock
AnnaBridge 189:f392fc9709a3 1273 * @arg @ref RCC_USART1CLKSOURCE_LSE LSE selected as USART1 clock
AnnaBridge 189:f392fc9709a3 1274 */
AnnaBridge 189:f392fc9709a3 1275 #define __HAL_RCC_USART1_CONFIG(__USART1CLKSOURCE__) \
AnnaBridge 189:f392fc9709a3 1276 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_USART1SW, (uint32_t)(__USART1CLKSOURCE__))
AnnaBridge 189:f392fc9709a3 1277
AnnaBridge 189:f392fc9709a3 1278 /** @brief Macro to get the USART1 clock source.
AnnaBridge 189:f392fc9709a3 1279 * @retval The clock source can be one of the following values:
AnnaBridge 189:f392fc9709a3 1280 @if STM32F302xC
AnnaBridge 189:f392fc9709a3 1281 * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock
AnnaBridge 189:f392fc9709a3 1282 @endif
AnnaBridge 189:f392fc9709a3 1283 @if STM32F303xC
AnnaBridge 189:f392fc9709a3 1284 * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock
AnnaBridge 189:f392fc9709a3 1285 @endif
AnnaBridge 189:f392fc9709a3 1286 @if STM32F358xx
AnnaBridge 189:f392fc9709a3 1287 * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock
AnnaBridge 189:f392fc9709a3 1288 @endif
AnnaBridge 189:f392fc9709a3 1289 @if STM32F302xE
AnnaBridge 189:f392fc9709a3 1290 * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock
AnnaBridge 189:f392fc9709a3 1291 @endif
AnnaBridge 189:f392fc9709a3 1292 @if STM32F303xE
AnnaBridge 189:f392fc9709a3 1293 * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock
AnnaBridge 189:f392fc9709a3 1294 @endif
AnnaBridge 189:f392fc9709a3 1295 @if STM32F398xx
AnnaBridge 189:f392fc9709a3 1296 * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock
AnnaBridge 189:f392fc9709a3 1297 @endif
AnnaBridge 189:f392fc9709a3 1298 @if STM32F373xC
AnnaBridge 189:f392fc9709a3 1299 * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock
AnnaBridge 189:f392fc9709a3 1300 @endif
AnnaBridge 189:f392fc9709a3 1301 @if STM32F378xx
AnnaBridge 189:f392fc9709a3 1302 * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock
AnnaBridge 189:f392fc9709a3 1303 @endif
AnnaBridge 189:f392fc9709a3 1304 @if STM32F301x8
AnnaBridge 189:f392fc9709a3 1305 * @arg @ref RCC_USART1CLKSOURCE_PCLK1 PCLK1 selected as USART1 clock
AnnaBridge 189:f392fc9709a3 1306 @endif
AnnaBridge 189:f392fc9709a3 1307 @if STM32F302x8
AnnaBridge 189:f392fc9709a3 1308 * @arg @ref RCC_USART1CLKSOURCE_PCLK1 PCLK1 selected as USART1 clock
AnnaBridge 189:f392fc9709a3 1309 @endif
AnnaBridge 189:f392fc9709a3 1310 @if STM32F318xx
AnnaBridge 189:f392fc9709a3 1311 * @arg @ref RCC_USART1CLKSOURCE_PCLK1 PCLK1 selected as USART1 clock
AnnaBridge 189:f392fc9709a3 1312 @endif
AnnaBridge 189:f392fc9709a3 1313 @if STM32F303x8
AnnaBridge 189:f392fc9709a3 1314 * @arg @ref RCC_USART1CLKSOURCE_PCLK1 PCLK1 selected as USART1 clock
AnnaBridge 189:f392fc9709a3 1315 @endif
AnnaBridge 189:f392fc9709a3 1316 @if STM32F334x8
AnnaBridge 189:f392fc9709a3 1317 * @arg @ref RCC_USART1CLKSOURCE_PCLK1 PCLK1 selected as USART1 clock
AnnaBridge 189:f392fc9709a3 1318 @endif
AnnaBridge 189:f392fc9709a3 1319 @if STM32F328xx
AnnaBridge 189:f392fc9709a3 1320 * @arg @ref RCC_USART1CLKSOURCE_PCLK1 PCLK1 selected as USART1 clock
AnnaBridge 189:f392fc9709a3 1321 @endif
AnnaBridge 189:f392fc9709a3 1322 * @arg @ref RCC_USART1CLKSOURCE_HSI HSI selected as USART1 clock
AnnaBridge 189:f392fc9709a3 1323 * @arg @ref RCC_USART1CLKSOURCE_SYSCLK System Clock selected as USART1 clock
AnnaBridge 189:f392fc9709a3 1324 * @arg @ref RCC_USART1CLKSOURCE_LSE LSE selected as USART1 clock
AnnaBridge 189:f392fc9709a3 1325 */
AnnaBridge 189:f392fc9709a3 1326 #define __HAL_RCC_GET_USART1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_USART1SW)))
AnnaBridge 189:f392fc9709a3 1327
AnnaBridge 189:f392fc9709a3 1328 #if defined(RCC_CFGR3_USART2SW)
AnnaBridge 189:f392fc9709a3 1329 /** @brief Macro to configure the USART2 clock (USART2CLK).
AnnaBridge 189:f392fc9709a3 1330 * @param __USART2CLKSOURCE__ specifies the USART2 clock source.
AnnaBridge 189:f392fc9709a3 1331 * This parameter can be one of the following values:
AnnaBridge 189:f392fc9709a3 1332 * @arg @ref RCC_USART2CLKSOURCE_PCLK1 PCLK1 selected as USART2 clock
AnnaBridge 189:f392fc9709a3 1333 * @arg @ref RCC_USART2CLKSOURCE_HSI HSI selected as USART2 clock
AnnaBridge 189:f392fc9709a3 1334 * @arg @ref RCC_USART2CLKSOURCE_SYSCLK System Clock selected as USART2 clock
AnnaBridge 189:f392fc9709a3 1335 * @arg @ref RCC_USART2CLKSOURCE_LSE LSE selected as USART2 clock
AnnaBridge 189:f392fc9709a3 1336 */
AnnaBridge 189:f392fc9709a3 1337 #define __HAL_RCC_USART2_CONFIG(__USART2CLKSOURCE__) \
AnnaBridge 189:f392fc9709a3 1338 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_USART2SW, (uint32_t)(__USART2CLKSOURCE__))
AnnaBridge 189:f392fc9709a3 1339
AnnaBridge 189:f392fc9709a3 1340 /** @brief Macro to get the USART2 clock source.
AnnaBridge 189:f392fc9709a3 1341 * @retval The clock source can be one of the following values:
AnnaBridge 189:f392fc9709a3 1342 * @arg @ref RCC_USART2CLKSOURCE_PCLK1 PCLK1 selected as USART2 clock
AnnaBridge 189:f392fc9709a3 1343 * @arg @ref RCC_USART2CLKSOURCE_HSI HSI selected as USART2 clock
AnnaBridge 189:f392fc9709a3 1344 * @arg @ref RCC_USART2CLKSOURCE_SYSCLK System Clock selected as USART2 clock
AnnaBridge 189:f392fc9709a3 1345 * @arg @ref RCC_USART2CLKSOURCE_LSE LSE selected as USART2 clock
AnnaBridge 189:f392fc9709a3 1346 */
AnnaBridge 189:f392fc9709a3 1347 #define __HAL_RCC_GET_USART2_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_USART2SW)))
AnnaBridge 189:f392fc9709a3 1348 #endif /* RCC_CFGR3_USART2SW */
AnnaBridge 189:f392fc9709a3 1349
AnnaBridge 189:f392fc9709a3 1350 #if defined(RCC_CFGR3_USART3SW)
AnnaBridge 189:f392fc9709a3 1351 /** @brief Macro to configure the USART3 clock (USART3CLK).
AnnaBridge 189:f392fc9709a3 1352 * @param __USART3CLKSOURCE__ specifies the USART3 clock source.
AnnaBridge 189:f392fc9709a3 1353 * This parameter can be one of the following values:
AnnaBridge 189:f392fc9709a3 1354 * @arg @ref RCC_USART3CLKSOURCE_PCLK1 PCLK1 selected as USART3 clock
AnnaBridge 189:f392fc9709a3 1355 * @arg @ref RCC_USART3CLKSOURCE_HSI HSI selected as USART3 clock
AnnaBridge 189:f392fc9709a3 1356 * @arg @ref RCC_USART3CLKSOURCE_SYSCLK System Clock selected as USART3 clock
AnnaBridge 189:f392fc9709a3 1357 * @arg @ref RCC_USART3CLKSOURCE_LSE LSE selected as USART3 clock
AnnaBridge 189:f392fc9709a3 1358 */
AnnaBridge 189:f392fc9709a3 1359 #define __HAL_RCC_USART3_CONFIG(__USART3CLKSOURCE__) \
AnnaBridge 189:f392fc9709a3 1360 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_USART3SW, (uint32_t)(__USART3CLKSOURCE__))
AnnaBridge 189:f392fc9709a3 1361
AnnaBridge 189:f392fc9709a3 1362 /** @brief Macro to get the USART3 clock source.
AnnaBridge 189:f392fc9709a3 1363 * @retval The clock source can be one of the following values:
AnnaBridge 189:f392fc9709a3 1364 * @arg @ref RCC_USART3CLKSOURCE_PCLK1 PCLK1 selected as USART3 clock
AnnaBridge 189:f392fc9709a3 1365 * @arg @ref RCC_USART3CLKSOURCE_HSI HSI selected as USART3 clock
AnnaBridge 189:f392fc9709a3 1366 * @arg @ref RCC_USART3CLKSOURCE_SYSCLK System Clock selected as USART3 clock
AnnaBridge 189:f392fc9709a3 1367 * @arg @ref RCC_USART3CLKSOURCE_LSE LSE selected as USART3 clock
AnnaBridge 189:f392fc9709a3 1368 */
AnnaBridge 189:f392fc9709a3 1369 #define __HAL_RCC_GET_USART3_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_USART3SW)))
AnnaBridge 189:f392fc9709a3 1370 #endif /* RCC_CFGR3_USART2SW */
AnnaBridge 189:f392fc9709a3 1371 /**
AnnaBridge 189:f392fc9709a3 1372 * @}
AnnaBridge 189:f392fc9709a3 1373 */
AnnaBridge 189:f392fc9709a3 1374
AnnaBridge 189:f392fc9709a3 1375 /** @defgroup RCC_I2Cx_Clock_Config RCC I2Cx Clock Config
AnnaBridge 189:f392fc9709a3 1376 * @{
AnnaBridge 189:f392fc9709a3 1377 */
AnnaBridge 189:f392fc9709a3 1378
AnnaBridge 189:f392fc9709a3 1379 /** @brief Macro to configure the I2C1 clock (I2C1CLK).
AnnaBridge 189:f392fc9709a3 1380 * @param __I2C1CLKSOURCE__ specifies the I2C1 clock source.
AnnaBridge 189:f392fc9709a3 1381 * This parameter can be one of the following values:
AnnaBridge 189:f392fc9709a3 1382 * @arg @ref RCC_I2C1CLKSOURCE_HSI HSI selected as I2C1 clock
AnnaBridge 189:f392fc9709a3 1383 * @arg @ref RCC_I2C1CLKSOURCE_SYSCLK System Clock selected as I2C1 clock
AnnaBridge 189:f392fc9709a3 1384 */
AnnaBridge 189:f392fc9709a3 1385 #define __HAL_RCC_I2C1_CONFIG(__I2C1CLKSOURCE__) \
AnnaBridge 189:f392fc9709a3 1386 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_I2C1SW, (uint32_t)(__I2C1CLKSOURCE__))
AnnaBridge 189:f392fc9709a3 1387
AnnaBridge 189:f392fc9709a3 1388 /** @brief Macro to get the I2C1 clock source.
AnnaBridge 189:f392fc9709a3 1389 * @retval The clock source can be one of the following values:
AnnaBridge 189:f392fc9709a3 1390 * @arg @ref RCC_I2C1CLKSOURCE_HSI HSI selected as I2C1 clock
AnnaBridge 189:f392fc9709a3 1391 * @arg @ref RCC_I2C1CLKSOURCE_SYSCLK System Clock selected as I2C1 clock
AnnaBridge 189:f392fc9709a3 1392 */
AnnaBridge 189:f392fc9709a3 1393 #define __HAL_RCC_GET_I2C1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_I2C1SW)))
AnnaBridge 189:f392fc9709a3 1394 /**
AnnaBridge 189:f392fc9709a3 1395 * @}
AnnaBridge 189:f392fc9709a3 1396 */
AnnaBridge 189:f392fc9709a3 1397
AnnaBridge 189:f392fc9709a3 1398 /** @defgroup RCC_PLL_Configuration PLL Configuration
AnnaBridge 189:f392fc9709a3 1399 * @{
AnnaBridge 189:f392fc9709a3 1400 */
AnnaBridge 189:f392fc9709a3 1401
AnnaBridge 189:f392fc9709a3 1402 /** @brief Macro to enable the main PLL.
AnnaBridge 189:f392fc9709a3 1403 * @note After enabling the main PLL, the application software should wait on
AnnaBridge 189:f392fc9709a3 1404 * PLLRDY flag to be set indicating that PLL clock is stable and can
AnnaBridge 189:f392fc9709a3 1405 * be used as system clock source.
AnnaBridge 189:f392fc9709a3 1406 * @note The main PLL is disabled by hardware when entering STOP and STANDBY modes.
AnnaBridge 189:f392fc9709a3 1407 */
AnnaBridge 189:f392fc9709a3 1408 #define __HAL_RCC_PLL_ENABLE() (*(__IO uint32_t *) RCC_CR_PLLON_BB = ENABLE)
AnnaBridge 189:f392fc9709a3 1409
AnnaBridge 189:f392fc9709a3 1410 /** @brief Macro to disable the main PLL.
AnnaBridge 189:f392fc9709a3 1411 * @note The main PLL can not be disabled if it is used as system clock source
AnnaBridge 189:f392fc9709a3 1412 */
AnnaBridge 189:f392fc9709a3 1413 #define __HAL_RCC_PLL_DISABLE() (*(__IO uint32_t *) RCC_CR_PLLON_BB = DISABLE)
AnnaBridge 189:f392fc9709a3 1414
AnnaBridge 189:f392fc9709a3 1415
AnnaBridge 189:f392fc9709a3 1416 /** @brief Get oscillator clock selected as PLL input clock
AnnaBridge 189:f392fc9709a3 1417 * @retval The clock source used for PLL entry. The returned value can be one
AnnaBridge 189:f392fc9709a3 1418 * of the following:
AnnaBridge 189:f392fc9709a3 1419 * @arg @ref RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL input clock
AnnaBridge 189:f392fc9709a3 1420 * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL input clock
AnnaBridge 189:f392fc9709a3 1421 */
AnnaBridge 189:f392fc9709a3 1422 #define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLSRC)))
AnnaBridge 189:f392fc9709a3 1423
AnnaBridge 189:f392fc9709a3 1424 /**
AnnaBridge 189:f392fc9709a3 1425 * @}
AnnaBridge 189:f392fc9709a3 1426 */
AnnaBridge 189:f392fc9709a3 1427
AnnaBridge 189:f392fc9709a3 1428 /** @defgroup RCC_Get_Clock_source Get Clock source
AnnaBridge 189:f392fc9709a3 1429 * @{
AnnaBridge 189:f392fc9709a3 1430 */
AnnaBridge 189:f392fc9709a3 1431
AnnaBridge 189:f392fc9709a3 1432 /**
AnnaBridge 189:f392fc9709a3 1433 * @brief Macro to configure the system clock source.
AnnaBridge 189:f392fc9709a3 1434 * @param __SYSCLKSOURCE__ specifies the system clock source.
AnnaBridge 189:f392fc9709a3 1435 * This parameter can be one of the following values:
AnnaBridge 189:f392fc9709a3 1436 * @arg @ref RCC_SYSCLKSOURCE_HSI HSI oscillator is used as system clock source.
AnnaBridge 189:f392fc9709a3 1437 * @arg @ref RCC_SYSCLKSOURCE_HSE HSE oscillator is used as system clock source.
AnnaBridge 189:f392fc9709a3 1438 * @arg @ref RCC_SYSCLKSOURCE_PLLCLK PLL output is used as system clock source.
AnnaBridge 189:f392fc9709a3 1439 */
AnnaBridge 189:f392fc9709a3 1440 #define __HAL_RCC_SYSCLK_CONFIG(__SYSCLKSOURCE__) \
AnnaBridge 189:f392fc9709a3 1441 MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__SYSCLKSOURCE__))
AnnaBridge 189:f392fc9709a3 1442
AnnaBridge 189:f392fc9709a3 1443 /** @brief Macro to get the clock source used as system clock.
AnnaBridge 189:f392fc9709a3 1444 * @retval The clock source used as system clock. The returned value can be one
AnnaBridge 189:f392fc9709a3 1445 * of the following:
AnnaBridge 189:f392fc9709a3 1446 * @arg @ref RCC_SYSCLKSOURCE_STATUS_HSI HSI used as system clock
AnnaBridge 189:f392fc9709a3 1447 * @arg @ref RCC_SYSCLKSOURCE_STATUS_HSE HSE used as system clock
AnnaBridge 189:f392fc9709a3 1448 * @arg @ref RCC_SYSCLKSOURCE_STATUS_PLLCLK PLL used as system clock
AnnaBridge 189:f392fc9709a3 1449 */
AnnaBridge 189:f392fc9709a3 1450 #define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR,RCC_CFGR_SWS)))
AnnaBridge 189:f392fc9709a3 1451
AnnaBridge 189:f392fc9709a3 1452 /**
AnnaBridge 189:f392fc9709a3 1453 * @}
AnnaBridge 189:f392fc9709a3 1454 */
AnnaBridge 189:f392fc9709a3 1455
AnnaBridge 189:f392fc9709a3 1456 /** @defgroup RCCEx_MCOx_Clock_Config RCC Extended MCOx Clock Config
AnnaBridge 189:f392fc9709a3 1457 * @{
AnnaBridge 189:f392fc9709a3 1458 */
AnnaBridge 189:f392fc9709a3 1459
AnnaBridge 189:f392fc9709a3 1460 #if defined(RCC_CFGR_MCOPRE)
AnnaBridge 189:f392fc9709a3 1461 /** @brief Macro to configure the MCO clock.
AnnaBridge 189:f392fc9709a3 1462 * @param __MCOCLKSOURCE__ specifies the MCO clock source.
AnnaBridge 189:f392fc9709a3 1463 * This parameter can be one of the following values:
AnnaBridge 189:f392fc9709a3 1464 * @arg @ref RCC_MCO1SOURCE_NOCLOCK No clock selected as MCO clock
AnnaBridge 189:f392fc9709a3 1465 * @arg @ref RCC_MCO1SOURCE_SYSCLK System Clock selected as MCO clock
AnnaBridge 189:f392fc9709a3 1466 * @arg @ref RCC_MCO1SOURCE_HSI HSI oscillator clock selected as MCO clock
AnnaBridge 189:f392fc9709a3 1467 * @arg @ref RCC_MCO1SOURCE_HSE HSE selected as MCO clock
AnnaBridge 189:f392fc9709a3 1468 * @arg @ref RCC_MCO1SOURCE_LSI LSI selected as MCO clock
AnnaBridge 189:f392fc9709a3 1469 * @arg @ref RCC_MCO1SOURCE_LSE LSE selected as MCO clock
AnnaBridge 189:f392fc9709a3 1470 * @arg @ref RCC_MCO1SOURCE_PLLCLK_DIV2 PLLCLK Divided by 2 selected as MCO clock
AnnaBridge 189:f392fc9709a3 1471 * @param __MCODIV__ specifies the MCO clock prescaler.
AnnaBridge 189:f392fc9709a3 1472 * This parameter can be one of the following values:
AnnaBridge 189:f392fc9709a3 1473 * @arg @ref RCC_MCODIV_1 MCO clock source is divided by 1
AnnaBridge 189:f392fc9709a3 1474 * @arg @ref RCC_MCODIV_2 MCO clock source is divided by 2
AnnaBridge 189:f392fc9709a3 1475 * @arg @ref RCC_MCODIV_4 MCO clock source is divided by 4
AnnaBridge 189:f392fc9709a3 1476 * @arg @ref RCC_MCODIV_8 MCO clock source is divided by 8
AnnaBridge 189:f392fc9709a3 1477 * @arg @ref RCC_MCODIV_16 MCO clock source is divided by 16
AnnaBridge 189:f392fc9709a3 1478 * @arg @ref RCC_MCODIV_32 MCO clock source is divided by 32
AnnaBridge 189:f392fc9709a3 1479 * @arg @ref RCC_MCODIV_64 MCO clock source is divided by 64
AnnaBridge 189:f392fc9709a3 1480 * @arg @ref RCC_MCODIV_128 MCO clock source is divided by 128
AnnaBridge 189:f392fc9709a3 1481 */
AnnaBridge 189:f392fc9709a3 1482 #else
AnnaBridge 189:f392fc9709a3 1483 /** @brief Macro to configure the MCO clock.
AnnaBridge 189:f392fc9709a3 1484 * @param __MCOCLKSOURCE__ specifies the MCO clock source.
AnnaBridge 189:f392fc9709a3 1485 * This parameter can be one of the following values:
AnnaBridge 189:f392fc9709a3 1486 * @arg @ref RCC_MCO1SOURCE_NOCLOCK No clock selected as MCO clock
AnnaBridge 189:f392fc9709a3 1487 * @arg @ref RCC_MCO1SOURCE_SYSCLK System Clock selected as MCO clock
AnnaBridge 189:f392fc9709a3 1488 * @arg @ref RCC_MCO1SOURCE_HSI HSI selected as MCO clock
AnnaBridge 189:f392fc9709a3 1489 * @arg @ref RCC_MCO1SOURCE_HSE HSE selected as MCO clock
AnnaBridge 189:f392fc9709a3 1490 * @arg @ref RCC_MCO1SOURCE_LSI LSI selected as MCO clock
AnnaBridge 189:f392fc9709a3 1491 * @arg @ref RCC_MCO1SOURCE_LSE LSE selected as MCO clock
AnnaBridge 189:f392fc9709a3 1492 * @arg @ref RCC_MCO1SOURCE_PLLCLK_DIV2 PLLCLK Divided by 2 selected as MCO clock
AnnaBridge 189:f392fc9709a3 1493 * @param __MCODIV__ specifies the MCO clock prescaler.
AnnaBridge 189:f392fc9709a3 1494 * This parameter can be one of the following values:
AnnaBridge 189:f392fc9709a3 1495 * @arg @ref RCC_MCODIV_1 No division applied on MCO clock source
AnnaBridge 189:f392fc9709a3 1496 */
AnnaBridge 189:f392fc9709a3 1497 #endif
AnnaBridge 189:f392fc9709a3 1498 #if defined(RCC_CFGR_MCOPRE)
AnnaBridge 189:f392fc9709a3 1499 #define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \
AnnaBridge 189:f392fc9709a3 1500 MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO | RCC_CFGR_MCOPRE), ((__MCOCLKSOURCE__) | (__MCODIV__)))
AnnaBridge 189:f392fc9709a3 1501 #else
AnnaBridge 189:f392fc9709a3 1502
AnnaBridge 189:f392fc9709a3 1503 #define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \
AnnaBridge 189:f392fc9709a3 1504 MODIFY_REG(RCC->CFGR, RCC_CFGR_MCO, (__MCOCLKSOURCE__))
AnnaBridge 189:f392fc9709a3 1505
AnnaBridge 189:f392fc9709a3 1506 #endif
AnnaBridge 189:f392fc9709a3 1507
AnnaBridge 189:f392fc9709a3 1508 /**
AnnaBridge 189:f392fc9709a3 1509 * @}
AnnaBridge 189:f392fc9709a3 1510 */
AnnaBridge 189:f392fc9709a3 1511
AnnaBridge 189:f392fc9709a3 1512 /** @defgroup RCC_RTC_Clock_Configuration RCC RTC Clock Configuration
AnnaBridge 189:f392fc9709a3 1513 * @{
AnnaBridge 189:f392fc9709a3 1514 */
AnnaBridge 189:f392fc9709a3 1515
AnnaBridge 189:f392fc9709a3 1516 /** @brief Macro to configure the RTC clock (RTCCLK).
AnnaBridge 189:f392fc9709a3 1517 * @note As the RTC clock configuration bits are in the Backup domain and write
AnnaBridge 189:f392fc9709a3 1518 * access is denied to this domain after reset, you have to enable write
AnnaBridge 189:f392fc9709a3 1519 * access using the Power Backup Access macro before to configure
AnnaBridge 189:f392fc9709a3 1520 * the RTC clock source (to be done once after reset).
AnnaBridge 189:f392fc9709a3 1521 * @note Once the RTC clock is configured it cannot be changed unless the
AnnaBridge 189:f392fc9709a3 1522 * Backup domain is reset using @ref __HAL_RCC_BACKUPRESET_FORCE() macro, or by
AnnaBridge 189:f392fc9709a3 1523 * a Power On Reset (POR).
AnnaBridge 189:f392fc9709a3 1524 *
AnnaBridge 189:f392fc9709a3 1525 * @param __RTC_CLKSOURCE__ specifies the RTC clock source.
AnnaBridge 189:f392fc9709a3 1526 * This parameter can be one of the following values:
AnnaBridge 189:f392fc9709a3 1527 * @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock
AnnaBridge 189:f392fc9709a3 1528 * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock
AnnaBridge 189:f392fc9709a3 1529 * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock
AnnaBridge 189:f392fc9709a3 1530 * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV32 HSE clock divided by 32
AnnaBridge 189:f392fc9709a3 1531 * @note If the LSE or LSI is used as RTC clock source, the RTC continues to
AnnaBridge 189:f392fc9709a3 1532 * work in STOP and STANDBY modes, and can be used as wakeup source.
AnnaBridge 189:f392fc9709a3 1533 * However, when the LSI clock and HSE clock divided by 32 is used as RTC clock source,
AnnaBridge 189:f392fc9709a3 1534 * the RTC cannot be used in STOP and STANDBY modes.
AnnaBridge 189:f392fc9709a3 1535 * @note The system must always be configured so as to get a PCLK frequency greater than or
AnnaBridge 189:f392fc9709a3 1536 * equal to the RTCCLK frequency for a proper operation of the RTC.
AnnaBridge 189:f392fc9709a3 1537 */
AnnaBridge 189:f392fc9709a3 1538 #define __HAL_RCC_RTC_CONFIG(__RTC_CLKSOURCE__) MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, (__RTC_CLKSOURCE__))
AnnaBridge 189:f392fc9709a3 1539
AnnaBridge 189:f392fc9709a3 1540 /** @brief Macro to get the RTC clock source.
AnnaBridge 189:f392fc9709a3 1541 * @retval The clock source can be one of the following values:
AnnaBridge 189:f392fc9709a3 1542 * @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock
AnnaBridge 189:f392fc9709a3 1543 * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock
AnnaBridge 189:f392fc9709a3 1544 * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock
AnnaBridge 189:f392fc9709a3 1545 * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV32 HSE clock divided by 32
AnnaBridge 189:f392fc9709a3 1546 */
AnnaBridge 189:f392fc9709a3 1547 #define __HAL_RCC_GET_RTC_SOURCE() (READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL))
AnnaBridge 189:f392fc9709a3 1548
AnnaBridge 189:f392fc9709a3 1549 /** @brief Macro to enable the the RTC clock.
AnnaBridge 189:f392fc9709a3 1550 * @note These macros must be used only after the RTC clock source was selected.
AnnaBridge 189:f392fc9709a3 1551 */
AnnaBridge 189:f392fc9709a3 1552 #define __HAL_RCC_RTC_ENABLE() (*(__IO uint32_t *) RCC_BDCR_RTCEN_BB = ENABLE)
AnnaBridge 189:f392fc9709a3 1553
AnnaBridge 189:f392fc9709a3 1554 /** @brief Macro to disable the the RTC clock.
AnnaBridge 189:f392fc9709a3 1555 * @note These macros must be used only after the RTC clock source was selected.
AnnaBridge 189:f392fc9709a3 1556 */
AnnaBridge 189:f392fc9709a3 1557 #define __HAL_RCC_RTC_DISABLE() (*(__IO uint32_t *) RCC_BDCR_RTCEN_BB = DISABLE)
AnnaBridge 189:f392fc9709a3 1558
AnnaBridge 189:f392fc9709a3 1559 /** @brief Macro to force the Backup domain reset.
AnnaBridge 189:f392fc9709a3 1560 * @note This function resets the RTC peripheral (including the backup registers)
AnnaBridge 189:f392fc9709a3 1561 * and the RTC clock source selection in RCC_BDCR register.
AnnaBridge 189:f392fc9709a3 1562 */
AnnaBridge 189:f392fc9709a3 1563 #define __HAL_RCC_BACKUPRESET_FORCE() (*(__IO uint32_t *) RCC_BDCR_BDRST_BB = ENABLE)
AnnaBridge 189:f392fc9709a3 1564
AnnaBridge 189:f392fc9709a3 1565 /** @brief Macros to release the Backup domain reset.
AnnaBridge 189:f392fc9709a3 1566 */
AnnaBridge 189:f392fc9709a3 1567 #define __HAL_RCC_BACKUPRESET_RELEASE() (*(__IO uint32_t *) RCC_BDCR_BDRST_BB = DISABLE)
AnnaBridge 189:f392fc9709a3 1568
AnnaBridge 189:f392fc9709a3 1569 /**
AnnaBridge 189:f392fc9709a3 1570 * @}
AnnaBridge 189:f392fc9709a3 1571 */
AnnaBridge 189:f392fc9709a3 1572
AnnaBridge 189:f392fc9709a3 1573 /** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management
AnnaBridge 189:f392fc9709a3 1574 * @brief macros to manage the specified RCC Flags and interrupts.
AnnaBridge 189:f392fc9709a3 1575 * @{
AnnaBridge 189:f392fc9709a3 1576 */
AnnaBridge 189:f392fc9709a3 1577
AnnaBridge 189:f392fc9709a3 1578 /** @brief Enable RCC interrupt.
AnnaBridge 189:f392fc9709a3 1579 * @param __INTERRUPT__ specifies the RCC interrupt sources to be enabled.
AnnaBridge 189:f392fc9709a3 1580 * This parameter can be any combination of the following values:
AnnaBridge 189:f392fc9709a3 1581 * @arg @ref RCC_IT_LSIRDY LSI ready interrupt
AnnaBridge 189:f392fc9709a3 1582 * @arg @ref RCC_IT_LSERDY LSE ready interrupt
AnnaBridge 189:f392fc9709a3 1583 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt
AnnaBridge 189:f392fc9709a3 1584 * @arg @ref RCC_IT_HSERDY HSE ready interrupt
AnnaBridge 189:f392fc9709a3 1585 * @arg @ref RCC_IT_PLLRDY main PLL ready interrupt
AnnaBridge 189:f392fc9709a3 1586 */
AnnaBridge 189:f392fc9709a3 1587 #define __HAL_RCC_ENABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS |= (__INTERRUPT__))
AnnaBridge 189:f392fc9709a3 1588
AnnaBridge 189:f392fc9709a3 1589 /** @brief Disable RCC interrupt.
AnnaBridge 189:f392fc9709a3 1590 * @param __INTERRUPT__ specifies the RCC interrupt sources to be disabled.
AnnaBridge 189:f392fc9709a3 1591 * This parameter can be any combination of the following values:
AnnaBridge 189:f392fc9709a3 1592 * @arg @ref RCC_IT_LSIRDY LSI ready interrupt
AnnaBridge 189:f392fc9709a3 1593 * @arg @ref RCC_IT_LSERDY LSE ready interrupt
AnnaBridge 189:f392fc9709a3 1594 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt
AnnaBridge 189:f392fc9709a3 1595 * @arg @ref RCC_IT_HSERDY HSE ready interrupt
AnnaBridge 189:f392fc9709a3 1596 * @arg @ref RCC_IT_PLLRDY main PLL ready interrupt
AnnaBridge 189:f392fc9709a3 1597 */
AnnaBridge 189:f392fc9709a3 1598 #define __HAL_RCC_DISABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS &= (uint8_t)(~(__INTERRUPT__)))
AnnaBridge 189:f392fc9709a3 1599
AnnaBridge 189:f392fc9709a3 1600 /** @brief Clear the RCC's interrupt pending bits.
AnnaBridge 189:f392fc9709a3 1601 * @param __INTERRUPT__ specifies the interrupt pending bit to clear.
AnnaBridge 189:f392fc9709a3 1602 * This parameter can be any combination of the following values:
AnnaBridge 189:f392fc9709a3 1603 * @arg @ref RCC_IT_LSIRDY LSI ready interrupt.
AnnaBridge 189:f392fc9709a3 1604 * @arg @ref RCC_IT_LSERDY LSE ready interrupt.
AnnaBridge 189:f392fc9709a3 1605 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt.
AnnaBridge 189:f392fc9709a3 1606 * @arg @ref RCC_IT_HSERDY HSE ready interrupt.
AnnaBridge 189:f392fc9709a3 1607 * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt.
AnnaBridge 189:f392fc9709a3 1608 * @arg @ref RCC_IT_CSS Clock Security System interrupt
AnnaBridge 189:f392fc9709a3 1609 */
AnnaBridge 189:f392fc9709a3 1610 #define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE2_ADDRESS = (__INTERRUPT__))
AnnaBridge 189:f392fc9709a3 1611
AnnaBridge 189:f392fc9709a3 1612 /** @brief Check the RCC's interrupt has occurred or not.
AnnaBridge 189:f392fc9709a3 1613 * @param __INTERRUPT__ specifies the RCC interrupt source to check.
AnnaBridge 189:f392fc9709a3 1614 * This parameter can be one of the following values:
AnnaBridge 189:f392fc9709a3 1615 * @arg @ref RCC_IT_LSIRDY LSI ready interrupt.
AnnaBridge 189:f392fc9709a3 1616 * @arg @ref RCC_IT_LSERDY LSE ready interrupt.
AnnaBridge 189:f392fc9709a3 1617 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt.
AnnaBridge 189:f392fc9709a3 1618 * @arg @ref RCC_IT_HSERDY HSE ready interrupt.
AnnaBridge 189:f392fc9709a3 1619 * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt.
AnnaBridge 189:f392fc9709a3 1620 * @arg @ref RCC_IT_CSS Clock Security System interrupt
AnnaBridge 189:f392fc9709a3 1621 * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
AnnaBridge 189:f392fc9709a3 1622 */
AnnaBridge 189:f392fc9709a3 1623 #define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIR & (__INTERRUPT__)) == (__INTERRUPT__))
AnnaBridge 189:f392fc9709a3 1624
AnnaBridge 189:f392fc9709a3 1625 /** @brief Set RMVF bit to clear the reset flags.
AnnaBridge 189:f392fc9709a3 1626 * The reset flags are RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST,
AnnaBridge 189:f392fc9709a3 1627 * RCC_FLAG_OBLRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST
AnnaBridge 189:f392fc9709a3 1628 */
AnnaBridge 189:f392fc9709a3 1629 #define __HAL_RCC_CLEAR_RESET_FLAGS() (*(__IO uint32_t *)RCC_CSR_RMVF_BB = ENABLE)
AnnaBridge 189:f392fc9709a3 1630
AnnaBridge 189:f392fc9709a3 1631 /** @brief Check RCC flag is set or not.
AnnaBridge 189:f392fc9709a3 1632 * @param __FLAG__ specifies the flag to check.
AnnaBridge 189:f392fc9709a3 1633 * This parameter can be one of the following values:
AnnaBridge 189:f392fc9709a3 1634 * @arg @ref RCC_FLAG_HSIRDY HSI oscillator clock ready.
AnnaBridge 189:f392fc9709a3 1635 * @arg @ref RCC_FLAG_HSERDY HSE oscillator clock ready.
AnnaBridge 189:f392fc9709a3 1636 * @arg @ref RCC_FLAG_PLLRDY Main PLL clock ready.
AnnaBridge 189:f392fc9709a3 1637 * @arg @ref RCC_FLAG_LSERDY LSE oscillator clock ready.
AnnaBridge 189:f392fc9709a3 1638 * @arg @ref RCC_FLAG_LSIRDY LSI oscillator clock ready.
AnnaBridge 189:f392fc9709a3 1639 * @arg @ref RCC_FLAG_OBLRST Option Byte Load reset
AnnaBridge 189:f392fc9709a3 1640 * @arg @ref RCC_FLAG_PINRST Pin reset.
AnnaBridge 189:f392fc9709a3 1641 * @arg @ref RCC_FLAG_PORRST POR/PDR reset.
AnnaBridge 189:f392fc9709a3 1642 * @arg @ref RCC_FLAG_SFTRST Software reset.
AnnaBridge 189:f392fc9709a3 1643 * @arg @ref RCC_FLAG_IWDGRST Independent Watchdog reset.
AnnaBridge 189:f392fc9709a3 1644 * @arg @ref RCC_FLAG_WWDGRST Window Watchdog reset.
AnnaBridge 189:f392fc9709a3 1645 * @arg @ref RCC_FLAG_LPWRRST Low Power reset.
AnnaBridge 189:f392fc9709a3 1646 @if defined(STM32F301x8)
AnnaBridge 189:f392fc9709a3 1647 * @arg @ref RCC_FLAG_V18PWRRST Reset flag of the 1.8 V domain
AnnaBridge 189:f392fc9709a3 1648 @endif
AnnaBridge 189:f392fc9709a3 1649 @if defined(STM32F302x8)
AnnaBridge 189:f392fc9709a3 1650 * @arg @ref RCC_FLAG_V18PWRRST Reset flag of the 1.8 V domain
AnnaBridge 189:f392fc9709a3 1651 @endif
AnnaBridge 189:f392fc9709a3 1652 @if defined(STM32F302xC)
AnnaBridge 189:f392fc9709a3 1653 * @arg @ref RCC_FLAG_V18PWRRST Reset flag of the 1.8 V domain
AnnaBridge 189:f392fc9709a3 1654 * @arg @ref RCC_FLAG_MCO Microcontroller Clock Output
AnnaBridge 189:f392fc9709a3 1655 @endif
AnnaBridge 189:f392fc9709a3 1656 @if defined(STM32F302xE)
AnnaBridge 189:f392fc9709a3 1657 * @arg @ref RCC_FLAG_V18PWRRST Reset flag of the 1.8 V domain
AnnaBridge 189:f392fc9709a3 1658 @endif
AnnaBridge 189:f392fc9709a3 1659 @if defined(STM32F303x8)
AnnaBridge 189:f392fc9709a3 1660 * @arg @ref RCC_FLAG_V18PWRRST Reset flag of the 1.8 V domain
AnnaBridge 189:f392fc9709a3 1661 @endif
AnnaBridge 189:f392fc9709a3 1662 @if defined(STM32F303xC)
AnnaBridge 189:f392fc9709a3 1663 * @arg @ref RCC_FLAG_V18PWRRST Reset flag of the 1.8 V domain
AnnaBridge 189:f392fc9709a3 1664 * @arg @ref RCC_FLAG_MCO Microcontroller Clock Output
AnnaBridge 189:f392fc9709a3 1665 @endif
AnnaBridge 189:f392fc9709a3 1666 @if defined(STM32F303xE)
AnnaBridge 189:f392fc9709a3 1667 * @arg @ref RCC_FLAG_V18PWRRST Reset flag of the 1.8 V domain
AnnaBridge 189:f392fc9709a3 1668 @endif
AnnaBridge 189:f392fc9709a3 1669 @if defined(STM32F334x8)
AnnaBridge 189:f392fc9709a3 1670 * @arg @ref RCC_FLAG_V18PWRRST Reset flag of the 1.8 V domain
AnnaBridge 189:f392fc9709a3 1671 @endif
AnnaBridge 189:f392fc9709a3 1672 @if defined(STM32F358xx)
AnnaBridge 189:f392fc9709a3 1673 * @arg @ref RCC_FLAG_MCO Microcontroller Clock Output
AnnaBridge 189:f392fc9709a3 1674 @endif
AnnaBridge 189:f392fc9709a3 1675 @if defined(STM32F373xC)
AnnaBridge 189:f392fc9709a3 1676 * @arg @ref RCC_FLAG_V18PWRRST Reset flag of the 1.8 V domain
AnnaBridge 189:f392fc9709a3 1677 @endif
AnnaBridge 189:f392fc9709a3 1678 * @retval The new state of __FLAG__ (TRUE or FALSE).
AnnaBridge 189:f392fc9709a3 1679 */
AnnaBridge 189:f392fc9709a3 1680 #define __HAL_RCC_GET_FLAG(__FLAG__) (((((__FLAG__) >> 5U) == CR_REG_INDEX) ? RCC->CR : \
AnnaBridge 189:f392fc9709a3 1681 (((__FLAG__) >> 5U) == BDCR_REG_INDEX)? RCC->BDCR : \
AnnaBridge 189:f392fc9709a3 1682 (((__FLAG__) >> 5U) == CFGR_REG_INDEX)? RCC->CFGR : \
AnnaBridge 189:f392fc9709a3 1683 RCC->CSR) & (1U << ((__FLAG__) & RCC_FLAG_MASK)))
AnnaBridge 189:f392fc9709a3 1684
AnnaBridge 189:f392fc9709a3 1685 /**
AnnaBridge 189:f392fc9709a3 1686 * @}
AnnaBridge 189:f392fc9709a3 1687 */
AnnaBridge 189:f392fc9709a3 1688
AnnaBridge 189:f392fc9709a3 1689 /**
AnnaBridge 189:f392fc9709a3 1690 * @}
AnnaBridge 189:f392fc9709a3 1691 */
AnnaBridge 189:f392fc9709a3 1692
AnnaBridge 189:f392fc9709a3 1693 /* Include RCC HAL Extension module */
AnnaBridge 189:f392fc9709a3 1694 #include "stm32f3xx_hal_rcc_ex.h"
AnnaBridge 189:f392fc9709a3 1695
AnnaBridge 189:f392fc9709a3 1696 /* Exported functions --------------------------------------------------------*/
AnnaBridge 189:f392fc9709a3 1697 /** @addtogroup RCC_Exported_Functions
AnnaBridge 189:f392fc9709a3 1698 * @{
AnnaBridge 189:f392fc9709a3 1699 */
AnnaBridge 189:f392fc9709a3 1700
AnnaBridge 189:f392fc9709a3 1701 /** @addtogroup RCC_Exported_Functions_Group1
AnnaBridge 189:f392fc9709a3 1702 * @{
AnnaBridge 189:f392fc9709a3 1703 */
AnnaBridge 189:f392fc9709a3 1704
AnnaBridge 189:f392fc9709a3 1705 /* Initialization and de-initialization functions ******************************/
AnnaBridge 189:f392fc9709a3 1706 void HAL_RCC_DeInit(void);
AnnaBridge 189:f392fc9709a3 1707 HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
AnnaBridge 189:f392fc9709a3 1708 HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);
AnnaBridge 189:f392fc9709a3 1709
AnnaBridge 189:f392fc9709a3 1710 /**
AnnaBridge 189:f392fc9709a3 1711 * @}
AnnaBridge 189:f392fc9709a3 1712 */
AnnaBridge 189:f392fc9709a3 1713
AnnaBridge 189:f392fc9709a3 1714 /** @addtogroup RCC_Exported_Functions_Group2
AnnaBridge 189:f392fc9709a3 1715 * @{
AnnaBridge 189:f392fc9709a3 1716 */
AnnaBridge 189:f392fc9709a3 1717
AnnaBridge 189:f392fc9709a3 1718 /* Peripheral Control functions ************************************************/
AnnaBridge 189:f392fc9709a3 1719 void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);
AnnaBridge 189:f392fc9709a3 1720 void HAL_RCC_EnableCSS(void);
AnnaBridge 189:f392fc9709a3 1721 /* CSS NMI IRQ handler */
AnnaBridge 189:f392fc9709a3 1722 void HAL_RCC_NMI_IRQHandler(void);
AnnaBridge 189:f392fc9709a3 1723 /* User Callbacks in non blocking mode (IT mode) */
AnnaBridge 189:f392fc9709a3 1724 void HAL_RCC_CSSCallback(void);
AnnaBridge 189:f392fc9709a3 1725 void HAL_RCC_DisableCSS(void);
AnnaBridge 189:f392fc9709a3 1726 uint32_t HAL_RCC_GetSysClockFreq(void);
AnnaBridge 189:f392fc9709a3 1727 uint32_t HAL_RCC_GetHCLKFreq(void);
AnnaBridge 189:f392fc9709a3 1728 uint32_t HAL_RCC_GetPCLK1Freq(void);
AnnaBridge 189:f392fc9709a3 1729 uint32_t HAL_RCC_GetPCLK2Freq(void);
AnnaBridge 189:f392fc9709a3 1730 void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
AnnaBridge 189:f392fc9709a3 1731 void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency);
AnnaBridge 189:f392fc9709a3 1732
AnnaBridge 189:f392fc9709a3 1733 /**
AnnaBridge 189:f392fc9709a3 1734 * @}
AnnaBridge 189:f392fc9709a3 1735 */
AnnaBridge 189:f392fc9709a3 1736
AnnaBridge 189:f392fc9709a3 1737 /**
AnnaBridge 189:f392fc9709a3 1738 * @}
AnnaBridge 189:f392fc9709a3 1739 */
AnnaBridge 189:f392fc9709a3 1740
AnnaBridge 189:f392fc9709a3 1741 /**
AnnaBridge 189:f392fc9709a3 1742 * @}
AnnaBridge 189:f392fc9709a3 1743 */
AnnaBridge 189:f392fc9709a3 1744
AnnaBridge 189:f392fc9709a3 1745 /**
AnnaBridge 189:f392fc9709a3 1746 * @}
AnnaBridge 189:f392fc9709a3 1747 */
AnnaBridge 189:f392fc9709a3 1748
AnnaBridge 189:f392fc9709a3 1749 #ifdef __cplusplus
AnnaBridge 189:f392fc9709a3 1750 }
AnnaBridge 189:f392fc9709a3 1751 #endif
AnnaBridge 189:f392fc9709a3 1752
AnnaBridge 189:f392fc9709a3 1753 #endif /* __STM32F3xx_HAL_RCC_H */
AnnaBridge 189:f392fc9709a3 1754
AnnaBridge 189:f392fc9709a3 1755 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
AnnaBridge 189:f392fc9709a3 1756