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cmsis/BUILD/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_ARM_MICRO/stm32f1xx_hal_dma.h@189:f392fc9709a3, 2019-02-20 (annotated)
- Committer:
- AnnaBridge
- Date:
- Wed Feb 20 22:31:08 2019 +0000
- Revision:
- 189:f392fc9709a3
mbed library release version 165
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| AnnaBridge | 189:f392fc9709a3 | 1 | /** |
| AnnaBridge | 189:f392fc9709a3 | 2 | ****************************************************************************** |
| AnnaBridge | 189:f392fc9709a3 | 3 | * @file stm32f1xx_hal_dma.h |
| AnnaBridge | 189:f392fc9709a3 | 4 | * @author MCD Application Team |
| AnnaBridge | 189:f392fc9709a3 | 5 | * @brief Header file of DMA HAL module. |
| AnnaBridge | 189:f392fc9709a3 | 6 | ****************************************************************************** |
| AnnaBridge | 189:f392fc9709a3 | 7 | * @attention |
| AnnaBridge | 189:f392fc9709a3 | 8 | * |
| AnnaBridge | 189:f392fc9709a3 | 9 | * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> |
| AnnaBridge | 189:f392fc9709a3 | 10 | * |
| AnnaBridge | 189:f392fc9709a3 | 11 | * Redistribution and use in source and binary forms, with or without modification, |
| AnnaBridge | 189:f392fc9709a3 | 12 | * are permitted provided that the following conditions are met: |
| AnnaBridge | 189:f392fc9709a3 | 13 | * 1. Redistributions of source code must retain the above copyright notice, |
| AnnaBridge | 189:f392fc9709a3 | 14 | * this list of conditions and the following disclaimer. |
| AnnaBridge | 189:f392fc9709a3 | 15 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| AnnaBridge | 189:f392fc9709a3 | 16 | * this list of conditions and the following disclaimer in the documentation |
| AnnaBridge | 189:f392fc9709a3 | 17 | * and/or other materials provided with the distribution. |
| AnnaBridge | 189:f392fc9709a3 | 18 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| AnnaBridge | 189:f392fc9709a3 | 19 | * may be used to endorse or promote products derived from this software |
| AnnaBridge | 189:f392fc9709a3 | 20 | * without specific prior written permission. |
| AnnaBridge | 189:f392fc9709a3 | 21 | * |
| AnnaBridge | 189:f392fc9709a3 | 22 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| AnnaBridge | 189:f392fc9709a3 | 23 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| AnnaBridge | 189:f392fc9709a3 | 24 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| AnnaBridge | 189:f392fc9709a3 | 25 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| AnnaBridge | 189:f392fc9709a3 | 26 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| AnnaBridge | 189:f392fc9709a3 | 27 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| AnnaBridge | 189:f392fc9709a3 | 28 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| AnnaBridge | 189:f392fc9709a3 | 29 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| AnnaBridge | 189:f392fc9709a3 | 30 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| AnnaBridge | 189:f392fc9709a3 | 31 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| AnnaBridge | 189:f392fc9709a3 | 32 | * |
| AnnaBridge | 189:f392fc9709a3 | 33 | ****************************************************************************** |
| AnnaBridge | 189:f392fc9709a3 | 34 | */ |
| AnnaBridge | 189:f392fc9709a3 | 35 | |
| AnnaBridge | 189:f392fc9709a3 | 36 | /* Define to prevent recursive inclusion -------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 37 | #ifndef __STM32F1xx_HAL_DMA_H |
| AnnaBridge | 189:f392fc9709a3 | 38 | #define __STM32F1xx_HAL_DMA_H |
| AnnaBridge | 189:f392fc9709a3 | 39 | |
| AnnaBridge | 189:f392fc9709a3 | 40 | #ifdef __cplusplus |
| AnnaBridge | 189:f392fc9709a3 | 41 | extern "C" { |
| AnnaBridge | 189:f392fc9709a3 | 42 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 43 | |
| AnnaBridge | 189:f392fc9709a3 | 44 | /* Includes ------------------------------------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 45 | #include "stm32f1xx_hal_def.h" |
| AnnaBridge | 189:f392fc9709a3 | 46 | |
| AnnaBridge | 189:f392fc9709a3 | 47 | /** @addtogroup STM32F1xx_HAL_Driver |
| AnnaBridge | 189:f392fc9709a3 | 48 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 49 | */ |
| AnnaBridge | 189:f392fc9709a3 | 50 | |
| AnnaBridge | 189:f392fc9709a3 | 51 | /** @addtogroup DMA |
| AnnaBridge | 189:f392fc9709a3 | 52 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 53 | */ |
| AnnaBridge | 189:f392fc9709a3 | 54 | |
| AnnaBridge | 189:f392fc9709a3 | 55 | /* Exported types ------------------------------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 56 | |
| AnnaBridge | 189:f392fc9709a3 | 57 | /** @defgroup DMA_Exported_Types DMA Exported Types |
| AnnaBridge | 189:f392fc9709a3 | 58 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 59 | */ |
| AnnaBridge | 189:f392fc9709a3 | 60 | |
| AnnaBridge | 189:f392fc9709a3 | 61 | /** |
| AnnaBridge | 189:f392fc9709a3 | 62 | * @brief DMA Configuration Structure definition |
| AnnaBridge | 189:f392fc9709a3 | 63 | */ |
| AnnaBridge | 189:f392fc9709a3 | 64 | typedef struct |
| AnnaBridge | 189:f392fc9709a3 | 65 | { |
| AnnaBridge | 189:f392fc9709a3 | 66 | uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral, |
| AnnaBridge | 189:f392fc9709a3 | 67 | from memory to memory or from peripheral to memory. |
| AnnaBridge | 189:f392fc9709a3 | 68 | This parameter can be a value of @ref DMA_Data_transfer_direction */ |
| AnnaBridge | 189:f392fc9709a3 | 69 | |
| AnnaBridge | 189:f392fc9709a3 | 70 | uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not. |
| AnnaBridge | 189:f392fc9709a3 | 71 | This parameter can be a value of @ref DMA_Peripheral_incremented_mode */ |
| AnnaBridge | 189:f392fc9709a3 | 72 | |
| AnnaBridge | 189:f392fc9709a3 | 73 | uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not. |
| AnnaBridge | 189:f392fc9709a3 | 74 | This parameter can be a value of @ref DMA_Memory_incremented_mode */ |
| AnnaBridge | 189:f392fc9709a3 | 75 | |
| AnnaBridge | 189:f392fc9709a3 | 76 | uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width. |
| AnnaBridge | 189:f392fc9709a3 | 77 | This parameter can be a value of @ref DMA_Peripheral_data_size */ |
| AnnaBridge | 189:f392fc9709a3 | 78 | |
| AnnaBridge | 189:f392fc9709a3 | 79 | uint32_t MemDataAlignment; /*!< Specifies the Memory data width. |
| AnnaBridge | 189:f392fc9709a3 | 80 | This parameter can be a value of @ref DMA_Memory_data_size */ |
| AnnaBridge | 189:f392fc9709a3 | 81 | |
| AnnaBridge | 189:f392fc9709a3 | 82 | uint32_t Mode; /*!< Specifies the operation mode of the DMAy Channelx. |
| AnnaBridge | 189:f392fc9709a3 | 83 | This parameter can be a value of @ref DMA_mode |
| AnnaBridge | 189:f392fc9709a3 | 84 | @note The circular buffer mode cannot be used if the memory-to-memory |
| AnnaBridge | 189:f392fc9709a3 | 85 | data transfer is configured on the selected Channel */ |
| AnnaBridge | 189:f392fc9709a3 | 86 | |
| AnnaBridge | 189:f392fc9709a3 | 87 | uint32_t Priority; /*!< Specifies the software priority for the DMAy Channelx. |
| AnnaBridge | 189:f392fc9709a3 | 88 | This parameter can be a value of @ref DMA_Priority_level */ |
| AnnaBridge | 189:f392fc9709a3 | 89 | } DMA_InitTypeDef; |
| AnnaBridge | 189:f392fc9709a3 | 90 | |
| AnnaBridge | 189:f392fc9709a3 | 91 | /** |
| AnnaBridge | 189:f392fc9709a3 | 92 | * @brief HAL DMA State structures definition |
| AnnaBridge | 189:f392fc9709a3 | 93 | */ |
| AnnaBridge | 189:f392fc9709a3 | 94 | typedef enum |
| AnnaBridge | 189:f392fc9709a3 | 95 | { |
| AnnaBridge | 189:f392fc9709a3 | 96 | HAL_DMA_STATE_RESET = 0x00U, /*!< DMA not yet initialized or disabled */ |
| AnnaBridge | 189:f392fc9709a3 | 97 | HAL_DMA_STATE_READY = 0x01U, /*!< DMA initialized and ready for use */ |
| AnnaBridge | 189:f392fc9709a3 | 98 | HAL_DMA_STATE_BUSY = 0x02U, /*!< DMA process is ongoing */ |
| AnnaBridge | 189:f392fc9709a3 | 99 | HAL_DMA_STATE_TIMEOUT = 0x03U /*!< DMA timeout state */ |
| AnnaBridge | 189:f392fc9709a3 | 100 | }HAL_DMA_StateTypeDef; |
| AnnaBridge | 189:f392fc9709a3 | 101 | |
| AnnaBridge | 189:f392fc9709a3 | 102 | /** |
| AnnaBridge | 189:f392fc9709a3 | 103 | * @brief HAL DMA Error Code structure definition |
| AnnaBridge | 189:f392fc9709a3 | 104 | */ |
| AnnaBridge | 189:f392fc9709a3 | 105 | typedef enum |
| AnnaBridge | 189:f392fc9709a3 | 106 | { |
| AnnaBridge | 189:f392fc9709a3 | 107 | HAL_DMA_FULL_TRANSFER = 0x00U, /*!< Full transfer */ |
| AnnaBridge | 189:f392fc9709a3 | 108 | HAL_DMA_HALF_TRANSFER = 0x01U /*!< Half Transfer */ |
| AnnaBridge | 189:f392fc9709a3 | 109 | }HAL_DMA_LevelCompleteTypeDef; |
| AnnaBridge | 189:f392fc9709a3 | 110 | |
| AnnaBridge | 189:f392fc9709a3 | 111 | /** |
| AnnaBridge | 189:f392fc9709a3 | 112 | * @brief HAL DMA Callback ID structure definition |
| AnnaBridge | 189:f392fc9709a3 | 113 | */ |
| AnnaBridge | 189:f392fc9709a3 | 114 | typedef enum |
| AnnaBridge | 189:f392fc9709a3 | 115 | { |
| AnnaBridge | 189:f392fc9709a3 | 116 | HAL_DMA_XFER_CPLT_CB_ID = 0x00U, /*!< Full transfer */ |
| AnnaBridge | 189:f392fc9709a3 | 117 | HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, /*!< Half transfer */ |
| AnnaBridge | 189:f392fc9709a3 | 118 | HAL_DMA_XFER_ERROR_CB_ID = 0x02U, /*!< Error */ |
| AnnaBridge | 189:f392fc9709a3 | 119 | HAL_DMA_XFER_ABORT_CB_ID = 0x03U, /*!< Abort */ |
| AnnaBridge | 189:f392fc9709a3 | 120 | HAL_DMA_XFER_ALL_CB_ID = 0x04U /*!< All */ |
| AnnaBridge | 189:f392fc9709a3 | 121 | |
| AnnaBridge | 189:f392fc9709a3 | 122 | }HAL_DMA_CallbackIDTypeDef; |
| AnnaBridge | 189:f392fc9709a3 | 123 | |
| AnnaBridge | 189:f392fc9709a3 | 124 | /** |
| AnnaBridge | 189:f392fc9709a3 | 125 | * @brief DMA handle Structure definition |
| AnnaBridge | 189:f392fc9709a3 | 126 | */ |
| AnnaBridge | 189:f392fc9709a3 | 127 | typedef struct __DMA_HandleTypeDef |
| AnnaBridge | 189:f392fc9709a3 | 128 | { |
| AnnaBridge | 189:f392fc9709a3 | 129 | DMA_Channel_TypeDef *Instance; /*!< Register base address */ |
| AnnaBridge | 189:f392fc9709a3 | 130 | |
| AnnaBridge | 189:f392fc9709a3 | 131 | DMA_InitTypeDef Init; /*!< DMA communication parameters */ |
| AnnaBridge | 189:f392fc9709a3 | 132 | |
| AnnaBridge | 189:f392fc9709a3 | 133 | HAL_LockTypeDef Lock; /*!< DMA locking object */ |
| AnnaBridge | 189:f392fc9709a3 | 134 | |
| AnnaBridge | 189:f392fc9709a3 | 135 | HAL_DMA_StateTypeDef State; /*!< DMA transfer state */ |
| AnnaBridge | 189:f392fc9709a3 | 136 | |
| AnnaBridge | 189:f392fc9709a3 | 137 | void *Parent; /*!< Parent object state */ |
| AnnaBridge | 189:f392fc9709a3 | 138 | |
| AnnaBridge | 189:f392fc9709a3 | 139 | void (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */ |
| AnnaBridge | 189:f392fc9709a3 | 140 | |
| AnnaBridge | 189:f392fc9709a3 | 141 | void (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */ |
| AnnaBridge | 189:f392fc9709a3 | 142 | |
| AnnaBridge | 189:f392fc9709a3 | 143 | void (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */ |
| AnnaBridge | 189:f392fc9709a3 | 144 | |
| AnnaBridge | 189:f392fc9709a3 | 145 | void (* XferAbortCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer abort callback */ |
| AnnaBridge | 189:f392fc9709a3 | 146 | |
| AnnaBridge | 189:f392fc9709a3 | 147 | __IO uint32_t ErrorCode; /*!< DMA Error code */ |
| AnnaBridge | 189:f392fc9709a3 | 148 | |
| AnnaBridge | 189:f392fc9709a3 | 149 | DMA_TypeDef *DmaBaseAddress; /*!< DMA Channel Base Address */ |
| AnnaBridge | 189:f392fc9709a3 | 150 | |
| AnnaBridge | 189:f392fc9709a3 | 151 | uint32_t ChannelIndex; /*!< DMA Channel Index */ |
| AnnaBridge | 189:f392fc9709a3 | 152 | |
| AnnaBridge | 189:f392fc9709a3 | 153 | } DMA_HandleTypeDef; |
| AnnaBridge | 189:f392fc9709a3 | 154 | /** |
| AnnaBridge | 189:f392fc9709a3 | 155 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 156 | */ |
| AnnaBridge | 189:f392fc9709a3 | 157 | |
| AnnaBridge | 189:f392fc9709a3 | 158 | /* Exported constants --------------------------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 159 | |
| AnnaBridge | 189:f392fc9709a3 | 160 | /** @defgroup DMA_Exported_Constants DMA Exported Constants |
| AnnaBridge | 189:f392fc9709a3 | 161 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 162 | */ |
| AnnaBridge | 189:f392fc9709a3 | 163 | |
| AnnaBridge | 189:f392fc9709a3 | 164 | /** @defgroup DMA_Error_Code DMA Error Code |
| AnnaBridge | 189:f392fc9709a3 | 165 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 166 | */ |
| AnnaBridge | 189:f392fc9709a3 | 167 | #define HAL_DMA_ERROR_NONE 0x00000000U /*!< No error */ |
| AnnaBridge | 189:f392fc9709a3 | 168 | #define HAL_DMA_ERROR_TE 0x00000001U /*!< Transfer error */ |
| AnnaBridge | 189:f392fc9709a3 | 169 | #define HAL_DMA_ERROR_NO_XFER 0x00000004U /*!< no ongoing transfer */ |
| AnnaBridge | 189:f392fc9709a3 | 170 | #define HAL_DMA_ERROR_TIMEOUT 0x00000020U /*!< Timeout error */ |
| AnnaBridge | 189:f392fc9709a3 | 171 | #define HAL_DMA_ERROR_NOT_SUPPORTED 0x00000100U /*!< Not supported mode */ |
| AnnaBridge | 189:f392fc9709a3 | 172 | /** |
| AnnaBridge | 189:f392fc9709a3 | 173 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 174 | */ |
| AnnaBridge | 189:f392fc9709a3 | 175 | |
| AnnaBridge | 189:f392fc9709a3 | 176 | /** @defgroup DMA_Data_transfer_direction DMA Data transfer direction |
| AnnaBridge | 189:f392fc9709a3 | 177 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 178 | */ |
| AnnaBridge | 189:f392fc9709a3 | 179 | #define DMA_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */ |
| AnnaBridge | 189:f392fc9709a3 | 180 | #define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_CCR_DIR) /*!< Memory to peripheral direction */ |
| AnnaBridge | 189:f392fc9709a3 | 181 | #define DMA_MEMORY_TO_MEMORY ((uint32_t)DMA_CCR_MEM2MEM) /*!< Memory to memory direction */ |
| AnnaBridge | 189:f392fc9709a3 | 182 | |
| AnnaBridge | 189:f392fc9709a3 | 183 | /** |
| AnnaBridge | 189:f392fc9709a3 | 184 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 185 | */ |
| AnnaBridge | 189:f392fc9709a3 | 186 | |
| AnnaBridge | 189:f392fc9709a3 | 187 | /** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode |
| AnnaBridge | 189:f392fc9709a3 | 188 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 189 | */ |
| AnnaBridge | 189:f392fc9709a3 | 190 | #define DMA_PINC_ENABLE ((uint32_t)DMA_CCR_PINC) /*!< Peripheral increment mode Enable */ |
| AnnaBridge | 189:f392fc9709a3 | 191 | #define DMA_PINC_DISABLE 0x00000000U /*!< Peripheral increment mode Disable */ |
| AnnaBridge | 189:f392fc9709a3 | 192 | /** |
| AnnaBridge | 189:f392fc9709a3 | 193 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 194 | */ |
| AnnaBridge | 189:f392fc9709a3 | 195 | |
| AnnaBridge | 189:f392fc9709a3 | 196 | /** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode |
| AnnaBridge | 189:f392fc9709a3 | 197 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 198 | */ |
| AnnaBridge | 189:f392fc9709a3 | 199 | #define DMA_MINC_ENABLE ((uint32_t)DMA_CCR_MINC) /*!< Memory increment mode Enable */ |
| AnnaBridge | 189:f392fc9709a3 | 200 | #define DMA_MINC_DISABLE 0x00000000U /*!< Memory increment mode Disable */ |
| AnnaBridge | 189:f392fc9709a3 | 201 | /** |
| AnnaBridge | 189:f392fc9709a3 | 202 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 203 | */ |
| AnnaBridge | 189:f392fc9709a3 | 204 | |
| AnnaBridge | 189:f392fc9709a3 | 205 | /** @defgroup DMA_Peripheral_data_size DMA Peripheral data size |
| AnnaBridge | 189:f392fc9709a3 | 206 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 207 | */ |
| AnnaBridge | 189:f392fc9709a3 | 208 | #define DMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment: Byte */ |
| AnnaBridge | 189:f392fc9709a3 | 209 | #define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_PSIZE_0) /*!< Peripheral data alignment: HalfWord */ |
| AnnaBridge | 189:f392fc9709a3 | 210 | #define DMA_PDATAALIGN_WORD ((uint32_t)DMA_CCR_PSIZE_1) /*!< Peripheral data alignment: Word */ |
| AnnaBridge | 189:f392fc9709a3 | 211 | /** |
| AnnaBridge | 189:f392fc9709a3 | 212 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 213 | */ |
| AnnaBridge | 189:f392fc9709a3 | 214 | |
| AnnaBridge | 189:f392fc9709a3 | 215 | /** @defgroup DMA_Memory_data_size DMA Memory data size |
| AnnaBridge | 189:f392fc9709a3 | 216 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 217 | */ |
| AnnaBridge | 189:f392fc9709a3 | 218 | #define DMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment: Byte */ |
| AnnaBridge | 189:f392fc9709a3 | 219 | #define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_MSIZE_0) /*!< Memory data alignment: HalfWord */ |
| AnnaBridge | 189:f392fc9709a3 | 220 | #define DMA_MDATAALIGN_WORD ((uint32_t)DMA_CCR_MSIZE_1) /*!< Memory data alignment: Word */ |
| AnnaBridge | 189:f392fc9709a3 | 221 | /** |
| AnnaBridge | 189:f392fc9709a3 | 222 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 223 | */ |
| AnnaBridge | 189:f392fc9709a3 | 224 | |
| AnnaBridge | 189:f392fc9709a3 | 225 | /** @defgroup DMA_mode DMA mode |
| AnnaBridge | 189:f392fc9709a3 | 226 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 227 | */ |
| AnnaBridge | 189:f392fc9709a3 | 228 | #define DMA_NORMAL 0x00000000U /*!< Normal mode */ |
| AnnaBridge | 189:f392fc9709a3 | 229 | #define DMA_CIRCULAR ((uint32_t)DMA_CCR_CIRC) /*!< Circular mode */ |
| AnnaBridge | 189:f392fc9709a3 | 230 | /** |
| AnnaBridge | 189:f392fc9709a3 | 231 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 232 | */ |
| AnnaBridge | 189:f392fc9709a3 | 233 | |
| AnnaBridge | 189:f392fc9709a3 | 234 | /** @defgroup DMA_Priority_level DMA Priority level |
| AnnaBridge | 189:f392fc9709a3 | 235 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 236 | */ |
| AnnaBridge | 189:f392fc9709a3 | 237 | #define DMA_PRIORITY_LOW 0x00000000U /*!< Priority level : Low */ |
| AnnaBridge | 189:f392fc9709a3 | 238 | #define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_CCR_PL_0) /*!< Priority level : Medium */ |
| AnnaBridge | 189:f392fc9709a3 | 239 | #define DMA_PRIORITY_HIGH ((uint32_t)DMA_CCR_PL_1) /*!< Priority level : High */ |
| AnnaBridge | 189:f392fc9709a3 | 240 | #define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_CCR_PL) /*!< Priority level : Very_High */ |
| AnnaBridge | 189:f392fc9709a3 | 241 | /** |
| AnnaBridge | 189:f392fc9709a3 | 242 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 243 | */ |
| AnnaBridge | 189:f392fc9709a3 | 244 | |
| AnnaBridge | 189:f392fc9709a3 | 245 | |
| AnnaBridge | 189:f392fc9709a3 | 246 | /** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions |
| AnnaBridge | 189:f392fc9709a3 | 247 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 248 | */ |
| AnnaBridge | 189:f392fc9709a3 | 249 | #define DMA_IT_TC ((uint32_t)DMA_CCR_TCIE) |
| AnnaBridge | 189:f392fc9709a3 | 250 | #define DMA_IT_HT ((uint32_t)DMA_CCR_HTIE) |
| AnnaBridge | 189:f392fc9709a3 | 251 | #define DMA_IT_TE ((uint32_t)DMA_CCR_TEIE) |
| AnnaBridge | 189:f392fc9709a3 | 252 | /** |
| AnnaBridge | 189:f392fc9709a3 | 253 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 254 | */ |
| AnnaBridge | 189:f392fc9709a3 | 255 | |
| AnnaBridge | 189:f392fc9709a3 | 256 | /** @defgroup DMA_flag_definitions DMA flag definitions |
| AnnaBridge | 189:f392fc9709a3 | 257 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 258 | */ |
| AnnaBridge | 189:f392fc9709a3 | 259 | #define DMA_FLAG_GL1 0x00000001U |
| AnnaBridge | 189:f392fc9709a3 | 260 | #define DMA_FLAG_TC1 0x00000002U |
| AnnaBridge | 189:f392fc9709a3 | 261 | #define DMA_FLAG_HT1 0x00000004U |
| AnnaBridge | 189:f392fc9709a3 | 262 | #define DMA_FLAG_TE1 0x00000008U |
| AnnaBridge | 189:f392fc9709a3 | 263 | #define DMA_FLAG_GL2 0x00000010U |
| AnnaBridge | 189:f392fc9709a3 | 264 | #define DMA_FLAG_TC2 0x00000020U |
| AnnaBridge | 189:f392fc9709a3 | 265 | #define DMA_FLAG_HT2 0x00000040U |
| AnnaBridge | 189:f392fc9709a3 | 266 | #define DMA_FLAG_TE2 0x00000080U |
| AnnaBridge | 189:f392fc9709a3 | 267 | #define DMA_FLAG_GL3 0x00000100U |
| AnnaBridge | 189:f392fc9709a3 | 268 | #define DMA_FLAG_TC3 0x00000200U |
| AnnaBridge | 189:f392fc9709a3 | 269 | #define DMA_FLAG_HT3 0x00000400U |
| AnnaBridge | 189:f392fc9709a3 | 270 | #define DMA_FLAG_TE3 0x00000800U |
| AnnaBridge | 189:f392fc9709a3 | 271 | #define DMA_FLAG_GL4 0x00001000U |
| AnnaBridge | 189:f392fc9709a3 | 272 | #define DMA_FLAG_TC4 0x00002000U |
| AnnaBridge | 189:f392fc9709a3 | 273 | #define DMA_FLAG_HT4 0x00004000U |
| AnnaBridge | 189:f392fc9709a3 | 274 | #define DMA_FLAG_TE4 0x00008000U |
| AnnaBridge | 189:f392fc9709a3 | 275 | #define DMA_FLAG_GL5 0x00010000U |
| AnnaBridge | 189:f392fc9709a3 | 276 | #define DMA_FLAG_TC5 0x00020000U |
| AnnaBridge | 189:f392fc9709a3 | 277 | #define DMA_FLAG_HT5 0x00040000U |
| AnnaBridge | 189:f392fc9709a3 | 278 | #define DMA_FLAG_TE5 0x00080000U |
| AnnaBridge | 189:f392fc9709a3 | 279 | #define DMA_FLAG_GL6 0x00100000U |
| AnnaBridge | 189:f392fc9709a3 | 280 | #define DMA_FLAG_TC6 0x00200000U |
| AnnaBridge | 189:f392fc9709a3 | 281 | #define DMA_FLAG_HT6 0x00400000U |
| AnnaBridge | 189:f392fc9709a3 | 282 | #define DMA_FLAG_TE6 0x00800000U |
| AnnaBridge | 189:f392fc9709a3 | 283 | #define DMA_FLAG_GL7 0x01000000U |
| AnnaBridge | 189:f392fc9709a3 | 284 | #define DMA_FLAG_TC7 0x02000000U |
| AnnaBridge | 189:f392fc9709a3 | 285 | #define DMA_FLAG_HT7 0x04000000U |
| AnnaBridge | 189:f392fc9709a3 | 286 | #define DMA_FLAG_TE7 0x08000000U |
| AnnaBridge | 189:f392fc9709a3 | 287 | /** |
| AnnaBridge | 189:f392fc9709a3 | 288 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 289 | */ |
| AnnaBridge | 189:f392fc9709a3 | 290 | |
| AnnaBridge | 189:f392fc9709a3 | 291 | /** |
| AnnaBridge | 189:f392fc9709a3 | 292 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 293 | */ |
| AnnaBridge | 189:f392fc9709a3 | 294 | |
| AnnaBridge | 189:f392fc9709a3 | 295 | |
| AnnaBridge | 189:f392fc9709a3 | 296 | /* Exported macros -----------------------------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 297 | /** @defgroup DMA_Exported_Macros DMA Exported Macros |
| AnnaBridge | 189:f392fc9709a3 | 298 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 299 | */ |
| AnnaBridge | 189:f392fc9709a3 | 300 | |
| AnnaBridge | 189:f392fc9709a3 | 301 | /** @brief Reset DMA handle state. |
| AnnaBridge | 189:f392fc9709a3 | 302 | * @param __HANDLE__: DMA handle |
| AnnaBridge | 189:f392fc9709a3 | 303 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 304 | */ |
| AnnaBridge | 189:f392fc9709a3 | 305 | #define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET) |
| AnnaBridge | 189:f392fc9709a3 | 306 | |
| AnnaBridge | 189:f392fc9709a3 | 307 | /** |
| AnnaBridge | 189:f392fc9709a3 | 308 | * @brief Enable the specified DMA Channel. |
| AnnaBridge | 189:f392fc9709a3 | 309 | * @param __HANDLE__: DMA handle |
| AnnaBridge | 189:f392fc9709a3 | 310 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 311 | */ |
| AnnaBridge | 189:f392fc9709a3 | 312 | #define __HAL_DMA_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CCR, DMA_CCR_EN)) |
| AnnaBridge | 189:f392fc9709a3 | 313 | |
| AnnaBridge | 189:f392fc9709a3 | 314 | /** |
| AnnaBridge | 189:f392fc9709a3 | 315 | * @brief Disable the specified DMA Channel. |
| AnnaBridge | 189:f392fc9709a3 | 316 | * @param __HANDLE__: DMA handle |
| AnnaBridge | 189:f392fc9709a3 | 317 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 318 | */ |
| AnnaBridge | 189:f392fc9709a3 | 319 | #define __HAL_DMA_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CCR, DMA_CCR_EN)) |
| AnnaBridge | 189:f392fc9709a3 | 320 | |
| AnnaBridge | 189:f392fc9709a3 | 321 | |
| AnnaBridge | 189:f392fc9709a3 | 322 | /* Interrupt & Flag management */ |
| AnnaBridge | 189:f392fc9709a3 | 323 | |
| AnnaBridge | 189:f392fc9709a3 | 324 | /** |
| AnnaBridge | 189:f392fc9709a3 | 325 | * @brief Enables the specified DMA Channel interrupts. |
| AnnaBridge | 189:f392fc9709a3 | 326 | * @param __HANDLE__: DMA handle |
| AnnaBridge | 189:f392fc9709a3 | 327 | * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled. |
| AnnaBridge | 189:f392fc9709a3 | 328 | * This parameter can be any combination of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 329 | * @arg DMA_IT_TC: Transfer complete interrupt mask |
| AnnaBridge | 189:f392fc9709a3 | 330 | * @arg DMA_IT_HT: Half transfer complete interrupt mask |
| AnnaBridge | 189:f392fc9709a3 | 331 | * @arg DMA_IT_TE: Transfer error interrupt mask |
| AnnaBridge | 189:f392fc9709a3 | 332 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 333 | */ |
| AnnaBridge | 189:f392fc9709a3 | 334 | #define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) (SET_BIT((__HANDLE__)->Instance->CCR, (__INTERRUPT__))) |
| AnnaBridge | 189:f392fc9709a3 | 335 | |
| AnnaBridge | 189:f392fc9709a3 | 336 | /** |
| AnnaBridge | 189:f392fc9709a3 | 337 | * @brief Disable the specified DMA Channel interrupts. |
| AnnaBridge | 189:f392fc9709a3 | 338 | * @param __HANDLE__: DMA handle |
| AnnaBridge | 189:f392fc9709a3 | 339 | * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled. |
| AnnaBridge | 189:f392fc9709a3 | 340 | * This parameter can be any combination of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 341 | * @arg DMA_IT_TC: Transfer complete interrupt mask |
| AnnaBridge | 189:f392fc9709a3 | 342 | * @arg DMA_IT_HT: Half transfer complete interrupt mask |
| AnnaBridge | 189:f392fc9709a3 | 343 | * @arg DMA_IT_TE: Transfer error interrupt mask |
| AnnaBridge | 189:f392fc9709a3 | 344 | * @retval None |
| AnnaBridge | 189:f392fc9709a3 | 345 | */ |
| AnnaBridge | 189:f392fc9709a3 | 346 | #define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (CLEAR_BIT((__HANDLE__)->Instance->CCR , (__INTERRUPT__))) |
| AnnaBridge | 189:f392fc9709a3 | 347 | |
| AnnaBridge | 189:f392fc9709a3 | 348 | /** |
| AnnaBridge | 189:f392fc9709a3 | 349 | * @brief Check whether the specified DMA Channel interrupt is enabled or not. |
| AnnaBridge | 189:f392fc9709a3 | 350 | * @param __HANDLE__: DMA handle |
| AnnaBridge | 189:f392fc9709a3 | 351 | * @param __INTERRUPT__: specifies the DMA interrupt source to check. |
| AnnaBridge | 189:f392fc9709a3 | 352 | * This parameter can be one of the following values: |
| AnnaBridge | 189:f392fc9709a3 | 353 | * @arg DMA_IT_TC: Transfer complete interrupt mask |
| AnnaBridge | 189:f392fc9709a3 | 354 | * @arg DMA_IT_HT: Half transfer complete interrupt mask |
| AnnaBridge | 189:f392fc9709a3 | 355 | * @arg DMA_IT_TE: Transfer error interrupt mask |
| AnnaBridge | 189:f392fc9709a3 | 356 | * @retval The state of DMA_IT (SET or RESET). |
| AnnaBridge | 189:f392fc9709a3 | 357 | */ |
| AnnaBridge | 189:f392fc9709a3 | 358 | #define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CCR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) |
| AnnaBridge | 189:f392fc9709a3 | 359 | |
| AnnaBridge | 189:f392fc9709a3 | 360 | /** |
| AnnaBridge | 189:f392fc9709a3 | 361 | * @brief Return the number of remaining data units in the current DMA Channel transfer. |
| AnnaBridge | 189:f392fc9709a3 | 362 | * @param __HANDLE__: DMA handle |
| AnnaBridge | 189:f392fc9709a3 | 363 | * @retval The number of remaining data units in the current DMA Channel transfer. |
| AnnaBridge | 189:f392fc9709a3 | 364 | */ |
| AnnaBridge | 189:f392fc9709a3 | 365 | #define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNDTR) |
| AnnaBridge | 189:f392fc9709a3 | 366 | |
| AnnaBridge | 189:f392fc9709a3 | 367 | /** |
| AnnaBridge | 189:f392fc9709a3 | 368 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 369 | */ |
| AnnaBridge | 189:f392fc9709a3 | 370 | |
| AnnaBridge | 189:f392fc9709a3 | 371 | /* Include DMA HAL Extension module */ |
| AnnaBridge | 189:f392fc9709a3 | 372 | #include "stm32f1xx_hal_dma_ex.h" |
| AnnaBridge | 189:f392fc9709a3 | 373 | |
| AnnaBridge | 189:f392fc9709a3 | 374 | /* Exported functions --------------------------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 375 | /** @addtogroup DMA_Exported_Functions |
| AnnaBridge | 189:f392fc9709a3 | 376 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 377 | */ |
| AnnaBridge | 189:f392fc9709a3 | 378 | |
| AnnaBridge | 189:f392fc9709a3 | 379 | /** @addtogroup DMA_Exported_Functions_Group1 |
| AnnaBridge | 189:f392fc9709a3 | 380 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 381 | */ |
| AnnaBridge | 189:f392fc9709a3 | 382 | /* Initialization and de-initialization functions *****************************/ |
| AnnaBridge | 189:f392fc9709a3 | 383 | HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma); |
| AnnaBridge | 189:f392fc9709a3 | 384 | HAL_StatusTypeDef HAL_DMA_DeInit (DMA_HandleTypeDef *hdma); |
| AnnaBridge | 189:f392fc9709a3 | 385 | /** |
| AnnaBridge | 189:f392fc9709a3 | 386 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 387 | */ |
| AnnaBridge | 189:f392fc9709a3 | 388 | |
| AnnaBridge | 189:f392fc9709a3 | 389 | /** @addtogroup DMA_Exported_Functions_Group2 |
| AnnaBridge | 189:f392fc9709a3 | 390 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 391 | */ |
| AnnaBridge | 189:f392fc9709a3 | 392 | /* IO operation functions *****************************************************/ |
| AnnaBridge | 189:f392fc9709a3 | 393 | HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); |
| AnnaBridge | 189:f392fc9709a3 | 394 | HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); |
| AnnaBridge | 189:f392fc9709a3 | 395 | HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma); |
| AnnaBridge | 189:f392fc9709a3 | 396 | HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma); |
| AnnaBridge | 189:f392fc9709a3 | 397 | HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout); |
| AnnaBridge | 189:f392fc9709a3 | 398 | void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma); |
| AnnaBridge | 189:f392fc9709a3 | 399 | HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)( DMA_HandleTypeDef * _hdma)); |
| AnnaBridge | 189:f392fc9709a3 | 400 | HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID); |
| AnnaBridge | 189:f392fc9709a3 | 401 | |
| AnnaBridge | 189:f392fc9709a3 | 402 | /** |
| AnnaBridge | 189:f392fc9709a3 | 403 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 404 | */ |
| AnnaBridge | 189:f392fc9709a3 | 405 | |
| AnnaBridge | 189:f392fc9709a3 | 406 | /** @addtogroup DMA_Exported_Functions_Group3 |
| AnnaBridge | 189:f392fc9709a3 | 407 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 408 | */ |
| AnnaBridge | 189:f392fc9709a3 | 409 | /* Peripheral State and Error functions ***************************************/ |
| AnnaBridge | 189:f392fc9709a3 | 410 | HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma); |
| AnnaBridge | 189:f392fc9709a3 | 411 | uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma); |
| AnnaBridge | 189:f392fc9709a3 | 412 | /** |
| AnnaBridge | 189:f392fc9709a3 | 413 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 414 | */ |
| AnnaBridge | 189:f392fc9709a3 | 415 | |
| AnnaBridge | 189:f392fc9709a3 | 416 | /** |
| AnnaBridge | 189:f392fc9709a3 | 417 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 418 | */ |
| AnnaBridge | 189:f392fc9709a3 | 419 | |
| AnnaBridge | 189:f392fc9709a3 | 420 | /* Private macros ------------------------------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 421 | /** @defgroup DMA_Private_Macros DMA Private Macros |
| AnnaBridge | 189:f392fc9709a3 | 422 | * @{ |
| AnnaBridge | 189:f392fc9709a3 | 423 | */ |
| AnnaBridge | 189:f392fc9709a3 | 424 | |
| AnnaBridge | 189:f392fc9709a3 | 425 | #define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \ |
| AnnaBridge | 189:f392fc9709a3 | 426 | ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \ |
| AnnaBridge | 189:f392fc9709a3 | 427 | ((DIRECTION) == DMA_MEMORY_TO_MEMORY)) |
| AnnaBridge | 189:f392fc9709a3 | 428 | |
| AnnaBridge | 189:f392fc9709a3 | 429 | #define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1U) && ((SIZE) < 0x10000U)) |
| AnnaBridge | 189:f392fc9709a3 | 430 | |
| AnnaBridge | 189:f392fc9709a3 | 431 | #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \ |
| AnnaBridge | 189:f392fc9709a3 | 432 | ((STATE) == DMA_PINC_DISABLE)) |
| AnnaBridge | 189:f392fc9709a3 | 433 | |
| AnnaBridge | 189:f392fc9709a3 | 434 | #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \ |
| AnnaBridge | 189:f392fc9709a3 | 435 | ((STATE) == DMA_MINC_DISABLE)) |
| AnnaBridge | 189:f392fc9709a3 | 436 | |
| AnnaBridge | 189:f392fc9709a3 | 437 | #define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \ |
| AnnaBridge | 189:f392fc9709a3 | 438 | ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \ |
| AnnaBridge | 189:f392fc9709a3 | 439 | ((SIZE) == DMA_PDATAALIGN_WORD)) |
| AnnaBridge | 189:f392fc9709a3 | 440 | |
| AnnaBridge | 189:f392fc9709a3 | 441 | #define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \ |
| AnnaBridge | 189:f392fc9709a3 | 442 | ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \ |
| AnnaBridge | 189:f392fc9709a3 | 443 | ((SIZE) == DMA_MDATAALIGN_WORD )) |
| AnnaBridge | 189:f392fc9709a3 | 444 | |
| AnnaBridge | 189:f392fc9709a3 | 445 | #define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \ |
| AnnaBridge | 189:f392fc9709a3 | 446 | ((MODE) == DMA_CIRCULAR)) |
| AnnaBridge | 189:f392fc9709a3 | 447 | |
| AnnaBridge | 189:f392fc9709a3 | 448 | #define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \ |
| AnnaBridge | 189:f392fc9709a3 | 449 | ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \ |
| AnnaBridge | 189:f392fc9709a3 | 450 | ((PRIORITY) == DMA_PRIORITY_HIGH) || \ |
| AnnaBridge | 189:f392fc9709a3 | 451 | ((PRIORITY) == DMA_PRIORITY_VERY_HIGH)) |
| AnnaBridge | 189:f392fc9709a3 | 452 | |
| AnnaBridge | 189:f392fc9709a3 | 453 | /** |
| AnnaBridge | 189:f392fc9709a3 | 454 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 455 | */ |
| AnnaBridge | 189:f392fc9709a3 | 456 | |
| AnnaBridge | 189:f392fc9709a3 | 457 | /* Private functions ---------------------------------------------------------*/ |
| AnnaBridge | 189:f392fc9709a3 | 458 | |
| AnnaBridge | 189:f392fc9709a3 | 459 | /** |
| AnnaBridge | 189:f392fc9709a3 | 460 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 461 | */ |
| AnnaBridge | 189:f392fc9709a3 | 462 | |
| AnnaBridge | 189:f392fc9709a3 | 463 | /** |
| AnnaBridge | 189:f392fc9709a3 | 464 | * @} |
| AnnaBridge | 189:f392fc9709a3 | 465 | */ |
| AnnaBridge | 189:f392fc9709a3 | 466 | |
| AnnaBridge | 189:f392fc9709a3 | 467 | #ifdef __cplusplus |
| AnnaBridge | 189:f392fc9709a3 | 468 | } |
| AnnaBridge | 189:f392fc9709a3 | 469 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 470 | |
| AnnaBridge | 189:f392fc9709a3 | 471 | #endif /* __STM32F1xx_HAL_DMA_H */ |
| AnnaBridge | 189:f392fc9709a3 | 472 | |
| AnnaBridge | 189:f392fc9709a3 | 473 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
