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cmsis/BUILD/mbed/TARGET_EFM32LG_STK3600/TOOLCHAIN_ARM_MICRO/em_opamp.h@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 189:f392fc9709a3 1 /**************************************************************************//**
AnnaBridge 189:f392fc9709a3 2 * @file em_opamp.h
AnnaBridge 189:f392fc9709a3 3 * @brief Operational Amplifier (OPAMP) peripheral API
AnnaBridge 189:f392fc9709a3 4 * @version 5.3.3
AnnaBridge 189:f392fc9709a3 5 ******************************************************************************
AnnaBridge 189:f392fc9709a3 6 * # License
AnnaBridge 189:f392fc9709a3 7 * <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
AnnaBridge 189:f392fc9709a3 8 *******************************************************************************
AnnaBridge 189:f392fc9709a3 9 *
AnnaBridge 189:f392fc9709a3 10 * Permission is granted to anyone to use this software for any purpose,
AnnaBridge 189:f392fc9709a3 11 * including commercial applications, and to alter it and redistribute it
AnnaBridge 189:f392fc9709a3 12 * freely, subject to the following restrictions:
AnnaBridge 189:f392fc9709a3 13 *
AnnaBridge 189:f392fc9709a3 14 * 1. The origin of this software must not be misrepresented; you must not
AnnaBridge 189:f392fc9709a3 15 * claim that you wrote the original software.
AnnaBridge 189:f392fc9709a3 16 * 2. Altered source versions must be plainly marked as such, and must not be
AnnaBridge 189:f392fc9709a3 17 * misrepresented as being the original software.
AnnaBridge 189:f392fc9709a3 18 * 3. This notice may not be removed or altered from any source distribution.
AnnaBridge 189:f392fc9709a3 19 *
AnnaBridge 189:f392fc9709a3 20 * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Labs has no
AnnaBridge 189:f392fc9709a3 21 * obligation to support this Software. Silicon Labs is providing the
AnnaBridge 189:f392fc9709a3 22 * Software "AS IS", with no express or implied warranties of any kind,
AnnaBridge 189:f392fc9709a3 23 * including, but not limited to, any implied warranties of merchantability
AnnaBridge 189:f392fc9709a3 24 * or fitness for any particular purpose or warranties against infringement
AnnaBridge 189:f392fc9709a3 25 * of any proprietary rights of a third party.
AnnaBridge 189:f392fc9709a3 26 *
AnnaBridge 189:f392fc9709a3 27 * Silicon Labs will not be liable for any consequential, incidental, or
AnnaBridge 189:f392fc9709a3 28 * special damages, or any other relief, or for any claim by any third party,
AnnaBridge 189:f392fc9709a3 29 * arising from your use of this Software.
AnnaBridge 189:f392fc9709a3 30 *
AnnaBridge 189:f392fc9709a3 31 ******************************************************************************/
AnnaBridge 189:f392fc9709a3 32
AnnaBridge 189:f392fc9709a3 33 #ifndef EM_OPAMP_H
AnnaBridge 189:f392fc9709a3 34 #define EM_OPAMP_H
AnnaBridge 189:f392fc9709a3 35
AnnaBridge 189:f392fc9709a3 36 #include "em_device.h"
AnnaBridge 189:f392fc9709a3 37 #if ((defined(_SILICON_LABS_32B_SERIES_0) && defined(OPAMP_PRESENT) && (OPAMP_COUNT == 1)) \
AnnaBridge 189:f392fc9709a3 38 || (defined(_SILICON_LABS_32B_SERIES_1) && defined(VDAC_PRESENT) && (VDAC_COUNT > 0)))
AnnaBridge 189:f392fc9709a3 39
AnnaBridge 189:f392fc9709a3 40 #ifdef __cplusplus
AnnaBridge 189:f392fc9709a3 41 extern "C" {
AnnaBridge 189:f392fc9709a3 42 #endif
AnnaBridge 189:f392fc9709a3 43
AnnaBridge 189:f392fc9709a3 44 #include <stdint.h>
AnnaBridge 189:f392fc9709a3 45 #include <stdbool.h>
AnnaBridge 189:f392fc9709a3 46
AnnaBridge 189:f392fc9709a3 47 #if defined(_SILICON_LABS_32B_SERIES_0)
AnnaBridge 189:f392fc9709a3 48 #include "em_dac.h"
AnnaBridge 189:f392fc9709a3 49 #elif defined (_SILICON_LABS_32B_SERIES_1)
AnnaBridge 189:f392fc9709a3 50 #include "em_vdac.h"
AnnaBridge 189:f392fc9709a3 51 #endif
AnnaBridge 189:f392fc9709a3 52
AnnaBridge 189:f392fc9709a3 53 /***************************************************************************//**
AnnaBridge 189:f392fc9709a3 54 * @addtogroup emlib
AnnaBridge 189:f392fc9709a3 55 * @{
AnnaBridge 189:f392fc9709a3 56 ******************************************************************************/
AnnaBridge 189:f392fc9709a3 57
AnnaBridge 189:f392fc9709a3 58 /***************************************************************************//**
AnnaBridge 189:f392fc9709a3 59 * @addtogroup OPAMP
AnnaBridge 189:f392fc9709a3 60 * @{
AnnaBridge 189:f392fc9709a3 61 ******************************************************************************/
AnnaBridge 189:f392fc9709a3 62
AnnaBridge 189:f392fc9709a3 63 /** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */
AnnaBridge 189:f392fc9709a3 64
AnnaBridge 189:f392fc9709a3 65 /** Validation of DAC OPA number for assert statements. */
AnnaBridge 189:f392fc9709a3 66 #if defined(_SILICON_LABS_32B_SERIES_0)
AnnaBridge 189:f392fc9709a3 67 #define DAC_OPA_VALID(opa) ((opa) <= OPA2)
AnnaBridge 189:f392fc9709a3 68 #elif defined(_SILICON_LABS_32B_SERIES_1)
AnnaBridge 189:f392fc9709a3 69 #if defined(VDAC_STATUS_OPA2ENS)
AnnaBridge 189:f392fc9709a3 70 #define VDAC_OPA_VALID(opa) ((opa) <= OPA2)
AnnaBridge 189:f392fc9709a3 71 #elif defined(VDAC_STATUS_OPA1ENS)
AnnaBridge 189:f392fc9709a3 72 #define VDAC_OPA_VALID(opa) ((opa) <= OPA1)
AnnaBridge 189:f392fc9709a3 73 #else
AnnaBridge 189:f392fc9709a3 74 #define VDAC_OPA_VALID(opa) ((opa) = OPA0)
AnnaBridge 189:f392fc9709a3 75 #endif
AnnaBridge 189:f392fc9709a3 76 #endif
AnnaBridge 189:f392fc9709a3 77
AnnaBridge 189:f392fc9709a3 78 /** @endcond */
AnnaBridge 189:f392fc9709a3 79
AnnaBridge 189:f392fc9709a3 80 /*******************************************************************************
AnnaBridge 189:f392fc9709a3 81 ******************************** ENUMS ************************************
AnnaBridge 189:f392fc9709a3 82 ******************************************************************************/
AnnaBridge 189:f392fc9709a3 83
AnnaBridge 189:f392fc9709a3 84 /** OPAMP selector values. */
AnnaBridge 189:f392fc9709a3 85 typedef enum {
AnnaBridge 189:f392fc9709a3 86 #if defined(_SILICON_LABS_32B_SERIES_0) || defined(VDAC_STATUS_OPA0ENS)
AnnaBridge 189:f392fc9709a3 87 OPA0 = 0, /**< Select OPA0. */
AnnaBridge 189:f392fc9709a3 88 #endif
AnnaBridge 189:f392fc9709a3 89 #if defined(_SILICON_LABS_32B_SERIES_0) || defined(VDAC_STATUS_OPA1ENS)
AnnaBridge 189:f392fc9709a3 90 OPA1 = 1, /**< Select OPA1. */
AnnaBridge 189:f392fc9709a3 91 #endif
AnnaBridge 189:f392fc9709a3 92 #if defined(_SILICON_LABS_32B_SERIES_0) || defined(VDAC_STATUS_OPA2ENS)
AnnaBridge 189:f392fc9709a3 93 OPA2 = 2 /**< Select OPA2. */
AnnaBridge 189:f392fc9709a3 94 #endif
AnnaBridge 189:f392fc9709a3 95 } OPAMP_TypeDef;
AnnaBridge 189:f392fc9709a3 96
AnnaBridge 189:f392fc9709a3 97 /** OPAMP negative terminal input selection values. */
AnnaBridge 189:f392fc9709a3 98 typedef enum {
AnnaBridge 189:f392fc9709a3 99 #if defined(_SILICON_LABS_32B_SERIES_0)
AnnaBridge 189:f392fc9709a3 100 opaNegSelDisable = DAC_OPA0MUX_NEGSEL_DISABLE, /**< Input disabled. */
AnnaBridge 189:f392fc9709a3 101 opaNegSelUnityGain = DAC_OPA0MUX_NEGSEL_UG, /**< Unity gain feedback path. */
AnnaBridge 189:f392fc9709a3 102 opaNegSelResTap = DAC_OPA0MUX_NEGSEL_OPATAP, /**< Feedback resistor ladder tap. */
AnnaBridge 189:f392fc9709a3 103 opaNegSelNegPad = DAC_OPA0MUX_NEGSEL_NEGPAD /**< Negative pad as input. */
AnnaBridge 189:f392fc9709a3 104 #elif defined(_SILICON_LABS_32B_SERIES_1)
AnnaBridge 189:f392fc9709a3 105 opaNegSelAPORT1YCH1 = VDAC_OPA_MUX_NEGSEL_APORT1YCH1, /**< APORT1YCH1 */
AnnaBridge 189:f392fc9709a3 106 opaNegSelAPORT1YCH3 = VDAC_OPA_MUX_NEGSEL_APORT1YCH3, /**< APORT1YCH3 */
AnnaBridge 189:f392fc9709a3 107 opaNegSelAPORT1YCH5 = VDAC_OPA_MUX_NEGSEL_APORT1YCH5, /**< APORT1YCH5 */
AnnaBridge 189:f392fc9709a3 108 opaNegSelAPORT1YCH7 = VDAC_OPA_MUX_NEGSEL_APORT1YCH7, /**< APORT1YCH7 */
AnnaBridge 189:f392fc9709a3 109 opaNegSelAPORT1YCH9 = VDAC_OPA_MUX_NEGSEL_APORT1YCH9, /**< APORT1YCH9 */
AnnaBridge 189:f392fc9709a3 110 opaNegSelAPORT1YCH11 = VDAC_OPA_MUX_NEGSEL_APORT1YCH11, /**< APORT1YCH11 */
AnnaBridge 189:f392fc9709a3 111 opaNegSelAPORT1YCH13 = VDAC_OPA_MUX_NEGSEL_APORT1YCH13, /**< APORT1YCH13 */
AnnaBridge 189:f392fc9709a3 112 opaNegSelAPORT1YCH15 = VDAC_OPA_MUX_NEGSEL_APORT1YCH15, /**< APORT1YCH15 */
AnnaBridge 189:f392fc9709a3 113 opaNegSelAPORT1YCH17 = VDAC_OPA_MUX_NEGSEL_APORT1YCH17, /**< APORT1YCH17 */
AnnaBridge 189:f392fc9709a3 114 opaNegSelAPORT1YCH19 = VDAC_OPA_MUX_NEGSEL_APORT1YCH19, /**< APORT1YCH19 */
AnnaBridge 189:f392fc9709a3 115 opaNegSelAPORT1YCH21 = VDAC_OPA_MUX_NEGSEL_APORT1YCH21, /**< APORT1YCH21 */
AnnaBridge 189:f392fc9709a3 116 opaNegSelAPORT1YCH23 = VDAC_OPA_MUX_NEGSEL_APORT1YCH23, /**< APORT1YCH23 */
AnnaBridge 189:f392fc9709a3 117 opaNegSelAPORT1YCH25 = VDAC_OPA_MUX_NEGSEL_APORT1YCH25, /**< APORT1YCH25 */
AnnaBridge 189:f392fc9709a3 118 opaNegSelAPORT1YCH27 = VDAC_OPA_MUX_NEGSEL_APORT1YCH27, /**< APORT1YCH27 */
AnnaBridge 189:f392fc9709a3 119 opaNegSelAPORT1YCH29 = VDAC_OPA_MUX_NEGSEL_APORT1YCH29, /**< APORT1YCH29 */
AnnaBridge 189:f392fc9709a3 120 opaNegSelAPORT1YCH31 = VDAC_OPA_MUX_NEGSEL_APORT1YCH31, /**< APORT1YCH31 */
AnnaBridge 189:f392fc9709a3 121 opaNegSelAPORT2YCH0 = VDAC_OPA_MUX_NEGSEL_APORT2YCH0, /**< APORT2YCH0 */
AnnaBridge 189:f392fc9709a3 122 opaNegSelAPORT2YCH2 = VDAC_OPA_MUX_NEGSEL_APORT2YCH2, /**< APORT2YCH2 */
AnnaBridge 189:f392fc9709a3 123 opaNegSelAPORT2YCH4 = VDAC_OPA_MUX_NEGSEL_APORT2YCH4, /**< APORT2YCH4 */
AnnaBridge 189:f392fc9709a3 124 opaNegSelAPORT2YCH6 = VDAC_OPA_MUX_NEGSEL_APORT2YCH6, /**< APORT2YCH6 */
AnnaBridge 189:f392fc9709a3 125 opaNegSelAPORT2YCH8 = VDAC_OPA_MUX_NEGSEL_APORT2YCH8, /**< APORT2YCH8 */
AnnaBridge 189:f392fc9709a3 126 opaNegSelAPORT2YCH10 = VDAC_OPA_MUX_NEGSEL_APORT2YCH10, /**< APORT2YCH10 */
AnnaBridge 189:f392fc9709a3 127 opaNegSelAPORT2YCH12 = VDAC_OPA_MUX_NEGSEL_APORT2YCH12, /**< APORT2YCH12 */
AnnaBridge 189:f392fc9709a3 128 opaNegSelAPORT2YCH14 = VDAC_OPA_MUX_NEGSEL_APORT2YCH14, /**< APORT2YCH14 */
AnnaBridge 189:f392fc9709a3 129 opaNegSelAPORT2YCH16 = VDAC_OPA_MUX_NEGSEL_APORT2YCH16, /**< APORT2YCH16 */
AnnaBridge 189:f392fc9709a3 130 opaNegSelAPORT2YCH18 = VDAC_OPA_MUX_NEGSEL_APORT2YCH18, /**< APORT2YCH18 */
AnnaBridge 189:f392fc9709a3 131 opaNegSelAPORT2YCH20 = VDAC_OPA_MUX_NEGSEL_APORT2YCH20, /**< APORT2YCH20 */
AnnaBridge 189:f392fc9709a3 132 opaNegSelAPORT2YCH22 = VDAC_OPA_MUX_NEGSEL_APORT2YCH22, /**< APORT2YCH22 */
AnnaBridge 189:f392fc9709a3 133 opaNegSelAPORT2YCH24 = VDAC_OPA_MUX_NEGSEL_APORT2YCH24, /**< APORT2YCH24 */
AnnaBridge 189:f392fc9709a3 134 opaNegSelAPORT2YCH26 = VDAC_OPA_MUX_NEGSEL_APORT2YCH26, /**< APORT2YCH26 */
AnnaBridge 189:f392fc9709a3 135 opaNegSelAPORT2YCH28 = VDAC_OPA_MUX_NEGSEL_APORT2YCH28, /**< APORT2YCH28 */
AnnaBridge 189:f392fc9709a3 136 opaNegSelAPORT2YCH30 = VDAC_OPA_MUX_NEGSEL_APORT2YCH30, /**< APORT2YCH30 */
AnnaBridge 189:f392fc9709a3 137 opaNegSelAPORT3YCH1 = VDAC_OPA_MUX_NEGSEL_APORT3YCH1, /**< APORT3YCH1 */
AnnaBridge 189:f392fc9709a3 138 opaNegSelAPORT3YCH3 = VDAC_OPA_MUX_NEGSEL_APORT3YCH3, /**< APORT3YCH3 */
AnnaBridge 189:f392fc9709a3 139 opaNegSelAPORT3YCH5 = VDAC_OPA_MUX_NEGSEL_APORT3YCH5, /**< APORT3YCH5 */
AnnaBridge 189:f392fc9709a3 140 opaNegSelAPORT3YCH7 = VDAC_OPA_MUX_NEGSEL_APORT3YCH7, /**< APORT3YCH7 */
AnnaBridge 189:f392fc9709a3 141 opaNegSelAPORT3YCH9 = VDAC_OPA_MUX_NEGSEL_APORT3YCH9, /**< APORT3YCH9 */
AnnaBridge 189:f392fc9709a3 142 opaNegSelAPORT3YCH11 = VDAC_OPA_MUX_NEGSEL_APORT3YCH11, /**< APORT3YCH11 */
AnnaBridge 189:f392fc9709a3 143 opaNegSelAPORT3YCH13 = VDAC_OPA_MUX_NEGSEL_APORT3YCH13, /**< APORT3YCH13 */
AnnaBridge 189:f392fc9709a3 144 opaNegSelAPORT3YCH15 = VDAC_OPA_MUX_NEGSEL_APORT3YCH15, /**< APORT3YCH15 */
AnnaBridge 189:f392fc9709a3 145 opaNegSelAPORT3YCH17 = VDAC_OPA_MUX_NEGSEL_APORT3YCH17, /**< APORT3YCH17 */
AnnaBridge 189:f392fc9709a3 146 opaNegSelAPORT3YCH19 = VDAC_OPA_MUX_NEGSEL_APORT3YCH19, /**< APORT3YCH19 */
AnnaBridge 189:f392fc9709a3 147 opaNegSelAPORT3YCH21 = VDAC_OPA_MUX_NEGSEL_APORT3YCH21, /**< APORT3YCH21 */
AnnaBridge 189:f392fc9709a3 148 opaNegSelAPORT3YCH23 = VDAC_OPA_MUX_NEGSEL_APORT3YCH23, /**< APORT3YCH23 */
AnnaBridge 189:f392fc9709a3 149 opaNegSelAPORT3YCH25 = VDAC_OPA_MUX_NEGSEL_APORT3YCH25, /**< APORT3YCH25 */
AnnaBridge 189:f392fc9709a3 150 opaNegSelAPORT3YCH27 = VDAC_OPA_MUX_NEGSEL_APORT3YCH27, /**< APORT3YCH27 */
AnnaBridge 189:f392fc9709a3 151 opaNegSelAPORT3YCH29 = VDAC_OPA_MUX_NEGSEL_APORT3YCH29, /**< APORT3YCH29 */
AnnaBridge 189:f392fc9709a3 152 opaNegSelAPORT3YCH31 = VDAC_OPA_MUX_NEGSEL_APORT3YCH31, /**< APORT3YCH31 */
AnnaBridge 189:f392fc9709a3 153 opaNegSelAPORT4YCH0 = VDAC_OPA_MUX_NEGSEL_APORT4YCH0, /**< APORT4YCH0 */
AnnaBridge 189:f392fc9709a3 154 opaNegSelAPORT4YCH2 = VDAC_OPA_MUX_NEGSEL_APORT4YCH2, /**< APORT4YCH2 */
AnnaBridge 189:f392fc9709a3 155 opaNegSelAPORT4YCH4 = VDAC_OPA_MUX_NEGSEL_APORT4YCH4, /**< APORT4YCH4 */
AnnaBridge 189:f392fc9709a3 156 opaNegSelAPORT4YCH6 = VDAC_OPA_MUX_NEGSEL_APORT4YCH6, /**< APORT4YCH6 */
AnnaBridge 189:f392fc9709a3 157 opaNegSelAPORT4YCH8 = VDAC_OPA_MUX_NEGSEL_APORT4YCH8, /**< APORT4YCH8 */
AnnaBridge 189:f392fc9709a3 158 opaNegSelAPORT4YCH10 = VDAC_OPA_MUX_NEGSEL_APORT4YCH10, /**< APORT4YCH10 */
AnnaBridge 189:f392fc9709a3 159 opaNegSelAPORT4YCH12 = VDAC_OPA_MUX_NEGSEL_APORT4YCH12, /**< APORT4YCH12 */
AnnaBridge 189:f392fc9709a3 160 opaNegSelAPORT4YCH14 = VDAC_OPA_MUX_NEGSEL_APORT4YCH14, /**< APORT4YCH14 */
AnnaBridge 189:f392fc9709a3 161 opaNegSelAPORT4YCH16 = VDAC_OPA_MUX_NEGSEL_APORT4YCH16, /**< APORT4YCH16 */
AnnaBridge 189:f392fc9709a3 162 opaNegSelAPORT4YCH18 = VDAC_OPA_MUX_NEGSEL_APORT4YCH18, /**< APORT4YCH18 */
AnnaBridge 189:f392fc9709a3 163 opaNegSelAPORT4YCH20 = VDAC_OPA_MUX_NEGSEL_APORT4YCH20, /**< APORT4YCH20 */
AnnaBridge 189:f392fc9709a3 164 opaNegSelAPORT4YCH22 = VDAC_OPA_MUX_NEGSEL_APORT4YCH22, /**< APORT4YCH22 */
AnnaBridge 189:f392fc9709a3 165 opaNegSelAPORT4YCH24 = VDAC_OPA_MUX_NEGSEL_APORT4YCH24, /**< APORT4YCH24 */
AnnaBridge 189:f392fc9709a3 166 opaNegSelAPORT4YCH26 = VDAC_OPA_MUX_NEGSEL_APORT4YCH26, /**< APORT4YCH26 */
AnnaBridge 189:f392fc9709a3 167 opaNegSelAPORT4YCH28 = VDAC_OPA_MUX_NEGSEL_APORT4YCH28, /**< APORT4YCH28 */
AnnaBridge 189:f392fc9709a3 168 opaNegSelAPORT4YCH30 = VDAC_OPA_MUX_NEGSEL_APORT4YCH30, /**< APORT4YCH30 */
AnnaBridge 189:f392fc9709a3 169 opaNegSelDisable = VDAC_OPA_MUX_NEGSEL_DISABLE, /**< Input disabled. */
AnnaBridge 189:f392fc9709a3 170 opaNegSelUnityGain = VDAC_OPA_MUX_NEGSEL_UG, /**< Unity gain feedback path. */
AnnaBridge 189:f392fc9709a3 171 opaNegSelResTap = VDAC_OPA_MUX_NEGSEL_OPATAP, /**< Feedback resistor ladder tap. */
AnnaBridge 189:f392fc9709a3 172 opaNegSelNegPad = VDAC_OPA_MUX_NEGSEL_NEGPAD /**< Negative pad as input. */
AnnaBridge 189:f392fc9709a3 173 #endif /* defined(_SILICON_LABS_32B_SERIES_0) */
AnnaBridge 189:f392fc9709a3 174 } OPAMP_NegSel_TypeDef;
AnnaBridge 189:f392fc9709a3 175
AnnaBridge 189:f392fc9709a3 176 /** OPAMP positive terminal input selection values. */
AnnaBridge 189:f392fc9709a3 177 typedef enum {
AnnaBridge 189:f392fc9709a3 178 #if defined(_SILICON_LABS_32B_SERIES_0)
AnnaBridge 189:f392fc9709a3 179 opaPosSelDisable = DAC_OPA0MUX_POSSEL_DISABLE, /**< Input disabled. */
AnnaBridge 189:f392fc9709a3 180 opaPosSelDac = DAC_OPA0MUX_POSSEL_DAC, /**< DAC as input (not OPA2). */
AnnaBridge 189:f392fc9709a3 181 opaPosSelPosPad = DAC_OPA0MUX_POSSEL_POSPAD, /**< Positive pad as input. */
AnnaBridge 189:f392fc9709a3 182 opaPosSelOpaIn = DAC_OPA0MUX_POSSEL_OPA0INP, /**< Input from OPAx. */
AnnaBridge 189:f392fc9709a3 183 opaPosSelResTapOpa0 = DAC_OPA0MUX_POSSEL_OPATAP /**< Feedback resistor ladder tap from OPA0. */
AnnaBridge 189:f392fc9709a3 184 #elif defined(_SILICON_LABS_32B_SERIES_1)
AnnaBridge 189:f392fc9709a3 185 opaPosSelAPORT1XCH0 = VDAC_OPA_MUX_POSSEL_APORT1XCH0, /**< APORT1XCH0 */
AnnaBridge 189:f392fc9709a3 186 opaPosSelAPORT1XCH2 = VDAC_OPA_MUX_POSSEL_APORT1XCH2, /**< APORT1XCH2 */
AnnaBridge 189:f392fc9709a3 187 opaPosSelAPORT1XCH4 = VDAC_OPA_MUX_POSSEL_APORT1XCH4, /**< APORT1XCH4 */
AnnaBridge 189:f392fc9709a3 188 opaPosSelAPORT1XCH6 = VDAC_OPA_MUX_POSSEL_APORT1XCH6, /**< APORT1XCH6 */
AnnaBridge 189:f392fc9709a3 189 opaPosSelAPORT1XCH8 = VDAC_OPA_MUX_POSSEL_APORT1XCH8, /**< APORT1XCH8 */
AnnaBridge 189:f392fc9709a3 190 opaPosSelAPORT1XCH10 = VDAC_OPA_MUX_POSSEL_APORT1XCH10, /**< APORT1XCH10 */
AnnaBridge 189:f392fc9709a3 191 opaPosSelAPORT1XCH12 = VDAC_OPA_MUX_POSSEL_APORT1XCH12, /**< APORT1XCH12 */
AnnaBridge 189:f392fc9709a3 192 opaPosSelAPORT1XCH14 = VDAC_OPA_MUX_POSSEL_APORT1XCH14, /**< APORT1XCH14 */
AnnaBridge 189:f392fc9709a3 193 opaPosSelAPORT1XCH16 = VDAC_OPA_MUX_POSSEL_APORT1XCH16, /**< APORT1XCH16 */
AnnaBridge 189:f392fc9709a3 194 opaPosSelAPORT1XCH18 = VDAC_OPA_MUX_POSSEL_APORT1XCH18, /**< APORT1XCH18 */
AnnaBridge 189:f392fc9709a3 195 opaPosSelAPORT1XCH20 = VDAC_OPA_MUX_POSSEL_APORT1XCH20, /**< APORT1XCH20 */
AnnaBridge 189:f392fc9709a3 196 opaPosSelAPORT1XCH22 = VDAC_OPA_MUX_POSSEL_APORT1XCH22, /**< APORT1XCH22 */
AnnaBridge 189:f392fc9709a3 197 opaPosSelAPORT1XCH24 = VDAC_OPA_MUX_POSSEL_APORT1XCH24, /**< APORT1XCH24 */
AnnaBridge 189:f392fc9709a3 198 opaPosSelAPORT1XCH26 = VDAC_OPA_MUX_POSSEL_APORT1XCH26, /**< APORT1XCH26 */
AnnaBridge 189:f392fc9709a3 199 opaPosSelAPORT1XCH28 = VDAC_OPA_MUX_POSSEL_APORT1XCH28, /**< APORT1XCH28 */
AnnaBridge 189:f392fc9709a3 200 opaPosSelAPORT1XCH30 = VDAC_OPA_MUX_POSSEL_APORT1XCH30, /**< APORT1XCH30 */
AnnaBridge 189:f392fc9709a3 201 opaPosSelAPORT2XCH1 = VDAC_OPA_MUX_POSSEL_APORT2XCH1, /**< APORT2XCH1 */
AnnaBridge 189:f392fc9709a3 202 opaPosSelAPORT2XCH3 = VDAC_OPA_MUX_POSSEL_APORT2XCH3, /**< APORT2XCH3 */
AnnaBridge 189:f392fc9709a3 203 opaPosSelAPORT2XCH5 = VDAC_OPA_MUX_POSSEL_APORT2XCH5, /**< APORT2XCH5 */
AnnaBridge 189:f392fc9709a3 204 opaPosSelAPORT2XCH7 = VDAC_OPA_MUX_POSSEL_APORT2XCH7, /**< APORT2XCH7 */
AnnaBridge 189:f392fc9709a3 205 opaPosSelAPORT2XCH9 = VDAC_OPA_MUX_POSSEL_APORT2XCH9, /**< APORT2XCH9 */
AnnaBridge 189:f392fc9709a3 206 opaPosSelAPORT2XCH11 = VDAC_OPA_MUX_POSSEL_APORT2XCH11, /**< APORT2XCH11 */
AnnaBridge 189:f392fc9709a3 207 opaPosSelAPORT2XCH13 = VDAC_OPA_MUX_POSSEL_APORT2XCH13, /**< APORT2XCH13 */
AnnaBridge 189:f392fc9709a3 208 opaPosSelAPORT2XCH15 = VDAC_OPA_MUX_POSSEL_APORT2XCH15, /**< APORT2XCH15 */
AnnaBridge 189:f392fc9709a3 209 opaPosSelAPORT2XCH17 = VDAC_OPA_MUX_POSSEL_APORT2XCH17, /**< APORT2XCH17 */
AnnaBridge 189:f392fc9709a3 210 opaPosSelAPORT2XCH19 = VDAC_OPA_MUX_POSSEL_APORT2XCH19, /**< APORT2XCH19 */
AnnaBridge 189:f392fc9709a3 211 opaPosSelAPORT2XCH21 = VDAC_OPA_MUX_POSSEL_APORT2XCH21, /**< APORT2XCH21 */
AnnaBridge 189:f392fc9709a3 212 opaPosSelAPORT2XCH23 = VDAC_OPA_MUX_POSSEL_APORT2XCH23, /**< APORT2XCH23 */
AnnaBridge 189:f392fc9709a3 213 opaPosSelAPORT2XCH25 = VDAC_OPA_MUX_POSSEL_APORT2XCH25, /**< APORT2XCH25 */
AnnaBridge 189:f392fc9709a3 214 opaPosSelAPORT2XCH27 = VDAC_OPA_MUX_POSSEL_APORT2XCH27, /**< APORT2XCH27 */
AnnaBridge 189:f392fc9709a3 215 opaPosSelAPORT2XCH29 = VDAC_OPA_MUX_POSSEL_APORT2XCH29, /**< APORT2XCH29 */
AnnaBridge 189:f392fc9709a3 216 opaPosSelAPORT2XCH31 = VDAC_OPA_MUX_POSSEL_APORT2XCH31, /**< APORT2XCH31 */
AnnaBridge 189:f392fc9709a3 217 opaPosSelAPORT3XCH0 = VDAC_OPA_MUX_POSSEL_APORT3XCH0, /**< APORT3XCH0 */
AnnaBridge 189:f392fc9709a3 218 opaPosSelAPORT3XCH2 = VDAC_OPA_MUX_POSSEL_APORT3XCH2, /**< APORT3XCH2 */
AnnaBridge 189:f392fc9709a3 219 opaPosSelAPORT3XCH4 = VDAC_OPA_MUX_POSSEL_APORT3XCH4, /**< APORT3XCH4 */
AnnaBridge 189:f392fc9709a3 220 opaPosSelAPORT3XCH6 = VDAC_OPA_MUX_POSSEL_APORT3XCH6, /**< APORT3XCH6 */
AnnaBridge 189:f392fc9709a3 221 opaPosSelAPORT3XCH8 = VDAC_OPA_MUX_POSSEL_APORT3XCH8, /**< APORT3XCH8 */
AnnaBridge 189:f392fc9709a3 222 opaPosSelAPORT3XCH10 = VDAC_OPA_MUX_POSSEL_APORT3XCH10, /**< APORT3XCH10 */
AnnaBridge 189:f392fc9709a3 223 opaPosSelAPORT3XCH12 = VDAC_OPA_MUX_POSSEL_APORT3XCH12, /**< APORT3XCH12 */
AnnaBridge 189:f392fc9709a3 224 opaPosSelAPORT3XCH14 = VDAC_OPA_MUX_POSSEL_APORT3XCH14, /**< APORT3XCH14 */
AnnaBridge 189:f392fc9709a3 225 opaPosSelAPORT3XCH16 = VDAC_OPA_MUX_POSSEL_APORT3XCH16, /**< APORT3XCH16 */
AnnaBridge 189:f392fc9709a3 226 opaPosSelAPORT3XCH18 = VDAC_OPA_MUX_POSSEL_APORT3XCH18, /**< APORT3XCH18 */
AnnaBridge 189:f392fc9709a3 227 opaPosSelAPORT3XCH20 = VDAC_OPA_MUX_POSSEL_APORT3XCH20, /**< APORT3XCH20 */
AnnaBridge 189:f392fc9709a3 228 opaPosSelAPORT3XCH22 = VDAC_OPA_MUX_POSSEL_APORT3XCH22, /**< APORT3XCH22 */
AnnaBridge 189:f392fc9709a3 229 opaPosSelAPORT3XCH24 = VDAC_OPA_MUX_POSSEL_APORT3XCH24, /**< APORT3XCH24 */
AnnaBridge 189:f392fc9709a3 230 opaPosSelAPORT3XCH26 = VDAC_OPA_MUX_POSSEL_APORT3XCH26, /**< APORT3XCH26 */
AnnaBridge 189:f392fc9709a3 231 opaPosSelAPORT3XCH28 = VDAC_OPA_MUX_POSSEL_APORT3XCH28, /**< APORT3XCH28 */
AnnaBridge 189:f392fc9709a3 232 opaPosSelAPORT3XCH30 = VDAC_OPA_MUX_POSSEL_APORT3XCH30, /**< APORT3XCH30 */
AnnaBridge 189:f392fc9709a3 233 opaPosSelAPORT4XCH1 = VDAC_OPA_MUX_POSSEL_APORT4XCH1, /**< APORT4XCH1 */
AnnaBridge 189:f392fc9709a3 234 opaPosSelAPORT4XCH3 = VDAC_OPA_MUX_POSSEL_APORT4XCH3, /**< APORT4XCH3 */
AnnaBridge 189:f392fc9709a3 235 opaPosSelAPORT4XCH5 = VDAC_OPA_MUX_POSSEL_APORT4XCH5, /**< APORT4XCH5 */
AnnaBridge 189:f392fc9709a3 236 opaPosSelAPORT4XCH7 = VDAC_OPA_MUX_POSSEL_APORT4XCH7, /**< APORT4XCH7 */
AnnaBridge 189:f392fc9709a3 237 opaPosSelAPORT4XCH9 = VDAC_OPA_MUX_POSSEL_APORT4XCH9, /**< APORT4XCH9 */
AnnaBridge 189:f392fc9709a3 238 opaPosSelAPORT4XCH11 = VDAC_OPA_MUX_POSSEL_APORT4XCH11, /**< APORT4XCH11 */
AnnaBridge 189:f392fc9709a3 239 opaPosSelAPORT4XCH13 = VDAC_OPA_MUX_POSSEL_APORT4XCH13, /**< APORT4XCH13 */
AnnaBridge 189:f392fc9709a3 240 opaPosSelAPORT4XCH15 = VDAC_OPA_MUX_POSSEL_APORT4XCH15, /**< APORT4XCH15 */
AnnaBridge 189:f392fc9709a3 241 opaPosSelAPORT4XCH17 = VDAC_OPA_MUX_POSSEL_APORT4XCH17, /**< APORT4XCH17 */
AnnaBridge 189:f392fc9709a3 242 opaPosSelAPORT4XCH19 = VDAC_OPA_MUX_POSSEL_APORT4XCH19, /**< APORT4XCH19 */
AnnaBridge 189:f392fc9709a3 243 opaPosSelAPORT4XCH21 = VDAC_OPA_MUX_POSSEL_APORT4XCH21, /**< APORT4XCH21 */
AnnaBridge 189:f392fc9709a3 244 opaPosSelAPORT4XCH23 = VDAC_OPA_MUX_POSSEL_APORT4XCH23, /**< APORT4XCH23 */
AnnaBridge 189:f392fc9709a3 245 opaPosSelAPORT4XCH25 = VDAC_OPA_MUX_POSSEL_APORT4XCH25, /**< APORT4XCH25 */
AnnaBridge 189:f392fc9709a3 246 opaPosSelAPORT4XCH27 = VDAC_OPA_MUX_POSSEL_APORT4XCH27, /**< APORT4XCH27 */
AnnaBridge 189:f392fc9709a3 247 opaPosSelAPORT4XCH29 = VDAC_OPA_MUX_POSSEL_APORT4XCH29, /**< APORT4XCH29 */
AnnaBridge 189:f392fc9709a3 248 opaPosSelAPORT4XCH31 = VDAC_OPA_MUX_POSSEL_APORT4XCH31, /**< APORT4XCH31 */
AnnaBridge 189:f392fc9709a3 249 opaPosSelDisable = VDAC_OPA_MUX_POSSEL_DISABLE, /**< Input disabled. */
AnnaBridge 189:f392fc9709a3 250 opaPosSelDac = VDAC_OPA_MUX_POSSEL_DAC, /**< DAC as input (not OPA2). */
AnnaBridge 189:f392fc9709a3 251 opaPosSelPosPad = VDAC_OPA_MUX_POSSEL_POSPAD, /**< Positive pad as input. */
AnnaBridge 189:f392fc9709a3 252 opaPosSelOpaIn = VDAC_OPA_MUX_POSSEL_OPANEXT, /**< Input from OPAx. */
AnnaBridge 189:f392fc9709a3 253 opaPosSelResTap = VDAC_OPA_MUX_POSSEL_OPATAP /**< Feedback resistor ladder tap. */
AnnaBridge 189:f392fc9709a3 254 #endif /* defined(_SILICON_LABS_32B_SERIES_0) */
AnnaBridge 189:f392fc9709a3 255 } OPAMP_PosSel_TypeDef;
AnnaBridge 189:f392fc9709a3 256
AnnaBridge 189:f392fc9709a3 257 /** OPAMP output terminal selection values. */
AnnaBridge 189:f392fc9709a3 258 typedef enum {
AnnaBridge 189:f392fc9709a3 259 #if defined(_SILICON_LABS_32B_SERIES_0)
AnnaBridge 189:f392fc9709a3 260 opaOutModeDisable = DAC_OPA0MUX_OUTMODE_DISABLE, /**< OPA output disabled. */
AnnaBridge 189:f392fc9709a3 261 opaOutModeMain = DAC_OPA0MUX_OUTMODE_MAIN, /**< Main output to pin enabled. */
AnnaBridge 189:f392fc9709a3 262 opaOutModeAlt = DAC_OPA0MUX_OUTMODE_ALT, /**< Alternate output(s) enabled (not OPA2). */
AnnaBridge 189:f392fc9709a3 263 opaOutModeAll = DAC_OPA0MUX_OUTMODE_ALL /**< Both main and alternate enabled (not OPA2). */
AnnaBridge 189:f392fc9709a3 264 #elif defined(_SILICON_LABS_32B_SERIES_1)
AnnaBridge 189:f392fc9709a3 265 opaOutModeDisable = 0, /**< OPA output disabled. */
AnnaBridge 189:f392fc9709a3 266 opaOutModeMain = VDAC_OPA_OUT_MAINOUTEN, /**< Main output to pin enabled. */
AnnaBridge 189:f392fc9709a3 267 opaOutModeAlt = VDAC_OPA_OUT_ALTOUTEN, /**< Alternate output(s) enabled (not OPA2). */
AnnaBridge 189:f392fc9709a3 268 opaOutModeAll = VDAC_OPA_OUT_SHORT, /**< Both main and alternate enabled (not OPA2). */
AnnaBridge 189:f392fc9709a3 269 opaOutModeAPORT1YCH1 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH1), /**< APORT output to APORT1YCH1 pin enabled. */
AnnaBridge 189:f392fc9709a3 270 opaOutModeAPORT1YCH3 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH3), /**< APORT output to APORT1YCH3 pin enabled. */
AnnaBridge 189:f392fc9709a3 271 opaOutModeAPORT1YCH5 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH5), /**< APORT output to APORT1YCH5 pin enabled. */
AnnaBridge 189:f392fc9709a3 272 opaOutModeAPORT1YCH7 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH7), /**< APORT output to APORT1YCH7 pin enabled. */
AnnaBridge 189:f392fc9709a3 273 opaOutModeAPORT1YCH9 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH9), /**< APORT output to APORT1YCH9 pin enabled. */
AnnaBridge 189:f392fc9709a3 274 opaOutModeAPORT1YCH11 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH11), /**< APORT output to APORT1YCH11 pin enabled. */
AnnaBridge 189:f392fc9709a3 275 opaOutModeAPORT1YCH13 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH13), /**< APORT output to APORT1YCH13 pin enabled. */
AnnaBridge 189:f392fc9709a3 276 opaOutModeAPORT1YCH15 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH15), /**< APORT output to APORT1YCH15 pin enabled. */
AnnaBridge 189:f392fc9709a3 277 opaOutModeAPORT1YCH17 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH17), /**< APORT output to APORT1YCH17 pin enabled. */
AnnaBridge 189:f392fc9709a3 278 opaOutModeAPORT1YCH19 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH19), /**< APORT output to APORT1YCH19 pin enabled. */
AnnaBridge 189:f392fc9709a3 279 opaOutModeAPORT1YCH21 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH21), /**< APORT output to APORT1YCH21 pin enabled. */
AnnaBridge 189:f392fc9709a3 280 opaOutModeAPORT1YCH23 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH23), /**< APORT output to APORT1YCH23 pin enabled. */
AnnaBridge 189:f392fc9709a3 281 opaOutModeAPORT1YCH25 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH25), /**< APORT output to APORT1YCH25 pin enabled. */
AnnaBridge 189:f392fc9709a3 282 opaOutModeAPORT1YCH27 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH27), /**< APORT output to APORT1YCH27 pin enabled. */
AnnaBridge 189:f392fc9709a3 283 opaOutModeAPORT1YCH29 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH29), /**< APORT output to APORT1YCH29 pin enabled. */
AnnaBridge 189:f392fc9709a3 284 opaOutModeAPORT1YCH31 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH31), /**< APORT output to APORT1YCH31 pin enabled. */
AnnaBridge 189:f392fc9709a3 285 opaOutModeAPORT2YCH0 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH0), /**< APORT output to APORT2YCH0 pin enabled. */
AnnaBridge 189:f392fc9709a3 286 opaOutModeAPORT2YCH2 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH2), /**< APORT output to APORT2YCH2 pin enabled. */
AnnaBridge 189:f392fc9709a3 287 opaOutModeAPORT2YCH4 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH4), /**< APORT output to APORT2YCH4 pin enabled. */
AnnaBridge 189:f392fc9709a3 288 opaOutModeAPORT2YCH6 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH6), /**< APORT output to APORT2YCH6 pin enabled. */
AnnaBridge 189:f392fc9709a3 289 opaOutModeAPORT2YCH8 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH8), /**< APORT output to APORT2YCH8 pin enabled. */
AnnaBridge 189:f392fc9709a3 290 opaOutModeAPORT2YCH10 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH10), /**< APORT output to APORT2YCH10 pin enabled. */
AnnaBridge 189:f392fc9709a3 291 opaOutModeAPORT2YCH12 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH12), /**< APORT output to APORT2YCH12 pin enabled. */
AnnaBridge 189:f392fc9709a3 292 opaOutModeAPORT2YCH14 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH14), /**< APORT output to APORT2YCH14 pin enabled. */
AnnaBridge 189:f392fc9709a3 293 opaOutModeAPORT2YCH16 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH16), /**< APORT output to APORT2YCH16 pin enabled. */
AnnaBridge 189:f392fc9709a3 294 opaOutModeAPORT2YCH18 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH18), /**< APORT output to APORT2YCH18 pin enabled. */
AnnaBridge 189:f392fc9709a3 295 opaOutModeAPORT2YCH20 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH20), /**< APORT output to APORT2YCH20 pin enabled. */
AnnaBridge 189:f392fc9709a3 296 opaOutModeAPORT2YCH22 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH22), /**< APORT output to APORT2YCH22 pin enabled. */
AnnaBridge 189:f392fc9709a3 297 opaOutModeAPORT2YCH24 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH24), /**< APORT output to APORT2YCH24 pin enabled. */
AnnaBridge 189:f392fc9709a3 298 opaOutModeAPORT2YCH26 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH26), /**< APORT output to APORT2YCH26 pin enabled. */
AnnaBridge 189:f392fc9709a3 299 opaOutModeAPORT2YCH28 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH28), /**< APORT output to APORT2YCH28 pin enabled. */
AnnaBridge 189:f392fc9709a3 300 opaOutModeAPORT2YCH30 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH30), /**< APORT output to APORT2YCH30 pin enabled. */
AnnaBridge 189:f392fc9709a3 301 opaOutModeAPORT3YCH1 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH1), /**< APORT output to APORT3YCH1 pin enabled. */
AnnaBridge 189:f392fc9709a3 302 opaOutModeAPORT3YCH3 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH3), /**< APORT output to APORT3YCH3 pin enabled. */
AnnaBridge 189:f392fc9709a3 303 opaOutModeAPORT3YCH5 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH5), /**< APORT output to APORT3YCH5 pin enabled. */
AnnaBridge 189:f392fc9709a3 304 opaOutModeAPORT3YCH7 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH7), /**< APORT output to APORT3YCH7 pin enabled. */
AnnaBridge 189:f392fc9709a3 305 opaOutModeAPORT3YCH9 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH9), /**< APORT output to APORT3YCH9 pin enabled. */
AnnaBridge 189:f392fc9709a3 306 opaOutModeAPORT3YCH11 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH11), /**< APORT output to APORT3YCH11 pin enabled. */
AnnaBridge 189:f392fc9709a3 307 opaOutModeAPORT3YCH13 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH13), /**< APORT output to APORT3YCH13 pin enabled. */
AnnaBridge 189:f392fc9709a3 308 opaOutModeAPORT3YCH15 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH15), /**< APORT output to APORT3YCH15 pin enabled. */
AnnaBridge 189:f392fc9709a3 309 opaOutModeAPORT3YCH17 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH17), /**< APORT output to APORT3YCH17 pin enabled. */
AnnaBridge 189:f392fc9709a3 310 opaOutModeAPORT3YCH19 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH19), /**< APORT output to APORT3YCH19 pin enabled. */
AnnaBridge 189:f392fc9709a3 311 opaOutModeAPORT3YCH21 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH21), /**< APORT output to APORT3YCH21 pin enabled. */
AnnaBridge 189:f392fc9709a3 312 opaOutModeAPORT3YCH23 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH23), /**< APORT output to APORT3YCH23 pin enabled. */
AnnaBridge 189:f392fc9709a3 313 opaOutModeAPORT3YCH25 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH25), /**< APORT output to APORT3YCH25 pin enabled. */
AnnaBridge 189:f392fc9709a3 314 opaOutModeAPORT3YCH27 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH27), /**< APORT output to APORT3YCH27 pin enabled. */
AnnaBridge 189:f392fc9709a3 315 opaOutModeAPORT3YCH29 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH29), /**< APORT output to APORT3YCH29 pin enabled. */
AnnaBridge 189:f392fc9709a3 316 opaOutModeAPORT3YCH31 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH31), /**< APORT output to APORT3YCH31 pin enabled. */
AnnaBridge 189:f392fc9709a3 317 opaOutModeAPORT4YCH0 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH0), /**< APORT output to APORT4YCH0 pin enabled. */
AnnaBridge 189:f392fc9709a3 318 opaOutModeAPORT4YCH2 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH2), /**< APORT output to APORT4YCH2 pin enabled. */
AnnaBridge 189:f392fc9709a3 319 opaOutModeAPORT4YCH4 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH4), /**< APORT output to APORT4YCH4 pin enabled. */
AnnaBridge 189:f392fc9709a3 320 opaOutModeAPORT4YCH6 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH6), /**< APORT output to APORT4YCH6 pin enabled. */
AnnaBridge 189:f392fc9709a3 321 opaOutModeAPORT4YCH8 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH8), /**< APORT output to APORT4YCH8 pin enabled. */
AnnaBridge 189:f392fc9709a3 322 opaOutModeAPORT4YCH10 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH10), /**< APORT output to APORT4YCH10 pin enabled. */
AnnaBridge 189:f392fc9709a3 323 opaOutModeAPORT4YCH12 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH12), /**< APORT output to APORT4YCH12 pin enabled. */
AnnaBridge 189:f392fc9709a3 324 opaOutModeAPORT4YCH14 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH14), /**< APORT output to APORT4YCH14 pin enabled. */
AnnaBridge 189:f392fc9709a3 325 opaOutModeAPORT4YCH16 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH16), /**< APORT output to APORT4YCH16 pin enabled. */
AnnaBridge 189:f392fc9709a3 326 opaOutModeAPORT4YCH18 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH18), /**< APORT output to APORT4YCH18 pin enabled. */
AnnaBridge 189:f392fc9709a3 327 opaOutModeAPORT4YCH20 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH20), /**< APORT output to APORT4YCH20 pin enabled. */
AnnaBridge 189:f392fc9709a3 328 opaOutModeAPORT4YCH22 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH22), /**< APORT output to APORT4YCH22 pin enabled. */
AnnaBridge 189:f392fc9709a3 329 opaOutModeAPORT4YCH24 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH24), /**< APORT output to APORT4YCH24 pin enabled. */
AnnaBridge 189:f392fc9709a3 330 opaOutModeAPORT4YCH26 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH26), /**< APORT output to APORT4YCH26 pin enabled. */
AnnaBridge 189:f392fc9709a3 331 opaOutModeAPORT4YCH28 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH28), /**< APORT output to APORT4YCH28 pin enabled. */
AnnaBridge 189:f392fc9709a3 332 opaOutModeAPORT4YCH30 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH30), /**< APORT output to APORT4YCH30 pin enabled. */
AnnaBridge 189:f392fc9709a3 333 #endif /* defined(_SILICON_LABS_32B_SERIES_0) */
AnnaBridge 189:f392fc9709a3 334 } OPAMP_OutMode_TypeDef;
AnnaBridge 189:f392fc9709a3 335
AnnaBridge 189:f392fc9709a3 336 /** OPAMP gain values. */
AnnaBridge 189:f392fc9709a3 337 typedef enum {
AnnaBridge 189:f392fc9709a3 338 #if defined(_SILICON_LABS_32B_SERIES_0)
AnnaBridge 189:f392fc9709a3 339 opaResSelDefault = DAC_OPA0MUX_RESSEL_DEFAULT, /**< Default value when resistor ladder is unused. */
AnnaBridge 189:f392fc9709a3 340 opaResSelR2eq0_33R1 = DAC_OPA0MUX_RESSEL_RES0, /**< R2 = 0.33 * R1 */
AnnaBridge 189:f392fc9709a3 341 opaResSelR2eqR1 = DAC_OPA0MUX_RESSEL_RES1, /**< R2 = R1 */
AnnaBridge 189:f392fc9709a3 342 opaResSelR1eq1_67R1 = DAC_OPA0MUX_RESSEL_RES2, /**< R2 = 1.67 R1 */
AnnaBridge 189:f392fc9709a3 343 opaResSelR2eq2R1 = DAC_OPA0MUX_RESSEL_RES3, /**< R2 = 2 * R1 */
AnnaBridge 189:f392fc9709a3 344 opaResSelR2eq3R1 = DAC_OPA0MUX_RESSEL_RES4, /**< R2 = 3 * R1 */
AnnaBridge 189:f392fc9709a3 345 opaResSelR2eq4_33R1 = DAC_OPA0MUX_RESSEL_RES5, /**< R2 = 4.33 * R1 */
AnnaBridge 189:f392fc9709a3 346 opaResSelR2eq7R1 = DAC_OPA0MUX_RESSEL_RES6, /**< R2 = 7 * R1 */
AnnaBridge 189:f392fc9709a3 347 opaResSelR2eq15R1 = DAC_OPA0MUX_RESSEL_RES7 /**< R2 = 15 * R1 */
AnnaBridge 189:f392fc9709a3 348 #elif defined(_SILICON_LABS_32B_SERIES_1)
AnnaBridge 189:f392fc9709a3 349 opaResSelDefault = VDAC_OPA_MUX_RESSEL_DEFAULT, /**< Default value when resistor ladder is unused. */
AnnaBridge 189:f392fc9709a3 350 opaResSelR2eq0_33R1 = VDAC_OPA_MUX_RESSEL_RES0, /**< R2 = 0.33 * R1 */
AnnaBridge 189:f392fc9709a3 351 opaResSelR2eqR1 = VDAC_OPA_MUX_RESSEL_RES1, /**< R2 = R1 */
AnnaBridge 189:f392fc9709a3 352 opaResSelR1eq1_67R1 = VDAC_OPA_MUX_RESSEL_RES2, /**< R2 = 1.67 R1 */
AnnaBridge 189:f392fc9709a3 353 opaResSelR2eq2_2R1 = VDAC_OPA_MUX_RESSEL_RES3, /**< R2 = 2.2 * R1 */
AnnaBridge 189:f392fc9709a3 354 opaResSelR2eq3R1 = VDAC_OPA_MUX_RESSEL_RES4, /**< R2 = 3 * R1 */
AnnaBridge 189:f392fc9709a3 355 opaResSelR2eq4_33R1 = VDAC_OPA_MUX_RESSEL_RES5, /**< R2 = 4.33 * R1 */
AnnaBridge 189:f392fc9709a3 356 opaResSelR2eq7R1 = VDAC_OPA_MUX_RESSEL_RES6, /**< R2 = 7 * R1 */
AnnaBridge 189:f392fc9709a3 357 opaResSelR2eq15R1 = VDAC_OPA_MUX_RESSEL_RES7 /**< R2 = 15 * R1 */
AnnaBridge 189:f392fc9709a3 358 #endif /* defined(_SILICON_LABS_32B_SERIES_0) */
AnnaBridge 189:f392fc9709a3 359 } OPAMP_ResSel_TypeDef;
AnnaBridge 189:f392fc9709a3 360
AnnaBridge 189:f392fc9709a3 361 /** OPAMP resistor ladder input selector values. */
AnnaBridge 189:f392fc9709a3 362 typedef enum {
AnnaBridge 189:f392fc9709a3 363 #if defined(_SILICON_LABS_32B_SERIES_0)
AnnaBridge 189:f392fc9709a3 364 opaResInMuxDisable = DAC_OPA0MUX_RESINMUX_DISABLE, /**< Resistor ladder disabled. */
AnnaBridge 189:f392fc9709a3 365 opaResInMuxOpaIn = DAC_OPA0MUX_RESINMUX_OPA0INP, /**< Input from OPAx. */
AnnaBridge 189:f392fc9709a3 366 opaResInMuxNegPad = DAC_OPA0MUX_RESINMUX_NEGPAD, /**< Input from negative pad. */
AnnaBridge 189:f392fc9709a3 367 opaResInMuxPosPad = DAC_OPA0MUX_RESINMUX_POSPAD, /**< Input from positive pad. */
AnnaBridge 189:f392fc9709a3 368 opaResInMuxVss = DAC_OPA0MUX_RESINMUX_VSS /**< Input connected to Vss. */
AnnaBridge 189:f392fc9709a3 369 #elif defined(_SILICON_LABS_32B_SERIES_1)
AnnaBridge 189:f392fc9709a3 370 opaResInMuxDisable = VDAC_OPA_MUX_RESINMUX_DISABLE, /**< Resistor ladder disabled. */
AnnaBridge 189:f392fc9709a3 371 opaResInMuxOpaIn = VDAC_OPA_MUX_RESINMUX_OPANEXT, /**< Input from OPAx. */
AnnaBridge 189:f392fc9709a3 372 opaResInMuxNegPad = VDAC_OPA_MUX_RESINMUX_NEGPAD, /**< Input from negative pad. */
AnnaBridge 189:f392fc9709a3 373 opaResInMuxPosPad = VDAC_OPA_MUX_RESINMUX_POSPAD, /**< Input from positive pad. */
AnnaBridge 189:f392fc9709a3 374 opaResInMuxComPad = VDAC_OPA_MUX_RESINMUX_COMPAD, /**< Input from negative pad of OPA0.
AnnaBridge 189:f392fc9709a3 375 Direct input to support common reference. */
AnnaBridge 189:f392fc9709a3 376 opaResInMuxCenter = VDAC_OPA_MUX_RESINMUX_CENTER, /**< OPA0 and OPA1 Resmux connected to form fully
AnnaBridge 189:f392fc9709a3 377 differential instrumentation amplifier. */
AnnaBridge 189:f392fc9709a3 378 opaResInMuxVss = VDAC_OPA_MUX_RESINMUX_VSS, /**< Input connected to Vss. */
AnnaBridge 189:f392fc9709a3 379 #endif /* defined(_SILICON_LABS_32B_SERIES_0) */
AnnaBridge 189:f392fc9709a3 380 } OPAMP_ResInMux_TypeDef;
AnnaBridge 189:f392fc9709a3 381
AnnaBridge 189:f392fc9709a3 382 #if defined(_SILICON_LABS_32B_SERIES_1)
AnnaBridge 189:f392fc9709a3 383 typedef enum {
AnnaBridge 189:f392fc9709a3 384 opaPrsModeDefault = VDAC_OPA_CTRL_PRSMODE_DEFAULT, /**< Default value when PRS is not the trigger. */
AnnaBridge 189:f392fc9709a3 385 opaPrsModePulsed = VDAC_OPA_CTRL_PRSMODE_PULSED, /**< PRS trigger is a pulse that starts the OPAMP
AnnaBridge 189:f392fc9709a3 386 warmup sequence. The end of the warmup sequence
AnnaBridge 189:f392fc9709a3 387 is controlled by timeout settings in OPAxTIMER. */
AnnaBridge 189:f392fc9709a3 388 opaPrsModeTimed = VDAC_OPA_CTRL_PRSMODE_TIMED, /**< PRS trigger is a pulse long enough to provide the
AnnaBridge 189:f392fc9709a3 389 OPAMP warmup sequence. The end of the warmup
AnnaBridge 189:f392fc9709a3 390 sequence is controlled by the edge of the pulse. */
AnnaBridge 189:f392fc9709a3 391 } OPAMP_PrsMode_TypeDef;
AnnaBridge 189:f392fc9709a3 392
AnnaBridge 189:f392fc9709a3 393 typedef enum {
AnnaBridge 189:f392fc9709a3 394 opaPrsSelDefault = VDAC_OPA_CTRL_PRSSEL_DEFAULT, /**< Default value when PRS is not the trigger. */
AnnaBridge 189:f392fc9709a3 395 opaPrsSelCh0 = VDAC_OPA_CTRL_PRSSEL_PRSCH0, /**< PRS channel 0 triggers OPAMP. */
AnnaBridge 189:f392fc9709a3 396 opaPrsSelCh1 = VDAC_OPA_CTRL_PRSSEL_PRSCH1, /**< PRS channel 1 triggers OPAMP. */
AnnaBridge 189:f392fc9709a3 397 opaPrsSelCh2 = VDAC_OPA_CTRL_PRSSEL_PRSCH2, /**< PRS channel 2 triggers OPAMP. */
AnnaBridge 189:f392fc9709a3 398 opaPrsSelCh3 = VDAC_OPA_CTRL_PRSSEL_PRSCH3, /**< PRS channel 3 triggers OPAMP. */
AnnaBridge 189:f392fc9709a3 399 opaPrsSelCh4 = VDAC_OPA_CTRL_PRSSEL_PRSCH4, /**< PRS channel 4 triggers OPAMP. */
AnnaBridge 189:f392fc9709a3 400 opaPrsSelCh5 = VDAC_OPA_CTRL_PRSSEL_PRSCH5, /**< PRS channel 5 triggers OPAMP. */
AnnaBridge 189:f392fc9709a3 401 opaPrsSelCh6 = VDAC_OPA_CTRL_PRSSEL_PRSCH6, /**< PRS channel 6 triggers OPAMP. */
AnnaBridge 189:f392fc9709a3 402 opaPrsSelCh7 = VDAC_OPA_CTRL_PRSSEL_PRSCH7, /**< PRS channel 7 triggers OPAMP. */
AnnaBridge 189:f392fc9709a3 403 #if defined(VDAC_OPA_CTRL_PRSSEL_PRSCH8)
AnnaBridge 189:f392fc9709a3 404 opaPrsSelCh8 = VDAC_OPA_CTRL_PRSSEL_PRSCH8, /**< PRS channel 8 triggers OPAMP. */
AnnaBridge 189:f392fc9709a3 405 opaPrsSelCh9 = VDAC_OPA_CTRL_PRSSEL_PRSCH9, /**< PRS channel 9 triggers OPAMP. */
AnnaBridge 189:f392fc9709a3 406 opaPrsSelCh10 = VDAC_OPA_CTRL_PRSSEL_PRSCH10, /**< PRS channel 10 triggers OPAMP. */
AnnaBridge 189:f392fc9709a3 407 opaPrsSelCh11 = VDAC_OPA_CTRL_PRSSEL_PRSCH11, /**< PRS channel 11 triggers OPAMP. */
AnnaBridge 189:f392fc9709a3 408 #endif
AnnaBridge 189:f392fc9709a3 409 } OPAMP_PrsSel_TypeDef;
AnnaBridge 189:f392fc9709a3 410
AnnaBridge 189:f392fc9709a3 411 typedef enum {
AnnaBridge 189:f392fc9709a3 412 opaPrsOutDefault = VDAC_OPA_CTRL_PRSOUTMODE_DEFAULT, /**< Default value. */
AnnaBridge 189:f392fc9709a3 413 opaPrsOutWarm = VDAC_OPA_CTRL_PRSOUTMODE_WARM, /**< Warm status available on PRS. */
AnnaBridge 189:f392fc9709a3 414 opaPrsOutOutValid = VDAC_OPA_CTRL_PRSOUTMODE_OUTVALID, /**< Outvalid status available on PRS. */
AnnaBridge 189:f392fc9709a3 415 } OPAMP_PrsOut_TypeDef;
AnnaBridge 189:f392fc9709a3 416
AnnaBridge 189:f392fc9709a3 417 typedef enum {
AnnaBridge 189:f392fc9709a3 418 opaOutScaleDefault = VDAC_OPA_CTRL_OUTSCALE_DEFAULT, /**< Default OPAM output drive strength. */
AnnaBridge 189:f392fc9709a3 419 opaOutScaleFull = VDAC_OPA_CTRL_OUTSCALE_FULL, /**< OPAMP uses full output drive strength. */
AnnaBridge 189:f392fc9709a3 420 opaOutSacleHalf = VDAC_OPA_CTRL_OUTSCALE_HALF, /**< OPAMP uses half output drive strength. */
AnnaBridge 189:f392fc9709a3 421 } OPAMP_OutScale_Typedef;
AnnaBridge 189:f392fc9709a3 422
AnnaBridge 189:f392fc9709a3 423 typedef enum {
AnnaBridge 189:f392fc9709a3 424 opaDrvStrDefault = VDAC_OPA_CTRL_DRIVESTRENGTH_DEFAULT, /**< Default value. */
AnnaBridge 189:f392fc9709a3 425 opaDrvStrLowerAccLowStr = (0 << _VDAC_OPA_CTRL_DRIVESTRENGTH_SHIFT), /**< Lower accuracy with low drive stregth. */
AnnaBridge 189:f392fc9709a3 426 opaDrvStrLowAccLowStr = (1 << _VDAC_OPA_CTRL_DRIVESTRENGTH_SHIFT), /**< Low accuracy with low drive stregth. */
AnnaBridge 189:f392fc9709a3 427 opaDrvStrHighAccHighStr = (2 << _VDAC_OPA_CTRL_DRIVESTRENGTH_SHIFT), /**< High accuracy with high drive stregth. */
AnnaBridge 189:f392fc9709a3 428 opaDrvStrHigherAccHighStr = (3 << _VDAC_OPA_CTRL_DRIVESTRENGTH_SHIFT), /**< Higher accuracy with high drive stregth. */
AnnaBridge 189:f392fc9709a3 429 } OPAMP_DrvStr_Typedef;
AnnaBridge 189:f392fc9709a3 430 #endif /* defined(_SILICON_LABS_32B_SERIES_0) */
AnnaBridge 189:f392fc9709a3 431
AnnaBridge 189:f392fc9709a3 432 /*******************************************************************************
AnnaBridge 189:f392fc9709a3 433 ******************************* STRUCTS ***********************************
AnnaBridge 189:f392fc9709a3 434 ******************************************************************************/
AnnaBridge 189:f392fc9709a3 435
AnnaBridge 189:f392fc9709a3 436 /** OPAMP init structure. */
AnnaBridge 189:f392fc9709a3 437 typedef struct {
AnnaBridge 189:f392fc9709a3 438 OPAMP_NegSel_TypeDef negSel; /**< Select input source for negative terminal. */
AnnaBridge 189:f392fc9709a3 439 OPAMP_PosSel_TypeDef posSel; /**< Select input source for positive terminal. */
AnnaBridge 189:f392fc9709a3 440 OPAMP_OutMode_TypeDef outMode; /**< Output terminal connection. */
AnnaBridge 189:f392fc9709a3 441 OPAMP_ResSel_TypeDef resSel; /**< Select R2/R1 resistor ratio. */
AnnaBridge 189:f392fc9709a3 442 OPAMP_ResInMux_TypeDef resInMux; /**< Select input source for resistor ladder. */
AnnaBridge 189:f392fc9709a3 443 uint32_t outPen; /**< Alternate output enable bit mask. This value
AnnaBridge 189:f392fc9709a3 444 should consist of one or more of the
AnnaBridge 189:f392fc9709a3 445 @if DOXYDOC_P1_DEVICE
AnnaBridge 189:f392fc9709a3 446 DAC_OPA[opa#]MUX_OUTPEN_OUT[output#] flags
AnnaBridge 189:f392fc9709a3 447 (defined in \<part_name\>_dac.h) OR'ed together.
AnnaBridge 189:f392fc9709a3 448 @n @n
AnnaBridge 189:f392fc9709a3 449 For OPA0:
AnnaBridge 189:f392fc9709a3 450 @li DAC_OPA0MUX_OUTPEN_OUT0
AnnaBridge 189:f392fc9709a3 451 @li DAC_OPA0MUX_OUTPEN_OUT1
AnnaBridge 189:f392fc9709a3 452 @li DAC_OPA0MUX_OUTPEN_OUT2
AnnaBridge 189:f392fc9709a3 453 @li DAC_OPA0MUX_OUTPEN_OUT3
AnnaBridge 189:f392fc9709a3 454 @li DAC_OPA0MUX_OUTPEN_OUT4
AnnaBridge 189:f392fc9709a3 455
AnnaBridge 189:f392fc9709a3 456 For OPA1:
AnnaBridge 189:f392fc9709a3 457 @li DAC_OPA1MUX_OUTPEN_OUT0
AnnaBridge 189:f392fc9709a3 458 @li DAC_OPA1MUX_OUTPEN_OUT1
AnnaBridge 189:f392fc9709a3 459 @li DAC_OPA1MUX_OUTPEN_OUT2
AnnaBridge 189:f392fc9709a3 460 @li DAC_OPA1MUX_OUTPEN_OUT3
AnnaBridge 189:f392fc9709a3 461 @li DAC_OPA1MUX_OUTPEN_OUT4
AnnaBridge 189:f392fc9709a3 462
AnnaBridge 189:f392fc9709a3 463 For OPA2:
AnnaBridge 189:f392fc9709a3 464 @li DAC_OPA2MUX_OUTPEN_OUT0
AnnaBridge 189:f392fc9709a3 465 @li DAC_OPA2MUX_OUTPEN_OUT1
AnnaBridge 189:f392fc9709a3 466
AnnaBridge 189:f392fc9709a3 467 E.g: @n
AnnaBridge 189:f392fc9709a3 468 init.outPen = DAC_OPA0MUX_OUTPEN_OUT0 |
AnnaBridge 189:f392fc9709a3 469 DAC_OPA0MUX_OUTPEN_OUT2 |
AnnaBridge 189:f392fc9709a3 470 DAC_OPA0MUX_OUTPEN_OUT4;
AnnaBridge 189:f392fc9709a3 471
AnnaBridge 189:f392fc9709a3 472 @elseif DOXYDOC_P2_DEVICE
AnnaBridge 189:f392fc9709a3 473 VDAC_OPA_OUT_ALTOUTPADEN_OUT[output#] flags
AnnaBridge 189:f392fc9709a3 474 (defined in \<part_name\>_vdac.h) OR'ed together.
AnnaBridge 189:f392fc9709a3 475 @n @n
AnnaBridge 189:f392fc9709a3 476 @li VDAC_OPA_OUT_ALTOUTPADEN_OUT0
AnnaBridge 189:f392fc9709a3 477 @li VDAC_OPA_OUT_ALTOUTPADEN_OUT1
AnnaBridge 189:f392fc9709a3 478 @li VDAC_OPA_OUT_ALTOUTPADEN_OUT2
AnnaBridge 189:f392fc9709a3 479 @li VDAC_OPA_OUT_ALTOUTPADEN_OUT3
AnnaBridge 189:f392fc9709a3 480 @li VDAC_OPA_OUT_ALTOUTPADEN_OUT4
AnnaBridge 189:f392fc9709a3 481
AnnaBridge 189:f392fc9709a3 482 E.g: @n
AnnaBridge 189:f392fc9709a3 483 init.outPen = VDAC_OPA_OUT_ALTOUTPADEN_OUT0 |
AnnaBridge 189:f392fc9709a3 484 VDAC_OPA_OUT_ALTOUTPADEN_OUT2 |
AnnaBridge 189:f392fc9709a3 485 VDAC_OPA_OUT_ALTOUTPADEN_OUT4;
AnnaBridge 189:f392fc9709a3 486 @endif */
AnnaBridge 189:f392fc9709a3 487 #if defined(_SILICON_LABS_32B_SERIES_0)
AnnaBridge 189:f392fc9709a3 488 uint32_t bias; /**< Set OPAMP bias current. */
AnnaBridge 189:f392fc9709a3 489 bool halfBias; /**< Divide OPAMP bias current by 2. */
AnnaBridge 189:f392fc9709a3 490 bool lpfPosPadDisable; /**< Disable low pass filter on positive pad. */
AnnaBridge 189:f392fc9709a3 491 bool lpfNegPadDisable; /**< Disable low pass filter on negative pad. */
AnnaBridge 189:f392fc9709a3 492 bool nextOut; /**< Enable NEXTOUT signal source. */
AnnaBridge 189:f392fc9709a3 493 bool npEn; /**< Enable positive pad. */
AnnaBridge 189:f392fc9709a3 494 bool ppEn; /**< Enable negative pad. */
AnnaBridge 189:f392fc9709a3 495 bool shortInputs; /**< Short OPAMP input terminals. */
AnnaBridge 189:f392fc9709a3 496 bool hcmDisable; /**< Disable input rail-to-rail capability. */
AnnaBridge 189:f392fc9709a3 497 bool defaultOffset; /**< Use factory calibrated opamp offset value. */
AnnaBridge 189:f392fc9709a3 498 uint32_t offset; /**< Opamp offset value when @ref defaultOffset is
AnnaBridge 189:f392fc9709a3 499 false. */
AnnaBridge 189:f392fc9709a3 500 #elif defined(_SILICON_LABS_32B_SERIES_1)
AnnaBridge 189:f392fc9709a3 501 OPAMP_DrvStr_Typedef drvStr; /**< OPAx operation mode. */
AnnaBridge 189:f392fc9709a3 502 bool gain3xEn; /**< Enable 3x gain resistor ladder. */
AnnaBridge 189:f392fc9709a3 503 bool halfDrvStr; /**< Half or full output drive strength. */
AnnaBridge 189:f392fc9709a3 504 bool ugBwScale; /**< Unity gain bandwidth scaled by factor of 2.5. */
AnnaBridge 189:f392fc9709a3 505 bool prsEn; /**< Enable PRS as OPAMP trigger. */
AnnaBridge 189:f392fc9709a3 506 OPAMP_PrsMode_TypeDef prsMode; /**< Selects PRS trigger mode. */
AnnaBridge 189:f392fc9709a3 507 OPAMP_PrsSel_TypeDef prsSel; /**< PRS channel trigger select. */
AnnaBridge 189:f392fc9709a3 508 OPAMP_PrsOut_TypeDef prsOutSel; /**< PRS output select. */
AnnaBridge 189:f392fc9709a3 509 bool aportYMasterDisable; /**< Disable bus master request on APORT Y. */
AnnaBridge 189:f392fc9709a3 510 bool aportXMasterDisable; /**< Disable bus master request on APORT X. */
AnnaBridge 189:f392fc9709a3 511 uint32_t settleTime; /**< Number of clock cycles to drive the output. */
AnnaBridge 189:f392fc9709a3 512 uint32_t startupDly; /**< OPAx startup delay in us. */
AnnaBridge 189:f392fc9709a3 513 bool hcmDisable; /**< Disable input rail-to-rail capability. */
AnnaBridge 189:f392fc9709a3 514 bool defaultOffsetN; /**< Use factory calibrated opamp inverting input
AnnaBridge 189:f392fc9709a3 515 offset value. */
AnnaBridge 189:f392fc9709a3 516 uint32_t offsetN; /**< Opamp inverting input offset value when
AnnaBridge 189:f392fc9709a3 517 @ref defaultOffsetInv is false. */
AnnaBridge 189:f392fc9709a3 518 bool defaultOffsetP; /**< Use factory calibrated opamp non-inverting
AnnaBridge 189:f392fc9709a3 519 input offset value. */
AnnaBridge 189:f392fc9709a3 520 uint32_t offsetP; /**< Opamp non-inverting input offset value when
AnnaBridge 189:f392fc9709a3 521 @ref defaultOffsetNon is false. */
AnnaBridge 189:f392fc9709a3 522 #endif /* defined(_SILICON_LABS_32B_SERIES_1) */
AnnaBridge 189:f392fc9709a3 523 } OPAMP_Init_TypeDef;
AnnaBridge 189:f392fc9709a3 524
AnnaBridge 189:f392fc9709a3 525 #if defined(_SILICON_LABS_32B_SERIES_0)
AnnaBridge 189:f392fc9709a3 526 /** Configuration of OPA0/1 in unity gain voltage follower mode. */
AnnaBridge 189:f392fc9709a3 527 #define OPA_INIT_UNITY_GAIN \
AnnaBridge 189:f392fc9709a3 528 { \
AnnaBridge 189:f392fc9709a3 529 opaNegSelUnityGain, /* Unity gain. */ \
AnnaBridge 189:f392fc9709a3 530 opaPosSelPosPad, /* Pos input from pad. */ \
AnnaBridge 189:f392fc9709a3 531 opaOutModeMain, /* Main output enabled. */ \
AnnaBridge 189:f392fc9709a3 532 opaResSelDefault, /* Resistor ladder is not used. */ \
AnnaBridge 189:f392fc9709a3 533 opaResInMuxDisable, /* Resistor ladder disabled. */ \
AnnaBridge 189:f392fc9709a3 534 0, /* No alternate outputs enabled. */ \
AnnaBridge 189:f392fc9709a3 535 _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \
AnnaBridge 189:f392fc9709a3 536 _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \
AnnaBridge 189:f392fc9709a3 537 false, /* No low pass filter on pos pad. */ \
AnnaBridge 189:f392fc9709a3 538 false, /* No low pass filter on neg pad. */ \
AnnaBridge 189:f392fc9709a3 539 false, /* No nextout output enabled. */ \
AnnaBridge 189:f392fc9709a3 540 false, /* Neg pad disabled. */ \
AnnaBridge 189:f392fc9709a3 541 true, /* Pos pad enabled, used as signal input. */ \
AnnaBridge 189:f392fc9709a3 542 false, /* No shorting of inputs. */ \
AnnaBridge 189:f392fc9709a3 543 false, /* Rail-to-rail input enabled. */ \
AnnaBridge 189:f392fc9709a3 544 true, /* Use factory calibrated opamp offset. */ \
AnnaBridge 189:f392fc9709a3 545 0 /* Opamp offset value (not used). */ \
AnnaBridge 189:f392fc9709a3 546 }
AnnaBridge 189:f392fc9709a3 547
AnnaBridge 189:f392fc9709a3 548 /** Configuration of OPA2 in unity gain voltage follower mode. */
AnnaBridge 189:f392fc9709a3 549 #define OPA_INIT_UNITY_GAIN_OPA2 \
AnnaBridge 189:f392fc9709a3 550 { \
AnnaBridge 189:f392fc9709a3 551 opaNegSelUnityGain, /* Unity gain. */ \
AnnaBridge 189:f392fc9709a3 552 opaPosSelPosPad, /* Pos input from pad. */ \
AnnaBridge 189:f392fc9709a3 553 opaOutModeMain, /* Main output enabled. */ \
AnnaBridge 189:f392fc9709a3 554 opaResSelDefault, /* Resistor ladder is not used. */ \
AnnaBridge 189:f392fc9709a3 555 opaResInMuxDisable, /* Resistor ladder disabled. */ \
AnnaBridge 189:f392fc9709a3 556 DAC_OPA0MUX_OUTPEN_OUT0, /* Alternate output 0 enabled. */ \
AnnaBridge 189:f392fc9709a3 557 _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \
AnnaBridge 189:f392fc9709a3 558 _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \
AnnaBridge 189:f392fc9709a3 559 false, /* No low pass filter on pos pad. */ \
AnnaBridge 189:f392fc9709a3 560 false, /* No low pass filter on neg pad. */ \
AnnaBridge 189:f392fc9709a3 561 false, /* No nextout output enabled. */ \
AnnaBridge 189:f392fc9709a3 562 false, /* Neg pad disabled. */ \
AnnaBridge 189:f392fc9709a3 563 true, /* Pos pad enabled, used as signal input. */ \
AnnaBridge 189:f392fc9709a3 564 false, /* No shorting of inputs. */ \
AnnaBridge 189:f392fc9709a3 565 false, /* Rail-to-rail input enabled. */ \
AnnaBridge 189:f392fc9709a3 566 true, /* Use factory calibrated opamp offset. */ \
AnnaBridge 189:f392fc9709a3 567 0 /* Opamp offset value (not used). */ \
AnnaBridge 189:f392fc9709a3 568 }
AnnaBridge 189:f392fc9709a3 569
AnnaBridge 189:f392fc9709a3 570 /** Configuration of OPA0/1 in non-inverting amplifier mode. */
AnnaBridge 189:f392fc9709a3 571 #define OPA_INIT_NON_INVERTING \
AnnaBridge 189:f392fc9709a3 572 { \
AnnaBridge 189:f392fc9709a3 573 opaNegSelResTap, /* Neg input from resistor ladder tap. */ \
AnnaBridge 189:f392fc9709a3 574 opaPosSelPosPad, /* Pos input from pad. */ \
AnnaBridge 189:f392fc9709a3 575 opaOutModeMain, /* Main output enabled. */ \
AnnaBridge 189:f392fc9709a3 576 opaResSelR2eq0_33R1, /* R2 = 1/3 R1 */ \
AnnaBridge 189:f392fc9709a3 577 opaResInMuxNegPad, /* Resistor ladder input from neg pad. */ \
AnnaBridge 189:f392fc9709a3 578 0, /* No alternate outputs enabled. */ \
AnnaBridge 189:f392fc9709a3 579 _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \
AnnaBridge 189:f392fc9709a3 580 _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \
AnnaBridge 189:f392fc9709a3 581 false, /* No low pass filter on pos pad. */ \
AnnaBridge 189:f392fc9709a3 582 false, /* No low pass filter on neg pad. */ \
AnnaBridge 189:f392fc9709a3 583 false, /* No nextout output enabled. */ \
AnnaBridge 189:f392fc9709a3 584 true, /* Neg pad enabled, used as signal ground. */ \
AnnaBridge 189:f392fc9709a3 585 true, /* Pos pad enabled, used as signal input. */ \
AnnaBridge 189:f392fc9709a3 586 false, /* No shorting of inputs. */ \
AnnaBridge 189:f392fc9709a3 587 false, /* Rail-to-rail input enabled. */ \
AnnaBridge 189:f392fc9709a3 588 true, /* Use factory calibrated opamp offset. */ \
AnnaBridge 189:f392fc9709a3 589 0 /* Opamp offset value (not used). */ \
AnnaBridge 189:f392fc9709a3 590 }
AnnaBridge 189:f392fc9709a3 591
AnnaBridge 189:f392fc9709a3 592 /** Configuration of OPA2 in non-inverting amplifier mode. */
AnnaBridge 189:f392fc9709a3 593 #define OPA_INIT_NON_INVERTING_OPA2 \
AnnaBridge 189:f392fc9709a3 594 { \
AnnaBridge 189:f392fc9709a3 595 opaNegSelResTap, /* Neg input from resistor ladder tap. */ \
AnnaBridge 189:f392fc9709a3 596 opaPosSelPosPad, /* Pos input from pad. */ \
AnnaBridge 189:f392fc9709a3 597 opaOutModeMain, /* Main output enabled. */ \
AnnaBridge 189:f392fc9709a3 598 opaResSelR2eq0_33R1, /* R2 = 1/3 R1 */ \
AnnaBridge 189:f392fc9709a3 599 opaResInMuxNegPad, /* Resistor ladder input from neg pad. */ \
AnnaBridge 189:f392fc9709a3 600 DAC_OPA0MUX_OUTPEN_OUT0, /* Alternate output 0 enabled. */ \
AnnaBridge 189:f392fc9709a3 601 _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \
AnnaBridge 189:f392fc9709a3 602 _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \
AnnaBridge 189:f392fc9709a3 603 false, /* No low pass filter on pos pad. */ \
AnnaBridge 189:f392fc9709a3 604 false, /* No low pass filter on neg pad. */ \
AnnaBridge 189:f392fc9709a3 605 false, /* No nextout output enabled. */ \
AnnaBridge 189:f392fc9709a3 606 true, /* Neg pad enabled, used as signal ground. */ \
AnnaBridge 189:f392fc9709a3 607 true, /* Pos pad enabled, used as signal input. */ \
AnnaBridge 189:f392fc9709a3 608 false, /* No shorting of inputs. */ \
AnnaBridge 189:f392fc9709a3 609 false, /* Rail-to-rail input enabled. */ \
AnnaBridge 189:f392fc9709a3 610 true, /* Use factory calibrated opamp offset. */ \
AnnaBridge 189:f392fc9709a3 611 0 /* Opamp offset value (not used). */ \
AnnaBridge 189:f392fc9709a3 612 }
AnnaBridge 189:f392fc9709a3 613
AnnaBridge 189:f392fc9709a3 614 /** Configuration of OPA0/1 in inverting amplifier mode. */
AnnaBridge 189:f392fc9709a3 615 #define OPA_INIT_INVERTING \
AnnaBridge 189:f392fc9709a3 616 { \
AnnaBridge 189:f392fc9709a3 617 opaNegSelResTap, /* Neg input from resistor ladder tap. */ \
AnnaBridge 189:f392fc9709a3 618 opaPosSelPosPad, /* Pos input from pad. */ \
AnnaBridge 189:f392fc9709a3 619 opaOutModeMain, /* Main output enabled. */ \
AnnaBridge 189:f392fc9709a3 620 opaResSelR2eqR1, /* R2 = R1 */ \
AnnaBridge 189:f392fc9709a3 621 opaResInMuxNegPad, /* Resistor ladder input from neg pad. */ \
AnnaBridge 189:f392fc9709a3 622 0, /* No alternate outputs enabled. */ \
AnnaBridge 189:f392fc9709a3 623 _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \
AnnaBridge 189:f392fc9709a3 624 _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \
AnnaBridge 189:f392fc9709a3 625 false, /* No low pass filter on pos pad. */ \
AnnaBridge 189:f392fc9709a3 626 false, /* No low pass filter on neg pad. */ \
AnnaBridge 189:f392fc9709a3 627 false, /* No nextout output enabled. */ \
AnnaBridge 189:f392fc9709a3 628 true, /* Neg pad enabled, used as signal input. */ \
AnnaBridge 189:f392fc9709a3 629 true, /* Pos pad enabled, used as signal ground. */ \
AnnaBridge 189:f392fc9709a3 630 false, /* No shorting of inputs. */ \
AnnaBridge 189:f392fc9709a3 631 false, /* Rail-to-rail input enabled. */ \
AnnaBridge 189:f392fc9709a3 632 true, /* Use factory calibrated opamp offset. */ \
AnnaBridge 189:f392fc9709a3 633 0 /* Opamp offset value (not used). */ \
AnnaBridge 189:f392fc9709a3 634 }
AnnaBridge 189:f392fc9709a3 635
AnnaBridge 189:f392fc9709a3 636 /** Configuration of OPA2 in inverting amplifier mode. */
AnnaBridge 189:f392fc9709a3 637 #define OPA_INIT_INVERTING_OPA2 \
AnnaBridge 189:f392fc9709a3 638 { \
AnnaBridge 189:f392fc9709a3 639 opaNegSelResTap, /* Neg input from resistor ladder tap. */ \
AnnaBridge 189:f392fc9709a3 640 opaPosSelPosPad, /* Pos input from pad. */ \
AnnaBridge 189:f392fc9709a3 641 opaOutModeMain, /* Main output enabled. */ \
AnnaBridge 189:f392fc9709a3 642 opaResSelR2eqR1, /* R2 = R1 */ \
AnnaBridge 189:f392fc9709a3 643 opaResInMuxNegPad, /* Resistor ladder input from neg pad. */ \
AnnaBridge 189:f392fc9709a3 644 DAC_OPA0MUX_OUTPEN_OUT0, /* Alternate output 0 enabled. */ \
AnnaBridge 189:f392fc9709a3 645 _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \
AnnaBridge 189:f392fc9709a3 646 _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \
AnnaBridge 189:f392fc9709a3 647 false, /* No low pass filter on pos pad. */ \
AnnaBridge 189:f392fc9709a3 648 false, /* No low pass filter on neg pad. */ \
AnnaBridge 189:f392fc9709a3 649 false, /* No nextout output enabled. */ \
AnnaBridge 189:f392fc9709a3 650 true, /* Neg pad enabled, used as signal input. */ \
AnnaBridge 189:f392fc9709a3 651 true, /* Pos pad enabled, used as signal ground. */ \
AnnaBridge 189:f392fc9709a3 652 false, /* No shorting of inputs. */ \
AnnaBridge 189:f392fc9709a3 653 false, /* Rail-to-rail input enabled. */ \
AnnaBridge 189:f392fc9709a3 654 true, /* Use factory calibrated opamp offset. */ \
AnnaBridge 189:f392fc9709a3 655 0 /* Opamp offset value (not used). */ \
AnnaBridge 189:f392fc9709a3 656 }
AnnaBridge 189:f392fc9709a3 657
AnnaBridge 189:f392fc9709a3 658 /** Configuration of OPA0 in cascaded non-inverting amplifier mode. */
AnnaBridge 189:f392fc9709a3 659 #define OPA_INIT_CASCADED_NON_INVERTING_OPA0 \
AnnaBridge 189:f392fc9709a3 660 { \
AnnaBridge 189:f392fc9709a3 661 opaNegSelResTap, /* Neg input from resistor ladder tap. */ \
AnnaBridge 189:f392fc9709a3 662 opaPosSelPosPad, /* Pos input from pad. */ \
AnnaBridge 189:f392fc9709a3 663 opaOutModeAll, /* Both main and alternate outputs. */ \
AnnaBridge 189:f392fc9709a3 664 opaResSelR2eq0_33R1, /* R2 = 1/3 R1 */ \
AnnaBridge 189:f392fc9709a3 665 opaResInMuxNegPad, /* Resistor ladder input from neg pad. */ \
AnnaBridge 189:f392fc9709a3 666 0, /* No alternate outputs enabled. */ \
AnnaBridge 189:f392fc9709a3 667 _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \
AnnaBridge 189:f392fc9709a3 668 _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \
AnnaBridge 189:f392fc9709a3 669 false, /* No low pass filter on pos pad. */ \
AnnaBridge 189:f392fc9709a3 670 false, /* No low pass filter on neg pad. */ \
AnnaBridge 189:f392fc9709a3 671 true, /* Pass output to next stage (OPA1). */ \
AnnaBridge 189:f392fc9709a3 672 true, /* Neg pad enabled, used as signal ground. */ \
AnnaBridge 189:f392fc9709a3 673 true, /* Pos pad enabled, used as signal input. */ \
AnnaBridge 189:f392fc9709a3 674 false, /* No shorting of inputs. */ \
AnnaBridge 189:f392fc9709a3 675 false, /* Rail-to-rail input enabled. */ \
AnnaBridge 189:f392fc9709a3 676 true, /* Use factory calibrated opamp offset. */ \
AnnaBridge 189:f392fc9709a3 677 0 /* Opamp offset value (not used). */ \
AnnaBridge 189:f392fc9709a3 678 }
AnnaBridge 189:f392fc9709a3 679
AnnaBridge 189:f392fc9709a3 680 /** Configuration of OPA1 in cascaded non-inverting amplifier mode. */
AnnaBridge 189:f392fc9709a3 681 #define OPA_INIT_CASCADED_NON_INVERTING_OPA1 \
AnnaBridge 189:f392fc9709a3 682 { \
AnnaBridge 189:f392fc9709a3 683 opaNegSelResTap, /* Neg input from resistor ladder tap. */ \
AnnaBridge 189:f392fc9709a3 684 opaPosSelOpaIn, /* Pos input from OPA0 output. */ \
AnnaBridge 189:f392fc9709a3 685 opaOutModeAll, /* Both main and alternate outputs. */ \
AnnaBridge 189:f392fc9709a3 686 opaResSelR2eq0_33R1, /* R2 = 1/3 R1 */ \
AnnaBridge 189:f392fc9709a3 687 opaResInMuxNegPad, /* Resistor ladder input from neg pad. */ \
AnnaBridge 189:f392fc9709a3 688 0, /* No alternate outputs enabled. */ \
AnnaBridge 189:f392fc9709a3 689 _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \
AnnaBridge 189:f392fc9709a3 690 _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \
AnnaBridge 189:f392fc9709a3 691 false, /* No low pass filter on pos pad. */ \
AnnaBridge 189:f392fc9709a3 692 false, /* No low pass filter on neg pad. */ \
AnnaBridge 189:f392fc9709a3 693 true, /* Pass output to next stage (OPA2). */ \
AnnaBridge 189:f392fc9709a3 694 true, /* Neg pad enabled, used as signal ground. */ \
AnnaBridge 189:f392fc9709a3 695 false, /* Pos pad disabled. */ \
AnnaBridge 189:f392fc9709a3 696 false, /* No shorting of inputs. */ \
AnnaBridge 189:f392fc9709a3 697 false, /* Rail-to-rail input enabled. */ \
AnnaBridge 189:f392fc9709a3 698 true, /* Use factory calibrated opamp offset. */ \
AnnaBridge 189:f392fc9709a3 699 0 /* Opamp offset value (not used). */ \
AnnaBridge 189:f392fc9709a3 700 }
AnnaBridge 189:f392fc9709a3 701
AnnaBridge 189:f392fc9709a3 702 /** Configuration of OPA2 in cascaded non-inverting amplifier mode. */
AnnaBridge 189:f392fc9709a3 703 #define OPA_INIT_CASCADED_NON_INVERTING_OPA2 \
AnnaBridge 189:f392fc9709a3 704 { \
AnnaBridge 189:f392fc9709a3 705 opaNegSelResTap, /* Neg input from resistor ladder tap. */ \
AnnaBridge 189:f392fc9709a3 706 opaPosSelOpaIn, /* Pos input from OPA1 output. */ \
AnnaBridge 189:f392fc9709a3 707 opaOutModeMain, /* Main output enabled. */ \
AnnaBridge 189:f392fc9709a3 708 opaResSelR2eq0_33R1, /* R2 = 1/3 R1 */ \
AnnaBridge 189:f392fc9709a3 709 opaResInMuxNegPad, /* Resistor ladder input from neg pad. */ \
AnnaBridge 189:f392fc9709a3 710 DAC_OPA0MUX_OUTPEN_OUT0, /* Alternate output 0 enabled. */ \
AnnaBridge 189:f392fc9709a3 711 _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \
AnnaBridge 189:f392fc9709a3 712 _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \
AnnaBridge 189:f392fc9709a3 713 false, /* No low pass filter on pos pad. */ \
AnnaBridge 189:f392fc9709a3 714 false, /* No low pass filter on neg pad. */ \
AnnaBridge 189:f392fc9709a3 715 false, /* No nextout output enabled. */ \
AnnaBridge 189:f392fc9709a3 716 true, /* Neg pad enabled, used as signal ground. */ \
AnnaBridge 189:f392fc9709a3 717 false, /* Pos pad disabled. */ \
AnnaBridge 189:f392fc9709a3 718 false, /* No shorting of inputs. */ \
AnnaBridge 189:f392fc9709a3 719 false, /* Rail-to-rail input enabled. */ \
AnnaBridge 189:f392fc9709a3 720 true, /* Use factory calibrated opamp offset. */ \
AnnaBridge 189:f392fc9709a3 721 0 /* Opamp offset value (not used). */ \
AnnaBridge 189:f392fc9709a3 722 }
AnnaBridge 189:f392fc9709a3 723
AnnaBridge 189:f392fc9709a3 724 /** Configuration of OPA0 in cascaded inverting amplifier mode. */
AnnaBridge 189:f392fc9709a3 725 #define OPA_INIT_CASCADED_INVERTING_OPA0 \
AnnaBridge 189:f392fc9709a3 726 { \
AnnaBridge 189:f392fc9709a3 727 opaNegSelResTap, /* Neg input from resistor ladder tap. */ \
AnnaBridge 189:f392fc9709a3 728 opaPosSelPosPad, /* Pos input from pad. */ \
AnnaBridge 189:f392fc9709a3 729 opaOutModeAll, /* Both main and alternate outputs. */ \
AnnaBridge 189:f392fc9709a3 730 opaResSelR2eqR1, /* R2 = R1 */ \
AnnaBridge 189:f392fc9709a3 731 opaResInMuxNegPad, /* Resistor ladder input from neg pad. */ \
AnnaBridge 189:f392fc9709a3 732 0, /* No alternate outputs enabled. */ \
AnnaBridge 189:f392fc9709a3 733 _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \
AnnaBridge 189:f392fc9709a3 734 _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \
AnnaBridge 189:f392fc9709a3 735 false, /* No low pass filter on pos pad. */ \
AnnaBridge 189:f392fc9709a3 736 false, /* No low pass filter on neg pad. */ \
AnnaBridge 189:f392fc9709a3 737 true, /* Pass output to next stage (OPA1). */ \
AnnaBridge 189:f392fc9709a3 738 true, /* Neg pad enabled, used as signal input. */ \
AnnaBridge 189:f392fc9709a3 739 true, /* Pos pad enabled, used as signal ground. */ \
AnnaBridge 189:f392fc9709a3 740 false, /* No shorting of inputs. */ \
AnnaBridge 189:f392fc9709a3 741 false, /* Rail-to-rail input enabled. */ \
AnnaBridge 189:f392fc9709a3 742 true, /* Use factory calibrated opamp offset. */ \
AnnaBridge 189:f392fc9709a3 743 0 /* Opamp offset value (not used). */ \
AnnaBridge 189:f392fc9709a3 744 }
AnnaBridge 189:f392fc9709a3 745
AnnaBridge 189:f392fc9709a3 746 /** Configuration of OPA1 in cascaded inverting amplifier mode. */
AnnaBridge 189:f392fc9709a3 747 #define OPA_INIT_CASCADED_INVERTING_OPA1 \
AnnaBridge 189:f392fc9709a3 748 { \
AnnaBridge 189:f392fc9709a3 749 opaNegSelResTap, /* Neg input from resistor ladder tap. */ \
AnnaBridge 189:f392fc9709a3 750 opaPosSelPosPad, /* Pos input from pad. */ \
AnnaBridge 189:f392fc9709a3 751 opaOutModeAll, /* Both main and alternate outputs. */ \
AnnaBridge 189:f392fc9709a3 752 opaResSelR2eqR1, /* R2 = R1 */ \
AnnaBridge 189:f392fc9709a3 753 opaResInMuxOpaIn, /* Resistor ladder input from OPA0. */ \
AnnaBridge 189:f392fc9709a3 754 0, /* No alternate outputs enabled. */ \
AnnaBridge 189:f392fc9709a3 755 _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \
AnnaBridge 189:f392fc9709a3 756 _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \
AnnaBridge 189:f392fc9709a3 757 false, /* No low pass filter on pos pad. */ \
AnnaBridge 189:f392fc9709a3 758 false, /* No low pass filter on neg pad. */ \
AnnaBridge 189:f392fc9709a3 759 true, /* Pass output to next stage (OPA2). */ \
AnnaBridge 189:f392fc9709a3 760 false, /* Neg pad disabled. */ \
AnnaBridge 189:f392fc9709a3 761 true, /* Pos pad enabled, used as signal ground. */ \
AnnaBridge 189:f392fc9709a3 762 false, /* No shorting of inputs. */ \
AnnaBridge 189:f392fc9709a3 763 false, /* Rail-to-rail input enabled. */ \
AnnaBridge 189:f392fc9709a3 764 true, /* Use factory calibrated opamp offset. */ \
AnnaBridge 189:f392fc9709a3 765 0 /* Opamp offset value (not used). */ \
AnnaBridge 189:f392fc9709a3 766 }
AnnaBridge 189:f392fc9709a3 767
AnnaBridge 189:f392fc9709a3 768 /** Configuration of OPA2 in cascaded inverting amplifier mode. */
AnnaBridge 189:f392fc9709a3 769 #define OPA_INIT_CASCADED_INVERTING_OPA2 \
AnnaBridge 189:f392fc9709a3 770 { \
AnnaBridge 189:f392fc9709a3 771 opaNegSelResTap, /* Neg input from resistor ladder tap. */ \
AnnaBridge 189:f392fc9709a3 772 opaPosSelPosPad, /* Pos input from pad. */ \
AnnaBridge 189:f392fc9709a3 773 opaOutModeMain, /* Main output enabled. */ \
AnnaBridge 189:f392fc9709a3 774 opaResSelR2eqR1, /* R2 = R1 */ \
AnnaBridge 189:f392fc9709a3 775 opaResInMuxOpaIn, /* Resistor ladder input from OPA1. */ \
AnnaBridge 189:f392fc9709a3 776 DAC_OPA0MUX_OUTPEN_OUT0, /* Alternate output 0 enabled. */ \
AnnaBridge 189:f392fc9709a3 777 _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \
AnnaBridge 189:f392fc9709a3 778 _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \
AnnaBridge 189:f392fc9709a3 779 false, /* No low pass filter on pos pad. */ \
AnnaBridge 189:f392fc9709a3 780 false, /* No low pass filter on neg pad. */ \
AnnaBridge 189:f392fc9709a3 781 false, /* No nextout output enabled. */ \
AnnaBridge 189:f392fc9709a3 782 false, /* Neg pad disabled. */ \
AnnaBridge 189:f392fc9709a3 783 true, /* Pos pad enabled, used as signal ground. */ \
AnnaBridge 189:f392fc9709a3 784 false, /* No shorting of inputs. */ \
AnnaBridge 189:f392fc9709a3 785 false, /* Rail-to-rail input enabled. */ \
AnnaBridge 189:f392fc9709a3 786 true, /* Use factory calibrated opamp offset. */ \
AnnaBridge 189:f392fc9709a3 787 0 /* Opamp offset value (not used). */ \
AnnaBridge 189:f392fc9709a3 788 }
AnnaBridge 189:f392fc9709a3 789
AnnaBridge 189:f392fc9709a3 790 /** Configuration of OPA0 in two-opamp differential driver mode. */
AnnaBridge 189:f392fc9709a3 791 #define OPA_INIT_DIFF_DRIVER_OPA0 \
AnnaBridge 189:f392fc9709a3 792 { \
AnnaBridge 189:f392fc9709a3 793 opaNegSelUnityGain, /* Unity gain. */ \
AnnaBridge 189:f392fc9709a3 794 opaPosSelPosPad, /* Pos input from pad. */ \
AnnaBridge 189:f392fc9709a3 795 opaOutModeAll, /* Both main and alternate outputs. */ \
AnnaBridge 189:f392fc9709a3 796 opaResSelDefault, /* Resistor ladder is not used. */ \
AnnaBridge 189:f392fc9709a3 797 opaResInMuxDisable, /* Resistor ladder disabled. */ \
AnnaBridge 189:f392fc9709a3 798 0, /* No alternate outputs enabled. */ \
AnnaBridge 189:f392fc9709a3 799 _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \
AnnaBridge 189:f392fc9709a3 800 _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \
AnnaBridge 189:f392fc9709a3 801 false, /* No low pass filter on pos pad. */ \
AnnaBridge 189:f392fc9709a3 802 false, /* No low pass filter on neg pad. */ \
AnnaBridge 189:f392fc9709a3 803 true, /* Pass output to next stage (OPA1). */ \
AnnaBridge 189:f392fc9709a3 804 false, /* Neg pad disabled. */ \
AnnaBridge 189:f392fc9709a3 805 true, /* Pos pad enabled, used as signal input. */ \
AnnaBridge 189:f392fc9709a3 806 false, /* No shorting of inputs. */ \
AnnaBridge 189:f392fc9709a3 807 false, /* Rail-to-rail input enabled. */ \
AnnaBridge 189:f392fc9709a3 808 true, /* Use factory calibrated opamp offset. */ \
AnnaBridge 189:f392fc9709a3 809 0 /* Opamp offset value (not used). */ \
AnnaBridge 189:f392fc9709a3 810 }
AnnaBridge 189:f392fc9709a3 811
AnnaBridge 189:f392fc9709a3 812 /** Configuration of OPA1 in two-opamp differential driver mode. */
AnnaBridge 189:f392fc9709a3 813 #define OPA_INIT_DIFF_DRIVER_OPA1 \
AnnaBridge 189:f392fc9709a3 814 { \
AnnaBridge 189:f392fc9709a3 815 opaNegSelResTap, /* Neg input from resistor ladder tap. */ \
AnnaBridge 189:f392fc9709a3 816 opaPosSelPosPad, /* Pos input from pad. */ \
AnnaBridge 189:f392fc9709a3 817 opaOutModeMain, /* Main output enabled. */ \
AnnaBridge 189:f392fc9709a3 818 opaResSelR2eqR1, /* R2 = R1 */ \
AnnaBridge 189:f392fc9709a3 819 opaResInMuxOpaIn, /* Resistor ladder input from OPA0. */ \
AnnaBridge 189:f392fc9709a3 820 0, /* No alternate outputs enabled. */ \
AnnaBridge 189:f392fc9709a3 821 _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \
AnnaBridge 189:f392fc9709a3 822 _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \
AnnaBridge 189:f392fc9709a3 823 false, /* No low pass filter on pos pad. */ \
AnnaBridge 189:f392fc9709a3 824 false, /* No low pass filter on neg pad. */ \
AnnaBridge 189:f392fc9709a3 825 false, /* No nextout output enabled. */ \
AnnaBridge 189:f392fc9709a3 826 false, /* Neg pad disabled. */ \
AnnaBridge 189:f392fc9709a3 827 true, /* Pos pad enabled, used as signal ground. */ \
AnnaBridge 189:f392fc9709a3 828 false, /* No shorting of inputs. */ \
AnnaBridge 189:f392fc9709a3 829 false, /* Rail-to-rail input enabled. */ \
AnnaBridge 189:f392fc9709a3 830 true, /* Use factory calibrated opamp offset. */ \
AnnaBridge 189:f392fc9709a3 831 0 /* Opamp offset value (not used). */ \
AnnaBridge 189:f392fc9709a3 832 }
AnnaBridge 189:f392fc9709a3 833
AnnaBridge 189:f392fc9709a3 834 /** Configuration of OPA0 in three-opamp differential receiver mode. */
AnnaBridge 189:f392fc9709a3 835 #define OPA_INIT_DIFF_RECEIVER_OPA0 \
AnnaBridge 189:f392fc9709a3 836 { \
AnnaBridge 189:f392fc9709a3 837 opaNegSelUnityGain, /* Unity gain. */ \
AnnaBridge 189:f392fc9709a3 838 opaPosSelPosPad, /* Pos input from pad. */ \
AnnaBridge 189:f392fc9709a3 839 opaOutModeAll, /* Both main and alternate outputs. */ \
AnnaBridge 189:f392fc9709a3 840 opaResSelR2eqR1, /* R2 = R1 */ \
AnnaBridge 189:f392fc9709a3 841 opaResInMuxNegPad, /* Resistor ladder input from neg pad. */ \
AnnaBridge 189:f392fc9709a3 842 0, /* No alternate outputs enabled. */ \
AnnaBridge 189:f392fc9709a3 843 _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \
AnnaBridge 189:f392fc9709a3 844 _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \
AnnaBridge 189:f392fc9709a3 845 false, /* No low pass filter on pos pad. */ \
AnnaBridge 189:f392fc9709a3 846 false, /* No low pass filter on neg pad. */ \
AnnaBridge 189:f392fc9709a3 847 true, /* Pass output to next stage (OPA2). */ \
AnnaBridge 189:f392fc9709a3 848 true, /* Neg pad enabled, used as signal ground. */ \
AnnaBridge 189:f392fc9709a3 849 true, /* Pos pad enabled, used as signal input. */ \
AnnaBridge 189:f392fc9709a3 850 false, /* No shorting of inputs. */ \
AnnaBridge 189:f392fc9709a3 851 false, /* Rail-to-rail input enabled. */ \
AnnaBridge 189:f392fc9709a3 852 true, /* Use factory calibrated opamp offset. */ \
AnnaBridge 189:f392fc9709a3 853 0 /* Opamp offset value (not used). */ \
AnnaBridge 189:f392fc9709a3 854 }
AnnaBridge 189:f392fc9709a3 855
AnnaBridge 189:f392fc9709a3 856 /** Configuration of OPA1 in three-opamp differential receiver mode. */
AnnaBridge 189:f392fc9709a3 857 #define OPA_INIT_DIFF_RECEIVER_OPA1 \
AnnaBridge 189:f392fc9709a3 858 { \
AnnaBridge 189:f392fc9709a3 859 opaNegSelUnityGain, /* Unity gain. */ \
AnnaBridge 189:f392fc9709a3 860 opaPosSelPosPad, /* Pos input from pad. */ \
AnnaBridge 189:f392fc9709a3 861 opaOutModeAll, /* Both main and alternate outputs. */ \
AnnaBridge 189:f392fc9709a3 862 opaResSelDefault, /* Resistor ladder is not used. */ \
AnnaBridge 189:f392fc9709a3 863 opaResInMuxDisable, /* Disable resistor ladder. */ \
AnnaBridge 189:f392fc9709a3 864 0, /* No alternate outputs enabled. */ \
AnnaBridge 189:f392fc9709a3 865 _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \
AnnaBridge 189:f392fc9709a3 866 _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \
AnnaBridge 189:f392fc9709a3 867 false, /* No low pass filter on pos pad. */ \
AnnaBridge 189:f392fc9709a3 868 false, /* No low pass filter on neg pad. */ \
AnnaBridge 189:f392fc9709a3 869 true, /* Pass output to next stage (OPA2). */ \
AnnaBridge 189:f392fc9709a3 870 false, /* Neg pad disabled. */ \
AnnaBridge 189:f392fc9709a3 871 true, /* Pos pad enabled, used as signal input. */ \
AnnaBridge 189:f392fc9709a3 872 false, /* No shorting of inputs. */ \
AnnaBridge 189:f392fc9709a3 873 false, /* Rail-to-rail input enabled. */ \
AnnaBridge 189:f392fc9709a3 874 true, /* Use factory calibrated opamp offset. */ \
AnnaBridge 189:f392fc9709a3 875 0 /* Opamp offset value (not used). */ \
AnnaBridge 189:f392fc9709a3 876 }
AnnaBridge 189:f392fc9709a3 877
AnnaBridge 189:f392fc9709a3 878 /** Configuration of OPA2 in three-opamp differential receiver mode. */
AnnaBridge 189:f392fc9709a3 879 #define OPA_INIT_DIFF_RECEIVER_OPA2 \
AnnaBridge 189:f392fc9709a3 880 { \
AnnaBridge 189:f392fc9709a3 881 opaNegSelResTap, /* Input from resistor ladder tap. */ \
AnnaBridge 189:f392fc9709a3 882 opaPosSelResTapOpa0, /* Input from OPA0 resistor ladder tap. */ \
AnnaBridge 189:f392fc9709a3 883 opaOutModeMain, /* Main output enabled. */ \
AnnaBridge 189:f392fc9709a3 884 opaResSelR2eqR1, /* R2 = R1 */ \
AnnaBridge 189:f392fc9709a3 885 opaResInMuxOpaIn, /* Resistor ladder input from OPA1. */ \
AnnaBridge 189:f392fc9709a3 886 DAC_OPA0MUX_OUTPEN_OUT0, /* Enable alternate output 0. */ \
AnnaBridge 189:f392fc9709a3 887 _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \
AnnaBridge 189:f392fc9709a3 888 _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \
AnnaBridge 189:f392fc9709a3 889 false, /* No low pass filter on pos pad. */ \
AnnaBridge 189:f392fc9709a3 890 false, /* No low pass filter on neg pad. */ \
AnnaBridge 189:f392fc9709a3 891 false, /* No nextout output enabled. */ \
AnnaBridge 189:f392fc9709a3 892 false, /* Neg pad disabled. */ \
AnnaBridge 189:f392fc9709a3 893 false, /* Pos pad disabled. */ \
AnnaBridge 189:f392fc9709a3 894 false, /* No shorting of inputs. */ \
AnnaBridge 189:f392fc9709a3 895 false, /* Rail-to-rail input enabled. */ \
AnnaBridge 189:f392fc9709a3 896 true, /* Use factory calibrated opamp offset. */ \
AnnaBridge 189:f392fc9709a3 897 0 /* Opamp offset value (not used). */ \
AnnaBridge 189:f392fc9709a3 898 }
AnnaBridge 189:f392fc9709a3 899
AnnaBridge 189:f392fc9709a3 900 #elif defined(_SILICON_LABS_32B_SERIES_1)
AnnaBridge 189:f392fc9709a3 901 /** Configuration of OPA in unity gain voltage follower mode. */
AnnaBridge 189:f392fc9709a3 902 #define OPA_INIT_UNITY_GAIN \
AnnaBridge 189:f392fc9709a3 903 { \
AnnaBridge 189:f392fc9709a3 904 opaNegSelUnityGain, /* Unity gain. */ \
AnnaBridge 189:f392fc9709a3 905 opaPosSelPosPad, /* Pos input from pad. */ \
AnnaBridge 189:f392fc9709a3 906 opaOutModeMain, /* Main output enabled. */ \
AnnaBridge 189:f392fc9709a3 907 opaResSelDefault, /* Resistor ladder is not used. */ \
AnnaBridge 189:f392fc9709a3 908 opaResInMuxDisable, /* Resistor ladder disabled. */ \
AnnaBridge 189:f392fc9709a3 909 0, /* No alternate outputs enabled. */ \
AnnaBridge 189:f392fc9709a3 910 opaDrvStrDefault, /* Default opamp operation mode. */ \
AnnaBridge 189:f392fc9709a3 911 false, /* Disable 3x gain setting. */ \
AnnaBridge 189:f392fc9709a3 912 false, /* Use full output drive strength. */ \
AnnaBridge 189:f392fc9709a3 913 false, /* Disable unity-gain bandwidth scaling. */ \
AnnaBridge 189:f392fc9709a3 914 false, /* Opamp triggered by OPAxEN. */ \
AnnaBridge 189:f392fc9709a3 915 opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \
AnnaBridge 189:f392fc9709a3 916 opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \
AnnaBridge 189:f392fc9709a3 917 opaPrsOutDefault, /* Default PRS output setting. */ \
AnnaBridge 189:f392fc9709a3 918 false, /* Bus mastering enabled on APORTX. */ \
AnnaBridge 189:f392fc9709a3 919 false, /* Bus mastering enabled on APORTY. */ \
AnnaBridge 189:f392fc9709a3 920 3, /* 3us settle time with default DrvStr. */ \
AnnaBridge 189:f392fc9709a3 921 0, /* No startup delay. */ \
AnnaBridge 189:f392fc9709a3 922 false, /* Rail-to-rail input enabled. */ \
AnnaBridge 189:f392fc9709a3 923 true, /* Use calibrated inverting offset. */ \
AnnaBridge 189:f392fc9709a3 924 0, /* Opamp offset value (not used). */ \
AnnaBridge 189:f392fc9709a3 925 true, /* Use calibrated non-inverting offset. */ \
AnnaBridge 189:f392fc9709a3 926 0 /* Opamp offset value (not used). */ \
AnnaBridge 189:f392fc9709a3 927 }
AnnaBridge 189:f392fc9709a3 928
AnnaBridge 189:f392fc9709a3 929 /** Configuration of OPA in non-inverting amplifier mode. */
AnnaBridge 189:f392fc9709a3 930 #define OPA_INIT_NON_INVERTING \
AnnaBridge 189:f392fc9709a3 931 { \
AnnaBridge 189:f392fc9709a3 932 opaNegSelResTap, /* Neg input from resistor ladder tap. */ \
AnnaBridge 189:f392fc9709a3 933 opaPosSelPosPad, /* Pos input from pad. */ \
AnnaBridge 189:f392fc9709a3 934 opaOutModeMain, /* Main output enabled. */ \
AnnaBridge 189:f392fc9709a3 935 opaResSelR2eq0_33R1, /* R2 = 1/3 R1 */ \
AnnaBridge 189:f392fc9709a3 936 opaResInMuxNegPad, /* Resistor ladder input from neg pad. */ \
AnnaBridge 189:f392fc9709a3 937 0, /* No alternate outputs enabled. */ \
AnnaBridge 189:f392fc9709a3 938 opaDrvStrDefault, /* Default opamp operation mode. */ \
AnnaBridge 189:f392fc9709a3 939 false, /* Disable 3x gain setting. */ \
AnnaBridge 189:f392fc9709a3 940 false, /* Use full output drive strength. */ \
AnnaBridge 189:f392fc9709a3 941 false, /* Disable unity-gain bandwidth scaling. */ \
AnnaBridge 189:f392fc9709a3 942 false, /* Opamp triggered by OPAxEN. */ \
AnnaBridge 189:f392fc9709a3 943 opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \
AnnaBridge 189:f392fc9709a3 944 opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \
AnnaBridge 189:f392fc9709a3 945 opaPrsOutDefault, /* Default PRS output setting. */ \
AnnaBridge 189:f392fc9709a3 946 false, /* Bus mastering enabled on APORTX. */ \
AnnaBridge 189:f392fc9709a3 947 false, /* Bus mastering enabled on APORTY. */ \
AnnaBridge 189:f392fc9709a3 948 3, /* 3us settle time with default DrvStr. */ \
AnnaBridge 189:f392fc9709a3 949 0, /* No startup delay. */ \
AnnaBridge 189:f392fc9709a3 950 false, /* Rail-to-rail input enabled. */ \
AnnaBridge 189:f392fc9709a3 951 true, /* Use calibrated inverting offset. */ \
AnnaBridge 189:f392fc9709a3 952 0, /* Opamp offset value (not used). */ \
AnnaBridge 189:f392fc9709a3 953 true, /* Use calibrated non-inverting offset. */ \
AnnaBridge 189:f392fc9709a3 954 0 /* Opamp offset value (not used). */ \
AnnaBridge 189:f392fc9709a3 955 }
AnnaBridge 189:f392fc9709a3 956
AnnaBridge 189:f392fc9709a3 957 /** Configuration of OPA in inverting amplifier mode. */
AnnaBridge 189:f392fc9709a3 958 #define OPA_INIT_INVERTING \
AnnaBridge 189:f392fc9709a3 959 { \
AnnaBridge 189:f392fc9709a3 960 opaNegSelResTap, /* Neg input from resistor ladder tap. */ \
AnnaBridge 189:f392fc9709a3 961 opaPosSelPosPad, /* Pos input from pad. */ \
AnnaBridge 189:f392fc9709a3 962 opaOutModeMain, /* Main output enabled. */ \
AnnaBridge 189:f392fc9709a3 963 opaResSelR2eqR1, /* R2 = R1 */ \
AnnaBridge 189:f392fc9709a3 964 opaResInMuxNegPad, /* Resistor ladder input from neg pad. */ \
AnnaBridge 189:f392fc9709a3 965 0, /* No alternate outputs enabled. */ \
AnnaBridge 189:f392fc9709a3 966 opaDrvStrDefault, /* Default opamp operation mode. */ \
AnnaBridge 189:f392fc9709a3 967 false, /* Disable 3x gain setting. */ \
AnnaBridge 189:f392fc9709a3 968 false, /* Use full output drive strength. */ \
AnnaBridge 189:f392fc9709a3 969 false, /* Disable unity-gain bandwidth scaling. */ \
AnnaBridge 189:f392fc9709a3 970 false, /* Opamp triggered by OPAxEN. */ \
AnnaBridge 189:f392fc9709a3 971 opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \
AnnaBridge 189:f392fc9709a3 972 opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \
AnnaBridge 189:f392fc9709a3 973 opaPrsOutDefault, /* Default PRS output setting. */ \
AnnaBridge 189:f392fc9709a3 974 false, /* Bus mastering enabled on APORTX. */ \
AnnaBridge 189:f392fc9709a3 975 false, /* Bus mastering enabled on APORTY. */ \
AnnaBridge 189:f392fc9709a3 976 3, /* 3us settle time with default DrvStr. */ \
AnnaBridge 189:f392fc9709a3 977 0, /* No startup delay. */ \
AnnaBridge 189:f392fc9709a3 978 false, /* Rail-to-rail input enabled. */ \
AnnaBridge 189:f392fc9709a3 979 true, /* Use calibrated inverting offset. */ \
AnnaBridge 189:f392fc9709a3 980 0, /* Opamp offset value (not used). */ \
AnnaBridge 189:f392fc9709a3 981 true, /* Use calibrated non-inverting offset. */ \
AnnaBridge 189:f392fc9709a3 982 0 /* Opamp offset value (not used). */ \
AnnaBridge 189:f392fc9709a3 983 }
AnnaBridge 189:f392fc9709a3 984
AnnaBridge 189:f392fc9709a3 985 /** Configuration of OPA0 in cascaded non-inverting amplifier mode. */
AnnaBridge 189:f392fc9709a3 986 #define OPA_INIT_CASCADED_NON_INVERTING_OPA0 \
AnnaBridge 189:f392fc9709a3 987 { \
AnnaBridge 189:f392fc9709a3 988 opaNegSelResTap, /* Neg input from resistor ladder tap. */ \
AnnaBridge 189:f392fc9709a3 989 opaPosSelPosPad, /* Pos input from pad. */ \
AnnaBridge 189:f392fc9709a3 990 opaOutModeMain, /* Main output enabled. */ \
AnnaBridge 189:f392fc9709a3 991 opaResSelR2eq0_33R1, /* R2 = 1/3 R1 */ \
AnnaBridge 189:f392fc9709a3 992 opaResInMuxNegPad, /* Resistor ladder input from neg pad. */ \
AnnaBridge 189:f392fc9709a3 993 0, /* No alternate outputs enabled. */ \
AnnaBridge 189:f392fc9709a3 994 opaDrvStrDefault, /* Default opamp operation mode. */ \
AnnaBridge 189:f392fc9709a3 995 false, /* Disable 3x gain setting. */ \
AnnaBridge 189:f392fc9709a3 996 false, /* Use full output drive strength. */ \
AnnaBridge 189:f392fc9709a3 997 false, /* Disable unity-gain bandwidth scaling. */ \
AnnaBridge 189:f392fc9709a3 998 false, /* Opamp triggered by OPAxEN. */ \
AnnaBridge 189:f392fc9709a3 999 opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \
AnnaBridge 189:f392fc9709a3 1000 opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \
AnnaBridge 189:f392fc9709a3 1001 opaPrsOutDefault, /* Default PRS output setting. */ \
AnnaBridge 189:f392fc9709a3 1002 false, /* Bus mastering enabled on APORTX. */ \
AnnaBridge 189:f392fc9709a3 1003 false, /* Bus mastering enabled on APORTY. */ \
AnnaBridge 189:f392fc9709a3 1004 3, /* 3us settle time with default DrvStr. */ \
AnnaBridge 189:f392fc9709a3 1005 0, /* No startup delay. */ \
AnnaBridge 189:f392fc9709a3 1006 false, /* Rail-to-rail input enabled. */ \
AnnaBridge 189:f392fc9709a3 1007 true, /* Use calibrated inverting offset. */ \
AnnaBridge 189:f392fc9709a3 1008 0, /* Opamp offset value (not used). */ \
AnnaBridge 189:f392fc9709a3 1009 true, /* Use calibrated non-inverting offset. */ \
AnnaBridge 189:f392fc9709a3 1010 0 /* Opamp offset value (not used). */ \
AnnaBridge 189:f392fc9709a3 1011 }
AnnaBridge 189:f392fc9709a3 1012
AnnaBridge 189:f392fc9709a3 1013 /** Configuration of OPA1 in cascaded non-inverting amplifier mode. */
AnnaBridge 189:f392fc9709a3 1014 #define OPA_INIT_CASCADED_NON_INVERTING_OPA1 \
AnnaBridge 189:f392fc9709a3 1015 { \
AnnaBridge 189:f392fc9709a3 1016 opaNegSelResTap, /* Neg input from resistor ladder tap. */ \
AnnaBridge 189:f392fc9709a3 1017 opaPosSelOpaIn, /* Pos input from OPA0 output. */ \
AnnaBridge 189:f392fc9709a3 1018 opaOutModeMain, /* Main output enabled. */ \
AnnaBridge 189:f392fc9709a3 1019 opaResSelR2eq0_33R1, /* R2 = 1/3 R1 */ \
AnnaBridge 189:f392fc9709a3 1020 opaResInMuxNegPad, /* Resistor ladder input from neg pad. */ \
AnnaBridge 189:f392fc9709a3 1021 0, /* No alternate outputs enabled. */ \
AnnaBridge 189:f392fc9709a3 1022 opaDrvStrDefault, /* Default opamp operation mode. */ \
AnnaBridge 189:f392fc9709a3 1023 false, /* Disable 3x gain setting. */ \
AnnaBridge 189:f392fc9709a3 1024 false, /* Use full output drive strength. */ \
AnnaBridge 189:f392fc9709a3 1025 false, /* Disable unity-gain bandwidth scaling. */ \
AnnaBridge 189:f392fc9709a3 1026 false, /* Opamp triggered by OPAxEN. */ \
AnnaBridge 189:f392fc9709a3 1027 opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \
AnnaBridge 189:f392fc9709a3 1028 opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \
AnnaBridge 189:f392fc9709a3 1029 opaPrsOutDefault, /* Default PRS output setting. */ \
AnnaBridge 189:f392fc9709a3 1030 false, /* Bus mastering enabled on APORTX. */ \
AnnaBridge 189:f392fc9709a3 1031 false, /* Bus mastering enabled on APORTY. */ \
AnnaBridge 189:f392fc9709a3 1032 3, /* 3us settle time with default DrvStr. */ \
AnnaBridge 189:f392fc9709a3 1033 0, /* No startup delay. */ \
AnnaBridge 189:f392fc9709a3 1034 false, /* Rail-to-rail input enabled. */ \
AnnaBridge 189:f392fc9709a3 1035 true, /* Use calibrated inverting offset. */ \
AnnaBridge 189:f392fc9709a3 1036 0, /* Opamp offset value (not used). */ \
AnnaBridge 189:f392fc9709a3 1037 true, /* Use calibrated non-inverting offset. */ \
AnnaBridge 189:f392fc9709a3 1038 0 /* Opamp offset value (not used). */ \
AnnaBridge 189:f392fc9709a3 1039 }
AnnaBridge 189:f392fc9709a3 1040
AnnaBridge 189:f392fc9709a3 1041 /** Configuration of OPA2 in cascaded non-inverting amplifier mode. */
AnnaBridge 189:f392fc9709a3 1042 #define OPA_INIT_CASCADED_NON_INVERTING_OPA2 \
AnnaBridge 189:f392fc9709a3 1043 { \
AnnaBridge 189:f392fc9709a3 1044 opaNegSelResTap, /* Neg input from resistor ladder tap. */ \
AnnaBridge 189:f392fc9709a3 1045 opaPosSelOpaIn, /* Pos input from OPA1 output. */ \
AnnaBridge 189:f392fc9709a3 1046 opaOutModeMain, /* Main output enabled. */ \
AnnaBridge 189:f392fc9709a3 1047 opaResSelR2eq0_33R1, /* R2 = 1/3 R1 */ \
AnnaBridge 189:f392fc9709a3 1048 opaResInMuxNegPad, /* Resistor ladder input from neg pad. */ \
AnnaBridge 189:f392fc9709a3 1049 0, /* No alternate outputs enabled. */ \
AnnaBridge 189:f392fc9709a3 1050 opaDrvStrDefault, /* Default opamp operation mode. */ \
AnnaBridge 189:f392fc9709a3 1051 false, /* Disable 3x gain setting. */ \
AnnaBridge 189:f392fc9709a3 1052 false, /* Use full output drive strength. */ \
AnnaBridge 189:f392fc9709a3 1053 false, /* Disable unity-gain bandwidth scaling. */ \
AnnaBridge 189:f392fc9709a3 1054 false, /* Opamp triggered by OPAxEN. */ \
AnnaBridge 189:f392fc9709a3 1055 opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \
AnnaBridge 189:f392fc9709a3 1056 opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \
AnnaBridge 189:f392fc9709a3 1057 opaPrsOutDefault, /* Default PRS output setting. */ \
AnnaBridge 189:f392fc9709a3 1058 false, /* Bus mastering enabled on APORTX. */ \
AnnaBridge 189:f392fc9709a3 1059 false, /* Bus mastering enabled on APORTY. */ \
AnnaBridge 189:f392fc9709a3 1060 3, /* 3us settle time with default DrvStr. */ \
AnnaBridge 189:f392fc9709a3 1061 0, /* No startup delay. */ \
AnnaBridge 189:f392fc9709a3 1062 false, /* Rail-to-rail input enabled. */ \
AnnaBridge 189:f392fc9709a3 1063 true, /* Use calibrated inverting offset. */ \
AnnaBridge 189:f392fc9709a3 1064 0, /* Opamp offset value (not used). */ \
AnnaBridge 189:f392fc9709a3 1065 true, /* Use calibrated non-inverting offset. */ \
AnnaBridge 189:f392fc9709a3 1066 0 /* Opamp offset value (not used). */ \
AnnaBridge 189:f392fc9709a3 1067 }
AnnaBridge 189:f392fc9709a3 1068
AnnaBridge 189:f392fc9709a3 1069 /** Configuration of OPA0 in cascaded inverting amplifier mode. */
AnnaBridge 189:f392fc9709a3 1070 #define OPA_INIT_CASCADED_INVERTING_OPA0 \
AnnaBridge 189:f392fc9709a3 1071 { \
AnnaBridge 189:f392fc9709a3 1072 opaNegSelResTap, /* Neg input from resistor ladder tap. */ \
AnnaBridge 189:f392fc9709a3 1073 opaPosSelPosPad, /* Pos input from pad. */ \
AnnaBridge 189:f392fc9709a3 1074 opaOutModeMain, /* Main output enabled. */ \
AnnaBridge 189:f392fc9709a3 1075 opaResSelR2eqR1, /* R2 = R1 */ \
AnnaBridge 189:f392fc9709a3 1076 opaResInMuxNegPad, /* Resistor ladder input from neg pad. */ \
AnnaBridge 189:f392fc9709a3 1077 0, /* No alternate outputs enabled. */ \
AnnaBridge 189:f392fc9709a3 1078 opaDrvStrDefault, /* Default opamp operation mode. */ \
AnnaBridge 189:f392fc9709a3 1079 false, /* Disable 3x gain setting. */ \
AnnaBridge 189:f392fc9709a3 1080 false, /* Use full output drive strength. */ \
AnnaBridge 189:f392fc9709a3 1081 false, /* Disable unity-gain bandwidth scaling. */ \
AnnaBridge 189:f392fc9709a3 1082 false, /* Opamp triggered by OPAxEN. */ \
AnnaBridge 189:f392fc9709a3 1083 opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \
AnnaBridge 189:f392fc9709a3 1084 opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \
AnnaBridge 189:f392fc9709a3 1085 opaPrsOutDefault, /* Default PRS output setting. */ \
AnnaBridge 189:f392fc9709a3 1086 false, /* Bus mastering enabled on APORTX. */ \
AnnaBridge 189:f392fc9709a3 1087 false, /* Bus mastering enabled on APORTY. */ \
AnnaBridge 189:f392fc9709a3 1088 3, /* 3us settle time with default DrvStr. */ \
AnnaBridge 189:f392fc9709a3 1089 0, /* No startup delay. */ \
AnnaBridge 189:f392fc9709a3 1090 false, /* Rail-to-rail input enabled. */ \
AnnaBridge 189:f392fc9709a3 1091 true, /* Use calibrated inverting offset. */ \
AnnaBridge 189:f392fc9709a3 1092 0, /* Opamp offset value (not used). */ \
AnnaBridge 189:f392fc9709a3 1093 true, /* Use calibrated non-inverting offset. */ \
AnnaBridge 189:f392fc9709a3 1094 0 /* Opamp offset value (not used). */ \
AnnaBridge 189:f392fc9709a3 1095 }
AnnaBridge 189:f392fc9709a3 1096
AnnaBridge 189:f392fc9709a3 1097 /** Configuration of OPA1 in cascaded inverting amplifier mode. */
AnnaBridge 189:f392fc9709a3 1098 #define OPA_INIT_CASCADED_INVERTING_OPA1 \
AnnaBridge 189:f392fc9709a3 1099 { \
AnnaBridge 189:f392fc9709a3 1100 opaNegSelResTap, /* Neg input from resistor ladder tap. */ \
AnnaBridge 189:f392fc9709a3 1101 opaPosSelPosPad, /* Pos input from pad. */ \
AnnaBridge 189:f392fc9709a3 1102 opaOutModeMain, /* Main output enabled. */ \
AnnaBridge 189:f392fc9709a3 1103 opaResSelR2eqR1, /* R2 = R1 */ \
AnnaBridge 189:f392fc9709a3 1104 opaResInMuxOpaIn, /* Resistor ladder input from OPA0. */ \
AnnaBridge 189:f392fc9709a3 1105 0, /* No alternate outputs enabled. */ \
AnnaBridge 189:f392fc9709a3 1106 opaDrvStrDefault, /* Default opamp operation mode. */ \
AnnaBridge 189:f392fc9709a3 1107 false, /* Disable 3x gain setting. */ \
AnnaBridge 189:f392fc9709a3 1108 false, /* Use full output drive strength. */ \
AnnaBridge 189:f392fc9709a3 1109 false, /* Disable unity-gain bandwidth scaling. */ \
AnnaBridge 189:f392fc9709a3 1110 false, /* Opamp triggered by OPAxEN. */ \
AnnaBridge 189:f392fc9709a3 1111 opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \
AnnaBridge 189:f392fc9709a3 1112 opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \
AnnaBridge 189:f392fc9709a3 1113 opaPrsOutDefault, /* Default PRS output setting. */ \
AnnaBridge 189:f392fc9709a3 1114 false, /* Bus mastering enabled on APORTX. */ \
AnnaBridge 189:f392fc9709a3 1115 false, /* Bus mastering enabled on APORTY. */ \
AnnaBridge 189:f392fc9709a3 1116 3, /* 3us settle time with default DrvStr. */ \
AnnaBridge 189:f392fc9709a3 1117 0, /* No startup delay. */ \
AnnaBridge 189:f392fc9709a3 1118 false, /* Rail-to-rail input enabled. */ \
AnnaBridge 189:f392fc9709a3 1119 true, /* Use calibrated inverting offset. */ \
AnnaBridge 189:f392fc9709a3 1120 0, /* Opamp offset value (not used). */ \
AnnaBridge 189:f392fc9709a3 1121 true, /* Use calibrated non-inverting offset. */ \
AnnaBridge 189:f392fc9709a3 1122 0 /* Opamp offset value (not used). */ \
AnnaBridge 189:f392fc9709a3 1123 }
AnnaBridge 189:f392fc9709a3 1124
AnnaBridge 189:f392fc9709a3 1125 /** Configuration of OPA2 in cascaded inverting amplifier mode. */
AnnaBridge 189:f392fc9709a3 1126 #define OPA_INIT_CASCADED_INVERTING_OPA2 \
AnnaBridge 189:f392fc9709a3 1127 { \
AnnaBridge 189:f392fc9709a3 1128 opaNegSelResTap, /* Neg input from resistor ladder tap. */ \
AnnaBridge 189:f392fc9709a3 1129 opaPosSelPosPad, /* Pos input from pad. */ \
AnnaBridge 189:f392fc9709a3 1130 opaOutModeMain, /* Main output enabled. */ \
AnnaBridge 189:f392fc9709a3 1131 opaResSelR2eqR1, /* R2 = R1 */ \
AnnaBridge 189:f392fc9709a3 1132 opaResInMuxOpaIn, /* Resistor ladder input from OPA1. */ \
AnnaBridge 189:f392fc9709a3 1133 0, /* No alternate outputs enabled. */ \
AnnaBridge 189:f392fc9709a3 1134 opaDrvStrDefault, /* Default opamp operation mode. */ \
AnnaBridge 189:f392fc9709a3 1135 false, /* Disable 3x gain setting. */ \
AnnaBridge 189:f392fc9709a3 1136 false, /* Use full output drive strength. */ \
AnnaBridge 189:f392fc9709a3 1137 false, /* Disable unity-gain bandwidth scaling. */ \
AnnaBridge 189:f392fc9709a3 1138 false, /* Opamp triggered by OPAxEN. */ \
AnnaBridge 189:f392fc9709a3 1139 opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \
AnnaBridge 189:f392fc9709a3 1140 opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \
AnnaBridge 189:f392fc9709a3 1141 opaPrsOutDefault, /* Default PRS output setting. */ \
AnnaBridge 189:f392fc9709a3 1142 false, /* Bus mastering enabled on APORTX. */ \
AnnaBridge 189:f392fc9709a3 1143 false, /* Bus mastering enabled on APORTY. */ \
AnnaBridge 189:f392fc9709a3 1144 3, /* 3us settle time with default DrvStr. */ \
AnnaBridge 189:f392fc9709a3 1145 0, /* No startup delay. */ \
AnnaBridge 189:f392fc9709a3 1146 false, /* Rail-to-rail input enabled. */ \
AnnaBridge 189:f392fc9709a3 1147 true, /* Use calibrated inverting offset. */ \
AnnaBridge 189:f392fc9709a3 1148 0, /* Opamp offset value (not used). */ \
AnnaBridge 189:f392fc9709a3 1149 true, /* Use calibrated non-inverting offset. */ \
AnnaBridge 189:f392fc9709a3 1150 0 /* Opamp offset value (not used). */ \
AnnaBridge 189:f392fc9709a3 1151 }
AnnaBridge 189:f392fc9709a3 1152
AnnaBridge 189:f392fc9709a3 1153 /** Configuration of OPA0 in two-opamp differential driver mode. */
AnnaBridge 189:f392fc9709a3 1154 #define OPA_INIT_DIFF_DRIVER_OPA0 \
AnnaBridge 189:f392fc9709a3 1155 { \
AnnaBridge 189:f392fc9709a3 1156 opaNegSelUnityGain, /* Unity gain. */ \
AnnaBridge 189:f392fc9709a3 1157 opaPosSelPosPad, /* Pos input from pad. */ \
AnnaBridge 189:f392fc9709a3 1158 opaOutModeMain, /* Main output enabled. */ \
AnnaBridge 189:f392fc9709a3 1159 opaResSelDefault, /* Resistor ladder is not used. */ \
AnnaBridge 189:f392fc9709a3 1160 opaResInMuxDisable, /* Resistor ladder disabled. */ \
AnnaBridge 189:f392fc9709a3 1161 0, /* No alternate outputs enabled. */ \
AnnaBridge 189:f392fc9709a3 1162 opaDrvStrDefault, /* Default opamp operation mode. */ \
AnnaBridge 189:f392fc9709a3 1163 false, /* Disable 3x gain setting. */ \
AnnaBridge 189:f392fc9709a3 1164 false, /* Use full output drive strength. */ \
AnnaBridge 189:f392fc9709a3 1165 false, /* Disable unity-gain bandwidth scaling. */ \
AnnaBridge 189:f392fc9709a3 1166 false, /* Opamp triggered by OPAxEN. */ \
AnnaBridge 189:f392fc9709a3 1167 opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \
AnnaBridge 189:f392fc9709a3 1168 opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \
AnnaBridge 189:f392fc9709a3 1169 opaPrsOutDefault, /* Default PRS output setting. */ \
AnnaBridge 189:f392fc9709a3 1170 false, /* Bus mastering enabled on APORTX. */ \
AnnaBridge 189:f392fc9709a3 1171 false, /* Bus mastering enabled on APORTY. */ \
AnnaBridge 189:f392fc9709a3 1172 3, /* 3us settle time with default DrvStr. */ \
AnnaBridge 189:f392fc9709a3 1173 0, /* No startup delay. */ \
AnnaBridge 189:f392fc9709a3 1174 false, /* Rail-to-rail input enabled. */ \
AnnaBridge 189:f392fc9709a3 1175 true, /* Use calibrated inverting offset. */ \
AnnaBridge 189:f392fc9709a3 1176 0, /* Opamp offset value (not used). */ \
AnnaBridge 189:f392fc9709a3 1177 true, /* Use calibrated non-inverting offset. */ \
AnnaBridge 189:f392fc9709a3 1178 0 /* Opamp offset value (not used). */ \
AnnaBridge 189:f392fc9709a3 1179 }
AnnaBridge 189:f392fc9709a3 1180
AnnaBridge 189:f392fc9709a3 1181 /** Configuration of OPA1 in two-opamp differential driver mode. */
AnnaBridge 189:f392fc9709a3 1182 #define OPA_INIT_DIFF_DRIVER_OPA1 \
AnnaBridge 189:f392fc9709a3 1183 { \
AnnaBridge 189:f392fc9709a3 1184 opaNegSelResTap, /* Neg input from resistor ladder tap. */ \
AnnaBridge 189:f392fc9709a3 1185 opaPosSelPosPad, /* Pos input from pad. */ \
AnnaBridge 189:f392fc9709a3 1186 opaOutModeMain, /* Main output enabled. */ \
AnnaBridge 189:f392fc9709a3 1187 opaResSelR2eqR1, /* R2 = R1 */ \
AnnaBridge 189:f392fc9709a3 1188 opaResInMuxOpaIn, /* Resistor ladder input from OPA0. */ \
AnnaBridge 189:f392fc9709a3 1189 0, /* No alternate outputs enabled. */ \
AnnaBridge 189:f392fc9709a3 1190 opaDrvStrDefault, /* Default opamp operation mode. */ \
AnnaBridge 189:f392fc9709a3 1191 false, /* Disable 3x gain setting. */ \
AnnaBridge 189:f392fc9709a3 1192 false, /* Use full output drive strength. */ \
AnnaBridge 189:f392fc9709a3 1193 false, /* Disable unity-gain bandwidth scaling. */ \
AnnaBridge 189:f392fc9709a3 1194 false, /* Opamp triggered by OPAxEN. */ \
AnnaBridge 189:f392fc9709a3 1195 opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \
AnnaBridge 189:f392fc9709a3 1196 opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \
AnnaBridge 189:f392fc9709a3 1197 opaPrsOutDefault, /* Default PRS output setting. */ \
AnnaBridge 189:f392fc9709a3 1198 false, /* Bus mastering enabled on APORTX. */ \
AnnaBridge 189:f392fc9709a3 1199 false, /* Bus mastering enabled on APORTY. */ \
AnnaBridge 189:f392fc9709a3 1200 3, /* 3us settle time with default DrvStr. */ \
AnnaBridge 189:f392fc9709a3 1201 0, /* No startup delay. */ \
AnnaBridge 189:f392fc9709a3 1202 false, /* Rail-to-rail input enabled. */ \
AnnaBridge 189:f392fc9709a3 1203 true, /* Use calibrated inverting offset. */ \
AnnaBridge 189:f392fc9709a3 1204 0, /* Opamp offset value (not used). */ \
AnnaBridge 189:f392fc9709a3 1205 true, /* Use calibrated non-inverting offset. */ \
AnnaBridge 189:f392fc9709a3 1206 0 /* Opamp offset value (not used). */ \
AnnaBridge 189:f392fc9709a3 1207 }
AnnaBridge 189:f392fc9709a3 1208
AnnaBridge 189:f392fc9709a3 1209 /** Configuration of OPA0 in three-opamp differential receiver mode. */
AnnaBridge 189:f392fc9709a3 1210 #define OPA_INIT_DIFF_RECEIVER_OPA0 \
AnnaBridge 189:f392fc9709a3 1211 { \
AnnaBridge 189:f392fc9709a3 1212 opaNegSelUnityGain, /* Unity gain. */ \
AnnaBridge 189:f392fc9709a3 1213 opaPosSelPosPad, /* Pos input from pad. */ \
AnnaBridge 189:f392fc9709a3 1214 opaOutModeMain, /* Main output enabled. */ \
AnnaBridge 189:f392fc9709a3 1215 opaResSelR2eqR1, /* R2 = R1 */ \
AnnaBridge 189:f392fc9709a3 1216 opaResInMuxNegPad, /* Resistor ladder input from neg pad. */ \
AnnaBridge 189:f392fc9709a3 1217 0, /* No alternate outputs enabled. */ \
AnnaBridge 189:f392fc9709a3 1218 opaDrvStrDefault, /* Default opamp operation mode. */ \
AnnaBridge 189:f392fc9709a3 1219 false, /* Disable 3x gain setting. */ \
AnnaBridge 189:f392fc9709a3 1220 false, /* Use full output drive strength. */ \
AnnaBridge 189:f392fc9709a3 1221 false, /* Disable unity-gain bandwidth scaling. */ \
AnnaBridge 189:f392fc9709a3 1222 false, /* Opamp triggered by OPAxEN. */ \
AnnaBridge 189:f392fc9709a3 1223 opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \
AnnaBridge 189:f392fc9709a3 1224 opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \
AnnaBridge 189:f392fc9709a3 1225 opaPrsOutDefault, /* Default PRS output setting. */ \
AnnaBridge 189:f392fc9709a3 1226 false, /* Bus mastering enabled on APORTX. */ \
AnnaBridge 189:f392fc9709a3 1227 false, /* Bus mastering enabled on APORTY. */ \
AnnaBridge 189:f392fc9709a3 1228 3, /* 3us settle time with default DrvStr. */ \
AnnaBridge 189:f392fc9709a3 1229 0, /* No startup delay. */ \
AnnaBridge 189:f392fc9709a3 1230 false, /* Rail-to-rail input enabled. */ \
AnnaBridge 189:f392fc9709a3 1231 true, /* Use calibrated inverting offset. */ \
AnnaBridge 189:f392fc9709a3 1232 0, /* Opamp offset value (not used). */ \
AnnaBridge 189:f392fc9709a3 1233 true, /* Use calibrated non-inverting offset. */ \
AnnaBridge 189:f392fc9709a3 1234 0 /* Opamp offset value (not used). */ \
AnnaBridge 189:f392fc9709a3 1235 }
AnnaBridge 189:f392fc9709a3 1236
AnnaBridge 189:f392fc9709a3 1237 /** Configuration of OPA1 in three-opamp differential receiver mode. */
AnnaBridge 189:f392fc9709a3 1238 #define OPA_INIT_DIFF_RECEIVER_OPA1 \
AnnaBridge 189:f392fc9709a3 1239 { \
AnnaBridge 189:f392fc9709a3 1240 opaNegSelUnityGain, /* Unity gain. */ \
AnnaBridge 189:f392fc9709a3 1241 opaPosSelPosPad, /* Pos input from pad. */ \
AnnaBridge 189:f392fc9709a3 1242 opaOutModeMain, /* Main output enabled. */ \
AnnaBridge 189:f392fc9709a3 1243 opaResSelDefault, /* Resistor ladder is not used. */ \
AnnaBridge 189:f392fc9709a3 1244 opaResInMuxDisable, /* Disable resistor ladder. */ \
AnnaBridge 189:f392fc9709a3 1245 0, /* No alternate outputs enabled. */ \
AnnaBridge 189:f392fc9709a3 1246 opaDrvStrDefault, /* Default opamp operation mode. */ \
AnnaBridge 189:f392fc9709a3 1247 false, /* Disable 3x gain setting. */ \
AnnaBridge 189:f392fc9709a3 1248 false, /* Use full output drive strength. */ \
AnnaBridge 189:f392fc9709a3 1249 false, /* Disable unity-gain bandwidth scaling. */ \
AnnaBridge 189:f392fc9709a3 1250 false, /* Opamp triggered by OPAxEN. */ \
AnnaBridge 189:f392fc9709a3 1251 opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \
AnnaBridge 189:f392fc9709a3 1252 opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \
AnnaBridge 189:f392fc9709a3 1253 opaPrsOutDefault, /* Default PRS output setting. */ \
AnnaBridge 189:f392fc9709a3 1254 false, /* Bus mastering enabled on APORTX. */ \
AnnaBridge 189:f392fc9709a3 1255 false, /* Bus mastering enabled on APORTY. */ \
AnnaBridge 189:f392fc9709a3 1256 3, /* 3us settle time with default DrvStr. */ \
AnnaBridge 189:f392fc9709a3 1257 0, /* No startup delay. */ \
AnnaBridge 189:f392fc9709a3 1258 false, /* Rail-to-rail input enabled. */ \
AnnaBridge 189:f392fc9709a3 1259 true, /* Use calibrated inverting offset. */ \
AnnaBridge 189:f392fc9709a3 1260 0, /* Opamp offset value (not used). */ \
AnnaBridge 189:f392fc9709a3 1261 true, /* Use calibrated non-inverting offset. */ \
AnnaBridge 189:f392fc9709a3 1262 0 /* Opamp offset value (not used). */ \
AnnaBridge 189:f392fc9709a3 1263 }
AnnaBridge 189:f392fc9709a3 1264
AnnaBridge 189:f392fc9709a3 1265 /** Configuration of OPA2 in three-opamp differential receiver mode. */
AnnaBridge 189:f392fc9709a3 1266 #define OPA_INIT_DIFF_RECEIVER_OPA2 \
AnnaBridge 189:f392fc9709a3 1267 { \
AnnaBridge 189:f392fc9709a3 1268 opaNegSelResTap, /* Input from resistor ladder tap. */ \
AnnaBridge 189:f392fc9709a3 1269 opaPosSelResTap, /* Input from OPA0 resistor ladder tap. */ \
AnnaBridge 189:f392fc9709a3 1270 opaOutModeMain, /* Main output enabled. */ \
AnnaBridge 189:f392fc9709a3 1271 opaResSelR2eqR1, /* R2 = R1 */ \
AnnaBridge 189:f392fc9709a3 1272 opaResInMuxOpaIn, /* Resistor ladder input from OPA1. */ \
AnnaBridge 189:f392fc9709a3 1273 0, /* No alternate outputs enabled. */ \
AnnaBridge 189:f392fc9709a3 1274 opaDrvStrDefault, /* Default opamp operation mode. */ \
AnnaBridge 189:f392fc9709a3 1275 false, /* Disable 3x gain setting. */ \
AnnaBridge 189:f392fc9709a3 1276 false, /* Use full output drive strength. */ \
AnnaBridge 189:f392fc9709a3 1277 false, /* Disable unity-gain bandwidth scaling. */ \
AnnaBridge 189:f392fc9709a3 1278 false, /* Opamp triggered by OPAxEN. */ \
AnnaBridge 189:f392fc9709a3 1279 opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \
AnnaBridge 189:f392fc9709a3 1280 opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \
AnnaBridge 189:f392fc9709a3 1281 opaPrsOutDefault, /* Default PRS output setting. */ \
AnnaBridge 189:f392fc9709a3 1282 false, /* Bus mastering enabled on APORTX. */ \
AnnaBridge 189:f392fc9709a3 1283 false, /* Bus mastering enabled on APORTY. */ \
AnnaBridge 189:f392fc9709a3 1284 3, /* 3us settle time with default DrvStr. */ \
AnnaBridge 189:f392fc9709a3 1285 0, /* No startup delay. */ \
AnnaBridge 189:f392fc9709a3 1286 false, /* Rail-to-rail input enabled. */ \
AnnaBridge 189:f392fc9709a3 1287 true, /* Use calibrated inverting offset. */ \
AnnaBridge 189:f392fc9709a3 1288 0, /* Opamp offset value (not used). */ \
AnnaBridge 189:f392fc9709a3 1289 true, /* Use calibrated non-inverting offset. */ \
AnnaBridge 189:f392fc9709a3 1290 0 /* Opamp offset value (not used). */ \
AnnaBridge 189:f392fc9709a3 1291 }
AnnaBridge 189:f392fc9709a3 1292
AnnaBridge 189:f392fc9709a3 1293 /** Configuration of OPA0 in two-opamp instrumentation amplifier mode. */
AnnaBridge 189:f392fc9709a3 1294 #define OPA_INIT_INSTR_AMP_OPA0 \
AnnaBridge 189:f392fc9709a3 1295 { \
AnnaBridge 189:f392fc9709a3 1296 opaNegSelResTap, /* Input from resistor ladder tap. */ \
AnnaBridge 189:f392fc9709a3 1297 opaPosSelPosPad, /* Pos input from pad. */ \
AnnaBridge 189:f392fc9709a3 1298 opaOutModeMain, /* Main output enabled. */ \
AnnaBridge 189:f392fc9709a3 1299 opaResSelR2eqR1, /* R2 = R1 */ \
AnnaBridge 189:f392fc9709a3 1300 opaResInMuxCenter, /* OPA0/OPA1 resistor ladders connected. */ \
AnnaBridge 189:f392fc9709a3 1301 0, /* No alternate outputs enabled. */ \
AnnaBridge 189:f392fc9709a3 1302 opaDrvStrDefault, /* Default opamp operation mode. */ \
AnnaBridge 189:f392fc9709a3 1303 false, /* Disable 3x gain setting. */ \
AnnaBridge 189:f392fc9709a3 1304 false, /* Use full output drive strength. */ \
AnnaBridge 189:f392fc9709a3 1305 false, /* Disable unity-gain bandwidth scaling. */ \
AnnaBridge 189:f392fc9709a3 1306 false, /* Opamp triggered by OPAxEN. */ \
AnnaBridge 189:f392fc9709a3 1307 opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \
AnnaBridge 189:f392fc9709a3 1308 opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \
AnnaBridge 189:f392fc9709a3 1309 opaPrsOutDefault, /* Default PRS output setting. */ \
AnnaBridge 189:f392fc9709a3 1310 false, /* Bus mastering enabled on APORTX. */ \
AnnaBridge 189:f392fc9709a3 1311 false, /* Bus mastering enabled on APORTY. */ \
AnnaBridge 189:f392fc9709a3 1312 3, /* 3us settle time with default DrvStr. */ \
AnnaBridge 189:f392fc9709a3 1313 0, /* No startup delay. */ \
AnnaBridge 189:f392fc9709a3 1314 false, /* Rail-to-rail input enabled. */ \
AnnaBridge 189:f392fc9709a3 1315 true, /* Use calibrated inverting offset. */ \
AnnaBridge 189:f392fc9709a3 1316 0, /* Opamp offset value (not used). */ \
AnnaBridge 189:f392fc9709a3 1317 true, /* Use calibrated non-inverting offset. */ \
AnnaBridge 189:f392fc9709a3 1318 0 /* Opamp offset value (not used). */ \
AnnaBridge 189:f392fc9709a3 1319 }
AnnaBridge 189:f392fc9709a3 1320
AnnaBridge 189:f392fc9709a3 1321 /** Configuration of OPA1 in two-opamp instrumentation amplifier mode. */
AnnaBridge 189:f392fc9709a3 1322 #define OPA_INIT_INSTR_AMP_OPA1 \
AnnaBridge 189:f392fc9709a3 1323 { \
AnnaBridge 189:f392fc9709a3 1324 opaNegSelNegPad, /* Neg input from pad. */ \
AnnaBridge 189:f392fc9709a3 1325 opaPosSelResTap, /* Input from resistor ladder tap. */ \
AnnaBridge 189:f392fc9709a3 1326 opaOutModeMain, /* Main output enabled. */ \
AnnaBridge 189:f392fc9709a3 1327 opaResSelR2eqR1, /* R2 = R1 */ \
AnnaBridge 189:f392fc9709a3 1328 opaResInMuxCenter, /* OPA0/OPA1 resistor ladders connected. */ \
AnnaBridge 189:f392fc9709a3 1329 0, /* No alternate outputs enabled. */ \
AnnaBridge 189:f392fc9709a3 1330 opaDrvStrDefault, /* Default opamp operation mode. */ \
AnnaBridge 189:f392fc9709a3 1331 false, /* Disable 3x gain setting. */ \
AnnaBridge 189:f392fc9709a3 1332 false, /* Use full output drive strength. */ \
AnnaBridge 189:f392fc9709a3 1333 false, /* Disable unity-gain bandwidth scaling. */ \
AnnaBridge 189:f392fc9709a3 1334 false, /* Opamp triggered by OPAxEN. */ \
AnnaBridge 189:f392fc9709a3 1335 opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \
AnnaBridge 189:f392fc9709a3 1336 opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \
AnnaBridge 189:f392fc9709a3 1337 opaPrsOutDefault, /* Default PRS output setting. */ \
AnnaBridge 189:f392fc9709a3 1338 false, /* Bus mastering enabled on APORTX. */ \
AnnaBridge 189:f392fc9709a3 1339 false, /* Bus mastering enabled on APORTY. */ \
AnnaBridge 189:f392fc9709a3 1340 3, /* 3us settle time with default DrvStr. */ \
AnnaBridge 189:f392fc9709a3 1341 0, /* No startup delay. */ \
AnnaBridge 189:f392fc9709a3 1342 false, /* Rail-to-rail input enabled. */ \
AnnaBridge 189:f392fc9709a3 1343 true, /* Use calibrated inverting offset. */ \
AnnaBridge 189:f392fc9709a3 1344 0, /* Opamp offset value (not used). */ \
AnnaBridge 189:f392fc9709a3 1345 true, /* Use calibrated non-inverting offset. */ \
AnnaBridge 189:f392fc9709a3 1346 0 /* Opamp offset value (not used). */ \
AnnaBridge 189:f392fc9709a3 1347 }
AnnaBridge 189:f392fc9709a3 1348
AnnaBridge 189:f392fc9709a3 1349 #endif /* defined(_SILICON_LABS_32B_SERIES_0) */
AnnaBridge 189:f392fc9709a3 1350
AnnaBridge 189:f392fc9709a3 1351 /*******************************************************************************
AnnaBridge 189:f392fc9709a3 1352 ***************************** PROTOTYPES **********************************
AnnaBridge 189:f392fc9709a3 1353 ******************************************************************************/
AnnaBridge 189:f392fc9709a3 1354
AnnaBridge 189:f392fc9709a3 1355 #if defined(_SILICON_LABS_32B_SERIES_0)
AnnaBridge 189:f392fc9709a3 1356 void OPAMP_Disable(DAC_TypeDef *dac, OPAMP_TypeDef opa);
AnnaBridge 189:f392fc9709a3 1357 void OPAMP_Enable(DAC_TypeDef *dac, OPAMP_TypeDef opa, const OPAMP_Init_TypeDef *init);
AnnaBridge 189:f392fc9709a3 1358 #elif defined(_SILICON_LABS_32B_SERIES_1)
AnnaBridge 189:f392fc9709a3 1359 void OPAMP_Disable(VDAC_TypeDef *dac, OPAMP_TypeDef opa);
AnnaBridge 189:f392fc9709a3 1360 void OPAMP_Enable(VDAC_TypeDef *dac, OPAMP_TypeDef opa, const OPAMP_Init_TypeDef *init);
AnnaBridge 189:f392fc9709a3 1361 #endif /* defined(_SILICON_LABS_32B_SERIES_0) */
AnnaBridge 189:f392fc9709a3 1362
AnnaBridge 189:f392fc9709a3 1363 /** @} (end addtogroup OPAMP) */
AnnaBridge 189:f392fc9709a3 1364 /** @} (end addtogroup emlib) */
AnnaBridge 189:f392fc9709a3 1365
AnnaBridge 189:f392fc9709a3 1366 #ifdef __cplusplus
AnnaBridge 189:f392fc9709a3 1367 }
AnnaBridge 189:f392fc9709a3 1368 #endif
AnnaBridge 189:f392fc9709a3 1369
AnnaBridge 189:f392fc9709a3 1370 #endif /* (defined(OPAMP_PRESENT) && (OPAMP_COUNT == 1))
AnnaBridge 189:f392fc9709a3 1371 || defined(VDAC_PRESENT) && (VDAC_COUNT > 0) */
AnnaBridge 189:f392fc9709a3 1372 #endif /* EM_OPAMP_H */