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targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_ll_rcc.c@165:e614a9f1c9e2, 2017-05-26 (annotated)

Committer:: AnnaBridge
Date:: Fri May 26 12:39:01 2017 +0100
Revision:: 165:e614a9f1c9e2
Parent:: 157:ff67d9f36b67
Child:: 186:707f6e361f3e

This updates the lib to the mbed lib v 143

Who changed what in which revision?

User	Revision	Line number	New contents of line
<>	157:ff67d9f36b67	1	/**
<>	157:ff67d9f36b67	2	******************************************************************************
<>	157:ff67d9f36b67	3	* @file stm32f3xx_ll_rcc.c
<>	157:ff67d9f36b67	4	* @author MCD Application Team
<>	157:ff67d9f36b67	5	* @version V1.4.0
<>	157:ff67d9f36b67	6	* @date 16-December-2016
<>	157:ff67d9f36b67	7	* @brief RCC LL module driver.
<>	157:ff67d9f36b67	8	******************************************************************************
<>	157:ff67d9f36b67	9	* @attention
<>	157:ff67d9f36b67	10	*
<>	157:ff67d9f36b67	11	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<>	157:ff67d9f36b67	12	*
<>	157:ff67d9f36b67	13	* Redistribution and use in source and binary forms, with or without modification,
<>	157:ff67d9f36b67	14	* are permitted provided that the following conditions are met:
<>	157:ff67d9f36b67	15	* 1. Redistributions of source code must retain the above copyright notice,
<>	157:ff67d9f36b67	16	* this list of conditions and the following disclaimer.
<>	157:ff67d9f36b67	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
<>	157:ff67d9f36b67	18	* this list of conditions and the following disclaimer in the documentation
<>	157:ff67d9f36b67	19	* and/or other materials provided with the distribution.
<>	157:ff67d9f36b67	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
<>	157:ff67d9f36b67	21	* may be used to endorse or promote products derived from this software
<>	157:ff67d9f36b67	22	* without specific prior written permission.
<>	157:ff67d9f36b67	23	*
<>	157:ff67d9f36b67	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<>	157:ff67d9f36b67	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<>	157:ff67d9f36b67	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<>	157:ff67d9f36b67	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<>	157:ff67d9f36b67	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<>	157:ff67d9f36b67	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<>	157:ff67d9f36b67	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<>	157:ff67d9f36b67	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<>	157:ff67d9f36b67	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<>	157:ff67d9f36b67	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<>	157:ff67d9f36b67	34	*
<>	157:ff67d9f36b67	35	******************************************************************************
<>	157:ff67d9f36b67	36	*/
<>	157:ff67d9f36b67	37	#if defined(USE_FULL_LL_DRIVER)
<>	157:ff67d9f36b67	38
<>	157:ff67d9f36b67	39	/* Includes ------------------------------------------------------------------*/
<>	157:ff67d9f36b67	40	#include "stm32f3xx_ll_rcc.h"
<>	157:ff67d9f36b67	41	#ifdef USE_FULL_ASSERT
<>	157:ff67d9f36b67	42	#include "stm32_assert.h"
<>	157:ff67d9f36b67	43	#else
<>	157:ff67d9f36b67	44	#define assert_param(expr) ((void)0U)
<>	157:ff67d9f36b67	45	#endif /* USE_FULL_ASSERT */
<>	157:ff67d9f36b67	46	/** @addtogroup STM32F3xx_LL_Driver
<>	157:ff67d9f36b67	47	* @{
<>	157:ff67d9f36b67	48	*/
<>	157:ff67d9f36b67	49
<>	157:ff67d9f36b67	50	#if defined(RCC)
<>	157:ff67d9f36b67	51
<>	157:ff67d9f36b67	52	/** @defgroup RCC_LL RCC
<>	157:ff67d9f36b67	53	* @{
<>	157:ff67d9f36b67	54	*/
<>	157:ff67d9f36b67	55
<>	157:ff67d9f36b67	56	/* Private types -------------------------------------------------------------*/
<>	157:ff67d9f36b67	57	/* Private variables ---------------------------------------------------------*/
<>	157:ff67d9f36b67	58	/** @addtogroup RCC_LL_Private_Variables
<>	157:ff67d9f36b67	59	* @{
<>	157:ff67d9f36b67	60	*/
<>	157:ff67d9f36b67	61	#if defined(RCC_CFGR2_ADC1PRES) \|\| defined(RCC_CFGR2_ADCPRE12) \|\| defined(RCC_CFGR2_ADCPRE34)
<>	157:ff67d9f36b67	62	const uint16_t aADCPrescTable[12] = {1U, 2U, 4U, 6U, 8U, 10U, 12U, 16U, 32U, 64U, 128U, 256U};
<>	157:ff67d9f36b67	63	#endif /* RCC_CFGR2_ADC1PRES \|\| RCC_CFGR2_ADCPRE12 \|\| RCC_CFGR2_ADCPRE34 */
<>	157:ff67d9f36b67	64	#if defined(RCC_CFGR_SDPRE)
<>	157:ff67d9f36b67	65	const uint8_t aSDADCPrescTable[16] = {2U, 4U, 6U, 8U, 10U, 12U, 14U, 16U, 20U, 24U, 28U, 32U, 36U, 40U, 44U, 48U};
<>	157:ff67d9f36b67	66	#endif /* RCC_CFGR_SDPRE */
<>	157:ff67d9f36b67	67	/**
<>	157:ff67d9f36b67	68	* @}
<>	157:ff67d9f36b67	69	*/
<>	157:ff67d9f36b67	70
<>	157:ff67d9f36b67	71
<>	157:ff67d9f36b67	72	/* Private constants ---------------------------------------------------------*/
<>	157:ff67d9f36b67	73	/* Private macros ------------------------------------------------------------*/
<>	157:ff67d9f36b67	74	/** @addtogroup RCC_LL_Private_Macros
<>	157:ff67d9f36b67	75	* @{
<>	157:ff67d9f36b67	76	*/
<>	157:ff67d9f36b67	77	#if defined(RCC_CFGR3_USART2SW) && defined(RCC_CFGR3_USART3SW)
<>	157:ff67d9f36b67	78	#define IS_LL_RCC_USART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USART1_CLKSOURCE) \
<>	157:ff67d9f36b67	79	\|\| ((__VALUE__) == LL_RCC_USART2_CLKSOURCE) \
<>	157:ff67d9f36b67	80	\|\| ((__VALUE__) == LL_RCC_USART3_CLKSOURCE))
<>	157:ff67d9f36b67	81	#elif defined(RCC_CFGR3_USART2SW) && !defined(RCC_CFGR3_USART3SW)
<>	157:ff67d9f36b67	82	#define IS_LL_RCC_USART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USART1_CLKSOURCE) \
<>	157:ff67d9f36b67	83	\|\| ((__VALUE__) == LL_RCC_USART2_CLKSOURCE))
<>	157:ff67d9f36b67	84	#elif defined(RCC_CFGR3_USART3SW) && !defined(RCC_CFGR3_USART2SW)
<>	157:ff67d9f36b67	85	#define IS_LL_RCC_USART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USART1_CLKSOURCE) \
<>	157:ff67d9f36b67	86	\|\| ((__VALUE__) == LL_RCC_USART3_CLKSOURCE))
<>	157:ff67d9f36b67	87	#else
<>	157:ff67d9f36b67	88	#define IS_LL_RCC_USART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USART1_CLKSOURCE))
<>	157:ff67d9f36b67	89	#endif /* RCC_CFGR3_USART2SW && RCC_CFGR3_USART3SW */
<>	157:ff67d9f36b67	90
<>	157:ff67d9f36b67	91	#if defined(UART4) && defined(UART5)
<>	157:ff67d9f36b67	92	#define IS_LL_RCC_UART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_UART4_CLKSOURCE) \
<>	157:ff67d9f36b67	93	\|\| ((__VALUE__) == LL_RCC_UART5_CLKSOURCE))
<>	157:ff67d9f36b67	94	#elif defined(UART4)
<>	157:ff67d9f36b67	95	#define IS_LL_RCC_UART_INSTANCE(__VALUE__) ((__VALUE__) == LL_RCC_UART4_CLKSOURCE)
<>	157:ff67d9f36b67	96	#elif defined(UART5)
<>	157:ff67d9f36b67	97	#define IS_LL_RCC_UART_INSTANCE(__VALUE__) ((__VALUE__) == LL_RCC_UART5_CLKSOURCE)
<>	157:ff67d9f36b67	98	#endif /* UART4 && UART5*/
<>	157:ff67d9f36b67	99
<>	157:ff67d9f36b67	100	#if defined(RCC_CFGR3_I2C2SW) && defined(RCC_CFGR3_I2C3SW)
<>	157:ff67d9f36b67	101	#define IS_LL_RCC_I2C_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_I2C1_CLKSOURCE) \
<>	157:ff67d9f36b67	102	\|\| ((__VALUE__) == LL_RCC_I2C2_CLKSOURCE) \
<>	157:ff67d9f36b67	103	\|\| ((__VALUE__) == LL_RCC_I2C3_CLKSOURCE))
<>	157:ff67d9f36b67	104
<>	157:ff67d9f36b67	105	#elif defined(RCC_CFGR3_I2C2SW) && !defined(RCC_CFGR3_I2C3SW)
<>	157:ff67d9f36b67	106	#define IS_LL_RCC_I2C_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_I2C1_CLKSOURCE) \
<>	157:ff67d9f36b67	107	\|\| ((__VALUE__) == LL_RCC_I2C2_CLKSOURCE))
<>	157:ff67d9f36b67	108
<>	157:ff67d9f36b67	109	#elif defined(RCC_CFGR3_I2C3SW) && !defined(RCC_CFGR3_I2C2SW)
<>	157:ff67d9f36b67	110	#define IS_LL_RCC_I2C_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_I2C1_CLKSOURCE) \
<>	157:ff67d9f36b67	111	\|\| ((__VALUE__) == LL_RCC_I2C3_CLKSOURCE))
<>	157:ff67d9f36b67	112
<>	157:ff67d9f36b67	113	#else
<>	157:ff67d9f36b67	114	#define IS_LL_RCC_I2C_CLKSOURCE(__VALUE__) ((__VALUE__) == LL_RCC_I2C1_CLKSOURCE)
<>	157:ff67d9f36b67	115	#endif /* RCC_CFGR3_I2C2SW && RCC_CFGR3_I2C3SW */
<>	157:ff67d9f36b67	116
<>	157:ff67d9f36b67	117	#define IS_LL_RCC_I2S_CLKSOURCE(__VALUE__) ((__VALUE__) == LL_RCC_I2S_CLKSOURCE)
<>	157:ff67d9f36b67	118
<>	157:ff67d9f36b67	119	#if defined(USB)
<>	157:ff67d9f36b67	120	#define IS_LL_RCC_USB_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USB_CLKSOURCE))
<>	157:ff67d9f36b67	121	#endif /* USB */
<>	157:ff67d9f36b67	122
<>	157:ff67d9f36b67	123	#if defined(RCC_CFGR_ADCPRE)
<>	157:ff67d9f36b67	124	#define IS_LL_RCC_ADC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_ADC_CLKSOURCE))
<>	157:ff67d9f36b67	125	#else
<>	157:ff67d9f36b67	126	#if defined(RCC_CFGR2_ADC1PRES)
<>	157:ff67d9f36b67	127	#define IS_LL_RCC_ADC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_ADC1_CLKSOURCE))
<>	157:ff67d9f36b67	128	#elif defined(RCC_CFGR2_ADCPRE12) && defined(RCC_CFGR2_ADCPRE34)
<>	157:ff67d9f36b67	129	#define IS_LL_RCC_ADC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_ADC12_CLKSOURCE) \
<>	157:ff67d9f36b67	130	\|\| ((__VALUE__) == LL_RCC_ADC34_CLKSOURCE))
<>	157:ff67d9f36b67	131	#else /* RCC_CFGR2_ADCPRE12 */
<>	157:ff67d9f36b67	132	#define IS_LL_RCC_ADC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_ADC12_CLKSOURCE))
<>	157:ff67d9f36b67	133	#endif /* RCC_CFGR2_ADC1PRES */
<>	157:ff67d9f36b67	134	#endif /* RCC_CFGR_ADCPRE */
<>	157:ff67d9f36b67	135
<>	157:ff67d9f36b67	136	#if defined(RCC_CFGR_SDPRE)
<>	157:ff67d9f36b67	137	#define IS_LL_RCC_SDADC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SDADC_CLKSOURCE))
<>	157:ff67d9f36b67	138	#endif /* RCC_CFGR_SDPRE */
<>	157:ff67d9f36b67	139
<>	157:ff67d9f36b67	140	#if defined(CEC)
<>	157:ff67d9f36b67	141	#define IS_LL_RCC_CEC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_CEC_CLKSOURCE))
<>	157:ff67d9f36b67	142	#endif /* CEC */
<>	157:ff67d9f36b67	143
<>	157:ff67d9f36b67	144	#if defined(RCC_CFGR3_TIMSW)
<>	157:ff67d9f36b67	145	#if defined(RCC_CFGR3_TIM8SW) && defined(RCC_CFGR3_TIM15SW) && defined(RCC_CFGR3_TIM16SW) \
<>	157:ff67d9f36b67	146	&& defined(RCC_CFGR3_TIM17SW) && defined(RCC_CFGR3_TIM20SW) && defined(RCC_CFGR3_TIM2SW) \
<>	157:ff67d9f36b67	147	&& defined(RCC_CFGR3_TIM34SW)
<>	157:ff67d9f36b67	148
<>	157:ff67d9f36b67	149	#define IS_LL_RCC_TIM_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_TIM1_CLKSOURCE) \
<>	157:ff67d9f36b67	150	\|\| ((__VALUE__) == LL_RCC_TIM2_CLKSOURCE) \
<>	157:ff67d9f36b67	151	\|\| ((__VALUE__) == LL_RCC_TIM8_CLKSOURCE) \
<>	157:ff67d9f36b67	152	\|\| ((__VALUE__) == LL_RCC_TIM15_CLKSOURCE) \
<>	157:ff67d9f36b67	153	\|\| ((__VALUE__) == LL_RCC_TIM16_CLKSOURCE) \
<>	157:ff67d9f36b67	154	\|\| ((__VALUE__) == LL_RCC_TIM17_CLKSOURCE) \
<>	157:ff67d9f36b67	155	\|\| ((__VALUE__) == LL_RCC_TIM20_CLKSOURCE) \
<>	157:ff67d9f36b67	156	\|\| ((__VALUE__) == LL_RCC_TIM34_CLKSOURCE))
<>	157:ff67d9f36b67	157
<>	157:ff67d9f36b67	158	#elif !defined(RCC_CFGR3_TIM8SW) && defined(RCC_CFGR3_TIM15SW) && defined(RCC_CFGR3_TIM16SW) \
<>	157:ff67d9f36b67	159	&& defined(RCC_CFGR3_TIM17SW) && !defined(RCC_CFGR3_TIM20SW) && defined(RCC_CFGR3_TIM2SW) \
<>	157:ff67d9f36b67	160	&& defined(RCC_CFGR3_TIM34SW)
<>	157:ff67d9f36b67	161
<>	157:ff67d9f36b67	162	#define IS_LL_RCC_TIM_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_TIM1_CLKSOURCE) \
<>	157:ff67d9f36b67	163	\|\| ((__VALUE__) == LL_RCC_TIM2_CLKSOURCE) \
<>	157:ff67d9f36b67	164	\|\| ((__VALUE__) == LL_RCC_TIM15_CLKSOURCE) \
<>	157:ff67d9f36b67	165	\|\| ((__VALUE__) == LL_RCC_TIM16_CLKSOURCE) \
<>	157:ff67d9f36b67	166	\|\| ((__VALUE__) == LL_RCC_TIM17_CLKSOURCE) \
<>	157:ff67d9f36b67	167	\|\| ((__VALUE__) == LL_RCC_TIM34_CLKSOURCE))
<>	157:ff67d9f36b67	168
<>	157:ff67d9f36b67	169	#elif defined(RCC_CFGR3_TIM8SW) && !defined(RCC_CFGR3_TIM15SW) && !defined(RCC_CFGR3_TIM16SW) \
<>	157:ff67d9f36b67	170	&& !defined(RCC_CFGR3_TIM17SW) && !defined(RCC_CFGR3_TIM20SW) && !defined(RCC_CFGR3_TIM2SW) \
<>	157:ff67d9f36b67	171	&& !defined(RCC_CFGR3_TIM34SW)
<>	157:ff67d9f36b67	172
<>	157:ff67d9f36b67	173	#define IS_LL_RCC_TIM_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_TIM1_CLKSOURCE) \
<>	157:ff67d9f36b67	174	\|\| ((__VALUE__) == LL_RCC_TIM8_CLKSOURCE))
<>	157:ff67d9f36b67	175
<>	157:ff67d9f36b67	176	#elif !defined(RCC_CFGR3_TIM8SW) && defined(RCC_CFGR3_TIM15SW) && defined(RCC_CFGR3_TIM16SW) \
<>	157:ff67d9f36b67	177	&& defined(RCC_CFGR3_TIM17SW) && !defined(RCC_CFGR3_TIM20SW) && !defined(RCC_CFGR3_TIM2SW) \
<>	157:ff67d9f36b67	178	&& !defined(RCC_CFGR3_TIM34SW)
<>	157:ff67d9f36b67	179
<>	157:ff67d9f36b67	180	#define IS_LL_RCC_TIM_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_TIM1_CLKSOURCE) \
<>	157:ff67d9f36b67	181	\|\| ((__VALUE__) == LL_RCC_TIM15_CLKSOURCE) \
<>	157:ff67d9f36b67	182	\|\| ((__VALUE__) == LL_RCC_TIM16_CLKSOURCE) \
<>	157:ff67d9f36b67	183	\|\| ((__VALUE__) == LL_RCC_TIM17_CLKSOURCE))
<>	157:ff67d9f36b67	184
<>	157:ff67d9f36b67	185	#elif !defined(RCC_CFGR3_TIM8SW) && !defined(RCC_CFGR3_TIM15SW) && !defined(RCC_CFGR3_TIM16SW) \
<>	157:ff67d9f36b67	186	&& !defined(RCC_CFGR3_TIM17SW) && !defined(RCC_CFGR3_TIM20SW) && !defined(RCC_CFGR3_TIM2SW) \
<>	157:ff67d9f36b67	187	&& !defined(RCC_CFGR3_TIM34SW)
<>	157:ff67d9f36b67	188
<>	157:ff67d9f36b67	189	#define IS_LL_RCC_TIM_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_TIM1_CLKSOURCE))
<>	157:ff67d9f36b67	190
<>	157:ff67d9f36b67	191	#else
<>	157:ff67d9f36b67	192	#error "Miss macro"
<>	157:ff67d9f36b67	193	#endif /* RCC_CFGR3_TIMxSW */
<>	157:ff67d9f36b67	194	#endif /* RCC_CFGR3_TIMSW */
<>	157:ff67d9f36b67	195
<>	157:ff67d9f36b67	196	#if defined(HRTIM1)
<>	157:ff67d9f36b67	197	#define IS_LL_RCC_HRTIM_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_HRTIM1_CLKSOURCE))
<>	157:ff67d9f36b67	198	#endif /* HRTIM1 */
<>	157:ff67d9f36b67	199
<>	157:ff67d9f36b67	200	/**
<>	157:ff67d9f36b67	201	* @}
<>	157:ff67d9f36b67	202	*/
<>	157:ff67d9f36b67	203
<>	157:ff67d9f36b67	204	/* Private function prototypes -----------------------------------------------*/
<>	157:ff67d9f36b67	205	/** @defgroup RCC_LL_Private_Functions RCC Private functions
<>	157:ff67d9f36b67	206	* @{
<>	157:ff67d9f36b67	207	*/
<>	157:ff67d9f36b67	208	uint32_t RCC_GetSystemClockFreq(void);
<>	157:ff67d9f36b67	209	uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency);
<>	157:ff67d9f36b67	210	uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency);
<>	157:ff67d9f36b67	211	uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency);
<>	157:ff67d9f36b67	212	uint32_t RCC_PLL_GetFreqDomain_SYS(void);
<>	157:ff67d9f36b67	213	/**
<>	157:ff67d9f36b67	214	* @}
<>	157:ff67d9f36b67	215	*/
<>	157:ff67d9f36b67	216
<>	157:ff67d9f36b67	217
<>	157:ff67d9f36b67	218	/* Exported functions --------------------------------------------------------*/
<>	157:ff67d9f36b67	219	/** @addtogroup RCC_LL_Exported_Functions
<>	157:ff67d9f36b67	220	* @{
<>	157:ff67d9f36b67	221	*/
<>	157:ff67d9f36b67	222
<>	157:ff67d9f36b67	223	/** @addtogroup RCC_LL_EF_Init
<>	157:ff67d9f36b67	224	* @{
<>	157:ff67d9f36b67	225	*/
<>	157:ff67d9f36b67	226
<>	157:ff67d9f36b67	227	/**
<>	157:ff67d9f36b67	228	* @brief Reset the RCC clock configuration to the default reset state.
<>	157:ff67d9f36b67	229	* @note The default reset state of the clock configuration is given below:
<>	157:ff67d9f36b67	230	* - HSI ON and used as system clock source
<>	157:ff67d9f36b67	231	* - HSE and PLL OFF
<>	157:ff67d9f36b67	232	* - AHB, APB1 and APB2 prescaler set to 1.
<>	157:ff67d9f36b67	233	* - CSS, MCO OFF
<>	157:ff67d9f36b67	234	* - All interrupts disabled
<>	157:ff67d9f36b67	235	* @note This function doesn't modify the configuration of the
<>	157:ff67d9f36b67	236	* - Peripheral clocks
<>	157:ff67d9f36b67	237	* - LSI, LSE and RTC clocks
<>	157:ff67d9f36b67	238	* @retval An ErrorStatus enumeration value:
<>	157:ff67d9f36b67	239	* - SUCCESS: RCC registers are de-initialized
<>	157:ff67d9f36b67	240	* - ERROR: not applicable
<>	157:ff67d9f36b67	241	*/
<>	157:ff67d9f36b67	242	ErrorStatus LL_RCC_DeInit(void)
<>	157:ff67d9f36b67	243	{
<>	157:ff67d9f36b67	244	uint32_t vl_mask = 0U;
<>	157:ff67d9f36b67	245
<>	157:ff67d9f36b67	246	/* Set HSION bit */
<>	157:ff67d9f36b67	247	LL_RCC_HSI_Enable();
<>	157:ff67d9f36b67	248
<>	157:ff67d9f36b67	249	/* Set HSITRIM bits to the reset value*/
<>	157:ff67d9f36b67	250	LL_RCC_HSI_SetCalibTrimming(0x10U);
<>	157:ff67d9f36b67	251
<>	157:ff67d9f36b67	252	/* Reset SW, HPRE, PPRE and MCOSEL bits */
<>	157:ff67d9f36b67	253	vl_mask = 0xFFFFFFFFU;
<>	157:ff67d9f36b67	254	CLEAR_BIT(vl_mask, (RCC_CFGR_SW \| RCC_CFGR_HPRE \| RCC_CFGR_PPRE1 \| RCC_CFGR_PPRE2 \| RCC_CFGR_MCOSEL));
<>	157:ff67d9f36b67	255	LL_RCC_WriteReg(CFGR, vl_mask);
<>	157:ff67d9f36b67	256
<>	157:ff67d9f36b67	257	/* Reset HSEON, CSSON, PLLON bits */
<>	157:ff67d9f36b67	258	vl_mask = 0xFFFFFFFFU;
<>	157:ff67d9f36b67	259	CLEAR_BIT(vl_mask, (RCC_CR_PLLON \| RCC_CR_CSSON \| RCC_CR_HSEON));
<>	157:ff67d9f36b67	260	LL_RCC_WriteReg(CR, vl_mask);
<>	157:ff67d9f36b67	261
<>	157:ff67d9f36b67	262	/* Reset HSEBYP bit */
<>	157:ff67d9f36b67	263	LL_RCC_HSE_DisableBypass();
<>	157:ff67d9f36b67	264
<>	157:ff67d9f36b67	265	/* Reset CFGR register */
<>	157:ff67d9f36b67	266	LL_RCC_WriteReg(CFGR, 0x00000000U);
<>	157:ff67d9f36b67	267
<>	157:ff67d9f36b67	268	/* Reset CFGR2 register */
<>	157:ff67d9f36b67	269	LL_RCC_WriteReg(CFGR2, 0x00000000U);
<>	157:ff67d9f36b67	270
<>	157:ff67d9f36b67	271	/* Reset CFGR3 register */
<>	157:ff67d9f36b67	272	LL_RCC_WriteReg(CFGR3, 0x00000000U);
<>	157:ff67d9f36b67	273
<>	157:ff67d9f36b67	274	/* Clear pending flags */
<>	157:ff67d9f36b67	275	vl_mask = (LL_RCC_CIR_LSIRDYC \| LL_RCC_CIR_LSERDYC \| LL_RCC_CIR_HSIRDYC \| LL_RCC_CIR_HSERDYC \| LL_RCC_CIR_PLLRDYC \| LL_RCC_CIR_CSSC);
<>	157:ff67d9f36b67	276	SET_BIT(RCC->CIR, vl_mask);
<>	157:ff67d9f36b67	277
<>	157:ff67d9f36b67	278	/* Disable all interrupts */
<>	157:ff67d9f36b67	279	LL_RCC_WriteReg(CIR, 0x00000000U);
<>	157:ff67d9f36b67	280
<>	157:ff67d9f36b67	281	return SUCCESS;
<>	157:ff67d9f36b67	282	}
<>	157:ff67d9f36b67	283
<>	157:ff67d9f36b67	284	/**
<>	157:ff67d9f36b67	285	* @}
<>	157:ff67d9f36b67	286	*/
<>	157:ff67d9f36b67	287
<>	157:ff67d9f36b67	288	/** @addtogroup RCC_LL_EF_Get_Freq
<>	157:ff67d9f36b67	289	* @brief Return the frequencies of different on chip clocks; System, AHB, APB1 and APB2 buses clocks
<>	157:ff67d9f36b67	290	* and different peripheral clocks available on the device.
<>	157:ff67d9f36b67	291	* @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(**)
<>	157:ff67d9f36b67	292	* @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(***)
<>	157:ff67d9f36b67	293	* @note If SYSCLK source is PLL, function returns values based on
<>	157:ff67d9f36b67	294	* HSI_VALUE() or HSE_VALUE(*) multiplied/divided by the PLL factors.
<>	157:ff67d9f36b67	295	* @note (**) HSI_VALUE is a defined constant but the real value may vary
<>	157:ff67d9f36b67	296	* depending on the variations in voltage and temperature.
<>	157:ff67d9f36b67	297	* @note (***) HSE_VALUE is a defined constant, user has to ensure that
<>	157:ff67d9f36b67	298	* HSE_VALUE is same as the real frequency of the crystal used.
<>	157:ff67d9f36b67	299	* Otherwise, this function may have wrong result.
<>	157:ff67d9f36b67	300	* @note The result of this function could be incorrect when using fractional
<>	157:ff67d9f36b67	301	* value for HSE crystal.
<>	157:ff67d9f36b67	302	* @note This function can be used by the user application to compute the
<>	157:ff67d9f36b67	303	* baud-rate for the communication peripherals or configure other parameters.
<>	157:ff67d9f36b67	304	* @{
<>	157:ff67d9f36b67	305	*/
<>	157:ff67d9f36b67	306
<>	157:ff67d9f36b67	307	/**
<>	157:ff67d9f36b67	308	* @brief Return the frequencies of different on chip clocks; System, AHB, APB1 and APB2 buses clocks
<>	157:ff67d9f36b67	309	* @note Each time SYSCLK, HCLK, PCLK1 and/or PCLK2 clock changes, this function
<>	157:ff67d9f36b67	310	* must be called to update structure fields. Otherwise, any
<>	157:ff67d9f36b67	311	* configuration based on this function will be incorrect.
<>	157:ff67d9f36b67	312	* @param RCC_Clocks pointer to a @ref LL_RCC_ClocksTypeDef structure which will hold the clocks frequencies
<>	157:ff67d9f36b67	313	* @retval None
<>	157:ff67d9f36b67	314	*/
<>	157:ff67d9f36b67	315	void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks)
<>	157:ff67d9f36b67	316	{
<>	157:ff67d9f36b67	317	/* Get SYSCLK frequency */
<>	157:ff67d9f36b67	318	RCC_Clocks->SYSCLK_Frequency = RCC_GetSystemClockFreq();
<>	157:ff67d9f36b67	319
<>	157:ff67d9f36b67	320	/* HCLK clock frequency */
<>	157:ff67d9f36b67	321	RCC_Clocks->HCLK_Frequency = RCC_GetHCLKClockFreq(RCC_Clocks->SYSCLK_Frequency);
<>	157:ff67d9f36b67	322
<>	157:ff67d9f36b67	323	/* PCLK1 clock frequency */
<>	157:ff67d9f36b67	324	RCC_Clocks->PCLK1_Frequency = RCC_GetPCLK1ClockFreq(RCC_Clocks->HCLK_Frequency);
<>	157:ff67d9f36b67	325
<>	157:ff67d9f36b67	326	/* PCLK2 clock frequency */
<>	157:ff67d9f36b67	327	RCC_Clocks->PCLK2_Frequency = RCC_GetPCLK2ClockFreq(RCC_Clocks->HCLK_Frequency);
<>	157:ff67d9f36b67	328	}
<>	157:ff67d9f36b67	329
<>	157:ff67d9f36b67	330	/**
<>	157:ff67d9f36b67	331	* @brief Return USARTx clock frequency
<>	157:ff67d9f36b67	332	* @param USARTxSource This parameter can be one of the following values:
<>	157:ff67d9f36b67	333	* @arg @ref LL_RCC_USART1_CLKSOURCE
<>	157:ff67d9f36b67	334	* @arg @ref LL_RCC_USART2_CLKSOURCE (*)
<>	157:ff67d9f36b67	335	* @arg @ref LL_RCC_USART3_CLKSOURCE (*)
<>	157:ff67d9f36b67	336	*
<>	157:ff67d9f36b67	337	* (*) value not defined in all devices.
<>	157:ff67d9f36b67	338	* @retval USART clock frequency (in Hz)
<>	157:ff67d9f36b67	339	* @arg @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI or LSE) is not ready
<>	157:ff67d9f36b67	340	*/
<>	157:ff67d9f36b67	341	uint32_t LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource)
<>	157:ff67d9f36b67	342	{
<>	157:ff67d9f36b67	343	uint32_t usart_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
<>	157:ff67d9f36b67	344
<>	157:ff67d9f36b67	345	/* Check parameter */
<>	157:ff67d9f36b67	346	assert_param(IS_LL_RCC_USART_CLKSOURCE(USARTxSource));
<>	157:ff67d9f36b67	347	#if defined(RCC_CFGR3_USART1SW)
<>	157:ff67d9f36b67	348	if (USARTxSource == LL_RCC_USART1_CLKSOURCE)
<>	157:ff67d9f36b67	349	{
<>	157:ff67d9f36b67	350	/* USART1CLK clock frequency */
<>	157:ff67d9f36b67	351	switch (LL_RCC_GetUSARTClockSource(USARTxSource))
<>	157:ff67d9f36b67	352	{
<>	157:ff67d9f36b67	353	case LL_RCC_USART1_CLKSOURCE_SYSCLK: /* USART1 Clock is System Clock */
<>	157:ff67d9f36b67	354	usart_frequency = RCC_GetSystemClockFreq();
<>	157:ff67d9f36b67	355	break;
<>	157:ff67d9f36b67	356
<>	157:ff67d9f36b67	357	case LL_RCC_USART1_CLKSOURCE_HSI: /* USART1 Clock is HSI Osc. */
<>	157:ff67d9f36b67	358	if (LL_RCC_HSI_IsReady())
<>	157:ff67d9f36b67	359	{
<>	157:ff67d9f36b67	360	usart_frequency = HSI_VALUE;
<>	157:ff67d9f36b67	361	}
<>	157:ff67d9f36b67	362	break;
<>	157:ff67d9f36b67	363
<>	157:ff67d9f36b67	364	case LL_RCC_USART1_CLKSOURCE_LSE: /* USART1 Clock is LSE Osc. */
<>	157:ff67d9f36b67	365	if (LL_RCC_LSE_IsReady())
<>	157:ff67d9f36b67	366	{
<>	157:ff67d9f36b67	367	usart_frequency = LSE_VALUE;
<>	157:ff67d9f36b67	368	}
<>	157:ff67d9f36b67	369	break;
<>	157:ff67d9f36b67	370
<>	157:ff67d9f36b67	371	#if defined(RCC_CFGR3_USART1SW_PCLK1)
<>	157:ff67d9f36b67	372	case LL_RCC_USART1_CLKSOURCE_PCLK1: /* USART1 Clock is PCLK1 */
<>	157:ff67d9f36b67	373	default:
<>	157:ff67d9f36b67	374	usart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
<>	157:ff67d9f36b67	375	#else
<>	157:ff67d9f36b67	376	case LL_RCC_USART1_CLKSOURCE_PCLK2: /* USART1 Clock is PCLK2 */
<>	157:ff67d9f36b67	377	default:
<>	157:ff67d9f36b67	378	usart_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
<>	157:ff67d9f36b67	379	#endif /* RCC_CFGR3_USART1SW_PCLK1 */
<>	157:ff67d9f36b67	380	break;
<>	157:ff67d9f36b67	381	}
<>	157:ff67d9f36b67	382	}
<>	157:ff67d9f36b67	383	#endif /* RCC_CFGR3_USART1SW */
<>	157:ff67d9f36b67	384
<>	157:ff67d9f36b67	385	#if defined(RCC_CFGR3_USART2SW)
<>	157:ff67d9f36b67	386	if (USARTxSource == LL_RCC_USART2_CLKSOURCE)
<>	157:ff67d9f36b67	387	{
<>	157:ff67d9f36b67	388	/* USART2CLK clock frequency */
<>	157:ff67d9f36b67	389	switch (LL_RCC_GetUSARTClockSource(USARTxSource))
<>	157:ff67d9f36b67	390	{
<>	157:ff67d9f36b67	391	case LL_RCC_USART2_CLKSOURCE_SYSCLK: /* USART2 Clock is System Clock */
<>	157:ff67d9f36b67	392	usart_frequency = RCC_GetSystemClockFreq();
<>	157:ff67d9f36b67	393	break;
<>	157:ff67d9f36b67	394
<>	157:ff67d9f36b67	395	case LL_RCC_USART2_CLKSOURCE_HSI: /* USART2 Clock is HSI Osc. */
<>	157:ff67d9f36b67	396	if (LL_RCC_HSI_IsReady())
<>	157:ff67d9f36b67	397	{
<>	157:ff67d9f36b67	398	usart_frequency = HSI_VALUE;
<>	157:ff67d9f36b67	399	}
<>	157:ff67d9f36b67	400	break;
<>	157:ff67d9f36b67	401
<>	157:ff67d9f36b67	402	case LL_RCC_USART2_CLKSOURCE_LSE: /* USART2 Clock is LSE Osc. */
<>	157:ff67d9f36b67	403	if (LL_RCC_LSE_IsReady())
<>	157:ff67d9f36b67	404	{
<>	157:ff67d9f36b67	405	usart_frequency = LSE_VALUE;
<>	157:ff67d9f36b67	406	}
<>	157:ff67d9f36b67	407	break;
<>	157:ff67d9f36b67	408
<>	157:ff67d9f36b67	409	case LL_RCC_USART2_CLKSOURCE_PCLK1: /* USART2 Clock is PCLK1 */
<>	157:ff67d9f36b67	410	default:
<>	157:ff67d9f36b67	411	usart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
<>	157:ff67d9f36b67	412	break;
<>	157:ff67d9f36b67	413	}
<>	157:ff67d9f36b67	414	}
<>	157:ff67d9f36b67	415	#endif /* RCC_CFGR3_USART2SW */
<>	157:ff67d9f36b67	416
<>	157:ff67d9f36b67	417	#if defined(RCC_CFGR3_USART3SW)
<>	157:ff67d9f36b67	418	if (USARTxSource == LL_RCC_USART3_CLKSOURCE)
<>	157:ff67d9f36b67	419	{
<>	157:ff67d9f36b67	420	/* USART3CLK clock frequency */
<>	157:ff67d9f36b67	421	switch (LL_RCC_GetUSARTClockSource(USARTxSource))
<>	157:ff67d9f36b67	422	{
<>	157:ff67d9f36b67	423	case LL_RCC_USART3_CLKSOURCE_SYSCLK: /* USART3 Clock is System Clock */
<>	157:ff67d9f36b67	424	usart_frequency = RCC_GetSystemClockFreq();
<>	157:ff67d9f36b67	425	break;
<>	157:ff67d9f36b67	426
<>	157:ff67d9f36b67	427	case LL_RCC_USART3_CLKSOURCE_HSI: /* USART3 Clock is HSI Osc. */
<>	157:ff67d9f36b67	428	if (LL_RCC_HSI_IsReady())
<>	157:ff67d9f36b67	429	{
<>	157:ff67d9f36b67	430	usart_frequency = HSI_VALUE;
<>	157:ff67d9f36b67	431	}
<>	157:ff67d9f36b67	432	break;
<>	157:ff67d9f36b67	433
<>	157:ff67d9f36b67	434	case LL_RCC_USART3_CLKSOURCE_LSE: /* USART3 Clock is LSE Osc. */
<>	157:ff67d9f36b67	435	if (LL_RCC_LSE_IsReady())
<>	157:ff67d9f36b67	436	{
<>	157:ff67d9f36b67	437	usart_frequency = LSE_VALUE;
<>	157:ff67d9f36b67	438	}
<>	157:ff67d9f36b67	439	break;
<>	157:ff67d9f36b67	440
<>	157:ff67d9f36b67	441	case LL_RCC_USART3_CLKSOURCE_PCLK1: /* USART3 Clock is PCLK1 */
<>	157:ff67d9f36b67	442	default:
<>	157:ff67d9f36b67	443	usart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
<>	157:ff67d9f36b67	444	break;
<>	157:ff67d9f36b67	445	}
<>	157:ff67d9f36b67	446	}
<>	157:ff67d9f36b67	447
<>	157:ff67d9f36b67	448	#endif /* RCC_CFGR3_USART3SW */
<>	157:ff67d9f36b67	449	return usart_frequency;
<>	157:ff67d9f36b67	450	}
<>	157:ff67d9f36b67	451
<>	157:ff67d9f36b67	452	#if defined(UART4) \|\| defined(UART5)
<>	157:ff67d9f36b67	453	/**
<>	157:ff67d9f36b67	454	* @brief Return UARTx clock frequency
<>	157:ff67d9f36b67	455	* @param UARTxSource This parameter can be one of the following values:
<>	157:ff67d9f36b67	456	* @arg @ref LL_RCC_UART4_CLKSOURCE
<>	157:ff67d9f36b67	457	* @arg @ref LL_RCC_UART5_CLKSOURCE
<>	157:ff67d9f36b67	458	* @retval UART clock frequency (in Hz)
<>	157:ff67d9f36b67	459	* @arg @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI or LSE) is not ready
<>	157:ff67d9f36b67	460	*/
<>	157:ff67d9f36b67	461	uint32_t LL_RCC_GetUARTClockFreq(uint32_t UARTxSource)
<>	157:ff67d9f36b67	462	{
<>	157:ff67d9f36b67	463	uint32_t uart_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
<>	157:ff67d9f36b67	464
<>	157:ff67d9f36b67	465	/* Check parameter */
<>	157:ff67d9f36b67	466	assert_param(IS_LL_RCC_UART_CLKSOURCE(UARTxSource));
<>	157:ff67d9f36b67	467
<>	157:ff67d9f36b67	468	#if defined(UART4)
<>	157:ff67d9f36b67	469	if (UARTxSource == LL_RCC_UART4_CLKSOURCE)
<>	157:ff67d9f36b67	470	{
<>	157:ff67d9f36b67	471	/* UART4CLK clock frequency */
<>	157:ff67d9f36b67	472	switch (LL_RCC_GetUARTClockSource(UARTxSource))
<>	157:ff67d9f36b67	473	{
<>	157:ff67d9f36b67	474	case LL_RCC_UART4_CLKSOURCE_SYSCLK: /* UART4 Clock is System Clock */
<>	157:ff67d9f36b67	475	uart_frequency = RCC_GetSystemClockFreq();
<>	157:ff67d9f36b67	476	break;
<>	157:ff67d9f36b67	477
<>	157:ff67d9f36b67	478	case LL_RCC_UART4_CLKSOURCE_HSI: /* UART4 Clock is HSI Osc. */
<>	157:ff67d9f36b67	479	if (LL_RCC_HSI_IsReady())
<>	157:ff67d9f36b67	480	{
<>	157:ff67d9f36b67	481	uart_frequency = HSI_VALUE;
<>	157:ff67d9f36b67	482	}
<>	157:ff67d9f36b67	483	break;
<>	157:ff67d9f36b67	484
<>	157:ff67d9f36b67	485	case LL_RCC_UART4_CLKSOURCE_LSE: /* UART4 Clock is LSE Osc. */
<>	157:ff67d9f36b67	486	if (LL_RCC_LSE_IsReady())
<>	157:ff67d9f36b67	487	{
<>	157:ff67d9f36b67	488	uart_frequency = LSE_VALUE;
<>	157:ff67d9f36b67	489	}
<>	157:ff67d9f36b67	490	break;
<>	157:ff67d9f36b67	491
<>	157:ff67d9f36b67	492	case LL_RCC_UART4_CLKSOURCE_PCLK1: /* UART4 Clock is PCLK1 */
<>	157:ff67d9f36b67	493	default:
<>	157:ff67d9f36b67	494	uart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
<>	157:ff67d9f36b67	495	break;
<>	157:ff67d9f36b67	496	}
<>	157:ff67d9f36b67	497	}
<>	157:ff67d9f36b67	498	#endif /* UART4 */
<>	157:ff67d9f36b67	499
<>	157:ff67d9f36b67	500	#if defined(UART5)
<>	157:ff67d9f36b67	501	if (UARTxSource == LL_RCC_UART5_CLKSOURCE)
<>	157:ff67d9f36b67	502	{
<>	157:ff67d9f36b67	503	/* UART5CLK clock frequency */
<>	157:ff67d9f36b67	504	switch (LL_RCC_GetUARTClockSource(UARTxSource))
<>	157:ff67d9f36b67	505	{
<>	157:ff67d9f36b67	506	case LL_RCC_UART5_CLKSOURCE_SYSCLK: /* UART5 Clock is System Clock */
<>	157:ff67d9f36b67	507	uart_frequency = RCC_GetSystemClockFreq();
<>	157:ff67d9f36b67	508	break;
<>	157:ff67d9f36b67	509
<>	157:ff67d9f36b67	510	case LL_RCC_UART5_CLKSOURCE_HSI: /* UART5 Clock is HSI Osc. */
<>	157:ff67d9f36b67	511	if (LL_RCC_HSI_IsReady())
<>	157:ff67d9f36b67	512	{
<>	157:ff67d9f36b67	513	uart_frequency = HSI_VALUE;
<>	157:ff67d9f36b67	514	}
<>	157:ff67d9f36b67	515	break;
<>	157:ff67d9f36b67	516
<>	157:ff67d9f36b67	517	case LL_RCC_UART5_CLKSOURCE_LSE: /* UART5 Clock is LSE Osc. */
<>	157:ff67d9f36b67	518	if (LL_RCC_LSE_IsReady())
<>	157:ff67d9f36b67	519	{
<>	157:ff67d9f36b67	520	uart_frequency = LSE_VALUE;
<>	157:ff67d9f36b67	521	}
<>	157:ff67d9f36b67	522	break;
<>	157:ff67d9f36b67	523
<>	157:ff67d9f36b67	524	case LL_RCC_UART5_CLKSOURCE_PCLK1: /* UART5 Clock is PCLK1 */
<>	157:ff67d9f36b67	525	default:
<>	157:ff67d9f36b67	526	uart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
<>	157:ff67d9f36b67	527	break;
<>	157:ff67d9f36b67	528	}
<>	157:ff67d9f36b67	529	}
<>	157:ff67d9f36b67	530	#endif /* UART5 */
<>	157:ff67d9f36b67	531
<>	157:ff67d9f36b67	532	return uart_frequency;
<>	157:ff67d9f36b67	533	}
<>	157:ff67d9f36b67	534	#endif /* UART4 \|\| UART5 */
<>	157:ff67d9f36b67	535
<>	157:ff67d9f36b67	536	/**
<>	157:ff67d9f36b67	537	* @brief Return I2Cx clock frequency
<>	157:ff67d9f36b67	538	* @param I2CxSource This parameter can be one of the following values:
<>	157:ff67d9f36b67	539	* @arg @ref LL_RCC_I2C1_CLKSOURCE
<>	157:ff67d9f36b67	540	* @arg @ref LL_RCC_I2C2_CLKSOURCE (*)
<>	157:ff67d9f36b67	541	* @arg @ref LL_RCC_I2C3_CLKSOURCE (*)
<>	157:ff67d9f36b67	542	*
<>	157:ff67d9f36b67	543	* (*) value not defined in all devices
<>	157:ff67d9f36b67	544	* @retval I2C clock frequency (in Hz)
<>	157:ff67d9f36b67	545	* @arg @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that HSI oscillator is not ready
<>	157:ff67d9f36b67	546	*/
<>	157:ff67d9f36b67	547	uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource)
<>	157:ff67d9f36b67	548	{
<>	157:ff67d9f36b67	549	uint32_t i2c_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
<>	157:ff67d9f36b67	550
<>	157:ff67d9f36b67	551	/* Check parameter */
<>	157:ff67d9f36b67	552	assert_param(IS_LL_RCC_I2C_CLKSOURCE(I2CxSource));
<>	157:ff67d9f36b67	553
<>	157:ff67d9f36b67	554	/* I2C1 CLK clock frequency */
<>	157:ff67d9f36b67	555	if (I2CxSource == LL_RCC_I2C1_CLKSOURCE)
<>	157:ff67d9f36b67	556	{
<>	157:ff67d9f36b67	557	switch (LL_RCC_GetI2CClockSource(I2CxSource))
<>	157:ff67d9f36b67	558	{
<>	157:ff67d9f36b67	559	case LL_RCC_I2C1_CLKSOURCE_SYSCLK: /* I2C1 Clock is System Clock */
<>	157:ff67d9f36b67	560	i2c_frequency = RCC_GetSystemClockFreq();
<>	157:ff67d9f36b67	561	break;
<>	157:ff67d9f36b67	562
<>	157:ff67d9f36b67	563	case LL_RCC_I2C1_CLKSOURCE_HSI: /* I2C1 Clock is HSI Osc. */
<>	157:ff67d9f36b67	564	default:
<>	157:ff67d9f36b67	565	if (LL_RCC_HSI_IsReady())
<>	157:ff67d9f36b67	566	{
<>	157:ff67d9f36b67	567	i2c_frequency = HSI_VALUE;
<>	157:ff67d9f36b67	568	}
<>	157:ff67d9f36b67	569	break;
<>	157:ff67d9f36b67	570	}
<>	157:ff67d9f36b67	571	}
<>	157:ff67d9f36b67	572
<>	157:ff67d9f36b67	573	#if defined(RCC_CFGR3_I2C2SW)
<>	157:ff67d9f36b67	574	/* I2C2 CLK clock frequency */
<>	157:ff67d9f36b67	575	if (I2CxSource == LL_RCC_I2C2_CLKSOURCE)
<>	157:ff67d9f36b67	576	{
<>	157:ff67d9f36b67	577	switch (LL_RCC_GetI2CClockSource(I2CxSource))
<>	157:ff67d9f36b67	578	{
<>	157:ff67d9f36b67	579	case LL_RCC_I2C2_CLKSOURCE_SYSCLK: /* I2C2 Clock is System Clock */
<>	157:ff67d9f36b67	580	i2c_frequency = RCC_GetSystemClockFreq();
<>	157:ff67d9f36b67	581	break;
<>	157:ff67d9f36b67	582
<>	157:ff67d9f36b67	583	case LL_RCC_I2C2_CLKSOURCE_HSI: /* I2C2 Clock is HSI Osc. */
<>	157:ff67d9f36b67	584	default:
<>	157:ff67d9f36b67	585	if (LL_RCC_HSI_IsReady())
<>	157:ff67d9f36b67	586	{
<>	157:ff67d9f36b67	587	i2c_frequency = HSI_VALUE;
<>	157:ff67d9f36b67	588	}
<>	157:ff67d9f36b67	589	break;
<>	157:ff67d9f36b67	590	}
<>	157:ff67d9f36b67	591	}
<>	157:ff67d9f36b67	592	#endif /RCC_CFGR3_I2C2SW/
<>	157:ff67d9f36b67	593
<>	157:ff67d9f36b67	594	#if defined(RCC_CFGR3_I2C3SW)
<>	157:ff67d9f36b67	595	/* I2C3 CLK clock frequency */
<>	157:ff67d9f36b67	596	if (I2CxSource == LL_RCC_I2C3_CLKSOURCE)
<>	157:ff67d9f36b67	597	{
<>	157:ff67d9f36b67	598	switch (LL_RCC_GetI2CClockSource(I2CxSource))
<>	157:ff67d9f36b67	599	{
<>	157:ff67d9f36b67	600	case LL_RCC_I2C3_CLKSOURCE_SYSCLK: /* I2C3 Clock is System Clock */
<>	157:ff67d9f36b67	601	i2c_frequency = RCC_GetSystemClockFreq();
<>	157:ff67d9f36b67	602	break;
<>	157:ff67d9f36b67	603
<>	157:ff67d9f36b67	604	case LL_RCC_I2C3_CLKSOURCE_HSI: /* I2C3 Clock is HSI Osc. */
<>	157:ff67d9f36b67	605	default:
<>	157:ff67d9f36b67	606	if (LL_RCC_HSI_IsReady())
<>	157:ff67d9f36b67	607	{
<>	157:ff67d9f36b67	608	i2c_frequency = HSI_VALUE;
<>	157:ff67d9f36b67	609	}
<>	157:ff67d9f36b67	610	break;
<>	157:ff67d9f36b67	611	}
<>	157:ff67d9f36b67	612	}
<>	157:ff67d9f36b67	613	#endif /RCC_CFGR3_I2C3SW/
<>	157:ff67d9f36b67	614
<>	157:ff67d9f36b67	615	return i2c_frequency;
<>	157:ff67d9f36b67	616	}
<>	157:ff67d9f36b67	617
<>	157:ff67d9f36b67	618	#if defined(RCC_CFGR_I2SSRC)
<>	157:ff67d9f36b67	619	/**
<>	157:ff67d9f36b67	620	* @brief Return I2Sx clock frequency
<>	157:ff67d9f36b67	621	* @param I2SxSource This parameter can be one of the following values:
<>	157:ff67d9f36b67	622	* @arg @ref LL_RCC_I2S_CLKSOURCE
<>	157:ff67d9f36b67	623	* @retval I2S clock frequency (in Hz)
<>	157:ff67d9f36b67	624	* @arg @ref LL_RCC_PERIPH_FREQUENCY_NA indicates that external clock is used */
<>	157:ff67d9f36b67	625	uint32_t LL_RCC_GetI2SClockFreq(uint32_t I2SxSource)
<>	157:ff67d9f36b67	626	{
<>	157:ff67d9f36b67	627	uint32_t i2s_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
<>	157:ff67d9f36b67	628
<>	157:ff67d9f36b67	629	/* Check parameter */
<>	157:ff67d9f36b67	630	assert_param(IS_LL_RCC_I2S_CLKSOURCE(I2SxSource));
<>	157:ff67d9f36b67	631
<>	157:ff67d9f36b67	632	/* I2S1CLK clock frequency */
<>	157:ff67d9f36b67	633	switch (LL_RCC_GetI2SClockSource(I2SxSource))
<>	157:ff67d9f36b67	634	{
<>	157:ff67d9f36b67	635	case LL_RCC_I2S_CLKSOURCE_SYSCLK: /!< System clock selected as I2S clock source /
<>	157:ff67d9f36b67	636	i2s_frequency = RCC_GetSystemClockFreq();
<>	157:ff67d9f36b67	637	break;
<>	157:ff67d9f36b67	638
<>	157:ff67d9f36b67	639	case LL_RCC_I2S_CLKSOURCE_PIN: /!< External clock selected as I2S clock source /
<>	157:ff67d9f36b67	640	default:
<>	157:ff67d9f36b67	641	i2s_frequency = LL_RCC_PERIPH_FREQUENCY_NA;
<>	157:ff67d9f36b67	642	break;
<>	157:ff67d9f36b67	643	}
<>	157:ff67d9f36b67	644
<>	157:ff67d9f36b67	645	return i2s_frequency;
<>	157:ff67d9f36b67	646	}
<>	157:ff67d9f36b67	647	#endif /* RCC_CFGR_I2SSRC */
<>	157:ff67d9f36b67	648	#if defined(USB)
<>	157:ff67d9f36b67	649	/**
<>	157:ff67d9f36b67	650	* @brief Return USBx clock frequency
<>	157:ff67d9f36b67	651	* @param USBxSource This parameter can be one of the following values:
<>	157:ff67d9f36b67	652	* @arg @ref LL_RCC_USB_CLKSOURCE
<>	157:ff67d9f36b67	653	* @retval USB clock frequency (in Hz)
<>	157:ff67d9f36b67	654	* @arg @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI48) or PLL is not ready
<>	157:ff67d9f36b67	655	* @arg @ref LL_RCC_PERIPH_FREQUENCY_NA indicates that no clock source selected
<>	157:ff67d9f36b67	656	*/
<>	157:ff67d9f36b67	657	uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource)
<>	157:ff67d9f36b67	658	{
<>	157:ff67d9f36b67	659	uint32_t usb_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
<>	157:ff67d9f36b67	660
<>	157:ff67d9f36b67	661	/* Check parameter */
<>	157:ff67d9f36b67	662	assert_param(IS_LL_RCC_USB_CLKSOURCE(USBxSource));
<>	157:ff67d9f36b67	663
<>	157:ff67d9f36b67	664	/* USBCLK clock frequency */
<>	157:ff67d9f36b67	665	switch (LL_RCC_GetUSBClockSource(USBxSource))
<>	157:ff67d9f36b67	666	{
<>	157:ff67d9f36b67	667	case LL_RCC_USB_CLKSOURCE_PLL: /* PLL clock used as USB clock source */
<>	157:ff67d9f36b67	668	if (LL_RCC_PLL_IsReady())
<>	157:ff67d9f36b67	669	{
<>	157:ff67d9f36b67	670	usb_frequency = RCC_PLL_GetFreqDomain_SYS();
<>	157:ff67d9f36b67	671	}
<>	157:ff67d9f36b67	672	break;
<>	157:ff67d9f36b67	673
<>	157:ff67d9f36b67	674	case LL_RCC_USB_CLKSOURCE_PLL_DIV_1_5: /* PLL clock used as USB clock source */
<>	157:ff67d9f36b67	675	default:
<>	157:ff67d9f36b67	676	if (LL_RCC_PLL_IsReady())
<>	157:ff67d9f36b67	677	{
<>	157:ff67d9f36b67	678	usb_frequency = (RCC_PLL_GetFreqDomain_SYS() * 3) / 2;
<>	157:ff67d9f36b67	679	}
<>	157:ff67d9f36b67	680	break;
<>	157:ff67d9f36b67	681	}
<>	157:ff67d9f36b67	682
<>	157:ff67d9f36b67	683	return usb_frequency;
<>	157:ff67d9f36b67	684	}
<>	157:ff67d9f36b67	685	#endif /* USB */
<>	157:ff67d9f36b67	686
<>	157:ff67d9f36b67	687	#if defined(RCC_CFGR_ADCPRE) \|\| defined(RCC_CFGR2_ADC1PRES) \|\| defined(RCC_CFGR2_ADCPRE12) \|\| defined(RCC_CFGR2_ADCPRE34)
<>	157:ff67d9f36b67	688	/**
<>	157:ff67d9f36b67	689	* @brief Return ADCx clock frequency
<>	157:ff67d9f36b67	690	* @param ADCxSource This parameter can be one of the following values:
<>	157:ff67d9f36b67	691	* @arg @ref LL_RCC_ADC_CLKSOURCE (*)
<>	157:ff67d9f36b67	692	* @arg @ref LL_RCC_ADC1_CLKSOURCE (*)
<>	157:ff67d9f36b67	693	* @arg @ref LL_RCC_ADC12_CLKSOURCE (*)
<>	157:ff67d9f36b67	694	* @arg @ref LL_RCC_ADC34_CLKSOURCE (*)
<>	157:ff67d9f36b67	695	*
<>	157:ff67d9f36b67	696	* (*) value not defined in all devices
<>	157:ff67d9f36b67	697	* @retval ADC clock frequency (in Hz)
<>	157:ff67d9f36b67	698	*/
<>	157:ff67d9f36b67	699	uint32_t LL_RCC_GetADCClockFreq(uint32_t ADCxSource)
<>	157:ff67d9f36b67	700	{
<>	157:ff67d9f36b67	701	uint32_t adc_prescaler = 0U;
<>	157:ff67d9f36b67	702	uint32_t adc_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
<>	157:ff67d9f36b67	703
<>	157:ff67d9f36b67	704	/* Check parameter */
<>	157:ff67d9f36b67	705	assert_param(IS_LL_RCC_ADC_CLKSOURCE(ADCxSource));
<>	157:ff67d9f36b67	706
<>	157:ff67d9f36b67	707	/* Get ADC prescaler */
<>	157:ff67d9f36b67	708	adc_prescaler = LL_RCC_GetADCClockSource(ADCxSource);
<>	157:ff67d9f36b67	709
<>	157:ff67d9f36b67	710	#if defined(RCC_CFGR_ADCPRE)
<>	157:ff67d9f36b67	711	/* ADC frequency = PCLK2 frequency / ADC prescaler (2, 4, 6 or 8) */
<>	157:ff67d9f36b67	712	adc_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()))
<>	157:ff67d9f36b67	713	/ (((adc_prescaler >> POSITION_VAL(ADCxSource)) + 1U) * 2U);
<>	157:ff67d9f36b67	714	#else
<>	157:ff67d9f36b67	715	if ((adc_prescaler & 0x0000FFFFU) == ((uint32_t)0x00000000U))
<>	157:ff67d9f36b67	716	{
<>	157:ff67d9f36b67	717	/* ADC frequency = HCLK frequency */
<>	157:ff67d9f36b67	718	adc_frequency = RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq());
<>	157:ff67d9f36b67	719	}
<>	157:ff67d9f36b67	720	else
<>	157:ff67d9f36b67	721	{
<>	157:ff67d9f36b67	722	/* ADC frequency = PCLK2 frequency / ADC prescaler (from 1 to 256) */
<>	157:ff67d9f36b67	723	adc_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()))
<>	157:ff67d9f36b67	724	/ (aADCPrescTable[((adc_prescaler & 0x0000FFFFU) >> POSITION_VAL(ADCxSource)) & 0xFU]);
<>	157:ff67d9f36b67	725	}
<>	157:ff67d9f36b67	726	#endif /* RCC_CFGR_ADCPRE */
<>	157:ff67d9f36b67	727
<>	157:ff67d9f36b67	728	return adc_frequency;
<>	157:ff67d9f36b67	729	}
<>	157:ff67d9f36b67	730	#endif /RCC_CFGR_ADCPRE \|\| RCC_CFGR2_ADC1PRES \|\| RCC_CFGR2_ADCPRE12 \|\| RCC_CFGR2_ADCPRE34 /
<>	157:ff67d9f36b67	731
<>	157:ff67d9f36b67	732	#if defined(RCC_CFGR_SDPRE)
<>	157:ff67d9f36b67	733	/**
<>	157:ff67d9f36b67	734	* @brief Return SDADCx clock frequency
<>	157:ff67d9f36b67	735	* @param SDADCxSource This parameter can be one of the following values:
<>	157:ff67d9f36b67	736	* @arg @ref LL_RCC_SDADC_CLKSOURCE
<>	157:ff67d9f36b67	737	* @retval SDADC clock frequency (in Hz)
<>	157:ff67d9f36b67	738	*/
<>	157:ff67d9f36b67	739	uint32_t LL_RCC_GetSDADCClockFreq(uint32_t SDADCxSource)
<>	157:ff67d9f36b67	740	{
<>	157:ff67d9f36b67	741	uint32_t sdadc_prescaler = 0U;
<>	157:ff67d9f36b67	742	uint32_t sdadc_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
<>	157:ff67d9f36b67	743
<>	157:ff67d9f36b67	744	/* Check parameter */
<>	157:ff67d9f36b67	745	assert_param(IS_LL_RCC_SDADC_CLKSOURCE(SDADCxSource));
<>	157:ff67d9f36b67	746
<>	157:ff67d9f36b67	747	/* Get SDADC prescaler */
<>	157:ff67d9f36b67	748	sdadc_prescaler = LL_RCC_GetSDADCClockSource(SDADCxSource);
<>	157:ff67d9f36b67	749
<>	157:ff67d9f36b67	750	/* SDADC frequency = SYSTEM frequency / SDADC prescaler (from 2 to 48) */
<>	157:ff67d9f36b67	751	sdadc_frequency = RCC_GetSystemClockFreq()
<>	157:ff67d9f36b67	752	/ (aSDADCPrescTable[(sdadc_prescaler >> POSITION_VAL(SDADCxSource)) & 0xFU]);
<>	157:ff67d9f36b67	753
<>	157:ff67d9f36b67	754	return sdadc_frequency;
<>	157:ff67d9f36b67	755	}
<>	157:ff67d9f36b67	756	#endif /RCC_CFGR_SDPRE /
<>	157:ff67d9f36b67	757
<>	157:ff67d9f36b67	758	#if defined(CEC)
<>	157:ff67d9f36b67	759	/**
<>	157:ff67d9f36b67	760	* @brief Return CECx clock frequency
<>	157:ff67d9f36b67	761	* @param CECxSource This parameter can be one of the following values:
<>	157:ff67d9f36b67	762	* @arg @ref LL_RCC_CEC_CLKSOURCE
<>	157:ff67d9f36b67	763	* @retval CEC clock frequency (in Hz)
<>	157:ff67d9f36b67	764	* @arg @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillators (HSI or LSE) are not ready
<>	157:ff67d9f36b67	765	*/
<>	157:ff67d9f36b67	766	uint32_t LL_RCC_GetCECClockFreq(uint32_t CECxSource)
<>	157:ff67d9f36b67	767	{
<>	157:ff67d9f36b67	768	uint32_t cec_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
<>	157:ff67d9f36b67	769
<>	157:ff67d9f36b67	770	/* Check parameter */
<>	157:ff67d9f36b67	771	assert_param(IS_LL_RCC_CEC_CLKSOURCE(CECxSource));
<>	157:ff67d9f36b67	772
<>	157:ff67d9f36b67	773	/* CECCLK clock frequency */
<>	157:ff67d9f36b67	774	switch (LL_RCC_GetCECClockSource(CECxSource))
<>	157:ff67d9f36b67	775	{
<>	157:ff67d9f36b67	776	case LL_RCC_CEC_CLKSOURCE_HSI_DIV244: /* HSI / 244 clock used as CEC clock source */
<>	157:ff67d9f36b67	777	if (LL_RCC_HSI_IsReady())
<>	157:ff67d9f36b67	778	{
<>	157:ff67d9f36b67	779	cec_frequency = HSI_VALUE / 244U;
<>	157:ff67d9f36b67	780	}
<>	157:ff67d9f36b67	781	break;
<>	157:ff67d9f36b67	782
<>	157:ff67d9f36b67	783	case LL_RCC_CEC_CLKSOURCE_LSE: /* LSE clock used as CEC clock source */
<>	157:ff67d9f36b67	784	default:
<>	157:ff67d9f36b67	785	if (LL_RCC_LSE_IsReady())
<>	157:ff67d9f36b67	786	{
<>	157:ff67d9f36b67	787	cec_frequency = LSE_VALUE;
<>	157:ff67d9f36b67	788	}
<>	157:ff67d9f36b67	789	break;
<>	157:ff67d9f36b67	790	}
<>	157:ff67d9f36b67	791
<>	157:ff67d9f36b67	792	return cec_frequency;
<>	157:ff67d9f36b67	793	}
<>	157:ff67d9f36b67	794	#endif /* CEC */
<>	157:ff67d9f36b67	795
<>	157:ff67d9f36b67	796	#if defined(RCC_CFGR3_TIMSW)
<>	157:ff67d9f36b67	797	/**
<>	157:ff67d9f36b67	798	* @brief Return TIMx clock frequency
<>	157:ff67d9f36b67	799	* @param TIMxSource This parameter can be one of the following values:
<>	157:ff67d9f36b67	800	* @arg @ref LL_RCC_TIM1_CLKSOURCE
<>	157:ff67d9f36b67	801	* @arg @ref LL_RCC_TIM8_CLKSOURCE (*)
<>	157:ff67d9f36b67	802	* @arg @ref LL_RCC_TIM15_CLKSOURCE (*)
<>	157:ff67d9f36b67	803	* @arg @ref LL_RCC_TIM16_CLKSOURCE (*)
<>	157:ff67d9f36b67	804	* @arg @ref LL_RCC_TIM17_CLKSOURCE (*)
<>	157:ff67d9f36b67	805	* @arg @ref LL_RCC_TIM20_CLKSOURCE (*)
<>	157:ff67d9f36b67	806	* @arg @ref LL_RCC_TIM2_CLKSOURCE (*)
<>	157:ff67d9f36b67	807	* @arg @ref LL_RCC_TIM34_CLKSOURCE (*)
<>	157:ff67d9f36b67	808	*
<>	157:ff67d9f36b67	809	* (*) value not defined in all devices
<>	157:ff67d9f36b67	810	* @retval TIM clock frequency (in Hz)
<>	157:ff67d9f36b67	811	*/
<>	157:ff67d9f36b67	812	uint32_t LL_RCC_GetTIMClockFreq(uint32_t TIMxSource)
<>	157:ff67d9f36b67	813	{
<>	157:ff67d9f36b67	814	uint32_t tim_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
<>	157:ff67d9f36b67	815
<>	157:ff67d9f36b67	816	/* Check parameter */
<>	157:ff67d9f36b67	817	assert_param(IS_LL_RCC_TIM_CLKSOURCE(TIMxSource));
<>	157:ff67d9f36b67	818
<>	157:ff67d9f36b67	819	if (TIMxSource == LL_RCC_TIM1_CLKSOURCE)
<>	157:ff67d9f36b67	820	{
<>	157:ff67d9f36b67	821	/* TIM1CLK clock frequency */
<>	157:ff67d9f36b67	822	if (LL_RCC_GetTIMClockSource(LL_RCC_TIM1_CLKSOURCE) == LL_RCC_TIM1_CLKSOURCE_PCLK2)
<>	157:ff67d9f36b67	823	{
<>	157:ff67d9f36b67	824	/* PCLK2 used as TIM1 clock source */
<>	157:ff67d9f36b67	825	tim_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
<>	157:ff67d9f36b67	826	}
<>	157:ff67d9f36b67	827	else /* LL_RCC_TIM1_CLKSOURCE_PLL */
<>	157:ff67d9f36b67	828	{
<>	157:ff67d9f36b67	829	/* PLL clock used as TIM1 clock source */
<>	157:ff67d9f36b67	830	tim_frequency = RCC_PLL_GetFreqDomain_SYS();
<>	157:ff67d9f36b67	831	}
<>	157:ff67d9f36b67	832	}
<>	157:ff67d9f36b67	833
<>	157:ff67d9f36b67	834	#if defined(RCC_CFGR3_TIM8SW)
<>	157:ff67d9f36b67	835	if (TIMxSource == LL_RCC_TIM8_CLKSOURCE)
<>	157:ff67d9f36b67	836	{
<>	157:ff67d9f36b67	837	/* TIM8CLK clock frequency */
<>	157:ff67d9f36b67	838	if (LL_RCC_GetTIMClockSource(LL_RCC_TIM8_CLKSOURCE) == LL_RCC_TIM8_CLKSOURCE_PCLK2)
<>	157:ff67d9f36b67	839	{
<>	157:ff67d9f36b67	840	/* PCLK2 used as TIM8 clock source */
<>	157:ff67d9f36b67	841	tim_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
<>	157:ff67d9f36b67	842	}
<>	157:ff67d9f36b67	843	else /* LL_RCC_TIM8_CLKSOURCE_PLL */
<>	157:ff67d9f36b67	844	{
<>	157:ff67d9f36b67	845	/* PLL clock used as TIM8 clock source */
<>	157:ff67d9f36b67	846	tim_frequency = RCC_PLL_GetFreqDomain_SYS();
<>	157:ff67d9f36b67	847	}
<>	157:ff67d9f36b67	848	}
<>	157:ff67d9f36b67	849	#endif /RCC_CFGR3_TIM8SW/
<>	157:ff67d9f36b67	850
<>	157:ff67d9f36b67	851	#if defined(RCC_CFGR3_TIM15SW)
<>	157:ff67d9f36b67	852	if (TIMxSource == LL_RCC_TIM15_CLKSOURCE)
<>	157:ff67d9f36b67	853	{
<>	157:ff67d9f36b67	854	/* TIM15CLK clock frequency */
<>	157:ff67d9f36b67	855	if (LL_RCC_GetTIMClockSource(LL_RCC_TIM15_CLKSOURCE) == LL_RCC_TIM15_CLKSOURCE_PCLK2)
<>	157:ff67d9f36b67	856	{
<>	157:ff67d9f36b67	857	/* PCLK2 used as TIM15 clock source */
<>	157:ff67d9f36b67	858	tim_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
<>	157:ff67d9f36b67	859	}
<>	157:ff67d9f36b67	860	else /* LL_RCC_TIM15_CLKSOURCE_PLL */
<>	157:ff67d9f36b67	861	{
<>	157:ff67d9f36b67	862	/* PLL clock used as TIM15 clock source */
<>	157:ff67d9f36b67	863	tim_frequency = RCC_PLL_GetFreqDomain_SYS();
<>	157:ff67d9f36b67	864	}
<>	157:ff67d9f36b67	865	}
<>	157:ff67d9f36b67	866	#endif /RCC_CFGR3_TIM15SW/
<>	157:ff67d9f36b67	867
<>	157:ff67d9f36b67	868	#if defined(RCC_CFGR3_TIM16SW)
<>	157:ff67d9f36b67	869	if (TIMxSource == LL_RCC_TIM16_CLKSOURCE)
<>	157:ff67d9f36b67	870	{
<>	157:ff67d9f36b67	871	/* TIM16CLK clock frequency */
<>	157:ff67d9f36b67	872	if (LL_RCC_GetTIMClockSource(LL_RCC_TIM16_CLKSOURCE) == LL_RCC_TIM16_CLKSOURCE_PCLK2)
<>	157:ff67d9f36b67	873	{
<>	157:ff67d9f36b67	874	/* PCLK2 used as TIM16 clock source */
<>	157:ff67d9f36b67	875	tim_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
<>	157:ff67d9f36b67	876	}
<>	157:ff67d9f36b67	877	else /* LL_RCC_TIM16_CLKSOURCE_PLL */
<>	157:ff67d9f36b67	878	{
<>	157:ff67d9f36b67	879	/* PLL clock used as TIM16 clock source */
<>	157:ff67d9f36b67	880	tim_frequency = RCC_PLL_GetFreqDomain_SYS();
<>	157:ff67d9f36b67	881	}
<>	157:ff67d9f36b67	882	}
<>	157:ff67d9f36b67	883	#endif /RCC_CFGR3_TIM16SW/
<>	157:ff67d9f36b67	884
<>	157:ff67d9f36b67	885	#if defined(RCC_CFGR3_TIM17SW)
<>	157:ff67d9f36b67	886	if (TIMxSource == LL_RCC_TIM17_CLKSOURCE)
<>	157:ff67d9f36b67	887	{
<>	157:ff67d9f36b67	888	/* TIM17CLK clock frequency */
<>	157:ff67d9f36b67	889	if (LL_RCC_GetTIMClockSource(LL_RCC_TIM17_CLKSOURCE) == LL_RCC_TIM17_CLKSOURCE_PCLK2)
<>	157:ff67d9f36b67	890	{
<>	157:ff67d9f36b67	891	/* PCLK2 used as TIM17 clock source */
<>	157:ff67d9f36b67	892	tim_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
<>	157:ff67d9f36b67	893	}
<>	157:ff67d9f36b67	894	else /* LL_RCC_TIM17_CLKSOURCE_PLL */
<>	157:ff67d9f36b67	895	{
<>	157:ff67d9f36b67	896	/* PLL clock used as TIM17 clock source */
<>	157:ff67d9f36b67	897	tim_frequency = RCC_PLL_GetFreqDomain_SYS();
<>	157:ff67d9f36b67	898	}
<>	157:ff67d9f36b67	899	}
<>	157:ff67d9f36b67	900	#endif /RCC_CFGR3_TIM17SW/
<>	157:ff67d9f36b67	901
<>	157:ff67d9f36b67	902	#if defined(RCC_CFGR3_TIM20SW)
<>	157:ff67d9f36b67	903	if (TIMxSource == LL_RCC_TIM20_CLKSOURCE)
<>	157:ff67d9f36b67	904	{
<>	157:ff67d9f36b67	905	/* TIM20CLK clock frequency */
<>	157:ff67d9f36b67	906	if (LL_RCC_GetTIMClockSource(LL_RCC_TIM20_CLKSOURCE) == LL_RCC_TIM20_CLKSOURCE_PCLK2)
<>	157:ff67d9f36b67	907	{
<>	157:ff67d9f36b67	908	/* PCLK2 used as TIM20 clock source */
<>	157:ff67d9f36b67	909	tim_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
<>	157:ff67d9f36b67	910	}
<>	157:ff67d9f36b67	911	else /* LL_RCC_TIM20_CLKSOURCE_PLL */
<>	157:ff67d9f36b67	912	{
<>	157:ff67d9f36b67	913	/* PLL clock used as TIM20 clock source */
<>	157:ff67d9f36b67	914	tim_frequency = RCC_PLL_GetFreqDomain_SYS();
<>	157:ff67d9f36b67	915	}
<>	157:ff67d9f36b67	916	}
<>	157:ff67d9f36b67	917	#endif /RCC_CFGR3_TIM20SW/
<>	157:ff67d9f36b67	918
<>	157:ff67d9f36b67	919	#if defined(RCC_CFGR3_TIM2SW)
<>	157:ff67d9f36b67	920	if (TIMxSource == LL_RCC_TIM2_CLKSOURCE)
<>	157:ff67d9f36b67	921	{
<>	157:ff67d9f36b67	922	/* TIM2CLK clock frequency */
<>	157:ff67d9f36b67	923	if (LL_RCC_GetTIMClockSource(LL_RCC_TIM2_CLKSOURCE) == LL_RCC_TIM2_CLKSOURCE_PCLK1)
<>	157:ff67d9f36b67	924	{
<>	157:ff67d9f36b67	925	/* PCLK1 used as TIM2 clock source */
<>	157:ff67d9f36b67	926	tim_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
<>	157:ff67d9f36b67	927	}
<>	157:ff67d9f36b67	928	else /* LL_RCC_TIM2_CLKSOURCE_PLL */
<>	157:ff67d9f36b67	929	{
<>	157:ff67d9f36b67	930	/* PLL clock used as TIM2 clock source */
<>	157:ff67d9f36b67	931	tim_frequency = RCC_PLL_GetFreqDomain_SYS();
<>	157:ff67d9f36b67	932	}
<>	157:ff67d9f36b67	933	}
<>	157:ff67d9f36b67	934	#endif /RCC_CFGR3_TIM2SW/
<>	157:ff67d9f36b67	935
<>	157:ff67d9f36b67	936	#if defined(RCC_CFGR3_TIM34SW)
<>	157:ff67d9f36b67	937	if (TIMxSource == LL_RCC_TIM34_CLKSOURCE)
<>	157:ff67d9f36b67	938	{
<>	157:ff67d9f36b67	939	/* TIM3/4 CLK clock frequency */
<>	157:ff67d9f36b67	940	if (LL_RCC_GetTIMClockSource(LL_RCC_TIM34_CLKSOURCE) == LL_RCC_TIM34_CLKSOURCE_PCLK1)
<>	157:ff67d9f36b67	941	{
<>	157:ff67d9f36b67	942	/* PCLK1 used as TIM3/4 clock source */
<>	157:ff67d9f36b67	943	tim_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
<>	157:ff67d9f36b67	944	}
<>	157:ff67d9f36b67	945	else /* LL_RCC_TIM34_CLKSOURCE_PLL */
<>	157:ff67d9f36b67	946	{
<>	157:ff67d9f36b67	947	/* PLL clock used as TIM3/4 clock source */
<>	157:ff67d9f36b67	948	tim_frequency = RCC_PLL_GetFreqDomain_SYS();
<>	157:ff67d9f36b67	949	}
<>	157:ff67d9f36b67	950	}
<>	157:ff67d9f36b67	951	#endif /RCC_CFGR3_TIM34SW/
<>	157:ff67d9f36b67	952
<>	157:ff67d9f36b67	953	return tim_frequency;
<>	157:ff67d9f36b67	954	}
<>	157:ff67d9f36b67	955	#endif /RCC_CFGR3_TIMSW/
<>	157:ff67d9f36b67	956
<>	157:ff67d9f36b67	957	#if defined(HRTIM1)
<>	157:ff67d9f36b67	958	/**
<>	157:ff67d9f36b67	959	* @brief Return HRTIMx clock frequency
<>	157:ff67d9f36b67	960	* @param HRTIMxSource This parameter can be one of the following values:
<>	157:ff67d9f36b67	961	* @arg @ref LL_RCC_HRTIM1_CLKSOURCE
<>	157:ff67d9f36b67	962	* @retval HRTIM clock frequency (in Hz)
<>	157:ff67d9f36b67	963	*/
<>	157:ff67d9f36b67	964	uint32_t LL_RCC_GetHRTIMClockFreq(uint32_t HRTIMxSource)
<>	157:ff67d9f36b67	965	{
<>	157:ff67d9f36b67	966	uint32_t hrtim_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
<>	157:ff67d9f36b67	967
<>	157:ff67d9f36b67	968	/* Check parameter */
<>	157:ff67d9f36b67	969	assert_param(IS_LL_RCC_HRTIM_CLKSOURCE(HRTIMxSource));
<>	157:ff67d9f36b67	970
<>	157:ff67d9f36b67	971	/* HRTIM1CLK clock frequency */
<>	157:ff67d9f36b67	972	if (LL_RCC_GetTIMClockSource(LL_RCC_HRTIM1_CLKSOURCE) == LL_RCC_HRTIM1_CLKSOURCE_PCLK2)
<>	157:ff67d9f36b67	973	{
<>	157:ff67d9f36b67	974	/* PCLK2 used as HRTIM1 clock source */
<>	157:ff67d9f36b67	975	hrtim_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
<>	157:ff67d9f36b67	976	}
<>	157:ff67d9f36b67	977	else /* LL_RCC_HRTIM1_CLKSOURCE_PLL */
<>	157:ff67d9f36b67	978	{
<>	157:ff67d9f36b67	979	/* PLL clock used as HRTIM1 clock source */
<>	157:ff67d9f36b67	980	hrtim_frequency = RCC_PLL_GetFreqDomain_SYS();
<>	157:ff67d9f36b67	981	}
<>	157:ff67d9f36b67	982
<>	157:ff67d9f36b67	983	return hrtim_frequency;
<>	157:ff67d9f36b67	984	}
<>	157:ff67d9f36b67	985	#endif /* HRTIM1 */
<>	157:ff67d9f36b67	986
<>	157:ff67d9f36b67	987	/**
<>	157:ff67d9f36b67	988	* @}
<>	157:ff67d9f36b67	989	*/
<>	157:ff67d9f36b67	990
<>	157:ff67d9f36b67	991	/**
<>	157:ff67d9f36b67	992	* @}
<>	157:ff67d9f36b67	993	*/
<>	157:ff67d9f36b67	994
<>	157:ff67d9f36b67	995	/** @addtogroup RCC_LL_Private_Functions
<>	157:ff67d9f36b67	996	* @{
<>	157:ff67d9f36b67	997	*/
<>	157:ff67d9f36b67	998
<>	157:ff67d9f36b67	999	/**
<>	157:ff67d9f36b67	1000	* @brief Return SYSTEM clock frequency
<>	157:ff67d9f36b67	1001	* @retval SYSTEM clock frequency (in Hz)
<>	157:ff67d9f36b67	1002	*/
<>	157:ff67d9f36b67	1003	uint32_t RCC_GetSystemClockFreq(void)
<>	157:ff67d9f36b67	1004	{
<>	157:ff67d9f36b67	1005	uint32_t frequency = 0U;
<>	157:ff67d9f36b67	1006
<>	157:ff67d9f36b67	1007	/* Get SYSCLK source -------------------------------------------------------*/
<>	157:ff67d9f36b67	1008	switch (LL_RCC_GetSysClkSource())
<>	157:ff67d9f36b67	1009	{
<>	157:ff67d9f36b67	1010	case LL_RCC_SYS_CLKSOURCE_STATUS_HSI: /* HSI used as system clock source */
<>	157:ff67d9f36b67	1011	frequency = HSI_VALUE;
<>	157:ff67d9f36b67	1012	break;
<>	157:ff67d9f36b67	1013
<>	157:ff67d9f36b67	1014	case LL_RCC_SYS_CLKSOURCE_STATUS_HSE: /* HSE used as system clock source */
<>	157:ff67d9f36b67	1015	frequency = HSE_VALUE;
<>	157:ff67d9f36b67	1016	break;
<>	157:ff67d9f36b67	1017
<>	157:ff67d9f36b67	1018	case LL_RCC_SYS_CLKSOURCE_STATUS_PLL: /* PLL used as system clock source */
<>	157:ff67d9f36b67	1019	frequency = RCC_PLL_GetFreqDomain_SYS();
<>	157:ff67d9f36b67	1020	break;
<>	157:ff67d9f36b67	1021
<>	157:ff67d9f36b67	1022	default:
<>	157:ff67d9f36b67	1023	frequency = HSI_VALUE;
<>	157:ff67d9f36b67	1024	break;
<>	157:ff67d9f36b67	1025	}
<>	157:ff67d9f36b67	1026
<>	157:ff67d9f36b67	1027	return frequency;
<>	157:ff67d9f36b67	1028	}
<>	157:ff67d9f36b67	1029
<>	157:ff67d9f36b67	1030	/**
<>	157:ff67d9f36b67	1031	* @brief Return HCLK clock frequency
<>	157:ff67d9f36b67	1032	* @param SYSCLK_Frequency SYSCLK clock frequency
<>	157:ff67d9f36b67	1033	* @retval HCLK clock frequency (in Hz)
<>	157:ff67d9f36b67	1034	*/
<>	157:ff67d9f36b67	1035	uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency)
<>	157:ff67d9f36b67	1036	{
<>	157:ff67d9f36b67	1037	/* HCLK clock frequency */
<>	157:ff67d9f36b67	1038	return __LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, LL_RCC_GetAHBPrescaler());
<>	157:ff67d9f36b67	1039	}
<>	157:ff67d9f36b67	1040
<>	157:ff67d9f36b67	1041	/**
<>	157:ff67d9f36b67	1042	* @brief Return PCLK1 clock frequency
<>	157:ff67d9f36b67	1043	* @param HCLK_Frequency HCLK clock frequency
<>	157:ff67d9f36b67	1044	* @retval PCLK1 clock frequency (in Hz)
<>	157:ff67d9f36b67	1045	*/
<>	157:ff67d9f36b67	1046	uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency)
<>	157:ff67d9f36b67	1047	{
<>	157:ff67d9f36b67	1048	/* PCLK1 clock frequency */
<>	157:ff67d9f36b67	1049	return __LL_RCC_CALC_PCLK1_FREQ(HCLK_Frequency, LL_RCC_GetAPB1Prescaler());
<>	157:ff67d9f36b67	1050	}
<>	157:ff67d9f36b67	1051
<>	157:ff67d9f36b67	1052	/**
<>	157:ff67d9f36b67	1053	* @brief Return PCLK2 clock frequency
<>	157:ff67d9f36b67	1054	* @param HCLK_Frequency HCLK clock frequency
<>	157:ff67d9f36b67	1055	* @retval PCLK2 clock frequency (in Hz)
<>	157:ff67d9f36b67	1056	*/
<>	157:ff67d9f36b67	1057	uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency)
<>	157:ff67d9f36b67	1058	{
<>	157:ff67d9f36b67	1059	/* PCLK2 clock frequency */
<>	157:ff67d9f36b67	1060	return __LL_RCC_CALC_PCLK2_FREQ(HCLK_Frequency, LL_RCC_GetAPB2Prescaler());
<>	157:ff67d9f36b67	1061	}
<>	157:ff67d9f36b67	1062
<>	157:ff67d9f36b67	1063	/**
<>	157:ff67d9f36b67	1064	* @brief Return PLL clock frequency used for system domain
<>	157:ff67d9f36b67	1065	* @retval PLL clock frequency (in Hz)
<>	157:ff67d9f36b67	1066	*/
<>	157:ff67d9f36b67	1067	uint32_t RCC_PLL_GetFreqDomain_SYS(void)
<>	157:ff67d9f36b67	1068	{
<>	157:ff67d9f36b67	1069	uint32_t pllinputfreq = 0U, pllsource = 0U;
<>	157:ff67d9f36b67	1070
<>	157:ff67d9f36b67	1071	/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL divider) * PLL Multiplicator */
<>	157:ff67d9f36b67	1072
<>	157:ff67d9f36b67	1073	/* Get PLL source */
<>	157:ff67d9f36b67	1074	pllsource = LL_RCC_PLL_GetMainSource();
<>	157:ff67d9f36b67	1075
<>	157:ff67d9f36b67	1076	switch (pllsource)
<>	157:ff67d9f36b67	1077	{
<>	157:ff67d9f36b67	1078	#if defined(RCC_PLLSRC_PREDIV1_SUPPORT)
<>	157:ff67d9f36b67	1079	case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
<>	157:ff67d9f36b67	1080	pllinputfreq = HSI_VALUE;
<>	157:ff67d9f36b67	1081	#else
<>	157:ff67d9f36b67	1082	case LL_RCC_PLLSOURCE_HSI_DIV_2: /* HSI used as PLL clock source */
<>	157:ff67d9f36b67	1083	pllinputfreq = HSI_VALUE / 2;
<>	157:ff67d9f36b67	1084	#endif /* RCC_PLLSRC_PREDIV1_SUPPORT */
<>	157:ff67d9f36b67	1085	break;
<>	157:ff67d9f36b67	1086
<>	157:ff67d9f36b67	1087	case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
<>	157:ff67d9f36b67	1088	pllinputfreq = HSE_VALUE;
<>	157:ff67d9f36b67	1089	break;
<>	157:ff67d9f36b67	1090
<>	157:ff67d9f36b67	1091	default:
<>	157:ff67d9f36b67	1092	#if defined(RCC_PLLSRC_PREDIV1_SUPPORT)
<>	157:ff67d9f36b67	1093	pllinputfreq = HSI_VALUE;
<>	157:ff67d9f36b67	1094	#else
<>	157:ff67d9f36b67	1095	pllinputfreq = HSI_VALUE / 2;
<>	157:ff67d9f36b67	1096	#endif /* RCC_PLLSRC_PREDIV1_SUPPORT */
<>	157:ff67d9f36b67	1097	break;
<>	157:ff67d9f36b67	1098	}
<>	157:ff67d9f36b67	1099	#if defined(RCC_PLLSRC_PREDIV1_SUPPORT)
<>	157:ff67d9f36b67	1100	return __LL_RCC_CALC_PLLCLK_FREQ(pllinputfreq, LL_RCC_PLL_GetMultiplicator(), LL_RCC_PLL_GetPrediv());
<>	157:ff67d9f36b67	1101	#else
<>	157:ff67d9f36b67	1102	return __LL_RCC_CALC_PLLCLK_FREQ((pllinputfreq / (LL_RCC_PLL_GetPrediv() + 1U)), LL_RCC_PLL_GetMultiplicator());
<>	157:ff67d9f36b67	1103	#endif /* RCC_PLLSRC_PREDIV1_SUPPORT */
<>	157:ff67d9f36b67	1104	}
<>	157:ff67d9f36b67	1105	/**
<>	157:ff67d9f36b67	1106	* @}
<>	157:ff67d9f36b67	1107	*/
<>	157:ff67d9f36b67	1108
<>	157:ff67d9f36b67	1109	/**
<>	157:ff67d9f36b67	1110	* @}
<>	157:ff67d9f36b67	1111	*/
<>	157:ff67d9f36b67	1112
<>	157:ff67d9f36b67	1113	#endif /* defined(RCC) */
<>	157:ff67d9f36b67	1114
<>	157:ff67d9f36b67	1115	/**
<>	157:ff67d9f36b67	1116	* @}
<>	157:ff67d9f36b67	1117	*/
<>	157:ff67d9f36b67	1118
<>	157:ff67d9f36b67	1119	#endif /* USE_FULL_LL_DRIVER */
<>	157:ff67d9f36b67	1120
<>	157:ff67d9f36b67	1121	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/