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targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_spi.h@182:a56a73fd2a6f, 2018-03-20 (annotated)

Committer:: AnnaBridge
Date:: Tue Mar 20 16:56:18 2018 +0000
Revision:: 182:a56a73fd2a6f
Parent:: 161:2cc1468da177
Child:: 186:707f6e361f3e

mbed-dev library. Release version 160

Who changed what in which revision?

User	Revision	Line number	New contents of line
<>	161:2cc1468da177	1	/**
<>	161:2cc1468da177	2	******************************************************************************
<>	161:2cc1468da177	3	* @file stm32f7xx_ll_spi.h
<>	161:2cc1468da177	4	* @author MCD Application Team
<>	161:2cc1468da177	5	* @brief Header file of SPI LL module.
<>	161:2cc1468da177	6	******************************************************************************
<>	161:2cc1468da177	7	* @attention
<>	161:2cc1468da177	8	*
<>	161:2cc1468da177	9	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<>	161:2cc1468da177	10	*
<>	161:2cc1468da177	11	* Redistribution and use in source and binary forms, with or without modification,
<>	161:2cc1468da177	12	* are permitted provided that the following conditions are met:
<>	161:2cc1468da177	13	* 1. Redistributions of source code must retain the above copyright notice,
<>	161:2cc1468da177	14	* this list of conditions and the following disclaimer.
<>	161:2cc1468da177	15	* 2. Redistributions in binary form must reproduce the above copyright notice,
<>	161:2cc1468da177	16	* this list of conditions and the following disclaimer in the documentation
<>	161:2cc1468da177	17	* and/or other materials provided with the distribution.
<>	161:2cc1468da177	18	* 3. Neither the name of STMicroelectronics nor the names of its contributors
<>	161:2cc1468da177	19	* may be used to endorse or promote products derived from this software
<>	161:2cc1468da177	20	* without specific prior written permission.
<>	161:2cc1468da177	21	*
<>	161:2cc1468da177	22	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<>	161:2cc1468da177	23	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<>	161:2cc1468da177	24	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<>	161:2cc1468da177	25	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<>	161:2cc1468da177	26	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<>	161:2cc1468da177	27	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<>	161:2cc1468da177	28	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<>	161:2cc1468da177	29	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<>	161:2cc1468da177	30	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<>	161:2cc1468da177	31	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<>	161:2cc1468da177	32	*
<>	161:2cc1468da177	33	******************************************************************************
<>	161:2cc1468da177	34	*/
<>	161:2cc1468da177	35
<>	161:2cc1468da177	36	/* Define to prevent recursive inclusion -------------------------------------*/
<>	161:2cc1468da177	37	#ifndef __STM32F7xx_LL_SPI_H
<>	161:2cc1468da177	38	#define __STM32F7xx_LL_SPI_H
<>	161:2cc1468da177	39
<>	161:2cc1468da177	40	#ifdef __cplusplus
<>	161:2cc1468da177	41	extern "C" {
<>	161:2cc1468da177	42	#endif
<>	161:2cc1468da177	43
<>	161:2cc1468da177	44	/* Includes ------------------------------------------------------------------*/
<>	161:2cc1468da177	45	#include "stm32f7xx.h"
<>	161:2cc1468da177	46
<>	161:2cc1468da177	47	/** @addtogroup STM32F7xx_LL_Driver
<>	161:2cc1468da177	48	* @{
<>	161:2cc1468da177	49	*/
<>	161:2cc1468da177	50
<>	161:2cc1468da177	51	#if defined (SPI1) \|\| defined (SPI2) \|\| defined (SPI3) \|\| defined(SPI4) \|\| defined(SPI5) \|\| defined(SPI6)
<>	161:2cc1468da177	52
<>	161:2cc1468da177	53	/** @defgroup SPI_LL SPI
<>	161:2cc1468da177	54	* @{
<>	161:2cc1468da177	55	*/
<>	161:2cc1468da177	56
<>	161:2cc1468da177	57	/* Private types -------------------------------------------------------------*/
<>	161:2cc1468da177	58	/* Private variables ---------------------------------------------------------*/
<>	161:2cc1468da177	59	/* Private macros ------------------------------------------------------------*/
<>	161:2cc1468da177	60
<>	161:2cc1468da177	61	/* Exported types ------------------------------------------------------------*/
<>	161:2cc1468da177	62	#if defined(USE_FULL_LL_DRIVER)
<>	161:2cc1468da177	63	/** @defgroup SPI_LL_ES_INIT SPI Exported Init structure
<>	161:2cc1468da177	64	* @{
<>	161:2cc1468da177	65	*/
<>	161:2cc1468da177	66
<>	161:2cc1468da177	67	/**
<>	161:2cc1468da177	68	* @brief SPI Init structures definition
<>	161:2cc1468da177	69	*/
<>	161:2cc1468da177	70	typedef struct
<>	161:2cc1468da177	71	{
<>	161:2cc1468da177	72	uint32_t TransferDirection; /*!< Specifies the SPI unidirectional or bidirectional data mode.
<>	161:2cc1468da177	73	This parameter can be a value of @ref SPI_LL_EC_TRANSFER_MODE.
<>	161:2cc1468da177	74
<>	161:2cc1468da177	75	This feature can be modified afterwards using unitary function @ref LL_SPI_SetTransferDirection().*/
<>	161:2cc1468da177	76
<>	161:2cc1468da177	77	uint32_t Mode; /*!< Specifies the SPI mode (Master/Slave).
<>	161:2cc1468da177	78	This parameter can be a value of @ref SPI_LL_EC_MODE.
<>	161:2cc1468da177	79
<>	161:2cc1468da177	80	This feature can be modified afterwards using unitary function @ref LL_SPI_SetMode().*/
<>	161:2cc1468da177	81
<>	161:2cc1468da177	82	uint32_t DataWidth; /*!< Specifies the SPI data width.
<>	161:2cc1468da177	83	This parameter can be a value of @ref SPI_LL_EC_DATAWIDTH.
<>	161:2cc1468da177	84
<>	161:2cc1468da177	85	This feature can be modified afterwards using unitary function @ref LL_SPI_SetDataWidth().*/
<>	161:2cc1468da177	86
<>	161:2cc1468da177	87	uint32_t ClockPolarity; /*!< Specifies the serial clock steady state.
<>	161:2cc1468da177	88	This parameter can be a value of @ref SPI_LL_EC_POLARITY.
<>	161:2cc1468da177	89
<>	161:2cc1468da177	90	This feature can be modified afterwards using unitary function @ref LL_SPI_SetClockPolarity().*/
<>	161:2cc1468da177	91
<>	161:2cc1468da177	92	uint32_t ClockPhase; /*!< Specifies the clock active edge for the bit capture.
<>	161:2cc1468da177	93	This parameter can be a value of @ref SPI_LL_EC_PHASE.
<>	161:2cc1468da177	94
<>	161:2cc1468da177	95	This feature can be modified afterwards using unitary function @ref LL_SPI_SetClockPhase().*/
<>	161:2cc1468da177	96
<>	161:2cc1468da177	97	uint32_t NSS; /*!< Specifies whether the NSS signal is managed by hardware (NSS pin) or by software using the SSI bit.
<>	161:2cc1468da177	98	This parameter can be a value of @ref SPI_LL_EC_NSS_MODE.
<>	161:2cc1468da177	99
<>	161:2cc1468da177	100	This feature can be modified afterwards using unitary function @ref LL_SPI_SetNSSMode().*/
<>	161:2cc1468da177	101
<>	161:2cc1468da177	102	uint32_t BaudRate; /*!< Specifies the BaudRate prescaler value which will be used to configure the transmit and receive SCK clock.
<>	161:2cc1468da177	103	This parameter can be a value of @ref SPI_LL_EC_BAUDRATEPRESCALER.
<>	161:2cc1468da177	104	@note The communication clock is derived from the master clock. The slave clock does not need to be set.
<>	161:2cc1468da177	105
<>	161:2cc1468da177	106	This feature can be modified afterwards using unitary function @ref LL_SPI_SetBaudRatePrescaler().*/
<>	161:2cc1468da177	107
<>	161:2cc1468da177	108	uint32_t BitOrder; /*!< Specifies whether data transfers start from MSB or LSB bit.
<>	161:2cc1468da177	109	This parameter can be a value of @ref SPI_LL_EC_BIT_ORDER.
<>	161:2cc1468da177	110
<>	161:2cc1468da177	111	This feature can be modified afterwards using unitary function @ref LL_SPI_SetTransferBitOrder().*/
<>	161:2cc1468da177	112
<>	161:2cc1468da177	113	uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not.
<>	161:2cc1468da177	114	This parameter can be a value of @ref SPI_LL_EC_CRC_CALCULATION.
<>	161:2cc1468da177	115
<>	161:2cc1468da177	116	This feature can be modified afterwards using unitary functions @ref LL_SPI_EnableCRC() and @ref LL_SPI_DisableCRC().*/
<>	161:2cc1468da177	117
<>	161:2cc1468da177	118	uint32_t CRCPoly; /*!< Specifies the polynomial used for the CRC calculation.
<>	161:2cc1468da177	119	This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFF.
<>	161:2cc1468da177	120
<>	161:2cc1468da177	121	This feature can be modified afterwards using unitary function @ref LL_SPI_SetCRCPolynomial().*/
<>	161:2cc1468da177	122
<>	161:2cc1468da177	123	} LL_SPI_InitTypeDef;
<>	161:2cc1468da177	124
<>	161:2cc1468da177	125	/**
<>	161:2cc1468da177	126	* @}
<>	161:2cc1468da177	127	*/
<>	161:2cc1468da177	128	#endif /* USE_FULL_LL_DRIVER */
<>	161:2cc1468da177	129
<>	161:2cc1468da177	130	/* Exported constants --------------------------------------------------------*/
<>	161:2cc1468da177	131	/** @defgroup SPI_LL_Exported_Constants SPI Exported Constants
<>	161:2cc1468da177	132	* @{
<>	161:2cc1468da177	133	*/
<>	161:2cc1468da177	134
<>	161:2cc1468da177	135	/** @defgroup SPI_LL_EC_GET_FLAG Get Flags Defines
<>	161:2cc1468da177	136	* @brief Flags defines which can be used with LL_SPI_ReadReg function
<>	161:2cc1468da177	137	* @{
<>	161:2cc1468da177	138	*/
<>	161:2cc1468da177	139	#define LL_SPI_SR_RXNE SPI_SR_RXNE /!< Rx buffer not empty flag /
<>	161:2cc1468da177	140	#define LL_SPI_SR_TXE SPI_SR_TXE /!< Tx buffer empty flag /
<>	161:2cc1468da177	141	#define LL_SPI_SR_BSY SPI_SR_BSY /!< Busy flag /
<>	161:2cc1468da177	142	#define LL_SPI_SR_CRCERR SPI_SR_CRCERR /!< CRC error flag /
<>	161:2cc1468da177	143	#define LL_SPI_SR_MODF SPI_SR_MODF /!< Mode fault flag /
<>	161:2cc1468da177	144	#define LL_SPI_SR_OVR SPI_SR_OVR /!< Overrun flag /
<>	161:2cc1468da177	145	#define LL_SPI_SR_FRE SPI_SR_FRE /!< TI mode frame format error flag /
<>	161:2cc1468da177	146	/**
<>	161:2cc1468da177	147	* @}
<>	161:2cc1468da177	148	*/
<>	161:2cc1468da177	149
<>	161:2cc1468da177	150	/** @defgroup SPI_LL_EC_IT IT Defines
<>	161:2cc1468da177	151	* @brief IT defines which can be used with LL_SPI_ReadReg and LL_SPI_WriteReg functions
<>	161:2cc1468da177	152	* @{
<>	161:2cc1468da177	153	*/
<>	161:2cc1468da177	154	#define LL_SPI_CR2_RXNEIE SPI_CR2_RXNEIE /!< Rx buffer not empty interrupt enable /
<>	161:2cc1468da177	155	#define LL_SPI_CR2_TXEIE SPI_CR2_TXEIE /!< Tx buffer empty interrupt enable /
<>	161:2cc1468da177	156	#define LL_SPI_CR2_ERRIE SPI_CR2_ERRIE /!< Error interrupt enable /
<>	161:2cc1468da177	157	/**
<>	161:2cc1468da177	158	* @}
<>	161:2cc1468da177	159	*/
<>	161:2cc1468da177	160
<>	161:2cc1468da177	161	/** @defgroup SPI_LL_EC_MODE Operation Mode
<>	161:2cc1468da177	162	* @{
<>	161:2cc1468da177	163	*/
<>	161:2cc1468da177	164	#define LL_SPI_MODE_MASTER (SPI_CR1_MSTR \| SPI_CR1_SSI) /!< Master configuration /
<>	161:2cc1468da177	165	#define LL_SPI_MODE_SLAVE 0x00000000U /!< Slave configuration /
<>	161:2cc1468da177	166	/**
<>	161:2cc1468da177	167	* @}
<>	161:2cc1468da177	168	*/
<>	161:2cc1468da177	169
<>	161:2cc1468da177	170	/** @defgroup SPI_LL_EC_PROTOCOL Serial Protocol
<>	161:2cc1468da177	171	* @{
<>	161:2cc1468da177	172	*/
<>	161:2cc1468da177	173	#define LL_SPI_PROTOCOL_MOTOROLA 0x00000000U /!< Motorola mode. Used as default value /
<>	161:2cc1468da177	174	#define LL_SPI_PROTOCOL_TI (SPI_CR2_FRF) /!< TI mode /
<>	161:2cc1468da177	175	/**
<>	161:2cc1468da177	176	* @}
<>	161:2cc1468da177	177	*/
<>	161:2cc1468da177	178
<>	161:2cc1468da177	179	/** @defgroup SPI_LL_EC_PHASE Clock Phase
<>	161:2cc1468da177	180	* @{
<>	161:2cc1468da177	181	*/
<>	161:2cc1468da177	182	#define LL_SPI_PHASE_1EDGE 0x00000000U /!< First clock transition is the first data capture edge /
<>	161:2cc1468da177	183	#define LL_SPI_PHASE_2EDGE (SPI_CR1_CPHA) /!< Second clock transition is the first data capture edge /
<>	161:2cc1468da177	184	/**
<>	161:2cc1468da177	185	* @}
<>	161:2cc1468da177	186	*/
<>	161:2cc1468da177	187
<>	161:2cc1468da177	188	/** @defgroup SPI_LL_EC_POLARITY Clock Polarity
<>	161:2cc1468da177	189	* @{
<>	161:2cc1468da177	190	*/
<>	161:2cc1468da177	191	#define LL_SPI_POLARITY_LOW 0x00000000U /!< Clock to 0 when idle /
<>	161:2cc1468da177	192	#define LL_SPI_POLARITY_HIGH (SPI_CR1_CPOL) /!< Clock to 1 when idle /
<>	161:2cc1468da177	193	/**
<>	161:2cc1468da177	194	* @}
<>	161:2cc1468da177	195	*/
<>	161:2cc1468da177	196
<>	161:2cc1468da177	197	/** @defgroup SPI_LL_EC_BAUDRATEPRESCALER Baud Rate Prescaler
<>	161:2cc1468da177	198	* @{
<>	161:2cc1468da177	199	*/
<>	161:2cc1468da177	200	#define LL_SPI_BAUDRATEPRESCALER_DIV2 0x00000000U /!< BaudRate control equal to fPCLK/2 /
<>	161:2cc1468da177	201	#define LL_SPI_BAUDRATEPRESCALER_DIV4 (SPI_CR1_BR_0) /!< BaudRate control equal to fPCLK/4 /
<>	161:2cc1468da177	202	#define LL_SPI_BAUDRATEPRESCALER_DIV8 (SPI_CR1_BR_1) /!< BaudRate control equal to fPCLK/8 /
<>	161:2cc1468da177	203	#define LL_SPI_BAUDRATEPRESCALER_DIV16 (SPI_CR1_BR_1 \| SPI_CR1_BR_0) /!< BaudRate control equal to fPCLK/16 /
<>	161:2cc1468da177	204	#define LL_SPI_BAUDRATEPRESCALER_DIV32 (SPI_CR1_BR_2) /!< BaudRate control equal to fPCLK/32 /
<>	161:2cc1468da177	205	#define LL_SPI_BAUDRATEPRESCALER_DIV64 (SPI_CR1_BR_2 \| SPI_CR1_BR_0) /!< BaudRate control equal to fPCLK/64 /
<>	161:2cc1468da177	206	#define LL_SPI_BAUDRATEPRESCALER_DIV128 (SPI_CR1_BR_2 \| SPI_CR1_BR_1) /!< BaudRate control equal to fPCLK/128 /
<>	161:2cc1468da177	207	#define LL_SPI_BAUDRATEPRESCALER_DIV256 (SPI_CR1_BR_2 \| SPI_CR1_BR_1 \| SPI_CR1_BR_0) /!< BaudRate control equal to fPCLK/256 /
<>	161:2cc1468da177	208	/**
<>	161:2cc1468da177	209	* @}
<>	161:2cc1468da177	210	*/
<>	161:2cc1468da177	211
<>	161:2cc1468da177	212	/** @defgroup SPI_LL_EC_BIT_ORDER Transmission Bit Order
<>	161:2cc1468da177	213	* @{
<>	161:2cc1468da177	214	*/
<>	161:2cc1468da177	215	#define LL_SPI_LSB_FIRST (SPI_CR1_LSBFIRST) /!< Data is transmitted/received with the LSB first /
<>	161:2cc1468da177	216	#define LL_SPI_MSB_FIRST 0x00000000U /!< Data is transmitted/received with the MSB first /
<>	161:2cc1468da177	217	/**
<>	161:2cc1468da177	218	* @}
<>	161:2cc1468da177	219	*/
<>	161:2cc1468da177	220
<>	161:2cc1468da177	221	/** @defgroup SPI_LL_EC_TRANSFER_MODE Transfer Mode
<>	161:2cc1468da177	222	* @{
<>	161:2cc1468da177	223	*/
<>	161:2cc1468da177	224	#define LL_SPI_FULL_DUPLEX 0x00000000U /!< Full-Duplex mode. Rx and Tx transfer on 2 lines /
<>	161:2cc1468da177	225	#define LL_SPI_SIMPLEX_RX (SPI_CR1_RXONLY) /!< Simplex Rx mode. Rx transfer only on 1 line /
<>	161:2cc1468da177	226	#define LL_SPI_HALF_DUPLEX_RX (SPI_CR1_BIDIMODE) /!< Half-Duplex Rx mode. Rx transfer on 1 line /
<>	161:2cc1468da177	227	#define LL_SPI_HALF_DUPLEX_TX (SPI_CR1_BIDIMODE \| SPI_CR1_BIDIOE) /!< Half-Duplex Tx mode. Tx transfer on 1 line /
<>	161:2cc1468da177	228	/**
<>	161:2cc1468da177	229	* @}
<>	161:2cc1468da177	230	*/
<>	161:2cc1468da177	231
<>	161:2cc1468da177	232	/** @defgroup SPI_LL_EC_NSS_MODE Slave Select Pin Mode
<>	161:2cc1468da177	233	* @{
<>	161:2cc1468da177	234	*/
<>	161:2cc1468da177	235	#define LL_SPI_NSS_SOFT (SPI_CR1_SSM) /!< NSS managed internally. NSS pin not used and free /
<>	161:2cc1468da177	236	#define LL_SPI_NSS_HARD_INPUT 0x00000000U /!< NSS pin used in Input. Only used in Master mode /
<>	161:2cc1468da177	237	#define LL_SPI_NSS_HARD_OUTPUT (((uint32_t)SPI_CR2_SSOE << 16U)) /!< NSS pin used in Output. Only used in Slave mode as chip select /
<>	161:2cc1468da177	238	/**
<>	161:2cc1468da177	239	* @}
<>	161:2cc1468da177	240	*/
<>	161:2cc1468da177	241
<>	161:2cc1468da177	242	/** @defgroup SPI_LL_EC_DATAWIDTH Datawidth
<>	161:2cc1468da177	243	* @{
<>	161:2cc1468da177	244	*/
<>	161:2cc1468da177	245	#define LL_SPI_DATAWIDTH_4BIT (SPI_CR2_DS_0 \| SPI_CR2_DS_1) /!< Data length for SPI transfer: 4 bits /
<>	161:2cc1468da177	246	#define LL_SPI_DATAWIDTH_5BIT (SPI_CR2_DS_2) /!< Data length for SPI transfer: 5 bits /
<>	161:2cc1468da177	247	#define LL_SPI_DATAWIDTH_6BIT (SPI_CR2_DS_2 \| SPI_CR2_DS_0) /!< Data length for SPI transfer: 6 bits /
<>	161:2cc1468da177	248	#define LL_SPI_DATAWIDTH_7BIT (SPI_CR2_DS_2 \| SPI_CR2_DS_1) /!< Data length for SPI transfer: 7 bits /
<>	161:2cc1468da177	249	#define LL_SPI_DATAWIDTH_8BIT (SPI_CR2_DS_2 \| SPI_CR2_DS_1 \| SPI_CR2_DS_0) /!< Data length for SPI transfer: 8 bits /
<>	161:2cc1468da177	250	#define LL_SPI_DATAWIDTH_9BIT (SPI_CR2_DS_3) /!< Data length for SPI transfer: 9 bits /
<>	161:2cc1468da177	251	#define LL_SPI_DATAWIDTH_10BIT (SPI_CR2_DS_3 \| SPI_CR2_DS_0) /!< Data length for SPI transfer: 10 bits /
<>	161:2cc1468da177	252	#define LL_SPI_DATAWIDTH_11BIT (SPI_CR2_DS_3 \| SPI_CR2_DS_1) /!< Data length for SPI transfer: 11 bits /
<>	161:2cc1468da177	253	#define LL_SPI_DATAWIDTH_12BIT (SPI_CR2_DS_3 \| SPI_CR2_DS_1 \| SPI_CR2_DS_0) /!< Data length for SPI transfer: 12 bits /
<>	161:2cc1468da177	254	#define LL_SPI_DATAWIDTH_13BIT (SPI_CR2_DS_3 \| SPI_CR2_DS_2) /!< Data length for SPI transfer: 13 bits /
<>	161:2cc1468da177	255	#define LL_SPI_DATAWIDTH_14BIT (SPI_CR2_DS_3 \| SPI_CR2_DS_2 \| SPI_CR2_DS_0) /!< Data length for SPI transfer: 14 bits /
<>	161:2cc1468da177	256	#define LL_SPI_DATAWIDTH_15BIT (SPI_CR2_DS_3 \| SPI_CR2_DS_2 \| SPI_CR2_DS_1) /!< Data length for SPI transfer: 15 bits /
<>	161:2cc1468da177	257	#define LL_SPI_DATAWIDTH_16BIT (SPI_CR2_DS_3 \| SPI_CR2_DS_2 \| SPI_CR2_DS_1 \| SPI_CR2_DS_0) /!< Data length for SPI transfer: 16 bits /
<>	161:2cc1468da177	258	/**
<>	161:2cc1468da177	259	* @}
<>	161:2cc1468da177	260	*/
<>	161:2cc1468da177	261	#if defined(USE_FULL_LL_DRIVER)
<>	161:2cc1468da177	262
<>	161:2cc1468da177	263	/** @defgroup SPI_LL_EC_CRC_CALCULATION CRC Calculation
<>	161:2cc1468da177	264	* @{
<>	161:2cc1468da177	265	*/
<>	161:2cc1468da177	266	#define LL_SPI_CRCCALCULATION_DISABLE 0x00000000U /!< CRC calculation disabled /
<>	161:2cc1468da177	267	#define LL_SPI_CRCCALCULATION_ENABLE (SPI_CR1_CRCEN) /!< CRC calculation enabled /
<>	161:2cc1468da177	268	/**
<>	161:2cc1468da177	269	* @}
<>	161:2cc1468da177	270	*/
<>	161:2cc1468da177	271	#endif /* USE_FULL_LL_DRIVER */
<>	161:2cc1468da177	272
<>	161:2cc1468da177	273	/** @defgroup SPI_LL_EC_CRC_LENGTH CRC Length
<>	161:2cc1468da177	274	* @{
<>	161:2cc1468da177	275	*/
<>	161:2cc1468da177	276	#define LL_SPI_CRC_8BIT 0x00000000U /!< 8-bit CRC length /
<>	161:2cc1468da177	277	#define LL_SPI_CRC_16BIT (SPI_CR1_CRCL) /!< 16-bit CRC length /
<>	161:2cc1468da177	278	/**
<>	161:2cc1468da177	279	* @}
<>	161:2cc1468da177	280	*/
<>	161:2cc1468da177	281
<>	161:2cc1468da177	282	/** @defgroup SPI_LL_EC_RX_FIFO_TH RX FIFO Threshold
<>	161:2cc1468da177	283	* @{
<>	161:2cc1468da177	284	*/
<>	161:2cc1468da177	285	#define LL_SPI_RX_FIFO_TH_HALF 0x00000000U /!< RXNE event is generated if FIFO level is greater than or equel to 1/2 (16-bit) /
<>	161:2cc1468da177	286	#define LL_SPI_RX_FIFO_TH_QUARTER (SPI_CR2_FRXTH) /!< RXNE event is generated if FIFO level is greater than or equel to 1/4 (8-bit) /
<>	161:2cc1468da177	287	/**
<>	161:2cc1468da177	288	* @}
<>	161:2cc1468da177	289	*/
<>	161:2cc1468da177	290
<>	161:2cc1468da177	291	/** @defgroup SPI_LL_EC_RX_FIFO RX FIFO Level
<>	161:2cc1468da177	292	* @{
<>	161:2cc1468da177	293	*/
<>	161:2cc1468da177	294	#define LL_SPI_RX_FIFO_EMPTY 0x00000000U /!< FIFO reception empty /
<>	161:2cc1468da177	295	#define LL_SPI_RX_FIFO_QUARTER_FULL (SPI_SR_FRLVL_0) /!< FIFO reception 1/4 /
<>	161:2cc1468da177	296	#define LL_SPI_RX_FIFO_HALF_FULL (SPI_SR_FRLVL_1) /!< FIFO reception 1/2 /
<>	161:2cc1468da177	297	#define LL_SPI_RX_FIFO_FULL (SPI_SR_FRLVL_1 \| SPI_SR_FRLVL_0) /!< FIFO reception full /
<>	161:2cc1468da177	298	/**
<>	161:2cc1468da177	299	* @}
<>	161:2cc1468da177	300	*/
<>	161:2cc1468da177	301
<>	161:2cc1468da177	302	/** @defgroup SPI_LL_EC_TX_FIFO TX FIFO Level
<>	161:2cc1468da177	303	* @{
<>	161:2cc1468da177	304	*/
<>	161:2cc1468da177	305	#define LL_SPI_TX_FIFO_EMPTY 0x00000000U /!< FIFO transmission empty /
<>	161:2cc1468da177	306	#define LL_SPI_TX_FIFO_QUARTER_FULL (SPI_SR_FTLVL_0) /!< FIFO transmission 1/4 /
<>	161:2cc1468da177	307	#define LL_SPI_TX_FIFO_HALF_FULL (SPI_SR_FTLVL_1) /!< FIFO transmission 1/2 /
<>	161:2cc1468da177	308	#define LL_SPI_TX_FIFO_FULL (SPI_SR_FTLVL_1 \| SPI_SR_FTLVL_0) /!< FIFO transmission full /
<>	161:2cc1468da177	309	/**
<>	161:2cc1468da177	310	* @}
<>	161:2cc1468da177	311	*/
<>	161:2cc1468da177	312
<>	161:2cc1468da177	313	/** @defgroup SPI_LL_EC_DMA_PARITY DMA Parity
<>	161:2cc1468da177	314	* @{
<>	161:2cc1468da177	315	*/
<>	161:2cc1468da177	316	#define LL_SPI_DMA_PARITY_EVEN 0x00000000U /!< Select DMA parity Even /
<>	161:2cc1468da177	317	#define LL_SPI_DMA_PARITY_ODD 0x00000001U /!< Select DMA parity Odd /
<>	161:2cc1468da177	318
<>	161:2cc1468da177	319	/**
<>	161:2cc1468da177	320	* @}
<>	161:2cc1468da177	321	*/
<>	161:2cc1468da177	322
<>	161:2cc1468da177	323	/**
<>	161:2cc1468da177	324	* @}
<>	161:2cc1468da177	325	*/
<>	161:2cc1468da177	326
<>	161:2cc1468da177	327	/* Exported macro ------------------------------------------------------------*/
<>	161:2cc1468da177	328	/** @defgroup SPI_LL_Exported_Macros SPI Exported Macros
<>	161:2cc1468da177	329	* @{
<>	161:2cc1468da177	330	*/
<>	161:2cc1468da177	331
<>	161:2cc1468da177	332	/** @defgroup SPI_LL_EM_WRITE_READ Common Write and read registers Macros
<>	161:2cc1468da177	333	* @{
<>	161:2cc1468da177	334	*/
<>	161:2cc1468da177	335
<>	161:2cc1468da177	336	/**
<>	161:2cc1468da177	337	* @brief Write a value in SPI register
<>	161:2cc1468da177	338	* @param __INSTANCE__ SPI Instance
<>	161:2cc1468da177	339	* @param __REG__ Register to be written
<>	161:2cc1468da177	340	* @param __VALUE__ Value to be written in the register
<>	161:2cc1468da177	341	* @retval None
<>	161:2cc1468da177	342	*/
<>	161:2cc1468da177	343	#define LL_SPI_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
<>	161:2cc1468da177	344
<>	161:2cc1468da177	345	/**
<>	161:2cc1468da177	346	* @brief Read a value in SPI register
<>	161:2cc1468da177	347	* @param __INSTANCE__ SPI Instance
<>	161:2cc1468da177	348	* @param __REG__ Register to be read
<>	161:2cc1468da177	349	* @retval Register value
<>	161:2cc1468da177	350	*/
<>	161:2cc1468da177	351	#define LL_SPI_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
<>	161:2cc1468da177	352	/**
<>	161:2cc1468da177	353	* @}
<>	161:2cc1468da177	354	*/
<>	161:2cc1468da177	355
<>	161:2cc1468da177	356	/**
<>	161:2cc1468da177	357	* @}
<>	161:2cc1468da177	358	*/
<>	161:2cc1468da177	359
<>	161:2cc1468da177	360	/* Exported functions --------------------------------------------------------*/
<>	161:2cc1468da177	361	/** @defgroup SPI_LL_Exported_Functions SPI Exported Functions
<>	161:2cc1468da177	362	* @{
<>	161:2cc1468da177	363	*/
<>	161:2cc1468da177	364
<>	161:2cc1468da177	365	/** @defgroup SPI_LL_EF_Configuration Configuration
<>	161:2cc1468da177	366	* @{
<>	161:2cc1468da177	367	*/
<>	161:2cc1468da177	368
<>	161:2cc1468da177	369	/**
<>	161:2cc1468da177	370	* @brief Enable SPI peripheral
<>	161:2cc1468da177	371	* @rmtoll CR1 SPE LL_SPI_Enable
<>	161:2cc1468da177	372	* @param SPIx SPI Instance
<>	161:2cc1468da177	373	* @retval None
<>	161:2cc1468da177	374	*/
<>	161:2cc1468da177	375	__STATIC_INLINE void LL_SPI_Enable(SPI_TypeDef *SPIx)
<>	161:2cc1468da177	376	{
<>	161:2cc1468da177	377	SET_BIT(SPIx->CR1, SPI_CR1_SPE);
<>	161:2cc1468da177	378	}
<>	161:2cc1468da177	379
<>	161:2cc1468da177	380	/**
<>	161:2cc1468da177	381	* @brief Disable SPI peripheral
<>	161:2cc1468da177	382	* @note When disabling the SPI, follow the procedure described in the Reference Manual.
<>	161:2cc1468da177	383	* @rmtoll CR1 SPE LL_SPI_Disable
<>	161:2cc1468da177	384	* @param SPIx SPI Instance
<>	161:2cc1468da177	385	* @retval None
<>	161:2cc1468da177	386	*/
<>	161:2cc1468da177	387	__STATIC_INLINE void LL_SPI_Disable(SPI_TypeDef *SPIx)
<>	161:2cc1468da177	388	{
<>	161:2cc1468da177	389	CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE);
<>	161:2cc1468da177	390	}
<>	161:2cc1468da177	391
<>	161:2cc1468da177	392	/**
<>	161:2cc1468da177	393	* @brief Check if SPI peripheral is enabled
<>	161:2cc1468da177	394	* @rmtoll CR1 SPE LL_SPI_IsEnabled
<>	161:2cc1468da177	395	* @param SPIx SPI Instance
<>	161:2cc1468da177	396	* @retval State of bit (1 or 0).
<>	161:2cc1468da177	397	*/
<>	161:2cc1468da177	398	__STATIC_INLINE uint32_t LL_SPI_IsEnabled(SPI_TypeDef *SPIx)
<>	161:2cc1468da177	399	{
<>	161:2cc1468da177	400	return (READ_BIT(SPIx->CR1, SPI_CR1_SPE) == (SPI_CR1_SPE));
<>	161:2cc1468da177	401	}
<>	161:2cc1468da177	402
<>	161:2cc1468da177	403	/**
<>	161:2cc1468da177	404	* @brief Set SPI operation mode to Master or Slave
<>	161:2cc1468da177	405	* @note This bit should not be changed when communication is ongoing.
<>	161:2cc1468da177	406	* @rmtoll CR1 MSTR LL_SPI_SetMode\n
<>	161:2cc1468da177	407	* CR1 SSI LL_SPI_SetMode
<>	161:2cc1468da177	408	* @param SPIx SPI Instance
<>	161:2cc1468da177	409	* @param Mode This parameter can be one of the following values:
<>	161:2cc1468da177	410	* @arg @ref LL_SPI_MODE_MASTER
<>	161:2cc1468da177	411	* @arg @ref LL_SPI_MODE_SLAVE
<>	161:2cc1468da177	412	* @retval None
<>	161:2cc1468da177	413	*/
<>	161:2cc1468da177	414	__STATIC_INLINE void LL_SPI_SetMode(SPI_TypeDef *SPIx, uint32_t Mode)
<>	161:2cc1468da177	415	{
<>	161:2cc1468da177	416	MODIFY_REG(SPIx->CR1, SPI_CR1_MSTR \| SPI_CR1_SSI, Mode);
<>	161:2cc1468da177	417	}
<>	161:2cc1468da177	418
<>	161:2cc1468da177	419	/**
<>	161:2cc1468da177	420	* @brief Get SPI operation mode (Master or Slave)
<>	161:2cc1468da177	421	* @rmtoll CR1 MSTR LL_SPI_GetMode\n
<>	161:2cc1468da177	422	* CR1 SSI LL_SPI_GetMode
<>	161:2cc1468da177	423	* @param SPIx SPI Instance
<>	161:2cc1468da177	424	* @retval Returned value can be one of the following values:
<>	161:2cc1468da177	425	* @arg @ref LL_SPI_MODE_MASTER
<>	161:2cc1468da177	426	* @arg @ref LL_SPI_MODE_SLAVE
<>	161:2cc1468da177	427	*/
<>	161:2cc1468da177	428	__STATIC_INLINE uint32_t LL_SPI_GetMode(SPI_TypeDef *SPIx)
<>	161:2cc1468da177	429	{
<>	161:2cc1468da177	430	return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_MSTR \| SPI_CR1_SSI));
<>	161:2cc1468da177	431	}
<>	161:2cc1468da177	432
<>	161:2cc1468da177	433	/**
<>	161:2cc1468da177	434	* @brief Set serial protocol used
<>	161:2cc1468da177	435	* @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
<>	161:2cc1468da177	436	* @rmtoll CR2 FRF LL_SPI_SetStandard
<>	161:2cc1468da177	437	* @param SPIx SPI Instance
<>	161:2cc1468da177	438	* @param Standard This parameter can be one of the following values:
<>	161:2cc1468da177	439	* @arg @ref LL_SPI_PROTOCOL_MOTOROLA
<>	161:2cc1468da177	440	* @arg @ref LL_SPI_PROTOCOL_TI
<>	161:2cc1468da177	441	* @retval None
<>	161:2cc1468da177	442	*/
<>	161:2cc1468da177	443	__STATIC_INLINE void LL_SPI_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard)
<>	161:2cc1468da177	444	{
<>	161:2cc1468da177	445	MODIFY_REG(SPIx->CR2, SPI_CR2_FRF, Standard);
<>	161:2cc1468da177	446	}
<>	161:2cc1468da177	447
<>	161:2cc1468da177	448	/**
<>	161:2cc1468da177	449	* @brief Get serial protocol used
<>	161:2cc1468da177	450	* @rmtoll CR2 FRF LL_SPI_GetStandard
<>	161:2cc1468da177	451	* @param SPIx SPI Instance
<>	161:2cc1468da177	452	* @retval Returned value can be one of the following values:
<>	161:2cc1468da177	453	* @arg @ref LL_SPI_PROTOCOL_MOTOROLA
<>	161:2cc1468da177	454	* @arg @ref LL_SPI_PROTOCOL_TI
<>	161:2cc1468da177	455	*/
<>	161:2cc1468da177	456	__STATIC_INLINE uint32_t LL_SPI_GetStandard(SPI_TypeDef *SPIx)
<>	161:2cc1468da177	457	{
<>	161:2cc1468da177	458	return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_FRF));
<>	161:2cc1468da177	459	}
<>	161:2cc1468da177	460
<>	161:2cc1468da177	461	/**
<>	161:2cc1468da177	462	* @brief Set clock phase
<>	161:2cc1468da177	463	* @note This bit should not be changed when communication is ongoing.
<>	161:2cc1468da177	464	* This bit is not used in SPI TI mode.
<>	161:2cc1468da177	465	* @rmtoll CR1 CPHA LL_SPI_SetClockPhase
<>	161:2cc1468da177	466	* @param SPIx SPI Instance
<>	161:2cc1468da177	467	* @param ClockPhase This parameter can be one of the following values:
<>	161:2cc1468da177	468	* @arg @ref LL_SPI_PHASE_1EDGE
<>	161:2cc1468da177	469	* @arg @ref LL_SPI_PHASE_2EDGE
<>	161:2cc1468da177	470	* @retval None
<>	161:2cc1468da177	471	*/
<>	161:2cc1468da177	472	__STATIC_INLINE void LL_SPI_SetClockPhase(SPI_TypeDef *SPIx, uint32_t ClockPhase)
<>	161:2cc1468da177	473	{
<>	161:2cc1468da177	474	MODIFY_REG(SPIx->CR1, SPI_CR1_CPHA, ClockPhase);
<>	161:2cc1468da177	475	}
<>	161:2cc1468da177	476
<>	161:2cc1468da177	477	/**
<>	161:2cc1468da177	478	* @brief Get clock phase
<>	161:2cc1468da177	479	* @rmtoll CR1 CPHA LL_SPI_GetClockPhase
<>	161:2cc1468da177	480	* @param SPIx SPI Instance
<>	161:2cc1468da177	481	* @retval Returned value can be one of the following values:
<>	161:2cc1468da177	482	* @arg @ref LL_SPI_PHASE_1EDGE
<>	161:2cc1468da177	483	* @arg @ref LL_SPI_PHASE_2EDGE
<>	161:2cc1468da177	484	*/
<>	161:2cc1468da177	485	__STATIC_INLINE uint32_t LL_SPI_GetClockPhase(SPI_TypeDef *SPIx)
<>	161:2cc1468da177	486	{
<>	161:2cc1468da177	487	return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPHA));
<>	161:2cc1468da177	488	}
<>	161:2cc1468da177	489
<>	161:2cc1468da177	490	/**
<>	161:2cc1468da177	491	* @brief Set clock polarity
<>	161:2cc1468da177	492	* @note This bit should not be changed when communication is ongoing.
<>	161:2cc1468da177	493	* This bit is not used in SPI TI mode.
<>	161:2cc1468da177	494	* @rmtoll CR1 CPOL LL_SPI_SetClockPolarity
<>	161:2cc1468da177	495	* @param SPIx SPI Instance
<>	161:2cc1468da177	496	* @param ClockPolarity This parameter can be one of the following values:
<>	161:2cc1468da177	497	* @arg @ref LL_SPI_POLARITY_LOW
<>	161:2cc1468da177	498	* @arg @ref LL_SPI_POLARITY_HIGH
<>	161:2cc1468da177	499	* @retval None
<>	161:2cc1468da177	500	*/
<>	161:2cc1468da177	501	__STATIC_INLINE void LL_SPI_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPolarity)
<>	161:2cc1468da177	502	{
<>	161:2cc1468da177	503	MODIFY_REG(SPIx->CR1, SPI_CR1_CPOL, ClockPolarity);
<>	161:2cc1468da177	504	}
<>	161:2cc1468da177	505
<>	161:2cc1468da177	506	/**
<>	161:2cc1468da177	507	* @brief Get clock polarity
<>	161:2cc1468da177	508	* @rmtoll CR1 CPOL LL_SPI_GetClockPolarity
<>	161:2cc1468da177	509	* @param SPIx SPI Instance
<>	161:2cc1468da177	510	* @retval Returned value can be one of the following values:
<>	161:2cc1468da177	511	* @arg @ref LL_SPI_POLARITY_LOW
<>	161:2cc1468da177	512	* @arg @ref LL_SPI_POLARITY_HIGH
<>	161:2cc1468da177	513	*/
<>	161:2cc1468da177	514	__STATIC_INLINE uint32_t LL_SPI_GetClockPolarity(SPI_TypeDef *SPIx)
<>	161:2cc1468da177	515	{
<>	161:2cc1468da177	516	return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPOL));
<>	161:2cc1468da177	517	}
<>	161:2cc1468da177	518
<>	161:2cc1468da177	519	/**
<>	161:2cc1468da177	520	* @brief Set baud rate prescaler
<>	161:2cc1468da177	521	* @note These bits should not be changed when communication is ongoing. SPI BaudRate = fPCLK/Prescaler.
<>	161:2cc1468da177	522	* @rmtoll CR1 BR LL_SPI_SetBaudRatePrescaler
<>	161:2cc1468da177	523	* @param SPIx SPI Instance
<>	161:2cc1468da177	524	* @param BaudRate This parameter can be one of the following values:
<>	161:2cc1468da177	525	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2
<>	161:2cc1468da177	526	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4
<>	161:2cc1468da177	527	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8
<>	161:2cc1468da177	528	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16
<>	161:2cc1468da177	529	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32
<>	161:2cc1468da177	530	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64
<>	161:2cc1468da177	531	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128
<>	161:2cc1468da177	532	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256
<>	161:2cc1468da177	533	* @retval None
<>	161:2cc1468da177	534	*/
<>	161:2cc1468da177	535	__STATIC_INLINE void LL_SPI_SetBaudRatePrescaler(SPI_TypeDef *SPIx, uint32_t BaudRate)
<>	161:2cc1468da177	536	{
<>	161:2cc1468da177	537	MODIFY_REG(SPIx->CR1, SPI_CR1_BR, BaudRate);
<>	161:2cc1468da177	538	}
<>	161:2cc1468da177	539
<>	161:2cc1468da177	540	/**
<>	161:2cc1468da177	541	* @brief Get baud rate prescaler
<>	161:2cc1468da177	542	* @rmtoll CR1 BR LL_SPI_GetBaudRatePrescaler
<>	161:2cc1468da177	543	* @param SPIx SPI Instance
<>	161:2cc1468da177	544	* @retval Returned value can be one of the following values:
<>	161:2cc1468da177	545	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2
<>	161:2cc1468da177	546	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4
<>	161:2cc1468da177	547	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8
<>	161:2cc1468da177	548	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16
<>	161:2cc1468da177	549	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32
<>	161:2cc1468da177	550	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64
<>	161:2cc1468da177	551	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128
<>	161:2cc1468da177	552	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256
<>	161:2cc1468da177	553	*/
<>	161:2cc1468da177	554	__STATIC_INLINE uint32_t LL_SPI_GetBaudRatePrescaler(SPI_TypeDef *SPIx)
<>	161:2cc1468da177	555	{
<>	161:2cc1468da177	556	return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_BR));
<>	161:2cc1468da177	557	}
<>	161:2cc1468da177	558
<>	161:2cc1468da177	559	/**
<>	161:2cc1468da177	560	* @brief Set transfer bit order
<>	161:2cc1468da177	561	* @note This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode.
<>	161:2cc1468da177	562	* @rmtoll CR1 LSBFIRST LL_SPI_SetTransferBitOrder
<>	161:2cc1468da177	563	* @param SPIx SPI Instance
<>	161:2cc1468da177	564	* @param BitOrder This parameter can be one of the following values:
<>	161:2cc1468da177	565	* @arg @ref LL_SPI_LSB_FIRST
<>	161:2cc1468da177	566	* @arg @ref LL_SPI_MSB_FIRST
<>	161:2cc1468da177	567	* @retval None
<>	161:2cc1468da177	568	*/
<>	161:2cc1468da177	569	__STATIC_INLINE void LL_SPI_SetTransferBitOrder(SPI_TypeDef *SPIx, uint32_t BitOrder)
<>	161:2cc1468da177	570	{
<>	161:2cc1468da177	571	MODIFY_REG(SPIx->CR1, SPI_CR1_LSBFIRST, BitOrder);
<>	161:2cc1468da177	572	}
<>	161:2cc1468da177	573
<>	161:2cc1468da177	574	/**
<>	161:2cc1468da177	575	* @brief Get transfer bit order
<>	161:2cc1468da177	576	* @rmtoll CR1 LSBFIRST LL_SPI_GetTransferBitOrder
<>	161:2cc1468da177	577	* @param SPIx SPI Instance
<>	161:2cc1468da177	578	* @retval Returned value can be one of the following values:
<>	161:2cc1468da177	579	* @arg @ref LL_SPI_LSB_FIRST
<>	161:2cc1468da177	580	* @arg @ref LL_SPI_MSB_FIRST
<>	161:2cc1468da177	581	*/
<>	161:2cc1468da177	582	__STATIC_INLINE uint32_t LL_SPI_GetTransferBitOrder(SPI_TypeDef *SPIx)
<>	161:2cc1468da177	583	{
<>	161:2cc1468da177	584	return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_LSBFIRST));
<>	161:2cc1468da177	585	}
<>	161:2cc1468da177	586
<>	161:2cc1468da177	587	/**
<>	161:2cc1468da177	588	* @brief Set transfer direction mode
<>	161:2cc1468da177	589	* @note For Half-Duplex mode, Rx Direction is set by default.
<>	161:2cc1468da177	590	* In master mode, the MOSI pin is used and in slave mode, the MISO pin is used for Half-Duplex.
<>	161:2cc1468da177	591	* @rmtoll CR1 RXONLY LL_SPI_SetTransferDirection\n
<>	161:2cc1468da177	592	* CR1 BIDIMODE LL_SPI_SetTransferDirection\n
<>	161:2cc1468da177	593	* CR1 BIDIOE LL_SPI_SetTransferDirection
<>	161:2cc1468da177	594	* @param SPIx SPI Instance
<>	161:2cc1468da177	595	* @param TransferDirection This parameter can be one of the following values:
<>	161:2cc1468da177	596	* @arg @ref LL_SPI_FULL_DUPLEX
<>	161:2cc1468da177	597	* @arg @ref LL_SPI_SIMPLEX_RX
<>	161:2cc1468da177	598	* @arg @ref LL_SPI_HALF_DUPLEX_RX
<>	161:2cc1468da177	599	* @arg @ref LL_SPI_HALF_DUPLEX_TX
<>	161:2cc1468da177	600	* @retval None
<>	161:2cc1468da177	601	*/
<>	161:2cc1468da177	602	__STATIC_INLINE void LL_SPI_SetTransferDirection(SPI_TypeDef *SPIx, uint32_t TransferDirection)
<>	161:2cc1468da177	603	{
<>	161:2cc1468da177	604	MODIFY_REG(SPIx->CR1, SPI_CR1_RXONLY \| SPI_CR1_BIDIMODE \| SPI_CR1_BIDIOE, TransferDirection);
<>	161:2cc1468da177	605	}
<>	161:2cc1468da177	606
<>	161:2cc1468da177	607	/**
<>	161:2cc1468da177	608	* @brief Get transfer direction mode
<>	161:2cc1468da177	609	* @rmtoll CR1 RXONLY LL_SPI_GetTransferDirection\n
<>	161:2cc1468da177	610	* CR1 BIDIMODE LL_SPI_GetTransferDirection\n
<>	161:2cc1468da177	611	* CR1 BIDIOE LL_SPI_GetTransferDirection
<>	161:2cc1468da177	612	* @param SPIx SPI Instance
<>	161:2cc1468da177	613	* @retval Returned value can be one of the following values:
<>	161:2cc1468da177	614	* @arg @ref LL_SPI_FULL_DUPLEX
<>	161:2cc1468da177	615	* @arg @ref LL_SPI_SIMPLEX_RX
<>	161:2cc1468da177	616	* @arg @ref LL_SPI_HALF_DUPLEX_RX
<>	161:2cc1468da177	617	* @arg @ref LL_SPI_HALF_DUPLEX_TX
<>	161:2cc1468da177	618	*/
<>	161:2cc1468da177	619	__STATIC_INLINE uint32_t LL_SPI_GetTransferDirection(SPI_TypeDef *SPIx)
<>	161:2cc1468da177	620	{
<>	161:2cc1468da177	621	return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_RXONLY \| SPI_CR1_BIDIMODE \| SPI_CR1_BIDIOE));
<>	161:2cc1468da177	622	}
<>	161:2cc1468da177	623
<>	161:2cc1468da177	624	/**
<>	161:2cc1468da177	625	* @brief Set frame data width
<>	161:2cc1468da177	626	* @rmtoll CR2 DS LL_SPI_SetDataWidth
<>	161:2cc1468da177	627	* @param SPIx SPI Instance
<>	161:2cc1468da177	628	* @param DataWidth This parameter can be one of the following values:
<>	161:2cc1468da177	629	* @arg @ref LL_SPI_DATAWIDTH_4BIT
<>	161:2cc1468da177	630	* @arg @ref LL_SPI_DATAWIDTH_5BIT
<>	161:2cc1468da177	631	* @arg @ref LL_SPI_DATAWIDTH_6BIT
<>	161:2cc1468da177	632	* @arg @ref LL_SPI_DATAWIDTH_7BIT
<>	161:2cc1468da177	633	* @arg @ref LL_SPI_DATAWIDTH_8BIT
<>	161:2cc1468da177	634	* @arg @ref LL_SPI_DATAWIDTH_9BIT
<>	161:2cc1468da177	635	* @arg @ref LL_SPI_DATAWIDTH_10BIT
<>	161:2cc1468da177	636	* @arg @ref LL_SPI_DATAWIDTH_11BIT
<>	161:2cc1468da177	637	* @arg @ref LL_SPI_DATAWIDTH_12BIT
<>	161:2cc1468da177	638	* @arg @ref LL_SPI_DATAWIDTH_13BIT
<>	161:2cc1468da177	639	* @arg @ref LL_SPI_DATAWIDTH_14BIT
<>	161:2cc1468da177	640	* @arg @ref LL_SPI_DATAWIDTH_15BIT
<>	161:2cc1468da177	641	* @arg @ref LL_SPI_DATAWIDTH_16BIT
<>	161:2cc1468da177	642	* @retval None
<>	161:2cc1468da177	643	*/
<>	161:2cc1468da177	644	__STATIC_INLINE void LL_SPI_SetDataWidth(SPI_TypeDef *SPIx, uint32_t DataWidth)
<>	161:2cc1468da177	645	{
<>	161:2cc1468da177	646	MODIFY_REG(SPIx->CR2, SPI_CR2_DS, DataWidth);
<>	161:2cc1468da177	647	}
<>	161:2cc1468da177	648
<>	161:2cc1468da177	649	/**
<>	161:2cc1468da177	650	* @brief Get frame data width
<>	161:2cc1468da177	651	* @rmtoll CR2 DS LL_SPI_GetDataWidth
<>	161:2cc1468da177	652	* @param SPIx SPI Instance
<>	161:2cc1468da177	653	* @retval Returned value can be one of the following values:
<>	161:2cc1468da177	654	* @arg @ref LL_SPI_DATAWIDTH_4BIT
<>	161:2cc1468da177	655	* @arg @ref LL_SPI_DATAWIDTH_5BIT
<>	161:2cc1468da177	656	* @arg @ref LL_SPI_DATAWIDTH_6BIT
<>	161:2cc1468da177	657	* @arg @ref LL_SPI_DATAWIDTH_7BIT
<>	161:2cc1468da177	658	* @arg @ref LL_SPI_DATAWIDTH_8BIT
<>	161:2cc1468da177	659	* @arg @ref LL_SPI_DATAWIDTH_9BIT
<>	161:2cc1468da177	660	* @arg @ref LL_SPI_DATAWIDTH_10BIT
<>	161:2cc1468da177	661	* @arg @ref LL_SPI_DATAWIDTH_11BIT
<>	161:2cc1468da177	662	* @arg @ref LL_SPI_DATAWIDTH_12BIT
<>	161:2cc1468da177	663	* @arg @ref LL_SPI_DATAWIDTH_13BIT
<>	161:2cc1468da177	664	* @arg @ref LL_SPI_DATAWIDTH_14BIT
<>	161:2cc1468da177	665	* @arg @ref LL_SPI_DATAWIDTH_15BIT
<>	161:2cc1468da177	666	* @arg @ref LL_SPI_DATAWIDTH_16BIT
<>	161:2cc1468da177	667	*/
<>	161:2cc1468da177	668	__STATIC_INLINE uint32_t LL_SPI_GetDataWidth(SPI_TypeDef *SPIx)
<>	161:2cc1468da177	669	{
<>	161:2cc1468da177	670	return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_DS));
<>	161:2cc1468da177	671	}
<>	161:2cc1468da177	672
<>	161:2cc1468da177	673	/**
<>	161:2cc1468da177	674	* @brief Set threshold of RXFIFO that triggers an RXNE event
<>	161:2cc1468da177	675	* @rmtoll CR2 FRXTH LL_SPI_SetRxFIFOThreshold
<>	161:2cc1468da177	676	* @param SPIx SPI Instance
<>	161:2cc1468da177	677	* @param Threshold This parameter can be one of the following values:
<>	161:2cc1468da177	678	* @arg @ref LL_SPI_RX_FIFO_TH_HALF
<>	161:2cc1468da177	679	* @arg @ref LL_SPI_RX_FIFO_TH_QUARTER
<>	161:2cc1468da177	680	* @retval None
<>	161:2cc1468da177	681	*/
<>	161:2cc1468da177	682	__STATIC_INLINE void LL_SPI_SetRxFIFOThreshold(SPI_TypeDef *SPIx, uint32_t Threshold)
<>	161:2cc1468da177	683	{
<>	161:2cc1468da177	684	MODIFY_REG(SPIx->CR2, SPI_CR2_FRXTH, Threshold);
<>	161:2cc1468da177	685	}
<>	161:2cc1468da177	686
<>	161:2cc1468da177	687	/**
<>	161:2cc1468da177	688	* @brief Get threshold of RXFIFO that triggers an RXNE event
<>	161:2cc1468da177	689	* @rmtoll CR2 FRXTH LL_SPI_GetRxFIFOThreshold
<>	161:2cc1468da177	690	* @param SPIx SPI Instance
<>	161:2cc1468da177	691	* @retval Returned value can be one of the following values:
<>	161:2cc1468da177	692	* @arg @ref LL_SPI_RX_FIFO_TH_HALF
<>	161:2cc1468da177	693	* @arg @ref LL_SPI_RX_FIFO_TH_QUARTER
<>	161:2cc1468da177	694	*/
<>	161:2cc1468da177	695	__STATIC_INLINE uint32_t LL_SPI_GetRxFIFOThreshold(SPI_TypeDef *SPIx)
<>	161:2cc1468da177	696	{
<>	161:2cc1468da177	697	return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_FRXTH));
<>	161:2cc1468da177	698	}
<>	161:2cc1468da177	699
<>	161:2cc1468da177	700	/**
<>	161:2cc1468da177	701	* @}
<>	161:2cc1468da177	702	*/
<>	161:2cc1468da177	703
<>	161:2cc1468da177	704	/** @defgroup SPI_LL_EF_CRC_Management CRC Management
<>	161:2cc1468da177	705	* @{
<>	161:2cc1468da177	706	*/
<>	161:2cc1468da177	707
<>	161:2cc1468da177	708	/**
<>	161:2cc1468da177	709	* @brief Enable CRC
<>	161:2cc1468da177	710	* @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
<>	161:2cc1468da177	711	* @rmtoll CR1 CRCEN LL_SPI_EnableCRC
<>	161:2cc1468da177	712	* @param SPIx SPI Instance
<>	161:2cc1468da177	713	* @retval None
<>	161:2cc1468da177	714	*/
<>	161:2cc1468da177	715	__STATIC_INLINE void LL_SPI_EnableCRC(SPI_TypeDef *SPIx)
<>	161:2cc1468da177	716	{
<>	161:2cc1468da177	717	SET_BIT(SPIx->CR1, SPI_CR1_CRCEN);
<>	161:2cc1468da177	718	}
<>	161:2cc1468da177	719
<>	161:2cc1468da177	720	/**
<>	161:2cc1468da177	721	* @brief Disable CRC
<>	161:2cc1468da177	722	* @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
<>	161:2cc1468da177	723	* @rmtoll CR1 CRCEN LL_SPI_DisableCRC
<>	161:2cc1468da177	724	* @param SPIx SPI Instance
<>	161:2cc1468da177	725	* @retval None
<>	161:2cc1468da177	726	*/
<>	161:2cc1468da177	727	__STATIC_INLINE void LL_SPI_DisableCRC(SPI_TypeDef *SPIx)
<>	161:2cc1468da177	728	{
<>	161:2cc1468da177	729	CLEAR_BIT(SPIx->CR1, SPI_CR1_CRCEN);
<>	161:2cc1468da177	730	}
<>	161:2cc1468da177	731
<>	161:2cc1468da177	732	/**
<>	161:2cc1468da177	733	* @brief Check if CRC is enabled
<>	161:2cc1468da177	734	* @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
<>	161:2cc1468da177	735	* @rmtoll CR1 CRCEN LL_SPI_IsEnabledCRC
<>	161:2cc1468da177	736	* @param SPIx SPI Instance
<>	161:2cc1468da177	737	* @retval State of bit (1 or 0).
<>	161:2cc1468da177	738	*/
<>	161:2cc1468da177	739	__STATIC_INLINE uint32_t LL_SPI_IsEnabledCRC(SPI_TypeDef *SPIx)
<>	161:2cc1468da177	740	{
<>	161:2cc1468da177	741	return (READ_BIT(SPIx->CR1, SPI_CR1_CRCEN) == (SPI_CR1_CRCEN));
<>	161:2cc1468da177	742	}
<>	161:2cc1468da177	743
<>	161:2cc1468da177	744	/**
<>	161:2cc1468da177	745	* @brief Set CRC Length
<>	161:2cc1468da177	746	* @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
<>	161:2cc1468da177	747	* @rmtoll CR1 CRCL LL_SPI_SetCRCWidth
<>	161:2cc1468da177	748	* @param SPIx SPI Instance
<>	161:2cc1468da177	749	* @param CRCLength This parameter can be one of the following values:
<>	161:2cc1468da177	750	* @arg @ref LL_SPI_CRC_8BIT
<>	161:2cc1468da177	751	* @arg @ref LL_SPI_CRC_16BIT
<>	161:2cc1468da177	752	* @retval None
<>	161:2cc1468da177	753	*/
<>	161:2cc1468da177	754	__STATIC_INLINE void LL_SPI_SetCRCWidth(SPI_TypeDef *SPIx, uint32_t CRCLength)
<>	161:2cc1468da177	755	{
<>	161:2cc1468da177	756	MODIFY_REG(SPIx->CR1, SPI_CR1_CRCL, CRCLength);
<>	161:2cc1468da177	757	}
<>	161:2cc1468da177	758
<>	161:2cc1468da177	759	/**
<>	161:2cc1468da177	760	* @brief Get CRC Length
<>	161:2cc1468da177	761	* @rmtoll CR1 CRCL LL_SPI_GetCRCWidth
<>	161:2cc1468da177	762	* @param SPIx SPI Instance
<>	161:2cc1468da177	763	* @retval Returned value can be one of the following values:
<>	161:2cc1468da177	764	* @arg @ref LL_SPI_CRC_8BIT
<>	161:2cc1468da177	765	* @arg @ref LL_SPI_CRC_16BIT
<>	161:2cc1468da177	766	*/
<>	161:2cc1468da177	767	__STATIC_INLINE uint32_t LL_SPI_GetCRCWidth(SPI_TypeDef *SPIx)
<>	161:2cc1468da177	768	{
<>	161:2cc1468da177	769	return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CRCL));
<>	161:2cc1468da177	770	}
<>	161:2cc1468da177	771
<>	161:2cc1468da177	772	/**
<>	161:2cc1468da177	773	* @brief Set CRCNext to transfer CRC on the line
<>	161:2cc1468da177	774	* @note This bit has to be written as soon as the last data is written in the SPIx_DR register.
<>	161:2cc1468da177	775	* @rmtoll CR1 CRCNEXT LL_SPI_SetCRCNext
<>	161:2cc1468da177	776	* @param SPIx SPI Instance
<>	161:2cc1468da177	777	* @retval None
<>	161:2cc1468da177	778	*/
<>	161:2cc1468da177	779	__STATIC_INLINE void LL_SPI_SetCRCNext(SPI_TypeDef *SPIx)
<>	161:2cc1468da177	780	{
<>	161:2cc1468da177	781	SET_BIT(SPIx->CR1, SPI_CR1_CRCNEXT);
<>	161:2cc1468da177	782	}
<>	161:2cc1468da177	783
<>	161:2cc1468da177	784	/**
<>	161:2cc1468da177	785	* @brief Set polynomial for CRC calculation
<>	161:2cc1468da177	786	* @rmtoll CRCPR CRCPOLY LL_SPI_SetCRCPolynomial
<>	161:2cc1468da177	787	* @param SPIx SPI Instance
<>	161:2cc1468da177	788	* @param CRCPoly This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFF
<>	161:2cc1468da177	789	* @retval None
<>	161:2cc1468da177	790	*/
<>	161:2cc1468da177	791	__STATIC_INLINE void LL_SPI_SetCRCPolynomial(SPI_TypeDef *SPIx, uint32_t CRCPoly)
<>	161:2cc1468da177	792	{
<>	161:2cc1468da177	793	WRITE_REG(SPIx->CRCPR, (uint16_t)CRCPoly);
<>	161:2cc1468da177	794	}
<>	161:2cc1468da177	795
<>	161:2cc1468da177	796	/**
<>	161:2cc1468da177	797	* @brief Get polynomial for CRC calculation
<>	161:2cc1468da177	798	* @rmtoll CRCPR CRCPOLY LL_SPI_GetCRCPolynomial
<>	161:2cc1468da177	799	* @param SPIx SPI Instance
<>	161:2cc1468da177	800	* @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
<>	161:2cc1468da177	801	*/
<>	161:2cc1468da177	802	__STATIC_INLINE uint32_t LL_SPI_GetCRCPolynomial(SPI_TypeDef *SPIx)
<>	161:2cc1468da177	803	{
<>	161:2cc1468da177	804	return (uint32_t)(READ_REG(SPIx->CRCPR));
<>	161:2cc1468da177	805	}
<>	161:2cc1468da177	806
<>	161:2cc1468da177	807	/**
<>	161:2cc1468da177	808	* @brief Get Rx CRC
<>	161:2cc1468da177	809	* @rmtoll RXCRCR RXCRC LL_SPI_GetRxCRC
<>	161:2cc1468da177	810	* @param SPIx SPI Instance
<>	161:2cc1468da177	811	* @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
<>	161:2cc1468da177	812	*/
<>	161:2cc1468da177	813	__STATIC_INLINE uint32_t LL_SPI_GetRxCRC(SPI_TypeDef *SPIx)
<>	161:2cc1468da177	814	{
<>	161:2cc1468da177	815	return (uint32_t)(READ_REG(SPIx->RXCRCR));
<>	161:2cc1468da177	816	}
<>	161:2cc1468da177	817
<>	161:2cc1468da177	818	/**
<>	161:2cc1468da177	819	* @brief Get Tx CRC
<>	161:2cc1468da177	820	* @rmtoll TXCRCR TXCRC LL_SPI_GetTxCRC
<>	161:2cc1468da177	821	* @param SPIx SPI Instance
<>	161:2cc1468da177	822	* @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
<>	161:2cc1468da177	823	*/
<>	161:2cc1468da177	824	__STATIC_INLINE uint32_t LL_SPI_GetTxCRC(SPI_TypeDef *SPIx)
<>	161:2cc1468da177	825	{
<>	161:2cc1468da177	826	return (uint32_t)(READ_REG(SPIx->TXCRCR));
<>	161:2cc1468da177	827	}
<>	161:2cc1468da177	828
<>	161:2cc1468da177	829	/**
<>	161:2cc1468da177	830	* @}
<>	161:2cc1468da177	831	*/
<>	161:2cc1468da177	832
<>	161:2cc1468da177	833	/** @defgroup SPI_LL_EF_NSS_Management Slave Select Pin Management
<>	161:2cc1468da177	834	* @{
<>	161:2cc1468da177	835	*/
<>	161:2cc1468da177	836
<>	161:2cc1468da177	837	/**
<>	161:2cc1468da177	838	* @brief Set NSS mode
<>	161:2cc1468da177	839	* @note LL_SPI_NSS_SOFT Mode is not used in SPI TI mode.
<>	161:2cc1468da177	840	* @rmtoll CR1 SSM LL_SPI_SetNSSMode\n
<>	161:2cc1468da177	841	* @rmtoll CR2 SSOE LL_SPI_SetNSSMode
<>	161:2cc1468da177	842	* @param SPIx SPI Instance
<>	161:2cc1468da177	843	* @param NSS This parameter can be one of the following values:
<>	161:2cc1468da177	844	* @arg @ref LL_SPI_NSS_SOFT
<>	161:2cc1468da177	845	* @arg @ref LL_SPI_NSS_HARD_INPUT
<>	161:2cc1468da177	846	* @arg @ref LL_SPI_NSS_HARD_OUTPUT
<>	161:2cc1468da177	847	* @retval None
<>	161:2cc1468da177	848	*/
<>	161:2cc1468da177	849	__STATIC_INLINE void LL_SPI_SetNSSMode(SPI_TypeDef *SPIx, uint32_t NSS)
<>	161:2cc1468da177	850	{
<>	161:2cc1468da177	851	MODIFY_REG(SPIx->CR1, SPI_CR1_SSM, NSS);
<>	161:2cc1468da177	852	MODIFY_REG(SPIx->CR2, SPI_CR2_SSOE, ((uint32_t)(NSS >> 16U)));
<>	161:2cc1468da177	853	}
<>	161:2cc1468da177	854
<>	161:2cc1468da177	855	/**
<>	161:2cc1468da177	856	* @brief Get NSS mode
<>	161:2cc1468da177	857	* @rmtoll CR1 SSM LL_SPI_GetNSSMode\n
<>	161:2cc1468da177	858	* @rmtoll CR2 SSOE LL_SPI_GetNSSMode
<>	161:2cc1468da177	859	* @param SPIx SPI Instance
<>	161:2cc1468da177	860	* @retval Returned value can be one of the following values:
<>	161:2cc1468da177	861	* @arg @ref LL_SPI_NSS_SOFT
<>	161:2cc1468da177	862	* @arg @ref LL_SPI_NSS_HARD_INPUT
<>	161:2cc1468da177	863	* @arg @ref LL_SPI_NSS_HARD_OUTPUT
<>	161:2cc1468da177	864	*/
<>	161:2cc1468da177	865	__STATIC_INLINE uint32_t LL_SPI_GetNSSMode(SPI_TypeDef *SPIx)
<>	161:2cc1468da177	866	{
<>	161:2cc1468da177	867	register uint32_t Ssm = (READ_BIT(SPIx->CR1, SPI_CR1_SSM));
<>	161:2cc1468da177	868	register uint32_t Ssoe = (READ_BIT(SPIx->CR2, SPI_CR2_SSOE) << 16U);
<>	161:2cc1468da177	869	return (Ssm \| Ssoe);
<>	161:2cc1468da177	870	}
<>	161:2cc1468da177	871
<>	161:2cc1468da177	872	/**
<>	161:2cc1468da177	873	* @brief Enable NSS pulse management
<>	161:2cc1468da177	874	* @note This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode.
<>	161:2cc1468da177	875	* @rmtoll CR2 NSSP LL_SPI_EnableNSSPulseMgt
<>	161:2cc1468da177	876	* @param SPIx SPI Instance
<>	161:2cc1468da177	877	* @retval None
<>	161:2cc1468da177	878	*/
<>	161:2cc1468da177	879	__STATIC_INLINE void LL_SPI_EnableNSSPulseMgt(SPI_TypeDef *SPIx)
<>	161:2cc1468da177	880	{
<>	161:2cc1468da177	881	SET_BIT(SPIx->CR2, SPI_CR2_NSSP);
<>	161:2cc1468da177	882	}
<>	161:2cc1468da177	883
<>	161:2cc1468da177	884	/**
<>	161:2cc1468da177	885	* @brief Disable NSS pulse management
<>	161:2cc1468da177	886	* @note This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode.
<>	161:2cc1468da177	887	* @rmtoll CR2 NSSP LL_SPI_DisableNSSPulseMgt
<>	161:2cc1468da177	888	* @param SPIx SPI Instance
<>	161:2cc1468da177	889	* @retval None
<>	161:2cc1468da177	890	*/
<>	161:2cc1468da177	891	__STATIC_INLINE void LL_SPI_DisableNSSPulseMgt(SPI_TypeDef *SPIx)
<>	161:2cc1468da177	892	{
<>	161:2cc1468da177	893	CLEAR_BIT(SPIx->CR2, SPI_CR2_NSSP);
<>	161:2cc1468da177	894	}
<>	161:2cc1468da177	895
<>	161:2cc1468da177	896	/**
<>	161:2cc1468da177	897	* @brief Check if NSS pulse is enabled
<>	161:2cc1468da177	898	* @note This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode.
<>	161:2cc1468da177	899	* @rmtoll CR2 NSSP LL_SPI_IsEnabledNSSPulse
<>	161:2cc1468da177	900	* @param SPIx SPI Instance
<>	161:2cc1468da177	901	* @retval State of bit (1 or 0).
<>	161:2cc1468da177	902	*/
<>	161:2cc1468da177	903	__STATIC_INLINE uint32_t LL_SPI_IsEnabledNSSPulse(SPI_TypeDef *SPIx)
<>	161:2cc1468da177	904	{
<>	161:2cc1468da177	905	return (READ_BIT(SPIx->CR2, SPI_CR2_NSSP) == (SPI_CR2_NSSP));
<>	161:2cc1468da177	906	}
<>	161:2cc1468da177	907
<>	161:2cc1468da177	908	/**
<>	161:2cc1468da177	909	* @}
<>	161:2cc1468da177	910	*/
<>	161:2cc1468da177	911
<>	161:2cc1468da177	912	/** @defgroup SPI_LL_EF_FLAG_Management FLAG Management
<>	161:2cc1468da177	913	* @{
<>	161:2cc1468da177	914	*/
<>	161:2cc1468da177	915
<>	161:2cc1468da177	916	/**
<>	161:2cc1468da177	917	* @brief Check if Rx buffer is not empty
<>	161:2cc1468da177	918	* @rmtoll SR RXNE LL_SPI_IsActiveFlag_RXNE
<>	161:2cc1468da177	919	* @param SPIx SPI Instance
<>	161:2cc1468da177	920	* @retval State of bit (1 or 0).
<>	161:2cc1468da177	921	*/
<>	161:2cc1468da177	922	__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXNE(SPI_TypeDef *SPIx)
<>	161:2cc1468da177	923	{
<>	161:2cc1468da177	924	return (READ_BIT(SPIx->SR, SPI_SR_RXNE) == (SPI_SR_RXNE));
<>	161:2cc1468da177	925	}
<>	161:2cc1468da177	926
<>	161:2cc1468da177	927	/**
<>	161:2cc1468da177	928	* @brief Check if Tx buffer is empty
<>	161:2cc1468da177	929	* @rmtoll SR TXE LL_SPI_IsActiveFlag_TXE
<>	161:2cc1468da177	930	* @param SPIx SPI Instance
<>	161:2cc1468da177	931	* @retval State of bit (1 or 0).
<>	161:2cc1468da177	932	*/
<>	161:2cc1468da177	933	__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXE(SPI_TypeDef *SPIx)
<>	161:2cc1468da177	934	{
<>	161:2cc1468da177	935	return (READ_BIT(SPIx->SR, SPI_SR_TXE) == (SPI_SR_TXE));
<>	161:2cc1468da177	936	}
<>	161:2cc1468da177	937
<>	161:2cc1468da177	938	/**
<>	161:2cc1468da177	939	* @brief Get CRC error flag
<>	161:2cc1468da177	940	* @rmtoll SR CRCERR LL_SPI_IsActiveFlag_CRCERR
<>	161:2cc1468da177	941	* @param SPIx SPI Instance
<>	161:2cc1468da177	942	* @retval State of bit (1 or 0).
<>	161:2cc1468da177	943	*/
<>	161:2cc1468da177	944	__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_CRCERR(SPI_TypeDef *SPIx)
<>	161:2cc1468da177	945	{
<>	161:2cc1468da177	946	return (READ_BIT(SPIx->SR, SPI_SR_CRCERR) == (SPI_SR_CRCERR));
<>	161:2cc1468da177	947	}
<>	161:2cc1468da177	948
<>	161:2cc1468da177	949	/**
<>	161:2cc1468da177	950	* @brief Get mode fault error flag
<>	161:2cc1468da177	951	* @rmtoll SR MODF LL_SPI_IsActiveFlag_MODF
<>	161:2cc1468da177	952	* @param SPIx SPI Instance
<>	161:2cc1468da177	953	* @retval State of bit (1 or 0).
<>	161:2cc1468da177	954	*/
<>	161:2cc1468da177	955	__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_MODF(SPI_TypeDef *SPIx)
<>	161:2cc1468da177	956	{
<>	161:2cc1468da177	957	return (READ_BIT(SPIx->SR, SPI_SR_MODF) == (SPI_SR_MODF));
<>	161:2cc1468da177	958	}
<>	161:2cc1468da177	959
<>	161:2cc1468da177	960	/**
<>	161:2cc1468da177	961	* @brief Get overrun error flag
<>	161:2cc1468da177	962	* @rmtoll SR OVR LL_SPI_IsActiveFlag_OVR
<>	161:2cc1468da177	963	* @param SPIx SPI Instance
<>	161:2cc1468da177	964	* @retval State of bit (1 or 0).
<>	161:2cc1468da177	965	*/
<>	161:2cc1468da177	966	__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_OVR(SPI_TypeDef *SPIx)
<>	161:2cc1468da177	967	{
<>	161:2cc1468da177	968	return (READ_BIT(SPIx->SR, SPI_SR_OVR) == (SPI_SR_OVR));
<>	161:2cc1468da177	969	}
<>	161:2cc1468da177	970
<>	161:2cc1468da177	971	/**
<>	161:2cc1468da177	972	* @brief Get busy flag
<>	161:2cc1468da177	973	* @note The BSY flag is cleared under any one of the following conditions:
<>	161:2cc1468da177	974	* -When the SPI is correctly disabled
<>	161:2cc1468da177	975	* -When a fault is detected in Master mode (MODF bit set to 1)
<>	161:2cc1468da177	976	* -In Master mode, when it finishes a data transmission and no new data is ready to be
<>	161:2cc1468da177	977	* sent
<>	161:2cc1468da177	978	* -In Slave mode, when the BSY flag is set to '0' for at least one SPI clock cycle between
<>	161:2cc1468da177	979	* each data transfer.
<>	161:2cc1468da177	980	* @rmtoll SR BSY LL_SPI_IsActiveFlag_BSY
<>	161:2cc1468da177	981	* @param SPIx SPI Instance
<>	161:2cc1468da177	982	* @retval State of bit (1 or 0).
<>	161:2cc1468da177	983	*/
<>	161:2cc1468da177	984	__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_BSY(SPI_TypeDef *SPIx)
<>	161:2cc1468da177	985	{
<>	161:2cc1468da177	986	return (READ_BIT(SPIx->SR, SPI_SR_BSY) == (SPI_SR_BSY));
<>	161:2cc1468da177	987	}
<>	161:2cc1468da177	988
<>	161:2cc1468da177	989	/**
<>	161:2cc1468da177	990	* @brief Get frame format error flag
<>	161:2cc1468da177	991	* @rmtoll SR FRE LL_SPI_IsActiveFlag_FRE
<>	161:2cc1468da177	992	* @param SPIx SPI Instance
<>	161:2cc1468da177	993	* @retval State of bit (1 or 0).
<>	161:2cc1468da177	994	*/
<>	161:2cc1468da177	995	__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_FRE(SPI_TypeDef *SPIx)
<>	161:2cc1468da177	996	{
<>	161:2cc1468da177	997	return (READ_BIT(SPIx->SR, SPI_SR_FRE) == (SPI_SR_FRE));
<>	161:2cc1468da177	998	}
<>	161:2cc1468da177	999
<>	161:2cc1468da177	1000	/**
<>	161:2cc1468da177	1001	* @brief Get FIFO reception Level
<>	161:2cc1468da177	1002	* @rmtoll SR FRLVL LL_SPI_GetRxFIFOLevel
<>	161:2cc1468da177	1003	* @param SPIx SPI Instance
<>	161:2cc1468da177	1004	* @retval Returned value can be one of the following values:
<>	161:2cc1468da177	1005	* @arg @ref LL_SPI_RX_FIFO_EMPTY
<>	161:2cc1468da177	1006	* @arg @ref LL_SPI_RX_FIFO_QUARTER_FULL
<>	161:2cc1468da177	1007	* @arg @ref LL_SPI_RX_FIFO_HALF_FULL
<>	161:2cc1468da177	1008	* @arg @ref LL_SPI_RX_FIFO_FULL
<>	161:2cc1468da177	1009	*/
<>	161:2cc1468da177	1010	__STATIC_INLINE uint32_t LL_SPI_GetRxFIFOLevel(SPI_TypeDef *SPIx)
<>	161:2cc1468da177	1011	{
<>	161:2cc1468da177	1012	return (uint32_t)(READ_BIT(SPIx->SR, SPI_SR_FRLVL));
<>	161:2cc1468da177	1013	}
<>	161:2cc1468da177	1014
<>	161:2cc1468da177	1015	/**
<>	161:2cc1468da177	1016	* @brief Get FIFO Transmission Level
<>	161:2cc1468da177	1017	* @rmtoll SR FTLVL LL_SPI_GetTxFIFOLevel
<>	161:2cc1468da177	1018	* @param SPIx SPI Instance
<>	161:2cc1468da177	1019	* @retval Returned value can be one of the following values:
<>	161:2cc1468da177	1020	* @arg @ref LL_SPI_TX_FIFO_EMPTY
<>	161:2cc1468da177	1021	* @arg @ref LL_SPI_TX_FIFO_QUARTER_FULL
<>	161:2cc1468da177	1022	* @arg @ref LL_SPI_TX_FIFO_HALF_FULL
<>	161:2cc1468da177	1023	* @arg @ref LL_SPI_TX_FIFO_FULL
<>	161:2cc1468da177	1024	*/
<>	161:2cc1468da177	1025	__STATIC_INLINE uint32_t LL_SPI_GetTxFIFOLevel(SPI_TypeDef *SPIx)
<>	161:2cc1468da177	1026	{
<>	161:2cc1468da177	1027	return (uint32_t)(READ_BIT(SPIx->SR, SPI_SR_FTLVL));
<>	161:2cc1468da177	1028	}
<>	161:2cc1468da177	1029
<>	161:2cc1468da177	1030	/**
<>	161:2cc1468da177	1031	* @brief Clear CRC error flag
<>	161:2cc1468da177	1032	* @rmtoll SR CRCERR LL_SPI_ClearFlag_CRCERR
<>	161:2cc1468da177	1033	* @param SPIx SPI Instance
<>	161:2cc1468da177	1034	* @retval None
<>	161:2cc1468da177	1035	*/
<>	161:2cc1468da177	1036	__STATIC_INLINE void LL_SPI_ClearFlag_CRCERR(SPI_TypeDef *SPIx)
<>	161:2cc1468da177	1037	{
<>	161:2cc1468da177	1038	CLEAR_BIT(SPIx->SR, SPI_SR_CRCERR);
<>	161:2cc1468da177	1039	}
<>	161:2cc1468da177	1040
<>	161:2cc1468da177	1041	/**
<>	161:2cc1468da177	1042	* @brief Clear mode fault error flag
<>	161:2cc1468da177	1043	* @note Clearing this flag is done by a read access to the SPIx_SR
<>	161:2cc1468da177	1044	* register followed by a write access to the SPIx_CR1 register
<>	161:2cc1468da177	1045	* @rmtoll SR MODF LL_SPI_ClearFlag_MODF
<>	161:2cc1468da177	1046	* @param SPIx SPI Instance
<>	161:2cc1468da177	1047	* @retval None
<>	161:2cc1468da177	1048	*/
<>	161:2cc1468da177	1049	__STATIC_INLINE void LL_SPI_ClearFlag_MODF(SPI_TypeDef *SPIx)
<>	161:2cc1468da177	1050	{
<>	161:2cc1468da177	1051	__IO uint32_t tmpreg;
<>	161:2cc1468da177	1052	tmpreg = SPIx->SR;
<>	161:2cc1468da177	1053	(void) tmpreg;
<>	161:2cc1468da177	1054	tmpreg = CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE);
<>	161:2cc1468da177	1055	(void) tmpreg;
<>	161:2cc1468da177	1056	}
<>	161:2cc1468da177	1057
<>	161:2cc1468da177	1058	/**
<>	161:2cc1468da177	1059	* @brief Clear overrun error flag
<>	161:2cc1468da177	1060	* @note Clearing this flag is done by a read access to the SPIx_DR
<>	161:2cc1468da177	1061	* register followed by a read access to the SPIx_SR register
<>	161:2cc1468da177	1062	* @rmtoll SR OVR LL_SPI_ClearFlag_OVR
<>	161:2cc1468da177	1063	* @param SPIx SPI Instance
<>	161:2cc1468da177	1064	* @retval None
<>	161:2cc1468da177	1065	*/
<>	161:2cc1468da177	1066	__STATIC_INLINE void LL_SPI_ClearFlag_OVR(SPI_TypeDef *SPIx)
<>	161:2cc1468da177	1067	{
<>	161:2cc1468da177	1068	__IO uint32_t tmpreg;
<>	161:2cc1468da177	1069	tmpreg = SPIx->DR;
<>	161:2cc1468da177	1070	(void) tmpreg;
<>	161:2cc1468da177	1071	tmpreg = SPIx->SR;
<>	161:2cc1468da177	1072	(void) tmpreg;
<>	161:2cc1468da177	1073	}
<>	161:2cc1468da177	1074
<>	161:2cc1468da177	1075	/**
<>	161:2cc1468da177	1076	* @brief Clear frame format error flag
<>	161:2cc1468da177	1077	* @note Clearing this flag is done by reading SPIx_SR register
<>	161:2cc1468da177	1078	* @rmtoll SR FRE LL_SPI_ClearFlag_FRE
<>	161:2cc1468da177	1079	* @param SPIx SPI Instance
<>	161:2cc1468da177	1080	* @retval None
<>	161:2cc1468da177	1081	*/
<>	161:2cc1468da177	1082	__STATIC_INLINE void LL_SPI_ClearFlag_FRE(SPI_TypeDef *SPIx)
<>	161:2cc1468da177	1083	{
<>	161:2cc1468da177	1084	__IO uint32_t tmpreg;
<>	161:2cc1468da177	1085	tmpreg = SPIx->SR;
<>	161:2cc1468da177	1086	(void) tmpreg;
<>	161:2cc1468da177	1087	}
<>	161:2cc1468da177	1088
<>	161:2cc1468da177	1089	/**
<>	161:2cc1468da177	1090	* @}
<>	161:2cc1468da177	1091	*/
<>	161:2cc1468da177	1092
<>	161:2cc1468da177	1093	/** @defgroup SPI_LL_EF_IT_Management Interrupt Management
<>	161:2cc1468da177	1094	* @{
<>	161:2cc1468da177	1095	*/
<>	161:2cc1468da177	1096
<>	161:2cc1468da177	1097	/**
<>	161:2cc1468da177	1098	* @brief Enable error interrupt
<>	161:2cc1468da177	1099	* @note This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode).
<>	161:2cc1468da177	1100	* @rmtoll CR2 ERRIE LL_SPI_EnableIT_ERR
<>	161:2cc1468da177	1101	* @param SPIx SPI Instance
<>	161:2cc1468da177	1102	* @retval None
<>	161:2cc1468da177	1103	*/
<>	161:2cc1468da177	1104	__STATIC_INLINE void LL_SPI_EnableIT_ERR(SPI_TypeDef *SPIx)
<>	161:2cc1468da177	1105	{
<>	161:2cc1468da177	1106	SET_BIT(SPIx->CR2, SPI_CR2_ERRIE);
<>	161:2cc1468da177	1107	}
<>	161:2cc1468da177	1108
<>	161:2cc1468da177	1109	/**
<>	161:2cc1468da177	1110	* @brief Enable Rx buffer not empty interrupt
<>	161:2cc1468da177	1111	* @rmtoll CR2 RXNEIE LL_SPI_EnableIT_RXNE
<>	161:2cc1468da177	1112	* @param SPIx SPI Instance
<>	161:2cc1468da177	1113	* @retval None
<>	161:2cc1468da177	1114	*/
<>	161:2cc1468da177	1115	__STATIC_INLINE void LL_SPI_EnableIT_RXNE(SPI_TypeDef *SPIx)
<>	161:2cc1468da177	1116	{
<>	161:2cc1468da177	1117	SET_BIT(SPIx->CR2, SPI_CR2_RXNEIE);
<>	161:2cc1468da177	1118	}
<>	161:2cc1468da177	1119
<>	161:2cc1468da177	1120	/**
<>	161:2cc1468da177	1121	* @brief Enable Tx buffer empty interrupt
<>	161:2cc1468da177	1122	* @rmtoll CR2 TXEIE LL_SPI_EnableIT_TXE
<>	161:2cc1468da177	1123	* @param SPIx SPI Instance
<>	161:2cc1468da177	1124	* @retval None
<>	161:2cc1468da177	1125	*/
<>	161:2cc1468da177	1126	__STATIC_INLINE void LL_SPI_EnableIT_TXE(SPI_TypeDef *SPIx)
<>	161:2cc1468da177	1127	{
<>	161:2cc1468da177	1128	SET_BIT(SPIx->CR2, SPI_CR2_TXEIE);
<>	161:2cc1468da177	1129	}
<>	161:2cc1468da177	1130
<>	161:2cc1468da177	1131	/**
<>	161:2cc1468da177	1132	* @brief Disable error interrupt
<>	161:2cc1468da177	1133	* @note This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode).
<>	161:2cc1468da177	1134	* @rmtoll CR2 ERRIE LL_SPI_DisableIT_ERR
<>	161:2cc1468da177	1135	* @param SPIx SPI Instance
<>	161:2cc1468da177	1136	* @retval None
<>	161:2cc1468da177	1137	*/
<>	161:2cc1468da177	1138	__STATIC_INLINE void LL_SPI_DisableIT_ERR(SPI_TypeDef *SPIx)
<>	161:2cc1468da177	1139	{
<>	161:2cc1468da177	1140	CLEAR_BIT(SPIx->CR2, SPI_CR2_ERRIE);
<>	161:2cc1468da177	1141	}
<>	161:2cc1468da177	1142
<>	161:2cc1468da177	1143	/**
<>	161:2cc1468da177	1144	* @brief Disable Rx buffer not empty interrupt
<>	161:2cc1468da177	1145	* @rmtoll CR2 RXNEIE LL_SPI_DisableIT_RXNE
<>	161:2cc1468da177	1146	* @param SPIx SPI Instance
<>	161:2cc1468da177	1147	* @retval None
<>	161:2cc1468da177	1148	*/
<>	161:2cc1468da177	1149	__STATIC_INLINE void LL_SPI_DisableIT_RXNE(SPI_TypeDef *SPIx)
<>	161:2cc1468da177	1150	{
<>	161:2cc1468da177	1151	CLEAR_BIT(SPIx->CR2, SPI_CR2_RXNEIE);
<>	161:2cc1468da177	1152	}
<>	161:2cc1468da177	1153
<>	161:2cc1468da177	1154	/**
<>	161:2cc1468da177	1155	* @brief Disable Tx buffer empty interrupt
<>	161:2cc1468da177	1156	* @rmtoll CR2 TXEIE LL_SPI_DisableIT_TXE
<>	161:2cc1468da177	1157	* @param SPIx SPI Instance
<>	161:2cc1468da177	1158	* @retval None
<>	161:2cc1468da177	1159	*/
<>	161:2cc1468da177	1160	__STATIC_INLINE void LL_SPI_DisableIT_TXE(SPI_TypeDef *SPIx)
<>	161:2cc1468da177	1161	{
<>	161:2cc1468da177	1162	CLEAR_BIT(SPIx->CR2, SPI_CR2_TXEIE);
<>	161:2cc1468da177	1163	}
<>	161:2cc1468da177	1164
<>	161:2cc1468da177	1165	/**
<>	161:2cc1468da177	1166	* @brief Check if error interrupt is enabled
<>	161:2cc1468da177	1167	* @rmtoll CR2 ERRIE LL_SPI_IsEnabledIT_ERR
<>	161:2cc1468da177	1168	* @param SPIx SPI Instance
<>	161:2cc1468da177	1169	* @retval State of bit (1 or 0).
<>	161:2cc1468da177	1170	*/
<>	161:2cc1468da177	1171	__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_ERR(SPI_TypeDef *SPIx)
<>	161:2cc1468da177	1172	{
<>	161:2cc1468da177	1173	return (READ_BIT(SPIx->CR2, SPI_CR2_ERRIE) == (SPI_CR2_ERRIE));
<>	161:2cc1468da177	1174	}
<>	161:2cc1468da177	1175
<>	161:2cc1468da177	1176	/**
<>	161:2cc1468da177	1177	* @brief Check if Rx buffer not empty interrupt is enabled
<>	161:2cc1468da177	1178	* @rmtoll CR2 RXNEIE LL_SPI_IsEnabledIT_RXNE
<>	161:2cc1468da177	1179	* @param SPIx SPI Instance
<>	161:2cc1468da177	1180	* @retval State of bit (1 or 0).
<>	161:2cc1468da177	1181	*/
<>	161:2cc1468da177	1182	__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_RXNE(SPI_TypeDef *SPIx)
<>	161:2cc1468da177	1183	{
<>	161:2cc1468da177	1184	return (READ_BIT(SPIx->CR2, SPI_CR2_RXNEIE) == (SPI_CR2_RXNEIE));
<>	161:2cc1468da177	1185	}
<>	161:2cc1468da177	1186
<>	161:2cc1468da177	1187	/**
<>	161:2cc1468da177	1188	* @brief Check if Tx buffer empty interrupt
<>	161:2cc1468da177	1189	* @rmtoll CR2 TXEIE LL_SPI_IsEnabledIT_TXE
<>	161:2cc1468da177	1190	* @param SPIx SPI Instance
<>	161:2cc1468da177	1191	* @retval State of bit (1 or 0).
<>	161:2cc1468da177	1192	*/
<>	161:2cc1468da177	1193	__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXE(SPI_TypeDef *SPIx)
<>	161:2cc1468da177	1194	{
<>	161:2cc1468da177	1195	return (READ_BIT(SPIx->CR2, SPI_CR2_TXEIE) == (SPI_CR2_TXEIE));
<>	161:2cc1468da177	1196	}
<>	161:2cc1468da177	1197
<>	161:2cc1468da177	1198	/**
<>	161:2cc1468da177	1199	* @}
<>	161:2cc1468da177	1200	*/
<>	161:2cc1468da177	1201
<>	161:2cc1468da177	1202	/** @defgroup SPI_LL_EF_DMA_Management DMA Management
<>	161:2cc1468da177	1203	* @{
<>	161:2cc1468da177	1204	*/
<>	161:2cc1468da177	1205
<>	161:2cc1468da177	1206	/**
<>	161:2cc1468da177	1207	* @brief Enable DMA Rx
<>	161:2cc1468da177	1208	* @rmtoll CR2 RXDMAEN LL_SPI_EnableDMAReq_RX
<>	161:2cc1468da177	1209	* @param SPIx SPI Instance
<>	161:2cc1468da177	1210	* @retval None
<>	161:2cc1468da177	1211	*/
<>	161:2cc1468da177	1212	__STATIC_INLINE void LL_SPI_EnableDMAReq_RX(SPI_TypeDef *SPIx)
<>	161:2cc1468da177	1213	{
<>	161:2cc1468da177	1214	SET_BIT(SPIx->CR2, SPI_CR2_RXDMAEN);
<>	161:2cc1468da177	1215	}
<>	161:2cc1468da177	1216
<>	161:2cc1468da177	1217	/**
<>	161:2cc1468da177	1218	* @brief Disable DMA Rx
<>	161:2cc1468da177	1219	* @rmtoll CR2 RXDMAEN LL_SPI_DisableDMAReq_RX
<>	161:2cc1468da177	1220	* @param SPIx SPI Instance
<>	161:2cc1468da177	1221	* @retval None
<>	161:2cc1468da177	1222	*/
<>	161:2cc1468da177	1223	__STATIC_INLINE void LL_SPI_DisableDMAReq_RX(SPI_TypeDef *SPIx)
<>	161:2cc1468da177	1224	{
<>	161:2cc1468da177	1225	CLEAR_BIT(SPIx->CR2, SPI_CR2_RXDMAEN);
<>	161:2cc1468da177	1226	}
<>	161:2cc1468da177	1227
<>	161:2cc1468da177	1228	/**
<>	161:2cc1468da177	1229	* @brief Check if DMA Rx is enabled
<>	161:2cc1468da177	1230	* @rmtoll CR2 RXDMAEN LL_SPI_IsEnabledDMAReq_RX
<>	161:2cc1468da177	1231	* @param SPIx SPI Instance
<>	161:2cc1468da177	1232	* @retval State of bit (1 or 0).
<>	161:2cc1468da177	1233	*/
<>	161:2cc1468da177	1234	__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx)
<>	161:2cc1468da177	1235	{
<>	161:2cc1468da177	1236	return (READ_BIT(SPIx->CR2, SPI_CR2_RXDMAEN) == (SPI_CR2_RXDMAEN));
<>	161:2cc1468da177	1237	}
<>	161:2cc1468da177	1238
<>	161:2cc1468da177	1239	/**
<>	161:2cc1468da177	1240	* @brief Enable DMA Tx
<>	161:2cc1468da177	1241	* @rmtoll CR2 TXDMAEN LL_SPI_EnableDMAReq_TX
<>	161:2cc1468da177	1242	* @param SPIx SPI Instance
<>	161:2cc1468da177	1243	* @retval None
<>	161:2cc1468da177	1244	*/
<>	161:2cc1468da177	1245	__STATIC_INLINE void LL_SPI_EnableDMAReq_TX(SPI_TypeDef *SPIx)
<>	161:2cc1468da177	1246	{
<>	161:2cc1468da177	1247	SET_BIT(SPIx->CR2, SPI_CR2_TXDMAEN);
<>	161:2cc1468da177	1248	}
<>	161:2cc1468da177	1249
<>	161:2cc1468da177	1250	/**
<>	161:2cc1468da177	1251	* @brief Disable DMA Tx
<>	161:2cc1468da177	1252	* @rmtoll CR2 TXDMAEN LL_SPI_DisableDMAReq_TX
<>	161:2cc1468da177	1253	* @param SPIx SPI Instance
<>	161:2cc1468da177	1254	* @retval None
<>	161:2cc1468da177	1255	*/
<>	161:2cc1468da177	1256	__STATIC_INLINE void LL_SPI_DisableDMAReq_TX(SPI_TypeDef *SPIx)
<>	161:2cc1468da177	1257	{
<>	161:2cc1468da177	1258	CLEAR_BIT(SPIx->CR2, SPI_CR2_TXDMAEN);
<>	161:2cc1468da177	1259	}
<>	161:2cc1468da177	1260
<>	161:2cc1468da177	1261	/**
<>	161:2cc1468da177	1262	* @brief Check if DMA Tx is enabled
<>	161:2cc1468da177	1263	* @rmtoll CR2 TXDMAEN LL_SPI_IsEnabledDMAReq_TX
<>	161:2cc1468da177	1264	* @param SPIx SPI Instance
<>	161:2cc1468da177	1265	* @retval State of bit (1 or 0).
<>	161:2cc1468da177	1266	*/
<>	161:2cc1468da177	1267	__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx)
<>	161:2cc1468da177	1268	{
<>	161:2cc1468da177	1269	return (READ_BIT(SPIx->CR2, SPI_CR2_TXDMAEN) == (SPI_CR2_TXDMAEN));
<>	161:2cc1468da177	1270	}
<>	161:2cc1468da177	1271
<>	161:2cc1468da177	1272	/**
<>	161:2cc1468da177	1273	* @brief Set parity of Last DMA reception
<>	161:2cc1468da177	1274	* @rmtoll CR2 LDMARX LL_SPI_SetDMAParity_RX
<>	161:2cc1468da177	1275	* @param SPIx SPI Instance
<>	161:2cc1468da177	1276	* @param Parity This parameter can be one of the following values:
<>	161:2cc1468da177	1277	* @arg @ref LL_SPI_DMA_PARITY_ODD
<>	161:2cc1468da177	1278	* @arg @ref LL_SPI_DMA_PARITY_EVEN
<>	161:2cc1468da177	1279	* @retval None
<>	161:2cc1468da177	1280	*/
<>	161:2cc1468da177	1281	__STATIC_INLINE void LL_SPI_SetDMAParity_RX(SPI_TypeDef *SPIx, uint32_t Parity)
<>	161:2cc1468da177	1282	{
<>	161:2cc1468da177	1283	MODIFY_REG(SPIx->CR2, SPI_CR2_LDMARX, (Parity << SPI_CR2_LDMARX_Pos));
<>	161:2cc1468da177	1284	}
<>	161:2cc1468da177	1285
<>	161:2cc1468da177	1286	/**
<>	161:2cc1468da177	1287	* @brief Get parity configuration for Last DMA reception
<>	161:2cc1468da177	1288	* @rmtoll CR2 LDMARX LL_SPI_GetDMAParity_RX
<>	161:2cc1468da177	1289	* @param SPIx SPI Instance
<>	161:2cc1468da177	1290	* @retval Returned value can be one of the following values:
<>	161:2cc1468da177	1291	* @arg @ref LL_SPI_DMA_PARITY_ODD
<>	161:2cc1468da177	1292	* @arg @ref LL_SPI_DMA_PARITY_EVEN
<>	161:2cc1468da177	1293	*/
<>	161:2cc1468da177	1294	__STATIC_INLINE uint32_t LL_SPI_GetDMAParity_RX(SPI_TypeDef *SPIx)
<>	161:2cc1468da177	1295	{
<>	161:2cc1468da177	1296	return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_LDMARX) >> SPI_CR2_LDMARX_Pos);
<>	161:2cc1468da177	1297	}
<>	161:2cc1468da177	1298
<>	161:2cc1468da177	1299	/**
<>	161:2cc1468da177	1300	* @brief Set parity of Last DMA transmission
<>	161:2cc1468da177	1301	* @rmtoll CR2 LDMATX LL_SPI_SetDMAParity_TX
<>	161:2cc1468da177	1302	* @param SPIx SPI Instance
<>	161:2cc1468da177	1303	* @param Parity This parameter can be one of the following values:
<>	161:2cc1468da177	1304	* @arg @ref LL_SPI_DMA_PARITY_ODD
<>	161:2cc1468da177	1305	* @arg @ref LL_SPI_DMA_PARITY_EVEN
<>	161:2cc1468da177	1306	* @retval None
<>	161:2cc1468da177	1307	*/
<>	161:2cc1468da177	1308	__STATIC_INLINE void LL_SPI_SetDMAParity_TX(SPI_TypeDef *SPIx, uint32_t Parity)
<>	161:2cc1468da177	1309	{
<>	161:2cc1468da177	1310	MODIFY_REG(SPIx->CR2, SPI_CR2_LDMATX, (Parity << SPI_CR2_LDMATX_Pos));
<>	161:2cc1468da177	1311	}
<>	161:2cc1468da177	1312
<>	161:2cc1468da177	1313	/**
<>	161:2cc1468da177	1314	* @brief Get parity configuration for Last DMA transmission
<>	161:2cc1468da177	1315	* @rmtoll CR2 LDMATX LL_SPI_GetDMAParity_TX
<>	161:2cc1468da177	1316	* @param SPIx SPI Instance
<>	161:2cc1468da177	1317	* @retval Returned value can be one of the following values:
<>	161:2cc1468da177	1318	* @arg @ref LL_SPI_DMA_PARITY_ODD
<>	161:2cc1468da177	1319	* @arg @ref LL_SPI_DMA_PARITY_EVEN
<>	161:2cc1468da177	1320	*/
<>	161:2cc1468da177	1321	__STATIC_INLINE uint32_t LL_SPI_GetDMAParity_TX(SPI_TypeDef *SPIx)
<>	161:2cc1468da177	1322	{
<>	161:2cc1468da177	1323	return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_LDMATX) >> SPI_CR2_LDMATX_Pos);
<>	161:2cc1468da177	1324	}
<>	161:2cc1468da177	1325
<>	161:2cc1468da177	1326	/**
<>	161:2cc1468da177	1327	* @brief Get the data register address used for DMA transfer
<>	161:2cc1468da177	1328	* @rmtoll DR DR LL_SPI_DMA_GetRegAddr
<>	161:2cc1468da177	1329	* @param SPIx SPI Instance
<>	161:2cc1468da177	1330	* @retval Address of data register
<>	161:2cc1468da177	1331	*/
<>	161:2cc1468da177	1332	__STATIC_INLINE uint32_t LL_SPI_DMA_GetRegAddr(SPI_TypeDef *SPIx)
<>	161:2cc1468da177	1333	{
<>	161:2cc1468da177	1334	return (uint32_t) & (SPIx->DR);
<>	161:2cc1468da177	1335	}
<>	161:2cc1468da177	1336
<>	161:2cc1468da177	1337	/**
<>	161:2cc1468da177	1338	* @}
<>	161:2cc1468da177	1339	*/
<>	161:2cc1468da177	1340
<>	161:2cc1468da177	1341	/** @defgroup SPI_LL_EF_DATA_Management DATA Management
<>	161:2cc1468da177	1342	* @{
<>	161:2cc1468da177	1343	*/
<>	161:2cc1468da177	1344
<>	161:2cc1468da177	1345	/**
<>	161:2cc1468da177	1346	* @brief Read 8-Bits in the data register
<>	161:2cc1468da177	1347	* @rmtoll DR DR LL_SPI_ReceiveData8
<>	161:2cc1468da177	1348	* @param SPIx SPI Instance
<>	161:2cc1468da177	1349	* @retval RxData Value between Min_Data=0x00 and Max_Data=0xFF
<>	161:2cc1468da177	1350	*/
<>	161:2cc1468da177	1351	__STATIC_INLINE uint8_t LL_SPI_ReceiveData8(SPI_TypeDef *SPIx)
<>	161:2cc1468da177	1352	{
<>	161:2cc1468da177	1353	return (uint8_t)(READ_REG(SPIx->DR));
<>	161:2cc1468da177	1354	}
<>	161:2cc1468da177	1355
<>	161:2cc1468da177	1356	/**
<>	161:2cc1468da177	1357	* @brief Read 16-Bits in the data register
<>	161:2cc1468da177	1358	* @rmtoll DR DR LL_SPI_ReceiveData16
<>	161:2cc1468da177	1359	* @param SPIx SPI Instance
<>	161:2cc1468da177	1360	* @retval RxData Value between Min_Data=0x00 and Max_Data=0xFFFF
<>	161:2cc1468da177	1361	*/
<>	161:2cc1468da177	1362	__STATIC_INLINE uint16_t LL_SPI_ReceiveData16(SPI_TypeDef *SPIx)
<>	161:2cc1468da177	1363	{
<>	161:2cc1468da177	1364	return (uint16_t)(READ_REG(SPIx->DR));
<>	161:2cc1468da177	1365	}
<>	161:2cc1468da177	1366
<>	161:2cc1468da177	1367	/**
<>	161:2cc1468da177	1368	* @brief Write 8-Bits in the data register
<>	161:2cc1468da177	1369	* @rmtoll DR DR LL_SPI_TransmitData8
<>	161:2cc1468da177	1370	* @param SPIx SPI Instance
<>	161:2cc1468da177	1371	* @param TxData Value between Min_Data=0x00 and Max_Data=0xFF
<>	161:2cc1468da177	1372	* @retval None
<>	161:2cc1468da177	1373	*/
<>	161:2cc1468da177	1374	__STATIC_INLINE void LL_SPI_TransmitData8(SPI_TypeDef *SPIx, uint8_t TxData)
<>	161:2cc1468da177	1375	{
<>	161:2cc1468da177	1376	((__IO uint8_t )&SPIx->DR) = TxData;
<>	161:2cc1468da177	1377	}
<>	161:2cc1468da177	1378
<>	161:2cc1468da177	1379	/**
<>	161:2cc1468da177	1380	* @brief Write 16-Bits in the data register
<>	161:2cc1468da177	1381	* @rmtoll DR DR LL_SPI_TransmitData16
<>	161:2cc1468da177	1382	* @param SPIx SPI Instance
<>	161:2cc1468da177	1383	* @param TxData Value between Min_Data=0x00 and Max_Data=0xFFFF
<>	161:2cc1468da177	1384	* @retval None
<>	161:2cc1468da177	1385	*/
<>	161:2cc1468da177	1386	__STATIC_INLINE void LL_SPI_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData)
<>	161:2cc1468da177	1387	{
<>	161:2cc1468da177	1388	((__IO uint16_t )&SPIx->DR) = TxData;
<>	161:2cc1468da177	1389	}
<>	161:2cc1468da177	1390
<>	161:2cc1468da177	1391	/**
<>	161:2cc1468da177	1392	* @}
<>	161:2cc1468da177	1393	*/
<>	161:2cc1468da177	1394	#if defined(USE_FULL_LL_DRIVER)
<>	161:2cc1468da177	1395	/** @defgroup SPI_LL_EF_Init Initialization and de-initialization functions
<>	161:2cc1468da177	1396	* @{
<>	161:2cc1468da177	1397	*/
<>	161:2cc1468da177	1398
<>	161:2cc1468da177	1399	ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx);
<>	161:2cc1468da177	1400	ErrorStatus LL_SPI_Init(SPI_TypeDef SPIx, LL_SPI_InitTypeDef SPI_InitStruct);
<>	161:2cc1468da177	1401	void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct);
<>	161:2cc1468da177	1402
<>	161:2cc1468da177	1403	/**
<>	161:2cc1468da177	1404	* @}
<>	161:2cc1468da177	1405	*/
<>	161:2cc1468da177	1406	#endif /* USE_FULL_LL_DRIVER */
<>	161:2cc1468da177	1407	/**
<>	161:2cc1468da177	1408	* @}
<>	161:2cc1468da177	1409	*/
<>	161:2cc1468da177	1410
<>	161:2cc1468da177	1411	/**
<>	161:2cc1468da177	1412	* @}
<>	161:2cc1468da177	1413	*/
<>	161:2cc1468da177	1414
<>	161:2cc1468da177	1415	/** @defgroup I2S_LL I2S
<>	161:2cc1468da177	1416	* @{
<>	161:2cc1468da177	1417	*/
<>	161:2cc1468da177	1418
<>	161:2cc1468da177	1419	/* Private variables ---------------------------------------------------------*/
<>	161:2cc1468da177	1420	/* Private constants ---------------------------------------------------------*/
<>	161:2cc1468da177	1421	/* Private macros ------------------------------------------------------------*/
<>	161:2cc1468da177	1422
<>	161:2cc1468da177	1423	/* Exported types ------------------------------------------------------------*/
<>	161:2cc1468da177	1424	#if defined(USE_FULL_LL_DRIVER)
<>	161:2cc1468da177	1425	/** @defgroup I2S_LL_ES_INIT I2S Exported Init structure
<>	161:2cc1468da177	1426	* @{
<>	161:2cc1468da177	1427	*/
<>	161:2cc1468da177	1428
<>	161:2cc1468da177	1429	/**
<>	161:2cc1468da177	1430	* @brief I2S Init structure definition
<>	161:2cc1468da177	1431	*/
<>	161:2cc1468da177	1432
<>	161:2cc1468da177	1433	typedef struct
<>	161:2cc1468da177	1434	{
<>	161:2cc1468da177	1435	uint32_t Mode; /*!< Specifies the I2S operating mode.
<>	161:2cc1468da177	1436	This parameter can be a value of @ref I2S_LL_EC_MODE
<>	161:2cc1468da177	1437
<>	161:2cc1468da177	1438	This feature can be modified afterwards using unitary function @ref LL_I2S_SetTransferMode().*/
<>	161:2cc1468da177	1439
<>	161:2cc1468da177	1440	uint32_t Standard; /*!< Specifies the standard used for the I2S communication.
<>	161:2cc1468da177	1441	This parameter can be a value of @ref I2S_LL_EC_STANDARD
<>	161:2cc1468da177	1442
<>	161:2cc1468da177	1443	This feature can be modified afterwards using unitary function @ref LL_I2S_SetStandard().*/
<>	161:2cc1468da177	1444
<>	161:2cc1468da177	1445
<>	161:2cc1468da177	1446	uint32_t DataFormat; /*!< Specifies the data format for the I2S communication.
<>	161:2cc1468da177	1447	This parameter can be a value of @ref I2S_LL_EC_DATA_FORMAT
<>	161:2cc1468da177	1448
<>	161:2cc1468da177	1449	This feature can be modified afterwards using unitary function @ref LL_I2S_SetDataFormat().*/
<>	161:2cc1468da177	1450
<>	161:2cc1468da177	1451
<>	161:2cc1468da177	1452	uint32_t MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not.
<>	161:2cc1468da177	1453	This parameter can be a value of @ref I2S_LL_EC_MCLK_OUTPUT
<>	161:2cc1468da177	1454
<>	161:2cc1468da177	1455	This feature can be modified afterwards using unitary functions @ref LL_I2S_EnableMasterClock() or @ref LL_I2S_DisableMasterClock.*/
<>	161:2cc1468da177	1456
<>	161:2cc1468da177	1457
<>	161:2cc1468da177	1458	uint32_t AudioFreq; /*!< Specifies the frequency selected for the I2S communication.
<>	161:2cc1468da177	1459	This parameter can be a value of @ref I2S_LL_EC_AUDIO_FREQ
<>	161:2cc1468da177	1460
<>	161:2cc1468da177	1461	Audio Frequency can be modified afterwards using Reference manual formulas to calculate Prescaler Linear, Parity
<>	161:2cc1468da177	1462	and unitary functions @ref LL_I2S_SetPrescalerLinear() and @ref LL_I2S_SetPrescalerParity() to set it.*/
<>	161:2cc1468da177	1463
<>	161:2cc1468da177	1464
<>	161:2cc1468da177	1465	uint32_t ClockPolarity; /*!< Specifies the idle state of the I2S clock.
<>	161:2cc1468da177	1466	This parameter can be a value of @ref I2S_LL_EC_POLARITY
<>	161:2cc1468da177	1467
<>	161:2cc1468da177	1468	This feature can be modified afterwards using unitary function @ref LL_I2S_SetClockPolarity().*/
<>	161:2cc1468da177	1469
<>	161:2cc1468da177	1470	} LL_I2S_InitTypeDef;
<>	161:2cc1468da177	1471
<>	161:2cc1468da177	1472	/**
<>	161:2cc1468da177	1473	* @}
<>	161:2cc1468da177	1474	*/
<>	161:2cc1468da177	1475	#endif /USE_FULL_LL_DRIVER/
<>	161:2cc1468da177	1476
<>	161:2cc1468da177	1477	/* Exported constants --------------------------------------------------------*/
<>	161:2cc1468da177	1478	/** @defgroup I2S_LL_Exported_Constants I2S Exported Constants
<>	161:2cc1468da177	1479	* @{
<>	161:2cc1468da177	1480	*/
<>	161:2cc1468da177	1481
<>	161:2cc1468da177	1482	/** @defgroup I2S_LL_EC_GET_FLAG Get Flags Defines
<>	161:2cc1468da177	1483	* @brief Flags defines which can be used with LL_I2S_ReadReg function
<>	161:2cc1468da177	1484	* @{
<>	161:2cc1468da177	1485	*/
<>	161:2cc1468da177	1486	#define LL_I2S_SR_RXNE LL_SPI_SR_RXNE /!< Rx buffer not empty flag /
<>	161:2cc1468da177	1487	#define LL_I2S_SR_TXE LL_SPI_SR_TXE /!< Tx buffer empty flag /
<>	161:2cc1468da177	1488	#define LL_I2S_SR_BSY LL_SPI_SR_BSY /!< Busy flag /
<>	161:2cc1468da177	1489	#define LL_I2S_SR_UDR SPI_SR_UDR /!< Underrun flag /
<>	161:2cc1468da177	1490	#define LL_I2S_SR_OVR LL_SPI_SR_OVR /!< Overrun flag /
<>	161:2cc1468da177	1491	#define LL_I2S_SR_FRE LL_SPI_SR_FRE /!< TI mode frame format error flag /
<>	161:2cc1468da177	1492	/**
<>	161:2cc1468da177	1493	* @}
<>	161:2cc1468da177	1494	*/
<>	161:2cc1468da177	1495
<>	161:2cc1468da177	1496	/** @defgroup SPI_LL_EC_IT IT Defines
<>	161:2cc1468da177	1497	* @brief IT defines which can be used with LL_SPI_ReadReg and LL_SPI_WriteReg functions
<>	161:2cc1468da177	1498	* @{
<>	161:2cc1468da177	1499	*/
<>	161:2cc1468da177	1500	#define LL_I2S_CR2_RXNEIE LL_SPI_CR2_RXNEIE /!< Rx buffer not empty interrupt enable /
<>	161:2cc1468da177	1501	#define LL_I2S_CR2_TXEIE LL_SPI_CR2_TXEIE /!< Tx buffer empty interrupt enable /
<>	161:2cc1468da177	1502	#define LL_I2S_CR2_ERRIE LL_SPI_CR2_ERRIE /!< Error interrupt enable /
<>	161:2cc1468da177	1503	/**
<>	161:2cc1468da177	1504	* @}
<>	161:2cc1468da177	1505	*/
<>	161:2cc1468da177	1506
<>	161:2cc1468da177	1507	/** @defgroup I2S_LL_EC_DATA_FORMAT Data format
<>	161:2cc1468da177	1508	* @{
<>	161:2cc1468da177	1509	*/
<>	161:2cc1468da177	1510	#define LL_I2S_DATAFORMAT_16B 0x00000000U /!< Data length 16 bits, Channel lenght 16bit /
<>	161:2cc1468da177	1511	#define LL_I2S_DATAFORMAT_16B_EXTENDED (SPI_I2SCFGR_CHLEN) /!< Data length 16 bits, Channel lenght 32bit /
<>	161:2cc1468da177	1512	#define LL_I2S_DATAFORMAT_24B (SPI_I2SCFGR_CHLEN \| SPI_I2SCFGR_DATLEN_0) /!< Data length 24 bits, Channel lenght 32bit /
<>	161:2cc1468da177	1513	#define LL_I2S_DATAFORMAT_32B (SPI_I2SCFGR_CHLEN \| SPI_I2SCFGR_DATLEN_1) /!< Data length 16 bits, Channel lenght 32bit /
<>	161:2cc1468da177	1514	/**
<>	161:2cc1468da177	1515	* @}
<>	161:2cc1468da177	1516	*/
<>	161:2cc1468da177	1517
<>	161:2cc1468da177	1518	/** @defgroup I2S_LL_EC_POLARITY Clock Polarity
<>	161:2cc1468da177	1519	* @{
<>	161:2cc1468da177	1520	*/
<>	161:2cc1468da177	1521	#define LL_I2S_POLARITY_LOW 0x00000000U /!< Clock steady state is low level /
<>	161:2cc1468da177	1522	#define LL_I2S_POLARITY_HIGH (SPI_I2SCFGR_CKPOL) /!< Clock steady state is high level /
<>	161:2cc1468da177	1523	/**
<>	161:2cc1468da177	1524	* @}
<>	161:2cc1468da177	1525	*/
<>	161:2cc1468da177	1526
<>	161:2cc1468da177	1527	/** @defgroup I2S_LL_EC_STANDARD I2s Standard
<>	161:2cc1468da177	1528	* @{
<>	161:2cc1468da177	1529	*/
<>	161:2cc1468da177	1530	#define LL_I2S_STANDARD_PHILIPS 0x00000000U /!< I2S standard philips /
<>	161:2cc1468da177	1531	#define LL_I2S_STANDARD_MSB (SPI_I2SCFGR_I2SSTD_0) /!< MSB justified standard (left justified) /
<>	161:2cc1468da177	1532	#define LL_I2S_STANDARD_LSB (SPI_I2SCFGR_I2SSTD_1) /!< LSB justified standard (right justified) /
<>	161:2cc1468da177	1533	#define LL_I2S_STANDARD_PCM_SHORT (SPI_I2SCFGR_I2SSTD_0 \| SPI_I2SCFGR_I2SSTD_1) /!< PCM standard, short frame synchronization /
<>	161:2cc1468da177	1534	#define LL_I2S_STANDARD_PCM_LONG (SPI_I2SCFGR_I2SSTD_0 \| SPI_I2SCFGR_I2SSTD_1 \| SPI_I2SCFGR_PCMSYNC) /!< PCM standard, long frame synchronization /
<>	161:2cc1468da177	1535	/**
<>	161:2cc1468da177	1536	* @}
<>	161:2cc1468da177	1537	*/
<>	161:2cc1468da177	1538
<>	161:2cc1468da177	1539	/** @defgroup I2S_LL_EC_MODE Operation Mode
<>	161:2cc1468da177	1540	* @{
<>	161:2cc1468da177	1541	*/
<>	161:2cc1468da177	1542	#define LL_I2S_MODE_SLAVE_TX 0x00000000U /!< Slave Tx configuration /
<>	161:2cc1468da177	1543	#define LL_I2S_MODE_SLAVE_RX (SPI_I2SCFGR_I2SCFG_0) /!< Slave Rx configuration /
<>	161:2cc1468da177	1544	#define LL_I2S_MODE_MASTER_TX (SPI_I2SCFGR_I2SCFG_1) /!< Master Tx configuration /
<>	161:2cc1468da177	1545	#define LL_I2S_MODE_MASTER_RX (SPI_I2SCFGR_I2SCFG_0 \| SPI_I2SCFGR_I2SCFG_1) /!< Master Rx configuration /
<>	161:2cc1468da177	1546	/**
<>	161:2cc1468da177	1547	* @}
<>	161:2cc1468da177	1548	*/
<>	161:2cc1468da177	1549
<>	161:2cc1468da177	1550	/** @defgroup I2S_LL_EC_PRESCALER_FACTOR Prescaler Factor
<>	161:2cc1468da177	1551	* @{
<>	161:2cc1468da177	1552	*/
<>	161:2cc1468da177	1553	#define LL_I2S_PRESCALER_PARITY_EVEN 0x00000000U /!< Odd factor: Real divider value is = I2SDIV 2 */
<>	161:2cc1468da177	1554	#define LL_I2S_PRESCALER_PARITY_ODD (SPI_I2SPR_ODD >> 8U) /!< Odd factor: Real divider value is = (I2SDIV 2)+1 */
<>	161:2cc1468da177	1555	/**
<>	161:2cc1468da177	1556	* @}
<>	161:2cc1468da177	1557	*/
<>	161:2cc1468da177	1558
<>	161:2cc1468da177	1559	#if defined(USE_FULL_LL_DRIVER)
<>	161:2cc1468da177	1560
<>	161:2cc1468da177	1561	/** @defgroup I2S_LL_EC_MCLK_OUTPUT MCLK Output
<>	161:2cc1468da177	1562	* @{
<>	161:2cc1468da177	1563	*/
<>	161:2cc1468da177	1564	#define LL_I2S_MCLK_OUTPUT_DISABLE 0x00000000U /!< Master clock output is disabled /
<>	161:2cc1468da177	1565	#define LL_I2S_MCLK_OUTPUT_ENABLE (SPI_I2SPR_MCKOE) /!< Master clock output is enabled /
<>	161:2cc1468da177	1566	/**
<>	161:2cc1468da177	1567	* @}
<>	161:2cc1468da177	1568	*/
<>	161:2cc1468da177	1569
<>	161:2cc1468da177	1570	/** @defgroup I2S_LL_EC_AUDIO_FREQ Audio Frequency
<>	161:2cc1468da177	1571	* @{
<>	161:2cc1468da177	1572	*/
<>	161:2cc1468da177	1573
<>	161:2cc1468da177	1574	#define LL_I2S_AUDIOFREQ_192K 192000U /!< Audio Frequency configuration 192000 Hz /
<>	161:2cc1468da177	1575	#define LL_I2S_AUDIOFREQ_96K 96000U /!< Audio Frequency configuration 96000 Hz /
<>	161:2cc1468da177	1576	#define LL_I2S_AUDIOFREQ_48K 48000U /!< Audio Frequency configuration 48000 Hz /
<>	161:2cc1468da177	1577	#define LL_I2S_AUDIOFREQ_44K 44100U /!< Audio Frequency configuration 44100 Hz /
<>	161:2cc1468da177	1578	#define LL_I2S_AUDIOFREQ_32K 32000U /!< Audio Frequency configuration 32000 Hz /
<>	161:2cc1468da177	1579	#define LL_I2S_AUDIOFREQ_22K 22050U /!< Audio Frequency configuration 22050 Hz /
<>	161:2cc1468da177	1580	#define LL_I2S_AUDIOFREQ_16K 16000U /!< Audio Frequency configuration 16000 Hz /
<>	161:2cc1468da177	1581	#define LL_I2S_AUDIOFREQ_11K 11025U /!< Audio Frequency configuration 11025 Hz /
<>	161:2cc1468da177	1582	#define LL_I2S_AUDIOFREQ_8K 8000U /!< Audio Frequency configuration 8000 Hz /
<>	161:2cc1468da177	1583	#define LL_I2S_AUDIOFREQ_DEFAULT 2U /!< Audio Freq not specified. Register I2SDIV = 2 /
<>	161:2cc1468da177	1584	/**
<>	161:2cc1468da177	1585	* @}
<>	161:2cc1468da177	1586	*/
<>	161:2cc1468da177	1587	#endif /* USE_FULL_LL_DRIVER */
<>	161:2cc1468da177	1588
<>	161:2cc1468da177	1589	/**
<>	161:2cc1468da177	1590	* @}
<>	161:2cc1468da177	1591	*/
<>	161:2cc1468da177	1592
<>	161:2cc1468da177	1593	/* Exported macro ------------------------------------------------------------*/
<>	161:2cc1468da177	1594	/** @defgroup I2S_LL_Exported_Macros I2S Exported Macros
<>	161:2cc1468da177	1595	* @{
<>	161:2cc1468da177	1596	*/
<>	161:2cc1468da177	1597
<>	161:2cc1468da177	1598	/** @defgroup I2S_LL_EM_WRITE_READ Common Write and read registers Macros
<>	161:2cc1468da177	1599	* @{
<>	161:2cc1468da177	1600	*/
<>	161:2cc1468da177	1601
<>	161:2cc1468da177	1602	/**
<>	161:2cc1468da177	1603	* @brief Write a value in I2S register
<>	161:2cc1468da177	1604	* @param __INSTANCE__ I2S Instance
<>	161:2cc1468da177	1605	* @param __REG__ Register to be written
<>	161:2cc1468da177	1606	* @param __VALUE__ Value to be written in the register
<>	161:2cc1468da177	1607	* @retval None
<>	161:2cc1468da177	1608	*/
<>	161:2cc1468da177	1609	#define LL_I2S_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
<>	161:2cc1468da177	1610
<>	161:2cc1468da177	1611	/**
<>	161:2cc1468da177	1612	* @brief Read a value in I2S register
<>	161:2cc1468da177	1613	* @param __INSTANCE__ I2S Instance
<>	161:2cc1468da177	1614	* @param __REG__ Register to be read
<>	161:2cc1468da177	1615	* @retval Register value
<>	161:2cc1468da177	1616	*/
<>	161:2cc1468da177	1617	#define LL_I2S_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
<>	161:2cc1468da177	1618	/**
<>	161:2cc1468da177	1619	* @}
<>	161:2cc1468da177	1620	*/
<>	161:2cc1468da177	1621
<>	161:2cc1468da177	1622	/**
<>	161:2cc1468da177	1623	* @}
<>	161:2cc1468da177	1624	*/
<>	161:2cc1468da177	1625
<>	161:2cc1468da177	1626
<>	161:2cc1468da177	1627	/* Exported functions --------------------------------------------------------*/
<>	161:2cc1468da177	1628
<>	161:2cc1468da177	1629	/** @defgroup I2S_LL_Exported_Functions I2S Exported Functions
<>	161:2cc1468da177	1630	* @{
<>	161:2cc1468da177	1631	*/
<>	161:2cc1468da177	1632
<>	161:2cc1468da177	1633	/** @defgroup I2S_LL_EF_Configuration Configuration
<>	161:2cc1468da177	1634	* @{
<>	161:2cc1468da177	1635	*/
<>	161:2cc1468da177	1636
<>	161:2cc1468da177	1637	/**
<>	161:2cc1468da177	1638	* @brief Select I2S mode and Enable I2S peripheral
<>	161:2cc1468da177	1639	* @rmtoll I2SCFGR I2SMOD LL_I2S_Enable\n
<>	161:2cc1468da177	1640	* I2SCFGR I2SE LL_I2S_Enable
<>	161:2cc1468da177	1641	* @param SPIx SPI Instance
<>	161:2cc1468da177	1642	* @retval None
<>	161:2cc1468da177	1643	*/
<>	161:2cc1468da177	1644	__STATIC_INLINE void LL_I2S_Enable(SPI_TypeDef *SPIx)
<>	161:2cc1468da177	1645	{
<>	161:2cc1468da177	1646	SET_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD \| SPI_I2SCFGR_I2SE);
<>	161:2cc1468da177	1647	}
<>	161:2cc1468da177	1648
<>	161:2cc1468da177	1649	/**
<>	161:2cc1468da177	1650	* @brief Disable I2S peripheral
<>	161:2cc1468da177	1651	* @rmtoll I2SCFGR I2SE LL_I2S_Disable
<>	161:2cc1468da177	1652	* @param SPIx SPI Instance
<>	161:2cc1468da177	1653	* @retval None
<>	161:2cc1468da177	1654	*/
<>	161:2cc1468da177	1655	__STATIC_INLINE void LL_I2S_Disable(SPI_TypeDef *SPIx)
<>	161:2cc1468da177	1656	{
<>	161:2cc1468da177	1657	CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD \| SPI_I2SCFGR_I2SE);
<>	161:2cc1468da177	1658	}
<>	161:2cc1468da177	1659
<>	161:2cc1468da177	1660	/**
<>	161:2cc1468da177	1661	* @brief Check if I2S peripheral is enabled
<>	161:2cc1468da177	1662	* @rmtoll I2SCFGR I2SE LL_I2S_IsEnabled
<>	161:2cc1468da177	1663	* @param SPIx SPI Instance
<>	161:2cc1468da177	1664	* @retval State of bit (1 or 0).
<>	161:2cc1468da177	1665	*/
<>	161:2cc1468da177	1666	__STATIC_INLINE uint32_t LL_I2S_IsEnabled(SPI_TypeDef *SPIx)
<>	161:2cc1468da177	1667	{
<>	161:2cc1468da177	1668	return (READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SE) == (SPI_I2SCFGR_I2SE));
<>	161:2cc1468da177	1669	}
<>	161:2cc1468da177	1670
<>	161:2cc1468da177	1671	/**
<>	161:2cc1468da177	1672	* @brief Set I2S data frame length
<>	161:2cc1468da177	1673	* @rmtoll I2SCFGR DATLEN LL_I2S_SetDataFormat\n
<>	161:2cc1468da177	1674	* I2SCFGR CHLEN LL_I2S_SetDataFormat
<>	161:2cc1468da177	1675	* @param SPIx SPI Instance
<>	161:2cc1468da177	1676	* @param DataFormat This parameter can be one of the following values:
<>	161:2cc1468da177	1677	* @arg @ref LL_I2S_DATAFORMAT_16B
<>	161:2cc1468da177	1678	* @arg @ref LL_I2S_DATAFORMAT_16B_EXTENDED
<>	161:2cc1468da177	1679	* @arg @ref LL_I2S_DATAFORMAT_24B
<>	161:2cc1468da177	1680	* @arg @ref LL_I2S_DATAFORMAT_32B
<>	161:2cc1468da177	1681	* @retval None
<>	161:2cc1468da177	1682	*/
<>	161:2cc1468da177	1683	__STATIC_INLINE void LL_I2S_SetDataFormat(SPI_TypeDef *SPIx, uint32_t DataFormat)
<>	161:2cc1468da177	1684	{
<>	161:2cc1468da177	1685	MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_DATLEN \| SPI_I2SCFGR_CHLEN, DataFormat);
<>	161:2cc1468da177	1686	}
<>	161:2cc1468da177	1687
<>	161:2cc1468da177	1688	/**
<>	161:2cc1468da177	1689	* @brief Get I2S data frame length
<>	161:2cc1468da177	1690	* @rmtoll I2SCFGR DATLEN LL_I2S_GetDataFormat\n
<>	161:2cc1468da177	1691	* I2SCFGR CHLEN LL_I2S_GetDataFormat
<>	161:2cc1468da177	1692	* @param SPIx SPI Instance
<>	161:2cc1468da177	1693	* @retval Returned value can be one of the following values:
<>	161:2cc1468da177	1694	* @arg @ref LL_I2S_DATAFORMAT_16B
<>	161:2cc1468da177	1695	* @arg @ref LL_I2S_DATAFORMAT_16B_EXTENDED
<>	161:2cc1468da177	1696	* @arg @ref LL_I2S_DATAFORMAT_24B
<>	161:2cc1468da177	1697	* @arg @ref LL_I2S_DATAFORMAT_32B
<>	161:2cc1468da177	1698	*/
<>	161:2cc1468da177	1699	__STATIC_INLINE uint32_t LL_I2S_GetDataFormat(SPI_TypeDef *SPIx)
<>	161:2cc1468da177	1700	{
<>	161:2cc1468da177	1701	return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_DATLEN \| SPI_I2SCFGR_CHLEN));
<>	161:2cc1468da177	1702	}
<>	161:2cc1468da177	1703
<>	161:2cc1468da177	1704	/**
<>	161:2cc1468da177	1705	* @brief Set I2S clock polarity
<>	161:2cc1468da177	1706	* @rmtoll I2SCFGR CKPOL LL_I2S_SetClockPolarity
<>	161:2cc1468da177	1707	* @param SPIx SPI Instance
<>	161:2cc1468da177	1708	* @param ClockPolarity This parameter can be one of the following values:
<>	161:2cc1468da177	1709	* @arg @ref LL_I2S_POLARITY_LOW
<>	161:2cc1468da177	1710	* @arg @ref LL_I2S_POLARITY_HIGH
<>	161:2cc1468da177	1711	* @retval None
<>	161:2cc1468da177	1712	*/
<>	161:2cc1468da177	1713	__STATIC_INLINE void LL_I2S_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPolarity)
<>	161:2cc1468da177	1714	{
<>	161:2cc1468da177	1715	SET_BIT(SPIx->I2SCFGR, ClockPolarity);
<>	161:2cc1468da177	1716	}
<>	161:2cc1468da177	1717
<>	161:2cc1468da177	1718	/**
<>	161:2cc1468da177	1719	* @brief Get I2S clock polarity
<>	161:2cc1468da177	1720	* @rmtoll I2SCFGR CKPOL LL_I2S_GetClockPolarity
<>	161:2cc1468da177	1721	* @param SPIx SPI Instance
<>	161:2cc1468da177	1722	* @retval Returned value can be one of the following values:
<>	161:2cc1468da177	1723	* @arg @ref LL_I2S_POLARITY_LOW
<>	161:2cc1468da177	1724	* @arg @ref LL_I2S_POLARITY_HIGH
<>	161:2cc1468da177	1725	*/
<>	161:2cc1468da177	1726	__STATIC_INLINE uint32_t LL_I2S_GetClockPolarity(SPI_TypeDef *SPIx)
<>	161:2cc1468da177	1727	{
<>	161:2cc1468da177	1728	return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_CKPOL));
<>	161:2cc1468da177	1729	}
<>	161:2cc1468da177	1730
<>	161:2cc1468da177	1731	/**
<>	161:2cc1468da177	1732	* @brief Set I2S standard protocol
<>	161:2cc1468da177	1733	* @rmtoll I2SCFGR I2SSTD LL_I2S_SetStandard\n
<>	161:2cc1468da177	1734	* I2SCFGR PCMSYNC LL_I2S_SetStandard
<>	161:2cc1468da177	1735	* @param SPIx SPI Instance
<>	161:2cc1468da177	1736	* @param Standard This parameter can be one of the following values:
<>	161:2cc1468da177	1737	* @arg @ref LL_I2S_STANDARD_PHILIPS
<>	161:2cc1468da177	1738	* @arg @ref LL_I2S_STANDARD_MSB
<>	161:2cc1468da177	1739	* @arg @ref LL_I2S_STANDARD_LSB
<>	161:2cc1468da177	1740	* @arg @ref LL_I2S_STANDARD_PCM_SHORT
<>	161:2cc1468da177	1741	* @arg @ref LL_I2S_STANDARD_PCM_LONG
<>	161:2cc1468da177	1742	* @retval None
<>	161:2cc1468da177	1743	*/
<>	161:2cc1468da177	1744	__STATIC_INLINE void LL_I2S_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard)
<>	161:2cc1468da177	1745	{
<>	161:2cc1468da177	1746	MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_I2SSTD \| SPI_I2SCFGR_PCMSYNC, Standard);
<>	161:2cc1468da177	1747	}
<>	161:2cc1468da177	1748
<>	161:2cc1468da177	1749	/**
<>	161:2cc1468da177	1750	* @brief Get I2S standard protocol
<>	161:2cc1468da177	1751	* @rmtoll I2SCFGR I2SSTD LL_I2S_GetStandard\n
<>	161:2cc1468da177	1752	* I2SCFGR PCMSYNC LL_I2S_GetStandard
<>	161:2cc1468da177	1753	* @param SPIx SPI Instance
<>	161:2cc1468da177	1754	* @retval Returned value can be one of the following values:
<>	161:2cc1468da177	1755	* @arg @ref LL_I2S_STANDARD_PHILIPS
<>	161:2cc1468da177	1756	* @arg @ref LL_I2S_STANDARD_MSB
<>	161:2cc1468da177	1757	* @arg @ref LL_I2S_STANDARD_LSB
<>	161:2cc1468da177	1758	* @arg @ref LL_I2S_STANDARD_PCM_SHORT
<>	161:2cc1468da177	1759	* @arg @ref LL_I2S_STANDARD_PCM_LONG
<>	161:2cc1468da177	1760	*/
<>	161:2cc1468da177	1761	__STATIC_INLINE uint32_t LL_I2S_GetStandard(SPI_TypeDef *SPIx)
<>	161:2cc1468da177	1762	{
<>	161:2cc1468da177	1763	return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SSTD \| SPI_I2SCFGR_PCMSYNC));
<>	161:2cc1468da177	1764	}
<>	161:2cc1468da177	1765
<>	161:2cc1468da177	1766	/**
<>	161:2cc1468da177	1767	* @brief Set I2S transfer mode
<>	161:2cc1468da177	1768	* @rmtoll I2SCFGR I2SCFG LL_I2S_SetTransferMode
<>	161:2cc1468da177	1769	* @param SPIx SPI Instance
<>	161:2cc1468da177	1770	* @param Mode This parameter can be one of the following values:
<>	161:2cc1468da177	1771	* @arg @ref LL_I2S_MODE_SLAVE_TX
<>	161:2cc1468da177	1772	* @arg @ref LL_I2S_MODE_SLAVE_RX
<>	161:2cc1468da177	1773	* @arg @ref LL_I2S_MODE_MASTER_TX
<>	161:2cc1468da177	1774	* @arg @ref LL_I2S_MODE_MASTER_RX
<>	161:2cc1468da177	1775	* @retval None
<>	161:2cc1468da177	1776	*/
<>	161:2cc1468da177	1777	__STATIC_INLINE void LL_I2S_SetTransferMode(SPI_TypeDef *SPIx, uint32_t Mode)
<>	161:2cc1468da177	1778	{
<>	161:2cc1468da177	1779	MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_I2SCFG, Mode);
<>	161:2cc1468da177	1780	}
<>	161:2cc1468da177	1781
<>	161:2cc1468da177	1782	/**
<>	161:2cc1468da177	1783	* @brief Get I2S transfer mode
<>	161:2cc1468da177	1784	* @rmtoll I2SCFGR I2SCFG LL_I2S_GetTransferMode
<>	161:2cc1468da177	1785	* @param SPIx SPI Instance
<>	161:2cc1468da177	1786	* @retval Returned value can be one of the following values:
<>	161:2cc1468da177	1787	* @arg @ref LL_I2S_MODE_SLAVE_TX
<>	161:2cc1468da177	1788	* @arg @ref LL_I2S_MODE_SLAVE_RX
<>	161:2cc1468da177	1789	* @arg @ref LL_I2S_MODE_MASTER_TX
<>	161:2cc1468da177	1790	* @arg @ref LL_I2S_MODE_MASTER_RX
<>	161:2cc1468da177	1791	*/
<>	161:2cc1468da177	1792	__STATIC_INLINE uint32_t LL_I2S_GetTransferMode(SPI_TypeDef *SPIx)
<>	161:2cc1468da177	1793	{
<>	161:2cc1468da177	1794	return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SCFG));
<>	161:2cc1468da177	1795	}
<>	161:2cc1468da177	1796
<>	161:2cc1468da177	1797	/**
<>	161:2cc1468da177	1798	* @brief Set I2S linear prescaler
<>	161:2cc1468da177	1799	* @rmtoll I2SPR I2SDIV LL_I2S_SetPrescalerLinear
<>	161:2cc1468da177	1800	* @param SPIx SPI Instance
<>	161:2cc1468da177	1801	* @param PrescalerLinear Value between Min_Data=0x02 and Max_Data=0xFF
<>	161:2cc1468da177	1802	* @retval None
<>	161:2cc1468da177	1803	*/
<>	161:2cc1468da177	1804	__STATIC_INLINE void LL_I2S_SetPrescalerLinear(SPI_TypeDef *SPIx, uint8_t PrescalerLinear)
<>	161:2cc1468da177	1805	{
<>	161:2cc1468da177	1806	MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_I2SDIV, PrescalerLinear);
<>	161:2cc1468da177	1807	}
<>	161:2cc1468da177	1808
<>	161:2cc1468da177	1809	/**
<>	161:2cc1468da177	1810	* @brief Get I2S linear prescaler
<>	161:2cc1468da177	1811	* @rmtoll I2SPR I2SDIV LL_I2S_GetPrescalerLinear
<>	161:2cc1468da177	1812	* @param SPIx SPI Instance
<>	161:2cc1468da177	1813	* @retval PrescalerLinear Value between Min_Data=0x02 and Max_Data=0xFF
<>	161:2cc1468da177	1814	*/
<>	161:2cc1468da177	1815	__STATIC_INLINE uint32_t LL_I2S_GetPrescalerLinear(SPI_TypeDef *SPIx)
<>	161:2cc1468da177	1816	{
<>	161:2cc1468da177	1817	return (uint32_t)(READ_BIT(SPIx->I2SPR, SPI_I2SPR_I2SDIV));
<>	161:2cc1468da177	1818	}
<>	161:2cc1468da177	1819
<>	161:2cc1468da177	1820	/**
<>	161:2cc1468da177	1821	* @brief Set I2S parity prescaler
<>	161:2cc1468da177	1822	* @rmtoll I2SPR ODD LL_I2S_SetPrescalerParity
<>	161:2cc1468da177	1823	* @param SPIx SPI Instance
<>	161:2cc1468da177	1824	* @param PrescalerParity This parameter can be one of the following values:
<>	161:2cc1468da177	1825	* @arg @ref LL_I2S_PRESCALER_PARITY_EVEN
<>	161:2cc1468da177	1826	* @arg @ref LL_I2S_PRESCALER_PARITY_ODD
<>	161:2cc1468da177	1827	* @retval None
<>	161:2cc1468da177	1828	*/
<>	161:2cc1468da177	1829	__STATIC_INLINE void LL_I2S_SetPrescalerParity(SPI_TypeDef *SPIx, uint32_t PrescalerParity)
<>	161:2cc1468da177	1830	{
<>	161:2cc1468da177	1831	MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_ODD, PrescalerParity << 8U);
<>	161:2cc1468da177	1832	}
<>	161:2cc1468da177	1833
<>	161:2cc1468da177	1834	/**
<>	161:2cc1468da177	1835	* @brief Get I2S parity prescaler
<>	161:2cc1468da177	1836	* @rmtoll I2SPR ODD LL_I2S_GetPrescalerParity
<>	161:2cc1468da177	1837	* @param SPIx SPI Instance
<>	161:2cc1468da177	1838	* @retval Returned value can be one of the following values:
<>	161:2cc1468da177	1839	* @arg @ref LL_I2S_PRESCALER_PARITY_EVEN
<>	161:2cc1468da177	1840	* @arg @ref LL_I2S_PRESCALER_PARITY_ODD
<>	161:2cc1468da177	1841	*/
<>	161:2cc1468da177	1842	__STATIC_INLINE uint32_t LL_I2S_GetPrescalerParity(SPI_TypeDef *SPIx)
<>	161:2cc1468da177	1843	{
<>	161:2cc1468da177	1844	return (uint32_t)(READ_BIT(SPIx->I2SPR, SPI_I2SPR_ODD) >> 8U);
<>	161:2cc1468da177	1845	}
<>	161:2cc1468da177	1846
<>	161:2cc1468da177	1847	/**
<>	161:2cc1468da177	1848	* @brief Enable the master clock ouput (Pin MCK)
<>	161:2cc1468da177	1849	* @rmtoll I2SPR MCKOE LL_I2S_EnableMasterClock
<>	161:2cc1468da177	1850	* @param SPIx SPI Instance
<>	161:2cc1468da177	1851	* @retval None
<>	161:2cc1468da177	1852	*/
<>	161:2cc1468da177	1853	__STATIC_INLINE void LL_I2S_EnableMasterClock(SPI_TypeDef *SPIx)
<>	161:2cc1468da177	1854	{
<>	161:2cc1468da177	1855	SET_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE);
<>	161:2cc1468da177	1856	}
<>	161:2cc1468da177	1857
<>	161:2cc1468da177	1858	/**
<>	161:2cc1468da177	1859	* @brief Disable the master clock ouput (Pin MCK)
<>	161:2cc1468da177	1860	* @rmtoll I2SPR MCKOE LL_I2S_DisableMasterClock
<>	161:2cc1468da177	1861	* @param SPIx SPI Instance
<>	161:2cc1468da177	1862	* @retval None
<>	161:2cc1468da177	1863	*/
<>	161:2cc1468da177	1864	__STATIC_INLINE void LL_I2S_DisableMasterClock(SPI_TypeDef *SPIx)
<>	161:2cc1468da177	1865	{
<>	161:2cc1468da177	1866	CLEAR_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE);
<>	161:2cc1468da177	1867	}
<>	161:2cc1468da177	1868
<>	161:2cc1468da177	1869	/**
<>	161:2cc1468da177	1870	* @brief Check if the master clock ouput (Pin MCK) is enabled
<>	161:2cc1468da177	1871	* @rmtoll I2SPR MCKOE LL_I2S_IsEnabledMasterClock
<>	161:2cc1468da177	1872	* @param SPIx SPI Instance
<>	161:2cc1468da177	1873	* @retval State of bit (1 or 0).
<>	161:2cc1468da177	1874	*/
<>	161:2cc1468da177	1875	__STATIC_INLINE uint32_t LL_I2S_IsEnabledMasterClock(SPI_TypeDef *SPIx)
<>	161:2cc1468da177	1876	{
<>	161:2cc1468da177	1877	return (READ_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE) == (SPI_I2SPR_MCKOE));
<>	161:2cc1468da177	1878	}
<>	161:2cc1468da177	1879
<>	161:2cc1468da177	1880	#if defined(SPI_I2SCFGR_ASTRTEN)
<>	161:2cc1468da177	1881	/**
<>	161:2cc1468da177	1882	* @brief Enable asynchronous start
<>	161:2cc1468da177	1883	* @rmtoll I2SCFGR ASTRTEN LL_I2S_EnableAsyncStart
<>	161:2cc1468da177	1884	* @param SPIx SPI Instance
<>	161:2cc1468da177	1885	* @retval None
<>	161:2cc1468da177	1886	*/
<>	161:2cc1468da177	1887	__STATIC_INLINE void LL_I2S_EnableAsyncStart(SPI_TypeDef *SPIx)
<>	161:2cc1468da177	1888	{
<>	161:2cc1468da177	1889	SET_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_ASTRTEN);
<>	161:2cc1468da177	1890	}
<>	161:2cc1468da177	1891
<>	161:2cc1468da177	1892	/**
<>	161:2cc1468da177	1893	* @brief Disable asynchronous start
<>	161:2cc1468da177	1894	* @rmtoll I2SCFGR ASTRTEN LL_I2S_DisableAsyncStart
<>	161:2cc1468da177	1895	* @param SPIx SPI Instance
<>	161:2cc1468da177	1896	* @retval None
<>	161:2cc1468da177	1897	*/
<>	161:2cc1468da177	1898	__STATIC_INLINE void LL_I2S_DisableAsyncStart(SPI_TypeDef *SPIx)
<>	161:2cc1468da177	1899	{
<>	161:2cc1468da177	1900	CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_ASTRTEN);
<>	161:2cc1468da177	1901	}
<>	161:2cc1468da177	1902
<>	161:2cc1468da177	1903	/**
<>	161:2cc1468da177	1904	* @brief Check if asynchronous start is enabled
<>	161:2cc1468da177	1905	* @rmtoll I2SCFGR ASTRTEN LL_I2S_IsEnabledAsyncStart
<>	161:2cc1468da177	1906	* @param SPIx SPI Instance
<>	161:2cc1468da177	1907	* @retval State of bit (1 or 0).
<>	161:2cc1468da177	1908	*/
<>	161:2cc1468da177	1909	__STATIC_INLINE uint32_t LL_I2S_IsEnabledAsyncStart(SPI_TypeDef *SPIx)
<>	161:2cc1468da177	1910	{
<>	161:2cc1468da177	1911	return (READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_ASTRTEN) == (SPI_I2SCFGR_ASTRTEN));
<>	161:2cc1468da177	1912	}
<>	161:2cc1468da177	1913	#endif /* SPI_I2SCFGR_ASTRTEN */
<>	161:2cc1468da177	1914
<>	161:2cc1468da177	1915	/**
<>	161:2cc1468da177	1916	* @}
<>	161:2cc1468da177	1917	*/
<>	161:2cc1468da177	1918
<>	161:2cc1468da177	1919	/** @defgroup I2S_LL_EF_FLAG FLAG Management
<>	161:2cc1468da177	1920	* @{
<>	161:2cc1468da177	1921	*/
<>	161:2cc1468da177	1922
<>	161:2cc1468da177	1923	/**
<>	161:2cc1468da177	1924	* @brief Check if Rx buffer is not empty
<>	161:2cc1468da177	1925	* @rmtoll SR RXNE LL_I2S_IsActiveFlag_RXNE
<>	161:2cc1468da177	1926	* @param SPIx SPI Instance
<>	161:2cc1468da177	1927	* @retval State of bit (1 or 0).
<>	161:2cc1468da177	1928	*/
<>	161:2cc1468da177	1929	__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_RXNE(SPI_TypeDef *SPIx)
<>	161:2cc1468da177	1930	{
<>	161:2cc1468da177	1931	return LL_SPI_IsActiveFlag_RXNE(SPIx);
<>	161:2cc1468da177	1932	}
<>	161:2cc1468da177	1933
<>	161:2cc1468da177	1934	/**
<>	161:2cc1468da177	1935	* @brief Check if Tx buffer is empty
<>	161:2cc1468da177	1936	* @rmtoll SR TXE LL_I2S_IsActiveFlag_TXE
<>	161:2cc1468da177	1937	* @param SPIx SPI Instance
<>	161:2cc1468da177	1938	* @retval State of bit (1 or 0).
<>	161:2cc1468da177	1939	*/
<>	161:2cc1468da177	1940	__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_TXE(SPI_TypeDef *SPIx)
<>	161:2cc1468da177	1941	{
<>	161:2cc1468da177	1942	return LL_SPI_IsActiveFlag_TXE(SPIx);
<>	161:2cc1468da177	1943	}
<>	161:2cc1468da177	1944
<>	161:2cc1468da177	1945	/**
<>	161:2cc1468da177	1946	* @brief Get busy flag
<>	161:2cc1468da177	1947	* @rmtoll SR BSY LL_I2S_IsActiveFlag_BSY
<>	161:2cc1468da177	1948	* @param SPIx SPI Instance
<>	161:2cc1468da177	1949	* @retval State of bit (1 or 0).
<>	161:2cc1468da177	1950	*/
<>	161:2cc1468da177	1951	__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_BSY(SPI_TypeDef *SPIx)
<>	161:2cc1468da177	1952	{
<>	161:2cc1468da177	1953	return LL_SPI_IsActiveFlag_BSY(SPIx);
<>	161:2cc1468da177	1954	}
<>	161:2cc1468da177	1955
<>	161:2cc1468da177	1956	/**
<>	161:2cc1468da177	1957	* @brief Get overrun error flag
<>	161:2cc1468da177	1958	* @rmtoll SR OVR LL_I2S_IsActiveFlag_OVR
<>	161:2cc1468da177	1959	* @param SPIx SPI Instance
<>	161:2cc1468da177	1960	* @retval State of bit (1 or 0).
<>	161:2cc1468da177	1961	*/
<>	161:2cc1468da177	1962	__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_OVR(SPI_TypeDef *SPIx)
<>	161:2cc1468da177	1963	{
<>	161:2cc1468da177	1964	return LL_SPI_IsActiveFlag_OVR(SPIx);
<>	161:2cc1468da177	1965	}
<>	161:2cc1468da177	1966
<>	161:2cc1468da177	1967	/**
<>	161:2cc1468da177	1968	* @brief Get underrun error flag
<>	161:2cc1468da177	1969	* @rmtoll SR UDR LL_I2S_IsActiveFlag_UDR
<>	161:2cc1468da177	1970	* @param SPIx SPI Instance
<>	161:2cc1468da177	1971	* @retval State of bit (1 or 0).
<>	161:2cc1468da177	1972	*/
<>	161:2cc1468da177	1973	__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_UDR(SPI_TypeDef *SPIx)
<>	161:2cc1468da177	1974	{
<>	161:2cc1468da177	1975	return (READ_BIT(SPIx->SR, SPI_SR_UDR) == (SPI_SR_UDR));
<>	161:2cc1468da177	1976	}
<>	161:2cc1468da177	1977
<>	161:2cc1468da177	1978	/**
<>	161:2cc1468da177	1979	* @brief Get frame format error flag
<>	161:2cc1468da177	1980	* @rmtoll SR FRE LL_I2S_IsActiveFlag_FRE
<>	161:2cc1468da177	1981	* @param SPIx SPI Instance
<>	161:2cc1468da177	1982	* @retval State of bit (1 or 0).
<>	161:2cc1468da177	1983	*/
<>	161:2cc1468da177	1984	__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_FRE(SPI_TypeDef *SPIx)
<>	161:2cc1468da177	1985	{
<>	161:2cc1468da177	1986	return LL_SPI_IsActiveFlag_FRE(SPIx);
<>	161:2cc1468da177	1987	}
<>	161:2cc1468da177	1988
<>	161:2cc1468da177	1989	/**
<>	161:2cc1468da177	1990	* @brief Get channel side flag.
<>	161:2cc1468da177	1991	* @note 0: Channel Left has to be transmitted or has been received\n
<>	161:2cc1468da177	1992	* 1: Channel Right has to be transmitted or has been received\n
<>	161:2cc1468da177	1993	* It has no significance in PCM mode.
<>	161:2cc1468da177	1994	* @rmtoll SR CHSIDE LL_I2S_IsActiveFlag_CHSIDE
<>	161:2cc1468da177	1995	* @param SPIx SPI Instance
<>	161:2cc1468da177	1996	* @retval State of bit (1 or 0).
<>	161:2cc1468da177	1997	*/
<>	161:2cc1468da177	1998	__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_CHSIDE(SPI_TypeDef *SPIx)
<>	161:2cc1468da177	1999	{
<>	161:2cc1468da177	2000	return (READ_BIT(SPIx->SR, SPI_SR_CHSIDE) == (SPI_SR_CHSIDE));
<>	161:2cc1468da177	2001	}
<>	161:2cc1468da177	2002
<>	161:2cc1468da177	2003	/**
<>	161:2cc1468da177	2004	* @brief Clear overrun error flag
<>	161:2cc1468da177	2005	* @rmtoll SR OVR LL_I2S_ClearFlag_OVR
<>	161:2cc1468da177	2006	* @param SPIx SPI Instance
<>	161:2cc1468da177	2007	* @retval None
<>	161:2cc1468da177	2008	*/
<>	161:2cc1468da177	2009	__STATIC_INLINE void LL_I2S_ClearFlag_OVR(SPI_TypeDef *SPIx)
<>	161:2cc1468da177	2010	{
<>	161:2cc1468da177	2011	LL_SPI_ClearFlag_OVR(SPIx);
<>	161:2cc1468da177	2012	}
<>	161:2cc1468da177	2013
<>	161:2cc1468da177	2014	/**
<>	161:2cc1468da177	2015	* @brief Clear underrun error flag
<>	161:2cc1468da177	2016	* @rmtoll SR UDR LL_I2S_ClearFlag_UDR
<>	161:2cc1468da177	2017	* @param SPIx SPI Instance
<>	161:2cc1468da177	2018	* @retval None
<>	161:2cc1468da177	2019	*/
<>	161:2cc1468da177	2020	__STATIC_INLINE void LL_I2S_ClearFlag_UDR(SPI_TypeDef *SPIx)
<>	161:2cc1468da177	2021	{
<>	161:2cc1468da177	2022	__IO uint32_t tmpreg;
<>	161:2cc1468da177	2023	tmpreg = SPIx->SR;
<>	161:2cc1468da177	2024	(void)tmpreg;
<>	161:2cc1468da177	2025	}
<>	161:2cc1468da177	2026
<>	161:2cc1468da177	2027	/**
<>	161:2cc1468da177	2028	* @brief Clear frame format error flag
<>	161:2cc1468da177	2029	* @rmtoll SR FRE LL_I2S_ClearFlag_FRE
<>	161:2cc1468da177	2030	* @param SPIx SPI Instance
<>	161:2cc1468da177	2031	* @retval None
<>	161:2cc1468da177	2032	*/
<>	161:2cc1468da177	2033	__STATIC_INLINE void LL_I2S_ClearFlag_FRE(SPI_TypeDef *SPIx)
<>	161:2cc1468da177	2034	{
<>	161:2cc1468da177	2035	LL_SPI_ClearFlag_FRE(SPIx);
<>	161:2cc1468da177	2036	}
<>	161:2cc1468da177	2037
<>	161:2cc1468da177	2038	/**
<>	161:2cc1468da177	2039	* @}
<>	161:2cc1468da177	2040	*/
<>	161:2cc1468da177	2041
<>	161:2cc1468da177	2042	/** @defgroup I2S_LL_EF_IT Interrupt Management
<>	161:2cc1468da177	2043	* @{
<>	161:2cc1468da177	2044	*/
<>	161:2cc1468da177	2045
<>	161:2cc1468da177	2046	/**
<>	161:2cc1468da177	2047	* @brief Enable error IT
<>	161:2cc1468da177	2048	* @note This bit controls the generation of an interrupt when an error condition occurs (OVR, UDR and FRE in I2S mode).
<>	161:2cc1468da177	2049	* @rmtoll CR2 ERRIE LL_I2S_EnableIT_ERR
<>	161:2cc1468da177	2050	* @param SPIx SPI Instance
<>	161:2cc1468da177	2051	* @retval None
<>	161:2cc1468da177	2052	*/
<>	161:2cc1468da177	2053	__STATIC_INLINE void LL_I2S_EnableIT_ERR(SPI_TypeDef *SPIx)
<>	161:2cc1468da177	2054	{
<>	161:2cc1468da177	2055	LL_SPI_EnableIT_ERR(SPIx);
<>	161:2cc1468da177	2056	}
<>	161:2cc1468da177	2057
<>	161:2cc1468da177	2058	/**
<>	161:2cc1468da177	2059	* @brief Enable Rx buffer not empty IT
<>	161:2cc1468da177	2060	* @rmtoll CR2 RXNEIE LL_I2S_EnableIT_RXNE
<>	161:2cc1468da177	2061	* @param SPIx SPI Instance
<>	161:2cc1468da177	2062	* @retval None
<>	161:2cc1468da177	2063	*/
<>	161:2cc1468da177	2064	__STATIC_INLINE void LL_I2S_EnableIT_RXNE(SPI_TypeDef *SPIx)
<>	161:2cc1468da177	2065	{
<>	161:2cc1468da177	2066	LL_SPI_EnableIT_RXNE(SPIx);
<>	161:2cc1468da177	2067	}
<>	161:2cc1468da177	2068
<>	161:2cc1468da177	2069	/**
<>	161:2cc1468da177	2070	* @brief Enable Tx buffer empty IT
<>	161:2cc1468da177	2071	* @rmtoll CR2 TXEIE LL_I2S_EnableIT_TXE
<>	161:2cc1468da177	2072	* @param SPIx SPI Instance
<>	161:2cc1468da177	2073	* @retval None
<>	161:2cc1468da177	2074	*/
<>	161:2cc1468da177	2075	__STATIC_INLINE void LL_I2S_EnableIT_TXE(SPI_TypeDef *SPIx)
<>	161:2cc1468da177	2076	{
<>	161:2cc1468da177	2077	LL_SPI_EnableIT_TXE(SPIx);
<>	161:2cc1468da177	2078	}
<>	161:2cc1468da177	2079
<>	161:2cc1468da177	2080	/**
<>	161:2cc1468da177	2081	* @brief Disable error IT
<>	161:2cc1468da177	2082	* @note This bit controls the generation of an interrupt when an error condition occurs (OVR, UDR and FRE in I2S mode).
<>	161:2cc1468da177	2083	* @rmtoll CR2 ERRIE LL_I2S_DisableIT_ERR
<>	161:2cc1468da177	2084	* @param SPIx SPI Instance
<>	161:2cc1468da177	2085	* @retval None
<>	161:2cc1468da177	2086	*/
<>	161:2cc1468da177	2087	__STATIC_INLINE void LL_I2S_DisableIT_ERR(SPI_TypeDef *SPIx)
<>	161:2cc1468da177	2088	{
<>	161:2cc1468da177	2089	LL_SPI_DisableIT_ERR(SPIx);
<>	161:2cc1468da177	2090	}
<>	161:2cc1468da177	2091
<>	161:2cc1468da177	2092	/**
<>	161:2cc1468da177	2093	* @brief Disable Rx buffer not empty IT
<>	161:2cc1468da177	2094	* @rmtoll CR2 RXNEIE LL_I2S_DisableIT_RXNE
<>	161:2cc1468da177	2095	* @param SPIx SPI Instance
<>	161:2cc1468da177	2096	* @retval None
<>	161:2cc1468da177	2097	*/
<>	161:2cc1468da177	2098	__STATIC_INLINE void LL_I2S_DisableIT_RXNE(SPI_TypeDef *SPIx)
<>	161:2cc1468da177	2099	{
<>	161:2cc1468da177	2100	LL_SPI_DisableIT_RXNE(SPIx);
<>	161:2cc1468da177	2101	}
<>	161:2cc1468da177	2102
<>	161:2cc1468da177	2103	/**
<>	161:2cc1468da177	2104	* @brief Disable Tx buffer empty IT
<>	161:2cc1468da177	2105	* @rmtoll CR2 TXEIE LL_I2S_DisableIT_TXE
<>	161:2cc1468da177	2106	* @param SPIx SPI Instance
<>	161:2cc1468da177	2107	* @retval None
<>	161:2cc1468da177	2108	*/
<>	161:2cc1468da177	2109	__STATIC_INLINE void LL_I2S_DisableIT_TXE(SPI_TypeDef *SPIx)
<>	161:2cc1468da177	2110	{
<>	161:2cc1468da177	2111	LL_SPI_DisableIT_TXE(SPIx);
<>	161:2cc1468da177	2112	}
<>	161:2cc1468da177	2113
<>	161:2cc1468da177	2114	/**
<>	161:2cc1468da177	2115	* @brief Check if ERR IT is enabled
<>	161:2cc1468da177	2116	* @rmtoll CR2 ERRIE LL_I2S_IsEnabledIT_ERR
<>	161:2cc1468da177	2117	* @param SPIx SPI Instance
<>	161:2cc1468da177	2118	* @retval State of bit (1 or 0).
<>	161:2cc1468da177	2119	*/
<>	161:2cc1468da177	2120	__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_ERR(SPI_TypeDef *SPIx)
<>	161:2cc1468da177	2121	{
<>	161:2cc1468da177	2122	return LL_SPI_IsEnabledIT_ERR(SPIx);
<>	161:2cc1468da177	2123	}
<>	161:2cc1468da177	2124
<>	161:2cc1468da177	2125	/**
<>	161:2cc1468da177	2126	* @brief Check if RXNE IT is enabled
<>	161:2cc1468da177	2127	* @rmtoll CR2 RXNEIE LL_I2S_IsEnabledIT_RXNE
<>	161:2cc1468da177	2128	* @param SPIx SPI Instance
<>	161:2cc1468da177	2129	* @retval State of bit (1 or 0).
<>	161:2cc1468da177	2130	*/
<>	161:2cc1468da177	2131	__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_RXNE(SPI_TypeDef *SPIx)
<>	161:2cc1468da177	2132	{
<>	161:2cc1468da177	2133	return LL_SPI_IsEnabledIT_RXNE(SPIx);
<>	161:2cc1468da177	2134	}
<>	161:2cc1468da177	2135
<>	161:2cc1468da177	2136	/**
<>	161:2cc1468da177	2137	* @brief Check if TXE IT is enabled
<>	161:2cc1468da177	2138	* @rmtoll CR2 TXEIE LL_I2S_IsEnabledIT_TXE
<>	161:2cc1468da177	2139	* @param SPIx SPI Instance
<>	161:2cc1468da177	2140	* @retval State of bit (1 or 0).
<>	161:2cc1468da177	2141	*/
<>	161:2cc1468da177	2142	__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_TXE(SPI_TypeDef *SPIx)
<>	161:2cc1468da177	2143	{
<>	161:2cc1468da177	2144	return LL_SPI_IsEnabledIT_TXE(SPIx);
<>	161:2cc1468da177	2145	}
<>	161:2cc1468da177	2146
<>	161:2cc1468da177	2147	/**
<>	161:2cc1468da177	2148	* @}
<>	161:2cc1468da177	2149	*/
<>	161:2cc1468da177	2150
<>	161:2cc1468da177	2151	/** @defgroup I2S_LL_EF_DMA DMA Management
<>	161:2cc1468da177	2152	* @{
<>	161:2cc1468da177	2153	*/
<>	161:2cc1468da177	2154
<>	161:2cc1468da177	2155	/**
<>	161:2cc1468da177	2156	* @brief Enable DMA Rx
<>	161:2cc1468da177	2157	* @rmtoll CR2 RXDMAEN LL_I2S_EnableDMAReq_RX
<>	161:2cc1468da177	2158	* @param SPIx SPI Instance
<>	161:2cc1468da177	2159	* @retval None
<>	161:2cc1468da177	2160	*/
<>	161:2cc1468da177	2161	__STATIC_INLINE void LL_I2S_EnableDMAReq_RX(SPI_TypeDef *SPIx)
<>	161:2cc1468da177	2162	{
<>	161:2cc1468da177	2163	LL_SPI_EnableDMAReq_RX(SPIx);
<>	161:2cc1468da177	2164	}
<>	161:2cc1468da177	2165
<>	161:2cc1468da177	2166	/**
<>	161:2cc1468da177	2167	* @brief Disable DMA Rx
<>	161:2cc1468da177	2168	* @rmtoll CR2 RXDMAEN LL_I2S_DisableDMAReq_RX
<>	161:2cc1468da177	2169	* @param SPIx SPI Instance
<>	161:2cc1468da177	2170	* @retval None
<>	161:2cc1468da177	2171	*/
<>	161:2cc1468da177	2172	__STATIC_INLINE void LL_I2S_DisableDMAReq_RX(SPI_TypeDef *SPIx)
<>	161:2cc1468da177	2173	{
<>	161:2cc1468da177	2174	LL_SPI_DisableDMAReq_RX(SPIx);
<>	161:2cc1468da177	2175	}
<>	161:2cc1468da177	2176
<>	161:2cc1468da177	2177	/**
<>	161:2cc1468da177	2178	* @brief Check if DMA Rx is enabled
<>	161:2cc1468da177	2179	* @rmtoll CR2 RXDMAEN LL_I2S_IsEnabledDMAReq_RX
<>	161:2cc1468da177	2180	* @param SPIx SPI Instance
<>	161:2cc1468da177	2181	* @retval State of bit (1 or 0).
<>	161:2cc1468da177	2182	*/
<>	161:2cc1468da177	2183	__STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx)
<>	161:2cc1468da177	2184	{
<>	161:2cc1468da177	2185	return LL_SPI_IsEnabledDMAReq_RX(SPIx);
<>	161:2cc1468da177	2186	}
<>	161:2cc1468da177	2187
<>	161:2cc1468da177	2188	/**
<>	161:2cc1468da177	2189	* @brief Enable DMA Tx
<>	161:2cc1468da177	2190	* @rmtoll CR2 TXDMAEN LL_I2S_EnableDMAReq_TX
<>	161:2cc1468da177	2191	* @param SPIx SPI Instance
<>	161:2cc1468da177	2192	* @retval None
<>	161:2cc1468da177	2193	*/
<>	161:2cc1468da177	2194	__STATIC_INLINE void LL_I2S_EnableDMAReq_TX(SPI_TypeDef *SPIx)
<>	161:2cc1468da177	2195	{
<>	161:2cc1468da177	2196	LL_SPI_EnableDMAReq_TX(SPIx);
<>	161:2cc1468da177	2197	}
<>	161:2cc1468da177	2198
<>	161:2cc1468da177	2199	/**
<>	161:2cc1468da177	2200	* @brief Disable DMA Tx
<>	161:2cc1468da177	2201	* @rmtoll CR2 TXDMAEN LL_I2S_DisableDMAReq_TX
<>	161:2cc1468da177	2202	* @param SPIx SPI Instance
<>	161:2cc1468da177	2203	* @retval None
<>	161:2cc1468da177	2204	*/
<>	161:2cc1468da177	2205	__STATIC_INLINE void LL_I2S_DisableDMAReq_TX(SPI_TypeDef *SPIx)
<>	161:2cc1468da177	2206	{
<>	161:2cc1468da177	2207	LL_SPI_DisableDMAReq_TX(SPIx);
<>	161:2cc1468da177	2208	}
<>	161:2cc1468da177	2209
<>	161:2cc1468da177	2210	/**
<>	161:2cc1468da177	2211	* @brief Check if DMA Tx is enabled
<>	161:2cc1468da177	2212	* @rmtoll CR2 TXDMAEN LL_I2S_IsEnabledDMAReq_TX
<>	161:2cc1468da177	2213	* @param SPIx SPI Instance
<>	161:2cc1468da177	2214	* @retval State of bit (1 or 0).
<>	161:2cc1468da177	2215	*/
<>	161:2cc1468da177	2216	__STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx)
<>	161:2cc1468da177	2217	{
<>	161:2cc1468da177	2218	return LL_SPI_IsEnabledDMAReq_TX(SPIx);
<>	161:2cc1468da177	2219	}
<>	161:2cc1468da177	2220
<>	161:2cc1468da177	2221	/**
<>	161:2cc1468da177	2222	* @}
<>	161:2cc1468da177	2223	*/
<>	161:2cc1468da177	2224
<>	161:2cc1468da177	2225	/** @defgroup I2S_LL_EF_DATA DATA Management
<>	161:2cc1468da177	2226	* @{
<>	161:2cc1468da177	2227	*/
<>	161:2cc1468da177	2228
<>	161:2cc1468da177	2229	/**
<>	161:2cc1468da177	2230	* @brief Read 16-Bits in data register
<>	161:2cc1468da177	2231	* @rmtoll DR DR LL_I2S_ReceiveData16
<>	161:2cc1468da177	2232	* @param SPIx SPI Instance
<>	161:2cc1468da177	2233	* @retval RxData Value between Min_Data=0x0000 and Max_Data=0xFFFF
<>	161:2cc1468da177	2234	*/
<>	161:2cc1468da177	2235	__STATIC_INLINE uint16_t LL_I2S_ReceiveData16(SPI_TypeDef *SPIx)
<>	161:2cc1468da177	2236	{
<>	161:2cc1468da177	2237	return LL_SPI_ReceiveData16(SPIx);
<>	161:2cc1468da177	2238	}
<>	161:2cc1468da177	2239
<>	161:2cc1468da177	2240	/**
<>	161:2cc1468da177	2241	* @brief Write 16-Bits in data register
<>	161:2cc1468da177	2242	* @rmtoll DR DR LL_I2S_TransmitData16
<>	161:2cc1468da177	2243	* @param SPIx SPI Instance
<>	161:2cc1468da177	2244	* @param TxData Value between Min_Data=0x0000 and Max_Data=0xFFFF
<>	161:2cc1468da177	2245	* @retval None
<>	161:2cc1468da177	2246	*/
<>	161:2cc1468da177	2247	__STATIC_INLINE void LL_I2S_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData)
<>	161:2cc1468da177	2248	{
<>	161:2cc1468da177	2249	LL_SPI_TransmitData16(SPIx, TxData);
<>	161:2cc1468da177	2250	}
<>	161:2cc1468da177	2251
<>	161:2cc1468da177	2252	/**
<>	161:2cc1468da177	2253	* @}
<>	161:2cc1468da177	2254	*/
<>	161:2cc1468da177	2255
<>	161:2cc1468da177	2256	#if defined(USE_FULL_LL_DRIVER)
<>	161:2cc1468da177	2257	/** @defgroup I2S_LL_EF_Init Initialization and de-initialization functions
<>	161:2cc1468da177	2258	* @{
<>	161:2cc1468da177	2259	*/
<>	161:2cc1468da177	2260
<>	161:2cc1468da177	2261	ErrorStatus LL_I2S_DeInit(SPI_TypeDef *SPIx);
<>	161:2cc1468da177	2262	ErrorStatus LL_I2S_Init(SPI_TypeDef SPIx, LL_I2S_InitTypeDef I2S_InitStruct);
<>	161:2cc1468da177	2263	void LL_I2S_StructInit(LL_I2S_InitTypeDef *I2S_InitStruct);
<>	161:2cc1468da177	2264	void LL_I2S_ConfigPrescaler(SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_t PrescalerParity);
<>	161:2cc1468da177	2265
<>	161:2cc1468da177	2266	/**
<>	161:2cc1468da177	2267	* @}
<>	161:2cc1468da177	2268	*/
<>	161:2cc1468da177	2269	#endif /* USE_FULL_LL_DRIVER */
<>	161:2cc1468da177	2270
<>	161:2cc1468da177	2271	/**
<>	161:2cc1468da177	2272	* @}
<>	161:2cc1468da177	2273	*/
<>	161:2cc1468da177	2274
<>	161:2cc1468da177	2275	/**
<>	161:2cc1468da177	2276	* @}
<>	161:2cc1468da177	2277	*/
<>	161:2cc1468da177	2278
<>	161:2cc1468da177	2279	#endif /* defined (SPI1) \|\| defined (SPI2) \|\| defined (SPI3) \|\| defined(SPI4) \|\| defined(SPI5) \|\| defined(SPI6) */
<>	161:2cc1468da177	2280
<>	161:2cc1468da177	2281	/**
<>	161:2cc1468da177	2282	* @}
<>	161:2cc1468da177	2283	*/
<>	161:2cc1468da177	2284
<>	161:2cc1468da177	2285	#ifdef __cplusplus
<>	161:2cc1468da177	2286	}
<>	161:2cc1468da177	2287	#endif
<>	161:2cc1468da177	2288
<>	161:2cc1468da177	2289	#endif /* __STM32F7xx_LL_SPI_H */
<>	161:2cc1468da177	2290
<>	161:2cc1468da177	2291	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/