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targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_flash_ex.c@182:a56a73fd2a6f, 2018-03-20 (annotated)

Committer:
AnnaBridge
Date:
Tue Mar 20 16:56:18 2018 +0000
Revision:
182:a56a73fd2a6f
Parent:
168:9672193075cf 
mbed-dev library. Release version 160

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f7xx_hal_flash_ex.c
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @brief Extended FLASH HAL module driver.
<> 144:ef7eb2e8f9f7 6 * This file provides firmware functions to manage the following
<> 144:ef7eb2e8f9f7 7 * functionalities of the FLASH extension peripheral:
<> 144:ef7eb2e8f9f7 8 * + Extended programming operations functions
<> 144:ef7eb2e8f9f7 9 *
<> 144:ef7eb2e8f9f7 10 @verbatim
<> 144:ef7eb2e8f9f7 11 ==============================================================================
<> 144:ef7eb2e8f9f7 12 ##### Flash Extension features #####
<> 144:ef7eb2e8f9f7 13 ==============================================================================
<> 144:ef7eb2e8f9f7 14
<> 144:ef7eb2e8f9f7 15 [..] Comparing to other previous devices, the FLASH interface for STM32F76xx/STM32F77xx
<> 144:ef7eb2e8f9f7 16 devices contains the following additional features
<> 144:ef7eb2e8f9f7 17
<> 144:ef7eb2e8f9f7 18 (+) Capacity up to 2 Mbyte with dual bank architecture supporting read-while-write
<> 144:ef7eb2e8f9f7 19 capability (RWW)
<> 144:ef7eb2e8f9f7 20 (+) Dual bank memory organization
<> 144:ef7eb2e8f9f7 21 (+) Dual boot mode
<> 144:ef7eb2e8f9f7 22
<> 144:ef7eb2e8f9f7 23 ##### How to use this driver #####
<> 144:ef7eb2e8f9f7 24 ==============================================================================
<> 144:ef7eb2e8f9f7 25 [..] This driver provides functions to configure and program the FLASH memory
<> 144:ef7eb2e8f9f7 26 of all STM32F7xx devices. It includes
<> 144:ef7eb2e8f9f7 27 (#) FLASH Memory Erase functions:
<> 144:ef7eb2e8f9f7 28 (++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and
<> 144:ef7eb2e8f9f7 29 HAL_FLASH_Lock() functions
<> 144:ef7eb2e8f9f7 30 (++) Erase function: Erase sector, erase all sectors
<> 144:ef7eb2e8f9f7 31 (++) There are two modes of erase :
<> 144:ef7eb2e8f9f7 32 (+++) Polling Mode using HAL_FLASHEx_Erase()
<> 144:ef7eb2e8f9f7 33 (+++) Interrupt Mode using HAL_FLASHEx_Erase_IT()
<> 144:ef7eb2e8f9f7 34
<> 144:ef7eb2e8f9f7 35 (#) Option Bytes Programming functions: Use HAL_FLASHEx_OBProgram() to :
<> 144:ef7eb2e8f9f7 36 (++) Set/Reset the write protection
<> 144:ef7eb2e8f9f7 37 (++) Set the Read protection Level
<> 144:ef7eb2e8f9f7 38 (++) Set the BOR level
<> 144:ef7eb2e8f9f7 39 (++) Program the user Option Bytes
<> 144:ef7eb2e8f9f7 40
<> 144:ef7eb2e8f9f7 41 @endverbatim
<> 144:ef7eb2e8f9f7 42 ******************************************************************************
<> 144:ef7eb2e8f9f7 43 * @attention
<> 144:ef7eb2e8f9f7 44 *
AnnaBridge 168:9672193075cf 45 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 46 *
<> 144:ef7eb2e8f9f7 47 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 48 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 49 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 50 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 51 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 52 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 53 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 54 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 55 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 56 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 57 *
<> 144:ef7eb2e8f9f7 58 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 59 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 60 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 61 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 62 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 63 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 64 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 65 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 66 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 67 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 68 *
<> 144:ef7eb2e8f9f7 69 ******************************************************************************
<> 144:ef7eb2e8f9f7 70 */
<> 144:ef7eb2e8f9f7 71
<> 144:ef7eb2e8f9f7 72 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 73 #include "stm32f7xx_hal.h"
<> 144:ef7eb2e8f9f7 74
<> 144:ef7eb2e8f9f7 75 /** @addtogroup STM32F7xx_HAL_Driver
<> 144:ef7eb2e8f9f7 76 * @{
<> 144:ef7eb2e8f9f7 77 */
<> 144:ef7eb2e8f9f7 78
<> 144:ef7eb2e8f9f7 79 /** @defgroup FLASHEx FLASHEx
<> 144:ef7eb2e8f9f7 80 * @brief FLASH HAL Extension module driver
<> 144:ef7eb2e8f9f7 81 * @{
<> 144:ef7eb2e8f9f7 82 */
<> 144:ef7eb2e8f9f7 83
<> 144:ef7eb2e8f9f7 84 #ifdef HAL_FLASH_MODULE_ENABLED
<> 144:ef7eb2e8f9f7 85
<> 144:ef7eb2e8f9f7 86 /* Private typedef -----------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 87 /* Private define ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 88 /** @addtogroup FLASHEx_Private_Constants
<> 144:ef7eb2e8f9f7 89 * @{
<> 144:ef7eb2e8f9f7 90 */
<> 157:ff67d9f36b67 91 #define SECTOR_MASK 0xFFFFFF07U
<> 157:ff67d9f36b67 92 #define FLASH_TIMEOUT_VALUE 50000U/* 50 s */
<> 144:ef7eb2e8f9f7 93 /**
<> 144:ef7eb2e8f9f7 94 * @}
<> 144:ef7eb2e8f9f7 95 */
<> 144:ef7eb2e8f9f7 96
<> 144:ef7eb2e8f9f7 97 /* Private macro -------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 98 /* Private variables ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 99 /** @addtogroup FLASHEx_Private_Variables
<> 144:ef7eb2e8f9f7 100 * @{
<> 144:ef7eb2e8f9f7 101 */
<> 144:ef7eb2e8f9f7 102 extern FLASH_ProcessTypeDef pFlash;
<> 144:ef7eb2e8f9f7 103 /**
<> 144:ef7eb2e8f9f7 104 * @}
<> 144:ef7eb2e8f9f7 105 */
<> 144:ef7eb2e8f9f7 106
<> 144:ef7eb2e8f9f7 107 /* Private function prototypes -----------------------------------------------*/
<> 144:ef7eb2e8f9f7 108 /** @addtogroup FLASHEx_Private_Functions
<> 144:ef7eb2e8f9f7 109 * @{
<> 144:ef7eb2e8f9f7 110 */
<> 144:ef7eb2e8f9f7 111 /* Option bytes control */
<> 144:ef7eb2e8f9f7 112 static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WRPSector);
<> 144:ef7eb2e8f9f7 113 static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WRPSector);
<> 144:ef7eb2e8f9f7 114 static HAL_StatusTypeDef FLASH_OB_RDP_LevelConfig(uint8_t Level);
<> 144:ef7eb2e8f9f7 115 static HAL_StatusTypeDef FLASH_OB_BOR_LevelConfig(uint8_t Level);
<> 144:ef7eb2e8f9f7 116 static HAL_StatusTypeDef FLASH_OB_BootAddressConfig(uint32_t BootOption, uint32_t Address);
<> 144:ef7eb2e8f9f7 117 static uint32_t FLASH_OB_GetUser(void);
<> 144:ef7eb2e8f9f7 118 static uint32_t FLASH_OB_GetWRP(void);
<> 144:ef7eb2e8f9f7 119 static uint8_t FLASH_OB_GetRDP(void);
<> 144:ef7eb2e8f9f7 120 static uint32_t FLASH_OB_GetBOR(void);
<> 144:ef7eb2e8f9f7 121 static uint32_t FLASH_OB_GetBootAddress(uint32_t BootOption);
<> 144:ef7eb2e8f9f7 122
<> 144:ef7eb2e8f9f7 123 #if defined (FLASH_OPTCR_nDBANK)
<> 144:ef7eb2e8f9f7 124 static void FLASH_MassErase(uint8_t VoltageRange, uint32_t Banks);
<> 144:ef7eb2e8f9f7 125 static HAL_StatusTypeDef FLASH_OB_UserConfig(uint32_t Wwdg, uint32_t Iwdg, uint32_t Stop, uint32_t Stdby, uint32_t Iwdgstop, \
<> 144:ef7eb2e8f9f7 126 uint32_t Iwdgstdby, uint32_t NDBank, uint32_t NDBoot);
<> 144:ef7eb2e8f9f7 127 #else
<> 144:ef7eb2e8f9f7 128 static void FLASH_MassErase(uint8_t VoltageRange);
<> 144:ef7eb2e8f9f7 129 static HAL_StatusTypeDef FLASH_OB_UserConfig(uint32_t Wwdg, uint32_t Iwdg, uint32_t Stop, uint32_t Stdby, uint32_t Iwdgstop, uint32_t Iwdgstdby);
<> 144:ef7eb2e8f9f7 130 #endif /* FLASH_OPTCR_nDBANK */
<> 144:ef7eb2e8f9f7 131
<> 161:2cc1468da177 132 #if defined (FLASH_OPTCR2_PCROP)
<> 161:2cc1468da177 133 static HAL_StatusTypeDef FLASH_OB_PCROP_Config(uint32_t PCROPSector);
<> 161:2cc1468da177 134 static HAL_StatusTypeDef FLASH_OB_PCROP_RDP_Config(uint32_t Pcrop_Rdp);
<> 161:2cc1468da177 135 static uint32_t FLASH_OB_GetPCROP(void);
<> 161:2cc1468da177 136 static uint32_t FLASH_OB_GetPCROPRDP(void);
<> 161:2cc1468da177 137 #endif /* FLASH_OPTCR2_PCROP */
<> 161:2cc1468da177 138
<> 144:ef7eb2e8f9f7 139 extern HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout);
<> 144:ef7eb2e8f9f7 140 /**
<> 144:ef7eb2e8f9f7 141 * @}
<> 144:ef7eb2e8f9f7 142 */
<> 144:ef7eb2e8f9f7 143
<> 144:ef7eb2e8f9f7 144 /* Exported functions --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 145 /** @defgroup FLASHEx_Exported_Functions FLASHEx Exported Functions
<> 144:ef7eb2e8f9f7 146 * @{
<> 144:ef7eb2e8f9f7 147 */
<> 144:ef7eb2e8f9f7 148
<> 144:ef7eb2e8f9f7 149 /** @defgroup FLASHEx_Exported_Functions_Group1 Extended IO operation functions
<> 144:ef7eb2e8f9f7 150 * @brief Extended IO operation functions
<> 144:ef7eb2e8f9f7 151 *
<> 144:ef7eb2e8f9f7 152 @verbatim
<> 144:ef7eb2e8f9f7 153 ===============================================================================
<> 144:ef7eb2e8f9f7 154 ##### Extended programming operation functions #####
<> 144:ef7eb2e8f9f7 155 ===============================================================================
<> 144:ef7eb2e8f9f7 156 [..]
<> 144:ef7eb2e8f9f7 157 This subsection provides a set of functions allowing to manage the Extension FLASH
<> 144:ef7eb2e8f9f7 158 programming operations Operations.
<> 144:ef7eb2e8f9f7 159
<> 144:ef7eb2e8f9f7 160 @endverbatim
<> 144:ef7eb2e8f9f7 161 * @{
<> 144:ef7eb2e8f9f7 162 */
<> 144:ef7eb2e8f9f7 163 /**
<> 144:ef7eb2e8f9f7 164 * @brief Perform a mass erase or erase the specified FLASH memory sectors
AnnaBridge 182:a56a73fd2a6f 165 * @param[in] pEraseInit pointer to an FLASH_EraseInitTypeDef structure that
<> 144:ef7eb2e8f9f7 166 * contains the configuration information for the erasing.
<> 144:ef7eb2e8f9f7 167 *
AnnaBridge 182:a56a73fd2a6f 168 * @param[out] SectorError pointer to variable that
<> 144:ef7eb2e8f9f7 169 * contains the configuration information on faulty sector in case of error
<> 144:ef7eb2e8f9f7 170 * (0xFFFFFFFF means that all the sectors have been correctly erased)
<> 144:ef7eb2e8f9f7 171 *
<> 144:ef7eb2e8f9f7 172 * @retval HAL Status
<> 144:ef7eb2e8f9f7 173 */
<> 144:ef7eb2e8f9f7 174 HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *SectorError)
<> 144:ef7eb2e8f9f7 175 {
<> 144:ef7eb2e8f9f7 176 HAL_StatusTypeDef status = HAL_ERROR;
<> 144:ef7eb2e8f9f7 177 uint32_t index = 0;
<> 144:ef7eb2e8f9f7 178
<> 144:ef7eb2e8f9f7 179 /* Process Locked */
<> 144:ef7eb2e8f9f7 180 __HAL_LOCK(&pFlash);
<> 144:ef7eb2e8f9f7 181
<> 144:ef7eb2e8f9f7 182 /* Check the parameters */
<> 144:ef7eb2e8f9f7 183 assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase));
<> 144:ef7eb2e8f9f7 184
<> 144:ef7eb2e8f9f7 185 /* Wait for last operation to be completed */
<> 144:ef7eb2e8f9f7 186 status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
<> 144:ef7eb2e8f9f7 187
<> 144:ef7eb2e8f9f7 188 if(status == HAL_OK)
<> 144:ef7eb2e8f9f7 189 {
<> 144:ef7eb2e8f9f7 190 /*Initialization of SectorError variable*/
<> 144:ef7eb2e8f9f7 191 *SectorError = 0xFFFFFFFFU;
<> 144:ef7eb2e8f9f7 192
<> 144:ef7eb2e8f9f7 193 if(pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE)
<> 144:ef7eb2e8f9f7 194 {
<> 144:ef7eb2e8f9f7 195 /*Mass erase to be done*/
<> 144:ef7eb2e8f9f7 196 #if defined (FLASH_OPTCR_nDBANK)
<> 144:ef7eb2e8f9f7 197 FLASH_MassErase((uint8_t) pEraseInit->VoltageRange, pEraseInit->Banks);
<> 144:ef7eb2e8f9f7 198 #else
<> 144:ef7eb2e8f9f7 199 FLASH_MassErase((uint8_t) pEraseInit->VoltageRange);
<> 144:ef7eb2e8f9f7 200 #endif /* FLASH_OPTCR_nDBANK */
<> 144:ef7eb2e8f9f7 201
<> 144:ef7eb2e8f9f7 202 /* Wait for last operation to be completed */
<> 144:ef7eb2e8f9f7 203 status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
<> 144:ef7eb2e8f9f7 204
<> 144:ef7eb2e8f9f7 205 /* if the erase operation is completed, disable the MER Bit */
<> 144:ef7eb2e8f9f7 206 FLASH->CR &= (~FLASH_MER_BIT);
<> 144:ef7eb2e8f9f7 207 }
<> 144:ef7eb2e8f9f7 208 else
<> 144:ef7eb2e8f9f7 209 {
<> 144:ef7eb2e8f9f7 210 /* Check the parameters */
<> 144:ef7eb2e8f9f7 211 assert_param(IS_FLASH_NBSECTORS(pEraseInit->NbSectors + pEraseInit->Sector));
<> 144:ef7eb2e8f9f7 212
<> 144:ef7eb2e8f9f7 213 /* Erase by sector by sector to be done*/
<> 144:ef7eb2e8f9f7 214 for(index = pEraseInit->Sector; index < (pEraseInit->NbSectors + pEraseInit->Sector); index++)
<> 144:ef7eb2e8f9f7 215 {
<> 144:ef7eb2e8f9f7 216 FLASH_Erase_Sector(index, (uint8_t) pEraseInit->VoltageRange);
<> 144:ef7eb2e8f9f7 217
<> 144:ef7eb2e8f9f7 218 /* Wait for last operation to be completed */
<> 144:ef7eb2e8f9f7 219 status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
<> 144:ef7eb2e8f9f7 220
<> 144:ef7eb2e8f9f7 221 /* If the erase operation is completed, disable the SER Bit and SNB Bits */
<> 144:ef7eb2e8f9f7 222 CLEAR_BIT(FLASH->CR, (FLASH_CR_SER | FLASH_CR_SNB));
<> 144:ef7eb2e8f9f7 223
<> 144:ef7eb2e8f9f7 224 if(status != HAL_OK)
<> 144:ef7eb2e8f9f7 225 {
<> 144:ef7eb2e8f9f7 226 /* In case of error, stop erase procedure and return the faulty sector*/
<> 144:ef7eb2e8f9f7 227 *SectorError = index;
<> 144:ef7eb2e8f9f7 228 break;
<> 144:ef7eb2e8f9f7 229 }
<> 144:ef7eb2e8f9f7 230 }
<> 144:ef7eb2e8f9f7 231 }
<> 144:ef7eb2e8f9f7 232 }
<> 144:ef7eb2e8f9f7 233
<> 144:ef7eb2e8f9f7 234 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 235 __HAL_UNLOCK(&pFlash);
<> 144:ef7eb2e8f9f7 236
<> 144:ef7eb2e8f9f7 237 return status;
<> 144:ef7eb2e8f9f7 238 }
<> 144:ef7eb2e8f9f7 239
<> 144:ef7eb2e8f9f7 240 /**
<> 144:ef7eb2e8f9f7 241 * @brief Perform a mass erase or erase the specified FLASH memory sectors with interrupt enabled
AnnaBridge 182:a56a73fd2a6f 242 * @param pEraseInit pointer to an FLASH_EraseInitTypeDef structure that
<> 144:ef7eb2e8f9f7 243 * contains the configuration information for the erasing.
<> 144:ef7eb2e8f9f7 244 *
<> 144:ef7eb2e8f9f7 245 * @retval HAL Status
<> 144:ef7eb2e8f9f7 246 */
<> 144:ef7eb2e8f9f7 247 HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit)
<> 144:ef7eb2e8f9f7 248 {
<> 144:ef7eb2e8f9f7 249 HAL_StatusTypeDef status = HAL_OK;
<> 144:ef7eb2e8f9f7 250
<> 144:ef7eb2e8f9f7 251 /* Process Locked */
<> 144:ef7eb2e8f9f7 252 __HAL_LOCK(&pFlash);
<> 144:ef7eb2e8f9f7 253
<> 144:ef7eb2e8f9f7 254 /* Check the parameters */
<> 144:ef7eb2e8f9f7 255 assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase));
<> 144:ef7eb2e8f9f7 256
<> 144:ef7eb2e8f9f7 257 /* Enable End of FLASH Operation interrupt */
<> 144:ef7eb2e8f9f7 258 __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP);
<> 144:ef7eb2e8f9f7 259
<> 144:ef7eb2e8f9f7 260 /* Enable Error source interrupt */
<> 144:ef7eb2e8f9f7 261 __HAL_FLASH_ENABLE_IT(FLASH_IT_ERR);
<> 144:ef7eb2e8f9f7 262
<> 144:ef7eb2e8f9f7 263 /* Clear pending flags (if any) */
<> 144:ef7eb2e8f9f7 264 __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP | FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR |\
<> 144:ef7eb2e8f9f7 265 FLASH_FLAG_PGAERR | FLASH_FLAG_PGPERR| FLASH_FLAG_ERSERR);
<> 144:ef7eb2e8f9f7 266
<> 144:ef7eb2e8f9f7 267 if(pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE)
<> 144:ef7eb2e8f9f7 268 {
<> 144:ef7eb2e8f9f7 269 /*Mass erase to be done*/
<> 144:ef7eb2e8f9f7 270 pFlash.ProcedureOnGoing = FLASH_PROC_MASSERASE;
<> 144:ef7eb2e8f9f7 271 #if defined (FLASH_OPTCR_nDBANK)
<> 144:ef7eb2e8f9f7 272 FLASH_MassErase((uint8_t) pEraseInit->VoltageRange, pEraseInit->Banks);
<> 144:ef7eb2e8f9f7 273 #else
<> 144:ef7eb2e8f9f7 274 FLASH_MassErase((uint8_t) pEraseInit->VoltageRange);
<> 144:ef7eb2e8f9f7 275 #endif /* FLASH_OPTCR_nDBANK */
<> 144:ef7eb2e8f9f7 276 }
<> 144:ef7eb2e8f9f7 277 else
<> 144:ef7eb2e8f9f7 278 {
<> 144:ef7eb2e8f9f7 279 /* Erase by sector to be done*/
<> 144:ef7eb2e8f9f7 280
<> 144:ef7eb2e8f9f7 281 /* Check the parameters */
<> 144:ef7eb2e8f9f7 282 assert_param(IS_FLASH_NBSECTORS(pEraseInit->NbSectors + pEraseInit->Sector));
<> 144:ef7eb2e8f9f7 283
<> 144:ef7eb2e8f9f7 284 pFlash.ProcedureOnGoing = FLASH_PROC_SECTERASE;
<> 144:ef7eb2e8f9f7 285 pFlash.NbSectorsToErase = pEraseInit->NbSectors;
<> 144:ef7eb2e8f9f7 286 pFlash.Sector = pEraseInit->Sector;
<> 144:ef7eb2e8f9f7 287 pFlash.VoltageForErase = (uint8_t)pEraseInit->VoltageRange;
<> 144:ef7eb2e8f9f7 288
<> 144:ef7eb2e8f9f7 289 /*Erase 1st sector and wait for IT*/
<> 144:ef7eb2e8f9f7 290 FLASH_Erase_Sector(pEraseInit->Sector, pEraseInit->VoltageRange);
<> 144:ef7eb2e8f9f7 291 }
<> 144:ef7eb2e8f9f7 292
<> 144:ef7eb2e8f9f7 293 return status;
<> 144:ef7eb2e8f9f7 294 }
<> 144:ef7eb2e8f9f7 295
<> 144:ef7eb2e8f9f7 296 /**
<> 144:ef7eb2e8f9f7 297 * @brief Program option bytes
AnnaBridge 182:a56a73fd2a6f 298 * @param pOBInit pointer to an FLASH_OBInitStruct structure that
<> 144:ef7eb2e8f9f7 299 * contains the configuration information for the programming.
<> 144:ef7eb2e8f9f7 300 *
<> 144:ef7eb2e8f9f7 301 * @retval HAL Status
<> 144:ef7eb2e8f9f7 302 */
<> 144:ef7eb2e8f9f7 303 HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit)
<> 144:ef7eb2e8f9f7 304 {
<> 144:ef7eb2e8f9f7 305 HAL_StatusTypeDef status = HAL_ERROR;
<> 144:ef7eb2e8f9f7 306
<> 144:ef7eb2e8f9f7 307 /* Process Locked */
<> 144:ef7eb2e8f9f7 308 __HAL_LOCK(&pFlash);
<> 144:ef7eb2e8f9f7 309
<> 144:ef7eb2e8f9f7 310 /* Check the parameters */
<> 144:ef7eb2e8f9f7 311 assert_param(IS_OPTIONBYTE(pOBInit->OptionType));
<> 144:ef7eb2e8f9f7 312
<> 144:ef7eb2e8f9f7 313 /* Write protection configuration */
<> 144:ef7eb2e8f9f7 314 if((pOBInit->OptionType & OPTIONBYTE_WRP) == OPTIONBYTE_WRP)
<> 144:ef7eb2e8f9f7 315 {
<> 144:ef7eb2e8f9f7 316 assert_param(IS_WRPSTATE(pOBInit->WRPState));
<> 144:ef7eb2e8f9f7 317 if(pOBInit->WRPState == OB_WRPSTATE_ENABLE)
<> 144:ef7eb2e8f9f7 318 {
<> 144:ef7eb2e8f9f7 319 /*Enable of Write protection on the selected Sector*/
<> 144:ef7eb2e8f9f7 320 status = FLASH_OB_EnableWRP(pOBInit->WRPSector);
<> 144:ef7eb2e8f9f7 321 }
<> 144:ef7eb2e8f9f7 322 else
<> 144:ef7eb2e8f9f7 323 {
<> 144:ef7eb2e8f9f7 324 /*Disable of Write protection on the selected Sector*/
<> 144:ef7eb2e8f9f7 325 status = FLASH_OB_DisableWRP(pOBInit->WRPSector);
<> 144:ef7eb2e8f9f7 326 }
<> 144:ef7eb2e8f9f7 327 }
<> 144:ef7eb2e8f9f7 328
<> 144:ef7eb2e8f9f7 329 /* Read protection configuration */
<> 144:ef7eb2e8f9f7 330 if((pOBInit->OptionType & OPTIONBYTE_RDP) == OPTIONBYTE_RDP)
<> 144:ef7eb2e8f9f7 331 {
<> 144:ef7eb2e8f9f7 332 status = FLASH_OB_RDP_LevelConfig(pOBInit->RDPLevel);
<> 144:ef7eb2e8f9f7 333 }
<> 144:ef7eb2e8f9f7 334
<> 144:ef7eb2e8f9f7 335 /* USER configuration */
<> 144:ef7eb2e8f9f7 336 if((pOBInit->OptionType & OPTIONBYTE_USER) == OPTIONBYTE_USER)
<> 144:ef7eb2e8f9f7 337 {
<> 144:ef7eb2e8f9f7 338 #if defined (FLASH_OPTCR_nDBANK)
<> 144:ef7eb2e8f9f7 339 status = FLASH_OB_UserConfig(pOBInit->USERConfig & OB_WWDG_SW,
<> 144:ef7eb2e8f9f7 340 pOBInit->USERConfig & OB_IWDG_SW,
<> 144:ef7eb2e8f9f7 341 pOBInit->USERConfig & OB_STOP_NO_RST,
<> 144:ef7eb2e8f9f7 342 pOBInit->USERConfig & OB_STDBY_NO_RST,
<> 144:ef7eb2e8f9f7 343 pOBInit->USERConfig & OB_IWDG_STOP_ACTIVE,
<> 144:ef7eb2e8f9f7 344 pOBInit->USERConfig & OB_IWDG_STDBY_ACTIVE,
<> 144:ef7eb2e8f9f7 345 pOBInit->USERConfig & OB_NDBANK_SINGLE_BANK,
<> 144:ef7eb2e8f9f7 346 pOBInit->USERConfig & OB_DUAL_BOOT_DISABLE);
<> 144:ef7eb2e8f9f7 347 #else
<> 144:ef7eb2e8f9f7 348 status = FLASH_OB_UserConfig(pOBInit->USERConfig & OB_WWDG_SW,
<> 144:ef7eb2e8f9f7 349 pOBInit->USERConfig & OB_IWDG_SW,
<> 144:ef7eb2e8f9f7 350 pOBInit->USERConfig & OB_STOP_NO_RST,
<> 144:ef7eb2e8f9f7 351 pOBInit->USERConfig & OB_STDBY_NO_RST,
<> 144:ef7eb2e8f9f7 352 pOBInit->USERConfig & OB_IWDG_STOP_ACTIVE,
<> 144:ef7eb2e8f9f7 353 pOBInit->USERConfig & OB_IWDG_STDBY_ACTIVE);
<> 144:ef7eb2e8f9f7 354 #endif /* FLASH_OPTCR_nDBANK */
<> 144:ef7eb2e8f9f7 355 }
<> 144:ef7eb2e8f9f7 356
<> 144:ef7eb2e8f9f7 357 /* BOR Level configuration */
<> 144:ef7eb2e8f9f7 358 if((pOBInit->OptionType & OPTIONBYTE_BOR) == OPTIONBYTE_BOR)
<> 144:ef7eb2e8f9f7 359 {
<> 144:ef7eb2e8f9f7 360 status = FLASH_OB_BOR_LevelConfig(pOBInit->BORLevel);
<> 144:ef7eb2e8f9f7 361 }
<> 144:ef7eb2e8f9f7 362
<> 144:ef7eb2e8f9f7 363 /* Boot 0 Address configuration */
<> 144:ef7eb2e8f9f7 364 if((pOBInit->OptionType & OPTIONBYTE_BOOTADDR_0) == OPTIONBYTE_BOOTADDR_0)
<> 144:ef7eb2e8f9f7 365 {
<> 144:ef7eb2e8f9f7 366 status = FLASH_OB_BootAddressConfig(OPTIONBYTE_BOOTADDR_0, pOBInit->BootAddr0);
<> 144:ef7eb2e8f9f7 367 }
<> 144:ef7eb2e8f9f7 368
<> 144:ef7eb2e8f9f7 369 /* Boot 1 Address configuration */
<> 144:ef7eb2e8f9f7 370 if((pOBInit->OptionType & OPTIONBYTE_BOOTADDR_1) == OPTIONBYTE_BOOTADDR_1)
<> 144:ef7eb2e8f9f7 371 {
<> 144:ef7eb2e8f9f7 372 status = FLASH_OB_BootAddressConfig(OPTIONBYTE_BOOTADDR_1, pOBInit->BootAddr1);
<> 144:ef7eb2e8f9f7 373 }
<> 161:2cc1468da177 374
<> 161:2cc1468da177 375 #if defined (FLASH_OPTCR2_PCROP)
<> 161:2cc1468da177 376 /* PCROP configuration */
<> 161:2cc1468da177 377 if((pOBInit->OptionType & OPTIONBYTE_PCROP) == OPTIONBYTE_PCROP)
<> 161:2cc1468da177 378 {
<> 161:2cc1468da177 379 status = FLASH_OB_PCROP_Config(pOBInit->PCROPSector);
<> 161:2cc1468da177 380 }
<> 161:2cc1468da177 381
<> 161:2cc1468da177 382 /* PCROP_RDP configuration */
<> 161:2cc1468da177 383 if((pOBInit->OptionType & OPTIONBYTE_PCROP_RDP) == OPTIONBYTE_PCROP_RDP)
<> 161:2cc1468da177 384 {
<> 161:2cc1468da177 385 status = FLASH_OB_PCROP_RDP_Config(pOBInit->PCROPRdp);
<> 161:2cc1468da177 386 }
<> 161:2cc1468da177 387 #endif /* FLASH_OPTCR2_PCROP */
<> 144:ef7eb2e8f9f7 388
<> 144:ef7eb2e8f9f7 389 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 390 __HAL_UNLOCK(&pFlash);
<> 144:ef7eb2e8f9f7 391
<> 144:ef7eb2e8f9f7 392 return status;
<> 144:ef7eb2e8f9f7 393 }
<> 144:ef7eb2e8f9f7 394
<> 144:ef7eb2e8f9f7 395 /**
<> 144:ef7eb2e8f9f7 396 * @brief Get the Option byte configuration
AnnaBridge 182:a56a73fd2a6f 397 * @param pOBInit pointer to an FLASH_OBInitStruct structure that
<> 144:ef7eb2e8f9f7 398 * contains the configuration information for the programming.
<> 144:ef7eb2e8f9f7 399 *
<> 144:ef7eb2e8f9f7 400 * @retval None
<> 144:ef7eb2e8f9f7 401 */
<> 144:ef7eb2e8f9f7 402 void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit)
<> 144:ef7eb2e8f9f7 403 {
<> 144:ef7eb2e8f9f7 404 pOBInit->OptionType = OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER |\
<> 144:ef7eb2e8f9f7 405 OPTIONBYTE_BOR | OPTIONBYTE_BOOTADDR_0 | OPTIONBYTE_BOOTADDR_1;
<> 144:ef7eb2e8f9f7 406
<> 144:ef7eb2e8f9f7 407 /*Get WRP*/
<> 144:ef7eb2e8f9f7 408 pOBInit->WRPSector = FLASH_OB_GetWRP();
<> 144:ef7eb2e8f9f7 409
<> 144:ef7eb2e8f9f7 410 /*Get RDP Level*/
<> 144:ef7eb2e8f9f7 411 pOBInit->RDPLevel = FLASH_OB_GetRDP();
<> 144:ef7eb2e8f9f7 412
<> 144:ef7eb2e8f9f7 413 /*Get USER*/
<> 144:ef7eb2e8f9f7 414 pOBInit->USERConfig = FLASH_OB_GetUser();
<> 144:ef7eb2e8f9f7 415
<> 144:ef7eb2e8f9f7 416 /*Get BOR Level*/
<> 144:ef7eb2e8f9f7 417 pOBInit->BORLevel = FLASH_OB_GetBOR();
<> 144:ef7eb2e8f9f7 418
<> 144:ef7eb2e8f9f7 419 /*Get Boot Address when Boot pin = 0 */
<> 144:ef7eb2e8f9f7 420 pOBInit->BootAddr0 = FLASH_OB_GetBootAddress(OPTIONBYTE_BOOTADDR_0);
<> 144:ef7eb2e8f9f7 421
<> 144:ef7eb2e8f9f7 422 /*Get Boot Address when Boot pin = 1 */
<> 144:ef7eb2e8f9f7 423 pOBInit->BootAddr1 = FLASH_OB_GetBootAddress(OPTIONBYTE_BOOTADDR_1);
<> 161:2cc1468da177 424
<> 161:2cc1468da177 425 #if defined (FLASH_OPTCR2_PCROP)
<> 161:2cc1468da177 426 /*Get PCROP Sectors */
<> 161:2cc1468da177 427 pOBInit->PCROPSector = FLASH_OB_GetPCROP();
<> 161:2cc1468da177 428
<> 161:2cc1468da177 429 /*Get PCROP_RDP Value */
<> 161:2cc1468da177 430 pOBInit->PCROPRdp = FLASH_OB_GetPCROPRDP();
<> 161:2cc1468da177 431 #endif /* FLASH_OPTCR2_PCROP */
<> 144:ef7eb2e8f9f7 432 }
<> 144:ef7eb2e8f9f7 433 /**
<> 144:ef7eb2e8f9f7 434 * @}
<> 144:ef7eb2e8f9f7 435 */
<> 144:ef7eb2e8f9f7 436
<> 144:ef7eb2e8f9f7 437 #if defined (FLASH_OPTCR_nDBANK)
<> 144:ef7eb2e8f9f7 438 /**
<> 144:ef7eb2e8f9f7 439 * @brief Full erase of FLASH memory sectors
AnnaBridge 182:a56a73fd2a6f 440 * @param VoltageRange The device voltage range which defines the erase parallelism.
<> 144:ef7eb2e8f9f7 441 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 442 * @arg VOLTAGE_RANGE_1: when the device voltage range is 1.8V to 2.1V,
<> 144:ef7eb2e8f9f7 443 * the operation will be done by byte (8-bit)
<> 144:ef7eb2e8f9f7 444 * @arg VOLTAGE_RANGE_2: when the device voltage range is 2.1V to 2.7V,
<> 144:ef7eb2e8f9f7 445 * the operation will be done by half word (16-bit)
<> 144:ef7eb2e8f9f7 446 * @arg VOLTAGE_RANGE_3: when the device voltage range is 2.7V to 3.6V,
<> 144:ef7eb2e8f9f7 447 * the operation will be done by word (32-bit)
<> 144:ef7eb2e8f9f7 448 * @arg VOLTAGE_RANGE_4: when the device voltage range is 2.7V to 3.6V + External Vpp,
<> 144:ef7eb2e8f9f7 449 * the operation will be done by double word (64-bit)
AnnaBridge 182:a56a73fd2a6f 450 * @param Banks Banks to be erased
<> 144:ef7eb2e8f9f7 451 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 452 * @arg FLASH_BANK_1: Bank1 to be erased
<> 144:ef7eb2e8f9f7 453 * @arg FLASH_BANK_2: Bank2 to be erased
<> 144:ef7eb2e8f9f7 454 * @arg FLASH_BANK_BOTH: Bank1 and Bank2 to be erased
<> 144:ef7eb2e8f9f7 455 *
<> 144:ef7eb2e8f9f7 456 * @retval HAL Status
<> 144:ef7eb2e8f9f7 457 */
<> 144:ef7eb2e8f9f7 458 static void FLASH_MassErase(uint8_t VoltageRange, uint32_t Banks)
<> 144:ef7eb2e8f9f7 459 {
<> 144:ef7eb2e8f9f7 460 /* Check the parameters */
<> 144:ef7eb2e8f9f7 461 assert_param(IS_VOLTAGERANGE(VoltageRange));
<> 144:ef7eb2e8f9f7 462 assert_param(IS_FLASH_BANK(Banks));
<> 144:ef7eb2e8f9f7 463
<> 144:ef7eb2e8f9f7 464 /* if the previous operation is completed, proceed to erase all sectors */
<> 144:ef7eb2e8f9f7 465 FLASH->CR &= CR_PSIZE_MASK;
<> 144:ef7eb2e8f9f7 466 if(Banks == FLASH_BANK_BOTH)
<> 144:ef7eb2e8f9f7 467 {
<> 144:ef7eb2e8f9f7 468 /* bank1 & bank2 will be erased*/
<> 144:ef7eb2e8f9f7 469 FLASH->CR |= FLASH_MER_BIT;
<> 144:ef7eb2e8f9f7 470 }
<> 144:ef7eb2e8f9f7 471 else if(Banks == FLASH_BANK_2)
<> 144:ef7eb2e8f9f7 472 {
<> 144:ef7eb2e8f9f7 473 /*Only bank2 will be erased*/
<> 144:ef7eb2e8f9f7 474 FLASH->CR |= FLASH_CR_MER2;
<> 144:ef7eb2e8f9f7 475 }
<> 144:ef7eb2e8f9f7 476 else
<> 144:ef7eb2e8f9f7 477 {
<> 144:ef7eb2e8f9f7 478 /*Only bank1 will be erased*/
<> 144:ef7eb2e8f9f7 479 FLASH->CR |= FLASH_CR_MER1;
<> 144:ef7eb2e8f9f7 480 }
<> 144:ef7eb2e8f9f7 481 FLASH->CR |= FLASH_CR_STRT | ((uint32_t)VoltageRange <<8);
<> 144:ef7eb2e8f9f7 482 /* Data synchronous Barrier (DSB) Just after the write operation
<> 144:ef7eb2e8f9f7 483 This will force the CPU to respect the sequence of instruction (no optimization).*/
<> 144:ef7eb2e8f9f7 484 __DSB();
<> 144:ef7eb2e8f9f7 485 }
<> 144:ef7eb2e8f9f7 486
<> 144:ef7eb2e8f9f7 487 /**
<> 144:ef7eb2e8f9f7 488 * @brief Erase the specified FLASH memory sector
AnnaBridge 182:a56a73fd2a6f 489 * @param Sector FLASH sector to erase
<> 144:ef7eb2e8f9f7 490 * The value of this parameter depend on device used within the same series
AnnaBridge 182:a56a73fd2a6f 491 * @param VoltageRange The device voltage range which defines the erase parallelism.
<> 144:ef7eb2e8f9f7 492 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 493 * @arg FLASH_VOLTAGE_RANGE_1: when the device voltage range is 1.8V to 2.1V,
<> 144:ef7eb2e8f9f7 494 * the operation will be done by byte (8-bit)
<> 144:ef7eb2e8f9f7 495 * @arg FLASH_VOLTAGE_RANGE_2: when the device voltage range is 2.1V to 2.7V,
<> 144:ef7eb2e8f9f7 496 * the operation will be done by half word (16-bit)
<> 144:ef7eb2e8f9f7 497 * @arg FLASH_VOLTAGE_RANGE_3: when the device voltage range is 2.7V to 3.6V,
<> 144:ef7eb2e8f9f7 498 * the operation will be done by word (32-bit)
<> 144:ef7eb2e8f9f7 499 * @arg FLASH_VOLTAGE_RANGE_4: when the device voltage range is 2.7V to 3.6V + External Vpp,
<> 144:ef7eb2e8f9f7 500 * the operation will be done by double word (64-bit)
<> 144:ef7eb2e8f9f7 501 *
<> 144:ef7eb2e8f9f7 502 * @retval None
<> 144:ef7eb2e8f9f7 503 */
<> 144:ef7eb2e8f9f7 504 void FLASH_Erase_Sector(uint32_t Sector, uint8_t VoltageRange)
<> 144:ef7eb2e8f9f7 505 {
<> 144:ef7eb2e8f9f7 506 uint32_t tmp_psize = 0;
<> 144:ef7eb2e8f9f7 507
<> 144:ef7eb2e8f9f7 508 /* Check the parameters */
<> 144:ef7eb2e8f9f7 509 assert_param(IS_FLASH_SECTOR(Sector));
<> 144:ef7eb2e8f9f7 510 assert_param(IS_VOLTAGERANGE(VoltageRange));
<> 144:ef7eb2e8f9f7 511
<> 144:ef7eb2e8f9f7 512 if(VoltageRange == FLASH_VOLTAGE_RANGE_1)
<> 144:ef7eb2e8f9f7 513 {
<> 144:ef7eb2e8f9f7 514 tmp_psize = FLASH_PSIZE_BYTE;
<> 144:ef7eb2e8f9f7 515 }
<> 144:ef7eb2e8f9f7 516 else if(VoltageRange == FLASH_VOLTAGE_RANGE_2)
<> 144:ef7eb2e8f9f7 517 {
<> 144:ef7eb2e8f9f7 518 tmp_psize = FLASH_PSIZE_HALF_WORD;
<> 144:ef7eb2e8f9f7 519 }
<> 144:ef7eb2e8f9f7 520 else if(VoltageRange == FLASH_VOLTAGE_RANGE_3)
<> 144:ef7eb2e8f9f7 521 {
<> 144:ef7eb2e8f9f7 522 tmp_psize = FLASH_PSIZE_WORD;
<> 144:ef7eb2e8f9f7 523 }
<> 144:ef7eb2e8f9f7 524 else
<> 144:ef7eb2e8f9f7 525 {
<> 144:ef7eb2e8f9f7 526 tmp_psize = FLASH_PSIZE_DOUBLE_WORD;
<> 144:ef7eb2e8f9f7 527 }
<> 144:ef7eb2e8f9f7 528
<> 144:ef7eb2e8f9f7 529 /* Need to add offset of 4 when sector higher than FLASH_SECTOR_11 */
<> 144:ef7eb2e8f9f7 530 if(Sector > FLASH_SECTOR_11)
<> 144:ef7eb2e8f9f7 531 {
<> 144:ef7eb2e8f9f7 532 Sector += 4;
<> 144:ef7eb2e8f9f7 533 }
<> 144:ef7eb2e8f9f7 534
<> 144:ef7eb2e8f9f7 535 /* If the previous operation is completed, proceed to erase the sector */
<> 144:ef7eb2e8f9f7 536 FLASH->CR &= CR_PSIZE_MASK;
<> 144:ef7eb2e8f9f7 537 FLASH->CR |= tmp_psize;
<> 144:ef7eb2e8f9f7 538 CLEAR_BIT(FLASH->CR, FLASH_CR_SNB);
AnnaBridge 182:a56a73fd2a6f 539 FLASH->CR |= FLASH_CR_SER | (Sector << FLASH_CR_SNB_Pos);
<> 144:ef7eb2e8f9f7 540 FLASH->CR |= FLASH_CR_STRT;
<> 144:ef7eb2e8f9f7 541
<> 144:ef7eb2e8f9f7 542 /* Data synchronous Barrier (DSB) Just after the write operation
<> 144:ef7eb2e8f9f7 543 This will force the CPU to respect the sequence of instruction (no optimization).*/
<> 144:ef7eb2e8f9f7 544 __DSB();
<> 144:ef7eb2e8f9f7 545 }
<> 144:ef7eb2e8f9f7 546
<> 144:ef7eb2e8f9f7 547 /**
<> 144:ef7eb2e8f9f7 548 * @brief Return the FLASH Write Protection Option Bytes value.
<> 144:ef7eb2e8f9f7 549 * @retval uint32_t FLASH Write Protection Option Bytes value
<> 144:ef7eb2e8f9f7 550 */
<> 144:ef7eb2e8f9f7 551 static uint32_t FLASH_OB_GetWRP(void)
<> 144:ef7eb2e8f9f7 552 {
<> 144:ef7eb2e8f9f7 553 /* Return the FLASH write protection Register value */
<> 144:ef7eb2e8f9f7 554 return ((uint32_t)(FLASH->OPTCR & 0x0FFF0000));
<> 144:ef7eb2e8f9f7 555 }
<> 144:ef7eb2e8f9f7 556
<> 144:ef7eb2e8f9f7 557 /**
<> 144:ef7eb2e8f9f7 558 * @brief Program the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY.
AnnaBridge 182:a56a73fd2a6f 559 * @param Wwdg Selects the IWDG mode
<> 144:ef7eb2e8f9f7 560 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 561 * @arg OB_WWDG_SW: Software WWDG selected
<> 144:ef7eb2e8f9f7 562 * @arg OB_WWDG_HW: Hardware WWDG selected
AnnaBridge 182:a56a73fd2a6f 563 * @param Iwdg Selects the WWDG mode
<> 144:ef7eb2e8f9f7 564 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 565 * @arg OB_IWDG_SW: Software IWDG selected
<> 144:ef7eb2e8f9f7 566 * @arg OB_IWDG_HW: Hardware IWDG selected
AnnaBridge 182:a56a73fd2a6f 567 * @param Stop Reset event when entering STOP mode.
<> 144:ef7eb2e8f9f7 568 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 569 * @arg OB_STOP_NO_RST: No reset generated when entering in STOP
<> 144:ef7eb2e8f9f7 570 * @arg OB_STOP_RST: Reset generated when entering in STOP
AnnaBridge 182:a56a73fd2a6f 571 * @param Stdby Reset event when entering Standby mode.
<> 144:ef7eb2e8f9f7 572 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 573 * @arg OB_STDBY_NO_RST: No reset generated when entering in STANDBY
<> 144:ef7eb2e8f9f7 574 * @arg OB_STDBY_RST: Reset generated when entering in STANDBY
AnnaBridge 182:a56a73fd2a6f 575 * @param Iwdgstop Independent watchdog counter freeze in Stop mode.
<> 144:ef7eb2e8f9f7 576 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 577 * @arg OB_IWDG_STOP_FREEZE: Freeze IWDG counter in STOP
<> 144:ef7eb2e8f9f7 578 * @arg OB_IWDG_STOP_ACTIVE: IWDG counter active in STOP
AnnaBridge 182:a56a73fd2a6f 579 * @param Iwdgstdby Independent watchdog counter freeze in standby mode.
<> 144:ef7eb2e8f9f7 580 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 581 * @arg OB_IWDG_STDBY_FREEZE: Freeze IWDG counter in STANDBY
<> 144:ef7eb2e8f9f7 582 * @arg OB_IWDG_STDBY_ACTIVE: IWDG counter active in STANDBY
AnnaBridge 182:a56a73fd2a6f 583 * @param NDBank Flash Single Bank mode enabled.
<> 144:ef7eb2e8f9f7 584 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 585 * @arg OB_NDBANK_SINGLE_BANK: enable 256 bits mode (Flash is a single bank)
<> 144:ef7eb2e8f9f7 586 * @arg OB_NDBANK_DUAL_BANK: disable 256 bits mode (Flash is a dual bank in 128 bits mode)
AnnaBridge 182:a56a73fd2a6f 587 * @param NDBoot Flash Dual boot mode disable.
<> 144:ef7eb2e8f9f7 588 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 589 * @arg OB_DUAL_BOOT_DISABLE: Disable Dual Boot
<> 144:ef7eb2e8f9f7 590 * @arg OB_DUAL_BOOT_ENABLE: Enable Dual Boot
<> 144:ef7eb2e8f9f7 591
<> 144:ef7eb2e8f9f7 592 * @retval HAL Status
<> 144:ef7eb2e8f9f7 593 */
<> 144:ef7eb2e8f9f7 594 static HAL_StatusTypeDef FLASH_OB_UserConfig(uint32_t Wwdg, uint32_t Iwdg, uint32_t Stop, uint32_t Stdby, uint32_t Iwdgstop, \
<> 144:ef7eb2e8f9f7 595 uint32_t Iwdgstdby, uint32_t NDBank, uint32_t NDBoot)
<> 144:ef7eb2e8f9f7 596 {
<> 144:ef7eb2e8f9f7 597 uint32_t useroptionmask = 0x00;
<> 144:ef7eb2e8f9f7 598 uint32_t useroptionvalue = 0x00;
<> 144:ef7eb2e8f9f7 599
<> 144:ef7eb2e8f9f7 600 HAL_StatusTypeDef status = HAL_OK;
<> 144:ef7eb2e8f9f7 601
<> 144:ef7eb2e8f9f7 602 /* Check the parameters */
<> 144:ef7eb2e8f9f7 603 assert_param(IS_OB_WWDG_SOURCE(Wwdg));
<> 144:ef7eb2e8f9f7 604 assert_param(IS_OB_IWDG_SOURCE(Iwdg));
<> 144:ef7eb2e8f9f7 605 assert_param(IS_OB_STOP_SOURCE(Stop));
<> 144:ef7eb2e8f9f7 606 assert_param(IS_OB_STDBY_SOURCE(Stdby));
<> 144:ef7eb2e8f9f7 607 assert_param(IS_OB_IWDG_STOP_FREEZE(Iwdgstop));
<> 144:ef7eb2e8f9f7 608 assert_param(IS_OB_IWDG_STDBY_FREEZE(Iwdgstdby));
<> 144:ef7eb2e8f9f7 609 assert_param(IS_OB_NDBANK(NDBank));
<> 144:ef7eb2e8f9f7 610 assert_param(IS_OB_NDBOOT(NDBoot));
<> 144:ef7eb2e8f9f7 611
<> 144:ef7eb2e8f9f7 612 /* Wait for last operation to be completed */
<> 144:ef7eb2e8f9f7 613 status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
<> 144:ef7eb2e8f9f7 614
<> 144:ef7eb2e8f9f7 615 if(status == HAL_OK)
<> 144:ef7eb2e8f9f7 616 {
<> 144:ef7eb2e8f9f7 617 useroptionmask = (FLASH_OPTCR_WWDG_SW | FLASH_OPTCR_IWDG_SW | FLASH_OPTCR_nRST_STOP | \
<> 144:ef7eb2e8f9f7 618 FLASH_OPTCR_nRST_STDBY | FLASH_OPTCR_IWDG_STOP | FLASH_OPTCR_IWDG_STDBY | \
<> 144:ef7eb2e8f9f7 619 FLASH_OPTCR_nDBOOT | FLASH_OPTCR_nDBANK);
<> 144:ef7eb2e8f9f7 620
<> 144:ef7eb2e8f9f7 621 useroptionvalue = (Iwdg | Wwdg | Stop | Stdby | Iwdgstop | Iwdgstdby | NDBoot | NDBank);
<> 144:ef7eb2e8f9f7 622
<> 144:ef7eb2e8f9f7 623 /* Update User Option Byte */
<> 144:ef7eb2e8f9f7 624 MODIFY_REG(FLASH->OPTCR, useroptionmask, useroptionvalue);
<> 144:ef7eb2e8f9f7 625 }
<> 144:ef7eb2e8f9f7 626
<> 144:ef7eb2e8f9f7 627 return status;
<> 144:ef7eb2e8f9f7 628 }
<> 144:ef7eb2e8f9f7 629
<> 144:ef7eb2e8f9f7 630 /**
<> 144:ef7eb2e8f9f7 631 * @brief Return the FLASH User Option Byte value.
<> 144:ef7eb2e8f9f7 632 * @retval uint32_t FLASH User Option Bytes values: WWDG_SW(Bit4), IWDG_SW(Bit5), nRST_STOP(Bit6),
<> 144:ef7eb2e8f9f7 633 * nRST_STDBY(Bit7), nDBOOT(Bit28), nDBANK(Bit29), IWDG_STDBY(Bit30) and IWDG_STOP(Bit31).
<> 144:ef7eb2e8f9f7 634 */
<> 144:ef7eb2e8f9f7 635 static uint32_t FLASH_OB_GetUser(void)
<> 144:ef7eb2e8f9f7 636 {
<> 144:ef7eb2e8f9f7 637 /* Return the User Option Byte */
<> 144:ef7eb2e8f9f7 638 return ((uint32_t)(FLASH->OPTCR & 0xF00000F0U));
<> 144:ef7eb2e8f9f7 639 }
<> 144:ef7eb2e8f9f7 640 #else
<> 144:ef7eb2e8f9f7 641
<> 144:ef7eb2e8f9f7 642 /**
<> 144:ef7eb2e8f9f7 643 * @brief Full erase of FLASH memory sectors
AnnaBridge 182:a56a73fd2a6f 644 * @param VoltageRange The device voltage range which defines the erase parallelism.
<> 144:ef7eb2e8f9f7 645 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 646 * @arg VOLTAGE_RANGE_1: when the device voltage range is 1.8V to 2.1V,
<> 144:ef7eb2e8f9f7 647 * the operation will be done by byte (8-bit)
<> 144:ef7eb2e8f9f7 648 * @arg VOLTAGE_RANGE_2: when the device voltage range is 2.1V to 2.7V,
<> 144:ef7eb2e8f9f7 649 * the operation will be done by half word (16-bit)
<> 144:ef7eb2e8f9f7 650 * @arg VOLTAGE_RANGE_3: when the device voltage range is 2.7V to 3.6V,
<> 144:ef7eb2e8f9f7 651 * the operation will be done by word (32-bit)
<> 144:ef7eb2e8f9f7 652 * @arg VOLTAGE_RANGE_4: when the device voltage range is 2.7V to 3.6V + External Vpp,
<> 144:ef7eb2e8f9f7 653 * the operation will be done by double word (64-bit)
<> 144:ef7eb2e8f9f7 654 *
<> 144:ef7eb2e8f9f7 655 * @retval HAL Status
<> 144:ef7eb2e8f9f7 656 */
<> 144:ef7eb2e8f9f7 657 static void FLASH_MassErase(uint8_t VoltageRange)
<> 144:ef7eb2e8f9f7 658 {
<> 144:ef7eb2e8f9f7 659 /* Check the parameters */
<> 144:ef7eb2e8f9f7 660 assert_param(IS_VOLTAGERANGE(VoltageRange));
<> 144:ef7eb2e8f9f7 661
<> 144:ef7eb2e8f9f7 662 /* if the previous operation is completed, proceed to erase all sectors */
<> 144:ef7eb2e8f9f7 663 FLASH->CR &= CR_PSIZE_MASK;
<> 144:ef7eb2e8f9f7 664 FLASH->CR |= FLASH_CR_MER;
<> 144:ef7eb2e8f9f7 665 FLASH->CR |= FLASH_CR_STRT | ((uint32_t)VoltageRange <<8);
<> 144:ef7eb2e8f9f7 666 /* Data synchronous Barrier (DSB) Just after the write operation
<> 144:ef7eb2e8f9f7 667 This will force the CPU to respect the sequence of instruction (no optimization).*/
<> 144:ef7eb2e8f9f7 668 __DSB();
<> 144:ef7eb2e8f9f7 669 }
<> 144:ef7eb2e8f9f7 670
<> 144:ef7eb2e8f9f7 671 /**
<> 144:ef7eb2e8f9f7 672 * @brief Erase the specified FLASH memory sector
AnnaBridge 182:a56a73fd2a6f 673 * @param Sector FLASH sector to erase
<> 144:ef7eb2e8f9f7 674 * The value of this parameter depend on device used within the same series
AnnaBridge 182:a56a73fd2a6f 675 * @param VoltageRange The device voltage range which defines the erase parallelism.
<> 144:ef7eb2e8f9f7 676 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 677 * @arg FLASH_VOLTAGE_RANGE_1: when the device voltage range is 1.8V to 2.1V,
<> 144:ef7eb2e8f9f7 678 * the operation will be done by byte (8-bit)
<> 144:ef7eb2e8f9f7 679 * @arg FLASH_VOLTAGE_RANGE_2: when the device voltage range is 2.1V to 2.7V,
<> 144:ef7eb2e8f9f7 680 * the operation will be done by half word (16-bit)
<> 144:ef7eb2e8f9f7 681 * @arg FLASH_VOLTAGE_RANGE_3: when the device voltage range is 2.7V to 3.6V,
<> 144:ef7eb2e8f9f7 682 * the operation will be done by word (32-bit)
<> 144:ef7eb2e8f9f7 683 * @arg FLASH_VOLTAGE_RANGE_4: when the device voltage range is 2.7V to 3.6V + External Vpp,
<> 144:ef7eb2e8f9f7 684 * the operation will be done by double word (64-bit)
<> 144:ef7eb2e8f9f7 685 *
<> 144:ef7eb2e8f9f7 686 * @retval None
<> 144:ef7eb2e8f9f7 687 */
<> 144:ef7eb2e8f9f7 688 void FLASH_Erase_Sector(uint32_t Sector, uint8_t VoltageRange)
<> 144:ef7eb2e8f9f7 689 {
<> 144:ef7eb2e8f9f7 690 uint32_t tmp_psize = 0;
<> 144:ef7eb2e8f9f7 691
<> 144:ef7eb2e8f9f7 692 /* Check the parameters */
<> 144:ef7eb2e8f9f7 693 assert_param(IS_FLASH_SECTOR(Sector));
<> 144:ef7eb2e8f9f7 694 assert_param(IS_VOLTAGERANGE(VoltageRange));
<> 144:ef7eb2e8f9f7 695
<> 144:ef7eb2e8f9f7 696 if(VoltageRange == FLASH_VOLTAGE_RANGE_1)
<> 144:ef7eb2e8f9f7 697 {
<> 144:ef7eb2e8f9f7 698 tmp_psize = FLASH_PSIZE_BYTE;
<> 144:ef7eb2e8f9f7 699 }
<> 144:ef7eb2e8f9f7 700 else if(VoltageRange == FLASH_VOLTAGE_RANGE_2)
<> 144:ef7eb2e8f9f7 701 {
<> 144:ef7eb2e8f9f7 702 tmp_psize = FLASH_PSIZE_HALF_WORD;
<> 144:ef7eb2e8f9f7 703 }
<> 144:ef7eb2e8f9f7 704 else if(VoltageRange == FLASH_VOLTAGE_RANGE_3)
<> 144:ef7eb2e8f9f7 705 {
<> 144:ef7eb2e8f9f7 706 tmp_psize = FLASH_PSIZE_WORD;
<> 144:ef7eb2e8f9f7 707 }
<> 144:ef7eb2e8f9f7 708 else
<> 144:ef7eb2e8f9f7 709 {
<> 144:ef7eb2e8f9f7 710 tmp_psize = FLASH_PSIZE_DOUBLE_WORD;
<> 144:ef7eb2e8f9f7 711 }
<> 144:ef7eb2e8f9f7 712
<> 144:ef7eb2e8f9f7 713 /* If the previous operation is completed, proceed to erase the sector */
<> 144:ef7eb2e8f9f7 714 FLASH->CR &= CR_PSIZE_MASK;
<> 144:ef7eb2e8f9f7 715 FLASH->CR |= tmp_psize;
<> 144:ef7eb2e8f9f7 716 FLASH->CR &= SECTOR_MASK;
AnnaBridge 182:a56a73fd2a6f 717 FLASH->CR |= FLASH_CR_SER | (Sector << FLASH_CR_SNB_Pos);
<> 144:ef7eb2e8f9f7 718 FLASH->CR |= FLASH_CR_STRT;
<> 144:ef7eb2e8f9f7 719
<> 144:ef7eb2e8f9f7 720 /* Data synchronous Barrier (DSB) Just after the write operation
<> 144:ef7eb2e8f9f7 721 This will force the CPU to respect the sequence of instruction (no optimization).*/
<> 144:ef7eb2e8f9f7 722 __DSB();
<> 144:ef7eb2e8f9f7 723 }
<> 144:ef7eb2e8f9f7 724
<> 144:ef7eb2e8f9f7 725 /**
<> 144:ef7eb2e8f9f7 726 * @brief Return the FLASH Write Protection Option Bytes value.
<> 144:ef7eb2e8f9f7 727 * @retval uint32_t FLASH Write Protection Option Bytes value
<> 144:ef7eb2e8f9f7 728 */
<> 144:ef7eb2e8f9f7 729 static uint32_t FLASH_OB_GetWRP(void)
<> 144:ef7eb2e8f9f7 730 {
<> 144:ef7eb2e8f9f7 731 /* Return the FLASH write protection Register value */
<> 144:ef7eb2e8f9f7 732 return ((uint32_t)(FLASH->OPTCR & 0x00FF0000));
<> 144:ef7eb2e8f9f7 733 }
<> 144:ef7eb2e8f9f7 734
<> 144:ef7eb2e8f9f7 735 /**
<> 144:ef7eb2e8f9f7 736 * @brief Program the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY.
AnnaBridge 182:a56a73fd2a6f 737 * @param Wwdg Selects the IWDG mode
<> 144:ef7eb2e8f9f7 738 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 739 * @arg OB_WWDG_SW: Software WWDG selected
<> 144:ef7eb2e8f9f7 740 * @arg OB_WWDG_HW: Hardware WWDG selected
AnnaBridge 182:a56a73fd2a6f 741 * @param Iwdg Selects the WWDG mode
<> 144:ef7eb2e8f9f7 742 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 743 * @arg OB_IWDG_SW: Software IWDG selected
<> 144:ef7eb2e8f9f7 744 * @arg OB_IWDG_HW: Hardware IWDG selected
AnnaBridge 182:a56a73fd2a6f 745 * @param Stop Reset event when entering STOP mode.
<> 144:ef7eb2e8f9f7 746 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 747 * @arg OB_STOP_NO_RST: No reset generated when entering in STOP
<> 144:ef7eb2e8f9f7 748 * @arg OB_STOP_RST: Reset generated when entering in STOP
AnnaBridge 182:a56a73fd2a6f 749 * @param Stdby Reset event when entering Standby mode.
<> 144:ef7eb2e8f9f7 750 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 751 * @arg OB_STDBY_NO_RST: No reset generated when entering in STANDBY
<> 144:ef7eb2e8f9f7 752 * @arg OB_STDBY_RST: Reset generated when entering in STANDBY
AnnaBridge 182:a56a73fd2a6f 753 * @param Iwdgstop Independent watchdog counter freeze in Stop mode.
<> 144:ef7eb2e8f9f7 754 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 755 * @arg OB_IWDG_STOP_FREEZE: Freeze IWDG counter in STOP
<> 144:ef7eb2e8f9f7 756 * @arg OB_IWDG_STOP_ACTIVE: IWDG counter active in STOP
AnnaBridge 182:a56a73fd2a6f 757 * @param Iwdgstdby Independent watchdog counter freeze in standby mode.
<> 144:ef7eb2e8f9f7 758 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 759 * @arg OB_IWDG_STDBY_FREEZE: Freeze IWDG counter in STANDBY
<> 144:ef7eb2e8f9f7 760 * @arg OB_IWDG_STDBY_ACTIVE: IWDG counter active in STANDBY
<> 144:ef7eb2e8f9f7 761 * @retval HAL Status
<> 144:ef7eb2e8f9f7 762 */
<> 144:ef7eb2e8f9f7 763 static HAL_StatusTypeDef FLASH_OB_UserConfig(uint32_t Wwdg, uint32_t Iwdg, uint32_t Stop, uint32_t Stdby, uint32_t Iwdgstop, uint32_t Iwdgstdby)
<> 144:ef7eb2e8f9f7 764 {
<> 144:ef7eb2e8f9f7 765 uint32_t useroptionmask = 0x00;
<> 144:ef7eb2e8f9f7 766 uint32_t useroptionvalue = 0x00;
<> 144:ef7eb2e8f9f7 767
<> 144:ef7eb2e8f9f7 768 HAL_StatusTypeDef status = HAL_OK;
<> 144:ef7eb2e8f9f7 769
<> 144:ef7eb2e8f9f7 770 /* Check the parameters */
<> 144:ef7eb2e8f9f7 771 assert_param(IS_OB_WWDG_SOURCE(Wwdg));
<> 144:ef7eb2e8f9f7 772 assert_param(IS_OB_IWDG_SOURCE(Iwdg));
<> 144:ef7eb2e8f9f7 773 assert_param(IS_OB_STOP_SOURCE(Stop));
<> 144:ef7eb2e8f9f7 774 assert_param(IS_OB_STDBY_SOURCE(Stdby));
<> 144:ef7eb2e8f9f7 775 assert_param(IS_OB_IWDG_STOP_FREEZE(Iwdgstop));
<> 144:ef7eb2e8f9f7 776 assert_param(IS_OB_IWDG_STDBY_FREEZE(Iwdgstdby));
<> 144:ef7eb2e8f9f7 777
<> 144:ef7eb2e8f9f7 778 /* Wait for last operation to be completed */
<> 144:ef7eb2e8f9f7 779 status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
<> 144:ef7eb2e8f9f7 780
<> 144:ef7eb2e8f9f7 781 if(status == HAL_OK)
<> 144:ef7eb2e8f9f7 782 {
<> 144:ef7eb2e8f9f7 783 useroptionmask = (FLASH_OPTCR_WWDG_SW | FLASH_OPTCR_IWDG_SW | FLASH_OPTCR_nRST_STOP | \
<> 144:ef7eb2e8f9f7 784 FLASH_OPTCR_nRST_STDBY | FLASH_OPTCR_IWDG_STOP | FLASH_OPTCR_IWDG_STDBY);
<> 144:ef7eb2e8f9f7 785
<> 144:ef7eb2e8f9f7 786 useroptionvalue = (Iwdg | Wwdg | Stop | Stdby | Iwdgstop | Iwdgstdby);
<> 144:ef7eb2e8f9f7 787
<> 144:ef7eb2e8f9f7 788 /* Update User Option Byte */
<> 144:ef7eb2e8f9f7 789 MODIFY_REG(FLASH->OPTCR, useroptionmask, useroptionvalue);
<> 144:ef7eb2e8f9f7 790 }
<> 144:ef7eb2e8f9f7 791
<> 144:ef7eb2e8f9f7 792 return status;
<> 144:ef7eb2e8f9f7 793
<> 144:ef7eb2e8f9f7 794 }
<> 144:ef7eb2e8f9f7 795
<> 144:ef7eb2e8f9f7 796 /**
<> 144:ef7eb2e8f9f7 797 * @brief Return the FLASH User Option Byte value.
<> 144:ef7eb2e8f9f7 798 * @retval uint32_t FLASH User Option Bytes values: WWDG_SW(Bit4), IWDG_SW(Bit5), nRST_STOP(Bit6),
<> 144:ef7eb2e8f9f7 799 * nRST_STDBY(Bit7), IWDG_STDBY(Bit30) and IWDG_STOP(Bit31).
<> 144:ef7eb2e8f9f7 800 */
<> 144:ef7eb2e8f9f7 801 static uint32_t FLASH_OB_GetUser(void)
<> 144:ef7eb2e8f9f7 802 {
<> 144:ef7eb2e8f9f7 803 /* Return the User Option Byte */
<> 157:ff67d9f36b67 804 return ((uint32_t)(FLASH->OPTCR & 0xC00000F0U));
<> 144:ef7eb2e8f9f7 805 }
<> 144:ef7eb2e8f9f7 806 #endif /* FLASH_OPTCR_nDBANK */
<> 144:ef7eb2e8f9f7 807
<> 144:ef7eb2e8f9f7 808 /**
<> 144:ef7eb2e8f9f7 809 * @brief Enable the write protection of the desired bank1 or bank2 sectors
<> 144:ef7eb2e8f9f7 810 *
<> 144:ef7eb2e8f9f7 811 * @note When the memory read protection level is selected (RDP level = 1),
<> 144:ef7eb2e8f9f7 812 * it is not possible to program or erase the flash sector i if CortexM7
<> 144:ef7eb2e8f9f7 813 * debug features are connected or boot code is executed in RAM, even if nWRPi = 1
<> 144:ef7eb2e8f9f7 814 *
AnnaBridge 182:a56a73fd2a6f 815 * @param WRPSector specifies the sector(s) to be write protected.
<> 144:ef7eb2e8f9f7 816 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 817 * @arg WRPSector: A value between OB_WRP_SECTOR_0 and OB_WRP_SECTOR_7 (for STM32F74xxx/STM32F75xxx devices)
<> 144:ef7eb2e8f9f7 818 * or a value between OB_WRP_SECTOR_0 and OB_WRP_SECTOR_11 (in Single Bank mode for STM32F76xxx/STM32F77xxx devices)
<> 144:ef7eb2e8f9f7 819 * or a value between OB_WRP_DB_SECTOR_0 and OB_WRP_DB_SECTOR_23 (in Dual Bank mode for STM32F76xxx/STM32F77xxx devices)
<> 144:ef7eb2e8f9f7 820 * @arg OB_WRP_SECTOR_All
<> 144:ef7eb2e8f9f7 821 *
<> 144:ef7eb2e8f9f7 822 * @retval HAL FLASH State
<> 144:ef7eb2e8f9f7 823 */
<> 144:ef7eb2e8f9f7 824 static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WRPSector)
<> 144:ef7eb2e8f9f7 825 {
<> 144:ef7eb2e8f9f7 826 HAL_StatusTypeDef status = HAL_OK;
<> 144:ef7eb2e8f9f7 827
<> 144:ef7eb2e8f9f7 828 /* Check the parameters */
<> 144:ef7eb2e8f9f7 829 assert_param(IS_OB_WRP_SECTOR(WRPSector));
<> 144:ef7eb2e8f9f7 830
<> 144:ef7eb2e8f9f7 831 /* Wait for last operation to be completed */
<> 144:ef7eb2e8f9f7 832 status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
<> 144:ef7eb2e8f9f7 833
<> 144:ef7eb2e8f9f7 834 if(status == HAL_OK)
<> 144:ef7eb2e8f9f7 835 {
<> 144:ef7eb2e8f9f7 836 /*Write protection enabled on sectors */
<> 144:ef7eb2e8f9f7 837 FLASH->OPTCR &= (~WRPSector);
<> 144:ef7eb2e8f9f7 838 }
<> 144:ef7eb2e8f9f7 839
<> 144:ef7eb2e8f9f7 840 return status;
<> 144:ef7eb2e8f9f7 841 }
<> 144:ef7eb2e8f9f7 842
<> 144:ef7eb2e8f9f7 843 /**
<> 144:ef7eb2e8f9f7 844 * @brief Disable the write protection of the desired bank1 or bank 2 sectors
<> 144:ef7eb2e8f9f7 845 *
<> 144:ef7eb2e8f9f7 846 * @note When the memory read protection level is selected (RDP level = 1),
<> 144:ef7eb2e8f9f7 847 * it is not possible to program or erase the flash sector i if CortexM4
<> 144:ef7eb2e8f9f7 848 * debug features are connected or boot code is executed in RAM, even if nWRPi = 1
<> 144:ef7eb2e8f9f7 849 *
AnnaBridge 182:a56a73fd2a6f 850 * @param WRPSector specifies the sector(s) to be write protected.
<> 144:ef7eb2e8f9f7 851 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 852 * @arg WRPSector: A value between OB_WRP_SECTOR_0 and OB_WRP_SECTOR_7 (for STM32F74xxx/STM32F75xxx devices)
<> 144:ef7eb2e8f9f7 853 * or a value between OB_WRP_SECTOR_0 and OB_WRP_SECTOR_11 (in Single Bank mode for STM32F76xxx/STM32F77xxx devices)
<> 144:ef7eb2e8f9f7 854 * or a value between OB_WRP_DB_SECTOR_0 and OB_WRP_DB_SECTOR_23 (in Dual Bank mode for STM32F76xxx/STM32F77xxx devices)
<> 144:ef7eb2e8f9f7 855 * @arg OB_WRP_Sector_All
<> 144:ef7eb2e8f9f7 856 *
<> 144:ef7eb2e8f9f7 857 *
<> 144:ef7eb2e8f9f7 858 * @retval HAL Status
<> 144:ef7eb2e8f9f7 859 */
<> 144:ef7eb2e8f9f7 860 static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WRPSector)
<> 144:ef7eb2e8f9f7 861 {
<> 144:ef7eb2e8f9f7 862 HAL_StatusTypeDef status = HAL_OK;
<> 144:ef7eb2e8f9f7 863
<> 144:ef7eb2e8f9f7 864 /* Check the parameters */
<> 144:ef7eb2e8f9f7 865 assert_param(IS_OB_WRP_SECTOR(WRPSector));
<> 144:ef7eb2e8f9f7 866
<> 144:ef7eb2e8f9f7 867 /* Wait for last operation to be completed */
<> 144:ef7eb2e8f9f7 868 status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
<> 144:ef7eb2e8f9f7 869
<> 144:ef7eb2e8f9f7 870 if(status == HAL_OK)
<> 144:ef7eb2e8f9f7 871 {
<> 144:ef7eb2e8f9f7 872 /* Write protection disabled on sectors */
<> 144:ef7eb2e8f9f7 873 FLASH->OPTCR |= (WRPSector);
<> 144:ef7eb2e8f9f7 874 }
<> 144:ef7eb2e8f9f7 875
<> 144:ef7eb2e8f9f7 876 return status;
<> 144:ef7eb2e8f9f7 877 }
<> 144:ef7eb2e8f9f7 878
<> 144:ef7eb2e8f9f7 879 /**
<> 144:ef7eb2e8f9f7 880 * @brief Set the read protection level.
AnnaBridge 182:a56a73fd2a6f 881 * @param Level specifies the read protection level.
<> 144:ef7eb2e8f9f7 882 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 883 * @arg OB_RDP_LEVEL_0: No protection
<> 144:ef7eb2e8f9f7 884 * @arg OB_RDP_LEVEL_1: Read protection of the memory
<> 144:ef7eb2e8f9f7 885 * @arg OB_RDP_LEVEL_2: Full chip protection
<> 144:ef7eb2e8f9f7 886 *
<> 144:ef7eb2e8f9f7 887 * @note WARNING: When enabling OB_RDP level 2 it's no more possible to go back to level 1 or 0
<> 144:ef7eb2e8f9f7 888 *
<> 144:ef7eb2e8f9f7 889 * @retval HAL Status
<> 144:ef7eb2e8f9f7 890 */
<> 144:ef7eb2e8f9f7 891 static HAL_StatusTypeDef FLASH_OB_RDP_LevelConfig(uint8_t Level)
<> 144:ef7eb2e8f9f7 892 {
<> 144:ef7eb2e8f9f7 893 HAL_StatusTypeDef status = HAL_OK;
<> 144:ef7eb2e8f9f7 894
<> 144:ef7eb2e8f9f7 895 /* Check the parameters */
<> 144:ef7eb2e8f9f7 896 assert_param(IS_OB_RDP_LEVEL(Level));
<> 144:ef7eb2e8f9f7 897
<> 144:ef7eb2e8f9f7 898 /* Wait for last operation to be completed */
<> 144:ef7eb2e8f9f7 899 status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
<> 144:ef7eb2e8f9f7 900
<> 144:ef7eb2e8f9f7 901 if(status == HAL_OK)
<> 144:ef7eb2e8f9f7 902 {
<> 144:ef7eb2e8f9f7 903 *(__IO uint8_t*)OPTCR_BYTE1_ADDRESS = Level;
<> 144:ef7eb2e8f9f7 904 }
<> 144:ef7eb2e8f9f7 905
<> 144:ef7eb2e8f9f7 906 return status;
<> 144:ef7eb2e8f9f7 907 }
<> 144:ef7eb2e8f9f7 908
<> 144:ef7eb2e8f9f7 909 /**
<> 144:ef7eb2e8f9f7 910 * @brief Set the BOR Level.
AnnaBridge 182:a56a73fd2a6f 911 * @param Level specifies the Option Bytes BOR Reset Level.
<> 144:ef7eb2e8f9f7 912 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 913 * @arg OB_BOR_LEVEL3: Supply voltage ranges from 2.7 to 3.6 V
<> 144:ef7eb2e8f9f7 914 * @arg OB_BOR_LEVEL2: Supply voltage ranges from 2.4 to 2.7 V
<> 144:ef7eb2e8f9f7 915 * @arg OB_BOR_LEVEL1: Supply voltage ranges from 2.1 to 2.4 V
<> 144:ef7eb2e8f9f7 916 * @arg OB_BOR_OFF: Supply voltage ranges from 1.62 to 2.1 V
<> 144:ef7eb2e8f9f7 917 * @retval HAL Status
<> 144:ef7eb2e8f9f7 918 */
<> 144:ef7eb2e8f9f7 919 static HAL_StatusTypeDef FLASH_OB_BOR_LevelConfig(uint8_t Level)
<> 144:ef7eb2e8f9f7 920 {
<> 144:ef7eb2e8f9f7 921 /* Check the parameters */
<> 144:ef7eb2e8f9f7 922 assert_param(IS_OB_BOR_LEVEL(Level));
<> 144:ef7eb2e8f9f7 923
<> 144:ef7eb2e8f9f7 924 /* Set the BOR Level */
<> 144:ef7eb2e8f9f7 925 MODIFY_REG(FLASH->OPTCR, FLASH_OPTCR_BOR_LEV, Level);
<> 144:ef7eb2e8f9f7 926
<> 144:ef7eb2e8f9f7 927 return HAL_OK;
<> 144:ef7eb2e8f9f7 928
<> 144:ef7eb2e8f9f7 929 }
<> 144:ef7eb2e8f9f7 930
<> 144:ef7eb2e8f9f7 931 /**
<> 144:ef7eb2e8f9f7 932 * @brief Configure Boot base address.
<> 144:ef7eb2e8f9f7 933 *
AnnaBridge 182:a56a73fd2a6f 934 * @param BootOption specifies Boot base address depending from Boot pin = 0 or pin = 1
<> 144:ef7eb2e8f9f7 935 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 936 * @arg OPTIONBYTE_BOOTADDR_0 : Boot address based when Boot pin = 0
<> 144:ef7eb2e8f9f7 937 * @arg OPTIONBYTE_BOOTADDR_1 : Boot address based when Boot pin = 1
AnnaBridge 182:a56a73fd2a6f 938 * @param Address specifies Boot base address
<> 144:ef7eb2e8f9f7 939 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 940 * @arg OB_BOOTADDR_ITCM_RAM : Boot from ITCM RAM (0x00000000)
<> 144:ef7eb2e8f9f7 941 * @arg OB_BOOTADDR_SYSTEM : Boot from System memory bootloader (0x00100000)
<> 144:ef7eb2e8f9f7 942 * @arg OB_BOOTADDR_ITCM_FLASH : Boot from Flash on ITCM interface (0x00200000)
<> 144:ef7eb2e8f9f7 943 * @arg OB_BOOTADDR_AXIM_FLASH : Boot from Flash on AXIM interface (0x08000000)
<> 144:ef7eb2e8f9f7 944 * @arg OB_BOOTADDR_DTCM_RAM : Boot from DTCM RAM (0x20000000)
<> 144:ef7eb2e8f9f7 945 * @arg OB_BOOTADDR_SRAM1 : Boot from SRAM1 (0x20010000)
<> 144:ef7eb2e8f9f7 946 * @arg OB_BOOTADDR_SRAM2 : Boot from SRAM2 (0x2004C000)
<> 144:ef7eb2e8f9f7 947 *
<> 144:ef7eb2e8f9f7 948 * @retval HAL Status
<> 144:ef7eb2e8f9f7 949 */
<> 144:ef7eb2e8f9f7 950 static HAL_StatusTypeDef FLASH_OB_BootAddressConfig(uint32_t BootOption, uint32_t Address)
<> 144:ef7eb2e8f9f7 951 {
<> 144:ef7eb2e8f9f7 952 HAL_StatusTypeDef status = HAL_OK;
<> 144:ef7eb2e8f9f7 953
<> 144:ef7eb2e8f9f7 954 /* Check the parameters */
<> 144:ef7eb2e8f9f7 955 assert_param(IS_OB_BOOT_ADDRESS(Address));
<> 144:ef7eb2e8f9f7 956
<> 144:ef7eb2e8f9f7 957 /* Wait for last operation to be completed */
<> 144:ef7eb2e8f9f7 958 status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
<> 144:ef7eb2e8f9f7 959
<> 144:ef7eb2e8f9f7 960 if(status == HAL_OK)
<> 144:ef7eb2e8f9f7 961 {
<> 144:ef7eb2e8f9f7 962 if(BootOption == OPTIONBYTE_BOOTADDR_0)
<> 144:ef7eb2e8f9f7 963 {
<> 144:ef7eb2e8f9f7 964 MODIFY_REG(FLASH->OPTCR1, FLASH_OPTCR1_BOOT_ADD0, Address);
<> 144:ef7eb2e8f9f7 965 }
<> 144:ef7eb2e8f9f7 966 else
<> 144:ef7eb2e8f9f7 967 {
<> 144:ef7eb2e8f9f7 968 MODIFY_REG(FLASH->OPTCR1, FLASH_OPTCR1_BOOT_ADD1, (Address << 16));
<> 144:ef7eb2e8f9f7 969 }
<> 144:ef7eb2e8f9f7 970 }
<> 144:ef7eb2e8f9f7 971
<> 144:ef7eb2e8f9f7 972 return status;
<> 144:ef7eb2e8f9f7 973 }
<> 144:ef7eb2e8f9f7 974
<> 144:ef7eb2e8f9f7 975 /**
<> 144:ef7eb2e8f9f7 976 * @brief Returns the FLASH Read Protection level.
<> 144:ef7eb2e8f9f7 977 * @retval FlagStatus FLASH ReadOut Protection Status:
<> 144:ef7eb2e8f9f7 978 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 979 * @arg OB_RDP_LEVEL_0: No protection
<> 144:ef7eb2e8f9f7 980 * @arg OB_RDP_LEVEL_1: Read protection of the memory
<> 144:ef7eb2e8f9f7 981 * @arg OB_RDP_LEVEL_2: Full chip protection
<> 144:ef7eb2e8f9f7 982 */
<> 144:ef7eb2e8f9f7 983 static uint8_t FLASH_OB_GetRDP(void)
<> 144:ef7eb2e8f9f7 984 {
<> 144:ef7eb2e8f9f7 985 uint8_t readstatus = OB_RDP_LEVEL_0;
<> 144:ef7eb2e8f9f7 986
<> 144:ef7eb2e8f9f7 987 if ((*(__IO uint8_t*)(OPTCR_BYTE1_ADDRESS)) == OB_RDP_LEVEL_0)
<> 144:ef7eb2e8f9f7 988 {
<> 144:ef7eb2e8f9f7 989 readstatus = OB_RDP_LEVEL_0;
<> 144:ef7eb2e8f9f7 990 }
<> 144:ef7eb2e8f9f7 991 else if ((*(__IO uint8_t*)(OPTCR_BYTE1_ADDRESS)) == OB_RDP_LEVEL_2)
<> 144:ef7eb2e8f9f7 992 {
<> 144:ef7eb2e8f9f7 993 readstatus = OB_RDP_LEVEL_2;
<> 144:ef7eb2e8f9f7 994 }
<> 144:ef7eb2e8f9f7 995 else
<> 144:ef7eb2e8f9f7 996 {
<> 144:ef7eb2e8f9f7 997 readstatus = OB_RDP_LEVEL_1;
<> 144:ef7eb2e8f9f7 998 }
<> 144:ef7eb2e8f9f7 999
<> 144:ef7eb2e8f9f7 1000 return readstatus;
<> 144:ef7eb2e8f9f7 1001 }
<> 144:ef7eb2e8f9f7 1002
<> 144:ef7eb2e8f9f7 1003 /**
<> 144:ef7eb2e8f9f7 1004 * @brief Returns the FLASH BOR level.
<> 144:ef7eb2e8f9f7 1005 * @retval uint32_t The FLASH BOR level:
<> 144:ef7eb2e8f9f7 1006 * - OB_BOR_LEVEL3: Supply voltage ranges from 2.7 to 3.6 V
<> 144:ef7eb2e8f9f7 1007 * - OB_BOR_LEVEL2: Supply voltage ranges from 2.4 to 2.7 V
<> 144:ef7eb2e8f9f7 1008 * - OB_BOR_LEVEL1: Supply voltage ranges from 2.1 to 2.4 V
<> 144:ef7eb2e8f9f7 1009 * - OB_BOR_OFF : Supply voltage ranges from 1.62 to 2.1 V
<> 144:ef7eb2e8f9f7 1010 */
<> 144:ef7eb2e8f9f7 1011 static uint32_t FLASH_OB_GetBOR(void)
<> 144:ef7eb2e8f9f7 1012 {
<> 144:ef7eb2e8f9f7 1013 /* Return the FLASH BOR level */
<> 144:ef7eb2e8f9f7 1014 return ((uint32_t)(FLASH->OPTCR & 0x0C));
<> 144:ef7eb2e8f9f7 1015 }
<> 144:ef7eb2e8f9f7 1016
<> 144:ef7eb2e8f9f7 1017 /**
<> 144:ef7eb2e8f9f7 1018 * @brief Configure Boot base address.
<> 144:ef7eb2e8f9f7 1019 *
AnnaBridge 182:a56a73fd2a6f 1020 * @param BootOption specifies Boot base address depending from Boot pin = 0 or pin = 1
<> 144:ef7eb2e8f9f7 1021 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1022 * @arg OPTIONBYTE_BOOTADDR_0 : Boot address based when Boot pin = 0
<> 144:ef7eb2e8f9f7 1023 * @arg OPTIONBYTE_BOOTADDR_1 : Boot address based when Boot pin = 1
<> 144:ef7eb2e8f9f7 1024 *
<> 144:ef7eb2e8f9f7 1025 * @retval uint32_t Boot Base Address:
<> 144:ef7eb2e8f9f7 1026 * - OB_BOOTADDR_ITCM_RAM : Boot from ITCM RAM (0x00000000)
<> 144:ef7eb2e8f9f7 1027 * - OB_BOOTADDR_SYSTEM : Boot from System memory bootloader (0x00100000)
<> 144:ef7eb2e8f9f7 1028 * - OB_BOOTADDR_ITCM_FLASH : Boot from Flash on ITCM interface (0x00200000)
<> 144:ef7eb2e8f9f7 1029 * - OB_BOOTADDR_AXIM_FLASH : Boot from Flash on AXIM interface (0x08000000)
<> 144:ef7eb2e8f9f7 1030 * - OB_BOOTADDR_DTCM_RAM : Boot from DTCM RAM (0x20000000)
<> 144:ef7eb2e8f9f7 1031 * - OB_BOOTADDR_SRAM1 : Boot from SRAM1 (0x20010000)
<> 144:ef7eb2e8f9f7 1032 * - OB_BOOTADDR_SRAM2 : Boot from SRAM2 (0x2004C000)
<> 144:ef7eb2e8f9f7 1033 */
<> 144:ef7eb2e8f9f7 1034 static uint32_t FLASH_OB_GetBootAddress(uint32_t BootOption)
<> 144:ef7eb2e8f9f7 1035 {
<> 144:ef7eb2e8f9f7 1036 uint32_t Address = 0;
<> 144:ef7eb2e8f9f7 1037
<> 144:ef7eb2e8f9f7 1038 /* Return the Boot base Address */
<> 144:ef7eb2e8f9f7 1039 if(BootOption == OPTIONBYTE_BOOTADDR_0)
<> 144:ef7eb2e8f9f7 1040 {
<> 144:ef7eb2e8f9f7 1041 Address = FLASH->OPTCR1 & FLASH_OPTCR1_BOOT_ADD0;
<> 144:ef7eb2e8f9f7 1042 }
<> 144:ef7eb2e8f9f7 1043 else
<> 144:ef7eb2e8f9f7 1044 {
<> 144:ef7eb2e8f9f7 1045 Address = ((FLASH->OPTCR1 & FLASH_OPTCR1_BOOT_ADD1) >> 16);
<> 144:ef7eb2e8f9f7 1046 }
<> 144:ef7eb2e8f9f7 1047
<> 144:ef7eb2e8f9f7 1048 return Address;
<> 144:ef7eb2e8f9f7 1049 }
<> 144:ef7eb2e8f9f7 1050
<> 161:2cc1468da177 1051 #if defined (FLASH_OPTCR2_PCROP)
<> 161:2cc1468da177 1052 /**
<> 161:2cc1468da177 1053 * @brief Set the PCROP protection for sectors.
AnnaBridge 182:a56a73fd2a6f 1054 * @param PCROPSector specifies the sector(s) to be PCROP protected.
<> 161:2cc1468da177 1055 * This parameter can be one of the following values:
<> 161:2cc1468da177 1056 * @arg OB_PCROP_SECTOR_x: A value between OB_PCROP_SECTOR_0 and OB_PCROP_SECTOR_7
<> 161:2cc1468da177 1057 * @arg OB_PCROP_SECTOR_ALL
<> 161:2cc1468da177 1058 *
<> 161:2cc1468da177 1059 * @retval HAL Status
<> 161:2cc1468da177 1060 */
<> 161:2cc1468da177 1061 static HAL_StatusTypeDef FLASH_OB_PCROP_Config(uint32_t PCROPSector)
<> 161:2cc1468da177 1062 {
<> 161:2cc1468da177 1063 HAL_StatusTypeDef status = HAL_OK;
<> 161:2cc1468da177 1064
<> 161:2cc1468da177 1065 /* Check the parameters */
<> 161:2cc1468da177 1066 assert_param(IS_OB_PCROP_SECTOR(PCROPSector));
<> 161:2cc1468da177 1067
<> 161:2cc1468da177 1068 /* Wait for last operation to be completed */
<> 161:2cc1468da177 1069 status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
<> 161:2cc1468da177 1070
<> 161:2cc1468da177 1071 if(status == HAL_OK)
<> 161:2cc1468da177 1072 {
<> 161:2cc1468da177 1073 MODIFY_REG(FLASH->OPTCR2, FLASH_OPTCR2_PCROP, PCROPSector);
<> 161:2cc1468da177 1074 }
<> 161:2cc1468da177 1075
<> 161:2cc1468da177 1076 return status;
<> 161:2cc1468da177 1077 }
<> 161:2cc1468da177 1078
<> 161:2cc1468da177 1079 /**
<> 161:2cc1468da177 1080 * @brief Set the PCROP_RDP value
AnnaBridge 182:a56a73fd2a6f 1081 * @param Pcrop_Rdp specifies the PCROP_RDP bit value.
<> 161:2cc1468da177 1082 *
<> 161:2cc1468da177 1083 * @retval HAL Status
<> 161:2cc1468da177 1084 */
<> 161:2cc1468da177 1085 static HAL_StatusTypeDef FLASH_OB_PCROP_RDP_Config(uint32_t Pcrop_Rdp)
<> 161:2cc1468da177 1086 {
<> 161:2cc1468da177 1087 HAL_StatusTypeDef status = HAL_OK;
<> 161:2cc1468da177 1088
<> 161:2cc1468da177 1089 /* Check the parameters */
<> 161:2cc1468da177 1090 assert_param(IS_OB_PCROP_RDP_VALUE(Pcrop_Rdp));
<> 161:2cc1468da177 1091
<> 161:2cc1468da177 1092 /* Wait for last operation to be completed */
<> 161:2cc1468da177 1093 status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
<> 161:2cc1468da177 1094
<> 161:2cc1468da177 1095 if(status == HAL_OK)
<> 161:2cc1468da177 1096 {
<> 161:2cc1468da177 1097 MODIFY_REG(FLASH->OPTCR2, FLASH_OPTCR2_PCROP_RDP, Pcrop_Rdp);
<> 161:2cc1468da177 1098 }
<> 161:2cc1468da177 1099
<> 161:2cc1468da177 1100 return status;
<> 161:2cc1468da177 1101 }
<> 161:2cc1468da177 1102
<> 161:2cc1468da177 1103 /**
<> 161:2cc1468da177 1104 * @brief Return the FLASH PCROP Protection Option Bytes value.
<> 161:2cc1468da177 1105 * @retval uint32_t FLASH PCROP Protection Option Bytes value
<> 161:2cc1468da177 1106 */
<> 161:2cc1468da177 1107 static uint32_t FLASH_OB_GetPCROP(void)
<> 161:2cc1468da177 1108 {
<> 161:2cc1468da177 1109 /* Return the FLASH write protection Register value */
<> 161:2cc1468da177 1110 return ((uint32_t)(FLASH->OPTCR2 & FLASH_OPTCR2_PCROP));
<> 161:2cc1468da177 1111 }
<> 161:2cc1468da177 1112
<> 161:2cc1468da177 1113 /**
<> 161:2cc1468da177 1114 * @brief Return the FLASH PCROP_RDP option byte value.
<> 161:2cc1468da177 1115 * @retval uint32_t FLASH PCROP_RDP option byte value
<> 161:2cc1468da177 1116 */
<> 161:2cc1468da177 1117 static uint32_t FLASH_OB_GetPCROPRDP(void)
<> 161:2cc1468da177 1118 {
<> 161:2cc1468da177 1119 /* Return the FLASH write protection Register value */
<> 161:2cc1468da177 1120 return ((uint32_t)(FLASH->OPTCR2 & FLASH_OPTCR2_PCROP_RDP));
<> 161:2cc1468da177 1121 }
<> 161:2cc1468da177 1122 #endif /* FLASH_OPTCR2_PCROP */
<> 161:2cc1468da177 1123
<> 144:ef7eb2e8f9f7 1124 /**
<> 144:ef7eb2e8f9f7 1125 * @}
<> 144:ef7eb2e8f9f7 1126 */
<> 144:ef7eb2e8f9f7 1127
<> 144:ef7eb2e8f9f7 1128 #endif /* HAL_FLASH_MODULE_ENABLED */
<> 144:ef7eb2e8f9f7 1129
<> 144:ef7eb2e8f9f7 1130 /**
<> 144:ef7eb2e8f9f7 1131 * @}
<> 144:ef7eb2e8f9f7 1132 */
<> 144:ef7eb2e8f9f7 1133
<> 144:ef7eb2e8f9f7 1134 /**
<> 144:ef7eb2e8f9f7 1135 * @}
<> 144:ef7eb2e8f9f7 1136 */
<> 144:ef7eb2e8f9f7 1137
<> 144:ef7eb2e8f9f7 1138 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/