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targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/gic.h@0:9b334a45a8ff, 2015-10-01 (annotated)

Committer:
bogdanm
Date:
Thu Oct 01 15:25:22 2015 +0300
Revision:
0:9b334a45a8ff
Child:
144:ef7eb2e8f9f7
Initial commit on mbed-dev



Replaces mbed-src (now inactive)

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 0:9b334a45a8ff 1 /**************************************************************************//**
bogdanm 0:9b334a45a8ff 2 * @file gic.h
bogdanm 0:9b334a45a8ff 3 * @brief Implementation of GIC functions declared in CMSIS Cortex-A9 Core Peripheral Access Layer Header File
bogdanm 0:9b334a45a8ff 4 * @version
bogdanm 0:9b334a45a8ff 5 * @date 29 August 2013
bogdanm 0:9b334a45a8ff 6 *
bogdanm 0:9b334a45a8ff 7 * @note
bogdanm 0:9b334a45a8ff 8 *
bogdanm 0:9b334a45a8ff 9 ******************************************************************************/
bogdanm 0:9b334a45a8ff 10 /* Copyright (c) 2011 - 2013 ARM LIMITED
bogdanm 0:9b334a45a8ff 11
bogdanm 0:9b334a45a8ff 12 All rights reserved.
bogdanm 0:9b334a45a8ff 13 Redistribution and use in source and binary forms, with or without
bogdanm 0:9b334a45a8ff 14 modification, are permitted provided that the following conditions are met:
bogdanm 0:9b334a45a8ff 15 - Redistributions of source code must retain the above copyright
bogdanm 0:9b334a45a8ff 16 notice, this list of conditions and the following disclaimer.
bogdanm 0:9b334a45a8ff 17 - Redistributions in binary form must reproduce the above copyright
bogdanm 0:9b334a45a8ff 18 notice, this list of conditions and the following disclaimer in the
bogdanm 0:9b334a45a8ff 19 documentation and/or other materials provided with the distribution.
bogdanm 0:9b334a45a8ff 20 - Neither the name of ARM nor the names of its contributors may be used
bogdanm 0:9b334a45a8ff 21 to endorse or promote products derived from this software without
bogdanm 0:9b334a45a8ff 22 specific prior written permission.
bogdanm 0:9b334a45a8ff 23 *
bogdanm 0:9b334a45a8ff 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 0:9b334a45a8ff 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 0:9b334a45a8ff 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
bogdanm 0:9b334a45a8ff 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
bogdanm 0:9b334a45a8ff 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
bogdanm 0:9b334a45a8ff 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
bogdanm 0:9b334a45a8ff 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
bogdanm 0:9b334a45a8ff 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
bogdanm 0:9b334a45a8ff 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
bogdanm 0:9b334a45a8ff 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
bogdanm 0:9b334a45a8ff 34 POSSIBILITY OF SUCH DAMAGE.
bogdanm 0:9b334a45a8ff 35 ---------------------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 36
bogdanm 0:9b334a45a8ff 37 #ifndef GIC_H_
bogdanm 0:9b334a45a8ff 38 #define GIC_H_
bogdanm 0:9b334a45a8ff 39
bogdanm 0:9b334a45a8ff 40 /* IO definitions (access restrictions to peripheral registers) */
bogdanm 0:9b334a45a8ff 41 /**
bogdanm 0:9b334a45a8ff 42 */
bogdanm 0:9b334a45a8ff 43 #ifdef __cplusplus
bogdanm 0:9b334a45a8ff 44 #define __I volatile /*!< Defines 'read only' permissions */
bogdanm 0:9b334a45a8ff 45 #else
bogdanm 0:9b334a45a8ff 46 #define __I volatile const /*!< Defines 'read only' permissions */
bogdanm 0:9b334a45a8ff 47 #endif
bogdanm 0:9b334a45a8ff 48 #define __O volatile /*!< Defines 'write only' permissions */
bogdanm 0:9b334a45a8ff 49 #define __IO volatile /*!< Defines 'read / write' permissions */
bogdanm 0:9b334a45a8ff 50
bogdanm 0:9b334a45a8ff 51 /** \brief Structure type to access the Generic Interrupt Controller Distributor (GICD)
bogdanm 0:9b334a45a8ff 52 */
bogdanm 0:9b334a45a8ff 53 typedef struct
bogdanm 0:9b334a45a8ff 54 {
bogdanm 0:9b334a45a8ff 55 __IO uint32_t ICDDCR;
bogdanm 0:9b334a45a8ff 56 __I uint32_t ICDICTR;
bogdanm 0:9b334a45a8ff 57 __I uint32_t ICDIIDR;
bogdanm 0:9b334a45a8ff 58 uint32_t RESERVED0[29];
bogdanm 0:9b334a45a8ff 59 __IO uint32_t ICDISR[32];
bogdanm 0:9b334a45a8ff 60 __IO uint32_t ICDISER[32];
bogdanm 0:9b334a45a8ff 61 __IO uint32_t ICDICER[32];
bogdanm 0:9b334a45a8ff 62 __IO uint32_t ICDISPR[32];
bogdanm 0:9b334a45a8ff 63 __IO uint32_t ICDICPR[32];
bogdanm 0:9b334a45a8ff 64 __I uint32_t ICDABR[32];
bogdanm 0:9b334a45a8ff 65 uint32_t RESERVED1[32];
bogdanm 0:9b334a45a8ff 66 __IO uint32_t ICDIPR[256];
bogdanm 0:9b334a45a8ff 67 __IO uint32_t ICDIPTR[256];
bogdanm 0:9b334a45a8ff 68 __IO uint32_t ICDICFR[64];
bogdanm 0:9b334a45a8ff 69 uint32_t RESERVED2[128];
bogdanm 0:9b334a45a8ff 70 __IO uint32_t ICDSGIR;
bogdanm 0:9b334a45a8ff 71 } GICDistributor_Type;
bogdanm 0:9b334a45a8ff 72
bogdanm 0:9b334a45a8ff 73 /** \brief Structure type to access the Controller Interface (GICC)
bogdanm 0:9b334a45a8ff 74 */
bogdanm 0:9b334a45a8ff 75 typedef struct
bogdanm 0:9b334a45a8ff 76 {
bogdanm 0:9b334a45a8ff 77 __IO uint32_t ICCICR; // +0x000 - RW - CPU Interface Control Register
bogdanm 0:9b334a45a8ff 78 __IO uint32_t ICCPMR; // +0x004 - RW - Interrupt Priority Mask Register
bogdanm 0:9b334a45a8ff 79 __IO uint32_t ICCBPR; // +0x008 - RW - Binary Point Register
bogdanm 0:9b334a45a8ff 80 __I uint32_t ICCIAR; // +0x00C - RO - Interrupt Acknowledge Register
bogdanm 0:9b334a45a8ff 81 __IO uint32_t ICCEOIR; // +0x010 - WO - End of Interrupt Register
bogdanm 0:9b334a45a8ff 82 __I uint32_t ICCRPR; // +0x014 - RO - Running Priority Register
bogdanm 0:9b334a45a8ff 83 __I uint32_t ICCHPIR; // +0x018 - RO - Highest Pending Interrupt Register
bogdanm 0:9b334a45a8ff 84 __IO uint32_t ICCABPR; // +0x01C - RW - Aliased Binary Point Register
bogdanm 0:9b334a45a8ff 85
bogdanm 0:9b334a45a8ff 86 uint32_t RESERVED[55];
bogdanm 0:9b334a45a8ff 87
bogdanm 0:9b334a45a8ff 88 __I uint32_t ICCIIDR; // +0x0FC - RO - CPU Interface Identification Register
bogdanm 0:9b334a45a8ff 89 } GICInterface_Type;
bogdanm 0:9b334a45a8ff 90
bogdanm 0:9b334a45a8ff 91 /*@} end of GICD */
bogdanm 0:9b334a45a8ff 92
bogdanm 0:9b334a45a8ff 93 /* ########################## GIC functions #################################### */
bogdanm 0:9b334a45a8ff 94 /** \brief Functions that manage interrupts via the GIC.
bogdanm 0:9b334a45a8ff 95 @{
bogdanm 0:9b334a45a8ff 96 */
bogdanm 0:9b334a45a8ff 97
bogdanm 0:9b334a45a8ff 98 /** \brief Enable DistributorGICInterface->ICCICR |= 1; //enable interface
bogdanm 0:9b334a45a8ff 99
bogdanm 0:9b334a45a8ff 100 Enables the forwarding of pending interrupts to the CPU interfaces.
bogdanm 0:9b334a45a8ff 101
bogdanm 0:9b334a45a8ff 102 */
bogdanm 0:9b334a45a8ff 103 void GIC_EnableDistributor(void);
bogdanm 0:9b334a45a8ff 104
bogdanm 0:9b334a45a8ff 105 /** \brief Disable Distributor
bogdanm 0:9b334a45a8ff 106
bogdanm 0:9b334a45a8ff 107 Disables the forwarding of pending interrupts to the CPU interfaces.
bogdanm 0:9b334a45a8ff 108
bogdanm 0:9b334a45a8ff 109 */
bogdanm 0:9b334a45a8ff 110 void GIC_DisableDistributor(void);
bogdanm 0:9b334a45a8ff 111
bogdanm 0:9b334a45a8ff 112 /** \brief Provides information about the configuration of the GIC.
bogdanm 0:9b334a45a8ff 113 Provides information about the configuration of the GIC.
bogdanm 0:9b334a45a8ff 114 - whether the GIC implements the Security Extensions
bogdanm 0:9b334a45a8ff 115 - the maximum number of interrupt IDs that the GIC supports
bogdanm 0:9b334a45a8ff 116 - the number of CPU interfaces implemented
bogdanm 0:9b334a45a8ff 117 - if the GIC implements the Security Extensions, the maximum number of implemented Lockable Shared Peripheral Interrupts (LSPIs).
bogdanm 0:9b334a45a8ff 118
bogdanm 0:9b334a45a8ff 119 \return Distributor Information.
bogdanm 0:9b334a45a8ff 120 */
bogdanm 0:9b334a45a8ff 121 uint32_t GIC_DistributorInfo(void);
bogdanm 0:9b334a45a8ff 122
bogdanm 0:9b334a45a8ff 123 /** \brief Distributor Implementer Identification Register.
bogdanm 0:9b334a45a8ff 124
bogdanm 0:9b334a45a8ff 125 Distributor Implementer Identification Register
bogdanm 0:9b334a45a8ff 126
bogdanm 0:9b334a45a8ff 127 \return Implementer Information.
bogdanm 0:9b334a45a8ff 128 */
bogdanm 0:9b334a45a8ff 129 uint32_t GIC_DistributorImplementer(void);
bogdanm 0:9b334a45a8ff 130
bogdanm 0:9b334a45a8ff 131 /** \brief Set list of processors that the interrupt is sent to if it is asserted.
bogdanm 0:9b334a45a8ff 132
bogdanm 0:9b334a45a8ff 133 The ICDIPTRs provide an 8-bit CPU targets field for each interrupt supported by the GIC.
bogdanm 0:9b334a45a8ff 134 This field stores the list of processors that the interrupt is sent to if it is asserted.
bogdanm 0:9b334a45a8ff 135
bogdanm 0:9b334a45a8ff 136 \param [in] IRQn Interrupt number.
bogdanm 0:9b334a45a8ff 137 \param [in] target CPU target
bogdanm 0:9b334a45a8ff 138 */
bogdanm 0:9b334a45a8ff 139 void GIC_SetTarget(IRQn_Type IRQn, uint32_t cpu_target);
bogdanm 0:9b334a45a8ff 140
bogdanm 0:9b334a45a8ff 141 /** \brief Get list of processors that the interrupt is sent to if it is asserted.
bogdanm 0:9b334a45a8ff 142
bogdanm 0:9b334a45a8ff 143 The ICDIPTRs provide an 8-bit CPU targets field for each interrupt supported by the GIC.
bogdanm 0:9b334a45a8ff 144 This field stores the list of processors that the interrupt is sent to if it is asserted.
bogdanm 0:9b334a45a8ff 145
bogdanm 0:9b334a45a8ff 146 \param [in] IRQn Interrupt number.
bogdanm 0:9b334a45a8ff 147 \param [in] target CPU target
bogdanm 0:9b334a45a8ff 148 */
bogdanm 0:9b334a45a8ff 149 uint32_t GIC_GetTarget(IRQn_Type IRQn);
bogdanm 0:9b334a45a8ff 150
bogdanm 0:9b334a45a8ff 151 /** \brief Enable Interface
bogdanm 0:9b334a45a8ff 152
bogdanm 0:9b334a45a8ff 153 Enables the signalling of interrupts to the target processors.
bogdanm 0:9b334a45a8ff 154
bogdanm 0:9b334a45a8ff 155 */
bogdanm 0:9b334a45a8ff 156 void GIC_EnableInterface(void);
bogdanm 0:9b334a45a8ff 157
bogdanm 0:9b334a45a8ff 158 /** \brief Disable Interface
bogdanm 0:9b334a45a8ff 159
bogdanm 0:9b334a45a8ff 160 Disables the signalling of interrupts to the target processors.
bogdanm 0:9b334a45a8ff 161
bogdanm 0:9b334a45a8ff 162 */
bogdanm 0:9b334a45a8ff 163 void GIC_DisableInterface(void);
bogdanm 0:9b334a45a8ff 164
bogdanm 0:9b334a45a8ff 165 /** \brief Acknowledge Interrupt
bogdanm 0:9b334a45a8ff 166
bogdanm 0:9b334a45a8ff 167 The function acknowledges the highest priority pending interrupt and returns its IRQ number.
bogdanm 0:9b334a45a8ff 168
bogdanm 0:9b334a45a8ff 169 \return Interrupt number
bogdanm 0:9b334a45a8ff 170 */
bogdanm 0:9b334a45a8ff 171 IRQn_Type GIC_AcknowledgePending(void);
bogdanm 0:9b334a45a8ff 172
bogdanm 0:9b334a45a8ff 173 /** \brief End Interrupt
bogdanm 0:9b334a45a8ff 174
bogdanm 0:9b334a45a8ff 175 The function writes the end of interrupt register, indicating that handling of the interrupt is complete.
bogdanm 0:9b334a45a8ff 176
bogdanm 0:9b334a45a8ff 177 \param [in] IRQn Interrupt number.
bogdanm 0:9b334a45a8ff 178 */
bogdanm 0:9b334a45a8ff 179 void GIC_EndInterrupt(IRQn_Type IRQn);
bogdanm 0:9b334a45a8ff 180
bogdanm 0:9b334a45a8ff 181
bogdanm 0:9b334a45a8ff 182 /** \brief Enable Interrupt
bogdanm 0:9b334a45a8ff 183
bogdanm 0:9b334a45a8ff 184 Set-enable bit for each interrupt supported by the GIC.
bogdanm 0:9b334a45a8ff 185
bogdanm 0:9b334a45a8ff 186 \param [in] IRQn External interrupt number.
bogdanm 0:9b334a45a8ff 187 */
bogdanm 0:9b334a45a8ff 188 void GIC_EnableIRQ(IRQn_Type IRQn);
bogdanm 0:9b334a45a8ff 189
bogdanm 0:9b334a45a8ff 190 /** \brief Disable Interrupt
bogdanm 0:9b334a45a8ff 191
bogdanm 0:9b334a45a8ff 192 Clear-enable bit for each interrupt supported by the GIC.
bogdanm 0:9b334a45a8ff 193
bogdanm 0:9b334a45a8ff 194 \param [in] IRQn Number of the external interrupt to disable
bogdanm 0:9b334a45a8ff 195 */
bogdanm 0:9b334a45a8ff 196 void GIC_DisableIRQ(IRQn_Type IRQn);
bogdanm 0:9b334a45a8ff 197
bogdanm 0:9b334a45a8ff 198 /** \brief Set Pending Interrupt
bogdanm 0:9b334a45a8ff 199
bogdanm 0:9b334a45a8ff 200 Set-pending bit for each interrupt supported by the GIC.
bogdanm 0:9b334a45a8ff 201
bogdanm 0:9b334a45a8ff 202 \param [in] IRQn Interrupt number.
bogdanm 0:9b334a45a8ff 203 */
bogdanm 0:9b334a45a8ff 204 void GIC_SetPendingIRQ(IRQn_Type IRQn);
bogdanm 0:9b334a45a8ff 205
bogdanm 0:9b334a45a8ff 206 /** \brief Clear Pending Interrupt
bogdanm 0:9b334a45a8ff 207
bogdanm 0:9b334a45a8ff 208 Clear-pending bit for each interrupt supported by the GIC
bogdanm 0:9b334a45a8ff 209
bogdanm 0:9b334a45a8ff 210 \param [in] IRQn Number of the interrupt for clear pending
bogdanm 0:9b334a45a8ff 211 */
bogdanm 0:9b334a45a8ff 212 void GIC_ClearPendingIRQ(IRQn_Type IRQn);
bogdanm 0:9b334a45a8ff 213
bogdanm 0:9b334a45a8ff 214 /** \brief Int_config field for each interrupt supported by the GIC.
bogdanm 0:9b334a45a8ff 215
bogdanm 0:9b334a45a8ff 216 This field identifies whether the corresponding interrupt is:
bogdanm 0:9b334a45a8ff 217 (1) edge-triggered or (0) level-sensitive
bogdanm 0:9b334a45a8ff 218 (1) 1-N model or (0) N-N model
bogdanm 0:9b334a45a8ff 219
bogdanm 0:9b334a45a8ff 220 \param [in] IRQn Interrupt number.
bogdanm 0:9b334a45a8ff 221 \param [in] edge_level (1) edge-triggered or (0) level-sensitive
bogdanm 0:9b334a45a8ff 222 \param [in] model (1) 1-N model or (0) N-N model
bogdanm 0:9b334a45a8ff 223 */
bogdanm 0:9b334a45a8ff 224 void GIC_SetLevelModel(IRQn_Type IRQn, int8_t edge_level, int8_t model);
bogdanm 0:9b334a45a8ff 225
bogdanm 0:9b334a45a8ff 226
bogdanm 0:9b334a45a8ff 227 /** \brief Set Interrupt Priority
bogdanm 0:9b334a45a8ff 228
bogdanm 0:9b334a45a8ff 229 The function sets the priority of an interrupt.
bogdanm 0:9b334a45a8ff 230
bogdanm 0:9b334a45a8ff 231 \param [in] IRQn Interrupt number.
bogdanm 0:9b334a45a8ff 232 \param [in] priority Priority to set.
bogdanm 0:9b334a45a8ff 233 */
bogdanm 0:9b334a45a8ff 234 void GIC_SetPriority(IRQn_Type IRQn, uint32_t priority);
bogdanm 0:9b334a45a8ff 235
bogdanm 0:9b334a45a8ff 236 /** \brief Get Interrupt Priority
bogdanm 0:9b334a45a8ff 237
bogdanm 0:9b334a45a8ff 238 The function reads the priority of an interrupt.
bogdanm 0:9b334a45a8ff 239
bogdanm 0:9b334a45a8ff 240 \param [in] IRQn Interrupt number.
bogdanm 0:9b334a45a8ff 241 \return Interrupt Priority.
bogdanm 0:9b334a45a8ff 242 */
bogdanm 0:9b334a45a8ff 243 uint32_t GIC_GetPriority(IRQn_Type IRQn);
bogdanm 0:9b334a45a8ff 244
bogdanm 0:9b334a45a8ff 245 /** \brief CPU Interface Priority Mask Register
bogdanm 0:9b334a45a8ff 246
bogdanm 0:9b334a45a8ff 247 The priority mask level for the CPU interface. If the priority of an interrupt is higher than the
bogdanm 0:9b334a45a8ff 248 value indicated by this field, the interface signals the interrupt to the processor.
bogdanm 0:9b334a45a8ff 249
bogdanm 0:9b334a45a8ff 250 \param [in] Mask.
bogdanm 0:9b334a45a8ff 251 */
bogdanm 0:9b334a45a8ff 252 void GIC_InterfacePriorityMask(uint32_t priority);
bogdanm 0:9b334a45a8ff 253
bogdanm 0:9b334a45a8ff 254 /** \brief Set the binary point.
bogdanm 0:9b334a45a8ff 255
bogdanm 0:9b334a45a8ff 256 Set the point at which the priority value fields split into two parts, the group priority field and the subpriority field.
bogdanm 0:9b334a45a8ff 257
bogdanm 0:9b334a45a8ff 258 \param [in] Mask.
bogdanm 0:9b334a45a8ff 259 */
bogdanm 0:9b334a45a8ff 260 void GIC_SetBinaryPoint(uint32_t binary_point);
bogdanm 0:9b334a45a8ff 261
bogdanm 0:9b334a45a8ff 262 /** \brief Get the binary point.
bogdanm 0:9b334a45a8ff 263
bogdanm 0:9b334a45a8ff 264 Get the point at which the priority value fields split into two parts, the group priority field and the subpriority field.
bogdanm 0:9b334a45a8ff 265
bogdanm 0:9b334a45a8ff 266 \return Binary point.
bogdanm 0:9b334a45a8ff 267 */
bogdanm 0:9b334a45a8ff 268 uint32_t GIC_GetBinaryPoint(uint32_t binary_point);
bogdanm 0:9b334a45a8ff 269
bogdanm 0:9b334a45a8ff 270 /** \brief Get Interrupt state.
bogdanm 0:9b334a45a8ff 271
bogdanm 0:9b334a45a8ff 272 Get the interrupt state, whether pending and/or active
bogdanm 0:9b334a45a8ff 273
bogdanm 0:9b334a45a8ff 274 \return 0 - inactive, 1 - pending, 2 - active, 3 - pending and active
bogdanm 0:9b334a45a8ff 275 */
bogdanm 0:9b334a45a8ff 276 uint32_t GIC_GetIRQStatus(IRQn_Type IRQn);
bogdanm 0:9b334a45a8ff 277
bogdanm 0:9b334a45a8ff 278 /** \brief Send Software Generated interrupt
bogdanm 0:9b334a45a8ff 279
bogdanm 0:9b334a45a8ff 280 Provides an interrupt priority filter. Only interrupts with higher priority than the value in this register can be signalled to the processor.
bogdanm 0:9b334a45a8ff 281 GIC_InterfacePriorityMask
bogdanm 0:9b334a45a8ff 282 \param [in] IRQn The Interrupt ID of the SGI.
bogdanm 0:9b334a45a8ff 283 \param [in] target_list CPUTargetList
bogdanm 0:9b334a45a8ff 284 \param [in] filter_list TargetListFilter
bogdanm 0:9b334a45a8ff 285 */
bogdanm 0:9b334a45a8ff 286 void GIC_SendSGI(IRQn_Type IRQn, uint32_t target_list, uint32_t filter_list);
bogdanm 0:9b334a45a8ff 287
bogdanm 0:9b334a45a8ff 288 /** \brief API call to initialise the interrupt distributor
bogdanm 0:9b334a45a8ff 289
bogdanm 0:9b334a45a8ff 290 API call to initialise the interrupt distributor
bogdanm 0:9b334a45a8ff 291
bogdanm 0:9b334a45a8ff 292 */
bogdanm 0:9b334a45a8ff 293 void GIC_DistInit(void);
bogdanm 0:9b334a45a8ff 294
bogdanm 0:9b334a45a8ff 295 /** \brief API call to initialise the CPU interface
bogdanm 0:9b334a45a8ff 296
bogdanm 0:9b334a45a8ff 297 API call to initialise the CPU interface
bogdanm 0:9b334a45a8ff 298
bogdanm 0:9b334a45a8ff 299 */
bogdanm 0:9b334a45a8ff 300 void GIC_CPUInterfaceInit(void);
bogdanm 0:9b334a45a8ff 301
bogdanm 0:9b334a45a8ff 302 /** \brief API call to set the Interrupt Configuration Registers
bogdanm 0:9b334a45a8ff 303
bogdanm 0:9b334a45a8ff 304 API call to initialise the Interrupt Configuration Registers
bogdanm 0:9b334a45a8ff 305
bogdanm 0:9b334a45a8ff 306 */
bogdanm 0:9b334a45a8ff 307 void GIC_SetICDICFR (const uint32_t *ICDICFRn);
bogdanm 0:9b334a45a8ff 308
bogdanm 0:9b334a45a8ff 309 /** \brief API call to Enable the GIC
bogdanm 0:9b334a45a8ff 310
bogdanm 0:9b334a45a8ff 311 API call to Enable the GIC
bogdanm 0:9b334a45a8ff 312
bogdanm 0:9b334a45a8ff 313 */
bogdanm 0:9b334a45a8ff 314 void GIC_Enable(void);
bogdanm 0:9b334a45a8ff 315
bogdanm 0:9b334a45a8ff 316 #endif /* GIC_H_ */