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targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/config/adi_sport_config.h@178:79309dc6340a, 2017-11-23 (annotated)
- Committer:
- AnnaBridge
- Date:
- Thu Nov 23 11:57:25 2017 +0000
- Revision:
- 178:79309dc6340a
mbed-dev library. Release version 156
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| AnnaBridge | 178:79309dc6340a | 1 | /*! **************************************************************************** |
| AnnaBridge | 178:79309dc6340a | 2 | * @file adi_sport_config.h |
| AnnaBridge | 178:79309dc6340a | 3 | * @brief Configuration options for SPORT driver. |
| AnnaBridge | 178:79309dc6340a | 4 | * @details This is specific to the SPORT driver and will be included by the |
| AnnaBridge | 178:79309dc6340a | 5 | * driver. It is not required for the application to include this |
| AnnaBridge | 178:79309dc6340a | 6 | * header file. |
| AnnaBridge | 178:79309dc6340a | 7 | ----------------------------------------------------------------------------- |
| AnnaBridge | 178:79309dc6340a | 8 | Copyright (c) 2016 Analog Devices, Inc. |
| AnnaBridge | 178:79309dc6340a | 9 | |
| AnnaBridge | 178:79309dc6340a | 10 | All rights reserved. |
| AnnaBridge | 178:79309dc6340a | 11 | |
| AnnaBridge | 178:79309dc6340a | 12 | Redistribution and use in source and binary forms, with or without modification, |
| AnnaBridge | 178:79309dc6340a | 13 | are permitted provided that the following conditions are met: |
| AnnaBridge | 178:79309dc6340a | 14 | - Redistributions of source code must retain the above copyright notice, |
| AnnaBridge | 178:79309dc6340a | 15 | this list of conditions and the following disclaimer. |
| AnnaBridge | 178:79309dc6340a | 16 | - Redistributions in binary form must reproduce the above copyright notice, |
| AnnaBridge | 178:79309dc6340a | 17 | this list of conditions and the following disclaimer in the documentation |
| AnnaBridge | 178:79309dc6340a | 18 | and/or other materials provided with the distribution. |
| AnnaBridge | 178:79309dc6340a | 19 | - Modified versions of the software must be conspicuously marked as such. |
| AnnaBridge | 178:79309dc6340a | 20 | - This software is licensed solely and exclusively for use with processors |
| AnnaBridge | 178:79309dc6340a | 21 | manufactured by or for Analog Devices, Inc. |
| AnnaBridge | 178:79309dc6340a | 22 | - This software may not be combined or merged with other code in any manner |
| AnnaBridge | 178:79309dc6340a | 23 | that would cause the software to become subject to terms and conditions |
| AnnaBridge | 178:79309dc6340a | 24 | which differ from those listed here. |
| AnnaBridge | 178:79309dc6340a | 25 | - Neither the name of Analog Devices, Inc. nor the names of its |
| AnnaBridge | 178:79309dc6340a | 26 | contributors may be used to endorse or promote products derived |
| AnnaBridge | 178:79309dc6340a | 27 | from this software without specific prior written permission. |
| AnnaBridge | 178:79309dc6340a | 28 | - The use of this software may or may not infringe the patent rights of one |
| AnnaBridge | 178:79309dc6340a | 29 | or more patent holders. This license does not release you from the |
| AnnaBridge | 178:79309dc6340a | 30 | requirement that you obtain separate licenses from these patent holders |
| AnnaBridge | 178:79309dc6340a | 31 | to use this software. |
| AnnaBridge | 178:79309dc6340a | 32 | |
| AnnaBridge | 178:79309dc6340a | 33 | THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" AND ANY |
| AnnaBridge | 178:79309dc6340a | 34 | EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, |
| AnnaBridge | 178:79309dc6340a | 35 | TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN |
| AnnaBridge | 178:79309dc6340a | 36 | NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, |
| AnnaBridge | 178:79309dc6340a | 37 | INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR CONSEQUENTIAL DAMAGES |
| AnnaBridge | 178:79309dc6340a | 38 | (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF CLAIMS OF INTELLECTUAL |
| AnnaBridge | 178:79309dc6340a | 39 | PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS |
| AnnaBridge | 178:79309dc6340a | 40 | OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
| AnnaBridge | 178:79309dc6340a | 41 | THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING |
| AnnaBridge | 178:79309dc6340a | 42 | NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, |
| AnnaBridge | 178:79309dc6340a | 43 | EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| AnnaBridge | 178:79309dc6340a | 44 | |
| AnnaBridge | 178:79309dc6340a | 45 | *******************************************************************************/ |
| AnnaBridge | 178:79309dc6340a | 46 | #ifndef ADI_SPORT_CONFIG_H |
| AnnaBridge | 178:79309dc6340a | 47 | #define ADI_SPORT_CONFIG_H |
| AnnaBridge | 178:79309dc6340a | 48 | #include <adi_global_config.h> |
| AnnaBridge | 178:79309dc6340a | 49 | |
| AnnaBridge | 178:79309dc6340a | 50 | /** @addtogroup SPORT_Driver_Config Static Configuration |
| AnnaBridge | 178:79309dc6340a | 51 | * @ingroup SPORT_Driver |
| AnnaBridge | 178:79309dc6340a | 52 | * @{ |
| AnnaBridge | 178:79309dc6340a | 53 | */ |
| AnnaBridge | 178:79309dc6340a | 54 | |
| AnnaBridge | 178:79309dc6340a | 55 | /************* SPORT Driver configurations FOR SPORT-0-A ***************/ |
| AnnaBridge | 178:79309dc6340a | 56 | /*! |
| AnnaBridge | 178:79309dc6340a | 57 | Frame Sync Multiplexer Select.\n |
| AnnaBridge | 178:79309dc6340a | 58 | 0 - Disable frame sync multiplexing\n |
| AnnaBridge | 178:79309dc6340a | 59 | 1 - Enable frame sync multiplexing. |
| AnnaBridge | 178:79309dc6340a | 60 | */ |
| AnnaBridge | 178:79309dc6340a | 61 | #define ADI_CFG_SPORT0A_ENABLE_FSMUXSEL (0u) |
| AnnaBridge | 178:79309dc6340a | 62 | |
| AnnaBridge | 178:79309dc6340a | 63 | /*! |
| AnnaBridge | 178:79309dc6340a | 64 | Clock Multiplexer Select.\n |
| AnnaBridge | 178:79309dc6340a | 65 | 0 - Disable serial clock multiplexing\n |
| AnnaBridge | 178:79309dc6340a | 66 | 1 - Enable serial clock multiplexing. |
| AnnaBridge | 178:79309dc6340a | 67 | */ |
| AnnaBridge | 178:79309dc6340a | 68 | #define ADI_CFG_SPORT0A_ENABLE_CKMUXSEL (1u) |
| AnnaBridge | 178:79309dc6340a | 69 | |
| AnnaBridge | 178:79309dc6340a | 70 | /*! |
| AnnaBridge | 178:79309dc6340a | 71 | Least-Significant Bit First.\n |
| AnnaBridge | 178:79309dc6340a | 72 | 0 - MSB first sent/received.\n |
| AnnaBridge | 178:79309dc6340a | 73 | 1 - LSB first sent/received. |
| AnnaBridge | 178:79309dc6340a | 74 | */ |
| AnnaBridge | 178:79309dc6340a | 75 | #define ADI_CFG_SPORT0A_LSB_FIRST (0u) |
| AnnaBridge | 178:79309dc6340a | 76 | |
| AnnaBridge | 178:79309dc6340a | 77 | |
| AnnaBridge | 178:79309dc6340a | 78 | /*! |
| AnnaBridge | 178:79309dc6340a | 79 | Serial Word Length in bits.\n |
| AnnaBridge | 178:79309dc6340a | 80 | 1 - 32 - SPORT word length |
| AnnaBridge | 178:79309dc6340a | 81 | */ |
| AnnaBridge | 178:79309dc6340a | 82 | #define ADI_CFG_SPORT0A_SERIAL_WLEN (32u) |
| AnnaBridge | 178:79309dc6340a | 83 | |
| AnnaBridge | 178:79309dc6340a | 84 | |
| AnnaBridge | 178:79309dc6340a | 85 | /*! |
| AnnaBridge | 178:79309dc6340a | 86 | Internal Clock.\n |
| AnnaBridge | 178:79309dc6340a | 87 | 0 - External clock.\n |
| AnnaBridge | 178:79309dc6340a | 88 | 1 - Internal clock. |
| AnnaBridge | 178:79309dc6340a | 89 | */ |
| AnnaBridge | 178:79309dc6340a | 90 | #define ADI_CFG_SPORT0A_INTERNAL_CLK (1u) |
| AnnaBridge | 178:79309dc6340a | 91 | |
| AnnaBridge | 178:79309dc6340a | 92 | /*! |
| AnnaBridge | 178:79309dc6340a | 93 | Operation Mode\n |
| AnnaBridge | 178:79309dc6340a | 94 | 0 - DSP standard.\n |
| AnnaBridge | 178:79309dc6340a | 95 | 1 - Timer_enable mode. |
| AnnaBridge | 178:79309dc6340a | 96 | */ |
| AnnaBridge | 178:79309dc6340a | 97 | #define ADI_CFG_SPORT0A_OPERATION_MODE (0u) |
| AnnaBridge | 178:79309dc6340a | 98 | |
| AnnaBridge | 178:79309dc6340a | 99 | |
| AnnaBridge | 178:79309dc6340a | 100 | /*! |
| AnnaBridge | 178:79309dc6340a | 101 | Clock Rising Edge\n |
| AnnaBridge | 178:79309dc6340a | 102 | 0 - Clock falling edge\n |
| AnnaBridge | 178:79309dc6340a | 103 | 1 - Clock rising edge. |
| AnnaBridge | 178:79309dc6340a | 104 | */ |
| AnnaBridge | 178:79309dc6340a | 105 | #define ADI_CFG_SPORT0A_CLOCK_EDGE (0u) |
| AnnaBridge | 178:79309dc6340a | 106 | |
| AnnaBridge | 178:79309dc6340a | 107 | /*! |
| AnnaBridge | 178:79309dc6340a | 108 | Frame Sync Required\n |
| AnnaBridge | 178:79309dc6340a | 109 | 0 - No frame sync required \n |
| AnnaBridge | 178:79309dc6340a | 110 | 1 - Frame sync required. |
| AnnaBridge | 178:79309dc6340a | 111 | */ |
| AnnaBridge | 178:79309dc6340a | 112 | #define ADI_CFG_SPORT0A_FS_REQUIRED (1u) |
| AnnaBridge | 178:79309dc6340a | 113 | |
| AnnaBridge | 178:79309dc6340a | 114 | /*! |
| AnnaBridge | 178:79309dc6340a | 115 | Internal Frame Sync\n |
| AnnaBridge | 178:79309dc6340a | 116 | 0 - External frame sync\n |
| AnnaBridge | 178:79309dc6340a | 117 | 1 - Internal frame sync |
| AnnaBridge | 178:79309dc6340a | 118 | */ |
| AnnaBridge | 178:79309dc6340a | 119 | #define ADI_CFG_SPORT0A_INTERNAL_FS (0u) |
| AnnaBridge | 178:79309dc6340a | 120 | |
| AnnaBridge | 178:79309dc6340a | 121 | |
| AnnaBridge | 178:79309dc6340a | 122 | /*! |
| AnnaBridge | 178:79309dc6340a | 123 | Data-Independent Frame Sync\n |
| AnnaBridge | 178:79309dc6340a | 124 | 0 - Data-dependent frame sync\n |
| AnnaBridge | 178:79309dc6340a | 125 | 1 - Data-independent frame |
| AnnaBridge | 178:79309dc6340a | 126 | */ |
| AnnaBridge | 178:79309dc6340a | 127 | #define ADI_CFG_SPORT0A_DATA_INDEPENDENT_FS (0u) |
| AnnaBridge | 178:79309dc6340a | 128 | |
| AnnaBridge | 178:79309dc6340a | 129 | /*! |
| AnnaBridge | 178:79309dc6340a | 130 | Active-Low Frame Sync\n |
| AnnaBridge | 178:79309dc6340a | 131 | 0 - Active high frame sync\n |
| AnnaBridge | 178:79309dc6340a | 132 | 1 - Active low frame sync |
| AnnaBridge | 178:79309dc6340a | 133 | */ |
| AnnaBridge | 178:79309dc6340a | 134 | #define ADI_CFG_SPORT0A_ACTIVE_LOW_FS (0u) |
| AnnaBridge | 178:79309dc6340a | 135 | |
| AnnaBridge | 178:79309dc6340a | 136 | /*! |
| AnnaBridge | 178:79309dc6340a | 137 | Late Frame Sync\n |
| AnnaBridge | 178:79309dc6340a | 138 | 0 - Early frame sync\n |
| AnnaBridge | 178:79309dc6340a | 139 | 1 - Late frame sync |
| AnnaBridge | 178:79309dc6340a | 140 | */ |
| AnnaBridge | 178:79309dc6340a | 141 | #define ADI_CFG_SPORT0A_LATE_FS (0u) |
| AnnaBridge | 178:79309dc6340a | 142 | |
| AnnaBridge | 178:79309dc6340a | 143 | /*! |
| AnnaBridge | 178:79309dc6340a | 144 | Enable Packing \n |
| AnnaBridge | 178:79309dc6340a | 145 | 0 - Disable\n |
| AnnaBridge | 178:79309dc6340a | 146 | 1 - 8-bit packing enable\n |
| AnnaBridge | 178:79309dc6340a | 147 | 2 - 16-bit packing enable |
| AnnaBridge | 178:79309dc6340a | 148 | */ |
| AnnaBridge | 178:79309dc6340a | 149 | #define ADI_CFG_SPORT0A_ENABLE_PACKING (0u) |
| AnnaBridge | 178:79309dc6340a | 150 | |
| AnnaBridge | 178:79309dc6340a | 151 | /*! |
| AnnaBridge | 178:79309dc6340a | 152 | Frame Sync Error Operation |
| AnnaBridge | 178:79309dc6340a | 153 | 0 - Flag the Frame Sync error\n |
| AnnaBridge | 178:79309dc6340a | 154 | 1 - When frame Sync error occurs, discard the receive data |
| AnnaBridge | 178:79309dc6340a | 155 | */ |
| AnnaBridge | 178:79309dc6340a | 156 | #define ADI_CFG_SPORT0A_FS_ERROR_OPERATION (1u) |
| AnnaBridge | 178:79309dc6340a | 157 | |
| AnnaBridge | 178:79309dc6340a | 158 | /*! |
| AnnaBridge | 178:79309dc6340a | 159 | Enabling Gated Clock\n |
| AnnaBridge | 178:79309dc6340a | 160 | 0 - Disable Gated Clock\n |
| AnnaBridge | 178:79309dc6340a | 161 | 1 - Enable Gated Clock |
| AnnaBridge | 178:79309dc6340a | 162 | */ |
| AnnaBridge | 178:79309dc6340a | 163 | #define ADI_CFG_SPORT0A_GATED_CLOCK (0u) |
| AnnaBridge | 178:79309dc6340a | 164 | |
| AnnaBridge | 178:79309dc6340a | 165 | /*! |
| AnnaBridge | 178:79309dc6340a | 166 | Serial Clock divisor.\n |
| AnnaBridge | 178:79309dc6340a | 167 | 0 - 65535 - Serial Clock Divisor which SPORT device use to calculate the serial |
| AnnaBridge | 178:79309dc6340a | 168 | clock (ACLK) from the processor system clock (PCLK). |
| AnnaBridge | 178:79309dc6340a | 169 | */ |
| AnnaBridge | 178:79309dc6340a | 170 | #define ADI_CFG_SPORT0A_CLOCK_DIVISOR (2u) |
| AnnaBridge | 178:79309dc6340a | 171 | |
| AnnaBridge | 178:79309dc6340a | 172 | /*! |
| AnnaBridge | 178:79309dc6340a | 173 | Frame Sync Divisor.\n |
| AnnaBridge | 178:79309dc6340a | 174 | 0 - 128 - Frame Sync Divisor which select the number of transmit or receive clock |
| AnnaBridge | 178:79309dc6340a | 175 | cycles that the half SPORT counts before generating a frame sync pulse. |
| AnnaBridge | 178:79309dc6340a | 176 | */ |
| AnnaBridge | 178:79309dc6340a | 177 | #define ADI_CFG_SPORT0A_FS_DIVISOR (0x40u) |
| AnnaBridge | 178:79309dc6340a | 178 | |
| AnnaBridge | 178:79309dc6340a | 179 | |
| AnnaBridge | 178:79309dc6340a | 180 | /*! |
| AnnaBridge | 178:79309dc6340a | 181 | CONVT to FS duration.\n |
| AnnaBridge | 178:79309dc6340a | 182 | 0 - 128 - Specify the value of the number of clocks which would be programmed |
| AnnaBridge | 178:79309dc6340a | 183 | corresponding to the desired time duration from assertion of CONVT |
| AnnaBridge | 178:79309dc6340a | 184 | signal to Frame sync signal |
| AnnaBridge | 178:79309dc6340a | 185 | */ |
| AnnaBridge | 178:79309dc6340a | 186 | #define ADI_CFG_SPORT0A_CONVT_FS_DURATION (1u) |
| AnnaBridge | 178:79309dc6340a | 187 | |
| AnnaBridge | 178:79309dc6340a | 188 | /*! |
| AnnaBridge | 178:79309dc6340a | 189 | Polarity of the Convt signal.\n |
| AnnaBridge | 178:79309dc6340a | 190 | 0 - Active High Polarity\n |
| AnnaBridge | 178:79309dc6340a | 191 | 1 - Active low Polarity |
| AnnaBridge | 178:79309dc6340a | 192 | */ |
| AnnaBridge | 178:79309dc6340a | 193 | #define ADI_CFG_SPORT0A_CONVT_POLARITY (0u) |
| AnnaBridge | 178:79309dc6340a | 194 | |
| AnnaBridge | 178:79309dc6340a | 195 | /*! |
| AnnaBridge | 178:79309dc6340a | 196 | CONVT signal width.\n |
| AnnaBridge | 178:79309dc6340a | 197 | 0 - 15 - Specify the value of the number of serial clocks for which CONVT |
| AnnaBridge | 178:79309dc6340a | 198 | signal should be active |
| AnnaBridge | 178:79309dc6340a | 199 | |
| AnnaBridge | 178:79309dc6340a | 200 | */ |
| AnnaBridge | 178:79309dc6340a | 201 | #define ADI_CFG_SPORT0A_CONVT_WIDTH (1u) |
| AnnaBridge | 178:79309dc6340a | 202 | |
| AnnaBridge | 178:79309dc6340a | 203 | #if defined(ADI_CFG_SPORT0A_SERIAL_WLEN) |
| AnnaBridge | 178:79309dc6340a | 204 | #if (ADI_CFG_SPORT0A_SERIAL_WLEN <= 3u) || (ADI_CFG_SPORT0A_SERIAL_WLEN > 32u) |
| AnnaBridge | 178:79309dc6340a | 205 | #error "Invalid word length : it must be between 4 and 32" |
| AnnaBridge | 178:79309dc6340a | 206 | #endif |
| AnnaBridge | 178:79309dc6340a | 207 | #else |
| AnnaBridge | 178:79309dc6340a | 208 | #error "ADI_CFG_SPORT0A_SERIAL_WLEN undefined!!! " |
| AnnaBridge | 178:79309dc6340a | 209 | #endif |
| AnnaBridge | 178:79309dc6340a | 210 | |
| AnnaBridge | 178:79309dc6340a | 211 | /************* SPORT Driver configurations FOR SPORT-0-B ***************/ |
| AnnaBridge | 178:79309dc6340a | 212 | /*! |
| AnnaBridge | 178:79309dc6340a | 213 | Least-Significant Bit First.\n |
| AnnaBridge | 178:79309dc6340a | 214 | 0 - MSB first sent/received.\n |
| AnnaBridge | 178:79309dc6340a | 215 | 1 - LSB first sent/received. |
| AnnaBridge | 178:79309dc6340a | 216 | */ |
| AnnaBridge | 178:79309dc6340a | 217 | #define ADI_CFG_SPORT0B_LSB_FIRST (0u) |
| AnnaBridge | 178:79309dc6340a | 218 | |
| AnnaBridge | 178:79309dc6340a | 219 | |
| AnnaBridge | 178:79309dc6340a | 220 | /*! |
| AnnaBridge | 178:79309dc6340a | 221 | Serial Word Length in bits.\n |
| AnnaBridge | 178:79309dc6340a | 222 | 1 - 32 - SPORT word length |
| AnnaBridge | 178:79309dc6340a | 223 | */ |
| AnnaBridge | 178:79309dc6340a | 224 | #define ADI_CFG_SPORT0B_SERIAL_WLEN (32u) |
| AnnaBridge | 178:79309dc6340a | 225 | |
| AnnaBridge | 178:79309dc6340a | 226 | |
| AnnaBridge | 178:79309dc6340a | 227 | /*! |
| AnnaBridge | 178:79309dc6340a | 228 | Internal Clock.\n |
| AnnaBridge | 178:79309dc6340a | 229 | 0 - External clock.\n |
| AnnaBridge | 178:79309dc6340a | 230 | 1 - Internal clock. |
| AnnaBridge | 178:79309dc6340a | 231 | */ |
| AnnaBridge | 178:79309dc6340a | 232 | #define ADI_CFG_SPORT0B_INTERNAL_CLK (1u) |
| AnnaBridge | 178:79309dc6340a | 233 | |
| AnnaBridge | 178:79309dc6340a | 234 | /*! |
| AnnaBridge | 178:79309dc6340a | 235 | Operation Mode\n |
| AnnaBridge | 178:79309dc6340a | 236 | 0 - DSP standard.\n |
| AnnaBridge | 178:79309dc6340a | 237 | 1 - Timer_enable mode. |
| AnnaBridge | 178:79309dc6340a | 238 | */ |
| AnnaBridge | 178:79309dc6340a | 239 | #define ADI_CFG_SPORT0B_OPERATION_MODE (0u) |
| AnnaBridge | 178:79309dc6340a | 240 | |
| AnnaBridge | 178:79309dc6340a | 241 | |
| AnnaBridge | 178:79309dc6340a | 242 | /*! |
| AnnaBridge | 178:79309dc6340a | 243 | Clock Rising Edge\n |
| AnnaBridge | 178:79309dc6340a | 244 | 0 - Clock falling edge\n |
| AnnaBridge | 178:79309dc6340a | 245 | 1 - Clock rising edge. |
| AnnaBridge | 178:79309dc6340a | 246 | */ |
| AnnaBridge | 178:79309dc6340a | 247 | #define ADI_CFG_SPORT0B_CLOCK_EDGE (0u) |
| AnnaBridge | 178:79309dc6340a | 248 | |
| AnnaBridge | 178:79309dc6340a | 249 | /*! |
| AnnaBridge | 178:79309dc6340a | 250 | Frame Sync Required\n |
| AnnaBridge | 178:79309dc6340a | 251 | 0 - No frame sync required \n |
| AnnaBridge | 178:79309dc6340a | 252 | 1 - Frame sync required. |
| AnnaBridge | 178:79309dc6340a | 253 | */ |
| AnnaBridge | 178:79309dc6340a | 254 | #define ADI_CFG_SPORT0B_FS_REQUIRED (1u) |
| AnnaBridge | 178:79309dc6340a | 255 | |
| AnnaBridge | 178:79309dc6340a | 256 | /*! |
| AnnaBridge | 178:79309dc6340a | 257 | Internal Frame Sync\n |
| AnnaBridge | 178:79309dc6340a | 258 | 0 - External frame sync\n |
| AnnaBridge | 178:79309dc6340a | 259 | 1 - Internal frame sync |
| AnnaBridge | 178:79309dc6340a | 260 | */ |
| AnnaBridge | 178:79309dc6340a | 261 | #define ADI_CFG_SPORT0B_INTERNAL_FS (1u) |
| AnnaBridge | 178:79309dc6340a | 262 | |
| AnnaBridge | 178:79309dc6340a | 263 | |
| AnnaBridge | 178:79309dc6340a | 264 | /*! |
| AnnaBridge | 178:79309dc6340a | 265 | Data-Independent Frame Sync\n |
| AnnaBridge | 178:79309dc6340a | 266 | 0 - Data-dependent frame sync\n |
| AnnaBridge | 178:79309dc6340a | 267 | 1 - Data-independent frame |
| AnnaBridge | 178:79309dc6340a | 268 | */ |
| AnnaBridge | 178:79309dc6340a | 269 | #define ADI_CFG_SPORT0B_DATA_INDEPENDENT_FS (0u) |
| AnnaBridge | 178:79309dc6340a | 270 | |
| AnnaBridge | 178:79309dc6340a | 271 | /*! |
| AnnaBridge | 178:79309dc6340a | 272 | Active-Low Frame Sync\n |
| AnnaBridge | 178:79309dc6340a | 273 | 0 - Active high frame sync\n |
| AnnaBridge | 178:79309dc6340a | 274 | 1 - Active low frame sync |
| AnnaBridge | 178:79309dc6340a | 275 | */ |
| AnnaBridge | 178:79309dc6340a | 276 | #define ADI_CFG_SPORT0B_ACTIVE_LOW_FS (0u) |
| AnnaBridge | 178:79309dc6340a | 277 | |
| AnnaBridge | 178:79309dc6340a | 278 | /*! |
| AnnaBridge | 178:79309dc6340a | 279 | Late Frame Sync\n |
| AnnaBridge | 178:79309dc6340a | 280 | 0 - Early frame sync\n |
| AnnaBridge | 178:79309dc6340a | 281 | 1 - Late frame sync |
| AnnaBridge | 178:79309dc6340a | 282 | */ |
| AnnaBridge | 178:79309dc6340a | 283 | #define ADI_CFG_SPORT0B_LATE_FS (0u) |
| AnnaBridge | 178:79309dc6340a | 284 | |
| AnnaBridge | 178:79309dc6340a | 285 | /*! |
| AnnaBridge | 178:79309dc6340a | 286 | Enable Packing \n |
| AnnaBridge | 178:79309dc6340a | 287 | 0 - Disable\n |
| AnnaBridge | 178:79309dc6340a | 288 | 1 - 8-bit packing enable\n |
| AnnaBridge | 178:79309dc6340a | 289 | 2 - 16-bit packing enable\n |
| AnnaBridge | 178:79309dc6340a | 290 | */ |
| AnnaBridge | 178:79309dc6340a | 291 | #define ADI_CFG_SPORT0B_ENABLE_PACKING (0u) |
| AnnaBridge | 178:79309dc6340a | 292 | |
| AnnaBridge | 178:79309dc6340a | 293 | /*! |
| AnnaBridge | 178:79309dc6340a | 294 | Frame Sync Error Operation\n |
| AnnaBridge | 178:79309dc6340a | 295 | 0 - Flag the Frame Sync error\n |
| AnnaBridge | 178:79309dc6340a | 296 | 1 - When frame Sync error occurs, discard the receive data |
| AnnaBridge | 178:79309dc6340a | 297 | */ |
| AnnaBridge | 178:79309dc6340a | 298 | #define ADI_CFG_SPORT0B_FS_ERROR_OPERATION (1u) |
| AnnaBridge | 178:79309dc6340a | 299 | |
| AnnaBridge | 178:79309dc6340a | 300 | /*! |
| AnnaBridge | 178:79309dc6340a | 301 | Enabling Gated Clock\n |
| AnnaBridge | 178:79309dc6340a | 302 | 0 - Disable Gated Clock\n |
| AnnaBridge | 178:79309dc6340a | 303 | 1 - Enable Gated Clock |
| AnnaBridge | 178:79309dc6340a | 304 | */ |
| AnnaBridge | 178:79309dc6340a | 305 | #define ADI_CFG_SPORT0B_GATED_CLOCK (0u) |
| AnnaBridge | 178:79309dc6340a | 306 | |
| AnnaBridge | 178:79309dc6340a | 307 | /*! |
| AnnaBridge | 178:79309dc6340a | 308 | Serial Clock divisor.\n |
| AnnaBridge | 178:79309dc6340a | 309 | 0 - 65535 - Serial Clock Divisor which SPORT device use to calculate the serial |
| AnnaBridge | 178:79309dc6340a | 310 | clock (ACLK) from the processor system clock (PCLK). |
| AnnaBridge | 178:79309dc6340a | 311 | */ |
| AnnaBridge | 178:79309dc6340a | 312 | #define ADI_CFG_SPORT0B_CLOCK_DIVISOR (2u) |
| AnnaBridge | 178:79309dc6340a | 313 | |
| AnnaBridge | 178:79309dc6340a | 314 | /*! |
| AnnaBridge | 178:79309dc6340a | 315 | Frame Sync Divisor.\n |
| AnnaBridge | 178:79309dc6340a | 316 | 0 - 128 - Frame Sync Divisor which select the number of transmit or receive clock |
| AnnaBridge | 178:79309dc6340a | 317 | cycles that the half SPORT counts before generating a frame sync pulse. |
| AnnaBridge | 178:79309dc6340a | 318 | */ |
| AnnaBridge | 178:79309dc6340a | 319 | #define ADI_CFG_SPORT0B_FS_DIVISOR (0x40u) |
| AnnaBridge | 178:79309dc6340a | 320 | |
| AnnaBridge | 178:79309dc6340a | 321 | |
| AnnaBridge | 178:79309dc6340a | 322 | /*! |
| AnnaBridge | 178:79309dc6340a | 323 | CONVT to FS duration.\n |
| AnnaBridge | 178:79309dc6340a | 324 | 0 - 128 - Specify the value of the number of clocks which would be programmed |
| AnnaBridge | 178:79309dc6340a | 325 | corresponding to the desired time duration from assertion of CONVT |
| AnnaBridge | 178:79309dc6340a | 326 | signal to Frame sync signal |
| AnnaBridge | 178:79309dc6340a | 327 | */ |
| AnnaBridge | 178:79309dc6340a | 328 | #define ADI_CFG_SPORT0B_CONVT_FS_DURATION (1u) |
| AnnaBridge | 178:79309dc6340a | 329 | |
| AnnaBridge | 178:79309dc6340a | 330 | /*! |
| AnnaBridge | 178:79309dc6340a | 331 | Polarity of the Convt signal.\n |
| AnnaBridge | 178:79309dc6340a | 332 | 0 - Active High Polarity\n |
| AnnaBridge | 178:79309dc6340a | 333 | 1 - Active low Polarity |
| AnnaBridge | 178:79309dc6340a | 334 | */ |
| AnnaBridge | 178:79309dc6340a | 335 | #define ADI_CFG_SPORT0B_CONVT_POLARITY (0u) |
| AnnaBridge | 178:79309dc6340a | 336 | |
| AnnaBridge | 178:79309dc6340a | 337 | /*! |
| AnnaBridge | 178:79309dc6340a | 338 | CONVT signal width.\n |
| AnnaBridge | 178:79309dc6340a | 339 | 0-15 - Specify the value of the number of serial clocks for which CONVT |
| AnnaBridge | 178:79309dc6340a | 340 | signal should be active |
| AnnaBridge | 178:79309dc6340a | 341 | |
| AnnaBridge | 178:79309dc6340a | 342 | */ |
| AnnaBridge | 178:79309dc6340a | 343 | #define ADI_CFG_SPORT0B_CONVT_WIDTH (1u) |
| AnnaBridge | 178:79309dc6340a | 344 | |
| AnnaBridge | 178:79309dc6340a | 345 | #if defined(ADI_CFG_SPORT0B_SERIAL_WLEN) |
| AnnaBridge | 178:79309dc6340a | 346 | #if (ADI_CFG_SPORT0B_SERIAL_WLEN <= 3u) || (ADI_CFG_SPORT0B_SERIAL_WLEN > 32u) |
| AnnaBridge | 178:79309dc6340a | 347 | #error "Invalid word length : it must be between 4 and 32" |
| AnnaBridge | 178:79309dc6340a | 348 | #endif |
| AnnaBridge | 178:79309dc6340a | 349 | #else |
| AnnaBridge | 178:79309dc6340a | 350 | #error "ADI_CFG_SPORT0B_SERIAL_WLEN undefined!!! " |
| AnnaBridge | 178:79309dc6340a | 351 | #endif |
| AnnaBridge | 178:79309dc6340a | 352 | |
| AnnaBridge | 178:79309dc6340a | 353 | /*! @} */ |
| AnnaBridge | 178:79309dc6340a | 354 | |
| AnnaBridge | 178:79309dc6340a | 355 | #endif /* ADI_SPORT_CONFIG_H */ |
