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targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_rcc_ex.c@186:707f6e361f3e, 2018-06-22 (annotated)

Committer:
Anna Bridge
Date:
Fri Jun 22 16:45:37 2018 +0100
Revision:
186:707f6e361f3e
Parent:
157:ff67d9f36b67 
mbed-dev library. Release version 162

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f3xx_hal_rcc_ex.c
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @brief Extended RCC HAL module driver.
<> 144:ef7eb2e8f9f7 6 * This file provides firmware functions to manage the following
<> 144:ef7eb2e8f9f7 7 * functionalities RCC extension peripheral:
<> 144:ef7eb2e8f9f7 8 * + Extended Peripheral Control functions
<> 144:ef7eb2e8f9f7 9 *
<> 144:ef7eb2e8f9f7 10 ******************************************************************************
<> 144:ef7eb2e8f9f7 11 * @attention
<> 144:ef7eb2e8f9f7 12 *
<> 144:ef7eb2e8f9f7 13 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 14 *
<> 144:ef7eb2e8f9f7 15 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 16 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 17 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 18 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 19 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 20 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 21 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 22 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 23 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 24 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 25 *
<> 144:ef7eb2e8f9f7 26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 27 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 29 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 30 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 32 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 33 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 34 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 36 *
<> 144:ef7eb2e8f9f7 37 ******************************************************************************
<> 144:ef7eb2e8f9f7 38 */
<> 144:ef7eb2e8f9f7 39
<> 144:ef7eb2e8f9f7 40 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 41 #include "stm32f3xx_hal.h"
<> 144:ef7eb2e8f9f7 42
<> 144:ef7eb2e8f9f7 43 /** @addtogroup STM32F3xx_HAL_Driver
<> 144:ef7eb2e8f9f7 44 * @{
<> 144:ef7eb2e8f9f7 45 */
<> 144:ef7eb2e8f9f7 46
<> 144:ef7eb2e8f9f7 47 #ifdef HAL_RCC_MODULE_ENABLED
<> 144:ef7eb2e8f9f7 48
<> 144:ef7eb2e8f9f7 49 /** @defgroup RCCEx RCCEx
<> 144:ef7eb2e8f9f7 50 * @brief RCC Extension HAL module driver.
<> 144:ef7eb2e8f9f7 51 * @{
<> 144:ef7eb2e8f9f7 52 */
<> 144:ef7eb2e8f9f7 53
<> 144:ef7eb2e8f9f7 54 /* Private typedef -----------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 55 /* Private define ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 56 /* Private macro -------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 57 /** @defgroup RCCEx_Private_Macros RCCEx Private Macros
<> 144:ef7eb2e8f9f7 58 * @{
<> 144:ef7eb2e8f9f7 59 */
<> 144:ef7eb2e8f9f7 60 /**
<> 144:ef7eb2e8f9f7 61 * @}
<> 144:ef7eb2e8f9f7 62 */
<> 144:ef7eb2e8f9f7 63
<> 144:ef7eb2e8f9f7 64 /* Private variables ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 65 /* Private function prototypes -----------------------------------------------*/
<> 144:ef7eb2e8f9f7 66 /* Private functions ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 67 #if defined(RCC_CFGR2_ADC1PRES) || defined(RCC_CFGR2_ADCPRE12) || defined(RCC_CFGR2_ADCPRE34) || defined(RCC_CFGR_USBPRE) \
<> 144:ef7eb2e8f9f7 68 || defined(RCC_CFGR3_TIM1SW) || defined(RCC_CFGR3_TIM2SW) || defined(RCC_CFGR3_TIM8SW) || defined(RCC_CFGR3_TIM15SW) \
<> 144:ef7eb2e8f9f7 69 || defined(RCC_CFGR3_TIM16SW) || defined(RCC_CFGR3_TIM17SW) || defined(RCC_CFGR3_TIM20SW) || defined(RCC_CFGR3_TIM34SW) \
<> 144:ef7eb2e8f9f7 70 || defined(RCC_CFGR3_HRTIM1SW)
<> 144:ef7eb2e8f9f7 71 /** @defgroup RCCEx_Private_Functions RCCEx Private Functions
<> 144:ef7eb2e8f9f7 72 * @{
<> 144:ef7eb2e8f9f7 73 */
<> 144:ef7eb2e8f9f7 74 static uint32_t RCC_GetPLLCLKFreq(void);
<> 144:ef7eb2e8f9f7 75
<> 144:ef7eb2e8f9f7 76 /**
<> 144:ef7eb2e8f9f7 77 * @}
<> 144:ef7eb2e8f9f7 78 */
<> 144:ef7eb2e8f9f7 79 #endif /* RCC_CFGR2_ADC1PRES || RCC_CFGR2_ADCPRExx || RCC_CFGR3_TIMxSW || RCC_CFGR3_HRTIM1SW || RCC_CFGR_USBPRE */
<> 144:ef7eb2e8f9f7 80
<> 144:ef7eb2e8f9f7 81 /** @defgroup RCCEx_Exported_Functions RCCEx Exported Functions
<> 144:ef7eb2e8f9f7 82 * @{
<> 144:ef7eb2e8f9f7 83 */
<> 144:ef7eb2e8f9f7 84
<> 144:ef7eb2e8f9f7 85 /** @defgroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control functions
<> 144:ef7eb2e8f9f7 86 * @brief Extended Peripheral Control functions
<> 144:ef7eb2e8f9f7 87 *
<> 144:ef7eb2e8f9f7 88 @verbatim
<> 144:ef7eb2e8f9f7 89 ===============================================================================
<> 144:ef7eb2e8f9f7 90 ##### Extended Peripheral Control functions #####
<> 144:ef7eb2e8f9f7 91 ===============================================================================
<> 144:ef7eb2e8f9f7 92 [..]
<> 144:ef7eb2e8f9f7 93 This subsection provides a set of functions allowing to control the RCC Clocks
<> 144:ef7eb2e8f9f7 94 frequencies.
<> 144:ef7eb2e8f9f7 95 [..]
<> 144:ef7eb2e8f9f7 96 (@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to
<> 144:ef7eb2e8f9f7 97 select the RTC clock source; in this case the Backup domain will be reset in
<> 144:ef7eb2e8f9f7 98 order to modify the RTC Clock source, as consequence RTC registers (including
<> 144:ef7eb2e8f9f7 99 the backup registers) are set to their reset values.
<> 144:ef7eb2e8f9f7 100
<> 144:ef7eb2e8f9f7 101 @endverbatim
<> 144:ef7eb2e8f9f7 102 * @{
<> 144:ef7eb2e8f9f7 103 */
<> 144:ef7eb2e8f9f7 104
<> 144:ef7eb2e8f9f7 105 /**
<> 144:ef7eb2e8f9f7 106 * @brief Initializes the RCC extended peripherals clocks according to the specified
<> 144:ef7eb2e8f9f7 107 * parameters in the RCC_PeriphCLKInitTypeDef.
<> 144:ef7eb2e8f9f7 108 * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that
<> 144:ef7eb2e8f9f7 109 * contains the configuration information for the Extended Peripherals clocks
<> 144:ef7eb2e8f9f7 110 * (ADC, CEC, I2C, I2S, SDADC, HRTIM, TIM, USART, RTC and USB).
<> 144:ef7eb2e8f9f7 111 *
<> 144:ef7eb2e8f9f7 112 * @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select
<> 144:ef7eb2e8f9f7 113 * the RTC clock source; in this case the Backup domain will be reset in
<> 144:ef7eb2e8f9f7 114 * order to modify the RTC Clock source, as consequence RTC registers (including
<> 144:ef7eb2e8f9f7 115 * the backup registers) and RCC_BDCR register are set to their reset values.
<> 144:ef7eb2e8f9f7 116 *
<> 144:ef7eb2e8f9f7 117 * @retval HAL status
<> 144:ef7eb2e8f9f7 118 */
<> 144:ef7eb2e8f9f7 119 HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
<> 144:ef7eb2e8f9f7 120 {
<> 157:ff67d9f36b67 121 uint32_t tickstart = 0U;
<> 157:ff67d9f36b67 122 uint32_t temp_reg = 0U;
<> 144:ef7eb2e8f9f7 123
<> 144:ef7eb2e8f9f7 124 /* Check the parameters */
<> 144:ef7eb2e8f9f7 125 assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
<> 144:ef7eb2e8f9f7 126
<> 144:ef7eb2e8f9f7 127 /*---------------------------- RTC configuration -------------------------------*/
<> 144:ef7eb2e8f9f7 128 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))
<> 144:ef7eb2e8f9f7 129 {
<> 144:ef7eb2e8f9f7 130 /* check for RTC Parameters used to output RTCCLK */
<> 144:ef7eb2e8f9f7 131 assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
<> 144:ef7eb2e8f9f7 132
<> 144:ef7eb2e8f9f7 133 FlagStatus pwrclkchanged = RESET;
<> 144:ef7eb2e8f9f7 134
<> 144:ef7eb2e8f9f7 135 /* As soon as function is called to change RTC clock source, activation of the
<> 144:ef7eb2e8f9f7 136 power domain is done. */
<> 144:ef7eb2e8f9f7 137 /* Requires to enable write access to Backup Domain of necessary */
<> 144:ef7eb2e8f9f7 138 if(__HAL_RCC_PWR_IS_CLK_DISABLED())
<> 144:ef7eb2e8f9f7 139 {
<> 144:ef7eb2e8f9f7 140 __HAL_RCC_PWR_CLK_ENABLE();
<> 144:ef7eb2e8f9f7 141 pwrclkchanged = SET;
<> 144:ef7eb2e8f9f7 142 }
<> 144:ef7eb2e8f9f7 143
<> 144:ef7eb2e8f9f7 144 if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
<> 144:ef7eb2e8f9f7 145 {
<> 144:ef7eb2e8f9f7 146 /* Enable write access to Backup domain */
<> 144:ef7eb2e8f9f7 147 SET_BIT(PWR->CR, PWR_CR_DBP);
<> 144:ef7eb2e8f9f7 148
<> 144:ef7eb2e8f9f7 149 /* Wait for Backup domain Write protection disable */
<> 144:ef7eb2e8f9f7 150 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 151
<> 144:ef7eb2e8f9f7 152 while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
<> 144:ef7eb2e8f9f7 153 {
<> 144:ef7eb2e8f9f7 154 if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
<> 144:ef7eb2e8f9f7 155 {
<> 144:ef7eb2e8f9f7 156 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 157 }
<> 144:ef7eb2e8f9f7 158 }
<> 144:ef7eb2e8f9f7 159 }
<> 144:ef7eb2e8f9f7 160
<> 144:ef7eb2e8f9f7 161 /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */
<> 144:ef7eb2e8f9f7 162 temp_reg = (RCC->BDCR & RCC_BDCR_RTCSEL);
<> 144:ef7eb2e8f9f7 163 if((temp_reg != 0x00000000U) && (temp_reg != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)))
<> 144:ef7eb2e8f9f7 164 {
<> 144:ef7eb2e8f9f7 165 /* Store the content of BDCR register before the reset of Backup Domain */
<> 144:ef7eb2e8f9f7 166 temp_reg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
<> 144:ef7eb2e8f9f7 167 /* RTC Clock selection can be changed only if the Backup Domain is reset */
<> 144:ef7eb2e8f9f7 168 __HAL_RCC_BACKUPRESET_FORCE();
<> 144:ef7eb2e8f9f7 169 __HAL_RCC_BACKUPRESET_RELEASE();
<> 144:ef7eb2e8f9f7 170 /* Restore the Content of BDCR register */
<> 144:ef7eb2e8f9f7 171 RCC->BDCR = temp_reg;
<> 144:ef7eb2e8f9f7 172
<> 144:ef7eb2e8f9f7 173 /* Wait for LSERDY if LSE was enabled */
<> 144:ef7eb2e8f9f7 174 if (HAL_IS_BIT_SET(temp_reg, RCC_BDCR_LSEON))
<> 144:ef7eb2e8f9f7 175 {
<> 144:ef7eb2e8f9f7 176 /* Get Start Tick */
<> 144:ef7eb2e8f9f7 177 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 178
<> 144:ef7eb2e8f9f7 179 /* Wait till LSE is ready */
<> 144:ef7eb2e8f9f7 180 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
<> 144:ef7eb2e8f9f7 181 {
<> 144:ef7eb2e8f9f7 182 if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
<> 144:ef7eb2e8f9f7 183 {
<> 144:ef7eb2e8f9f7 184 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 185 }
<> 144:ef7eb2e8f9f7 186 }
<> 144:ef7eb2e8f9f7 187 }
<> 144:ef7eb2e8f9f7 188 }
<> 144:ef7eb2e8f9f7 189 __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
<> 144:ef7eb2e8f9f7 190
<> 144:ef7eb2e8f9f7 191 /* Require to disable power clock if necessary */
<> 144:ef7eb2e8f9f7 192 if(pwrclkchanged == SET)
<> 144:ef7eb2e8f9f7 193 {
<> 144:ef7eb2e8f9f7 194 __HAL_RCC_PWR_CLK_DISABLE();
<> 144:ef7eb2e8f9f7 195 }
<> 144:ef7eb2e8f9f7 196 }
<> 144:ef7eb2e8f9f7 197
<> 144:ef7eb2e8f9f7 198 /*------------------------------- USART1 Configuration ------------------------*/
<> 144:ef7eb2e8f9f7 199 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1)
<> 144:ef7eb2e8f9f7 200 {
<> 144:ef7eb2e8f9f7 201 /* Check the parameters */
<> 144:ef7eb2e8f9f7 202 assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection));
<> 144:ef7eb2e8f9f7 203
<> 144:ef7eb2e8f9f7 204 /* Configure the USART1 clock source */
<> 144:ef7eb2e8f9f7 205 __HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection);
<> 144:ef7eb2e8f9f7 206 }
<> 144:ef7eb2e8f9f7 207
<> 144:ef7eb2e8f9f7 208 #if defined(RCC_CFGR3_USART2SW)
<> 144:ef7eb2e8f9f7 209 /*----------------------------- USART2 Configuration --------------------------*/
<> 144:ef7eb2e8f9f7 210 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2)
<> 144:ef7eb2e8f9f7 211 {
<> 144:ef7eb2e8f9f7 212 /* Check the parameters */
<> 144:ef7eb2e8f9f7 213 assert_param(IS_RCC_USART2CLKSOURCE(PeriphClkInit->Usart2ClockSelection));
<> 144:ef7eb2e8f9f7 214
<> 144:ef7eb2e8f9f7 215 /* Configure the USART2 clock source */
<> 144:ef7eb2e8f9f7 216 __HAL_RCC_USART2_CONFIG(PeriphClkInit->Usart2ClockSelection);
<> 144:ef7eb2e8f9f7 217 }
<> 144:ef7eb2e8f9f7 218 #endif /* RCC_CFGR3_USART2SW */
<> 144:ef7eb2e8f9f7 219
<> 144:ef7eb2e8f9f7 220 #if defined(RCC_CFGR3_USART3SW)
<> 144:ef7eb2e8f9f7 221 /*------------------------------ USART3 Configuration ------------------------*/
<> 144:ef7eb2e8f9f7 222 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3)
<> 144:ef7eb2e8f9f7 223 {
<> 144:ef7eb2e8f9f7 224 /* Check the parameters */
<> 144:ef7eb2e8f9f7 225 assert_param(IS_RCC_USART3CLKSOURCE(PeriphClkInit->Usart3ClockSelection));
<> 144:ef7eb2e8f9f7 226
<> 144:ef7eb2e8f9f7 227 /* Configure the USART3 clock source */
<> 144:ef7eb2e8f9f7 228 __HAL_RCC_USART3_CONFIG(PeriphClkInit->Usart3ClockSelection);
<> 144:ef7eb2e8f9f7 229 }
<> 144:ef7eb2e8f9f7 230 #endif /* RCC_CFGR3_USART3SW */
<> 144:ef7eb2e8f9f7 231
<> 144:ef7eb2e8f9f7 232 /*------------------------------ I2C1 Configuration ------------------------*/
<> 144:ef7eb2e8f9f7 233 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1)
<> 144:ef7eb2e8f9f7 234 {
<> 144:ef7eb2e8f9f7 235 /* Check the parameters */
<> 144:ef7eb2e8f9f7 236 assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection));
<> 144:ef7eb2e8f9f7 237
<> 144:ef7eb2e8f9f7 238 /* Configure the I2C1 clock source */
<> 144:ef7eb2e8f9f7 239 __HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection);
<> 144:ef7eb2e8f9f7 240 }
<> 144:ef7eb2e8f9f7 241
<> 144:ef7eb2e8f9f7 242 #if defined(STM32F302xE) || defined(STM32F303xE)\
<> 144:ef7eb2e8f9f7 243 || defined(STM32F302xC) || defined(STM32F303xC)\
<> 144:ef7eb2e8f9f7 244 || defined(STM32F302x8) \
<> 144:ef7eb2e8f9f7 245 || defined(STM32F373xC)
<> 144:ef7eb2e8f9f7 246 /*------------------------------ USB Configuration ------------------------*/
<> 144:ef7eb2e8f9f7 247 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB)
<> 144:ef7eb2e8f9f7 248 {
<> 144:ef7eb2e8f9f7 249 /* Check the parameters */
<> 144:ef7eb2e8f9f7 250 assert_param(IS_RCC_USBCLKSOURCE(PeriphClkInit->USBClockSelection));
<> 144:ef7eb2e8f9f7 251
<> 144:ef7eb2e8f9f7 252 /* Configure the USB clock source */
<> 144:ef7eb2e8f9f7 253 __HAL_RCC_USB_CONFIG(PeriphClkInit->USBClockSelection);
<> 144:ef7eb2e8f9f7 254 }
<> 144:ef7eb2e8f9f7 255
<> 144:ef7eb2e8f9f7 256 #endif /* STM32F302xE || STM32F303xE || */
<> 144:ef7eb2e8f9f7 257 /* STM32F302xC || STM32F303xC || */
<> 144:ef7eb2e8f9f7 258 /* STM32F302x8 || */
<> 144:ef7eb2e8f9f7 259 /* STM32F373xC */
<> 144:ef7eb2e8f9f7 260
<> 144:ef7eb2e8f9f7 261 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\
<> 144:ef7eb2e8f9f7 262 || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)\
<> 144:ef7eb2e8f9f7 263 || defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)\
<> 144:ef7eb2e8f9f7 264 || defined(STM32F373xC) || defined(STM32F378xx)
<> 144:ef7eb2e8f9f7 265
<> 144:ef7eb2e8f9f7 266 /*------------------------------ I2C2 Configuration ------------------------*/
<> 144:ef7eb2e8f9f7 267 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2)
<> 144:ef7eb2e8f9f7 268 {
<> 144:ef7eb2e8f9f7 269 /* Check the parameters */
<> 144:ef7eb2e8f9f7 270 assert_param(IS_RCC_I2C2CLKSOURCE(PeriphClkInit->I2c2ClockSelection));
<> 144:ef7eb2e8f9f7 271
<> 144:ef7eb2e8f9f7 272 /* Configure the I2C2 clock source */
<> 144:ef7eb2e8f9f7 273 __HAL_RCC_I2C2_CONFIG(PeriphClkInit->I2c2ClockSelection);
<> 144:ef7eb2e8f9f7 274 }
<> 144:ef7eb2e8f9f7 275
<> 144:ef7eb2e8f9f7 276 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
<> 144:ef7eb2e8f9f7 277 /* STM32F302xC || STM32F303xC || STM32F358xx || */
<> 144:ef7eb2e8f9f7 278 /* STM32F301x8 || STM32F302x8 || STM32F318xx || */
<> 144:ef7eb2e8f9f7 279 /* STM32F373xC || STM32F378xx */
<> 144:ef7eb2e8f9f7 280
<> 144:ef7eb2e8f9f7 281 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\
<> 144:ef7eb2e8f9f7 282 || defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
<> 144:ef7eb2e8f9f7 283
<> 144:ef7eb2e8f9f7 284 /*------------------------------ I2C3 Configuration ------------------------*/
<> 144:ef7eb2e8f9f7 285 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3)
<> 144:ef7eb2e8f9f7 286 {
<> 144:ef7eb2e8f9f7 287 /* Check the parameters */
<> 144:ef7eb2e8f9f7 288 assert_param(IS_RCC_I2C3CLKSOURCE(PeriphClkInit->I2c3ClockSelection));
<> 144:ef7eb2e8f9f7 289
<> 144:ef7eb2e8f9f7 290 /* Configure the I2C3 clock source */
<> 144:ef7eb2e8f9f7 291 __HAL_RCC_I2C3_CONFIG(PeriphClkInit->I2c3ClockSelection);
<> 144:ef7eb2e8f9f7 292 }
<> 144:ef7eb2e8f9f7 293 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
<> 144:ef7eb2e8f9f7 294 /* STM32F301x8 || STM32F302x8 || STM32F318xx */
<> 144:ef7eb2e8f9f7 295
<> 144:ef7eb2e8f9f7 296 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\
<> 144:ef7eb2e8f9f7 297 || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)
<> 144:ef7eb2e8f9f7 298
<> 144:ef7eb2e8f9f7 299 /*------------------------------ UART4 Configuration ------------------------*/
<> 144:ef7eb2e8f9f7 300 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4)
<> 144:ef7eb2e8f9f7 301 {
<> 144:ef7eb2e8f9f7 302 /* Check the parameters */
<> 144:ef7eb2e8f9f7 303 assert_param(IS_RCC_UART4CLKSOURCE(PeriphClkInit->Uart4ClockSelection));
<> 144:ef7eb2e8f9f7 304
<> 144:ef7eb2e8f9f7 305 /* Configure the UART4 clock source */
<> 144:ef7eb2e8f9f7 306 __HAL_RCC_UART4_CONFIG(PeriphClkInit->Uart4ClockSelection);
<> 144:ef7eb2e8f9f7 307 }
<> 144:ef7eb2e8f9f7 308
<> 144:ef7eb2e8f9f7 309 /*------------------------------ UART5 Configuration ------------------------*/
<> 144:ef7eb2e8f9f7 310 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5)
<> 144:ef7eb2e8f9f7 311 {
<> 144:ef7eb2e8f9f7 312 /* Check the parameters */
<> 144:ef7eb2e8f9f7 313 assert_param(IS_RCC_UART5CLKSOURCE(PeriphClkInit->Uart5ClockSelection));
<> 144:ef7eb2e8f9f7 314
<> 144:ef7eb2e8f9f7 315 /* Configure the UART5 clock source */
<> 144:ef7eb2e8f9f7 316 __HAL_RCC_UART5_CONFIG(PeriphClkInit->Uart5ClockSelection);
<> 144:ef7eb2e8f9f7 317 }
<> 144:ef7eb2e8f9f7 318
<> 144:ef7eb2e8f9f7 319 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
<> 144:ef7eb2e8f9f7 320 /* STM32F302xC || STM32F303xC || STM32F358xx */
<> 144:ef7eb2e8f9f7 321
<> 144:ef7eb2e8f9f7 322 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\
<> 144:ef7eb2e8f9f7 323 || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)\
<> 144:ef7eb2e8f9f7 324 || defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
<> 144:ef7eb2e8f9f7 325 /*------------------------------ I2S Configuration ------------------------*/
<> 144:ef7eb2e8f9f7 326 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S)
<> 144:ef7eb2e8f9f7 327 {
<> 144:ef7eb2e8f9f7 328 /* Check the parameters */
<> 144:ef7eb2e8f9f7 329 assert_param(IS_RCC_I2SCLKSOURCE(PeriphClkInit->I2sClockSelection));
<> 144:ef7eb2e8f9f7 330
<> 144:ef7eb2e8f9f7 331 /* Configure the I2S clock source */
<> 144:ef7eb2e8f9f7 332 __HAL_RCC_I2S_CONFIG(PeriphClkInit->I2sClockSelection);
<> 144:ef7eb2e8f9f7 333 }
<> 144:ef7eb2e8f9f7 334
<> 144:ef7eb2e8f9f7 335 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
<> 144:ef7eb2e8f9f7 336 /* STM32F302xC || STM32F303xC || STM32F358xx || */
<> 144:ef7eb2e8f9f7 337 /* STM32F301x8 || STM32F302x8 || STM32F318xx */
<> 144:ef7eb2e8f9f7 338
<> 144:ef7eb2e8f9f7 339 #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
<> 144:ef7eb2e8f9f7 340
<> 144:ef7eb2e8f9f7 341 /*------------------------------ ADC1 clock Configuration ------------------*/
<> 144:ef7eb2e8f9f7 342 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC1) == RCC_PERIPHCLK_ADC1)
<> 144:ef7eb2e8f9f7 343 {
<> 144:ef7eb2e8f9f7 344 /* Check the parameters */
<> 144:ef7eb2e8f9f7 345 assert_param(IS_RCC_ADC1PLLCLK_DIV(PeriphClkInit->Adc1ClockSelection));
<> 144:ef7eb2e8f9f7 346
<> 144:ef7eb2e8f9f7 347 /* Configure the ADC1 clock source */
<> 144:ef7eb2e8f9f7 348 __HAL_RCC_ADC1_CONFIG(PeriphClkInit->Adc1ClockSelection);
<> 144:ef7eb2e8f9f7 349 }
<> 144:ef7eb2e8f9f7 350
<> 144:ef7eb2e8f9f7 351 #endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */
<> 144:ef7eb2e8f9f7 352
<> 144:ef7eb2e8f9f7 353 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\
<> 144:ef7eb2e8f9f7 354 || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)\
<> 144:ef7eb2e8f9f7 355 || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
<> 144:ef7eb2e8f9f7 356
<> 144:ef7eb2e8f9f7 357 /*------------------------------ ADC1 & ADC2 clock Configuration -------------*/
<> 144:ef7eb2e8f9f7 358 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC12) == RCC_PERIPHCLK_ADC12)
<> 144:ef7eb2e8f9f7 359 {
<> 144:ef7eb2e8f9f7 360 /* Check the parameters */
<> 144:ef7eb2e8f9f7 361 assert_param(IS_RCC_ADC12PLLCLK_DIV(PeriphClkInit->Adc12ClockSelection));
<> 144:ef7eb2e8f9f7 362
<> 144:ef7eb2e8f9f7 363 /* Configure the ADC12 clock source */
<> 144:ef7eb2e8f9f7 364 __HAL_RCC_ADC12_CONFIG(PeriphClkInit->Adc12ClockSelection);
<> 144:ef7eb2e8f9f7 365 }
<> 144:ef7eb2e8f9f7 366
<> 144:ef7eb2e8f9f7 367 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
<> 144:ef7eb2e8f9f7 368 /* STM32F302xC || STM32F303xC || STM32F358xx || */
<> 144:ef7eb2e8f9f7 369 /* STM32F303x8 || STM32F334x8 || STM32F328xx */
<> 144:ef7eb2e8f9f7 370
<> 144:ef7eb2e8f9f7 371 #if defined(STM32F303xE) || defined(STM32F398xx)\
<> 144:ef7eb2e8f9f7 372 || defined(STM32F303xC) || defined(STM32F358xx)
<> 144:ef7eb2e8f9f7 373
<> 144:ef7eb2e8f9f7 374 /*------------------------------ ADC3 & ADC4 clock Configuration -------------*/
<> 144:ef7eb2e8f9f7 375 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC34) == RCC_PERIPHCLK_ADC34)
<> 144:ef7eb2e8f9f7 376 {
<> 144:ef7eb2e8f9f7 377 /* Check the parameters */
<> 144:ef7eb2e8f9f7 378 assert_param(IS_RCC_ADC34PLLCLK_DIV(PeriphClkInit->Adc34ClockSelection));
<> 144:ef7eb2e8f9f7 379
<> 144:ef7eb2e8f9f7 380 /* Configure the ADC34 clock source */
<> 144:ef7eb2e8f9f7 381 __HAL_RCC_ADC34_CONFIG(PeriphClkInit->Adc34ClockSelection);
<> 144:ef7eb2e8f9f7 382 }
<> 144:ef7eb2e8f9f7 383
<> 144:ef7eb2e8f9f7 384 #endif /* STM32F303xE || STM32F398xx || */
<> 144:ef7eb2e8f9f7 385 /* STM32F303xC || STM32F358xx */
<> 144:ef7eb2e8f9f7 386
<> 144:ef7eb2e8f9f7 387 #if defined(STM32F373xC) || defined(STM32F378xx)
<> 144:ef7eb2e8f9f7 388
<> 144:ef7eb2e8f9f7 389 /*------------------------------ ADC1 clock Configuration ------------------*/
<> 144:ef7eb2e8f9f7 390 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC1) == RCC_PERIPHCLK_ADC1)
<> 144:ef7eb2e8f9f7 391 {
<> 144:ef7eb2e8f9f7 392 /* Check the parameters */
<> 144:ef7eb2e8f9f7 393 assert_param(IS_RCC_ADC1PCLK2_DIV(PeriphClkInit->Adc1ClockSelection));
<> 144:ef7eb2e8f9f7 394
<> 144:ef7eb2e8f9f7 395 /* Configure the ADC1 clock source */
<> 144:ef7eb2e8f9f7 396 __HAL_RCC_ADC1_CONFIG(PeriphClkInit->Adc1ClockSelection);
<> 144:ef7eb2e8f9f7 397 }
<> 144:ef7eb2e8f9f7 398
<> 144:ef7eb2e8f9f7 399 #endif /* STM32F373xC || STM32F378xx */
<> 144:ef7eb2e8f9f7 400
<> 144:ef7eb2e8f9f7 401 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\
<> 144:ef7eb2e8f9f7 402 || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)\
<> 144:ef7eb2e8f9f7 403 || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)\
<> 144:ef7eb2e8f9f7 404 || defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
<> 144:ef7eb2e8f9f7 405
<> 144:ef7eb2e8f9f7 406 /*------------------------------ TIM1 clock Configuration ----------------*/
<> 144:ef7eb2e8f9f7 407 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM1) == RCC_PERIPHCLK_TIM1)
<> 144:ef7eb2e8f9f7 408 {
<> 144:ef7eb2e8f9f7 409 /* Check the parameters */
<> 144:ef7eb2e8f9f7 410 assert_param(IS_RCC_TIM1CLKSOURCE(PeriphClkInit->Tim1ClockSelection));
<> 144:ef7eb2e8f9f7 411
<> 144:ef7eb2e8f9f7 412 /* Configure the TIM1 clock source */
<> 144:ef7eb2e8f9f7 413 __HAL_RCC_TIM1_CONFIG(PeriphClkInit->Tim1ClockSelection);
<> 144:ef7eb2e8f9f7 414 }
<> 144:ef7eb2e8f9f7 415
<> 144:ef7eb2e8f9f7 416 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
<> 144:ef7eb2e8f9f7 417 /* STM32F302xC || STM32F303xC || STM32F358xx || */
<> 144:ef7eb2e8f9f7 418 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
<> 144:ef7eb2e8f9f7 419 /* STM32F301x8 || STM32F302x8 || STM32F318xx */
<> 144:ef7eb2e8f9f7 420
<> 144:ef7eb2e8f9f7 421 #if defined(STM32F303xE) || defined(STM32F398xx)\
<> 144:ef7eb2e8f9f7 422 || defined(STM32F303xC) || defined(STM32F358xx)
<> 144:ef7eb2e8f9f7 423
<> 144:ef7eb2e8f9f7 424 /*------------------------------ TIM8 clock Configuration ----------------*/
<> 144:ef7eb2e8f9f7 425 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM8) == RCC_PERIPHCLK_TIM8)
<> 144:ef7eb2e8f9f7 426 {
<> 144:ef7eb2e8f9f7 427 /* Check the parameters */
<> 144:ef7eb2e8f9f7 428 assert_param(IS_RCC_TIM8CLKSOURCE(PeriphClkInit->Tim8ClockSelection));
<> 144:ef7eb2e8f9f7 429
<> 144:ef7eb2e8f9f7 430 /* Configure the TIM8 clock source */
<> 144:ef7eb2e8f9f7 431 __HAL_RCC_TIM8_CONFIG(PeriphClkInit->Tim8ClockSelection);
<> 144:ef7eb2e8f9f7 432 }
<> 144:ef7eb2e8f9f7 433
<> 144:ef7eb2e8f9f7 434 #endif /* STM32F303xE || STM32F398xx || */
<> 144:ef7eb2e8f9f7 435 /* STM32F303xC || STM32F358xx */
<> 144:ef7eb2e8f9f7 436
<> 144:ef7eb2e8f9f7 437 #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
<> 144:ef7eb2e8f9f7 438
<> 144:ef7eb2e8f9f7 439 /*------------------------------ TIM15 clock Configuration ----------------*/
<> 144:ef7eb2e8f9f7 440 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM15) == RCC_PERIPHCLK_TIM15)
<> 144:ef7eb2e8f9f7 441 {
<> 144:ef7eb2e8f9f7 442 /* Check the parameters */
<> 144:ef7eb2e8f9f7 443 assert_param(IS_RCC_TIM15CLKSOURCE(PeriphClkInit->Tim15ClockSelection));
<> 144:ef7eb2e8f9f7 444
<> 144:ef7eb2e8f9f7 445 /* Configure the TIM15 clock source */
<> 144:ef7eb2e8f9f7 446 __HAL_RCC_TIM15_CONFIG(PeriphClkInit->Tim15ClockSelection);
<> 144:ef7eb2e8f9f7 447 }
<> 144:ef7eb2e8f9f7 448
<> 144:ef7eb2e8f9f7 449 /*------------------------------ TIM16 clock Configuration ----------------*/
<> 144:ef7eb2e8f9f7 450 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM16) == RCC_PERIPHCLK_TIM16)
<> 144:ef7eb2e8f9f7 451 {
<> 144:ef7eb2e8f9f7 452 /* Check the parameters */
<> 144:ef7eb2e8f9f7 453 assert_param(IS_RCC_TIM16CLKSOURCE(PeriphClkInit->Tim16ClockSelection));
<> 144:ef7eb2e8f9f7 454
<> 144:ef7eb2e8f9f7 455 /* Configure the TIM16 clock source */
<> 144:ef7eb2e8f9f7 456 __HAL_RCC_TIM16_CONFIG(PeriphClkInit->Tim16ClockSelection);
<> 144:ef7eb2e8f9f7 457 }
<> 144:ef7eb2e8f9f7 458
<> 144:ef7eb2e8f9f7 459 /*------------------------------ TIM17 clock Configuration ----------------*/
<> 144:ef7eb2e8f9f7 460 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM17) == RCC_PERIPHCLK_TIM17)
<> 144:ef7eb2e8f9f7 461 {
<> 144:ef7eb2e8f9f7 462 /* Check the parameters */
<> 144:ef7eb2e8f9f7 463 assert_param(IS_RCC_TIM17CLKSOURCE(PeriphClkInit->Tim17ClockSelection));
<> 144:ef7eb2e8f9f7 464
<> 144:ef7eb2e8f9f7 465 /* Configure the TIM17 clock source */
<> 144:ef7eb2e8f9f7 466 __HAL_RCC_TIM17_CONFIG(PeriphClkInit->Tim17ClockSelection);
<> 144:ef7eb2e8f9f7 467 }
<> 144:ef7eb2e8f9f7 468
<> 144:ef7eb2e8f9f7 469 #endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */
<> 144:ef7eb2e8f9f7 470
<> 144:ef7eb2e8f9f7 471 #if defined(STM32F334x8)
<> 144:ef7eb2e8f9f7 472
<> 144:ef7eb2e8f9f7 473 /*------------------------------ HRTIM1 clock Configuration ----------------*/
<> 144:ef7eb2e8f9f7 474 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_HRTIM1) == RCC_PERIPHCLK_HRTIM1)
<> 144:ef7eb2e8f9f7 475 {
<> 144:ef7eb2e8f9f7 476 /* Check the parameters */
<> 144:ef7eb2e8f9f7 477 assert_param(IS_RCC_HRTIM1CLKSOURCE(PeriphClkInit->Hrtim1ClockSelection));
<> 144:ef7eb2e8f9f7 478
<> 144:ef7eb2e8f9f7 479 /* Configure the HRTIM1 clock source */
<> 144:ef7eb2e8f9f7 480 __HAL_RCC_HRTIM1_CONFIG(PeriphClkInit->Hrtim1ClockSelection);
<> 144:ef7eb2e8f9f7 481 }
<> 144:ef7eb2e8f9f7 482
<> 144:ef7eb2e8f9f7 483 #endif /* STM32F334x8 */
<> 144:ef7eb2e8f9f7 484
<> 144:ef7eb2e8f9f7 485 #if defined(STM32F373xC) || defined(STM32F378xx)
<> 144:ef7eb2e8f9f7 486
<> 144:ef7eb2e8f9f7 487 /*------------------------------ SDADC clock Configuration -------------------*/
<> 144:ef7eb2e8f9f7 488 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDADC) == RCC_PERIPHCLK_SDADC)
<> 144:ef7eb2e8f9f7 489 {
<> 144:ef7eb2e8f9f7 490 /* Check the parameters */
<> 144:ef7eb2e8f9f7 491 assert_param(IS_RCC_SDADCSYSCLK_DIV(PeriphClkInit->SdadcClockSelection));
<> 144:ef7eb2e8f9f7 492
<> 144:ef7eb2e8f9f7 493 /* Configure the SDADC clock prescaler */
<> 144:ef7eb2e8f9f7 494 __HAL_RCC_SDADC_CONFIG(PeriphClkInit->SdadcClockSelection);
<> 144:ef7eb2e8f9f7 495 }
<> 144:ef7eb2e8f9f7 496
<> 144:ef7eb2e8f9f7 497 /*------------------------------ CEC clock Configuration -------------------*/
<> 144:ef7eb2e8f9f7 498 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC)
<> 144:ef7eb2e8f9f7 499 {
<> 144:ef7eb2e8f9f7 500 /* Check the parameters */
<> 144:ef7eb2e8f9f7 501 assert_param(IS_RCC_CECCLKSOURCE(PeriphClkInit->CecClockSelection));
<> 144:ef7eb2e8f9f7 502
<> 144:ef7eb2e8f9f7 503 /* Configure the CEC clock source */
<> 144:ef7eb2e8f9f7 504 __HAL_RCC_CEC_CONFIG(PeriphClkInit->CecClockSelection);
<> 144:ef7eb2e8f9f7 505 }
<> 144:ef7eb2e8f9f7 506
<> 144:ef7eb2e8f9f7 507 #endif /* STM32F373xC || STM32F378xx */
<> 144:ef7eb2e8f9f7 508
<> 144:ef7eb2e8f9f7 509 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
<> 144:ef7eb2e8f9f7 510
<> 144:ef7eb2e8f9f7 511 /*------------------------------ TIM2 clock Configuration -------------------*/
<> 144:ef7eb2e8f9f7 512 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM2) == RCC_PERIPHCLK_TIM2)
<> 144:ef7eb2e8f9f7 513 {
<> 144:ef7eb2e8f9f7 514 /* Check the parameters */
<> 144:ef7eb2e8f9f7 515 assert_param(IS_RCC_TIM2CLKSOURCE(PeriphClkInit->Tim2ClockSelection));
<> 144:ef7eb2e8f9f7 516
<> 144:ef7eb2e8f9f7 517 /* Configure the CEC clock source */
<> 144:ef7eb2e8f9f7 518 __HAL_RCC_TIM2_CONFIG(PeriphClkInit->Tim2ClockSelection);
<> 144:ef7eb2e8f9f7 519 }
<> 144:ef7eb2e8f9f7 520
<> 144:ef7eb2e8f9f7 521 /*------------------------------ TIM3 clock Configuration -------------------*/
<> 144:ef7eb2e8f9f7 522 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM34) == RCC_PERIPHCLK_TIM34)
<> 144:ef7eb2e8f9f7 523 {
<> 144:ef7eb2e8f9f7 524 /* Check the parameters */
<> 144:ef7eb2e8f9f7 525 assert_param(IS_RCC_TIM3CLKSOURCE(PeriphClkInit->Tim34ClockSelection));
<> 144:ef7eb2e8f9f7 526
<> 144:ef7eb2e8f9f7 527 /* Configure the CEC clock source */
<> 144:ef7eb2e8f9f7 528 __HAL_RCC_TIM34_CONFIG(PeriphClkInit->Tim34ClockSelection);
<> 144:ef7eb2e8f9f7 529 }
<> 144:ef7eb2e8f9f7 530
<> 144:ef7eb2e8f9f7 531 /*------------------------------ TIM15 clock Configuration ------------------*/
<> 144:ef7eb2e8f9f7 532 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM15) == RCC_PERIPHCLK_TIM15)
<> 144:ef7eb2e8f9f7 533 {
<> 144:ef7eb2e8f9f7 534 /* Check the parameters */
<> 144:ef7eb2e8f9f7 535 assert_param(IS_RCC_TIM15CLKSOURCE(PeriphClkInit->Tim15ClockSelection));
<> 144:ef7eb2e8f9f7 536
<> 144:ef7eb2e8f9f7 537 /* Configure the CEC clock source */
<> 144:ef7eb2e8f9f7 538 __HAL_RCC_TIM15_CONFIG(PeriphClkInit->Tim15ClockSelection);
<> 144:ef7eb2e8f9f7 539 }
<> 144:ef7eb2e8f9f7 540
<> 144:ef7eb2e8f9f7 541 /*------------------------------ TIM16 clock Configuration ------------------*/
<> 144:ef7eb2e8f9f7 542 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM16) == RCC_PERIPHCLK_TIM16)
<> 144:ef7eb2e8f9f7 543 {
<> 144:ef7eb2e8f9f7 544 /* Check the parameters */
<> 144:ef7eb2e8f9f7 545 assert_param(IS_RCC_TIM16CLKSOURCE(PeriphClkInit->Tim16ClockSelection));
<> 144:ef7eb2e8f9f7 546
<> 144:ef7eb2e8f9f7 547 /* Configure the CEC clock source */
<> 144:ef7eb2e8f9f7 548 __HAL_RCC_TIM16_CONFIG(PeriphClkInit->Tim16ClockSelection);
<> 144:ef7eb2e8f9f7 549 }
<> 144:ef7eb2e8f9f7 550
<> 144:ef7eb2e8f9f7 551 /*------------------------------ TIM17 clock Configuration ------------------*/
<> 144:ef7eb2e8f9f7 552 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM17) == RCC_PERIPHCLK_TIM17)
<> 144:ef7eb2e8f9f7 553 {
<> 144:ef7eb2e8f9f7 554 /* Check the parameters */
<> 144:ef7eb2e8f9f7 555 assert_param(IS_RCC_TIM17CLKSOURCE(PeriphClkInit->Tim17ClockSelection));
<> 144:ef7eb2e8f9f7 556
<> 144:ef7eb2e8f9f7 557 /* Configure the CEC clock source */
<> 144:ef7eb2e8f9f7 558 __HAL_RCC_TIM17_CONFIG(PeriphClkInit->Tim17ClockSelection);
<> 144:ef7eb2e8f9f7 559 }
<> 144:ef7eb2e8f9f7 560
<> 144:ef7eb2e8f9f7 561 #endif /* STM32F302xE || STM32F303xE || STM32F398xx */
<> 144:ef7eb2e8f9f7 562
<> 144:ef7eb2e8f9f7 563 #if defined(STM32F303xE) || defined(STM32F398xx)
<> 144:ef7eb2e8f9f7 564 /*------------------------------ TIM20 clock Configuration ------------------*/
<> 144:ef7eb2e8f9f7 565 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM20) == RCC_PERIPHCLK_TIM20)
<> 144:ef7eb2e8f9f7 566 {
<> 144:ef7eb2e8f9f7 567 /* Check the parameters */
<> 144:ef7eb2e8f9f7 568 assert_param(IS_RCC_TIM20CLKSOURCE(PeriphClkInit->Tim20ClockSelection));
<> 144:ef7eb2e8f9f7 569
<> 144:ef7eb2e8f9f7 570 /* Configure the CEC clock source */
<> 144:ef7eb2e8f9f7 571 __HAL_RCC_TIM20_CONFIG(PeriphClkInit->Tim20ClockSelection);
<> 144:ef7eb2e8f9f7 572 }
<> 144:ef7eb2e8f9f7 573 #endif /* STM32F303xE || STM32F398xx */
<> 144:ef7eb2e8f9f7 574
<> 144:ef7eb2e8f9f7 575
<> 144:ef7eb2e8f9f7 576 return HAL_OK;
<> 144:ef7eb2e8f9f7 577 }
<> 144:ef7eb2e8f9f7 578
<> 144:ef7eb2e8f9f7 579 /**
<> 144:ef7eb2e8f9f7 580 * @brief Get the RCC_ClkInitStruct according to the internal
<> 144:ef7eb2e8f9f7 581 * RCC configuration registers.
<> 144:ef7eb2e8f9f7 582 * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that
<> 144:ef7eb2e8f9f7 583 * returns the configuration information for the Extended Peripherals clocks
<> 144:ef7eb2e8f9f7 584 * (ADC, CEC, I2C, I2S, SDADC, HRTIM, TIM, USART, RTC and USB clocks).
<> 144:ef7eb2e8f9f7 585 * @retval None
<> 144:ef7eb2e8f9f7 586 */
<> 144:ef7eb2e8f9f7 587 void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
<> 144:ef7eb2e8f9f7 588 {
<> 144:ef7eb2e8f9f7 589 /* Set all possible values for the extended clock type parameter------------*/
<> 144:ef7eb2e8f9f7 590 /* Common part first */
<> 144:ef7eb2e8f9f7 591 #if defined(RCC_CFGR3_USART2SW) && defined(RCC_CFGR3_USART3SW)
<> 144:ef7eb2e8f9f7 592 PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \
<> 144:ef7eb2e8f9f7 593 RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_RTC;
<> 144:ef7eb2e8f9f7 594 #else
<> 144:ef7eb2e8f9f7 595 PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | \
<> 144:ef7eb2e8f9f7 596 RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_RTC;
<> 144:ef7eb2e8f9f7 597 #endif /* RCC_CFGR3_USART2SW && RCC_CFGR3_USART3SW */
<> 144:ef7eb2e8f9f7 598
<> 144:ef7eb2e8f9f7 599 /* Get the RTC configuration --------------------------------------------*/
<> 144:ef7eb2e8f9f7 600 PeriphClkInit->RTCClockSelection = __HAL_RCC_GET_RTC_SOURCE();
<> 144:ef7eb2e8f9f7 601 /* Get the USART1 clock configuration --------------------------------------------*/
<> 144:ef7eb2e8f9f7 602 PeriphClkInit->Usart1ClockSelection = __HAL_RCC_GET_USART1_SOURCE();
<> 144:ef7eb2e8f9f7 603 #if defined(RCC_CFGR3_USART2SW)
<> 144:ef7eb2e8f9f7 604 /* Get the USART2 clock configuration -----------------------------------------*/
<> 144:ef7eb2e8f9f7 605 PeriphClkInit->Usart2ClockSelection = __HAL_RCC_GET_USART2_SOURCE();
<> 144:ef7eb2e8f9f7 606 #endif /* RCC_CFGR3_USART2SW */
<> 144:ef7eb2e8f9f7 607 #if defined(RCC_CFGR3_USART3SW)
<> 144:ef7eb2e8f9f7 608 /* Get the USART3 clock configuration -----------------------------------------*/
<> 144:ef7eb2e8f9f7 609 PeriphClkInit->Usart3ClockSelection = __HAL_RCC_GET_USART3_SOURCE();
<> 144:ef7eb2e8f9f7 610 #endif /* RCC_CFGR3_USART3SW */
<> 144:ef7eb2e8f9f7 611 /* Get the I2C1 clock configuration -----------------------------------------*/
<> 144:ef7eb2e8f9f7 612 PeriphClkInit->I2c1ClockSelection = __HAL_RCC_GET_I2C1_SOURCE();
<> 144:ef7eb2e8f9f7 613
<> 144:ef7eb2e8f9f7 614 #if defined(STM32F302xE) || defined(STM32F303xE)\
<> 144:ef7eb2e8f9f7 615 || defined(STM32F302xC) || defined(STM32F303xC)\
<> 144:ef7eb2e8f9f7 616 || defined(STM32F302x8) \
<> 144:ef7eb2e8f9f7 617 || defined(STM32F373xC)
<> 144:ef7eb2e8f9f7 618
<> 144:ef7eb2e8f9f7 619 PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_USB;
<> 144:ef7eb2e8f9f7 620 /* Get the USB clock configuration -----------------------------------------*/
<> 144:ef7eb2e8f9f7 621 PeriphClkInit->USBClockSelection = __HAL_RCC_GET_USB_SOURCE();
<> 144:ef7eb2e8f9f7 622
<> 144:ef7eb2e8f9f7 623 #endif /* STM32F302xE || STM32F303xE || */
<> 144:ef7eb2e8f9f7 624 /* STM32F302xC || STM32F303xC || */
<> 144:ef7eb2e8f9f7 625 /* STM32F302x8 || */
<> 144:ef7eb2e8f9f7 626 /* STM32F373xC */
<> 144:ef7eb2e8f9f7 627
<> 144:ef7eb2e8f9f7 628 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\
<> 144:ef7eb2e8f9f7 629 || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)\
<> 144:ef7eb2e8f9f7 630 || defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)\
<> 144:ef7eb2e8f9f7 631 || defined(STM32F373xC) || defined(STM32F378xx)
<> 144:ef7eb2e8f9f7 632
<> 144:ef7eb2e8f9f7 633 PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2C2;
<> 144:ef7eb2e8f9f7 634 /* Get the I2C2 clock configuration -----------------------------------------*/
<> 144:ef7eb2e8f9f7 635 PeriphClkInit->I2c2ClockSelection = __HAL_RCC_GET_I2C2_SOURCE();
<> 144:ef7eb2e8f9f7 636
<> 144:ef7eb2e8f9f7 637 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
<> 144:ef7eb2e8f9f7 638 /* STM32F302xC || STM32F303xC || STM32F358xx || */
<> 144:ef7eb2e8f9f7 639 /* STM32F301x8 || STM32F302x8 || STM32F318xx || */
<> 144:ef7eb2e8f9f7 640 /* STM32F373xC || STM32F378xx */
<> 144:ef7eb2e8f9f7 641
<> 144:ef7eb2e8f9f7 642 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\
<> 144:ef7eb2e8f9f7 643 || defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
<> 144:ef7eb2e8f9f7 644
<> 144:ef7eb2e8f9f7 645 PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2C3;
<> 144:ef7eb2e8f9f7 646 /* Get the I2C3 clock configuration -----------------------------------------*/
<> 144:ef7eb2e8f9f7 647 PeriphClkInit->I2c3ClockSelection = __HAL_RCC_GET_I2C3_SOURCE();
<> 144:ef7eb2e8f9f7 648
<> 144:ef7eb2e8f9f7 649 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
<> 144:ef7eb2e8f9f7 650 /* STM32F301x8 || STM32F302x8 || STM32F318xx */
<> 144:ef7eb2e8f9f7 651
<> 144:ef7eb2e8f9f7 652 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\
<> 144:ef7eb2e8f9f7 653 || defined(STM32F302xC) || defined(STM32F303xC) ||defined(STM32F358xx)
<> 144:ef7eb2e8f9f7 654
<> 144:ef7eb2e8f9f7 655 PeriphClkInit->PeriphClockSelection |= (RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5);
<> 144:ef7eb2e8f9f7 656 /* Get the UART4 clock configuration -----------------------------------------*/
<> 144:ef7eb2e8f9f7 657 PeriphClkInit->Uart4ClockSelection = __HAL_RCC_GET_UART4_SOURCE();
<> 144:ef7eb2e8f9f7 658 /* Get the UART5 clock configuration -----------------------------------------*/
<> 144:ef7eb2e8f9f7 659 PeriphClkInit->Uart5ClockSelection = __HAL_RCC_GET_UART5_SOURCE();
<> 144:ef7eb2e8f9f7 660
<> 144:ef7eb2e8f9f7 661 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
<> 144:ef7eb2e8f9f7 662 /* STM32F302xC || STM32F303xC || STM32F358xx */
<> 144:ef7eb2e8f9f7 663
<> 144:ef7eb2e8f9f7 664 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\
<> 144:ef7eb2e8f9f7 665 || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)\
<> 144:ef7eb2e8f9f7 666 || defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
<> 144:ef7eb2e8f9f7 667
<> 144:ef7eb2e8f9f7 668 PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2S;
<> 144:ef7eb2e8f9f7 669 /* Get the I2S clock configuration -----------------------------------------*/
<> 144:ef7eb2e8f9f7 670 PeriphClkInit->I2sClockSelection = __HAL_RCC_GET_I2S_SOURCE();
<> 144:ef7eb2e8f9f7 671
<> 144:ef7eb2e8f9f7 672 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
<> 144:ef7eb2e8f9f7 673 /* STM32F302xC || STM32F303xC || STM32F358xx || */
<> 144:ef7eb2e8f9f7 674 /* STM32F301x8 || STM32F302x8 || STM32F318xx || */
<> 144:ef7eb2e8f9f7 675
<> 144:ef7eb2e8f9f7 676 #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)\
<> 144:ef7eb2e8f9f7 677 || defined(STM32F373xC) || defined(STM32F378xx)
<> 144:ef7eb2e8f9f7 678
<> 144:ef7eb2e8f9f7 679 PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_ADC1;
<> 144:ef7eb2e8f9f7 680 /* Get the ADC1 clock configuration -----------------------------------------*/
<> 144:ef7eb2e8f9f7 681 PeriphClkInit->Adc1ClockSelection = __HAL_RCC_GET_ADC1_SOURCE();
<> 144:ef7eb2e8f9f7 682
<> 144:ef7eb2e8f9f7 683 #endif /* STM32F301x8 || STM32F302x8 || STM32F318xx || */
<> 144:ef7eb2e8f9f7 684 /* STM32F373xC || STM32F378xx */
<> 144:ef7eb2e8f9f7 685
<> 144:ef7eb2e8f9f7 686 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\
<> 144:ef7eb2e8f9f7 687 || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)\
<> 144:ef7eb2e8f9f7 688 || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
<> 144:ef7eb2e8f9f7 689
<> 144:ef7eb2e8f9f7 690 PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_ADC12;
<> 144:ef7eb2e8f9f7 691 /* Get the ADC1 & ADC2 clock configuration -----------------------------------------*/
<> 144:ef7eb2e8f9f7 692 PeriphClkInit->Adc12ClockSelection = __HAL_RCC_GET_ADC12_SOURCE();
<> 144:ef7eb2e8f9f7 693
<> 144:ef7eb2e8f9f7 694 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
<> 144:ef7eb2e8f9f7 695 /* STM32F302xC || STM32F303xC || STM32F358xx || */
<> 144:ef7eb2e8f9f7 696 /* STM32F303x8 || STM32F334x8 || STM32F328xx */
<> 144:ef7eb2e8f9f7 697
<> 144:ef7eb2e8f9f7 698 #if defined(STM32F303xE) || defined(STM32F398xx)\
<> 144:ef7eb2e8f9f7 699 || defined(STM32F303xC) || defined(STM32F358xx)
<> 144:ef7eb2e8f9f7 700
<> 144:ef7eb2e8f9f7 701 PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_ADC34;
<> 144:ef7eb2e8f9f7 702 /* Get the ADC3 & ADC4 clock configuration -----------------------------------------*/
<> 144:ef7eb2e8f9f7 703 PeriphClkInit->Adc34ClockSelection = __HAL_RCC_GET_ADC34_SOURCE();
<> 144:ef7eb2e8f9f7 704
<> 144:ef7eb2e8f9f7 705 #endif /* STM32F303xE || STM32F398xx || */
<> 144:ef7eb2e8f9f7 706 /* STM32F303xC || STM32F358xx */
<> 144:ef7eb2e8f9f7 707
<> 144:ef7eb2e8f9f7 708 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\
<> 144:ef7eb2e8f9f7 709 || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)\
<> 144:ef7eb2e8f9f7 710 || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)\
<> 144:ef7eb2e8f9f7 711 || defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
<> 144:ef7eb2e8f9f7 712
<> 144:ef7eb2e8f9f7 713 PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_TIM1;
<> 144:ef7eb2e8f9f7 714 /* Get the TIM1 clock configuration -----------------------------------------*/
<> 144:ef7eb2e8f9f7 715 PeriphClkInit->Tim1ClockSelection = __HAL_RCC_GET_TIM1_SOURCE();
<> 144:ef7eb2e8f9f7 716
<> 144:ef7eb2e8f9f7 717 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
<> 144:ef7eb2e8f9f7 718 /* STM32F302xC || STM32F303xC || STM32F358xx || */
<> 144:ef7eb2e8f9f7 719 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
<> 144:ef7eb2e8f9f7 720 /* STM32F301x8 || STM32F302x8 || STM32F318xx */
<> 144:ef7eb2e8f9f7 721
<> 144:ef7eb2e8f9f7 722 #if defined(STM32F303xE) || defined(STM32F398xx)\
<> 144:ef7eb2e8f9f7 723 || defined(STM32F303xC) || defined(STM32F358xx)
<> 144:ef7eb2e8f9f7 724
<> 144:ef7eb2e8f9f7 725 PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_TIM8;
<> 144:ef7eb2e8f9f7 726 /* Get the TIM8 clock configuration -----------------------------------------*/
<> 144:ef7eb2e8f9f7 727 PeriphClkInit->Tim8ClockSelection = __HAL_RCC_GET_TIM8_SOURCE();
<> 144:ef7eb2e8f9f7 728
<> 144:ef7eb2e8f9f7 729 #endif /* STM32F303xE || STM32F398xx || */
<> 144:ef7eb2e8f9f7 730 /* STM32F303xC || STM32F358xx */
<> 144:ef7eb2e8f9f7 731
<> 144:ef7eb2e8f9f7 732 #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
<> 144:ef7eb2e8f9f7 733
<> 144:ef7eb2e8f9f7 734 PeriphClkInit->PeriphClockSelection |= (RCC_PERIPHCLK_TIM15 | RCC_PERIPHCLK_TIM16 | RCC_PERIPHCLK_TIM17);
<> 144:ef7eb2e8f9f7 735 /* Get the TIM15 clock configuration -----------------------------------------*/
<> 144:ef7eb2e8f9f7 736 PeriphClkInit->Tim15ClockSelection = __HAL_RCC_GET_TIM15_SOURCE();
<> 144:ef7eb2e8f9f7 737 /* Get the TIM16 clock configuration -----------------------------------------*/
<> 144:ef7eb2e8f9f7 738 PeriphClkInit->Tim16ClockSelection = __HAL_RCC_GET_TIM16_SOURCE();
<> 144:ef7eb2e8f9f7 739 /* Get the TIM17 clock configuration -----------------------------------------*/
<> 144:ef7eb2e8f9f7 740 PeriphClkInit->Tim17ClockSelection = __HAL_RCC_GET_TIM17_SOURCE();
<> 144:ef7eb2e8f9f7 741
<> 144:ef7eb2e8f9f7 742 #endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */
<> 144:ef7eb2e8f9f7 743
<> 144:ef7eb2e8f9f7 744 #if defined(STM32F334x8)
<> 144:ef7eb2e8f9f7 745
<> 144:ef7eb2e8f9f7 746 PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_HRTIM1;
<> 144:ef7eb2e8f9f7 747 /* Get the HRTIM1 clock configuration -----------------------------------------*/
<> 144:ef7eb2e8f9f7 748 PeriphClkInit->Hrtim1ClockSelection = __HAL_RCC_GET_HRTIM1_SOURCE();
<> 144:ef7eb2e8f9f7 749
<> 144:ef7eb2e8f9f7 750 #endif /* STM32F334x8 */
<> 144:ef7eb2e8f9f7 751
<> 144:ef7eb2e8f9f7 752 #if defined(STM32F373xC) || defined(STM32F378xx)
<> 144:ef7eb2e8f9f7 753
<> 144:ef7eb2e8f9f7 754 PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_SDADC;
<> 144:ef7eb2e8f9f7 755 /* Get the SDADC clock configuration -----------------------------------------*/
<> 144:ef7eb2e8f9f7 756 PeriphClkInit->SdadcClockSelection = __HAL_RCC_GET_SDADC_SOURCE();
<> 144:ef7eb2e8f9f7 757
<> 144:ef7eb2e8f9f7 758 PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_CEC;
<> 144:ef7eb2e8f9f7 759 /* Get the CEC clock configuration -----------------------------------------*/
<> 144:ef7eb2e8f9f7 760 PeriphClkInit->CecClockSelection = __HAL_RCC_GET_CEC_SOURCE();
<> 144:ef7eb2e8f9f7 761
<> 144:ef7eb2e8f9f7 762 #endif /* STM32F373xC || STM32F378xx */
<> 144:ef7eb2e8f9f7 763
<> 144:ef7eb2e8f9f7 764 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
<> 144:ef7eb2e8f9f7 765
<> 144:ef7eb2e8f9f7 766 PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_TIM2;
<> 144:ef7eb2e8f9f7 767 /* Get the TIM2 clock configuration -----------------------------------------*/
<> 144:ef7eb2e8f9f7 768 PeriphClkInit->Tim2ClockSelection = __HAL_RCC_GET_TIM2_SOURCE();
<> 144:ef7eb2e8f9f7 769
<> 144:ef7eb2e8f9f7 770 PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_TIM34;
<> 144:ef7eb2e8f9f7 771 /* Get the TIM3 clock configuration -----------------------------------------*/
<> 144:ef7eb2e8f9f7 772 PeriphClkInit->Tim34ClockSelection = __HAL_RCC_GET_TIM34_SOURCE();
<> 144:ef7eb2e8f9f7 773
<> 144:ef7eb2e8f9f7 774 PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_TIM15;
<> 144:ef7eb2e8f9f7 775 /* Get the TIM15 clock configuration -----------------------------------------*/
<> 144:ef7eb2e8f9f7 776 PeriphClkInit->Tim15ClockSelection = __HAL_RCC_GET_TIM15_SOURCE();
<> 144:ef7eb2e8f9f7 777
<> 144:ef7eb2e8f9f7 778 PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_TIM16;
<> 144:ef7eb2e8f9f7 779 /* Get the TIM16 clock configuration -----------------------------------------*/
<> 144:ef7eb2e8f9f7 780 PeriphClkInit->Tim16ClockSelection = __HAL_RCC_GET_TIM16_SOURCE();
<> 144:ef7eb2e8f9f7 781
<> 144:ef7eb2e8f9f7 782 PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_TIM17;
<> 144:ef7eb2e8f9f7 783 /* Get the TIM17 clock configuration -----------------------------------------*/
<> 144:ef7eb2e8f9f7 784 PeriphClkInit->Tim17ClockSelection = __HAL_RCC_GET_TIM17_SOURCE();
<> 144:ef7eb2e8f9f7 785
<> 144:ef7eb2e8f9f7 786 #endif /* STM32F302xE || STM32F303xE || STM32F398xx */
<> 144:ef7eb2e8f9f7 787
<> 144:ef7eb2e8f9f7 788 #if defined (STM32F303xE) || defined(STM32F398xx)
<> 144:ef7eb2e8f9f7 789 PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_TIM20;
<> 144:ef7eb2e8f9f7 790 /* Get the TIM20 clock configuration -----------------------------------------*/
<> 144:ef7eb2e8f9f7 791 PeriphClkInit->Tim20ClockSelection = __HAL_RCC_GET_TIM20_SOURCE();
<> 144:ef7eb2e8f9f7 792 #endif /* STM32F303xE || STM32F398xx */
<> 144:ef7eb2e8f9f7 793 }
<> 144:ef7eb2e8f9f7 794
<> 144:ef7eb2e8f9f7 795 /**
<> 144:ef7eb2e8f9f7 796 * @brief Returns the peripheral clock frequency
<> 144:ef7eb2e8f9f7 797 * @note Returns 0 if peripheral clock is unknown or 0xDEADDEAD if not applicable.
<> 144:ef7eb2e8f9f7 798 * @param PeriphClk Peripheral clock identifier
<> 144:ef7eb2e8f9f7 799 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 800 * @arg @ref RCC_PERIPHCLK_RTC RTC peripheral clock
<> 144:ef7eb2e8f9f7 801 * @arg @ref RCC_PERIPHCLK_USART1 USART1 peripheral clock
<> 144:ef7eb2e8f9f7 802 * @arg @ref RCC_PERIPHCLK_I2C1 I2C1 peripheral clock
<> 144:ef7eb2e8f9f7 803 @if STM32F301x8
<> 144:ef7eb2e8f9f7 804 * @arg @ref RCC_PERIPHCLK_I2C2 I2C2 peripheral clock
<> 144:ef7eb2e8f9f7 805 * @arg @ref RCC_PERIPHCLK_I2C3 I2C3 peripheral clock
<> 144:ef7eb2e8f9f7 806 * @arg @ref RCC_PERIPHCLK_I2S I2S peripheral clock
<> 144:ef7eb2e8f9f7 807 * @arg @ref RCC_PERIPHCLK_ADC1 ADC1 peripheral clock
<> 144:ef7eb2e8f9f7 808 * @arg @ref RCC_PERIPHCLK_TIM1 TIM1 peripheral clock
<> 144:ef7eb2e8f9f7 809 * @arg @ref RCC_PERIPHCLK_TIM15 TIM15 peripheral clock
<> 144:ef7eb2e8f9f7 810 * @arg @ref RCC_PERIPHCLK_TIM16 TIM16 peripheral clock
<> 144:ef7eb2e8f9f7 811 * @arg @ref RCC_PERIPHCLK_TIM17 TIM17 peripheral clock
<> 144:ef7eb2e8f9f7 812 @endif
<> 144:ef7eb2e8f9f7 813 @if STM32F302x8
<> 144:ef7eb2e8f9f7 814 * @arg @ref RCC_PERIPHCLK_I2C2 I2C2 peripheral clock
<> 144:ef7eb2e8f9f7 815 * @arg @ref RCC_PERIPHCLK_I2C3 I2C3 peripheral clock
<> 144:ef7eb2e8f9f7 816 * @arg @ref RCC_PERIPHCLK_I2S I2S peripheral clock
<> 144:ef7eb2e8f9f7 817 * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock
<> 144:ef7eb2e8f9f7 818 * @arg @ref RCC_PERIPHCLK_ADC1 ADC1 peripheral clock
<> 144:ef7eb2e8f9f7 819 * @arg @ref RCC_PERIPHCLK_TIM1 TIM1 peripheral clock
<> 144:ef7eb2e8f9f7 820 * @arg @ref RCC_PERIPHCLK_TIM15 TIM15 peripheral clock
<> 144:ef7eb2e8f9f7 821 * @arg @ref RCC_PERIPHCLK_TIM16 TIM16 peripheral clock
<> 144:ef7eb2e8f9f7 822 * @arg @ref RCC_PERIPHCLK_TIM17 TIM17 peripheral clock
<> 144:ef7eb2e8f9f7 823 @endif
<> 144:ef7eb2e8f9f7 824 @if STM32F302xC
<> 144:ef7eb2e8f9f7 825 * @arg @ref RCC_PERIPHCLK_USART2 USART2 peripheral clock
<> 144:ef7eb2e8f9f7 826 * @arg @ref RCC_PERIPHCLK_USART3 USART3 peripheral clock
<> 144:ef7eb2e8f9f7 827 * @arg @ref RCC_PERIPHCLK_UART4 UART4 peripheral clock
<> 144:ef7eb2e8f9f7 828 * @arg @ref RCC_PERIPHCLK_UART5 UART5 peripheral clock
<> 144:ef7eb2e8f9f7 829 * @arg @ref RCC_PERIPHCLK_I2C2 I2C2 peripheral clock
<> 144:ef7eb2e8f9f7 830 * @arg @ref RCC_PERIPHCLK_I2S I2S peripheral clock
<> 144:ef7eb2e8f9f7 831 * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock
<> 144:ef7eb2e8f9f7 832 * @arg @ref RCC_PERIPHCLK_ADC12 ADC12 peripheral clock
<> 144:ef7eb2e8f9f7 833 * @arg @ref RCC_PERIPHCLK_TIM1 TIM1 peripheral clock
<> 144:ef7eb2e8f9f7 834 @endif
<> 144:ef7eb2e8f9f7 835 @if STM32F302xE
<> 144:ef7eb2e8f9f7 836 * @arg @ref RCC_PERIPHCLK_USART2 USART2 peripheral clock
<> 144:ef7eb2e8f9f7 837 * @arg @ref RCC_PERIPHCLK_USART3 USART3 peripheral clock
<> 144:ef7eb2e8f9f7 838 * @arg @ref RCC_PERIPHCLK_UART4 UART4 peripheral clock
<> 144:ef7eb2e8f9f7 839 * @arg @ref RCC_PERIPHCLK_UART5 UART5 peripheral clock
<> 144:ef7eb2e8f9f7 840 * @arg @ref RCC_PERIPHCLK_I2C2 I2C2 peripheral clock
<> 144:ef7eb2e8f9f7 841 * @arg @ref RCC_PERIPHCLK_I2C3 I2C3 peripheral clock
<> 144:ef7eb2e8f9f7 842 * @arg @ref RCC_PERIPHCLK_I2S I2S peripheral clock
<> 144:ef7eb2e8f9f7 843 * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock
<> 144:ef7eb2e8f9f7 844 * @arg @ref RCC_PERIPHCLK_ADC12 ADC12 peripheral clock
<> 144:ef7eb2e8f9f7 845 * @arg @ref RCC_PERIPHCLK_TIM1 TIM1 peripheral clock
<> 144:ef7eb2e8f9f7 846 * @arg @ref RCC_PERIPHCLK_TIM2 TIM2 peripheral clock
<> 144:ef7eb2e8f9f7 847 * @arg @ref RCC_PERIPHCLK_TIM15 TIM15 peripheral clock
<> 144:ef7eb2e8f9f7 848 * @arg @ref RCC_PERIPHCLK_TIM16 TIM16 peripheral clock
<> 144:ef7eb2e8f9f7 849 * @arg @ref RCC_PERIPHCLK_TIM17 TIM17 peripheral clock
<> 144:ef7eb2e8f9f7 850 * @arg @ref RCC_PERIPHCLK_TIM34 TIM34 peripheral clock
<> 144:ef7eb2e8f9f7 851 @endif
<> 144:ef7eb2e8f9f7 852 @if STM32F303x8
<> 144:ef7eb2e8f9f7 853 * @arg @ref RCC_PERIPHCLK_ADC12 ADC12 peripheral clock
<> 144:ef7eb2e8f9f7 854 * @arg @ref RCC_PERIPHCLK_TIM1 TIM1 peripheral clock
<> 144:ef7eb2e8f9f7 855 @endif
<> 144:ef7eb2e8f9f7 856 @if STM32F303xC
<> 144:ef7eb2e8f9f7 857 * @arg @ref RCC_PERIPHCLK_USART2 USART2 peripheral clock
<> 144:ef7eb2e8f9f7 858 * @arg @ref RCC_PERIPHCLK_USART3 USART3 peripheral clock
<> 144:ef7eb2e8f9f7 859 * @arg @ref RCC_PERIPHCLK_UART4 UART4 peripheral clock
<> 144:ef7eb2e8f9f7 860 * @arg @ref RCC_PERIPHCLK_UART5 UART5 peripheral clock
<> 144:ef7eb2e8f9f7 861 * @arg @ref RCC_PERIPHCLK_I2C2 I2C2 peripheral clock
<> 144:ef7eb2e8f9f7 862 * @arg @ref RCC_PERIPHCLK_I2S I2S peripheral clock
<> 144:ef7eb2e8f9f7 863 * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock
<> 144:ef7eb2e8f9f7 864 * @arg @ref RCC_PERIPHCLK_ADC12 ADC12 peripheral clock
<> 144:ef7eb2e8f9f7 865 * @arg @ref RCC_PERIPHCLK_ADC34 ADC34 peripheral clock
<> 144:ef7eb2e8f9f7 866 * @arg @ref RCC_PERIPHCLK_TIM1 TIM1 peripheral clock
<> 144:ef7eb2e8f9f7 867 * @arg @ref RCC_PERIPHCLK_TIM8 TIM8 peripheral clock
<> 144:ef7eb2e8f9f7 868 @endif
<> 144:ef7eb2e8f9f7 869 @if STM32F303xE
<> 144:ef7eb2e8f9f7 870 * @arg @ref RCC_PERIPHCLK_USART2 USART2 peripheral clock
<> 144:ef7eb2e8f9f7 871 * @arg @ref RCC_PERIPHCLK_USART3 USART3 peripheral clock
<> 144:ef7eb2e8f9f7 872 * @arg @ref RCC_PERIPHCLK_UART4 UART4 peripheral clock
<> 144:ef7eb2e8f9f7 873 * @arg @ref RCC_PERIPHCLK_UART5 UART5 peripheral clock
<> 144:ef7eb2e8f9f7 874 * @arg @ref RCC_PERIPHCLK_I2C2 I2C2 peripheral clock
<> 144:ef7eb2e8f9f7 875 * @arg @ref RCC_PERIPHCLK_I2C3 I2C3 peripheral clock
<> 144:ef7eb2e8f9f7 876 * @arg @ref RCC_PERIPHCLK_I2S I2S peripheral clock
<> 144:ef7eb2e8f9f7 877 * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock
<> 144:ef7eb2e8f9f7 878 * @arg @ref RCC_PERIPHCLK_ADC12 ADC12 peripheral clock
<> 144:ef7eb2e8f9f7 879 * @arg @ref RCC_PERIPHCLK_ADC34 ADC34 peripheral clock
<> 144:ef7eb2e8f9f7 880 * @arg @ref RCC_PERIPHCLK_TIM1 TIM1 peripheral clock
<> 144:ef7eb2e8f9f7 881 * @arg @ref RCC_PERIPHCLK_TIM2 TIM2 peripheral clock
<> 144:ef7eb2e8f9f7 882 * @arg @ref RCC_PERIPHCLK_TIM8 TIM8 peripheral clock
<> 144:ef7eb2e8f9f7 883 * @arg @ref RCC_PERIPHCLK_TIM15 TIM15 peripheral clock
<> 144:ef7eb2e8f9f7 884 * @arg @ref RCC_PERIPHCLK_TIM16 TIM16 peripheral clock
<> 144:ef7eb2e8f9f7 885 * @arg @ref RCC_PERIPHCLK_TIM17 TIM17 peripheral clock
<> 144:ef7eb2e8f9f7 886 * @arg @ref RCC_PERIPHCLK_TIM20 TIM20 peripheral clock
<> 144:ef7eb2e8f9f7 887 * @arg @ref RCC_PERIPHCLK_TIM34 TIM34 peripheral clock
<> 144:ef7eb2e8f9f7 888 @endif
<> 144:ef7eb2e8f9f7 889 @if STM32F318xx
<> 144:ef7eb2e8f9f7 890 * @arg @ref RCC_PERIPHCLK_I2C2 I2C2 peripheral clock
<> 144:ef7eb2e8f9f7 891 * @arg @ref RCC_PERIPHCLK_I2C3 I2C3 peripheral clock
<> 144:ef7eb2e8f9f7 892 * @arg @ref RCC_PERIPHCLK_I2S I2S peripheral clock
<> 144:ef7eb2e8f9f7 893 * @arg @ref RCC_PERIPHCLK_ADC1 ADC1 peripheral clock
<> 144:ef7eb2e8f9f7 894 * @arg @ref RCC_PERIPHCLK_TIM1 TIM1 peripheral clock
<> 144:ef7eb2e8f9f7 895 * @arg @ref RCC_PERIPHCLK_TIM15 TIM15 peripheral clock
<> 144:ef7eb2e8f9f7 896 * @arg @ref RCC_PERIPHCLK_TIM16 TIM16 peripheral clock
<> 144:ef7eb2e8f9f7 897 * @arg @ref RCC_PERIPHCLK_TIM17 TIM17 peripheral clock
<> 144:ef7eb2e8f9f7 898 @endif
<> 144:ef7eb2e8f9f7 899 @if STM32F328xx
<> 144:ef7eb2e8f9f7 900 * @arg @ref RCC_PERIPHCLK_I2C2 I2C2 peripheral clock
<> 144:ef7eb2e8f9f7 901 * @arg @ref RCC_PERIPHCLK_ADC12 ADC12 peripheral clock
<> 144:ef7eb2e8f9f7 902 * @arg @ref RCC_PERIPHCLK_TIM1 TIM1 peripheral clock
<> 144:ef7eb2e8f9f7 903 @endif
<> 144:ef7eb2e8f9f7 904 @if STM32F334x8
<> 144:ef7eb2e8f9f7 905 * @arg @ref RCC_PERIPHCLK_ADC12 ADC12 peripheral clock
<> 144:ef7eb2e8f9f7 906 * @arg @ref RCC_PERIPHCLK_TIM1 TIM1 peripheral clock
<> 144:ef7eb2e8f9f7 907 * @arg @ref RCC_PERIPHCLK_HRTIM1 HRTIM1 peripheral clock
<> 144:ef7eb2e8f9f7 908 @endif
<> 144:ef7eb2e8f9f7 909 @if STM32F358xx
<> 144:ef7eb2e8f9f7 910 * @arg @ref RCC_PERIPHCLK_USART2 USART2 peripheral clock
<> 144:ef7eb2e8f9f7 911 * @arg @ref RCC_PERIPHCLK_USART3 USART3 peripheral clock
<> 144:ef7eb2e8f9f7 912 * @arg @ref RCC_PERIPHCLK_UART4 UART4 peripheral clock
<> 144:ef7eb2e8f9f7 913 * @arg @ref RCC_PERIPHCLK_UART5 UART5 peripheral clock
<> 144:ef7eb2e8f9f7 914 * @arg @ref RCC_PERIPHCLK_I2S I2S peripheral clock
<> 144:ef7eb2e8f9f7 915 * @arg @ref RCC_PERIPHCLK_ADC12 ADC12 peripheral clock
<> 144:ef7eb2e8f9f7 916 * @arg @ref RCC_PERIPHCLK_ADC34 ADC34 peripheral clock
<> 144:ef7eb2e8f9f7 917 * @arg @ref RCC_PERIPHCLK_TIM1 TIM1 peripheral clock
<> 144:ef7eb2e8f9f7 918 * @arg @ref RCC_PERIPHCLK_TIM8 TIM8 peripheral clock
<> 144:ef7eb2e8f9f7 919 @endif
<> 144:ef7eb2e8f9f7 920 @if STM32F373xC
<> 144:ef7eb2e8f9f7 921 * @arg @ref RCC_PERIPHCLK_USART2 USART2 peripheral clock
<> 144:ef7eb2e8f9f7 922 * @arg @ref RCC_PERIPHCLK_USART3 USART3 peripheral clock
<> 144:ef7eb2e8f9f7 923 * @arg @ref RCC_PERIPHCLK_I2C2 I2C2 peripheral clock
<> 144:ef7eb2e8f9f7 924 * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock
<> 144:ef7eb2e8f9f7 925 * @arg @ref RCC_PERIPHCLK_ADC1 ADC1 peripheral clock
<> 144:ef7eb2e8f9f7 926 * @arg @ref RCC_PERIPHCLK_SDADC SDADC peripheral clock
<> 144:ef7eb2e8f9f7 927 * @arg @ref RCC_PERIPHCLK_CEC CEC peripheral clock
<> 144:ef7eb2e8f9f7 928 @endif
<> 144:ef7eb2e8f9f7 929 @if STM32F378xx
<> 144:ef7eb2e8f9f7 930 * @arg @ref RCC_PERIPHCLK_USART2 USART2 peripheral clock
<> 144:ef7eb2e8f9f7 931 * @arg @ref RCC_PERIPHCLK_USART3 USART3 peripheral clock
<> 144:ef7eb2e8f9f7 932 * @arg @ref RCC_PERIPHCLK_I2C2 I2C2 peripheral clock
<> 144:ef7eb2e8f9f7 933 * @arg @ref RCC_PERIPHCLK_ADC1 ADC1 peripheral clock
<> 144:ef7eb2e8f9f7 934 * @arg @ref RCC_PERIPHCLK_SDADC SDADC peripheral clock
<> 144:ef7eb2e8f9f7 935 * @arg @ref RCC_PERIPHCLK_CEC CEC peripheral clock
<> 144:ef7eb2e8f9f7 936 @endif
<> 144:ef7eb2e8f9f7 937 @if STM32F398xx
<> 144:ef7eb2e8f9f7 938 * @arg @ref RCC_PERIPHCLK_USART2 USART2 peripheral clock
<> 144:ef7eb2e8f9f7 939 * @arg @ref RCC_PERIPHCLK_USART3 USART3 peripheral clock
<> 144:ef7eb2e8f9f7 940 * @arg @ref RCC_PERIPHCLK_UART4 UART4 peripheral clock
<> 144:ef7eb2e8f9f7 941 * @arg @ref RCC_PERIPHCLK_UART5 UART5 peripheral clock
<> 144:ef7eb2e8f9f7 942 * @arg @ref RCC_PERIPHCLK_I2C2 I2C2 peripheral clock
<> 144:ef7eb2e8f9f7 943 * @arg @ref RCC_PERIPHCLK_I2C3 I2C3 peripheral clock
<> 144:ef7eb2e8f9f7 944 * @arg @ref RCC_PERIPHCLK_I2S I2S peripheral clock
<> 144:ef7eb2e8f9f7 945 * @arg @ref RCC_PERIPHCLK_ADC12 ADC12 peripheral clock
<> 144:ef7eb2e8f9f7 946 * @arg @ref RCC_PERIPHCLK_ADC34 ADC34 peripheral clock
<> 144:ef7eb2e8f9f7 947 * @arg @ref RCC_PERIPHCLK_TIM1 TIM1 peripheral clock
<> 144:ef7eb2e8f9f7 948 * @arg @ref RCC_PERIPHCLK_TIM2 TIM2 peripheral clock
<> 144:ef7eb2e8f9f7 949 * @arg @ref RCC_PERIPHCLK_TIM8 TIM8 peripheral clock
<> 144:ef7eb2e8f9f7 950 * @arg @ref RCC_PERIPHCLK_TIM15 TIM15 peripheral clock
<> 144:ef7eb2e8f9f7 951 * @arg @ref RCC_PERIPHCLK_TIM16 TIM16 peripheral clock
<> 144:ef7eb2e8f9f7 952 * @arg @ref RCC_PERIPHCLK_TIM17 TIM17 peripheral clock
<> 144:ef7eb2e8f9f7 953 * @arg @ref RCC_PERIPHCLK_TIM20 TIM20 peripheral clock
<> 144:ef7eb2e8f9f7 954 * @arg @ref RCC_PERIPHCLK_TIM34 TIM34 peripheral clock
<> 144:ef7eb2e8f9f7 955 @endif
<> 144:ef7eb2e8f9f7 956 * @retval Frequency in Hz (0: means that no available frequency for the peripheral)
<> 144:ef7eb2e8f9f7 957 */
<> 144:ef7eb2e8f9f7 958 uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
<> 144:ef7eb2e8f9f7 959 {
Anna Bridge 186:707f6e361f3e 960 /* frequency == 0 : means that no available frequency for the peripheral */
<> 157:ff67d9f36b67 961 uint32_t frequency = 0U;
Anna Bridge 186:707f6e361f3e 962
<> 157:ff67d9f36b67 963 uint32_t srcclk = 0U;
<> 144:ef7eb2e8f9f7 964 #if defined(RCC_CFGR2_ADC1PRES) || defined(RCC_CFGR2_ADCPRE12) || defined(RCC_CFGR2_ADCPRE34)
Anna Bridge 186:707f6e361f3e 965 uint16_t adc_pll_prediv_table[16] = { 1U, 2U, 4U, 6U, 8U, 10U, 12U, 16U, 32U, 64U, 128U, 256U, 256U, 256U, 256U, 256U};
<> 144:ef7eb2e8f9f7 966 #endif /* RCC_CFGR2_ADC1PRES || RCC_CFGR2_ADCPRE12 || RCC_CFGR2_ADCPRE34 */
<> 157:ff67d9f36b67 967 #if defined(RCC_CFGR_SDPRE)
<> 157:ff67d9f36b67 968 uint8_t sdadc_prescaler_table[16] = { 2U, 4U, 6U, 8U, 10U, 12U, 14U, 16U, 20U, 24U, 28U, 32U, 36U, 40U, 44U, 48U};
<> 157:ff67d9f36b67 969 #endif /* RCC_CFGR_SDPRE */
<> 144:ef7eb2e8f9f7 970
<> 144:ef7eb2e8f9f7 971 /* Check the parameters */
<> 144:ef7eb2e8f9f7 972 assert_param(IS_RCC_PERIPHCLOCK(PeriphClk));
<> 144:ef7eb2e8f9f7 973
<> 144:ef7eb2e8f9f7 974 switch (PeriphClk)
<> 144:ef7eb2e8f9f7 975 {
<> 144:ef7eb2e8f9f7 976 case RCC_PERIPHCLK_RTC:
<> 144:ef7eb2e8f9f7 977 {
<> 144:ef7eb2e8f9f7 978 /* Get the current RTC source */
<> 144:ef7eb2e8f9f7 979 srcclk = __HAL_RCC_GET_RTC_SOURCE();
<> 144:ef7eb2e8f9f7 980
<> 144:ef7eb2e8f9f7 981 /* Check if LSE is ready and if RTC clock selection is LSE */
<> 144:ef7eb2e8f9f7 982 if ((srcclk == RCC_RTCCLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)))
<> 144:ef7eb2e8f9f7 983 {
<> 144:ef7eb2e8f9f7 984 frequency = LSE_VALUE;
<> 144:ef7eb2e8f9f7 985 }
<> 144:ef7eb2e8f9f7 986 /* Check if LSI is ready and if RTC clock selection is LSI */
<> 144:ef7eb2e8f9f7 987 else if ((srcclk == RCC_RTCCLKSOURCE_LSI) && (HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIRDY)))
<> 144:ef7eb2e8f9f7 988 {
<> 144:ef7eb2e8f9f7 989 frequency = LSI_VALUE;
<> 144:ef7eb2e8f9f7 990 }
<> 144:ef7eb2e8f9f7 991 /* Check if HSE is ready and if RTC clock selection is HSI_DIV32*/
<> 144:ef7eb2e8f9f7 992 else if ((srcclk == RCC_RTCCLKSOURCE_HSE_DIV32) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)))
<> 144:ef7eb2e8f9f7 993 {
<> 157:ff67d9f36b67 994 frequency = HSE_VALUE / 32U;
<> 144:ef7eb2e8f9f7 995 }
<> 144:ef7eb2e8f9f7 996 break;
<> 144:ef7eb2e8f9f7 997 }
<> 144:ef7eb2e8f9f7 998 case RCC_PERIPHCLK_USART1:
<> 144:ef7eb2e8f9f7 999 {
<> 144:ef7eb2e8f9f7 1000 /* Get the current USART1 source */
<> 144:ef7eb2e8f9f7 1001 srcclk = __HAL_RCC_GET_USART1_SOURCE();
<> 144:ef7eb2e8f9f7 1002
<> 144:ef7eb2e8f9f7 1003 /* Check if USART1 clock selection is PCLK1 */
<> 144:ef7eb2e8f9f7 1004 #if defined(RCC_USART1CLKSOURCE_PCLK2)
<> 144:ef7eb2e8f9f7 1005 if (srcclk == RCC_USART1CLKSOURCE_PCLK2)
<> 144:ef7eb2e8f9f7 1006 {
<> 144:ef7eb2e8f9f7 1007 frequency = HAL_RCC_GetPCLK2Freq();
<> 144:ef7eb2e8f9f7 1008 }
<> 144:ef7eb2e8f9f7 1009 #else
<> 144:ef7eb2e8f9f7 1010 if (srcclk == RCC_USART1CLKSOURCE_PCLK1)
<> 144:ef7eb2e8f9f7 1011 {
<> 144:ef7eb2e8f9f7 1012 frequency = HAL_RCC_GetPCLK1Freq();
<> 144:ef7eb2e8f9f7 1013 }
<> 144:ef7eb2e8f9f7 1014 #endif /* RCC_USART1CLKSOURCE_PCLK2 */
<> 144:ef7eb2e8f9f7 1015 /* Check if HSI is ready and if USART1 clock selection is HSI */
<> 144:ef7eb2e8f9f7 1016 else if ((srcclk == RCC_USART1CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)))
<> 144:ef7eb2e8f9f7 1017 {
<> 144:ef7eb2e8f9f7 1018 frequency = HSI_VALUE;
<> 144:ef7eb2e8f9f7 1019 }
<> 144:ef7eb2e8f9f7 1020 /* Check if USART1 clock selection is SYSCLK */
<> 144:ef7eb2e8f9f7 1021 else if (srcclk == RCC_USART1CLKSOURCE_SYSCLK)
<> 144:ef7eb2e8f9f7 1022 {
<> 144:ef7eb2e8f9f7 1023 frequency = HAL_RCC_GetSysClockFreq();
<> 144:ef7eb2e8f9f7 1024 }
<> 144:ef7eb2e8f9f7 1025 /* Check if LSE is ready and if USART1 clock selection is LSE */
<> 144:ef7eb2e8f9f7 1026 else if ((srcclk == RCC_USART1CLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)))
<> 144:ef7eb2e8f9f7 1027 {
<> 144:ef7eb2e8f9f7 1028 frequency = LSE_VALUE;
<> 144:ef7eb2e8f9f7 1029 }
<> 144:ef7eb2e8f9f7 1030 break;
<> 144:ef7eb2e8f9f7 1031 }
<> 144:ef7eb2e8f9f7 1032 #if defined(RCC_CFGR3_USART2SW)
<> 144:ef7eb2e8f9f7 1033 case RCC_PERIPHCLK_USART2:
<> 144:ef7eb2e8f9f7 1034 {
<> 144:ef7eb2e8f9f7 1035 /* Get the current USART2 source */
<> 144:ef7eb2e8f9f7 1036 srcclk = __HAL_RCC_GET_USART2_SOURCE();
<> 144:ef7eb2e8f9f7 1037
<> 144:ef7eb2e8f9f7 1038 /* Check if USART2 clock selection is PCLK1 */
<> 144:ef7eb2e8f9f7 1039 if (srcclk == RCC_USART2CLKSOURCE_PCLK1)
<> 144:ef7eb2e8f9f7 1040 {
<> 144:ef7eb2e8f9f7 1041 frequency = HAL_RCC_GetPCLK1Freq();
<> 144:ef7eb2e8f9f7 1042 }
<> 144:ef7eb2e8f9f7 1043 /* Check if HSI is ready and if USART2 clock selection is HSI */
<> 144:ef7eb2e8f9f7 1044 else if ((srcclk == RCC_USART2CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)))
<> 144:ef7eb2e8f9f7 1045 {
<> 144:ef7eb2e8f9f7 1046 frequency = HSI_VALUE;
<> 144:ef7eb2e8f9f7 1047 }
<> 144:ef7eb2e8f9f7 1048 /* Check if USART2 clock selection is SYSCLK */
<> 144:ef7eb2e8f9f7 1049 else if (srcclk == RCC_USART2CLKSOURCE_SYSCLK)
<> 144:ef7eb2e8f9f7 1050 {
<> 144:ef7eb2e8f9f7 1051 frequency = HAL_RCC_GetSysClockFreq();
<> 144:ef7eb2e8f9f7 1052 }
<> 144:ef7eb2e8f9f7 1053 /* Check if LSE is ready and if USART2 clock selection is LSE */
<> 144:ef7eb2e8f9f7 1054 else if ((srcclk == RCC_USART2CLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)))
<> 144:ef7eb2e8f9f7 1055 {
<> 144:ef7eb2e8f9f7 1056 frequency = LSE_VALUE;
<> 144:ef7eb2e8f9f7 1057 }
<> 144:ef7eb2e8f9f7 1058 break;
<> 144:ef7eb2e8f9f7 1059 }
<> 144:ef7eb2e8f9f7 1060 #endif /* RCC_CFGR3_USART2SW */
<> 144:ef7eb2e8f9f7 1061 #if defined(RCC_CFGR3_USART3SW)
<> 144:ef7eb2e8f9f7 1062 case RCC_PERIPHCLK_USART3:
<> 144:ef7eb2e8f9f7 1063 {
<> 144:ef7eb2e8f9f7 1064 /* Get the current USART3 source */
<> 144:ef7eb2e8f9f7 1065 srcclk = __HAL_RCC_GET_USART3_SOURCE();
<> 144:ef7eb2e8f9f7 1066
<> 144:ef7eb2e8f9f7 1067 /* Check if USART3 clock selection is PCLK1 */
<> 144:ef7eb2e8f9f7 1068 if (srcclk == RCC_USART3CLKSOURCE_PCLK1)
<> 144:ef7eb2e8f9f7 1069 {
<> 144:ef7eb2e8f9f7 1070 frequency = HAL_RCC_GetPCLK1Freq();
<> 144:ef7eb2e8f9f7 1071 }
<> 144:ef7eb2e8f9f7 1072 /* Check if HSI is ready and if USART3 clock selection is HSI */
<> 144:ef7eb2e8f9f7 1073 else if ((srcclk == RCC_USART3CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)))
<> 144:ef7eb2e8f9f7 1074 {
<> 144:ef7eb2e8f9f7 1075 frequency = HSI_VALUE;
<> 144:ef7eb2e8f9f7 1076 }
<> 144:ef7eb2e8f9f7 1077 /* Check if USART3 clock selection is SYSCLK */
<> 144:ef7eb2e8f9f7 1078 else if (srcclk == RCC_USART3CLKSOURCE_SYSCLK)
<> 144:ef7eb2e8f9f7 1079 {
<> 144:ef7eb2e8f9f7 1080 frequency = HAL_RCC_GetSysClockFreq();
<> 144:ef7eb2e8f9f7 1081 }
<> 144:ef7eb2e8f9f7 1082 /* Check if LSE is ready and if USART3 clock selection is LSE */
<> 144:ef7eb2e8f9f7 1083 else if ((srcclk == RCC_USART3CLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)))
<> 144:ef7eb2e8f9f7 1084 {
<> 144:ef7eb2e8f9f7 1085 frequency = LSE_VALUE;
<> 144:ef7eb2e8f9f7 1086 }
Anna Bridge 186:707f6e361f3e 1087 break;
<> 144:ef7eb2e8f9f7 1088 }
<> 144:ef7eb2e8f9f7 1089 #endif /* RCC_CFGR3_USART3SW */
<> 144:ef7eb2e8f9f7 1090 #if defined(RCC_CFGR3_UART4SW)
<> 144:ef7eb2e8f9f7 1091 case RCC_PERIPHCLK_UART4:
<> 144:ef7eb2e8f9f7 1092 {
<> 144:ef7eb2e8f9f7 1093 /* Get the current UART4 source */
<> 144:ef7eb2e8f9f7 1094 srcclk = __HAL_RCC_GET_UART4_SOURCE();
<> 144:ef7eb2e8f9f7 1095
<> 144:ef7eb2e8f9f7 1096 /* Check if UART4 clock selection is PCLK1 */
<> 144:ef7eb2e8f9f7 1097 if (srcclk == RCC_UART4CLKSOURCE_PCLK1)
<> 144:ef7eb2e8f9f7 1098 {
<> 144:ef7eb2e8f9f7 1099 frequency = HAL_RCC_GetPCLK1Freq();
<> 144:ef7eb2e8f9f7 1100 }
<> 144:ef7eb2e8f9f7 1101 /* Check if HSI is ready and if UART4 clock selection is HSI */
<> 144:ef7eb2e8f9f7 1102 else if ((srcclk == RCC_UART4CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)))
<> 144:ef7eb2e8f9f7 1103 {
<> 144:ef7eb2e8f9f7 1104 frequency = HSI_VALUE;
<> 144:ef7eb2e8f9f7 1105 }
<> 144:ef7eb2e8f9f7 1106 /* Check if UART4 clock selection is SYSCLK */
<> 144:ef7eb2e8f9f7 1107 else if (srcclk == RCC_UART4CLKSOURCE_SYSCLK)
<> 144:ef7eb2e8f9f7 1108 {
<> 144:ef7eb2e8f9f7 1109 frequency = HAL_RCC_GetSysClockFreq();
<> 144:ef7eb2e8f9f7 1110 }
<> 144:ef7eb2e8f9f7 1111 /* Check if LSE is ready and if UART4 clock selection is LSE */
<> 144:ef7eb2e8f9f7 1112 else if ((srcclk == RCC_UART4CLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)))
<> 144:ef7eb2e8f9f7 1113 {
<> 144:ef7eb2e8f9f7 1114 frequency = LSE_VALUE;
<> 144:ef7eb2e8f9f7 1115 }
<> 144:ef7eb2e8f9f7 1116 break;
<> 144:ef7eb2e8f9f7 1117 }
<> 144:ef7eb2e8f9f7 1118 #endif /* RCC_CFGR3_UART4SW */
<> 144:ef7eb2e8f9f7 1119 #if defined(RCC_CFGR3_UART5SW)
<> 144:ef7eb2e8f9f7 1120 case RCC_PERIPHCLK_UART5:
<> 144:ef7eb2e8f9f7 1121 {
<> 144:ef7eb2e8f9f7 1122 /* Get the current UART5 source */
<> 144:ef7eb2e8f9f7 1123 srcclk = __HAL_RCC_GET_UART5_SOURCE();
<> 144:ef7eb2e8f9f7 1124
<> 144:ef7eb2e8f9f7 1125 /* Check if UART5 clock selection is PCLK1 */
<> 144:ef7eb2e8f9f7 1126 if (srcclk == RCC_UART5CLKSOURCE_PCLK1)
<> 144:ef7eb2e8f9f7 1127 {
<> 144:ef7eb2e8f9f7 1128 frequency = HAL_RCC_GetPCLK1Freq();
<> 144:ef7eb2e8f9f7 1129 }
<> 144:ef7eb2e8f9f7 1130 /* Check if HSI is ready and if UART5 clock selection is HSI */
<> 144:ef7eb2e8f9f7 1131 else if ((srcclk == RCC_UART5CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)))
<> 144:ef7eb2e8f9f7 1132 {
<> 144:ef7eb2e8f9f7 1133 frequency = HSI_VALUE;
<> 144:ef7eb2e8f9f7 1134 }
<> 144:ef7eb2e8f9f7 1135 /* Check if UART5 clock selection is SYSCLK */
<> 144:ef7eb2e8f9f7 1136 else if (srcclk == RCC_UART5CLKSOURCE_SYSCLK)
<> 144:ef7eb2e8f9f7 1137 {
<> 144:ef7eb2e8f9f7 1138 frequency = HAL_RCC_GetSysClockFreq();
<> 144:ef7eb2e8f9f7 1139 }
<> 144:ef7eb2e8f9f7 1140 /* Check if LSE is ready and if UART5 clock selection is LSE */
<> 144:ef7eb2e8f9f7 1141 else if ((srcclk == RCC_UART5CLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)))
<> 144:ef7eb2e8f9f7 1142 {
<> 144:ef7eb2e8f9f7 1143 frequency = LSE_VALUE;
<> 144:ef7eb2e8f9f7 1144 }
<> 144:ef7eb2e8f9f7 1145 break;
<> 144:ef7eb2e8f9f7 1146 }
<> 144:ef7eb2e8f9f7 1147 #endif /* RCC_CFGR3_UART5SW */
<> 144:ef7eb2e8f9f7 1148 case RCC_PERIPHCLK_I2C1:
<> 144:ef7eb2e8f9f7 1149 {
<> 144:ef7eb2e8f9f7 1150 /* Get the current I2C1 source */
<> 144:ef7eb2e8f9f7 1151 srcclk = __HAL_RCC_GET_I2C1_SOURCE();
<> 144:ef7eb2e8f9f7 1152
<> 144:ef7eb2e8f9f7 1153 /* Check if HSI is ready and if I2C1 clock selection is HSI */
<> 144:ef7eb2e8f9f7 1154 if ((srcclk == RCC_I2C1CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)))
<> 144:ef7eb2e8f9f7 1155 {
<> 144:ef7eb2e8f9f7 1156 frequency = HSI_VALUE;
<> 144:ef7eb2e8f9f7 1157 }
<> 144:ef7eb2e8f9f7 1158 /* Check if I2C1 clock selection is SYSCLK */
<> 144:ef7eb2e8f9f7 1159 else if (srcclk == RCC_I2C1CLKSOURCE_SYSCLK)
<> 144:ef7eb2e8f9f7 1160 {
<> 144:ef7eb2e8f9f7 1161 frequency = HAL_RCC_GetSysClockFreq();
<> 144:ef7eb2e8f9f7 1162 }
<> 144:ef7eb2e8f9f7 1163 break;
<> 144:ef7eb2e8f9f7 1164 }
<> 144:ef7eb2e8f9f7 1165 #if defined(RCC_CFGR3_I2C2SW)
<> 144:ef7eb2e8f9f7 1166 case RCC_PERIPHCLK_I2C2:
<> 144:ef7eb2e8f9f7 1167 {
<> 144:ef7eb2e8f9f7 1168 /* Get the current I2C2 source */
<> 144:ef7eb2e8f9f7 1169 srcclk = __HAL_RCC_GET_I2C2_SOURCE();
<> 144:ef7eb2e8f9f7 1170
<> 144:ef7eb2e8f9f7 1171 /* Check if HSI is ready and if I2C2 clock selection is HSI */
<> 144:ef7eb2e8f9f7 1172 if ((srcclk == RCC_I2C2CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)))
<> 144:ef7eb2e8f9f7 1173 {
<> 144:ef7eb2e8f9f7 1174 frequency = HSI_VALUE;
<> 144:ef7eb2e8f9f7 1175 }
<> 144:ef7eb2e8f9f7 1176 /* Check if I2C2 clock selection is SYSCLK */
<> 144:ef7eb2e8f9f7 1177 else if (srcclk == RCC_I2C2CLKSOURCE_SYSCLK)
<> 144:ef7eb2e8f9f7 1178 {
<> 144:ef7eb2e8f9f7 1179 frequency = HAL_RCC_GetSysClockFreq();
<> 144:ef7eb2e8f9f7 1180 }
<> 144:ef7eb2e8f9f7 1181 break;
<> 144:ef7eb2e8f9f7 1182 }
<> 144:ef7eb2e8f9f7 1183 #endif /* RCC_CFGR3_I2C2SW */
<> 144:ef7eb2e8f9f7 1184 #if defined(RCC_CFGR3_I2C3SW)
<> 144:ef7eb2e8f9f7 1185 case RCC_PERIPHCLK_I2C3:
<> 144:ef7eb2e8f9f7 1186 {
<> 144:ef7eb2e8f9f7 1187 /* Get the current I2C3 source */
<> 144:ef7eb2e8f9f7 1188 srcclk = __HAL_RCC_GET_I2C3_SOURCE();
<> 144:ef7eb2e8f9f7 1189
<> 144:ef7eb2e8f9f7 1190 /* Check if HSI is ready and if I2C3 clock selection is HSI */
<> 144:ef7eb2e8f9f7 1191 if ((srcclk == RCC_I2C3CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)))
<> 144:ef7eb2e8f9f7 1192 {
<> 144:ef7eb2e8f9f7 1193 frequency = HSI_VALUE;
<> 144:ef7eb2e8f9f7 1194 }
<> 144:ef7eb2e8f9f7 1195 /* Check if I2C3 clock selection is SYSCLK */
<> 144:ef7eb2e8f9f7 1196 else if (srcclk == RCC_I2C3CLKSOURCE_SYSCLK)
<> 144:ef7eb2e8f9f7 1197 {
<> 144:ef7eb2e8f9f7 1198 frequency = HAL_RCC_GetSysClockFreq();
<> 144:ef7eb2e8f9f7 1199 }
<> 144:ef7eb2e8f9f7 1200 break;
<> 144:ef7eb2e8f9f7 1201 }
<> 144:ef7eb2e8f9f7 1202 #endif /* RCC_CFGR3_I2C3SW */
<> 144:ef7eb2e8f9f7 1203 #if defined(RCC_CFGR_I2SSRC)
<> 144:ef7eb2e8f9f7 1204 case RCC_PERIPHCLK_I2S:
<> 144:ef7eb2e8f9f7 1205 {
<> 144:ef7eb2e8f9f7 1206 /* Get the current I2S source */
<> 144:ef7eb2e8f9f7 1207 srcclk = __HAL_RCC_GET_I2S_SOURCE();
<> 144:ef7eb2e8f9f7 1208
<> 144:ef7eb2e8f9f7 1209 /* Check if I2S clock selection is External clock mapped on the I2S_CKIN pin */
<> 144:ef7eb2e8f9f7 1210 if (srcclk == RCC_I2SCLKSOURCE_EXT)
<> 144:ef7eb2e8f9f7 1211 {
<> 144:ef7eb2e8f9f7 1212 /* External clock used. Frequency cannot be returned.*/
<> 144:ef7eb2e8f9f7 1213 frequency = 0xDEADDEADU;
<> 144:ef7eb2e8f9f7 1214 }
<> 144:ef7eb2e8f9f7 1215 /* Check if I2S clock selection is SYSCLK */
<> 144:ef7eb2e8f9f7 1216 else if (srcclk == RCC_I2SCLKSOURCE_SYSCLK)
<> 144:ef7eb2e8f9f7 1217 {
<> 144:ef7eb2e8f9f7 1218 frequency = HAL_RCC_GetSysClockFreq();
<> 144:ef7eb2e8f9f7 1219 }
<> 144:ef7eb2e8f9f7 1220 break;
<> 144:ef7eb2e8f9f7 1221 }
<> 144:ef7eb2e8f9f7 1222 #endif /* RCC_CFGR_I2SSRC */
<> 144:ef7eb2e8f9f7 1223 #if defined(RCC_CFGR_USBPRE)
<> 144:ef7eb2e8f9f7 1224 case RCC_PERIPHCLK_USB:
<> 144:ef7eb2e8f9f7 1225 {
<> 144:ef7eb2e8f9f7 1226 /* Check if PLL is ready */
<> 144:ef7eb2e8f9f7 1227 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY))
<> 144:ef7eb2e8f9f7 1228 {
<> 144:ef7eb2e8f9f7 1229 /* Get the current USB source */
<> 144:ef7eb2e8f9f7 1230 srcclk = __HAL_RCC_GET_USB_SOURCE();
<> 144:ef7eb2e8f9f7 1231
<> 144:ef7eb2e8f9f7 1232 /* Check if USB clock selection is not divided */
<> 144:ef7eb2e8f9f7 1233 if (srcclk == RCC_USBCLKSOURCE_PLL)
<> 144:ef7eb2e8f9f7 1234 {
<> 144:ef7eb2e8f9f7 1235 frequency = RCC_GetPLLCLKFreq();
<> 144:ef7eb2e8f9f7 1236 }
<> 144:ef7eb2e8f9f7 1237 /* Check if USB clock selection is divided by 1.5 */
<> 144:ef7eb2e8f9f7 1238 else /* RCC_USBCLKSOURCE_PLL_DIV1_5 */
<> 144:ef7eb2e8f9f7 1239 {
<> 157:ff67d9f36b67 1240 frequency = (RCC_GetPLLCLKFreq() * 3U) / 2U;
<> 144:ef7eb2e8f9f7 1241 }
<> 144:ef7eb2e8f9f7 1242 }
<> 144:ef7eb2e8f9f7 1243 break;
<> 144:ef7eb2e8f9f7 1244 }
<> 144:ef7eb2e8f9f7 1245 #endif /* RCC_CFGR_USBPRE */
<> 144:ef7eb2e8f9f7 1246 #if defined(RCC_CFGR2_ADC1PRES) || defined(RCC_CFGR_ADCPRE)
<> 144:ef7eb2e8f9f7 1247 case RCC_PERIPHCLK_ADC1:
<> 144:ef7eb2e8f9f7 1248 {
<> 144:ef7eb2e8f9f7 1249 /* Get the current ADC1 source */
<> 144:ef7eb2e8f9f7 1250 srcclk = __HAL_RCC_GET_ADC1_SOURCE();
<> 144:ef7eb2e8f9f7 1251 #if defined(RCC_CFGR2_ADC1PRES)
<> 144:ef7eb2e8f9f7 1252 /* Check if ADC1 clock selection is AHB */
<> 144:ef7eb2e8f9f7 1253 if (srcclk == RCC_ADC1PLLCLK_OFF)
<> 144:ef7eb2e8f9f7 1254 {
<> 144:ef7eb2e8f9f7 1255 frequency = SystemCoreClock;
<> 144:ef7eb2e8f9f7 1256 }
<> 144:ef7eb2e8f9f7 1257 /* PLL clock has been selected */
<> 144:ef7eb2e8f9f7 1258 else
<> 144:ef7eb2e8f9f7 1259 {
<> 144:ef7eb2e8f9f7 1260 /* Check if PLL is ready */
<> 144:ef7eb2e8f9f7 1261 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY))
<> 144:ef7eb2e8f9f7 1262 {
<> 157:ff67d9f36b67 1263 /* Frequency is the PLL frequency divided by ADC prescaler (1U/2U/4U/6U/8U/10U/12U/16U/32U/64U/128U/256U) */
<> 157:ff67d9f36b67 1264 frequency = RCC_GetPLLCLKFreq() / adc_pll_prediv_table[(srcclk >> POSITION_VAL(RCC_CFGR2_ADC1PRES)) & 0xFU];
<> 144:ef7eb2e8f9f7 1265 }
<> 144:ef7eb2e8f9f7 1266 }
<> 144:ef7eb2e8f9f7 1267 #else /* RCC_CFGR_ADCPRE */
<> 157:ff67d9f36b67 1268 /* ADC1 is set to PLCK2 frequency divided by 2U/4U/6U/8U */
<> 157:ff67d9f36b67 1269 frequency = HAL_RCC_GetPCLK2Freq() / (((srcclk >> POSITION_VAL(RCC_CFGR_ADCPRE)) + 1U) * 2U);
<> 144:ef7eb2e8f9f7 1270 #endif /* RCC_CFGR2_ADC1PRES */
<> 144:ef7eb2e8f9f7 1271 break;
<> 144:ef7eb2e8f9f7 1272 }
<> 144:ef7eb2e8f9f7 1273 #endif /* RCC_CFGR2_ADC1PRES || RCC_CFGR_ADCPRE */
<> 144:ef7eb2e8f9f7 1274 #if defined(RCC_CFGR2_ADCPRE12)
<> 144:ef7eb2e8f9f7 1275 case RCC_PERIPHCLK_ADC12:
<> 144:ef7eb2e8f9f7 1276 {
<> 144:ef7eb2e8f9f7 1277 /* Get the current ADC12 source */
<> 144:ef7eb2e8f9f7 1278 srcclk = __HAL_RCC_GET_ADC12_SOURCE();
<> 144:ef7eb2e8f9f7 1279 /* Check if ADC12 clock selection is AHB */
<> 144:ef7eb2e8f9f7 1280 if (srcclk == RCC_ADC12PLLCLK_OFF)
<> 144:ef7eb2e8f9f7 1281 {
<> 144:ef7eb2e8f9f7 1282 frequency = SystemCoreClock;
<> 144:ef7eb2e8f9f7 1283 }
<> 144:ef7eb2e8f9f7 1284 /* PLL clock has been selected */
<> 144:ef7eb2e8f9f7 1285 else
<> 144:ef7eb2e8f9f7 1286 {
<> 144:ef7eb2e8f9f7 1287 /* Check if PLL is ready */
<> 144:ef7eb2e8f9f7 1288 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY))
<> 144:ef7eb2e8f9f7 1289 {
<> 157:ff67d9f36b67 1290 /* Frequency is the PLL frequency divided by ADC prescaler (1U/2U/4U/6/8U/10U/12U/16U/32U/64U/128U/256U) */
<> 144:ef7eb2e8f9f7 1291 frequency = RCC_GetPLLCLKFreq() / adc_pll_prediv_table[(srcclk >> POSITION_VAL(RCC_CFGR2_ADCPRE12)) & 0xF];
<> 144:ef7eb2e8f9f7 1292 }
<> 144:ef7eb2e8f9f7 1293 }
<> 144:ef7eb2e8f9f7 1294 break;
<> 144:ef7eb2e8f9f7 1295 }
<> 144:ef7eb2e8f9f7 1296 #endif /* RCC_CFGR2_ADCPRE12 */
<> 144:ef7eb2e8f9f7 1297 #if defined(RCC_CFGR2_ADCPRE34)
<> 144:ef7eb2e8f9f7 1298 case RCC_PERIPHCLK_ADC34:
<> 144:ef7eb2e8f9f7 1299 {
<> 144:ef7eb2e8f9f7 1300 /* Get the current ADC34 source */
<> 144:ef7eb2e8f9f7 1301 srcclk = __HAL_RCC_GET_ADC34_SOURCE();
<> 144:ef7eb2e8f9f7 1302 /* Check if ADC34 clock selection is AHB */
<> 144:ef7eb2e8f9f7 1303 if (srcclk == RCC_ADC34PLLCLK_OFF)
<> 144:ef7eb2e8f9f7 1304 {
<> 144:ef7eb2e8f9f7 1305 frequency = SystemCoreClock;
<> 144:ef7eb2e8f9f7 1306 }
<> 144:ef7eb2e8f9f7 1307 /* PLL clock has been selected */
<> 144:ef7eb2e8f9f7 1308 else
<> 144:ef7eb2e8f9f7 1309 {
<> 144:ef7eb2e8f9f7 1310 /* Check if PLL is ready */
<> 144:ef7eb2e8f9f7 1311 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY))
<> 144:ef7eb2e8f9f7 1312 {
<> 157:ff67d9f36b67 1313 /* Frequency is the PLL frequency divided by ADC prescaler (1U/2U/4U/6U/8U/10U/12U/16U/32U/64U/128U/256U) */
<> 144:ef7eb2e8f9f7 1314 frequency = RCC_GetPLLCLKFreq() / adc_pll_prediv_table[(srcclk >> POSITION_VAL(RCC_CFGR2_ADCPRE34)) & 0xF];
<> 144:ef7eb2e8f9f7 1315 }
<> 144:ef7eb2e8f9f7 1316 }
<> 144:ef7eb2e8f9f7 1317 break;
<> 144:ef7eb2e8f9f7 1318 }
<> 144:ef7eb2e8f9f7 1319 #endif /* RCC_CFGR2_ADCPRE34 */
<> 144:ef7eb2e8f9f7 1320 #if defined(RCC_CFGR3_TIM1SW)
<> 144:ef7eb2e8f9f7 1321 case RCC_PERIPHCLK_TIM1:
<> 144:ef7eb2e8f9f7 1322 {
<> 144:ef7eb2e8f9f7 1323 /* Get the current TIM1 source */
<> 144:ef7eb2e8f9f7 1324 srcclk = __HAL_RCC_GET_TIM1_SOURCE();
<> 144:ef7eb2e8f9f7 1325
<> 144:ef7eb2e8f9f7 1326 /* Check if PLL is ready and if TIM1 clock selection is PLL */
<> 144:ef7eb2e8f9f7 1327 if ((srcclk == RCC_TIM1CLK_PLLCLK) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY)))
<> 144:ef7eb2e8f9f7 1328 {
<> 144:ef7eb2e8f9f7 1329 frequency = RCC_GetPLLCLKFreq();
<> 144:ef7eb2e8f9f7 1330 }
<> 144:ef7eb2e8f9f7 1331 /* Check if TIM1 clock selection is SYSCLK */
<> 144:ef7eb2e8f9f7 1332 else if (srcclk == RCC_TIM1CLK_HCLK)
<> 144:ef7eb2e8f9f7 1333 {
<> 144:ef7eb2e8f9f7 1334 frequency = SystemCoreClock;
<> 144:ef7eb2e8f9f7 1335 }
<> 144:ef7eb2e8f9f7 1336 break;
<> 144:ef7eb2e8f9f7 1337 }
<> 144:ef7eb2e8f9f7 1338 #endif /* RCC_CFGR3_TIM1SW */
<> 144:ef7eb2e8f9f7 1339 #if defined(RCC_CFGR3_TIM2SW)
<> 144:ef7eb2e8f9f7 1340 case RCC_PERIPHCLK_TIM2:
<> 144:ef7eb2e8f9f7 1341 {
<> 144:ef7eb2e8f9f7 1342 /* Get the current TIM2 source */
<> 144:ef7eb2e8f9f7 1343 srcclk = __HAL_RCC_GET_TIM2_SOURCE();
<> 144:ef7eb2e8f9f7 1344
<> 144:ef7eb2e8f9f7 1345 /* Check if PLL is ready and if TIM2 clock selection is PLL */
<> 144:ef7eb2e8f9f7 1346 if ((srcclk == RCC_TIM2CLK_PLLCLK) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY)))
<> 144:ef7eb2e8f9f7 1347 {
<> 144:ef7eb2e8f9f7 1348 frequency = RCC_GetPLLCLKFreq();
<> 144:ef7eb2e8f9f7 1349 }
<> 144:ef7eb2e8f9f7 1350 /* Check if TIM2 clock selection is SYSCLK */
<> 144:ef7eb2e8f9f7 1351 else if (srcclk == RCC_TIM2CLK_HCLK)
<> 144:ef7eb2e8f9f7 1352 {
<> 144:ef7eb2e8f9f7 1353 frequency = SystemCoreClock;
<> 144:ef7eb2e8f9f7 1354 }
<> 144:ef7eb2e8f9f7 1355 break;
<> 144:ef7eb2e8f9f7 1356 }
<> 144:ef7eb2e8f9f7 1357 #endif /* RCC_CFGR3_TIM2SW */
<> 144:ef7eb2e8f9f7 1358 #if defined(RCC_CFGR3_TIM8SW)
<> 144:ef7eb2e8f9f7 1359 case RCC_PERIPHCLK_TIM8:
<> 144:ef7eb2e8f9f7 1360 {
<> 144:ef7eb2e8f9f7 1361 /* Get the current TIM8 source */
<> 144:ef7eb2e8f9f7 1362 srcclk = __HAL_RCC_GET_TIM8_SOURCE();
<> 144:ef7eb2e8f9f7 1363
<> 144:ef7eb2e8f9f7 1364 /* Check if PLL is ready and if TIM8 clock selection is PLL */
<> 144:ef7eb2e8f9f7 1365 if ((srcclk == RCC_TIM8CLK_PLLCLK) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY)))
<> 144:ef7eb2e8f9f7 1366 {
<> 144:ef7eb2e8f9f7 1367 frequency = RCC_GetPLLCLKFreq();
<> 144:ef7eb2e8f9f7 1368 }
<> 144:ef7eb2e8f9f7 1369 /* Check if TIM8 clock selection is SYSCLK */
<> 144:ef7eb2e8f9f7 1370 else if (srcclk == RCC_TIM8CLK_HCLK)
<> 144:ef7eb2e8f9f7 1371 {
<> 144:ef7eb2e8f9f7 1372 frequency = SystemCoreClock;
<> 144:ef7eb2e8f9f7 1373 }
<> 144:ef7eb2e8f9f7 1374 break;
<> 144:ef7eb2e8f9f7 1375 }
<> 144:ef7eb2e8f9f7 1376 #endif /* RCC_CFGR3_TIM8SW */
<> 144:ef7eb2e8f9f7 1377 #if defined(RCC_CFGR3_TIM15SW)
<> 144:ef7eb2e8f9f7 1378 case RCC_PERIPHCLK_TIM15:
<> 144:ef7eb2e8f9f7 1379 {
<> 144:ef7eb2e8f9f7 1380 /* Get the current TIM15 source */
<> 144:ef7eb2e8f9f7 1381 srcclk = __HAL_RCC_GET_TIM15_SOURCE();
<> 144:ef7eb2e8f9f7 1382
<> 144:ef7eb2e8f9f7 1383 /* Check if PLL is ready and if TIM15 clock selection is PLL */
<> 144:ef7eb2e8f9f7 1384 if ((srcclk == RCC_TIM15CLK_PLLCLK) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY)))
<> 144:ef7eb2e8f9f7 1385 {
<> 144:ef7eb2e8f9f7 1386 frequency = RCC_GetPLLCLKFreq();
<> 144:ef7eb2e8f9f7 1387 }
<> 144:ef7eb2e8f9f7 1388 /* Check if TIM15 clock selection is SYSCLK */
<> 144:ef7eb2e8f9f7 1389 else if (srcclk == RCC_TIM15CLK_HCLK)
<> 144:ef7eb2e8f9f7 1390 {
<> 144:ef7eb2e8f9f7 1391 frequency = SystemCoreClock;
<> 144:ef7eb2e8f9f7 1392 }
<> 144:ef7eb2e8f9f7 1393 break;
<> 144:ef7eb2e8f9f7 1394 }
<> 144:ef7eb2e8f9f7 1395 #endif /* RCC_CFGR3_TIM15SW */
<> 144:ef7eb2e8f9f7 1396 #if defined(RCC_CFGR3_TIM16SW)
<> 144:ef7eb2e8f9f7 1397 case RCC_PERIPHCLK_TIM16:
<> 144:ef7eb2e8f9f7 1398 {
<> 144:ef7eb2e8f9f7 1399 /* Get the current TIM16 source */
<> 144:ef7eb2e8f9f7 1400 srcclk = __HAL_RCC_GET_TIM16_SOURCE();
<> 144:ef7eb2e8f9f7 1401
<> 144:ef7eb2e8f9f7 1402 /* Check if PLL is ready and if TIM16 clock selection is PLL */
<> 144:ef7eb2e8f9f7 1403 if ((srcclk == RCC_TIM16CLK_PLLCLK) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY)))
<> 144:ef7eb2e8f9f7 1404 {
<> 144:ef7eb2e8f9f7 1405 frequency = RCC_GetPLLCLKFreq();
<> 144:ef7eb2e8f9f7 1406 }
<> 144:ef7eb2e8f9f7 1407 /* Check if TIM16 clock selection is SYSCLK */
<> 144:ef7eb2e8f9f7 1408 else if (srcclk == RCC_TIM16CLK_HCLK)
<> 144:ef7eb2e8f9f7 1409 {
<> 144:ef7eb2e8f9f7 1410 frequency = SystemCoreClock;
<> 144:ef7eb2e8f9f7 1411 }
<> 144:ef7eb2e8f9f7 1412 break;
<> 144:ef7eb2e8f9f7 1413 }
<> 144:ef7eb2e8f9f7 1414 #endif /* RCC_CFGR3_TIM16SW */
<> 144:ef7eb2e8f9f7 1415 #if defined(RCC_CFGR3_TIM17SW)
<> 144:ef7eb2e8f9f7 1416 case RCC_PERIPHCLK_TIM17:
<> 144:ef7eb2e8f9f7 1417 {
<> 144:ef7eb2e8f9f7 1418 /* Get the current TIM17 source */
<> 144:ef7eb2e8f9f7 1419 srcclk = __HAL_RCC_GET_TIM17_SOURCE();
<> 144:ef7eb2e8f9f7 1420
<> 144:ef7eb2e8f9f7 1421 /* Check if PLL is ready and if TIM17 clock selection is PLL */
<> 144:ef7eb2e8f9f7 1422 if ((srcclk == RCC_TIM17CLK_PLLCLK) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY)))
<> 144:ef7eb2e8f9f7 1423 {
<> 144:ef7eb2e8f9f7 1424 frequency = RCC_GetPLLCLKFreq();
<> 144:ef7eb2e8f9f7 1425 }
<> 144:ef7eb2e8f9f7 1426 /* Check if TIM17 clock selection is SYSCLK */
<> 144:ef7eb2e8f9f7 1427 else if (srcclk == RCC_TIM17CLK_HCLK)
<> 144:ef7eb2e8f9f7 1428 {
<> 144:ef7eb2e8f9f7 1429 frequency = SystemCoreClock;
<> 144:ef7eb2e8f9f7 1430 }
<> 144:ef7eb2e8f9f7 1431 break;
<> 144:ef7eb2e8f9f7 1432 }
<> 144:ef7eb2e8f9f7 1433 #endif /* RCC_CFGR3_TIM17SW */
<> 144:ef7eb2e8f9f7 1434 #if defined(RCC_CFGR3_TIM20SW)
<> 144:ef7eb2e8f9f7 1435 case RCC_PERIPHCLK_TIM20:
<> 144:ef7eb2e8f9f7 1436 {
<> 144:ef7eb2e8f9f7 1437 /* Get the current TIM20 source */
<> 144:ef7eb2e8f9f7 1438 srcclk = __HAL_RCC_GET_TIM20_SOURCE();
<> 144:ef7eb2e8f9f7 1439
<> 144:ef7eb2e8f9f7 1440 /* Check if PLL is ready and if TIM20 clock selection is PLL */
<> 144:ef7eb2e8f9f7 1441 if ((srcclk == RCC_TIM20CLK_PLLCLK) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY)))
<> 144:ef7eb2e8f9f7 1442 {
<> 144:ef7eb2e8f9f7 1443 frequency = RCC_GetPLLCLKFreq();
<> 144:ef7eb2e8f9f7 1444 }
<> 144:ef7eb2e8f9f7 1445 /* Check if TIM20 clock selection is SYSCLK */
<> 144:ef7eb2e8f9f7 1446 else if (srcclk == RCC_TIM20CLK_HCLK)
<> 144:ef7eb2e8f9f7 1447 {
<> 144:ef7eb2e8f9f7 1448 frequency = SystemCoreClock;
<> 144:ef7eb2e8f9f7 1449 }
<> 144:ef7eb2e8f9f7 1450 break;
<> 144:ef7eb2e8f9f7 1451 }
<> 144:ef7eb2e8f9f7 1452 #endif /* RCC_CFGR3_TIM20SW */
<> 144:ef7eb2e8f9f7 1453 #if defined(RCC_CFGR3_TIM34SW)
<> 144:ef7eb2e8f9f7 1454 case RCC_PERIPHCLK_TIM34:
<> 144:ef7eb2e8f9f7 1455 {
<> 144:ef7eb2e8f9f7 1456 /* Get the current TIM34 source */
<> 144:ef7eb2e8f9f7 1457 srcclk = __HAL_RCC_GET_TIM34_SOURCE();
<> 144:ef7eb2e8f9f7 1458
<> 144:ef7eb2e8f9f7 1459 /* Check if PLL is ready and if TIM34 clock selection is PLL */
<> 144:ef7eb2e8f9f7 1460 if ((srcclk == RCC_TIM34CLK_PLLCLK) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY)))
<> 144:ef7eb2e8f9f7 1461 {
<> 144:ef7eb2e8f9f7 1462 frequency = RCC_GetPLLCLKFreq();
<> 144:ef7eb2e8f9f7 1463 }
<> 144:ef7eb2e8f9f7 1464 /* Check if TIM34 clock selection is SYSCLK */
<> 144:ef7eb2e8f9f7 1465 else if (srcclk == RCC_TIM34CLK_HCLK)
<> 144:ef7eb2e8f9f7 1466 {
<> 144:ef7eb2e8f9f7 1467 frequency = SystemCoreClock;
<> 144:ef7eb2e8f9f7 1468 }
<> 144:ef7eb2e8f9f7 1469 break;
<> 144:ef7eb2e8f9f7 1470 }
<> 144:ef7eb2e8f9f7 1471 #endif /* RCC_CFGR3_TIM34SW */
<> 144:ef7eb2e8f9f7 1472 #if defined(RCC_CFGR3_HRTIM1SW)
<> 144:ef7eb2e8f9f7 1473 case RCC_PERIPHCLK_HRTIM1:
<> 144:ef7eb2e8f9f7 1474 {
<> 144:ef7eb2e8f9f7 1475 /* Get the current HRTIM1 source */
<> 144:ef7eb2e8f9f7 1476 srcclk = __HAL_RCC_GET_HRTIM1_SOURCE();
<> 144:ef7eb2e8f9f7 1477
<> 144:ef7eb2e8f9f7 1478 /* Check if PLL is ready and if HRTIM1 clock selection is PLL */
<> 144:ef7eb2e8f9f7 1479 if ((srcclk == RCC_HRTIM1CLK_PLLCLK) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY)))
<> 144:ef7eb2e8f9f7 1480 {
<> 144:ef7eb2e8f9f7 1481 frequency = RCC_GetPLLCLKFreq();
<> 144:ef7eb2e8f9f7 1482 }
<> 144:ef7eb2e8f9f7 1483 /* Check if HRTIM1 clock selection is SYSCLK */
<> 144:ef7eb2e8f9f7 1484 else if (srcclk == RCC_HRTIM1CLK_HCLK)
<> 144:ef7eb2e8f9f7 1485 {
<> 144:ef7eb2e8f9f7 1486 frequency = SystemCoreClock;
<> 144:ef7eb2e8f9f7 1487 }
Anna Bridge 186:707f6e361f3e 1488 break;
<> 144:ef7eb2e8f9f7 1489 }
<> 144:ef7eb2e8f9f7 1490 #endif /* RCC_CFGR3_HRTIM1SW */
<> 157:ff67d9f36b67 1491 #if defined(RCC_CFGR_SDPRE)
<> 144:ef7eb2e8f9f7 1492 case RCC_PERIPHCLK_SDADC:
<> 144:ef7eb2e8f9f7 1493 {
<> 144:ef7eb2e8f9f7 1494 /* Get the current SDADC source */
<> 144:ef7eb2e8f9f7 1495 srcclk = __HAL_RCC_GET_SDADC_SOURCE();
<> 157:ff67d9f36b67 1496 /* Frequency is the system frequency divided by SDADC prescaler (2U/4U/6U/8U/10U/12U/14U/16U/20U/24U/28U/32U/36U/40U/44U/48U) */
<> 157:ff67d9f36b67 1497 frequency = SystemCoreClock / sdadc_prescaler_table[(srcclk >> POSITION_VAL(RCC_CFGR_SDPRE)) & 0xF];
<> 144:ef7eb2e8f9f7 1498 break;
<> 144:ef7eb2e8f9f7 1499 }
<> 157:ff67d9f36b67 1500 #endif /* RCC_CFGR_SDPRE */
<> 144:ef7eb2e8f9f7 1501 #if defined(RCC_CFGR3_CECSW)
<> 144:ef7eb2e8f9f7 1502 case RCC_PERIPHCLK_CEC:
<> 144:ef7eb2e8f9f7 1503 {
<> 144:ef7eb2e8f9f7 1504 /* Get the current CEC source */
<> 144:ef7eb2e8f9f7 1505 srcclk = __HAL_RCC_GET_CEC_SOURCE();
<> 144:ef7eb2e8f9f7 1506
<> 144:ef7eb2e8f9f7 1507 /* Check if HSI is ready and if CEC clock selection is HSI */
<> 144:ef7eb2e8f9f7 1508 if ((srcclk == RCC_CECCLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)))
<> 144:ef7eb2e8f9f7 1509 {
<> 144:ef7eb2e8f9f7 1510 frequency = HSI_VALUE;
<> 144:ef7eb2e8f9f7 1511 }
<> 144:ef7eb2e8f9f7 1512 /* Check if LSE is ready and if CEC clock selection is LSE */
<> 144:ef7eb2e8f9f7 1513 else if ((srcclk == RCC_CECCLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)))
<> 144:ef7eb2e8f9f7 1514 {
<> 144:ef7eb2e8f9f7 1515 frequency = LSE_VALUE;
<> 144:ef7eb2e8f9f7 1516 }
<> 144:ef7eb2e8f9f7 1517 break;
<> 144:ef7eb2e8f9f7 1518 }
<> 144:ef7eb2e8f9f7 1519 #endif /* RCC_CFGR3_CECSW */
<> 144:ef7eb2e8f9f7 1520 default:
<> 144:ef7eb2e8f9f7 1521 {
<> 144:ef7eb2e8f9f7 1522 break;
<> 144:ef7eb2e8f9f7 1523 }
<> 144:ef7eb2e8f9f7 1524 }
<> 144:ef7eb2e8f9f7 1525 return(frequency);
<> 144:ef7eb2e8f9f7 1526 }
<> 144:ef7eb2e8f9f7 1527
<> 144:ef7eb2e8f9f7 1528 /**
<> 144:ef7eb2e8f9f7 1529 * @}
<> 144:ef7eb2e8f9f7 1530 */
<> 144:ef7eb2e8f9f7 1531
<> 144:ef7eb2e8f9f7 1532 /**
<> 144:ef7eb2e8f9f7 1533 * @}
<> 144:ef7eb2e8f9f7 1534 */
<> 144:ef7eb2e8f9f7 1535
<> 144:ef7eb2e8f9f7 1536
<> 144:ef7eb2e8f9f7 1537 #if defined(RCC_CFGR2_ADC1PRES) || defined(RCC_CFGR2_ADCPRE12) || defined(RCC_CFGR2_ADCPRE34) || defined(RCC_CFGR_USBPRE) \
<> 144:ef7eb2e8f9f7 1538 || defined(RCC_CFGR3_TIM1SW) || defined(RCC_CFGR3_TIM2SW) || defined(RCC_CFGR3_TIM8SW) || defined(RCC_CFGR3_TIM15SW) \
<> 144:ef7eb2e8f9f7 1539 || defined(RCC_CFGR3_TIM16SW) || defined(RCC_CFGR3_TIM17SW) || defined(RCC_CFGR3_TIM20SW) || defined(RCC_CFGR3_TIM34SW) \
<> 144:ef7eb2e8f9f7 1540 || defined(RCC_CFGR3_HRTIM1SW)
<> 144:ef7eb2e8f9f7 1541
<> 144:ef7eb2e8f9f7 1542 /** @addtogroup RCCEx_Private_Functions
<> 144:ef7eb2e8f9f7 1543 * @{
<> 144:ef7eb2e8f9f7 1544 */
<> 144:ef7eb2e8f9f7 1545 static uint32_t RCC_GetPLLCLKFreq(void)
<> 144:ef7eb2e8f9f7 1546 {
<> 157:ff67d9f36b67 1547 uint32_t pllmul = 0U, pllsource = 0U, prediv = 0U, pllclk = 0U;
<> 144:ef7eb2e8f9f7 1548
<> 144:ef7eb2e8f9f7 1549 pllmul = RCC->CFGR & RCC_CFGR_PLLMUL;
<> 157:ff67d9f36b67 1550 pllmul = ( pllmul >> 18U) + 2U;
<> 144:ef7eb2e8f9f7 1551 pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
<> 144:ef7eb2e8f9f7 1552 #if defined(RCC_CFGR_PLLSRC_HSI_DIV2)
<> 144:ef7eb2e8f9f7 1553 if (pllsource != RCC_PLLSOURCE_HSI)
<> 144:ef7eb2e8f9f7 1554 {
<> 157:ff67d9f36b67 1555 prediv = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1U;
<> 144:ef7eb2e8f9f7 1556 /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV * PLLMUL */
<> 144:ef7eb2e8f9f7 1557 pllclk = (HSE_VALUE/prediv) * pllmul;
<> 144:ef7eb2e8f9f7 1558 }
<> 144:ef7eb2e8f9f7 1559 else
<> 144:ef7eb2e8f9f7 1560 {
<> 157:ff67d9f36b67 1561 /* HSI used as PLL clock source : PLLCLK = HSI/2U * PLLMUL */
<> 157:ff67d9f36b67 1562 pllclk = (HSI_VALUE >> 1U) * pllmul;
<> 144:ef7eb2e8f9f7 1563 }
<> 144:ef7eb2e8f9f7 1564 #else
<> 157:ff67d9f36b67 1565 prediv = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1U;
<> 144:ef7eb2e8f9f7 1566 if (pllsource == RCC_CFGR_PLLSRC_HSE_PREDIV)
<> 144:ef7eb2e8f9f7 1567 {
<> 144:ef7eb2e8f9f7 1568 /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV * PLLMUL */
<> 144:ef7eb2e8f9f7 1569 pllclk = (HSE_VALUE/prediv) * pllmul;
<> 144:ef7eb2e8f9f7 1570 }
<> 144:ef7eb2e8f9f7 1571 else
<> 144:ef7eb2e8f9f7 1572 {
<> 144:ef7eb2e8f9f7 1573 /* HSI used as PLL clock source : PLLCLK = HSI/PREDIV * PLLMUL */
<> 144:ef7eb2e8f9f7 1574 pllclk = (HSI_VALUE/prediv) * pllmul;
<> 144:ef7eb2e8f9f7 1575 }
<> 144:ef7eb2e8f9f7 1576 #endif /* RCC_CFGR_PLLSRC_HSI_DIV2 */
<> 144:ef7eb2e8f9f7 1577
<> 144:ef7eb2e8f9f7 1578 return pllclk;
<> 144:ef7eb2e8f9f7 1579 }
<> 144:ef7eb2e8f9f7 1580 /**
<> 144:ef7eb2e8f9f7 1581 * @}
<> 144:ef7eb2e8f9f7 1582 */
<> 144:ef7eb2e8f9f7 1583
<> 144:ef7eb2e8f9f7 1584 #endif /* RCC_CFGR2_ADC1PRES || RCC_CFGR2_ADCPRExx || RCC_CFGR3_TIMxSW || RCC_CFGR3_HRTIM1SW || RCC_CFGR_USBPRE */
<> 144:ef7eb2e8f9f7 1585
<> 144:ef7eb2e8f9f7 1586 /**
<> 144:ef7eb2e8f9f7 1587 * @}
<> 144:ef7eb2e8f9f7 1588 */
<> 144:ef7eb2e8f9f7 1589
<> 144:ef7eb2e8f9f7 1590 #endif /* HAL_RCC_MODULE_ENABLED */
<> 144:ef7eb2e8f9f7 1591
<> 144:ef7eb2e8f9f7 1592 /**
<> 144:ef7eb2e8f9f7 1593 * @}
<> 144:ef7eb2e8f9f7 1594 */
<> 144:ef7eb2e8f9f7 1595
<> 144:ef7eb2e8f9f7 1596 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/