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targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F756xG/TARGET_NUCLEO_F756ZG/system_stm32f7xx.c@159:612c381a210f, 2017-02-28 (annotated)

Committer:
<>
Date:
Tue Feb 28 17:13:35 2017 +0000
Revision:
159:612c381a210f
Parent:
158:b23ee177fd68
Child:
161:2cc1468da177
This updates the lib to the mbed lib v137

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file system_stm32f7xx.c
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 157:ff67d9f36b67 5 * @version V1.1.2
<> 157:ff67d9f36b67 6 * @date 23-September-2016
<> 144:ef7eb2e8f9f7 7 * @brief CMSIS Cortex-M7 Device Peripheral Access Layer System Source File.
<> 144:ef7eb2e8f9f7 8 *
<> 144:ef7eb2e8f9f7 9 * This file provides two functions and one global variable to be called from
<> 144:ef7eb2e8f9f7 10 * user application:
<> 144:ef7eb2e8f9f7 11 * - SystemInit(): This function is called at startup just after reset and
<> 144:ef7eb2e8f9f7 12 * before branch to main program. This call is made inside
<> 144:ef7eb2e8f9f7 13 * the "startup_stm32f7xx.s" file.
<> 144:ef7eb2e8f9f7 14 *
<> 144:ef7eb2e8f9f7 15 * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
<> 144:ef7eb2e8f9f7 16 * by the user application to setup the SysTick
<> 144:ef7eb2e8f9f7 17 * timer or configure other parameters.
<> 144:ef7eb2e8f9f7 18 *
<> 144:ef7eb2e8f9f7 19 * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
<> 144:ef7eb2e8f9f7 20 * be called whenever the core clock is changed
<> 144:ef7eb2e8f9f7 21 * during program execution.
<> 144:ef7eb2e8f9f7 22 *
<> 144:ef7eb2e8f9f7 23 * This file configures the system clock as follows:
<> 144:ef7eb2e8f9f7 24 *-----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 25 * System clock source | [1] PLL_HSE_XTAL | [2] PLL_HSI if [1] fails
<> 144:ef7eb2e8f9f7 26 * | (external 25MHz xtal) | (internal 16MHz clock)
<> 144:ef7eb2e8f9f7 27 *-----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 28 * SYSCLK(MHz) | 216 | 216
<> 144:ef7eb2e8f9f7 29 *-----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 30 * AHBCLK (MHz) | 216 | 216
<> 144:ef7eb2e8f9f7 31 *-----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 32 * APB1CLK (MHz) | 54 | 54
<> 144:ef7eb2e8f9f7 33 *-----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 34 * APB2CLK (MHz) | 108 | 108
<> 144:ef7eb2e8f9f7 35 *-----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 36 * USB capable | YES | NO
<> 144:ef7eb2e8f9f7 37 * with 48 MHz precise clock | |
<> 144:ef7eb2e8f9f7 38 *-----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 39 ******************************************************************************
<> 144:ef7eb2e8f9f7 40 * @attention
<> 144:ef7eb2e8f9f7 41 *
<> 144:ef7eb2e8f9f7 42 * <h2><center>&copy; COPYRIGHT 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 43 *
<> 144:ef7eb2e8f9f7 44 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 45 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 46 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 47 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 48 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 49 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 50 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 51 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 52 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 53 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 54 *
<> 144:ef7eb2e8f9f7 55 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 56 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 57 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 58 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 59 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 60 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 61 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 62 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 63 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 64 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 65 *
<> 144:ef7eb2e8f9f7 66 ******************************************************************************
<> 144:ef7eb2e8f9f7 67 */
<> 144:ef7eb2e8f9f7 68
<> 144:ef7eb2e8f9f7 69 /** @addtogroup CMSIS
<> 144:ef7eb2e8f9f7 70 * @{
<> 144:ef7eb2e8f9f7 71 */
<> 144:ef7eb2e8f9f7 72
<> 144:ef7eb2e8f9f7 73 /** @addtogroup stm32f7xx_system
<> 144:ef7eb2e8f9f7 74 * @{
<> 144:ef7eb2e8f9f7 75 */
<> 144:ef7eb2e8f9f7 76
<> 144:ef7eb2e8f9f7 77 /** @addtogroup STM32F7xx_System_Private_Includes
<> 144:ef7eb2e8f9f7 78 * @{
<> 144:ef7eb2e8f9f7 79 */
<> 144:ef7eb2e8f9f7 80
<> 144:ef7eb2e8f9f7 81 #include "stm32f7xx.h"
<> 144:ef7eb2e8f9f7 82 #include "hal_tick.h"
<> 144:ef7eb2e8f9f7 83
<> 144:ef7eb2e8f9f7 84 HAL_StatusTypeDef HAL_Init(void);
<> 144:ef7eb2e8f9f7 85
<> 144:ef7eb2e8f9f7 86 #if !defined (HSE_VALUE)
<> 144:ef7eb2e8f9f7 87 #define HSE_VALUE ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz */
<> 144:ef7eb2e8f9f7 88 #endif /* HSE_VALUE */
<> 144:ef7eb2e8f9f7 89
<> 144:ef7eb2e8f9f7 90 #if !defined (HSI_VALUE)
<> 144:ef7eb2e8f9f7 91 #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
<> 144:ef7eb2e8f9f7 92 #endif /* HSI_VALUE */
<> 144:ef7eb2e8f9f7 93
<> 144:ef7eb2e8f9f7 94 /**
<> 144:ef7eb2e8f9f7 95 * @}
<> 144:ef7eb2e8f9f7 96 */
<> 144:ef7eb2e8f9f7 97
<> 144:ef7eb2e8f9f7 98 /** @addtogroup STM32F7xx_System_Private_TypesDefinitions
<> 144:ef7eb2e8f9f7 99 * @{
<> 144:ef7eb2e8f9f7 100 */
<> 144:ef7eb2e8f9f7 101
<> 144:ef7eb2e8f9f7 102 /**
<> 144:ef7eb2e8f9f7 103 * @}
<> 144:ef7eb2e8f9f7 104 */
<> 144:ef7eb2e8f9f7 105
<> 144:ef7eb2e8f9f7 106 /** @addtogroup STM32F7xx_System_Private_Defines
<> 144:ef7eb2e8f9f7 107 * @{
<> 144:ef7eb2e8f9f7 108 */
<> 144:ef7eb2e8f9f7 109
<> 144:ef7eb2e8f9f7 110 /************************* Miscellaneous Configuration ************************/
<> 144:ef7eb2e8f9f7 111 /*!< Uncomment the following line if you need to use external SRAM or SDRAM mounted
<> 144:ef7eb2e8f9f7 112 on STMicroelectronics EVAL/Discovery boards as data memory */
<> 144:ef7eb2e8f9f7 113 /*!< In case of EVAL/Discovery’s LCD use in application code, the DATA_IN_ExtSDRAM define
<> 144:ef7eb2e8f9f7 114 need to be added in the project preprocessor to avoid SDRAM multiple configuration
<> 144:ef7eb2e8f9f7 115 (the LCD uses SDRAM as frame buffer, and its configuration is done by the BSP_SDRAM_Init()) */
<> 144:ef7eb2e8f9f7 116 /* #define DATA_IN_ExtSRAM */
<> 144:ef7eb2e8f9f7 117 /* #define DATA_IN_ExtSDRAM */
<> 144:ef7eb2e8f9f7 118
<> 144:ef7eb2e8f9f7 119 /*!< Uncomment the following line if you need to relocate your vector Table in
<> 144:ef7eb2e8f9f7 120 Internal SRAM. */
<> 144:ef7eb2e8f9f7 121 /* #define VECT_TAB_SRAM */
<> 144:ef7eb2e8f9f7 122 #define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
<> 144:ef7eb2e8f9f7 123 This value must be a multiple of 0x200. */
<> 144:ef7eb2e8f9f7 124 /******************************************************************************/
<> 144:ef7eb2e8f9f7 125
<> 144:ef7eb2e8f9f7 126 /**
<> 144:ef7eb2e8f9f7 127 * @}
<> 144:ef7eb2e8f9f7 128 */
<> 144:ef7eb2e8f9f7 129
<> 144:ef7eb2e8f9f7 130 /** @addtogroup STM32F7xx_System_Private_Macros
<> 144:ef7eb2e8f9f7 131 * @{
<> 144:ef7eb2e8f9f7 132 */
<> 144:ef7eb2e8f9f7 133
<> 144:ef7eb2e8f9f7 134 /* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */
<> 144:ef7eb2e8f9f7 135 #define USE_PLL_HSE_EXTC (1) /* Use external clock */
<> 144:ef7eb2e8f9f7 136 #define USE_PLL_HSE_XTAL (1) /* Use external xtal */
<> 144:ef7eb2e8f9f7 137
<> 144:ef7eb2e8f9f7 138 /**
<> 144:ef7eb2e8f9f7 139 * @}
<> 144:ef7eb2e8f9f7 140 */
<> 144:ef7eb2e8f9f7 141
<> 144:ef7eb2e8f9f7 142 /** @addtogroup STM32F7xx_System_Private_Variables
<> 144:ef7eb2e8f9f7 143 * @{
<> 144:ef7eb2e8f9f7 144 */
<> 144:ef7eb2e8f9f7 145
<> 144:ef7eb2e8f9f7 146 /* This variable is updated in three ways:
<> 144:ef7eb2e8f9f7 147 1) by calling CMSIS function SystemCoreClockUpdate()
<> 144:ef7eb2e8f9f7 148 2) by calling HAL API function HAL_RCC_GetHCLKFreq()
<> 144:ef7eb2e8f9f7 149 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
<> 144:ef7eb2e8f9f7 150 Note: If you use this function to configure the system clock; then there
<> 144:ef7eb2e8f9f7 151 is no need to call the 2 first functions listed above, since SystemCoreClock
<> 144:ef7eb2e8f9f7 152 variable is updated automatically.
<> 144:ef7eb2e8f9f7 153 */
<> 144:ef7eb2e8f9f7 154 uint32_t SystemCoreClock = HSI_VALUE;
<> 144:ef7eb2e8f9f7 155 const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
<> 144:ef7eb2e8f9f7 156 const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};
<> 144:ef7eb2e8f9f7 157
<> 144:ef7eb2e8f9f7 158 /**
<> 144:ef7eb2e8f9f7 159 * @}
<> 144:ef7eb2e8f9f7 160 */
<> 144:ef7eb2e8f9f7 161
<> 144:ef7eb2e8f9f7 162 /** @addtogroup STM32F7xx_System_Private_FunctionPrototypes
<> 144:ef7eb2e8f9f7 163 * @{
<> 144:ef7eb2e8f9f7 164 */
<> 144:ef7eb2e8f9f7 165 #if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
<> 144:ef7eb2e8f9f7 166 static void SystemInit_ExtMemCtl(void);
<> 144:ef7eb2e8f9f7 167 #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
<> 144:ef7eb2e8f9f7 168
<> 144:ef7eb2e8f9f7 169 #if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
<> 144:ef7eb2e8f9f7 170 uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
<> 144:ef7eb2e8f9f7 171 #endif
<> 144:ef7eb2e8f9f7 172
<> 144:ef7eb2e8f9f7 173 uint8_t SetSysClock_PLL_HSI(void);
<> 144:ef7eb2e8f9f7 174
<> 144:ef7eb2e8f9f7 175 /**
<> 144:ef7eb2e8f9f7 176 * @}
<> 144:ef7eb2e8f9f7 177 */
<> 144:ef7eb2e8f9f7 178
<> 144:ef7eb2e8f9f7 179 /** @addtogroup STM32F7xx_System_Private_Functions
<> 144:ef7eb2e8f9f7 180 * @{
<> 144:ef7eb2e8f9f7 181 */
<> 144:ef7eb2e8f9f7 182
<> 144:ef7eb2e8f9f7 183 /**
<> 144:ef7eb2e8f9f7 184 * @brief Setup the microcontroller system
<> 144:ef7eb2e8f9f7 185 * Initialize the Embedded Flash Interface, the PLL and update the
<> 144:ef7eb2e8f9f7 186 * SystemFrequency variable.
<> 144:ef7eb2e8f9f7 187 * @param None
<> 144:ef7eb2e8f9f7 188 * @retval None
<> 144:ef7eb2e8f9f7 189 */
<> 144:ef7eb2e8f9f7 190 void SystemInit(void)
<> 144:ef7eb2e8f9f7 191 {
<> 144:ef7eb2e8f9f7 192 /* FPU settings ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 193 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
<> 144:ef7eb2e8f9f7 194 SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
<> 144:ef7eb2e8f9f7 195 #endif
<> 144:ef7eb2e8f9f7 196 /* Reset the RCC clock configuration to the default reset state ------------*/
<> 144:ef7eb2e8f9f7 197 /* Set HSION bit */
<> 144:ef7eb2e8f9f7 198 RCC->CR |= (uint32_t)0x00000001;
<> 144:ef7eb2e8f9f7 199
<> 144:ef7eb2e8f9f7 200 /* Reset CFGR register */
<> 144:ef7eb2e8f9f7 201 RCC->CFGR = 0x00000000;
<> 144:ef7eb2e8f9f7 202
<> 144:ef7eb2e8f9f7 203 /* Reset HSEON, CSSON and PLLON bits */
<> 144:ef7eb2e8f9f7 204 RCC->CR &= (uint32_t)0xFEF6FFFF;
<> 144:ef7eb2e8f9f7 205
<> 144:ef7eb2e8f9f7 206 /* Reset PLLCFGR register */
<> 144:ef7eb2e8f9f7 207 RCC->PLLCFGR = 0x24003010;
<> 144:ef7eb2e8f9f7 208
<> 144:ef7eb2e8f9f7 209 /* Reset HSEBYP bit */
<> 144:ef7eb2e8f9f7 210 RCC->CR &= (uint32_t)0xFFFBFFFF;
<> 144:ef7eb2e8f9f7 211
<> 144:ef7eb2e8f9f7 212 /* Disable all interrupts */
<> 144:ef7eb2e8f9f7 213 RCC->CIR = 0x00000000;
<> 144:ef7eb2e8f9f7 214
<> 144:ef7eb2e8f9f7 215 #if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
<> 144:ef7eb2e8f9f7 216 SystemInit_ExtMemCtl();
<> 144:ef7eb2e8f9f7 217 #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
<> 144:ef7eb2e8f9f7 218
<> 144:ef7eb2e8f9f7 219 /* Configure the Vector Table location add offset address ------------------*/
<> 144:ef7eb2e8f9f7 220 #ifdef VECT_TAB_SRAM
<> 144:ef7eb2e8f9f7 221 SCB->VTOR = RAMDTCM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
<> 144:ef7eb2e8f9f7 222 #else
<> 144:ef7eb2e8f9f7 223 SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
<> 144:ef7eb2e8f9f7 224 #endif
<> 144:ef7eb2e8f9f7 225
<> 144:ef7eb2e8f9f7 226 /* Configure the Cube driver */
<> 144:ef7eb2e8f9f7 227 SystemCoreClock = HSI_VALUE; // At this stage the HSI is used as system clock
<> 144:ef7eb2e8f9f7 228 HAL_Init();
<> 144:ef7eb2e8f9f7 229
<> 144:ef7eb2e8f9f7 230 // Enable CPU L1-Cache
<> 144:ef7eb2e8f9f7 231 SCB_EnableICache();
<> 144:ef7eb2e8f9f7 232 SCB_EnableDCache();
<> 144:ef7eb2e8f9f7 233
<> 144:ef7eb2e8f9f7 234 /* Configure the System clock source, PLL Multiplier and Divider factors,
<> 144:ef7eb2e8f9f7 235 AHB/APBx prescalers and Flash settings */
<> 144:ef7eb2e8f9f7 236 SetSysClock();
<> 144:ef7eb2e8f9f7 237
<> 144:ef7eb2e8f9f7 238 /* Reset the timer to avoid issues after the RAM initialization */
<> 144:ef7eb2e8f9f7 239 TIM_MST_RESET_ON;
<> 144:ef7eb2e8f9f7 240 TIM_MST_RESET_OFF;
<> 144:ef7eb2e8f9f7 241 }
<> 144:ef7eb2e8f9f7 242
<> 144:ef7eb2e8f9f7 243 /**
<> 144:ef7eb2e8f9f7 244 * @brief Update SystemCoreClock variable according to Clock Register Values.
<> 144:ef7eb2e8f9f7 245 * The SystemCoreClock variable contains the core clock (HCLK), it can
<> 144:ef7eb2e8f9f7 246 * be used by the user application to setup the SysTick timer or configure
<> 144:ef7eb2e8f9f7 247 * other parameters.
<> 144:ef7eb2e8f9f7 248 *
<> 144:ef7eb2e8f9f7 249 * @note Each time the core clock (HCLK) changes, this function must be called
<> 144:ef7eb2e8f9f7 250 * to update SystemCoreClock variable value. Otherwise, any configuration
<> 144:ef7eb2e8f9f7 251 * based on this variable will be incorrect.
<> 144:ef7eb2e8f9f7 252 *
<> 144:ef7eb2e8f9f7 253 * @note - The system frequency computed by this function is not the real
<> 144:ef7eb2e8f9f7 254 * frequency in the chip. It is calculated based on the predefined
<> 144:ef7eb2e8f9f7 255 * constant and the selected clock source:
<> 144:ef7eb2e8f9f7 256 *
<> 144:ef7eb2e8f9f7 257 * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
<> 144:ef7eb2e8f9f7 258 *
<> 144:ef7eb2e8f9f7 259 * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
<> 144:ef7eb2e8f9f7 260 *
<> 144:ef7eb2e8f9f7 261 * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
<> 144:ef7eb2e8f9f7 262 * or HSI_VALUE(*) multiplied/divided by the PLL factors.
<> 144:ef7eb2e8f9f7 263 *
<> 144:ef7eb2e8f9f7 264 * (*) HSI_VALUE is a constant defined in stm32f7xx.h file (default value
<> 144:ef7eb2e8f9f7 265 * 16 MHz) but the real value may vary depending on the variations
<> 144:ef7eb2e8f9f7 266 * in voltage and temperature.
<> 144:ef7eb2e8f9f7 267 *
<> 144:ef7eb2e8f9f7 268 * (**) HSE_VALUE is a constant defined in stm32f7xx.h file (default value
<> 144:ef7eb2e8f9f7 269 * 25 MHz), user has to ensure that HSE_VALUE is same as the real
<> 144:ef7eb2e8f9f7 270 * frequency of the crystal used. Otherwise, this function may
<> 144:ef7eb2e8f9f7 271 * have wrong result.
<> 144:ef7eb2e8f9f7 272 *
<> 144:ef7eb2e8f9f7 273 * - The result of this function could be not correct when using fractional
<> 144:ef7eb2e8f9f7 274 * value for HSE crystal.
<> 144:ef7eb2e8f9f7 275 *
<> 144:ef7eb2e8f9f7 276 * @param None
<> 144:ef7eb2e8f9f7 277 * @retval None
<> 144:ef7eb2e8f9f7 278 */
<> 144:ef7eb2e8f9f7 279 void SystemCoreClockUpdate(void)
<> 144:ef7eb2e8f9f7 280 {
<> 144:ef7eb2e8f9f7 281 uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
<> 144:ef7eb2e8f9f7 282
<> 144:ef7eb2e8f9f7 283 /* Get SYSCLK source -------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 284 tmp = RCC->CFGR & RCC_CFGR_SWS;
<> 144:ef7eb2e8f9f7 285
<> 144:ef7eb2e8f9f7 286 switch (tmp)
<> 144:ef7eb2e8f9f7 287 {
<> 144:ef7eb2e8f9f7 288 case 0x00: /* HSI used as system clock source */
<> 144:ef7eb2e8f9f7 289 SystemCoreClock = HSI_VALUE;
<> 144:ef7eb2e8f9f7 290 break;
<> 144:ef7eb2e8f9f7 291 case 0x04: /* HSE used as system clock source */
<> 144:ef7eb2e8f9f7 292 SystemCoreClock = HSE_VALUE;
<> 144:ef7eb2e8f9f7 293 break;
<> 144:ef7eb2e8f9f7 294 case 0x08: /* PLL used as system clock source */
<> 144:ef7eb2e8f9f7 295
<> 144:ef7eb2e8f9f7 296 /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N
<> 144:ef7eb2e8f9f7 297 SYSCLK = PLL_VCO / PLL_P
<> 144:ef7eb2e8f9f7 298 */
<> 144:ef7eb2e8f9f7 299 pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
<> 144:ef7eb2e8f9f7 300 pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
<> 144:ef7eb2e8f9f7 301
<> 144:ef7eb2e8f9f7 302 if (pllsource != 0)
<> 144:ef7eb2e8f9f7 303 {
<> 144:ef7eb2e8f9f7 304 /* HSE used as PLL clock source */
<> 144:ef7eb2e8f9f7 305 pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
<> 144:ef7eb2e8f9f7 306 }
<> 144:ef7eb2e8f9f7 307 else
<> 144:ef7eb2e8f9f7 308 {
<> 144:ef7eb2e8f9f7 309 /* HSI used as PLL clock source */
<> 144:ef7eb2e8f9f7 310 pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
<> 144:ef7eb2e8f9f7 311 }
<> 144:ef7eb2e8f9f7 312
<> 144:ef7eb2e8f9f7 313 pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;
<> 144:ef7eb2e8f9f7 314 SystemCoreClock = pllvco/pllp;
<> 144:ef7eb2e8f9f7 315 break;
<> 144:ef7eb2e8f9f7 316 default:
<> 144:ef7eb2e8f9f7 317 SystemCoreClock = HSI_VALUE;
<> 144:ef7eb2e8f9f7 318 break;
<> 144:ef7eb2e8f9f7 319 }
<> 144:ef7eb2e8f9f7 320 /* Compute HCLK frequency --------------------------------------------------*/
<> 144:ef7eb2e8f9f7 321 /* Get HCLK prescaler */
<> 144:ef7eb2e8f9f7 322 tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
<> 144:ef7eb2e8f9f7 323 /* HCLK frequency */
<> 144:ef7eb2e8f9f7 324 SystemCoreClock >>= tmp;
<> 144:ef7eb2e8f9f7 325 }
<> 144:ef7eb2e8f9f7 326
<> 144:ef7eb2e8f9f7 327 #if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
<> 144:ef7eb2e8f9f7 328 /**
<> 144:ef7eb2e8f9f7 329 * @brief Setup the external memory controller.
<> 144:ef7eb2e8f9f7 330 * Called in startup_stm32f7xx.s before jump to main.
<> 144:ef7eb2e8f9f7 331 * This function configures the external memories (SRAM/SDRAM)
<> 144:ef7eb2e8f9f7 332 * This SRAM/SDRAM will be used as program data memory (including heap and stack).
<> 144:ef7eb2e8f9f7 333 * @param None
<> 144:ef7eb2e8f9f7 334 * @retval None
<> 144:ef7eb2e8f9f7 335 */
<> 144:ef7eb2e8f9f7 336 void SystemInit_ExtMemCtl(void)
<> 144:ef7eb2e8f9f7 337 {
<> 144:ef7eb2e8f9f7 338 __IO uint32_t tmp = 0;
<> 144:ef7eb2e8f9f7 339 #if defined (DATA_IN_ExtSDRAM) && defined (DATA_IN_ExtSRAM)
<> 144:ef7eb2e8f9f7 340 register uint32_t tmpreg = 0, timeout = 0xFFFF;
<> 144:ef7eb2e8f9f7 341 register uint32_t index;
<> 144:ef7eb2e8f9f7 342
<> 144:ef7eb2e8f9f7 343 /* Enable GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface
<> 144:ef7eb2e8f9f7 344 clock */
<> 144:ef7eb2e8f9f7 345 RCC->AHB1ENR |= 0x000001F8;
<> 144:ef7eb2e8f9f7 346
<> 144:ef7eb2e8f9f7 347 /* Delay after an RCC peripheral clock enabling */
<> 144:ef7eb2e8f9f7 348 tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);
<> 144:ef7eb2e8f9f7 349
<> 144:ef7eb2e8f9f7 350 /* Connect PDx pins to FMC Alternate function */
<> 144:ef7eb2e8f9f7 351 GPIOD->AFR[0] = 0x00CCC0CC;
<> 144:ef7eb2e8f9f7 352 GPIOD->AFR[1] = 0xCCCCCCCC;
<> 144:ef7eb2e8f9f7 353 /* Configure PDx pins in Alternate function mode */
<> 144:ef7eb2e8f9f7 354 GPIOD->MODER = 0xAAAA0A8A;
<> 144:ef7eb2e8f9f7 355
<> 144:ef7eb2e8f9f7 356 /* Configure PDx pins speed to 100 MHz */
<> 144:ef7eb2e8f9f7 357 GPIOD->OSPEEDR = 0xFFFF0FCF;
<> 144:ef7eb2e8f9f7 358 /* Configure PDx pins Output type to push-pull */
<> 144:ef7eb2e8f9f7 359 GPIOD->OTYPER = 0x00000000;
<> 144:ef7eb2e8f9f7 360 /* No pull-up, pull-down for PDx pins */
<> 144:ef7eb2e8f9f7 361 GPIOD->PUPDR = 0x55550545;
<> 144:ef7eb2e8f9f7 362
<> 144:ef7eb2e8f9f7 363 /* Connect PEx pins to FMC Alternate function */
<> 144:ef7eb2e8f9f7 364 GPIOE->AFR[0] = 0xC00CC0CC;
<> 144:ef7eb2e8f9f7 365 GPIOE->AFR[1] = 0xCCCCCCCC;
<> 144:ef7eb2e8f9f7 366 /* Configure PEx pins in Alternate function mode */
<> 144:ef7eb2e8f9f7 367 GPIOE->MODER = 0xAAAA828A;
<> 144:ef7eb2e8f9f7 368 /* Configure PEx pins speed to 50 MHz */
<> 144:ef7eb2e8f9f7 369 GPIOE->OSPEEDR = 0xFFFFC3CF;
<> 144:ef7eb2e8f9f7 370 /* Configure PEx pins Output type to push-pull */
<> 144:ef7eb2e8f9f7 371 GPIOE->OTYPER = 0x00000000;
<> 144:ef7eb2e8f9f7 372 /* No pull-up, pull-down for PEx pins */
<> 144:ef7eb2e8f9f7 373 GPIOE->PUPDR = 0x55554145;
<> 144:ef7eb2e8f9f7 374
<> 144:ef7eb2e8f9f7 375 /* Connect PFx pins to FMC Alternate function */
<> 144:ef7eb2e8f9f7 376 GPIOF->AFR[0] = 0x00CCCCCC;
<> 144:ef7eb2e8f9f7 377 GPIOF->AFR[1] = 0xCCCCC000;
<> 144:ef7eb2e8f9f7 378 /* Configure PFx pins in Alternate function mode */
<> 144:ef7eb2e8f9f7 379 GPIOF->MODER = 0xAA800AAA;
<> 144:ef7eb2e8f9f7 380 /* Configure PFx pins speed to 50 MHz */
<> 144:ef7eb2e8f9f7 381 GPIOF->OSPEEDR = 0xFF800FFF;
<> 144:ef7eb2e8f9f7 382 /* Configure PFx pins Output type to push-pull */
<> 144:ef7eb2e8f9f7 383 GPIOF->OTYPER = 0x00000000;
<> 144:ef7eb2e8f9f7 384 /* No pull-up, pull-down for PFx pins */
<> 144:ef7eb2e8f9f7 385 GPIOF->PUPDR = 0x55400555;
<> 144:ef7eb2e8f9f7 386
<> 144:ef7eb2e8f9f7 387 /* Connect PGx pins to FMC Alternate function */
<> 144:ef7eb2e8f9f7 388 GPIOG->AFR[0] = 0x00CC00CC;
<> 144:ef7eb2e8f9f7 389 GPIOG->AFR[1] = 0xC00000CC;
<> 144:ef7eb2e8f9f7 390 /* Configure PGx pins in Alternate function mode */
<> 144:ef7eb2e8f9f7 391 GPIOG->MODER = 0x80220AAA;
<> 144:ef7eb2e8f9f7 392 /* Configure PGx pins speed to 50 MHz */
<> 144:ef7eb2e8f9f7 393 GPIOG->OSPEEDR = 0x80320FFF;
<> 144:ef7eb2e8f9f7 394 /* Configure PGx pins Output type to push-pull */
<> 144:ef7eb2e8f9f7 395 GPIOG->OTYPER = 0x00000000;
<> 144:ef7eb2e8f9f7 396 /* No pull-up, pull-down for PGx pins */
<> 144:ef7eb2e8f9f7 397 GPIOG->PUPDR = 0x40110555;
<> 144:ef7eb2e8f9f7 398
<> 144:ef7eb2e8f9f7 399 /* Connect PHx pins to FMC Alternate function */
<> 144:ef7eb2e8f9f7 400 GPIOH->AFR[0] = 0x00C0CC00;
<> 144:ef7eb2e8f9f7 401 GPIOH->AFR[1] = 0xCCCCCCCC;
<> 144:ef7eb2e8f9f7 402 /* Configure PHx pins in Alternate function mode */
<> 144:ef7eb2e8f9f7 403 GPIOH->MODER = 0xAAAA08A0;
<> 144:ef7eb2e8f9f7 404 /* Configure PHx pins speed to 50 MHz */
<> 144:ef7eb2e8f9f7 405 GPIOH->OSPEEDR = 0xAAAA08A0;
<> 144:ef7eb2e8f9f7 406 /* Configure PHx pins Output type to push-pull */
<> 144:ef7eb2e8f9f7 407 GPIOH->OTYPER = 0x00000000;
<> 144:ef7eb2e8f9f7 408 /* No pull-up, pull-down for PHx pins */
<> 144:ef7eb2e8f9f7 409 GPIOH->PUPDR = 0x55550450;
<> 144:ef7eb2e8f9f7 410
<> 144:ef7eb2e8f9f7 411 /* Connect PIx pins to FMC Alternate function */
<> 144:ef7eb2e8f9f7 412 GPIOI->AFR[0] = 0xCCCCCCCC;
<> 144:ef7eb2e8f9f7 413 GPIOI->AFR[1] = 0x00000CC0;
<> 144:ef7eb2e8f9f7 414 /* Configure PIx pins in Alternate function mode */
<> 144:ef7eb2e8f9f7 415 GPIOI->MODER = 0x0028AAAA;
<> 144:ef7eb2e8f9f7 416 /* Configure PIx pins speed to 50 MHz */
<> 144:ef7eb2e8f9f7 417 GPIOI->OSPEEDR = 0x0028AAAA;
<> 144:ef7eb2e8f9f7 418 /* Configure PIx pins Output type to push-pull */
<> 144:ef7eb2e8f9f7 419 GPIOI->OTYPER = 0x00000000;
<> 144:ef7eb2e8f9f7 420 /* No pull-up, pull-down for PIx pins */
<> 144:ef7eb2e8f9f7 421 GPIOI->PUPDR = 0x00145555;
<> 144:ef7eb2e8f9f7 422
<> 144:ef7eb2e8f9f7 423 /*-- FMC Configuration ------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 424 /* Enable the FMC interface clock */
<> 144:ef7eb2e8f9f7 425 RCC->AHB3ENR |= 0x00000001;
<> 144:ef7eb2e8f9f7 426
<> 144:ef7eb2e8f9f7 427 /* Delay after an RCC peripheral clock enabling */
<> 144:ef7eb2e8f9f7 428 tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);
<> 144:ef7eb2e8f9f7 429
<> 144:ef7eb2e8f9f7 430 /* Configure and enable Bank1_SRAM2 */
<> 144:ef7eb2e8f9f7 431 FMC_Bank1->BTCR[4] = 0x00001091;
<> 144:ef7eb2e8f9f7 432 FMC_Bank1->BTCR[5] = 0x00110212;
<> 144:ef7eb2e8f9f7 433 FMC_Bank1E->BWTR[4] = 0x0FFFFFFF;
<> 144:ef7eb2e8f9f7 434
<> 144:ef7eb2e8f9f7 435 /* Configure and enable SDRAM bank1 */
<> 144:ef7eb2e8f9f7 436 FMC_Bank5_6->SDCR[0] = 0x000019E5;
<> 144:ef7eb2e8f9f7 437 FMC_Bank5_6->SDTR[0] = 0x01116361;
<> 144:ef7eb2e8f9f7 438
<> 144:ef7eb2e8f9f7 439 /* SDRAM initialization sequence */
<> 144:ef7eb2e8f9f7 440 /* Clock enable command */
<> 144:ef7eb2e8f9f7 441 FMC_Bank5_6->SDCMR = 0x00000011;
<> 144:ef7eb2e8f9f7 442 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
<> 144:ef7eb2e8f9f7 443 while((tmpreg != 0) && (timeout-- > 0))
<> 144:ef7eb2e8f9f7 444 {
<> 144:ef7eb2e8f9f7 445 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
<> 144:ef7eb2e8f9f7 446 }
<> 144:ef7eb2e8f9f7 447
<> 144:ef7eb2e8f9f7 448 /* Delay */
<> 144:ef7eb2e8f9f7 449 for (index = 0; index<1000; index++);
<> 144:ef7eb2e8f9f7 450
<> 144:ef7eb2e8f9f7 451 /* PALL command */
<> 144:ef7eb2e8f9f7 452 FMC_Bank5_6->SDCMR = 0x00000012;
<> 144:ef7eb2e8f9f7 453 timeout = 0xFFFF;
<> 144:ef7eb2e8f9f7 454 while((tmpreg != 0) && (timeout-- > 0))
<> 144:ef7eb2e8f9f7 455 {
<> 144:ef7eb2e8f9f7 456 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
<> 144:ef7eb2e8f9f7 457 }
<> 144:ef7eb2e8f9f7 458
<> 144:ef7eb2e8f9f7 459 /* Auto refresh command */
<> 144:ef7eb2e8f9f7 460 FMC_Bank5_6->SDCMR = 0x000000F3;
<> 144:ef7eb2e8f9f7 461 timeout = 0xFFFF;
<> 144:ef7eb2e8f9f7 462 while((tmpreg != 0) && (timeout-- > 0))
<> 144:ef7eb2e8f9f7 463 {
<> 144:ef7eb2e8f9f7 464 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
<> 144:ef7eb2e8f9f7 465 }
<> 144:ef7eb2e8f9f7 466
<> 144:ef7eb2e8f9f7 467 /* MRD register program */
<> 144:ef7eb2e8f9f7 468 FMC_Bank5_6->SDCMR = 0x00046014;
<> 144:ef7eb2e8f9f7 469 timeout = 0xFFFF;
<> 144:ef7eb2e8f9f7 470 while((tmpreg != 0) && (timeout-- > 0))
<> 144:ef7eb2e8f9f7 471 {
<> 144:ef7eb2e8f9f7 472 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
<> 144:ef7eb2e8f9f7 473 }
<> 144:ef7eb2e8f9f7 474
<> 144:ef7eb2e8f9f7 475 /* Set refresh count */
<> 144:ef7eb2e8f9f7 476 tmpreg = FMC_Bank5_6->SDRTR;
<> 144:ef7eb2e8f9f7 477 FMC_Bank5_6->SDRTR = (tmpreg | (0x00000603<<1));
<> 144:ef7eb2e8f9f7 478
<> 144:ef7eb2e8f9f7 479 /* Disable write protection */
<> 144:ef7eb2e8f9f7 480 tmpreg = FMC_Bank5_6->SDCR[0];
<> 144:ef7eb2e8f9f7 481 FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF);
<> 144:ef7eb2e8f9f7 482
<> 144:ef7eb2e8f9f7 483 #elif defined (DATA_IN_ExtSDRAM)
<> 144:ef7eb2e8f9f7 484 register uint32_t tmpreg = 0, timeout = 0xFFFF;
<> 144:ef7eb2e8f9f7 485 register uint32_t index;
<> 144:ef7eb2e8f9f7 486
<> 144:ef7eb2e8f9f7 487 /* Enable GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface
<> 144:ef7eb2e8f9f7 488 clock */
<> 144:ef7eb2e8f9f7 489 RCC->AHB1ENR |= 0x000001F8;
<> 144:ef7eb2e8f9f7 490
<> 144:ef7eb2e8f9f7 491 /* Delay after an RCC peripheral clock enabling */
<> 144:ef7eb2e8f9f7 492 tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);
<> 144:ef7eb2e8f9f7 493
<> 144:ef7eb2e8f9f7 494 /* Connect PDx pins to FMC Alternate function */
<> 144:ef7eb2e8f9f7 495 GPIOD->AFR[0] = 0x000000CC;
<> 144:ef7eb2e8f9f7 496 GPIOD->AFR[1] = 0xCC000CCC;
<> 144:ef7eb2e8f9f7 497 /* Configure PDx pins in Alternate function mode */
<> 144:ef7eb2e8f9f7 498 GPIOD->MODER = 0xA02A000A;
<> 144:ef7eb2e8f9f7 499 /* Configure PDx pins speed to 50 MHz */
<> 144:ef7eb2e8f9f7 500 GPIOD->OSPEEDR = 0xA02A000A;
<> 144:ef7eb2e8f9f7 501 /* Configure PDx pins Output type to push-pull */
<> 144:ef7eb2e8f9f7 502 GPIOD->OTYPER = 0x00000000;
<> 144:ef7eb2e8f9f7 503 /* No pull-up, pull-down for PDx pins */
<> 144:ef7eb2e8f9f7 504 GPIOD->PUPDR = 0x50150005;
<> 144:ef7eb2e8f9f7 505
<> 144:ef7eb2e8f9f7 506 /* Connect PEx pins to FMC Alternate function */
<> 144:ef7eb2e8f9f7 507 GPIOE->AFR[0] = 0xC00000CC;
<> 144:ef7eb2e8f9f7 508 GPIOE->AFR[1] = 0xCCCCCCCC;
<> 144:ef7eb2e8f9f7 509 /* Configure PEx pins in Alternate function mode */
<> 144:ef7eb2e8f9f7 510 GPIOE->MODER = 0xAAAA800A;
<> 144:ef7eb2e8f9f7 511 /* Configure PEx pins speed to 50 MHz */
<> 144:ef7eb2e8f9f7 512 GPIOE->OSPEEDR = 0xAAAA800A;
<> 144:ef7eb2e8f9f7 513 /* Configure PEx pins Output type to push-pull */
<> 144:ef7eb2e8f9f7 514 GPIOE->OTYPER = 0x00000000;
<> 144:ef7eb2e8f9f7 515 /* No pull-up, pull-down for PEx pins */
<> 144:ef7eb2e8f9f7 516 GPIOE->PUPDR = 0x55554005;
<> 144:ef7eb2e8f9f7 517
<> 144:ef7eb2e8f9f7 518 /* Connect PFx pins to FMC Alternate function */
<> 144:ef7eb2e8f9f7 519 GPIOF->AFR[0] = 0x00CCCCCC;
<> 144:ef7eb2e8f9f7 520 GPIOF->AFR[1] = 0xCCCCC000;
<> 144:ef7eb2e8f9f7 521 /* Configure PFx pins in Alternate function mode */
<> 144:ef7eb2e8f9f7 522 GPIOF->MODER = 0xAA800AAA;
<> 144:ef7eb2e8f9f7 523 /* Configure PFx pins speed to 50 MHz */
<> 144:ef7eb2e8f9f7 524 GPIOF->OSPEEDR = 0xAA800AAA;
<> 144:ef7eb2e8f9f7 525 /* Configure PFx pins Output type to push-pull */
<> 144:ef7eb2e8f9f7 526 GPIOF->OTYPER = 0x00000000;
<> 144:ef7eb2e8f9f7 527 /* No pull-up, pull-down for PFx pins */
<> 144:ef7eb2e8f9f7 528 GPIOF->PUPDR = 0x55400555;
<> 144:ef7eb2e8f9f7 529
<> 144:ef7eb2e8f9f7 530 /* Connect PGx pins to FMC Alternate function */
<> 144:ef7eb2e8f9f7 531 GPIOG->AFR[0] = 0x00CC00CC;
<> 144:ef7eb2e8f9f7 532 GPIOG->AFR[1] = 0xC000000C;
<> 144:ef7eb2e8f9f7 533 /* Configure PGx pins in Alternate function mode */
<> 144:ef7eb2e8f9f7 534 GPIOG->MODER = 0x80020A0A;
<> 144:ef7eb2e8f9f7 535 /* Configure PGx pins speed to 50 MHz */
<> 144:ef7eb2e8f9f7 536 GPIOG->OSPEEDR = 0x80020A0A;
<> 144:ef7eb2e8f9f7 537 /* Configure PGx pins Output type to push-pull */
<> 144:ef7eb2e8f9f7 538 GPIOG->OTYPER = 0x00000000;
<> 144:ef7eb2e8f9f7 539 /* No pull-up, pull-down for PGx pins */
<> 144:ef7eb2e8f9f7 540 GPIOG->PUPDR = 0x40010505;
<> 144:ef7eb2e8f9f7 541
<> 144:ef7eb2e8f9f7 542 /* Connect PHx pins to FMC Alternate function */
<> 144:ef7eb2e8f9f7 543 GPIOH->AFR[0] = 0x00C0CC00;
<> 144:ef7eb2e8f9f7 544 GPIOH->AFR[1] = 0xCCCCCCCC;
<> 144:ef7eb2e8f9f7 545 /* Configure PHx pins in Alternate function mode */
<> 144:ef7eb2e8f9f7 546 GPIOH->MODER = 0xAAAA08A0;
<> 144:ef7eb2e8f9f7 547 /* Configure PHx pins speed to 50 MHz */
<> 144:ef7eb2e8f9f7 548 GPIOH->OSPEEDR = 0xAAAA08A0;
<> 144:ef7eb2e8f9f7 549 /* Configure PHx pins Output type to push-pull */
<> 144:ef7eb2e8f9f7 550 GPIOH->OTYPER = 0x00000000;
<> 144:ef7eb2e8f9f7 551 /* No pull-up, pull-down for PHx pins */
<> 144:ef7eb2e8f9f7 552 GPIOH->PUPDR = 0x55550450;
<> 144:ef7eb2e8f9f7 553
<> 144:ef7eb2e8f9f7 554 /* Connect PIx pins to FMC Alternate function */
<> 144:ef7eb2e8f9f7 555 GPIOI->AFR[0] = 0xCCCCCCCC;
<> 144:ef7eb2e8f9f7 556 GPIOI->AFR[1] = 0x00000CC0;
<> 144:ef7eb2e8f9f7 557 /* Configure PIx pins in Alternate function mode */
<> 144:ef7eb2e8f9f7 558 GPIOI->MODER = 0x0028AAAA;
<> 144:ef7eb2e8f9f7 559 /* Configure PIx pins speed to 50 MHz */
<> 144:ef7eb2e8f9f7 560 GPIOI->OSPEEDR = 0x0028AAAA;
<> 144:ef7eb2e8f9f7 561 /* Configure PIx pins Output type to push-pull */
<> 144:ef7eb2e8f9f7 562 GPIOI->OTYPER = 0x00000000;
<> 144:ef7eb2e8f9f7 563 /* No pull-up, pull-down for PIx pins */
<> 144:ef7eb2e8f9f7 564 GPIOI->PUPDR = 0x00145555;
<> 144:ef7eb2e8f9f7 565
<> 144:ef7eb2e8f9f7 566 /*-- FMC Configuration ------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 567 /* Enable the FMC interface clock */
<> 144:ef7eb2e8f9f7 568 RCC->AHB3ENR |= 0x00000001;
<> 144:ef7eb2e8f9f7 569
<> 144:ef7eb2e8f9f7 570 /* Delay after an RCC peripheral clock enabling */
<> 144:ef7eb2e8f9f7 571 tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);
<> 144:ef7eb2e8f9f7 572
<> 144:ef7eb2e8f9f7 573 /* Configure and enable SDRAM bank1 */
<> 144:ef7eb2e8f9f7 574 FMC_Bank5_6->SDCR[0] = 0x000019E5;
<> 144:ef7eb2e8f9f7 575 FMC_Bank5_6->SDTR[0] = 0x01116361;
<> 144:ef7eb2e8f9f7 576
<> 144:ef7eb2e8f9f7 577 /* SDRAM initialization sequence */
<> 144:ef7eb2e8f9f7 578 /* Clock enable command */
<> 144:ef7eb2e8f9f7 579 FMC_Bank5_6->SDCMR = 0x00000011;
<> 144:ef7eb2e8f9f7 580 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
<> 144:ef7eb2e8f9f7 581 while((tmpreg != 0) && (timeout-- > 0))
<> 144:ef7eb2e8f9f7 582 {
<> 144:ef7eb2e8f9f7 583 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
<> 144:ef7eb2e8f9f7 584 }
<> 144:ef7eb2e8f9f7 585
<> 144:ef7eb2e8f9f7 586 /* Delay */
<> 144:ef7eb2e8f9f7 587 for (index = 0; index<1000; index++);
<> 144:ef7eb2e8f9f7 588
<> 144:ef7eb2e8f9f7 589 /* PALL command */
<> 144:ef7eb2e8f9f7 590 FMC_Bank5_6->SDCMR = 0x00000012;
<> 144:ef7eb2e8f9f7 591 timeout = 0xFFFF;
<> 144:ef7eb2e8f9f7 592 while((tmpreg != 0) && (timeout-- > 0))
<> 144:ef7eb2e8f9f7 593 {
<> 144:ef7eb2e8f9f7 594 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
<> 144:ef7eb2e8f9f7 595 }
<> 144:ef7eb2e8f9f7 596
<> 144:ef7eb2e8f9f7 597 /* Auto refresh command */
<> 144:ef7eb2e8f9f7 598 FMC_Bank5_6->SDCMR = 0x000000F3;
<> 144:ef7eb2e8f9f7 599 timeout = 0xFFFF;
<> 144:ef7eb2e8f9f7 600 while((tmpreg != 0) && (timeout-- > 0))
<> 144:ef7eb2e8f9f7 601 {
<> 144:ef7eb2e8f9f7 602 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
<> 144:ef7eb2e8f9f7 603 }
<> 144:ef7eb2e8f9f7 604
<> 144:ef7eb2e8f9f7 605 /* MRD register program */
<> 144:ef7eb2e8f9f7 606 FMC_Bank5_6->SDCMR = 0x00046014;
<> 144:ef7eb2e8f9f7 607 timeout = 0xFFFF;
<> 144:ef7eb2e8f9f7 608 while((tmpreg != 0) && (timeout-- > 0))
<> 144:ef7eb2e8f9f7 609 {
<> 144:ef7eb2e8f9f7 610 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
<> 144:ef7eb2e8f9f7 611 }
<> 144:ef7eb2e8f9f7 612
<> 144:ef7eb2e8f9f7 613 /* Set refresh count */
<> 144:ef7eb2e8f9f7 614 tmpreg = FMC_Bank5_6->SDRTR;
<> 144:ef7eb2e8f9f7 615 FMC_Bank5_6->SDRTR = (tmpreg | (0x00000603<<1));
<> 144:ef7eb2e8f9f7 616
<> 144:ef7eb2e8f9f7 617 /* Disable write protection */
<> 144:ef7eb2e8f9f7 618 tmpreg = FMC_Bank5_6->SDCR[0];
<> 144:ef7eb2e8f9f7 619 FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF);
<> 144:ef7eb2e8f9f7 620
<> 144:ef7eb2e8f9f7 621 #elif defined(DATA_IN_ExtSRAM)
<> 144:ef7eb2e8f9f7 622 /*-- GPIOs Configuration -----------------------------------------------------*/
<> 144:ef7eb2e8f9f7 623 /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */
<> 144:ef7eb2e8f9f7 624 RCC->AHB1ENR |= 0x00000078;
<> 144:ef7eb2e8f9f7 625
<> 144:ef7eb2e8f9f7 626 /* Delay after an RCC peripheral clock enabling */
<> 144:ef7eb2e8f9f7 627 tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);
<> 144:ef7eb2e8f9f7 628
<> 144:ef7eb2e8f9f7 629 /* Connect PDx pins to FMC Alternate function */
<> 144:ef7eb2e8f9f7 630 GPIOD->AFR[0] = 0x00CCC0CC;
<> 144:ef7eb2e8f9f7 631 GPIOD->AFR[1] = 0xCCCCCCCC;
<> 144:ef7eb2e8f9f7 632 /* Configure PDx pins in Alternate function mode */
<> 144:ef7eb2e8f9f7 633 GPIOD->MODER = 0xAAAA0A8A;
<> 144:ef7eb2e8f9f7 634 /* Configure PDx pins speed to 100 MHz */
<> 144:ef7eb2e8f9f7 635 GPIOD->OSPEEDR = 0xFFFF0FCF;
<> 144:ef7eb2e8f9f7 636 /* Configure PDx pins Output type to push-pull */
<> 144:ef7eb2e8f9f7 637 GPIOD->OTYPER = 0x00000000;
<> 144:ef7eb2e8f9f7 638 /* No pull-up, pull-down for PDx pins */
<> 144:ef7eb2e8f9f7 639 GPIOD->PUPDR = 0x55550545;
<> 144:ef7eb2e8f9f7 640
<> 144:ef7eb2e8f9f7 641 /* Connect PEx pins to FMC Alternate function */
<> 144:ef7eb2e8f9f7 642 GPIOE->AFR[0] = 0xC00CC0CC;
<> 144:ef7eb2e8f9f7 643 GPIOE->AFR[1] = 0xCCCCCCCC;
<> 144:ef7eb2e8f9f7 644 /* Configure PEx pins in Alternate function mode */
<> 144:ef7eb2e8f9f7 645 GPIOE->MODER = 0xAAAA828A;
<> 144:ef7eb2e8f9f7 646 /* Configure PEx pins speed to 100 MHz */
<> 144:ef7eb2e8f9f7 647 GPIOE->OSPEEDR = 0xFFFFC3CF;
<> 144:ef7eb2e8f9f7 648 /* Configure PEx pins Output type to push-pull */
<> 144:ef7eb2e8f9f7 649 GPIOE->OTYPER = 0x00000000;
<> 144:ef7eb2e8f9f7 650 /* No pull-up, pull-down for PEx pins */
<> 144:ef7eb2e8f9f7 651 GPIOE->PUPDR = 0x55554145;
<> 144:ef7eb2e8f9f7 652
<> 144:ef7eb2e8f9f7 653 /* Connect PFx pins to FMC Alternate function */
<> 144:ef7eb2e8f9f7 654 GPIOF->AFR[0] = 0x00CCCCCC;
<> 144:ef7eb2e8f9f7 655 GPIOF->AFR[1] = 0xCCCC0000;
<> 144:ef7eb2e8f9f7 656 /* Configure PFx pins in Alternate function mode */
<> 144:ef7eb2e8f9f7 657 GPIOF->MODER = 0xAA000AAA;
<> 144:ef7eb2e8f9f7 658 /* Configure PFx pins speed to 100 MHz */
<> 144:ef7eb2e8f9f7 659 GPIOF->OSPEEDR = 0xFF000FFF;
<> 144:ef7eb2e8f9f7 660 /* Configure PFx pins Output type to push-pull */
<> 144:ef7eb2e8f9f7 661 GPIOF->OTYPER = 0x00000000;
<> 144:ef7eb2e8f9f7 662 /* No pull-up, pull-down for PFx pins */
<> 144:ef7eb2e8f9f7 663 GPIOF->PUPDR = 0x55000555;
<> 144:ef7eb2e8f9f7 664
<> 144:ef7eb2e8f9f7 665 /* Connect PGx pins to FMC Alternate function */
<> 144:ef7eb2e8f9f7 666 GPIOG->AFR[0] = 0x00CCCCCC;
<> 144:ef7eb2e8f9f7 667 GPIOG->AFR[1] = 0x000000C0;
<> 144:ef7eb2e8f9f7 668 /* Configure PGx pins in Alternate function mode */
<> 144:ef7eb2e8f9f7 669 GPIOG->MODER = 0x00200AAA;
<> 144:ef7eb2e8f9f7 670 /* Configure PGx pins speed to 100 MHz */
<> 144:ef7eb2e8f9f7 671 GPIOG->OSPEEDR = 0x00300FFF;
<> 144:ef7eb2e8f9f7 672 /* Configure PGx pins Output type to push-pull */
<> 144:ef7eb2e8f9f7 673 GPIOG->OTYPER = 0x00000000;
<> 144:ef7eb2e8f9f7 674 /* No pull-up, pull-down for PGx pins */
<> 144:ef7eb2e8f9f7 675 GPIOG->PUPDR = 0x00100555;
<> 144:ef7eb2e8f9f7 676
<> 144:ef7eb2e8f9f7 677 /*-- FMC/FSMC Configuration --------------------------------------------------*/
<> 144:ef7eb2e8f9f7 678 /* Enable the FMC/FSMC interface clock */
<> 144:ef7eb2e8f9f7 679 RCC->AHB3ENR |= 0x00000001;
<> 144:ef7eb2e8f9f7 680
<> 144:ef7eb2e8f9f7 681 /* Delay after an RCC peripheral clock enabling */
<> 144:ef7eb2e8f9f7 682 tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);
<> 144:ef7eb2e8f9f7 683
<> 144:ef7eb2e8f9f7 684 /* Configure and enable Bank1_SRAM2 */
<> 144:ef7eb2e8f9f7 685 FMC_Bank1->BTCR[4] = 0x00001091;
<> 144:ef7eb2e8f9f7 686 FMC_Bank1->BTCR[5] = 0x00110212;
<> 144:ef7eb2e8f9f7 687 FMC_Bank1E->BWTR[4] = 0x0FFFFFFF;
<> 144:ef7eb2e8f9f7 688
<> 144:ef7eb2e8f9f7 689 #endif /* DATA_IN_ExtSRAM */
<> 144:ef7eb2e8f9f7 690
<> 144:ef7eb2e8f9f7 691 (void)(tmp);
<> 144:ef7eb2e8f9f7 692 }
<> 144:ef7eb2e8f9f7 693 #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
<> 144:ef7eb2e8f9f7 694
<> 144:ef7eb2e8f9f7 695 /**
<> 144:ef7eb2e8f9f7 696 * @brief Configures the System clock source, PLL Multiplier and Divider factors,
<> 144:ef7eb2e8f9f7 697 * AHB/APBx prescalers and Flash settings
<> 144:ef7eb2e8f9f7 698 * @note This function should be called only once the RCC clock configuration
<> 144:ef7eb2e8f9f7 699 * is reset to the default reset state (done in SystemInit() function).
<> 144:ef7eb2e8f9f7 700 * @param None
<> 144:ef7eb2e8f9f7 701 * @retval None
<> 144:ef7eb2e8f9f7 702 */
<> 144:ef7eb2e8f9f7 703 void SetSysClock(void)
<> 144:ef7eb2e8f9f7 704 {
<> 144:ef7eb2e8f9f7 705 /* 1- Try to start with HSE and external clock */
<> 144:ef7eb2e8f9f7 706 #if USE_PLL_HSE_EXTC != 0
<> 144:ef7eb2e8f9f7 707 if (SetSysClock_PLL_HSE(1) == 0)
<> 144:ef7eb2e8f9f7 708 #endif
<> 144:ef7eb2e8f9f7 709 {
<> 144:ef7eb2e8f9f7 710 /* 2- If fail try to start with HSE and external xtal */
<> 144:ef7eb2e8f9f7 711 #if USE_PLL_HSE_XTAL != 0
<> 144:ef7eb2e8f9f7 712 if (SetSysClock_PLL_HSE(0) == 0)
<> 144:ef7eb2e8f9f7 713 #endif
<> 144:ef7eb2e8f9f7 714 {
<> 144:ef7eb2e8f9f7 715 /* 3- If fail start with HSI clock */
<> 144:ef7eb2e8f9f7 716 if (SetSysClock_PLL_HSI() == 0)
<> 144:ef7eb2e8f9f7 717 {
<> 144:ef7eb2e8f9f7 718 while(1)
<> 144:ef7eb2e8f9f7 719 {
<> 144:ef7eb2e8f9f7 720 // [TODO] Put something here to tell the user that a problem occured...
<> 144:ef7eb2e8f9f7 721 }
<> 144:ef7eb2e8f9f7 722 }
<> 144:ef7eb2e8f9f7 723 }
<> 144:ef7eb2e8f9f7 724 }
<> 144:ef7eb2e8f9f7 725
<> 144:ef7eb2e8f9f7 726 // Output clock on MCO2 pin(PC9) for debugging purpose
<> 144:ef7eb2e8f9f7 727 // Can be visualized on CN8 connector pin 4
<> 144:ef7eb2e8f9f7 728 //HAL_RCC_MCOConfig(RCC_MCO2, RCC_MCO2SOURCE_SYSCLK, RCC_MCODIV_4); // 216 MHz / 4 = 54 MHz
<> 144:ef7eb2e8f9f7 729 }
<> 144:ef7eb2e8f9f7 730
<> 144:ef7eb2e8f9f7 731 #if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
<> 144:ef7eb2e8f9f7 732 /******************************************************************************/
<> 144:ef7eb2e8f9f7 733 /* PLL (clocked by HSE) used as System clock source */
<> 144:ef7eb2e8f9f7 734 /******************************************************************************/
<> 144:ef7eb2e8f9f7 735 uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
<> 144:ef7eb2e8f9f7 736 {
<> 144:ef7eb2e8f9f7 737 RCC_ClkInitTypeDef RCC_ClkInitStruct;
<> 144:ef7eb2e8f9f7 738 RCC_OscInitTypeDef RCC_OscInitStruct;
<> 144:ef7eb2e8f9f7 739
<> 144:ef7eb2e8f9f7 740 // Enable power clock
<> 144:ef7eb2e8f9f7 741 __PWR_CLK_ENABLE();
<> 144:ef7eb2e8f9f7 742
<> 144:ef7eb2e8f9f7 743 // Enable HSE oscillator and activate PLL with HSE as source
<> 144:ef7eb2e8f9f7 744 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
<> 144:ef7eb2e8f9f7 745 if (bypass == 0)
<> 144:ef7eb2e8f9f7 746 {
<> 144:ef7eb2e8f9f7 747 RCC_OscInitStruct.HSEState = RCC_HSE_ON; /* External xtal on OSC_IN/OSC_OUT */
<> 144:ef7eb2e8f9f7 748 }
<> 144:ef7eb2e8f9f7 749 else
<> 144:ef7eb2e8f9f7 750 {
<> 144:ef7eb2e8f9f7 751 RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; /* External clock on OSC_IN */
<> 144:ef7eb2e8f9f7 752 }
<> 144:ef7eb2e8f9f7 753 // Warning: this configuration is for a 8 MHz xtal clock only
<> 144:ef7eb2e8f9f7 754 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
<> 144:ef7eb2e8f9f7 755 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
<> 144:ef7eb2e8f9f7 756 RCC_OscInitStruct.PLL.PLLM = 8; // VCO input clock = 1 MHz (8 MHz / 8)
<> 144:ef7eb2e8f9f7 757 RCC_OscInitStruct.PLL.PLLN = 432; // VCO output clock = 432 MHz (1 MHz * 432)
<> 144:ef7eb2e8f9f7 758 RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; // PLLCLK = 216 MHz (432 MHz / 2)
<> 144:ef7eb2e8f9f7 759 RCC_OscInitStruct.PLL.PLLQ = 9; // USB clock = 48 MHz (432 MHz / 9) --> OK for USB
<> 144:ef7eb2e8f9f7 760
<> 144:ef7eb2e8f9f7 761 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
<> 144:ef7eb2e8f9f7 762 {
<> 144:ef7eb2e8f9f7 763 return 0; // FAIL
<> 144:ef7eb2e8f9f7 764 }
<> 144:ef7eb2e8f9f7 765
<> 144:ef7eb2e8f9f7 766 // Activate the OverDrive to reach the 216 MHz Frequency
<> 144:ef7eb2e8f9f7 767 if (HAL_PWREx_EnableOverDrive() != HAL_OK)
<> 144:ef7eb2e8f9f7 768 {
<> 144:ef7eb2e8f9f7 769 return 0; // FAIL
<> 144:ef7eb2e8f9f7 770 }
<> 144:ef7eb2e8f9f7 771
<> 144:ef7eb2e8f9f7 772 // Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
<> 144:ef7eb2e8f9f7 773 RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
<> 144:ef7eb2e8f9f7 774 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 216 MHz
<> 144:ef7eb2e8f9f7 775 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 216 MHz
<> 144:ef7eb2e8f9f7 776 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; // 54 MHz
<> 144:ef7eb2e8f9f7 777 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; // 108 MHz
<> 144:ef7eb2e8f9f7 778
<> 144:ef7eb2e8f9f7 779 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_7) != HAL_OK)
<> 144:ef7eb2e8f9f7 780 {
<> 144:ef7eb2e8f9f7 781 return 0; // FAIL
<> 144:ef7eb2e8f9f7 782 }
<> 144:ef7eb2e8f9f7 783
<> 144:ef7eb2e8f9f7 784 return 1; // OK
<> 144:ef7eb2e8f9f7 785 }
<> 144:ef7eb2e8f9f7 786 #endif
<> 144:ef7eb2e8f9f7 787
<> 144:ef7eb2e8f9f7 788 /******************************************************************************/
<> 144:ef7eb2e8f9f7 789 /* PLL (clocked by HSI) used as System clock source */
<> 144:ef7eb2e8f9f7 790 /******************************************************************************/
<> 144:ef7eb2e8f9f7 791 uint8_t SetSysClock_PLL_HSI(void)
<> 144:ef7eb2e8f9f7 792 {
<> 144:ef7eb2e8f9f7 793 RCC_ClkInitTypeDef RCC_ClkInitStruct;
<> 144:ef7eb2e8f9f7 794 RCC_OscInitTypeDef RCC_OscInitStruct;
<> 144:ef7eb2e8f9f7 795
<> 144:ef7eb2e8f9f7 796 // Enable CPU L1-Cache
<> 144:ef7eb2e8f9f7 797 SCB_EnableICache();
<> 144:ef7eb2e8f9f7 798 SCB_EnableDCache();
<> 144:ef7eb2e8f9f7 799
<> 144:ef7eb2e8f9f7 800 // Enable power clock
<> 144:ef7eb2e8f9f7 801 __PWR_CLK_ENABLE();
<> 144:ef7eb2e8f9f7 802
<> 144:ef7eb2e8f9f7 803 // Enable HSI oscillator and activate PLL with HSI as source
<> 144:ef7eb2e8f9f7 804 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
<> 144:ef7eb2e8f9f7 805 RCC_OscInitStruct.HSIState = RCC_HSI_ON;
<> 144:ef7eb2e8f9f7 806 RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
<> 144:ef7eb2e8f9f7 807 RCC_OscInitStruct.HSICalibrationValue = 16;
<> 144:ef7eb2e8f9f7 808 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
<> 144:ef7eb2e8f9f7 809 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
<> 144:ef7eb2e8f9f7 810 RCC_OscInitStruct.PLL.PLLM = 16; // VCO input clock = 1 MHz (16 MHz / 16)
<> 144:ef7eb2e8f9f7 811 RCC_OscInitStruct.PLL.PLLN = 432; // VCO output clock = 432 MHz (1 MHz * 432)
<> 144:ef7eb2e8f9f7 812 RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; // PLLCLK = 216 MHz (432 MHz / 2)
<> 144:ef7eb2e8f9f7 813 RCC_OscInitStruct.PLL.PLLQ = 9; // USB clock = 48 MHz (432 MHz / 9) --> OK for USB
<> 144:ef7eb2e8f9f7 814
<> 144:ef7eb2e8f9f7 815 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
<> 144:ef7eb2e8f9f7 816 {
<> 144:ef7eb2e8f9f7 817 return 0; // FAIL
<> 144:ef7eb2e8f9f7 818 }
<> 144:ef7eb2e8f9f7 819
<> 144:ef7eb2e8f9f7 820 // Activate the OverDrive to reach the 216 MHz Frequency
<> 144:ef7eb2e8f9f7 821 if (HAL_PWREx_EnableOverDrive() != HAL_OK)
<> 144:ef7eb2e8f9f7 822 {
<> 144:ef7eb2e8f9f7 823 return 0; // FAIL
<> 144:ef7eb2e8f9f7 824 }
<> 144:ef7eb2e8f9f7 825
<> 144:ef7eb2e8f9f7 826 // Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
<> 144:ef7eb2e8f9f7 827 RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
<> 144:ef7eb2e8f9f7 828 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 216 MHz
<> 144:ef7eb2e8f9f7 829 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 216 MHz
<> 144:ef7eb2e8f9f7 830 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; // 54 MHz
<> 144:ef7eb2e8f9f7 831 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; // 108 MHz
<> 144:ef7eb2e8f9f7 832
<> 144:ef7eb2e8f9f7 833 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_7) != HAL_OK)
<> 144:ef7eb2e8f9f7 834 {
<> 144:ef7eb2e8f9f7 835 return 0; // FAIL
<> 144:ef7eb2e8f9f7 836 }
<> 144:ef7eb2e8f9f7 837
<> 144:ef7eb2e8f9f7 838 return 1; // OK
<> 144:ef7eb2e8f9f7 839 }
<> 144:ef7eb2e8f9f7 840
<> 144:ef7eb2e8f9f7 841 /**
<> 144:ef7eb2e8f9f7 842 * @}
<> 144:ef7eb2e8f9f7 843 */
<> 144:ef7eb2e8f9f7 844
<> 144:ef7eb2e8f9f7 845 /**
<> 144:ef7eb2e8f9f7 846 * @}
<> 144:ef7eb2e8f9f7 847 */
<> 144:ef7eb2e8f9f7 848
<> 144:ef7eb2e8f9f7 849 /**
<> 144:ef7eb2e8f9f7 850 * @}
<> 144:ef7eb2e8f9f7 851 */
<> 144:ef7eb2e8f9f7 852 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/