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targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_spi.c@159:612c381a210f, 2017-02-28 (annotated)

Committer:: <>
Date:: Tue Feb 28 17:13:35 2017 +0000
Revision:: 159:612c381a210f
Parent:: 154:37f96f9d4de2
Child:: 165:e614a9f1c9e2

This updates the lib to the mbed lib v137

Who changed what in which revision?

User	Revision	Line number	New contents of line
<>	144:ef7eb2e8f9f7	1	/**
<>	144:ef7eb2e8f9f7	2	******************************************************************************
<>	144:ef7eb2e8f9f7	3	* @file stm32f1xx_hal_spi.c
<>	144:ef7eb2e8f9f7	4	* @author MCD Application Team
<>	154:37f96f9d4de2	5	* @version V1.0.5
<>	154:37f96f9d4de2	6	* @date 06-December-2016
<>	144:ef7eb2e8f9f7	7	* @brief SPI HAL module driver.
<>	144:ef7eb2e8f9f7	8	*
<>	144:ef7eb2e8f9f7	9	* This file provides firmware functions to manage the following
<>	144:ef7eb2e8f9f7	10	* functionalities of the Serial Peripheral Interface (SPI) peripheral:
<>	144:ef7eb2e8f9f7	11	* + Initialization and de-initialization functions
<>	144:ef7eb2e8f9f7	12	* + IO operation functions
<>	144:ef7eb2e8f9f7	13	* + Peripheral Control functions
<>	144:ef7eb2e8f9f7	14	* + Peripheral State functions
<>	144:ef7eb2e8f9f7	15	@verbatim
<>	144:ef7eb2e8f9f7	16	==============================================================================
<>	144:ef7eb2e8f9f7	17	##### How to use this driver #####
<>	144:ef7eb2e8f9f7	18	==============================================================================
<>	144:ef7eb2e8f9f7	19	[..]
<>	144:ef7eb2e8f9f7	20	The SPI HAL driver can be used as follows:
<>	144:ef7eb2e8f9f7	21
<>	144:ef7eb2e8f9f7	22	(#) Declare a SPI_HandleTypeDef handle structure, for example:
<>	144:ef7eb2e8f9f7	23	SPI_HandleTypeDef hspi;
<>	144:ef7eb2e8f9f7	24
<>	144:ef7eb2e8f9f7	25	(#)Initialize the SPI low level resources by implementing the HAL_SPI_MspInit ()API:
<>	144:ef7eb2e8f9f7	26	(##) Enable the SPIx interface clock
<>	144:ef7eb2e8f9f7	27	(##) SPI pins configuration
<>	144:ef7eb2e8f9f7	28	(+++) Enable the clock for the SPI GPIOs
<>	144:ef7eb2e8f9f7	29	(+++) Configure these SPI pins as alternate function push-pull
<>	144:ef7eb2e8f9f7	30	(##) NVIC configuration if you need to use interrupt process
<>	144:ef7eb2e8f9f7	31	(+++) Configure the SPIx interrupt priority
<>	144:ef7eb2e8f9f7	32	(+++) Enable the NVIC SPI IRQ handle
<>	144:ef7eb2e8f9f7	33	(##) DMA Configuration if you need to use DMA process
<>	144:ef7eb2e8f9f7	34	(+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive Channel
<>	144:ef7eb2e8f9f7	35	(+++) Enable the DMAx clock
<>	144:ef7eb2e8f9f7	36	(+++) Configure the DMA handle parameters
<>	144:ef7eb2e8f9f7	37	(+++) Configure the DMA Tx or Rx Channel
<>	144:ef7eb2e8f9f7	38	(+++) Associate the initilalized hdma_tx(or _rx) handle to the hspi DMA Tx (or Rx) handle
<>	144:ef7eb2e8f9f7	39	(+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx Channel
<>	144:ef7eb2e8f9f7	40
<>	144:ef7eb2e8f9f7	41	(#) Program the Mode, Direction , Data size, Baudrate Prescaler, NSS
<>	144:ef7eb2e8f9f7	42	management, Clock polarity and phase, FirstBit and CRC configuration in the hspi Init structure.
<>	144:ef7eb2e8f9f7	43
<>	144:ef7eb2e8f9f7	44	(#) Initialize the SPI registers by calling the HAL_SPI_Init() API:
<>	144:ef7eb2e8f9f7	45	(++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
<>	144:ef7eb2e8f9f7	46	by calling the customed HAL_SPI_MspInit() API.
<>	144:ef7eb2e8f9f7	47	[..]
<>	144:ef7eb2e8f9f7	48	Circular mode restriction:
<>	144:ef7eb2e8f9f7	49	(#) The DMA circular mode cannot be used when the SPI is configured in these modes:
<>	144:ef7eb2e8f9f7	50	(##) Master 2Lines RxOnly
<>	144:ef7eb2e8f9f7	51	(##) Master 1Line Rx
<>	144:ef7eb2e8f9f7	52	(#) The CRC feature is not managed when the DMA circular mode is enabled
<>	144:ef7eb2e8f9f7	53	(#) When the SPI DMA Pause/Stop features are used, we must use the following APIs
<>	144:ef7eb2e8f9f7	54	the HAL_SPI_DMAPause()/ HAL_SPI_DMAStop() only under the SPI callbacks
<>	144:ef7eb2e8f9f7	55
<>	144:ef7eb2e8f9f7	56	@endverbatim
<>	144:ef7eb2e8f9f7	57	******************************************************************************
<>	144:ef7eb2e8f9f7	58	* @attention
<>	144:ef7eb2e8f9f7	59	*
<>	144:ef7eb2e8f9f7	60	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<>	144:ef7eb2e8f9f7	61	*
<>	144:ef7eb2e8f9f7	62	* Redistribution and use in source and binary forms, with or without modification,
<>	144:ef7eb2e8f9f7	63	* are permitted provided that the following conditions are met:
<>	144:ef7eb2e8f9f7	64	* 1. Redistributions of source code must retain the above copyright notice,
<>	144:ef7eb2e8f9f7	65	* this list of conditions and the following disclaimer.
<>	144:ef7eb2e8f9f7	66	* 2. Redistributions in binary form must reproduce the above copyright notice,
<>	144:ef7eb2e8f9f7	67	* this list of conditions and the following disclaimer in the documentation
<>	144:ef7eb2e8f9f7	68	* and/or other materials provided with the distribution.
<>	144:ef7eb2e8f9f7	69	* 3. Neither the name of STMicroelectronics nor the names of its contributors
<>	144:ef7eb2e8f9f7	70	* may be used to endorse or promote products derived from this software
<>	144:ef7eb2e8f9f7	71	* without specific prior written permission.
<>	144:ef7eb2e8f9f7	72	*
<>	144:ef7eb2e8f9f7	73	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<>	144:ef7eb2e8f9f7	74	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<>	144:ef7eb2e8f9f7	75	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<>	144:ef7eb2e8f9f7	76	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<>	144:ef7eb2e8f9f7	77	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<>	144:ef7eb2e8f9f7	78	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<>	144:ef7eb2e8f9f7	79	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<>	144:ef7eb2e8f9f7	80	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<>	144:ef7eb2e8f9f7	81	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<>	144:ef7eb2e8f9f7	82	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<>	144:ef7eb2e8f9f7	83	*
<>	144:ef7eb2e8f9f7	84	******************************************************************************
<>	144:ef7eb2e8f9f7	85	*/
<>	144:ef7eb2e8f9f7	86
<>	144:ef7eb2e8f9f7	87	/*
<>	144:ef7eb2e8f9f7	88	Using the HAL it is not possible to reach all supported SPI frequency with the differents SPI Modes,
<>	144:ef7eb2e8f9f7	89	the following table resume the max SPI frequency reached with data size 8bits/16bits,
<>	144:ef7eb2e8f9f7	90	according to frequency used on APBx Peripheral Clock (fPCLK) used by the SPI instance :
<>	144:ef7eb2e8f9f7	91
<>	144:ef7eb2e8f9f7	92	For 8 bits SPI data size transfers :
<>	144:ef7eb2e8f9f7	93	+--------------------------------------------------------------------------------------------------+
<>	144:ef7eb2e8f9f7	94	\| \| \| 2Lines Fullduplex \| 2Lines RxOnly \| 1Line \|
<>	144:ef7eb2e8f9f7	95	\| Process \| Tranfert mode \|-----------------------\|-----------------------\|-----------------------\|
<>	144:ef7eb2e8f9f7	96	\| \| \| Master \| Slave \| Master \| Slave \| Master \| Slave \|
<>	144:ef7eb2e8f9f7	97	\|==================================================================================================\|
<>	144:ef7eb2e8f9f7	98	\| T \| Polling \| fPCLK/8 \| fPCLK/8 \| NA \| NA \| NA \| NA \|
<>	144:ef7eb2e8f9f7	99	\| X \|----------------\|-----------\|-----------\|-----------\|-----------\|-----------\|-----------\|
<>	144:ef7eb2e8f9f7	100	\| / \| Interrupt \| fPCLK/32 \| fPCLK/32 \| NA \| NA \| NA \| NA \|
<>	144:ef7eb2e8f9f7	101	\| R \|----------------\|-----------\|-----------\|-----------\|-----------\|-----------\|-----------\|
<>	144:ef7eb2e8f9f7	102	\| X \| DMA \| fPCLK/2 \| fPCLK/4 \| NA \| NA \| NA \| NA \|
<>	144:ef7eb2e8f9f7	103	\|=========\|================\|===========\|===========\|===========\|===========\|===========\|===========\|
<>	144:ef7eb2e8f9f7	104	\| \| Polling \| fPCLK/4 \| fPCLK/8 \| fPCLK/128 \| fPCLK/16 \| fPCLK/128 \| fPCLK/8 \|
<>	144:ef7eb2e8f9f7	105	\| \|----------------\|-----------\|-----------\|-----------\|-----------\|-----------\|-----------\|
<>	144:ef7eb2e8f9f7	106	\| R \| Interrupt \| fPCLK/32 \| fPCLK/16 \| fPCLK/128 \| fPCLK/16 \| fPCLK/128 \| fPCLK/16 \|
<>	144:ef7eb2e8f9f7	107	\| X \|----------------\|-----------\|-----------\|-----------\|-----------\|-----------\|-----------\|
<>	144:ef7eb2e8f9f7	108	\| \| DMA \| fPCLK/2 \| fPCLK/2 \| fPCLK/128 \| fPCLK/16 \| fPCLK/128 \| fPCLK/2 \|
<>	144:ef7eb2e8f9f7	109	\|=========\|================\|===========\|===========\|===========\|===========\|===========\|===========\|
<>	144:ef7eb2e8f9f7	110	\| \| Polling \| fPCLK/4 \| fPCLK/4 \| NA \| NA \| fPCLK/4 \| fPCLK/64 \|
<>	144:ef7eb2e8f9f7	111	\| \|----------------\|-----------\|-----------\|-----------\|-----------\|-----------\|-----------\|
<>	144:ef7eb2e8f9f7	112	\| T \| Interrupt \| fPCLK/8 \| fPCLK/16 \| NA \| NA \| fPCLK/8 \| fPCLK/128 \|
<>	144:ef7eb2e8f9f7	113	\| X \|----------------\|-----------\|-----------\|-----------\|-----------\|-----------\|-----------\|
<>	144:ef7eb2e8f9f7	114	\| \| DMA \| fPCLK/2 \| fPCLK/4 \| NA \| NA \| fPCLK/2 \| fPCLK/64 \|
<>	144:ef7eb2e8f9f7	115	+--------------------------------------------------------------------------------------------------+
<>	144:ef7eb2e8f9f7	116
<>	144:ef7eb2e8f9f7	117	For 16 bits SPI data size transfers :
<>	144:ef7eb2e8f9f7	118	+--------------------------------------------------------------------------------------------------+
<>	144:ef7eb2e8f9f7	119	\| \| \| 2Lines Fullduplex \| 2Lines RxOnly \| 1Line \|
<>	144:ef7eb2e8f9f7	120	\| Process \| Tranfert mode \|-----------------------\|-----------------------\|-----------------------\|
<>	144:ef7eb2e8f9f7	121	\| \| \| Master \| Slave \| Master \| Slave \| Master \| Slave \|
<>	144:ef7eb2e8f9f7	122	\|==================================================================================================\|
<>	144:ef7eb2e8f9f7	123	\| T \| Polling \| fPCLK/2 \| fPCLK/4 \| NA \| NA \| NA \| NA \|
<>	144:ef7eb2e8f9f7	124	\| X \|----------------\|-----------\|-----------\|-----------\|-----------\|-----------\|-----------\|
<>	144:ef7eb2e8f9f7	125	\| / \| Interrupt \| fPCLK/16 \| fPCLK/16 \| NA \| NA \| NA \| NA \|
<>	144:ef7eb2e8f9f7	126	\| R \|----------------\|-----------\|-----------\|-----------\|-----------\|-----------\|-----------\|
<>	144:ef7eb2e8f9f7	127	\| X \| DMA \| fPCLK/2 \| fPCLK/4 \| NA \| NA \| NA \| NA \|
<>	144:ef7eb2e8f9f7	128	\|=========\|================\|===========\|===========\|===========\|===========\|===========\|===========\|
<>	144:ef7eb2e8f9f7	129	\| \| Polling \| fPCLK/2 \| fPCLK/4 \| fPCLK/64 \| fPCLK/8 \| fPCLK/64 \| fPCLK/4 \|
<>	144:ef7eb2e8f9f7	130	\| \|----------------\|-----------\|-----------\|-----------\|-----------\|-----------\|-----------\|
<>	144:ef7eb2e8f9f7	131	\| R \| Interrupt \| fPCLK/16 \| fPCLK/8 \| fPCLK/128 \| fPCLK/8 \| fPCLK/128 \| fPCLK/8 \|
<>	144:ef7eb2e8f9f7	132	\| X \|----------------\|-----------\|-----------\|-----------\|-----------\|-----------\|-----------\|
<>	144:ef7eb2e8f9f7	133	\| \| DMA \| fPCLK/2 \| fPCLK/2 \| fPCLK/128 \| fPCLK/8 \| fPCLK/128 \| fPCLK/2 \|
<>	144:ef7eb2e8f9f7	134	\|=========\|================\|===========\|===========\|===========\|===========\|===========\|===========\|
<>	144:ef7eb2e8f9f7	135	\| \| Polling \| fPCLK/2 \| fPCLK/4 \| NA \| NA \| fPCLK/2 \| fPCLK/64 \|
<>	144:ef7eb2e8f9f7	136	\| \|----------------\|-----------\|-----------\|-----------\|-----------\|-----------\|-----------\|
<>	144:ef7eb2e8f9f7	137	\| T \| Interrupt \| fPCLK/4 \| fPCLK/8 \| NA \| NA \| fPCLK/4 \| fPCLK/256 \|
<>	144:ef7eb2e8f9f7	138	\| X \|----------------\|-----------\|-----------\|-----------\|-----------\|-----------\|-----------\|
<>	144:ef7eb2e8f9f7	139	\| \| DMA \| fPCLK/2 \| fPCLK/4 \| NA \| NA \| fPCLK/2 \| fPCLK/32 \|
<>	144:ef7eb2e8f9f7	140	+--------------------------------------------------------------------------------------------------+
<>	144:ef7eb2e8f9f7	141
<>	144:ef7eb2e8f9f7	142	note:
<>	144:ef7eb2e8f9f7	143	The max SPI frequency depend on SPI data size (8bits, 16bits),
<>	144:ef7eb2e8f9f7	144	SPI mode(2 Lines fullduplex, 2 lines RxOnly, 1 line TX/RX) and Process mode (Polling, IT, DMA).
<>	144:ef7eb2e8f9f7	145
<>	144:ef7eb2e8f9f7	146	note:
<>	144:ef7eb2e8f9f7	147	TX/RX processes are HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_IT() and HAL_SPI_TransmitReceive_DMA()
<>	144:ef7eb2e8f9f7	148	RX processes are HAL_SPI_Receive(), HAL_SPI_Receive_IT() and HAL_SPI_Receive_DMA()
<>	144:ef7eb2e8f9f7	149	TX processes are HAL_SPI_Transmit(), HAL_SPI_Transmit_IT() and HAL_SPI_Transmit_DMA()
<>	144:ef7eb2e8f9f7	150
<>	144:ef7eb2e8f9f7	151	*/
<>	144:ef7eb2e8f9f7	152
<>	144:ef7eb2e8f9f7	153	/* Includes ------------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	154	#include "stm32f1xx_hal.h"
<>	144:ef7eb2e8f9f7	155
<>	144:ef7eb2e8f9f7	156	/** @addtogroup STM32F1xx_HAL_Driver
<>	144:ef7eb2e8f9f7	157	* @{
<>	144:ef7eb2e8f9f7	158	*/
<>	144:ef7eb2e8f9f7	159
<>	144:ef7eb2e8f9f7	160	/** @defgroup SPI SPI
<>	144:ef7eb2e8f9f7	161	* @brief SPI HAL module driver
<>	144:ef7eb2e8f9f7	162	* @{
<>	144:ef7eb2e8f9f7	163	*/
<>	144:ef7eb2e8f9f7	164
<>	144:ef7eb2e8f9f7	165	#ifdef HAL_SPI_MODULE_ENABLED
<>	144:ef7eb2e8f9f7	166
<>	144:ef7eb2e8f9f7	167	/* Private typedef -----------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	168	/* Private define ------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	169	/** @defgroup SPI_Private_Constants SPI Private Constants
<>	144:ef7eb2e8f9f7	170	* @{
<>	144:ef7eb2e8f9f7	171	*/
<>	144:ef7eb2e8f9f7	172	#define SPI_TIMEOUT_VALUE 10
<>	144:ef7eb2e8f9f7	173	/**
<>	144:ef7eb2e8f9f7	174	* @}
<>	144:ef7eb2e8f9f7	175	*/
<>	144:ef7eb2e8f9f7	176
<>	144:ef7eb2e8f9f7	177	/* Private macro -------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	178	/* Private variables ---------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	179	/* Private function prototypes -----------------------------------------------*/
<>	144:ef7eb2e8f9f7	180	/** @defgroup SPI_Private_Functions SPI Private Functions
<>	144:ef7eb2e8f9f7	181	* @{
<>	144:ef7eb2e8f9f7	182	*/
<>	144:ef7eb2e8f9f7	183	static void SPI_TxCloseIRQHandler(SPI_HandleTypeDef *hspi);
<>	144:ef7eb2e8f9f7	184	static void SPI_TxISR(SPI_HandleTypeDef *hspi);
<>	144:ef7eb2e8f9f7	185	static void SPI_RxCloseIRQHandler(SPI_HandleTypeDef *hspi);
<>	144:ef7eb2e8f9f7	186	static void SPI_2LinesRxISR(SPI_HandleTypeDef *hspi);
<>	144:ef7eb2e8f9f7	187	static void SPI_RxISR(SPI_HandleTypeDef *hspi);
<>	144:ef7eb2e8f9f7	188	static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma);
<>	144:ef7eb2e8f9f7	189	static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
<>	144:ef7eb2e8f9f7	190	static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma);
<>	144:ef7eb2e8f9f7	191	static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma);
<>	144:ef7eb2e8f9f7	192	static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma);
<>	144:ef7eb2e8f9f7	193	static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma);
<>	144:ef7eb2e8f9f7	194	static void SPI_DMAError(DMA_HandleTypeDef *hdma);
<>	144:ef7eb2e8f9f7	195	static HAL_StatusTypeDef SPI_WaitOnFlagUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus Status, uint32_t Timeout);
<>	144:ef7eb2e8f9f7	196	/**
<>	144:ef7eb2e8f9f7	197	* @}
<>	144:ef7eb2e8f9f7	198	*/
<>	144:ef7eb2e8f9f7	199
<>	144:ef7eb2e8f9f7	200	/* Exported functions ---------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	201
<>	144:ef7eb2e8f9f7	202	/** @defgroup SPI_Exported_Functions SPI Exported Functions
<>	144:ef7eb2e8f9f7	203	* @{
<>	144:ef7eb2e8f9f7	204	*/
<>	144:ef7eb2e8f9f7	205
<>	144:ef7eb2e8f9f7	206	/** @defgroup SPI_Exported_Functions_Group1 Initialization and de-initialization functions
<>	144:ef7eb2e8f9f7	207	* @brief Initialization and Configuration functions
<>	144:ef7eb2e8f9f7	208	*
<>	144:ef7eb2e8f9f7	209	@verbatim
<>	144:ef7eb2e8f9f7	210	===============================================================================
<>	144:ef7eb2e8f9f7	211	##### Initialization and de-initialization functions #####
<>	144:ef7eb2e8f9f7	212	===============================================================================
<>	144:ef7eb2e8f9f7	213	[..] This subsection provides a set of functions allowing to initialize and
<>	144:ef7eb2e8f9f7	214	de-initialiaze the SPIx peripheral:
<>	144:ef7eb2e8f9f7	215
<>	144:ef7eb2e8f9f7	216	(+) User must implement HAL_SPI_MspInit() function in which he configures
<>	144:ef7eb2e8f9f7	217	all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
<>	144:ef7eb2e8f9f7	218
<>	144:ef7eb2e8f9f7	219	(+) Call the function HAL_SPI_Init() to configure the selected device with
<>	144:ef7eb2e8f9f7	220	the selected configuration:
<>	144:ef7eb2e8f9f7	221	(++) Mode
<>	144:ef7eb2e8f9f7	222	(++) Direction
<>	144:ef7eb2e8f9f7	223	(++) Data Size
<>	144:ef7eb2e8f9f7	224	(++) Clock Polarity and Phase
<>	144:ef7eb2e8f9f7	225	(++) NSS Management
<>	144:ef7eb2e8f9f7	226	(++) BaudRate Prescaler
<>	144:ef7eb2e8f9f7	227	(++) FirstBit
<>	144:ef7eb2e8f9f7	228	(++) TIMode
<>	144:ef7eb2e8f9f7	229	(++) CRC Calculation
<>	144:ef7eb2e8f9f7	230	(++) CRC Polynomial if CRC enabled
<>	144:ef7eb2e8f9f7	231
<>	144:ef7eb2e8f9f7	232	(+) Call the function HAL_SPI_DeInit() to restore the default configuration
<>	144:ef7eb2e8f9f7	233	of the selected SPIx periperal.
<>	144:ef7eb2e8f9f7	234
<>	144:ef7eb2e8f9f7	235	@endverbatim
<>	144:ef7eb2e8f9f7	236	* @{
<>	144:ef7eb2e8f9f7	237	*/
<>	144:ef7eb2e8f9f7	238
<>	144:ef7eb2e8f9f7	239	/**
<>	144:ef7eb2e8f9f7	240	* @brief Initializes the SPI according to the specified parameters
<>	144:ef7eb2e8f9f7	241	* in the SPI_InitTypeDef and create the associated handle.
<>	144:ef7eb2e8f9f7	242	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	243	* the configuration information for SPI module.
<>	144:ef7eb2e8f9f7	244	* @retval HAL status
<>	144:ef7eb2e8f9f7	245	*/
<>	144:ef7eb2e8f9f7	246	__weak HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
<>	144:ef7eb2e8f9f7	247	{
<>	144:ef7eb2e8f9f7	248	/* Check the SPI handle allocation */
<>	144:ef7eb2e8f9f7	249	if(hspi == NULL)
<>	144:ef7eb2e8f9f7	250	{
<>	144:ef7eb2e8f9f7	251	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	252	}
<>	144:ef7eb2e8f9f7	253
<>	144:ef7eb2e8f9f7	254	/* Check the parameters */
<>	144:ef7eb2e8f9f7	255	assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));
<>	144:ef7eb2e8f9f7	256	assert_param(IS_SPI_MODE(hspi->Init.Mode));
<>	144:ef7eb2e8f9f7	257	assert_param(IS_SPI_DIRECTION_MODE(hspi->Init.Direction));
<>	144:ef7eb2e8f9f7	258	assert_param(IS_SPI_DATASIZE(hspi->Init.DataSize));
<>	144:ef7eb2e8f9f7	259	assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity));
<>	144:ef7eb2e8f9f7	260	assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase));
<>	144:ef7eb2e8f9f7	261	assert_param(IS_SPI_NSS(hspi->Init.NSS));
<>	144:ef7eb2e8f9f7	262	assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
<>	144:ef7eb2e8f9f7	263	assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit));
<>	144:ef7eb2e8f9f7	264	assert_param(IS_SPI_TIMODE(hspi->Init.TIMode));
<>	144:ef7eb2e8f9f7	265	assert_param(IS_SPI_CRC_CALCULATION(hspi->Init.CRCCalculation));
<>	144:ef7eb2e8f9f7	266	assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial));
<>	144:ef7eb2e8f9f7	267
<>	144:ef7eb2e8f9f7	268	if(hspi->State == HAL_SPI_STATE_RESET)
<>	144:ef7eb2e8f9f7	269	{
<>	144:ef7eb2e8f9f7	270	/* Allocate lock resource and initialize it */
<>	144:ef7eb2e8f9f7	271	hspi->Lock = HAL_UNLOCKED;
<>	144:ef7eb2e8f9f7	272
<>	144:ef7eb2e8f9f7	273	/* Init the low level hardware : GPIO, CLOCK, NVIC... */
<>	144:ef7eb2e8f9f7	274	HAL_SPI_MspInit(hspi);
<>	144:ef7eb2e8f9f7	275	}
<>	144:ef7eb2e8f9f7	276
<>	144:ef7eb2e8f9f7	277	hspi->State = HAL_SPI_STATE_BUSY;
<>	144:ef7eb2e8f9f7	278
<>	144:ef7eb2e8f9f7	279	/* Disble the selected SPI peripheral */
<>	144:ef7eb2e8f9f7	280	__HAL_SPI_DISABLE(hspi);
<>	144:ef7eb2e8f9f7	281
<>	144:ef7eb2e8f9f7	282	/----------------------- SPIx CR1 & CR2 Configuration ---------------------/
<>	144:ef7eb2e8f9f7	283	/* Configure : SPI Mode, Communication Mode, Data size, Clock polarity and phase, NSS management,
<>	144:ef7eb2e8f9f7	284	Communication speed, First bit and CRC calculation state */
<>	144:ef7eb2e8f9f7	285	WRITE_REG(hspi->Instance->CR1, (hspi->Init.Mode \| hspi->Init.Direction \| hspi->Init.DataSize \|
<>	144:ef7eb2e8f9f7	286	hspi->Init.CLKPolarity \| hspi->Init.CLKPhase \| (hspi->Init.NSS & SPI_CR1_SSM) \|
<>	144:ef7eb2e8f9f7	287	hspi->Init.BaudRatePrescaler \| hspi->Init.FirstBit \| hspi->Init.CRCCalculation) );
<>	144:ef7eb2e8f9f7	288
<>	144:ef7eb2e8f9f7	289	/* Configure : NSS management */
<>	144:ef7eb2e8f9f7	290	WRITE_REG(hspi->Instance->CR2, (((hspi->Init.NSS >> 16) & SPI_CR2_SSOE) \| hspi->Init.TIMode));
<>	144:ef7eb2e8f9f7	291
<>	144:ef7eb2e8f9f7	292	/---------------------------- SPIx CRCPOLY Configuration ------------------/
<>	144:ef7eb2e8f9f7	293	/* Configure : CRC Polynomial */
<>	144:ef7eb2e8f9f7	294	WRITE_REG(hspi->Instance->CRCPR, hspi->Init.CRCPolynomial);
<>	144:ef7eb2e8f9f7	295
<>	144:ef7eb2e8f9f7	296	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
<>	144:ef7eb2e8f9f7	297	hspi->State = HAL_SPI_STATE_READY;
<>	144:ef7eb2e8f9f7	298
<>	144:ef7eb2e8f9f7	299	return HAL_OK;
<>	144:ef7eb2e8f9f7	300	}
<>	144:ef7eb2e8f9f7	301
<>	144:ef7eb2e8f9f7	302	/**
<>	144:ef7eb2e8f9f7	303	* @brief DeInitializes the SPI peripheral
<>	144:ef7eb2e8f9f7	304	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	305	* the configuration information for SPI module.
<>	144:ef7eb2e8f9f7	306	* @retval HAL status
<>	144:ef7eb2e8f9f7	307	*/
<>	144:ef7eb2e8f9f7	308	HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi)
<>	144:ef7eb2e8f9f7	309	{
<>	144:ef7eb2e8f9f7	310	/* Check the SPI handle allocation */
<>	144:ef7eb2e8f9f7	311	if(hspi == NULL)
<>	144:ef7eb2e8f9f7	312	{
<>	144:ef7eb2e8f9f7	313	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	314	}
<>	144:ef7eb2e8f9f7	315
<>	144:ef7eb2e8f9f7	316	hspi->State = HAL_SPI_STATE_BUSY;
<>	144:ef7eb2e8f9f7	317
<>	144:ef7eb2e8f9f7	318	/* Disable the SPI Peripheral Clock */
<>	144:ef7eb2e8f9f7	319	__HAL_SPI_DISABLE(hspi);
<>	144:ef7eb2e8f9f7	320
<>	144:ef7eb2e8f9f7	321	/* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
<>	144:ef7eb2e8f9f7	322	HAL_SPI_MspDeInit(hspi);
<>	144:ef7eb2e8f9f7	323
<>	144:ef7eb2e8f9f7	324	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
<>	144:ef7eb2e8f9f7	325	hspi->State = HAL_SPI_STATE_RESET;
<>	144:ef7eb2e8f9f7	326
<>	144:ef7eb2e8f9f7	327	/* Release Lock */
<>	144:ef7eb2e8f9f7	328	__HAL_UNLOCK(hspi);
<>	144:ef7eb2e8f9f7	329
<>	144:ef7eb2e8f9f7	330	return HAL_OK;
<>	144:ef7eb2e8f9f7	331	}
<>	144:ef7eb2e8f9f7	332
<>	144:ef7eb2e8f9f7	333	/**
<>	144:ef7eb2e8f9f7	334	* @brief SPI MSP Init
<>	144:ef7eb2e8f9f7	335	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	336	* the configuration information for SPI module.
<>	144:ef7eb2e8f9f7	337	* @retval None
<>	144:ef7eb2e8f9f7	338	*/
<>	144:ef7eb2e8f9f7	339	__weak void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi)
<>	144:ef7eb2e8f9f7	340	{
<>	144:ef7eb2e8f9f7	341	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	342	UNUSED(hspi);
<>	144:ef7eb2e8f9f7	343	/* NOTE : This function Should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	344	the HAL_SPI_MspInit could be implenetd in the user file
<>	144:ef7eb2e8f9f7	345	*/
<>	144:ef7eb2e8f9f7	346	}
<>	144:ef7eb2e8f9f7	347
<>	144:ef7eb2e8f9f7	348	/**
<>	144:ef7eb2e8f9f7	349	* @brief SPI MSP DeInit
<>	144:ef7eb2e8f9f7	350	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	351	* the configuration information for SPI module.
<>	144:ef7eb2e8f9f7	352	* @retval None
<>	144:ef7eb2e8f9f7	353	*/
<>	144:ef7eb2e8f9f7	354	__weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi)
<>	144:ef7eb2e8f9f7	355	{
<>	144:ef7eb2e8f9f7	356	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	357	UNUSED(hspi);
<>	144:ef7eb2e8f9f7	358	/* NOTE : This function Should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	359	the HAL_SPI_MspDeInit could be implenetd in the user file
<>	144:ef7eb2e8f9f7	360	*/
<>	144:ef7eb2e8f9f7	361	}
<>	144:ef7eb2e8f9f7	362
<>	144:ef7eb2e8f9f7	363	/**
<>	144:ef7eb2e8f9f7	364	* @}
<>	144:ef7eb2e8f9f7	365	*/
<>	144:ef7eb2e8f9f7	366
<>	144:ef7eb2e8f9f7	367	/** @defgroup SPI_Exported_Functions_Group2 IO operation functions
<>	144:ef7eb2e8f9f7	368	* @brief Data transfers functions
<>	144:ef7eb2e8f9f7	369	*
<>	144:ef7eb2e8f9f7	370	@verbatim
<>	144:ef7eb2e8f9f7	371	==============================================================================
<>	144:ef7eb2e8f9f7	372	##### IO operation functions #####
<>	144:ef7eb2e8f9f7	373	===============================================================================
<>	144:ef7eb2e8f9f7	374	This subsection provides a set of functions allowing to manage the SPI
<>	144:ef7eb2e8f9f7	375	data transfers.
<>	144:ef7eb2e8f9f7	376
<>	144:ef7eb2e8f9f7	377	[..] The SPI supports master and slave mode :
<>	144:ef7eb2e8f9f7	378
<>	144:ef7eb2e8f9f7	379	(#) There are two modes of transfer:
<>	144:ef7eb2e8f9f7	380	(++) Blocking mode: The communication is performed in polling mode.
<>	144:ef7eb2e8f9f7	381	The HAL status of all data processing is returned by the same function
<>	144:ef7eb2e8f9f7	382	after finishing transfer.
<>	144:ef7eb2e8f9f7	383	(++) No-Blocking mode: The communication is performed using Interrupts
<>	144:ef7eb2e8f9f7	384	or DMA, These APIs return the HAL status.
<>	144:ef7eb2e8f9f7	385	The end of the data processing will be indicated through the
<>	144:ef7eb2e8f9f7	386	dedicated SPI IRQ when using Interrupt mode or the DMA IRQ when
<>	144:ef7eb2e8f9f7	387	using DMA mode.
<>	144:ef7eb2e8f9f7	388	The HAL_SPI_TxCpltCallback(), HAL_SPI_RxCpltCallback() and HAL_SPI_TxRxCpltCallback() user callbacks
<>	144:ef7eb2e8f9f7	389	will be executed respectivelly at the end of the transmit or Receive process
<>	144:ef7eb2e8f9f7	390	The HAL_SPI_ErrorCallback()user callback will be executed when a communication error is detected
<>	144:ef7eb2e8f9f7	391
<>	144:ef7eb2e8f9f7	392	(#) APIs provided for these 2 transfer modes (Blocking mode or Non blocking mode using either Interrupt or DMA)
<>	144:ef7eb2e8f9f7	393	exist for 1Line (simplex) and 2Lines (full duplex) modes.
<>	144:ef7eb2e8f9f7	394
<>	144:ef7eb2e8f9f7	395	@endverbatim
<>	144:ef7eb2e8f9f7	396	* @{
<>	144:ef7eb2e8f9f7	397	*/
<>	144:ef7eb2e8f9f7	398
<>	144:ef7eb2e8f9f7	399	/**
<>	144:ef7eb2e8f9f7	400	* @brief Transmit an amount of data in blocking mode
<>	144:ef7eb2e8f9f7	401	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	402	* the configuration information for SPI module.
<>	144:ef7eb2e8f9f7	403	* @param pData: pointer to data buffer
<>	144:ef7eb2e8f9f7	404	* @param Size: amount of data to be sent
<>	144:ef7eb2e8f9f7	405	* @param Timeout: Timeout duration
<>	144:ef7eb2e8f9f7	406	* @retval HAL status
<>	144:ef7eb2e8f9f7	407	*/
<>	144:ef7eb2e8f9f7	408	HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size, uint32_t Timeout)
<>	144:ef7eb2e8f9f7	409	{
<>	144:ef7eb2e8f9f7	410
<>	144:ef7eb2e8f9f7	411	if(hspi->State == HAL_SPI_STATE_READY)
<>	144:ef7eb2e8f9f7	412	{
<>	144:ef7eb2e8f9f7	413	if((pData == NULL ) \|\| (Size == 0))
<>	144:ef7eb2e8f9f7	414	{
<>	144:ef7eb2e8f9f7	415	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	416	}
<>	144:ef7eb2e8f9f7	417
<>	144:ef7eb2e8f9f7	418	/* Check the parameters */
<>	144:ef7eb2e8f9f7	419	assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
<>	144:ef7eb2e8f9f7	420
<>	144:ef7eb2e8f9f7	421	/* Process Locked */
<>	144:ef7eb2e8f9f7	422	__HAL_LOCK(hspi);
<>	144:ef7eb2e8f9f7	423
<>	144:ef7eb2e8f9f7	424	/* Configure communication */
<>	144:ef7eb2e8f9f7	425	hspi->State = HAL_SPI_STATE_BUSY_TX;
<>	144:ef7eb2e8f9f7	426	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
<>	144:ef7eb2e8f9f7	427
<>	144:ef7eb2e8f9f7	428	hspi->pTxBuffPtr = pData;
<>	144:ef7eb2e8f9f7	429	hspi->TxXferSize = Size;
<>	144:ef7eb2e8f9f7	430	hspi->TxXferCount = Size;
<>	144:ef7eb2e8f9f7	431
<>	144:ef7eb2e8f9f7	432	/Init field not used in handle to zero /
<>	144:ef7eb2e8f9f7	433	hspi->TxISR = 0;
<>	144:ef7eb2e8f9f7	434	hspi->RxISR = 0;
<>	144:ef7eb2e8f9f7	435	hspi->pRxBuffPtr = NULL;
<>	144:ef7eb2e8f9f7	436	hspi->RxXferSize = 0;
<>	144:ef7eb2e8f9f7	437	hspi->RxXferCount = 0;
<>	144:ef7eb2e8f9f7	438
<>	144:ef7eb2e8f9f7	439	/* Reset CRC Calculation */
<>	144:ef7eb2e8f9f7	440	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<>	144:ef7eb2e8f9f7	441	{
<>	144:ef7eb2e8f9f7	442	SPI_RESET_CRC(hspi);
<>	144:ef7eb2e8f9f7	443	}
<>	144:ef7eb2e8f9f7	444
<>	144:ef7eb2e8f9f7	445	if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
<>	144:ef7eb2e8f9f7	446	{
<>	144:ef7eb2e8f9f7	447	/* Configure communication direction : 1Line */
<>	144:ef7eb2e8f9f7	448	SPI_1LINE_TX(hspi);
<>	144:ef7eb2e8f9f7	449	}
<>	144:ef7eb2e8f9f7	450
<>	144:ef7eb2e8f9f7	451	/* Check if the SPI is already enabled */
<>	144:ef7eb2e8f9f7	452	if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
<>	144:ef7eb2e8f9f7	453	{
<>	144:ef7eb2e8f9f7	454	/* Enable SPI peripheral */
<>	144:ef7eb2e8f9f7	455	__HAL_SPI_ENABLE(hspi);
<>	144:ef7eb2e8f9f7	456	}
<>	144:ef7eb2e8f9f7	457
<>	144:ef7eb2e8f9f7	458	/* Transmit data in 8 Bit mode */
<>	144:ef7eb2e8f9f7	459	if(hspi->Init.DataSize == SPI_DATASIZE_8BIT)
<>	144:ef7eb2e8f9f7	460	{
<>	144:ef7eb2e8f9f7	461	if((hspi->Init.Mode == SPI_MODE_SLAVE)\|\| (hspi->TxXferCount == 0x01))
<>	144:ef7eb2e8f9f7	462	{
<>	144:ef7eb2e8f9f7	463	hspi->Instance->DR = (*hspi->pTxBuffPtr++);
<>	144:ef7eb2e8f9f7	464	hspi->TxXferCount--;
<>	144:ef7eb2e8f9f7	465	}
<>	144:ef7eb2e8f9f7	466
<>	144:ef7eb2e8f9f7	467	while(hspi->TxXferCount > 0)
<>	144:ef7eb2e8f9f7	468	{
<>	144:ef7eb2e8f9f7	469	/* Wait until TXE flag is set to send data */
<>	144:ef7eb2e8f9f7	470	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, Timeout) != HAL_OK)
<>	144:ef7eb2e8f9f7	471	{
<>	144:ef7eb2e8f9f7	472	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	473	}
<>	144:ef7eb2e8f9f7	474	hspi->Instance->DR = (*hspi->pTxBuffPtr++);
<>	144:ef7eb2e8f9f7	475	hspi->TxXferCount--;
<>	144:ef7eb2e8f9f7	476	}
<>	144:ef7eb2e8f9f7	477	/* Enable CRC Transmission */
<>	144:ef7eb2e8f9f7	478	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<>	144:ef7eb2e8f9f7	479	{
<>	144:ef7eb2e8f9f7	480	SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
<>	144:ef7eb2e8f9f7	481	}
<>	144:ef7eb2e8f9f7	482	}
<>	144:ef7eb2e8f9f7	483	/* Transmit data in 16 Bit mode */
<>	144:ef7eb2e8f9f7	484	else
<>	144:ef7eb2e8f9f7	485	{
<>	144:ef7eb2e8f9f7	486	if((hspi->Init.Mode == SPI_MODE_SLAVE) \|\| (hspi->TxXferCount == 0x01))
<>	144:ef7eb2e8f9f7	487	{
<>	144:ef7eb2e8f9f7	488	hspi->Instance->DR = ((uint16_t)hspi->pTxBuffPtr);
<>	144:ef7eb2e8f9f7	489	hspi->pTxBuffPtr+=2;
<>	144:ef7eb2e8f9f7	490	hspi->TxXferCount--;
<>	144:ef7eb2e8f9f7	491	}
<>	144:ef7eb2e8f9f7	492
<>	144:ef7eb2e8f9f7	493	while(hspi->TxXferCount > 0)
<>	144:ef7eb2e8f9f7	494	{
<>	144:ef7eb2e8f9f7	495	/* Wait until TXE flag is set to send data */
<>	144:ef7eb2e8f9f7	496	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, Timeout) != HAL_OK)
<>	144:ef7eb2e8f9f7	497	{
<>	144:ef7eb2e8f9f7	498	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	499	}
<>	144:ef7eb2e8f9f7	500	hspi->Instance->DR = ((uint16_t)hspi->pTxBuffPtr);
<>	144:ef7eb2e8f9f7	501	hspi->pTxBuffPtr+=2;
<>	144:ef7eb2e8f9f7	502	hspi->TxXferCount--;
<>	144:ef7eb2e8f9f7	503	}
<>	144:ef7eb2e8f9f7	504	/* Enable CRC Transmission */
<>	144:ef7eb2e8f9f7	505	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<>	144:ef7eb2e8f9f7	506	{
<>	144:ef7eb2e8f9f7	507	SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
<>	144:ef7eb2e8f9f7	508	}
<>	144:ef7eb2e8f9f7	509	}
<>	144:ef7eb2e8f9f7	510
<>	144:ef7eb2e8f9f7	511	/* Wait until TXE flag is set to send data */
<>	144:ef7eb2e8f9f7	512	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, Timeout) != HAL_OK)
<>	144:ef7eb2e8f9f7	513	{
<>	144:ef7eb2e8f9f7	514	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
<>	144:ef7eb2e8f9f7	515	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	516	}
<>	144:ef7eb2e8f9f7	517
<>	144:ef7eb2e8f9f7	518	/* Wait until Busy flag is reset before disabling SPI */
<>	144:ef7eb2e8f9f7	519	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_BSY, SET, Timeout) != HAL_OK)
<>	144:ef7eb2e8f9f7	520	{
<>	144:ef7eb2e8f9f7	521	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
<>	144:ef7eb2e8f9f7	522	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	523	}
<>	144:ef7eb2e8f9f7	524
<>	144:ef7eb2e8f9f7	525	/* Clear OVERUN flag in 2 Lines communication mode because received is not read */
<>	144:ef7eb2e8f9f7	526	if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
<>	144:ef7eb2e8f9f7	527	{
<>	144:ef7eb2e8f9f7	528	__HAL_SPI_CLEAR_OVRFLAG(hspi);
<>	144:ef7eb2e8f9f7	529	}
<>	144:ef7eb2e8f9f7	530
<>	144:ef7eb2e8f9f7	531	hspi->State = HAL_SPI_STATE_READY;
<>	144:ef7eb2e8f9f7	532
<>	144:ef7eb2e8f9f7	533	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	534	__HAL_UNLOCK(hspi);
<>	144:ef7eb2e8f9f7	535
<>	144:ef7eb2e8f9f7	536	return HAL_OK;
<>	144:ef7eb2e8f9f7	537	}
<>	144:ef7eb2e8f9f7	538	else
<>	144:ef7eb2e8f9f7	539	{
<>	144:ef7eb2e8f9f7	540	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	541	}
<>	144:ef7eb2e8f9f7	542	}
<>	144:ef7eb2e8f9f7	543
<>	144:ef7eb2e8f9f7	544	/**
<>	144:ef7eb2e8f9f7	545	* @brief Receive an amount of data in blocking mode
<>	144:ef7eb2e8f9f7	546	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	547	* the configuration information for SPI module.
<>	144:ef7eb2e8f9f7	548	* @param pData: pointer to data buffer
<>	144:ef7eb2e8f9f7	549	* @param Size: amount of data to be sent
<>	144:ef7eb2e8f9f7	550	* @param Timeout: Timeout duration
<>	144:ef7eb2e8f9f7	551	* @retval HAL status
<>	144:ef7eb2e8f9f7	552	*/
<>	144:ef7eb2e8f9f7	553	HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size, uint32_t Timeout)
<>	144:ef7eb2e8f9f7	554	{
<>	144:ef7eb2e8f9f7	555	__IO uint16_t tmpreg = 0;
<>	144:ef7eb2e8f9f7	556
<>	144:ef7eb2e8f9f7	557	if(hspi->State == HAL_SPI_STATE_READY)
<>	144:ef7eb2e8f9f7	558	{
<>	144:ef7eb2e8f9f7	559	if((pData == NULL ) \|\| (Size == 0))
<>	144:ef7eb2e8f9f7	560	{
<>	144:ef7eb2e8f9f7	561	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	562	}
<>	144:ef7eb2e8f9f7	563
<>	144:ef7eb2e8f9f7	564	/* Process Locked */
<>	144:ef7eb2e8f9f7	565	__HAL_LOCK(hspi);
<>	144:ef7eb2e8f9f7	566
<>	144:ef7eb2e8f9f7	567	/* Configure communication */
<>	144:ef7eb2e8f9f7	568	hspi->State = HAL_SPI_STATE_BUSY_RX;
<>	144:ef7eb2e8f9f7	569	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
<>	144:ef7eb2e8f9f7	570
<>	144:ef7eb2e8f9f7	571	hspi->pRxBuffPtr = pData;
<>	144:ef7eb2e8f9f7	572	hspi->RxXferSize = Size;
<>	144:ef7eb2e8f9f7	573	hspi->RxXferCount = Size;
<>	144:ef7eb2e8f9f7	574
<>	144:ef7eb2e8f9f7	575	/Init field not used in handle to zero /
<>	144:ef7eb2e8f9f7	576	hspi->RxISR = 0;
<>	144:ef7eb2e8f9f7	577	hspi->TxISR = 0;
<>	144:ef7eb2e8f9f7	578	hspi->pTxBuffPtr = NULL;
<>	144:ef7eb2e8f9f7	579	hspi->TxXferSize = 0;
<>	144:ef7eb2e8f9f7	580	hspi->TxXferCount = 0;
<>	144:ef7eb2e8f9f7	581
<>	144:ef7eb2e8f9f7	582	/* Configure communication direction : 1Line */
<>	144:ef7eb2e8f9f7	583	if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
<>	144:ef7eb2e8f9f7	584	{
<>	144:ef7eb2e8f9f7	585	SPI_1LINE_RX(hspi);
<>	144:ef7eb2e8f9f7	586	}
<>	144:ef7eb2e8f9f7	587
<>	144:ef7eb2e8f9f7	588	/* Reset CRC Calculation */
<>	144:ef7eb2e8f9f7	589	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<>	144:ef7eb2e8f9f7	590	{
<>	144:ef7eb2e8f9f7	591	SPI_RESET_CRC(hspi);
<>	144:ef7eb2e8f9f7	592	}
<>	144:ef7eb2e8f9f7	593
<>	144:ef7eb2e8f9f7	594	if((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))
<>	144:ef7eb2e8f9f7	595	{
<>	144:ef7eb2e8f9f7	596	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	597	__HAL_UNLOCK(hspi);
<>	144:ef7eb2e8f9f7	598
<>	144:ef7eb2e8f9f7	599	/* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
<>	144:ef7eb2e8f9f7	600	return HAL_SPI_TransmitReceive(hspi, pData, pData, Size, Timeout);
<>	144:ef7eb2e8f9f7	601	}
<>	144:ef7eb2e8f9f7	602
<>	144:ef7eb2e8f9f7	603	/* Check if the SPI is already enabled */
<>	144:ef7eb2e8f9f7	604	if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
<>	144:ef7eb2e8f9f7	605	{
<>	144:ef7eb2e8f9f7	606	/* Enable SPI peripheral */
<>	144:ef7eb2e8f9f7	607	__HAL_SPI_ENABLE(hspi);
<>	144:ef7eb2e8f9f7	608	}
<>	144:ef7eb2e8f9f7	609
<>	144:ef7eb2e8f9f7	610	/* Receive data in 8 Bit mode */
<>	144:ef7eb2e8f9f7	611	if(hspi->Init.DataSize == SPI_DATASIZE_8BIT)
<>	144:ef7eb2e8f9f7	612	{
<>	144:ef7eb2e8f9f7	613	while(hspi->RxXferCount > 1)
<>	144:ef7eb2e8f9f7	614	{
<>	144:ef7eb2e8f9f7	615	/* Wait until RXNE flag is set */
<>	144:ef7eb2e8f9f7	616	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
<>	144:ef7eb2e8f9f7	617	{
<>	144:ef7eb2e8f9f7	618	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	619	}
<>	144:ef7eb2e8f9f7	620
<>	144:ef7eb2e8f9f7	621	(*hspi->pRxBuffPtr++) = hspi->Instance->DR;
<>	144:ef7eb2e8f9f7	622	hspi->RxXferCount--;
<>	144:ef7eb2e8f9f7	623	}
<>	144:ef7eb2e8f9f7	624	/* Enable CRC Reception */
<>	144:ef7eb2e8f9f7	625	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<>	144:ef7eb2e8f9f7	626	{
<>	144:ef7eb2e8f9f7	627	SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
<>	144:ef7eb2e8f9f7	628	}
<>	144:ef7eb2e8f9f7	629	}
<>	144:ef7eb2e8f9f7	630	/* Receive data in 16 Bit mode */
<>	144:ef7eb2e8f9f7	631	else
<>	144:ef7eb2e8f9f7	632	{
<>	144:ef7eb2e8f9f7	633	while(hspi->RxXferCount > 1)
<>	144:ef7eb2e8f9f7	634	{
<>	144:ef7eb2e8f9f7	635	/* Wait until RXNE flag is set to read data */
<>	144:ef7eb2e8f9f7	636	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
<>	144:ef7eb2e8f9f7	637	{
<>	144:ef7eb2e8f9f7	638	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	639	}
<>	144:ef7eb2e8f9f7	640
<>	144:ef7eb2e8f9f7	641	((uint16_t)hspi->pRxBuffPtr) = hspi->Instance->DR;
<>	144:ef7eb2e8f9f7	642	hspi->pRxBuffPtr+=2;
<>	144:ef7eb2e8f9f7	643	hspi->RxXferCount--;
<>	144:ef7eb2e8f9f7	644	}
<>	144:ef7eb2e8f9f7	645	/* Enable CRC Reception */
<>	144:ef7eb2e8f9f7	646	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<>	144:ef7eb2e8f9f7	647	{
<>	144:ef7eb2e8f9f7	648	SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
<>	144:ef7eb2e8f9f7	649	}
<>	144:ef7eb2e8f9f7	650	}
<>	144:ef7eb2e8f9f7	651
<>	144:ef7eb2e8f9f7	652	/* Wait until RXNE flag is set */
<>	144:ef7eb2e8f9f7	653	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
<>	144:ef7eb2e8f9f7	654	{
<>	144:ef7eb2e8f9f7	655	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	656	}
<>	144:ef7eb2e8f9f7	657
<>	144:ef7eb2e8f9f7	658	/* Receive last data in 8 Bit mode */
<>	144:ef7eb2e8f9f7	659	if(hspi->Init.DataSize == SPI_DATASIZE_8BIT)
<>	144:ef7eb2e8f9f7	660	{
<>	144:ef7eb2e8f9f7	661	(*hspi->pRxBuffPtr++) = hspi->Instance->DR;
<>	144:ef7eb2e8f9f7	662	}
<>	144:ef7eb2e8f9f7	663	/* Receive last data in 16 Bit mode */
<>	144:ef7eb2e8f9f7	664	else
<>	144:ef7eb2e8f9f7	665	{
<>	144:ef7eb2e8f9f7	666	((uint16_t)hspi->pRxBuffPtr) = hspi->Instance->DR;
<>	144:ef7eb2e8f9f7	667	hspi->pRxBuffPtr+=2;
<>	144:ef7eb2e8f9f7	668	}
<>	144:ef7eb2e8f9f7	669	hspi->RxXferCount--;
<>	144:ef7eb2e8f9f7	670
<>	144:ef7eb2e8f9f7	671	/* If CRC computation is enabled */
<>	144:ef7eb2e8f9f7	672	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<>	144:ef7eb2e8f9f7	673	{
<>	144:ef7eb2e8f9f7	674	/* Wait until RXNE flag is set: CRC Received */
<>	144:ef7eb2e8f9f7	675	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
<>	144:ef7eb2e8f9f7	676	{
<>	144:ef7eb2e8f9f7	677	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
<>	144:ef7eb2e8f9f7	678	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	679	}
<>	144:ef7eb2e8f9f7	680
<>	144:ef7eb2e8f9f7	681	/* Read CRC to clear RXNE flag */
<>	144:ef7eb2e8f9f7	682	tmpreg = hspi->Instance->DR;
<>	144:ef7eb2e8f9f7	683	UNUSED(tmpreg);
<>	144:ef7eb2e8f9f7	684	}
<>	144:ef7eb2e8f9f7	685
<>	144:ef7eb2e8f9f7	686	if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)\|\|(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
<>	144:ef7eb2e8f9f7	687	{
<>	144:ef7eb2e8f9f7	688	/* Disable SPI peripheral */
<>	144:ef7eb2e8f9f7	689	__HAL_SPI_DISABLE(hspi);
<>	144:ef7eb2e8f9f7	690	}
<>	144:ef7eb2e8f9f7	691
<>	144:ef7eb2e8f9f7	692	hspi->State = HAL_SPI_STATE_READY;
<>	144:ef7eb2e8f9f7	693
<>	144:ef7eb2e8f9f7	694	/* Check if CRC error occurred */
<>	144:ef7eb2e8f9f7	695	if((hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET))
<>	144:ef7eb2e8f9f7	696	{
<>	144:ef7eb2e8f9f7	697	/* Check if CRC error is valid or not (workaround to be applied or not) */
<>	144:ef7eb2e8f9f7	698	if (SPI_ISCRCErrorValid(hspi) == SPI_VALID_CRC_ERROR)
<>	144:ef7eb2e8f9f7	699	{
<>	144:ef7eb2e8f9f7	700	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
<>	144:ef7eb2e8f9f7	701
<>	144:ef7eb2e8f9f7	702	/* Reset CRC Calculation */
<>	144:ef7eb2e8f9f7	703	SPI_RESET_CRC(hspi);
<>	144:ef7eb2e8f9f7	704
<>	144:ef7eb2e8f9f7	705	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	706	__HAL_UNLOCK(hspi);
<>	144:ef7eb2e8f9f7	707
<>	144:ef7eb2e8f9f7	708	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	709	}
<>	144:ef7eb2e8f9f7	710	else
<>	144:ef7eb2e8f9f7	711	{
<>	144:ef7eb2e8f9f7	712	__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
<>	144:ef7eb2e8f9f7	713	}
<>	144:ef7eb2e8f9f7	714	}
<>	144:ef7eb2e8f9f7	715
<>	144:ef7eb2e8f9f7	716	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	717	__HAL_UNLOCK(hspi);
<>	144:ef7eb2e8f9f7	718
<>	144:ef7eb2e8f9f7	719	return HAL_OK;
<>	144:ef7eb2e8f9f7	720	}
<>	144:ef7eb2e8f9f7	721	else
<>	144:ef7eb2e8f9f7	722	{
<>	144:ef7eb2e8f9f7	723	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	724	}
<>	144:ef7eb2e8f9f7	725	}
<>	144:ef7eb2e8f9f7	726
<>	144:ef7eb2e8f9f7	727	/**
<>	144:ef7eb2e8f9f7	728	* @brief Transmit and Receive an amount of data in blocking mode
<>	144:ef7eb2e8f9f7	729	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	730	* the configuration information for SPI module.
<>	144:ef7eb2e8f9f7	731	* @param pTxData: pointer to transmission data buffer
<>	144:ef7eb2e8f9f7	732	* @param pRxData: pointer to reception data buffer to be
<>	144:ef7eb2e8f9f7	733	* @param Size: amount of data to be sent
<>	144:ef7eb2e8f9f7	734	* @param Timeout: Timeout duration
<>	144:ef7eb2e8f9f7	735	* @retval HAL status
<>	144:ef7eb2e8f9f7	736	*/
<>	144:ef7eb2e8f9f7	737	HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef hspi, uint8_t pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
<>	144:ef7eb2e8f9f7	738	{
<>	144:ef7eb2e8f9f7	739	__IO uint16_t tmpreg = 0;
<>	144:ef7eb2e8f9f7	740
<>	144:ef7eb2e8f9f7	741	if((hspi->State == HAL_SPI_STATE_READY) \|\| (hspi->State == HAL_SPI_STATE_BUSY_RX))
<>	144:ef7eb2e8f9f7	742	{
<>	144:ef7eb2e8f9f7	743	if((pTxData == NULL ) \|\| (pRxData == NULL ) \|\| (Size == 0))
<>	144:ef7eb2e8f9f7	744	{
<>	144:ef7eb2e8f9f7	745	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	746	}
<>	144:ef7eb2e8f9f7	747
<>	144:ef7eb2e8f9f7	748	/* Check the parameters */
<>	144:ef7eb2e8f9f7	749	assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
<>	144:ef7eb2e8f9f7	750
<>	144:ef7eb2e8f9f7	751	/* Process Locked */
<>	144:ef7eb2e8f9f7	752	__HAL_LOCK(hspi);
<>	144:ef7eb2e8f9f7	753
<>	144:ef7eb2e8f9f7	754	/* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
<>	144:ef7eb2e8f9f7	755	if(hspi->State == HAL_SPI_STATE_READY)
<>	144:ef7eb2e8f9f7	756	{
<>	144:ef7eb2e8f9f7	757	hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
<>	144:ef7eb2e8f9f7	758	}
<>	144:ef7eb2e8f9f7	759
<>	144:ef7eb2e8f9f7	760	/* Configure communication */
<>	144:ef7eb2e8f9f7	761	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
<>	144:ef7eb2e8f9f7	762
<>	144:ef7eb2e8f9f7	763	hspi->pRxBuffPtr = pRxData;
<>	144:ef7eb2e8f9f7	764	hspi->RxXferSize = Size;
<>	144:ef7eb2e8f9f7	765	hspi->RxXferCount = Size;
<>	144:ef7eb2e8f9f7	766
<>	144:ef7eb2e8f9f7	767	hspi->pTxBuffPtr = pTxData;
<>	144:ef7eb2e8f9f7	768	hspi->TxXferSize = Size;
<>	144:ef7eb2e8f9f7	769	hspi->TxXferCount = Size;
<>	144:ef7eb2e8f9f7	770
<>	144:ef7eb2e8f9f7	771	/Init field not used in handle to zero /
<>	144:ef7eb2e8f9f7	772	hspi->RxISR = 0;
<>	144:ef7eb2e8f9f7	773	hspi->TxISR = 0;
<>	144:ef7eb2e8f9f7	774
<>	144:ef7eb2e8f9f7	775	/* Reset CRC Calculation */
<>	144:ef7eb2e8f9f7	776	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<>	144:ef7eb2e8f9f7	777	{
<>	144:ef7eb2e8f9f7	778	SPI_RESET_CRC(hspi);
<>	144:ef7eb2e8f9f7	779	}
<>	144:ef7eb2e8f9f7	780
<>	144:ef7eb2e8f9f7	781	/* Check if the SPI is already enabled */
<>	144:ef7eb2e8f9f7	782	if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
<>	144:ef7eb2e8f9f7	783	{
<>	144:ef7eb2e8f9f7	784	/* Enable SPI peripheral */
<>	144:ef7eb2e8f9f7	785	__HAL_SPI_ENABLE(hspi);
<>	144:ef7eb2e8f9f7	786	}
<>	144:ef7eb2e8f9f7	787
<>	144:ef7eb2e8f9f7	788	/* Transmit and Receive data in 16 Bit mode */
<>	144:ef7eb2e8f9f7	789	if(hspi->Init.DataSize == SPI_DATASIZE_16BIT)
<>	144:ef7eb2e8f9f7	790	{
<>	144:ef7eb2e8f9f7	791	if((hspi->Init.Mode == SPI_MODE_SLAVE) \|\| ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->TxXferCount == 0x01)))
<>	144:ef7eb2e8f9f7	792	{
<>	144:ef7eb2e8f9f7	793	hspi->Instance->DR = ((uint16_t)hspi->pTxBuffPtr);
<>	144:ef7eb2e8f9f7	794	hspi->pTxBuffPtr+=2;
<>	144:ef7eb2e8f9f7	795	hspi->TxXferCount--;
<>	144:ef7eb2e8f9f7	796	}
<>	144:ef7eb2e8f9f7	797	if(hspi->TxXferCount == 0)
<>	144:ef7eb2e8f9f7	798	{
<>	144:ef7eb2e8f9f7	799	/* Enable CRC Transmission */
<>	144:ef7eb2e8f9f7	800	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<>	144:ef7eb2e8f9f7	801	{
<>	144:ef7eb2e8f9f7	802	SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
<>	144:ef7eb2e8f9f7	803	}
<>	144:ef7eb2e8f9f7	804
<>	144:ef7eb2e8f9f7	805	/* Wait until RXNE flag is set */
<>	144:ef7eb2e8f9f7	806	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
<>	144:ef7eb2e8f9f7	807	{
<>	144:ef7eb2e8f9f7	808	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	809	}
<>	144:ef7eb2e8f9f7	810
<>	144:ef7eb2e8f9f7	811	((uint16_t)hspi->pRxBuffPtr) = hspi->Instance->DR;
<>	144:ef7eb2e8f9f7	812	hspi->pRxBuffPtr+=2;
<>	144:ef7eb2e8f9f7	813	hspi->RxXferCount--;
<>	144:ef7eb2e8f9f7	814	}
<>	144:ef7eb2e8f9f7	815	else
<>	144:ef7eb2e8f9f7	816	{
<>	144:ef7eb2e8f9f7	817	while(hspi->TxXferCount > 0)
<>	144:ef7eb2e8f9f7	818	{
<>	144:ef7eb2e8f9f7	819	/* Wait until TXE flag is set to send data */
<>	144:ef7eb2e8f9f7	820	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, Timeout) != HAL_OK)
<>	144:ef7eb2e8f9f7	821	{
<>	144:ef7eb2e8f9f7	822	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	823	}
<>	144:ef7eb2e8f9f7	824
<>	144:ef7eb2e8f9f7	825	hspi->Instance->DR = ((uint16_t)hspi->pTxBuffPtr);
<>	144:ef7eb2e8f9f7	826	hspi->pTxBuffPtr+=2;
<>	144:ef7eb2e8f9f7	827	hspi->TxXferCount--;
<>	144:ef7eb2e8f9f7	828
<>	144:ef7eb2e8f9f7	829	/* Enable CRC Transmission */
<>	144:ef7eb2e8f9f7	830	if((hspi->TxXferCount == 0) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
<>	144:ef7eb2e8f9f7	831	{
<>	144:ef7eb2e8f9f7	832	SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
<>	144:ef7eb2e8f9f7	833	}
<>	144:ef7eb2e8f9f7	834
<>	144:ef7eb2e8f9f7	835	/* Wait until RXNE flag is set */
<>	144:ef7eb2e8f9f7	836	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
<>	144:ef7eb2e8f9f7	837	{
<>	144:ef7eb2e8f9f7	838	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	839	}
<>	144:ef7eb2e8f9f7	840
<>	144:ef7eb2e8f9f7	841	((uint16_t)hspi->pRxBuffPtr) = hspi->Instance->DR;
<>	144:ef7eb2e8f9f7	842	hspi->pRxBuffPtr+=2;
<>	144:ef7eb2e8f9f7	843	hspi->RxXferCount--;
<>	144:ef7eb2e8f9f7	844	}
<>	144:ef7eb2e8f9f7	845	/* Receive the last byte */
<>	144:ef7eb2e8f9f7	846	if(hspi->Init.Mode == SPI_MODE_SLAVE)
<>	144:ef7eb2e8f9f7	847	{
<>	144:ef7eb2e8f9f7	848	/* Wait until RXNE flag is set */
<>	144:ef7eb2e8f9f7	849	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
<>	144:ef7eb2e8f9f7	850	{
<>	144:ef7eb2e8f9f7	851	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	852	}
<>	144:ef7eb2e8f9f7	853
<>	144:ef7eb2e8f9f7	854	((uint16_t)hspi->pRxBuffPtr) = hspi->Instance->DR;
<>	144:ef7eb2e8f9f7	855	hspi->pRxBuffPtr+=2;
<>	144:ef7eb2e8f9f7	856	hspi->RxXferCount--;
<>	144:ef7eb2e8f9f7	857	}
<>	144:ef7eb2e8f9f7	858	}
<>	144:ef7eb2e8f9f7	859	}
<>	144:ef7eb2e8f9f7	860	/* Transmit and Receive data in 8 Bit mode */
<>	144:ef7eb2e8f9f7	861	else
<>	144:ef7eb2e8f9f7	862	{
<>	144:ef7eb2e8f9f7	863	if((hspi->Init.Mode == SPI_MODE_SLAVE) \|\| ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->TxXferCount == 0x01)))
<>	144:ef7eb2e8f9f7	864	{
<>	144:ef7eb2e8f9f7	865	hspi->Instance->DR = (*hspi->pTxBuffPtr++);
<>	144:ef7eb2e8f9f7	866	hspi->TxXferCount--;
<>	144:ef7eb2e8f9f7	867	}
<>	144:ef7eb2e8f9f7	868	if(hspi->TxXferCount == 0)
<>	144:ef7eb2e8f9f7	869	{
<>	144:ef7eb2e8f9f7	870	/* Enable CRC Transmission */
<>	144:ef7eb2e8f9f7	871	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<>	144:ef7eb2e8f9f7	872	{
<>	144:ef7eb2e8f9f7	873	SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
<>	144:ef7eb2e8f9f7	874	}
<>	144:ef7eb2e8f9f7	875
<>	144:ef7eb2e8f9f7	876	/* Wait until RXNE flag is set */
<>	144:ef7eb2e8f9f7	877	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
<>	144:ef7eb2e8f9f7	878	{
<>	144:ef7eb2e8f9f7	879	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	880	}
<>	144:ef7eb2e8f9f7	881
<>	144:ef7eb2e8f9f7	882	(*hspi->pRxBuffPtr) = hspi->Instance->DR;
<>	144:ef7eb2e8f9f7	883	hspi->RxXferCount--;
<>	144:ef7eb2e8f9f7	884	}
<>	144:ef7eb2e8f9f7	885	else
<>	144:ef7eb2e8f9f7	886	{
<>	144:ef7eb2e8f9f7	887	while(hspi->TxXferCount > 0)
<>	144:ef7eb2e8f9f7	888	{
<>	144:ef7eb2e8f9f7	889	/* Wait until TXE flag is set to send data */
<>	144:ef7eb2e8f9f7	890	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, Timeout) != HAL_OK)
<>	144:ef7eb2e8f9f7	891	{
<>	144:ef7eb2e8f9f7	892	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	893	}
<>	144:ef7eb2e8f9f7	894
<>	144:ef7eb2e8f9f7	895	hspi->Instance->DR = (*hspi->pTxBuffPtr++);
<>	144:ef7eb2e8f9f7	896	hspi->TxXferCount--;
<>	144:ef7eb2e8f9f7	897
<>	144:ef7eb2e8f9f7	898	/* Enable CRC Transmission */
<>	144:ef7eb2e8f9f7	899	if((hspi->TxXferCount == 0) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
<>	144:ef7eb2e8f9f7	900	{
<>	144:ef7eb2e8f9f7	901	SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
<>	144:ef7eb2e8f9f7	902	}
<>	144:ef7eb2e8f9f7	903
<>	144:ef7eb2e8f9f7	904	/* Wait until RXNE flag is set */
<>	144:ef7eb2e8f9f7	905	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
<>	144:ef7eb2e8f9f7	906	{
<>	144:ef7eb2e8f9f7	907	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	908	}
<>	144:ef7eb2e8f9f7	909
<>	144:ef7eb2e8f9f7	910	(*hspi->pRxBuffPtr++) = hspi->Instance->DR;
<>	144:ef7eb2e8f9f7	911	hspi->RxXferCount--;
<>	144:ef7eb2e8f9f7	912	}
<>	144:ef7eb2e8f9f7	913	if(hspi->Init.Mode == SPI_MODE_SLAVE)
<>	144:ef7eb2e8f9f7	914	{
<>	144:ef7eb2e8f9f7	915	/* Wait until RXNE flag is set */
<>	144:ef7eb2e8f9f7	916	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
<>	144:ef7eb2e8f9f7	917	{
<>	144:ef7eb2e8f9f7	918	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	919	}
<>	144:ef7eb2e8f9f7	920
<>	144:ef7eb2e8f9f7	921	(*hspi->pRxBuffPtr++) = hspi->Instance->DR;
<>	144:ef7eb2e8f9f7	922	hspi->RxXferCount--;
<>	144:ef7eb2e8f9f7	923	}
<>	144:ef7eb2e8f9f7	924	}
<>	144:ef7eb2e8f9f7	925	}
<>	144:ef7eb2e8f9f7	926
<>	144:ef7eb2e8f9f7	927	/* Read CRC from DR to close CRC calculation process */
<>	144:ef7eb2e8f9f7	928	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<>	144:ef7eb2e8f9f7	929	{
<>	144:ef7eb2e8f9f7	930	/* Wait until RXNE flag is set */
<>	144:ef7eb2e8f9f7	931	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
<>	144:ef7eb2e8f9f7	932	{
<>	144:ef7eb2e8f9f7	933	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
<>	144:ef7eb2e8f9f7	934	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	935	}
<>	144:ef7eb2e8f9f7	936	/* Read CRC */
<>	144:ef7eb2e8f9f7	937	tmpreg = hspi->Instance->DR;
<>	144:ef7eb2e8f9f7	938	UNUSED(tmpreg);
<>	144:ef7eb2e8f9f7	939	}
<>	144:ef7eb2e8f9f7	940
<>	144:ef7eb2e8f9f7	941	/* Wait until Busy flag is reset before disabling SPI */
<>	144:ef7eb2e8f9f7	942	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_BSY, SET, Timeout) != HAL_OK)
<>	144:ef7eb2e8f9f7	943	{
<>	144:ef7eb2e8f9f7	944	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
<>	144:ef7eb2e8f9f7	945	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	946	}
<>	144:ef7eb2e8f9f7	947
<>	144:ef7eb2e8f9f7	948	hspi->State = HAL_SPI_STATE_READY;
<>	144:ef7eb2e8f9f7	949
<>	144:ef7eb2e8f9f7	950	/* Check if CRC error occurred */
<>	144:ef7eb2e8f9f7	951	if((hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET))
<>	144:ef7eb2e8f9f7	952	{
<>	144:ef7eb2e8f9f7	953	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
<>	144:ef7eb2e8f9f7	954
<>	144:ef7eb2e8f9f7	955	SPI_RESET_CRC(hspi);
<>	144:ef7eb2e8f9f7	956
<>	144:ef7eb2e8f9f7	957	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	958	__HAL_UNLOCK(hspi);
<>	144:ef7eb2e8f9f7	959
<>	144:ef7eb2e8f9f7	960	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	961	}
<>	144:ef7eb2e8f9f7	962
<>	144:ef7eb2e8f9f7	963	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	964	__HAL_UNLOCK(hspi);
<>	144:ef7eb2e8f9f7	965
<>	144:ef7eb2e8f9f7	966	return HAL_OK;
<>	144:ef7eb2e8f9f7	967	}
<>	144:ef7eb2e8f9f7	968	else
<>	144:ef7eb2e8f9f7	969	{
<>	144:ef7eb2e8f9f7	970	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	971	}
<>	144:ef7eb2e8f9f7	972	}
<>	144:ef7eb2e8f9f7	973
<>	144:ef7eb2e8f9f7	974	/**
<>	144:ef7eb2e8f9f7	975	* @brief Transmit an amount of data in no-blocking mode with Interrupt
<>	144:ef7eb2e8f9f7	976	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	977	* the configuration information for SPI module.
<>	144:ef7eb2e8f9f7	978	* @param pData: pointer to data buffer
<>	144:ef7eb2e8f9f7	979	* @param Size: amount of data to be sent
<>	144:ef7eb2e8f9f7	980	* @retval HAL status
<>	144:ef7eb2e8f9f7	981	*/
<>	144:ef7eb2e8f9f7	982	HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size)
<>	144:ef7eb2e8f9f7	983	{
<>	144:ef7eb2e8f9f7	984	if(hspi->State == HAL_SPI_STATE_READY)
<>	144:ef7eb2e8f9f7	985	{
<>	144:ef7eb2e8f9f7	986	if((pData == NULL) \|\| (Size == 0))
<>	144:ef7eb2e8f9f7	987	{
<>	144:ef7eb2e8f9f7	988	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	989	}
<>	144:ef7eb2e8f9f7	990
<>	144:ef7eb2e8f9f7	991	/* Check the parameters */
<>	144:ef7eb2e8f9f7	992	assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
<>	144:ef7eb2e8f9f7	993
<>	144:ef7eb2e8f9f7	994	/* Process Locked */
<>	144:ef7eb2e8f9f7	995	__HAL_LOCK(hspi);
<>	144:ef7eb2e8f9f7	996
<>	144:ef7eb2e8f9f7	997	/* Configure communication */
<>	144:ef7eb2e8f9f7	998	hspi->State = HAL_SPI_STATE_BUSY_TX;
<>	144:ef7eb2e8f9f7	999	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
<>	144:ef7eb2e8f9f7	1000
<>	144:ef7eb2e8f9f7	1001	hspi->TxISR = &SPI_TxISR;
<>	144:ef7eb2e8f9f7	1002	hspi->pTxBuffPtr = pData;
<>	144:ef7eb2e8f9f7	1003	hspi->TxXferSize = Size;
<>	144:ef7eb2e8f9f7	1004	hspi->TxXferCount = Size;
<>	144:ef7eb2e8f9f7	1005
<>	144:ef7eb2e8f9f7	1006	/Init field not used in handle to zero /
<>	144:ef7eb2e8f9f7	1007	hspi->RxISR = 0;
<>	144:ef7eb2e8f9f7	1008	hspi->pRxBuffPtr = NULL;
<>	144:ef7eb2e8f9f7	1009	hspi->RxXferSize = 0;
<>	144:ef7eb2e8f9f7	1010	hspi->RxXferCount = 0;
<>	144:ef7eb2e8f9f7	1011
<>	144:ef7eb2e8f9f7	1012	/* Configure communication direction : 1Line */
<>	144:ef7eb2e8f9f7	1013	if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
<>	144:ef7eb2e8f9f7	1014	{
<>	144:ef7eb2e8f9f7	1015	SPI_1LINE_TX(hspi);
<>	144:ef7eb2e8f9f7	1016	}
<>	144:ef7eb2e8f9f7	1017
<>	144:ef7eb2e8f9f7	1018	/* Reset CRC Calculation */
<>	144:ef7eb2e8f9f7	1019	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<>	144:ef7eb2e8f9f7	1020	{
<>	144:ef7eb2e8f9f7	1021	SPI_RESET_CRC(hspi);
<>	144:ef7eb2e8f9f7	1022	}
<>	144:ef7eb2e8f9f7	1023
<>	144:ef7eb2e8f9f7	1024	if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
<>	144:ef7eb2e8f9f7	1025	{
<>	144:ef7eb2e8f9f7	1026	__HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE));
<>	144:ef7eb2e8f9f7	1027	}
<>	144:ef7eb2e8f9f7	1028	else
<>	144:ef7eb2e8f9f7	1029	{
<>	144:ef7eb2e8f9f7	1030	/* Enable TXE and ERR interrupt */
<>	144:ef7eb2e8f9f7	1031	__HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE \| SPI_IT_ERR));
<>	144:ef7eb2e8f9f7	1032	}
<>	144:ef7eb2e8f9f7	1033	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	1034	__HAL_UNLOCK(hspi);
<>	144:ef7eb2e8f9f7	1035
<>	144:ef7eb2e8f9f7	1036	/* Check if the SPI is already enabled */
<>	144:ef7eb2e8f9f7	1037	if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
<>	144:ef7eb2e8f9f7	1038	{
<>	144:ef7eb2e8f9f7	1039	/* Enable SPI peripheral */
<>	144:ef7eb2e8f9f7	1040	__HAL_SPI_ENABLE(hspi);
<>	144:ef7eb2e8f9f7	1041	}
<>	144:ef7eb2e8f9f7	1042
<>	144:ef7eb2e8f9f7	1043	return HAL_OK;
<>	144:ef7eb2e8f9f7	1044	}
<>	144:ef7eb2e8f9f7	1045	else
<>	144:ef7eb2e8f9f7	1046	{
<>	144:ef7eb2e8f9f7	1047	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	1048	}
<>	144:ef7eb2e8f9f7	1049	}
<>	144:ef7eb2e8f9f7	1050
<>	144:ef7eb2e8f9f7	1051	/**
<>	144:ef7eb2e8f9f7	1052	* @brief Receive an amount of data in no-blocking mode with Interrupt
<>	144:ef7eb2e8f9f7	1053	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	1054	* the configuration information for SPI module.
<>	144:ef7eb2e8f9f7	1055	* @param pData: pointer to data buffer
<>	144:ef7eb2e8f9f7	1056	* @param Size: amount of data to be sent
<>	144:ef7eb2e8f9f7	1057	* @retval HAL status
<>	144:ef7eb2e8f9f7	1058	*/
<>	144:ef7eb2e8f9f7	1059	HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size)
<>	144:ef7eb2e8f9f7	1060	{
<>	144:ef7eb2e8f9f7	1061	if(hspi->State == HAL_SPI_STATE_READY)
<>	144:ef7eb2e8f9f7	1062	{
<>	144:ef7eb2e8f9f7	1063	if((pData == NULL) \|\| (Size == 0))
<>	144:ef7eb2e8f9f7	1064	{
<>	144:ef7eb2e8f9f7	1065	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	1066	}
<>	144:ef7eb2e8f9f7	1067
<>	144:ef7eb2e8f9f7	1068	/* Process Locked */
<>	144:ef7eb2e8f9f7	1069	__HAL_LOCK(hspi);
<>	144:ef7eb2e8f9f7	1070
<>	144:ef7eb2e8f9f7	1071	/* Configure communication */
<>	144:ef7eb2e8f9f7	1072	hspi->State = HAL_SPI_STATE_BUSY_RX;
<>	144:ef7eb2e8f9f7	1073	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
<>	144:ef7eb2e8f9f7	1074
<>	144:ef7eb2e8f9f7	1075	hspi->RxISR = &SPI_RxISR;
<>	144:ef7eb2e8f9f7	1076	hspi->pRxBuffPtr = pData;
<>	144:ef7eb2e8f9f7	1077	hspi->RxXferSize = Size;
<>	144:ef7eb2e8f9f7	1078	hspi->RxXferCount = Size ;
<>	144:ef7eb2e8f9f7	1079
<>	144:ef7eb2e8f9f7	1080	/Init field not used in handle to zero /
<>	144:ef7eb2e8f9f7	1081	hspi->TxISR = 0;
<>	144:ef7eb2e8f9f7	1082	hspi->pTxBuffPtr = NULL;
<>	144:ef7eb2e8f9f7	1083	hspi->TxXferSize = 0;
<>	144:ef7eb2e8f9f7	1084	hspi->TxXferCount = 0;
<>	144:ef7eb2e8f9f7	1085
<>	144:ef7eb2e8f9f7	1086	/* Configure communication direction : 1Line */
<>	144:ef7eb2e8f9f7	1087	if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
<>	144:ef7eb2e8f9f7	1088	{
<>	144:ef7eb2e8f9f7	1089	SPI_1LINE_RX(hspi);
<>	144:ef7eb2e8f9f7	1090	}
<>	144:ef7eb2e8f9f7	1091	else if((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
<>	144:ef7eb2e8f9f7	1092	{
<>	144:ef7eb2e8f9f7	1093	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	1094	__HAL_UNLOCK(hspi);
<>	144:ef7eb2e8f9f7	1095
<>	144:ef7eb2e8f9f7	1096	/* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
<>	144:ef7eb2e8f9f7	1097	return HAL_SPI_TransmitReceive_IT(hspi, pData, pData, Size);
<>	144:ef7eb2e8f9f7	1098	}
<>	144:ef7eb2e8f9f7	1099
<>	144:ef7eb2e8f9f7	1100	/* Reset CRC Calculation */
<>	144:ef7eb2e8f9f7	1101	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<>	144:ef7eb2e8f9f7	1102	{
<>	144:ef7eb2e8f9f7	1103	SPI_RESET_CRC(hspi);
<>	144:ef7eb2e8f9f7	1104	}
<>	144:ef7eb2e8f9f7	1105
<>	144:ef7eb2e8f9f7	1106	/* Enable TXE and ERR interrupt */
<>	144:ef7eb2e8f9f7	1107	__HAL_SPI_ENABLE_IT(hspi, (SPI_IT_RXNE \| SPI_IT_ERR));
<>	144:ef7eb2e8f9f7	1108
<>	144:ef7eb2e8f9f7	1109	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	1110	__HAL_UNLOCK(hspi);
<>	144:ef7eb2e8f9f7	1111
<>	144:ef7eb2e8f9f7	1112	/* Note : The SPI must be enabled after unlocking current process
<>	144:ef7eb2e8f9f7	1113	to avoid the risk of SPI interrupt handle execution before current
<>	144:ef7eb2e8f9f7	1114	process unlock */
<>	144:ef7eb2e8f9f7	1115
<>	144:ef7eb2e8f9f7	1116	/* Check if the SPI is already enabled */
<>	144:ef7eb2e8f9f7	1117	if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
<>	144:ef7eb2e8f9f7	1118	{
<>	144:ef7eb2e8f9f7	1119	/* Enable SPI peripheral */
<>	144:ef7eb2e8f9f7	1120	__HAL_SPI_ENABLE(hspi);
<>	144:ef7eb2e8f9f7	1121	}
<>	144:ef7eb2e8f9f7	1122
<>	144:ef7eb2e8f9f7	1123	return HAL_OK;
<>	144:ef7eb2e8f9f7	1124	}
<>	144:ef7eb2e8f9f7	1125	else
<>	144:ef7eb2e8f9f7	1126	{
<>	144:ef7eb2e8f9f7	1127	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	1128	}
<>	144:ef7eb2e8f9f7	1129	}
<>	144:ef7eb2e8f9f7	1130
<>	144:ef7eb2e8f9f7	1131	/**
<>	144:ef7eb2e8f9f7	1132	* @brief Transmit and Receive an amount of data in no-blocking mode with Interrupt
<>	144:ef7eb2e8f9f7	1133	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	1134	* the configuration information for SPI module.
<>	144:ef7eb2e8f9f7	1135	* @param pTxData: pointer to transmission data buffer
<>	144:ef7eb2e8f9f7	1136	* @param pRxData: pointer to reception data buffer to be
<>	144:ef7eb2e8f9f7	1137	* @param Size: amount of data to be sent
<>	144:ef7eb2e8f9f7	1138	* @retval HAL status
<>	144:ef7eb2e8f9f7	1139	*/
<>	144:ef7eb2e8f9f7	1140	HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef hspi, uint8_t pTxData, uint8_t *pRxData, uint16_t Size)
<>	144:ef7eb2e8f9f7	1141	{
<>	144:ef7eb2e8f9f7	1142
<>	144:ef7eb2e8f9f7	1143	if((hspi->State == HAL_SPI_STATE_READY) \|\| \
<>	144:ef7eb2e8f9f7	1144	((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->State == HAL_SPI_STATE_BUSY_RX)))
<>	144:ef7eb2e8f9f7	1145	{
<>	144:ef7eb2e8f9f7	1146	if((pTxData == NULL ) \|\| (pRxData == NULL ) \|\| (Size == 0))
<>	144:ef7eb2e8f9f7	1147	{
<>	144:ef7eb2e8f9f7	1148	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	1149	}
<>	144:ef7eb2e8f9f7	1150
<>	144:ef7eb2e8f9f7	1151	/* Check the parameters */
<>	144:ef7eb2e8f9f7	1152	assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
<>	144:ef7eb2e8f9f7	1153
<>	144:ef7eb2e8f9f7	1154	/* Process locked */
<>	144:ef7eb2e8f9f7	1155	__HAL_LOCK(hspi);
<>	144:ef7eb2e8f9f7	1156
<>	144:ef7eb2e8f9f7	1157	/* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
<>	144:ef7eb2e8f9f7	1158	if(hspi->State != HAL_SPI_STATE_BUSY_RX)
<>	144:ef7eb2e8f9f7	1159	{
<>	144:ef7eb2e8f9f7	1160	hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
<>	144:ef7eb2e8f9f7	1161	}
<>	144:ef7eb2e8f9f7	1162
<>	144:ef7eb2e8f9f7	1163	/* Configure communication */
<>	144:ef7eb2e8f9f7	1164	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
<>	144:ef7eb2e8f9f7	1165
<>	144:ef7eb2e8f9f7	1166	hspi->TxISR = &SPI_TxISR;
<>	144:ef7eb2e8f9f7	1167	hspi->pTxBuffPtr = pTxData;
<>	144:ef7eb2e8f9f7	1168	hspi->TxXferSize = Size;
<>	144:ef7eb2e8f9f7	1169	hspi->TxXferCount = Size;
<>	144:ef7eb2e8f9f7	1170
<>	144:ef7eb2e8f9f7	1171	hspi->RxISR = &SPI_2LinesRxISR;
<>	144:ef7eb2e8f9f7	1172	hspi->pRxBuffPtr = pRxData;
<>	144:ef7eb2e8f9f7	1173	hspi->RxXferSize = Size;
<>	144:ef7eb2e8f9f7	1174	hspi->RxXferCount = Size;
<>	144:ef7eb2e8f9f7	1175
<>	144:ef7eb2e8f9f7	1176	/* Reset CRC Calculation */
<>	144:ef7eb2e8f9f7	1177	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<>	144:ef7eb2e8f9f7	1178	{
<>	144:ef7eb2e8f9f7	1179	SPI_RESET_CRC(hspi);
<>	144:ef7eb2e8f9f7	1180	}
<>	144:ef7eb2e8f9f7	1181
<>	144:ef7eb2e8f9f7	1182	/* Enable TXE, RXNE and ERR interrupt */
<>	144:ef7eb2e8f9f7	1183	__HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE \| SPI_IT_RXNE \| SPI_IT_ERR));
<>	144:ef7eb2e8f9f7	1184
<>	144:ef7eb2e8f9f7	1185	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	1186	__HAL_UNLOCK(hspi);
<>	144:ef7eb2e8f9f7	1187
<>	144:ef7eb2e8f9f7	1188	/* Check if the SPI is already enabled */
<>	144:ef7eb2e8f9f7	1189	if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
<>	144:ef7eb2e8f9f7	1190	{
<>	144:ef7eb2e8f9f7	1191	/* Enable SPI peripheral */
<>	144:ef7eb2e8f9f7	1192	__HAL_SPI_ENABLE(hspi);
<>	144:ef7eb2e8f9f7	1193	}
<>	144:ef7eb2e8f9f7	1194
<>	144:ef7eb2e8f9f7	1195	return HAL_OK;
<>	144:ef7eb2e8f9f7	1196	}
<>	144:ef7eb2e8f9f7	1197	else
<>	144:ef7eb2e8f9f7	1198	{
<>	144:ef7eb2e8f9f7	1199	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	1200	}
<>	144:ef7eb2e8f9f7	1201	}
<>	144:ef7eb2e8f9f7	1202
<>	144:ef7eb2e8f9f7	1203	/**
<>	144:ef7eb2e8f9f7	1204	* @brief Transmit an amount of data in no-blocking mode with DMA
<>	144:ef7eb2e8f9f7	1205	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	1206	* the configuration information for SPI module.
<>	144:ef7eb2e8f9f7	1207	* @param pData: pointer to data buffer
<>	144:ef7eb2e8f9f7	1208	* @param Size: amount of data to be sent
<>	144:ef7eb2e8f9f7	1209	* @retval HAL status
<>	144:ef7eb2e8f9f7	1210	*/
<>	144:ef7eb2e8f9f7	1211	HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size)
<>	144:ef7eb2e8f9f7	1212	{
<>	144:ef7eb2e8f9f7	1213	if(hspi->State == HAL_SPI_STATE_READY)
<>	144:ef7eb2e8f9f7	1214	{
<>	144:ef7eb2e8f9f7	1215	if((pData == NULL) \|\| (Size == 0))
<>	144:ef7eb2e8f9f7	1216	{
<>	144:ef7eb2e8f9f7	1217	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	1218	}
<>	144:ef7eb2e8f9f7	1219
<>	144:ef7eb2e8f9f7	1220	/* Check the parameters */
<>	144:ef7eb2e8f9f7	1221	assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
<>	144:ef7eb2e8f9f7	1222
<>	144:ef7eb2e8f9f7	1223	/* Process Locked */
<>	144:ef7eb2e8f9f7	1224	__HAL_LOCK(hspi);
<>	144:ef7eb2e8f9f7	1225
<>	144:ef7eb2e8f9f7	1226	/* Configure communication */
<>	144:ef7eb2e8f9f7	1227	hspi->State = HAL_SPI_STATE_BUSY_TX;
<>	144:ef7eb2e8f9f7	1228	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
<>	144:ef7eb2e8f9f7	1229
<>	144:ef7eb2e8f9f7	1230	hspi->pTxBuffPtr = pData;
<>	144:ef7eb2e8f9f7	1231	hspi->TxXferSize = Size;
<>	144:ef7eb2e8f9f7	1232	hspi->TxXferCount = Size;
<>	144:ef7eb2e8f9f7	1233
<>	144:ef7eb2e8f9f7	1234	/Init field not used in handle to zero /
<>	144:ef7eb2e8f9f7	1235	hspi->TxISR = 0;
<>	144:ef7eb2e8f9f7	1236	hspi->RxISR = 0;
<>	144:ef7eb2e8f9f7	1237	hspi->pRxBuffPtr = NULL;
<>	144:ef7eb2e8f9f7	1238	hspi->RxXferSize = 0;
<>	144:ef7eb2e8f9f7	1239	hspi->RxXferCount = 0;
<>	144:ef7eb2e8f9f7	1240
<>	144:ef7eb2e8f9f7	1241	/* Configure communication direction : 1Line */
<>	144:ef7eb2e8f9f7	1242	if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
<>	144:ef7eb2e8f9f7	1243	{
<>	144:ef7eb2e8f9f7	1244	SPI_1LINE_TX(hspi);
<>	144:ef7eb2e8f9f7	1245	}
<>	144:ef7eb2e8f9f7	1246
<>	144:ef7eb2e8f9f7	1247	/* Reset CRC Calculation */
<>	144:ef7eb2e8f9f7	1248	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<>	144:ef7eb2e8f9f7	1249	{
<>	144:ef7eb2e8f9f7	1250	SPI_RESET_CRC(hspi);
<>	144:ef7eb2e8f9f7	1251	}
<>	144:ef7eb2e8f9f7	1252
<>	144:ef7eb2e8f9f7	1253	/* Set the SPI TxDMA Half transfer complete callback */
<>	144:ef7eb2e8f9f7	1254	hspi->hdmatx->XferHalfCpltCallback = SPI_DMAHalfTransmitCplt;
<>	144:ef7eb2e8f9f7	1255
<>	144:ef7eb2e8f9f7	1256	/* Set the SPI TxDMA transfer complete callback */
<>	144:ef7eb2e8f9f7	1257	hspi->hdmatx->XferCpltCallback = SPI_DMATransmitCplt;
<>	144:ef7eb2e8f9f7	1258
<>	144:ef7eb2e8f9f7	1259	/* Set the DMA error callback */
<>	144:ef7eb2e8f9f7	1260	hspi->hdmatx->XferErrorCallback = SPI_DMAError;
<>	144:ef7eb2e8f9f7	1261
<>	144:ef7eb2e8f9f7	1262	/* Enable the Tx DMA Channel */
<>	144:ef7eb2e8f9f7	1263	HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount);
<>	144:ef7eb2e8f9f7	1264
<>	144:ef7eb2e8f9f7	1265	/* Enable Tx DMA Request */
<>	144:ef7eb2e8f9f7	1266	SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
<>	144:ef7eb2e8f9f7	1267
<>	144:ef7eb2e8f9f7	1268	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	1269	__HAL_UNLOCK(hspi);
<>	144:ef7eb2e8f9f7	1270
<>	144:ef7eb2e8f9f7	1271	/* Check if the SPI is already enabled */
<>	144:ef7eb2e8f9f7	1272	if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
<>	144:ef7eb2e8f9f7	1273	{
<>	144:ef7eb2e8f9f7	1274	/* Enable SPI peripheral */
<>	144:ef7eb2e8f9f7	1275	__HAL_SPI_ENABLE(hspi);
<>	144:ef7eb2e8f9f7	1276	}
<>	144:ef7eb2e8f9f7	1277
<>	144:ef7eb2e8f9f7	1278	return HAL_OK;
<>	144:ef7eb2e8f9f7	1279	}
<>	144:ef7eb2e8f9f7	1280	else
<>	144:ef7eb2e8f9f7	1281	{
<>	144:ef7eb2e8f9f7	1282	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	1283	}
<>	144:ef7eb2e8f9f7	1284	}
<>	144:ef7eb2e8f9f7	1285
<>	144:ef7eb2e8f9f7	1286	/**
<>	144:ef7eb2e8f9f7	1287	* @brief Receive an amount of data in no-blocking mode with DMA
<>	144:ef7eb2e8f9f7	1288	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	1289	* the configuration information for SPI module.
<>	144:ef7eb2e8f9f7	1290	* @param pData: pointer to data buffer
<>	144:ef7eb2e8f9f7	1291	* @note When the CRC feature is enabled the pData Length must be Size + 1.
<>	144:ef7eb2e8f9f7	1292	* @param Size: amount of data to be sent
<>	144:ef7eb2e8f9f7	1293	* @retval HAL status
<>	144:ef7eb2e8f9f7	1294	*/
<>	144:ef7eb2e8f9f7	1295	HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size)
<>	144:ef7eb2e8f9f7	1296	{
<>	144:ef7eb2e8f9f7	1297	if(hspi->State == HAL_SPI_STATE_READY)
<>	144:ef7eb2e8f9f7	1298	{
<>	144:ef7eb2e8f9f7	1299	if((pData == NULL) \|\| (Size == 0))
<>	144:ef7eb2e8f9f7	1300	{
<>	144:ef7eb2e8f9f7	1301	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	1302	}
<>	144:ef7eb2e8f9f7	1303
<>	144:ef7eb2e8f9f7	1304	/* Process Locked */
<>	144:ef7eb2e8f9f7	1305	__HAL_LOCK(hspi);
<>	144:ef7eb2e8f9f7	1306
<>	144:ef7eb2e8f9f7	1307	/* Configure communication */
<>	144:ef7eb2e8f9f7	1308	hspi->State = HAL_SPI_STATE_BUSY_RX;
<>	144:ef7eb2e8f9f7	1309	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
<>	144:ef7eb2e8f9f7	1310
<>	144:ef7eb2e8f9f7	1311	hspi->pRxBuffPtr = pData;
<>	144:ef7eb2e8f9f7	1312	hspi->RxXferSize = Size;
<>	144:ef7eb2e8f9f7	1313	hspi->RxXferCount = Size;
<>	144:ef7eb2e8f9f7	1314
<>	144:ef7eb2e8f9f7	1315	/Init field not used in handle to zero /
<>	144:ef7eb2e8f9f7	1316	hspi->RxISR = 0;
<>	144:ef7eb2e8f9f7	1317	hspi->TxISR = 0;
<>	144:ef7eb2e8f9f7	1318	hspi->pTxBuffPtr = NULL;
<>	144:ef7eb2e8f9f7	1319	hspi->TxXferSize = 0;
<>	144:ef7eb2e8f9f7	1320	hspi->TxXferCount = 0;
<>	144:ef7eb2e8f9f7	1321
<>	144:ef7eb2e8f9f7	1322	/* Configure communication direction : 1Line */
<>	144:ef7eb2e8f9f7	1323	if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
<>	144:ef7eb2e8f9f7	1324	{
<>	144:ef7eb2e8f9f7	1325	SPI_1LINE_RX(hspi);
<>	144:ef7eb2e8f9f7	1326	}
<>	144:ef7eb2e8f9f7	1327	else if((hspi->Init.Direction == SPI_DIRECTION_2LINES)&&(hspi->Init.Mode == SPI_MODE_MASTER))
<>	144:ef7eb2e8f9f7	1328	{
<>	144:ef7eb2e8f9f7	1329	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	1330	__HAL_UNLOCK(hspi);
<>	144:ef7eb2e8f9f7	1331
<>	144:ef7eb2e8f9f7	1332	/* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
<>	144:ef7eb2e8f9f7	1333	return HAL_SPI_TransmitReceive_DMA(hspi, pData, pData, Size);
<>	144:ef7eb2e8f9f7	1334	}
<>	144:ef7eb2e8f9f7	1335
<>	144:ef7eb2e8f9f7	1336	/* Reset CRC Calculation */
<>	144:ef7eb2e8f9f7	1337	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<>	144:ef7eb2e8f9f7	1338	{
<>	144:ef7eb2e8f9f7	1339	SPI_RESET_CRC(hspi);
<>	144:ef7eb2e8f9f7	1340	}
<>	144:ef7eb2e8f9f7	1341
<>	144:ef7eb2e8f9f7	1342	/* Set the SPI RxDMA Half transfer complete callback */
<>	144:ef7eb2e8f9f7	1343	hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
<>	144:ef7eb2e8f9f7	1344
<>	144:ef7eb2e8f9f7	1345	/* Set the SPI Rx DMA transfer complete callback */
<>	144:ef7eb2e8f9f7	1346	hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
<>	144:ef7eb2e8f9f7	1347
<>	144:ef7eb2e8f9f7	1348	/* Set the DMA error callback */
<>	144:ef7eb2e8f9f7	1349	hspi->hdmarx->XferErrorCallback = SPI_DMAError;
<>	144:ef7eb2e8f9f7	1350
<>	144:ef7eb2e8f9f7	1351	/* Enable the Rx DMA Channel */
<>	144:ef7eb2e8f9f7	1352	HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount);
<>	144:ef7eb2e8f9f7	1353
<>	144:ef7eb2e8f9f7	1354	/* Enable Rx DMA Request */
<>	144:ef7eb2e8f9f7	1355	SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
<>	144:ef7eb2e8f9f7	1356
<>	144:ef7eb2e8f9f7	1357	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	1358	__HAL_UNLOCK(hspi);
<>	144:ef7eb2e8f9f7	1359
<>	144:ef7eb2e8f9f7	1360	/* Check if the SPI is already enabled */
<>	144:ef7eb2e8f9f7	1361	if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
<>	144:ef7eb2e8f9f7	1362	{
<>	144:ef7eb2e8f9f7	1363	/* Enable SPI peripheral */
<>	144:ef7eb2e8f9f7	1364	__HAL_SPI_ENABLE(hspi);
<>	144:ef7eb2e8f9f7	1365	}
<>	144:ef7eb2e8f9f7	1366
<>	144:ef7eb2e8f9f7	1367	return HAL_OK;
<>	144:ef7eb2e8f9f7	1368	}
<>	144:ef7eb2e8f9f7	1369	else
<>	144:ef7eb2e8f9f7	1370	{
<>	144:ef7eb2e8f9f7	1371	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	1372	}
<>	144:ef7eb2e8f9f7	1373	}
<>	144:ef7eb2e8f9f7	1374
<>	144:ef7eb2e8f9f7	1375	/**
<>	144:ef7eb2e8f9f7	1376	* @brief Transmit and Receive an amount of data in no-blocking mode with DMA
<>	144:ef7eb2e8f9f7	1377	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	1378	* the configuration information for SPI module.
<>	144:ef7eb2e8f9f7	1379	* @param pTxData: pointer to transmission data buffer
<>	144:ef7eb2e8f9f7	1380	* @param pRxData: pointer to reception data buffer
<>	144:ef7eb2e8f9f7	1381	* @note When the CRC feature is enabled the pRxData Length must be Size + 1
<>	144:ef7eb2e8f9f7	1382	* @param Size: amount of data to be sent
<>	144:ef7eb2e8f9f7	1383	* @retval HAL status
<>	144:ef7eb2e8f9f7	1384	*/
<>	144:ef7eb2e8f9f7	1385	HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef hspi, uint8_t pTxData, uint8_t *pRxData, uint16_t Size)
<>	144:ef7eb2e8f9f7	1386	{
<>	144:ef7eb2e8f9f7	1387	if((hspi->State == HAL_SPI_STATE_READY) \|\| \
<>	144:ef7eb2e8f9f7	1388	((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->State == HAL_SPI_STATE_BUSY_RX)))
<>	144:ef7eb2e8f9f7	1389	{
<>	144:ef7eb2e8f9f7	1390	if((pTxData == NULL ) \|\| (pRxData == NULL ) \|\| (Size == 0))
<>	144:ef7eb2e8f9f7	1391	{
<>	144:ef7eb2e8f9f7	1392	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	1393	}
<>	144:ef7eb2e8f9f7	1394
<>	144:ef7eb2e8f9f7	1395	/* Check the parameters */
<>	144:ef7eb2e8f9f7	1396	assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
<>	144:ef7eb2e8f9f7	1397
<>	144:ef7eb2e8f9f7	1398	/* Process locked */
<>	144:ef7eb2e8f9f7	1399	__HAL_LOCK(hspi);
<>	144:ef7eb2e8f9f7	1400
<>	144:ef7eb2e8f9f7	1401	/* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
<>	144:ef7eb2e8f9f7	1402	if(hspi->State != HAL_SPI_STATE_BUSY_RX)
<>	144:ef7eb2e8f9f7	1403	{
<>	144:ef7eb2e8f9f7	1404	hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
<>	144:ef7eb2e8f9f7	1405	}
<>	144:ef7eb2e8f9f7	1406
<>	144:ef7eb2e8f9f7	1407	/* Configure communication */
<>	144:ef7eb2e8f9f7	1408	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
<>	144:ef7eb2e8f9f7	1409
<>	144:ef7eb2e8f9f7	1410	hspi->pTxBuffPtr = (uint8_t*)pTxData;
<>	144:ef7eb2e8f9f7	1411	hspi->TxXferSize = Size;
<>	144:ef7eb2e8f9f7	1412	hspi->TxXferCount = Size;
<>	144:ef7eb2e8f9f7	1413
<>	144:ef7eb2e8f9f7	1414	hspi->pRxBuffPtr = (uint8_t*)pRxData;
<>	144:ef7eb2e8f9f7	1415	hspi->RxXferSize = Size;
<>	144:ef7eb2e8f9f7	1416	hspi->RxXferCount = Size;
<>	144:ef7eb2e8f9f7	1417
<>	144:ef7eb2e8f9f7	1418	/Init field not used in handle to zero /
<>	144:ef7eb2e8f9f7	1419	hspi->RxISR = 0;
<>	144:ef7eb2e8f9f7	1420	hspi->TxISR = 0;
<>	144:ef7eb2e8f9f7	1421
<>	144:ef7eb2e8f9f7	1422	/* Reset CRC Calculation */
<>	144:ef7eb2e8f9f7	1423	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<>	144:ef7eb2e8f9f7	1424	{
<>	144:ef7eb2e8f9f7	1425	SPI_RESET_CRC(hspi);
<>	144:ef7eb2e8f9f7	1426	}
<>	144:ef7eb2e8f9f7	1427
<>	144:ef7eb2e8f9f7	1428	/* Check if we are in Rx only or in Rx/Tx Mode and configure the DMA transfer complete callback */
<>	144:ef7eb2e8f9f7	1429	if(hspi->State == HAL_SPI_STATE_BUSY_RX)
<>	144:ef7eb2e8f9f7	1430	{
<>	144:ef7eb2e8f9f7	1431	/* Set the SPI Rx DMA Half transfer complete callback */
<>	144:ef7eb2e8f9f7	1432	hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
<>	144:ef7eb2e8f9f7	1433
<>	144:ef7eb2e8f9f7	1434	hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
<>	144:ef7eb2e8f9f7	1435	}
<>	144:ef7eb2e8f9f7	1436	else
<>	144:ef7eb2e8f9f7	1437	{
<>	144:ef7eb2e8f9f7	1438	/* Set the SPI Tx/Rx DMA Half transfer complete callback */
<>	144:ef7eb2e8f9f7	1439	hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfTransmitReceiveCplt;
<>	144:ef7eb2e8f9f7	1440
<>	144:ef7eb2e8f9f7	1441	hspi->hdmarx->XferCpltCallback = SPI_DMATransmitReceiveCplt;
<>	144:ef7eb2e8f9f7	1442	}
<>	144:ef7eb2e8f9f7	1443
<>	144:ef7eb2e8f9f7	1444	/* Set the DMA error callback */
<>	144:ef7eb2e8f9f7	1445	hspi->hdmarx->XferErrorCallback = SPI_DMAError;
<>	144:ef7eb2e8f9f7	1446
<>	144:ef7eb2e8f9f7	1447	/* Enable the Rx DMA Channel */
<>	144:ef7eb2e8f9f7	1448	HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount);
<>	144:ef7eb2e8f9f7	1449
<>	144:ef7eb2e8f9f7	1450	/* Enable Rx DMA Request */
<>	144:ef7eb2e8f9f7	1451	SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
<>	144:ef7eb2e8f9f7	1452
<>	144:ef7eb2e8f9f7	1453	/* Set the SPI Tx DMA transfer complete callback as NULL because the communication closing
<>	144:ef7eb2e8f9f7	1454	is performed in DMA reception complete callback */
<>	144:ef7eb2e8f9f7	1455	if(hspi->State == HAL_SPI_STATE_BUSY_TX_RX)
<>	144:ef7eb2e8f9f7	1456	{
<>	144:ef7eb2e8f9f7	1457	/* Set the DMA error callback */
<>	144:ef7eb2e8f9f7	1458	hspi->hdmatx->XferErrorCallback = SPI_DMAError;
<>	144:ef7eb2e8f9f7	1459	}
<>	144:ef7eb2e8f9f7	1460	else
<>	144:ef7eb2e8f9f7	1461	{
<>	144:ef7eb2e8f9f7	1462	hspi->hdmatx->XferErrorCallback = NULL;
<>	144:ef7eb2e8f9f7	1463	}
<>	144:ef7eb2e8f9f7	1464
<>	144:ef7eb2e8f9f7	1465	/* Enable the Tx DMA Channel */
<>	144:ef7eb2e8f9f7	1466	HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount);
<>	144:ef7eb2e8f9f7	1467
<>	144:ef7eb2e8f9f7	1468	/* Check if the SPI is already enabled */
<>	144:ef7eb2e8f9f7	1469	if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
<>	144:ef7eb2e8f9f7	1470	{
<>	144:ef7eb2e8f9f7	1471	/* Enable SPI peripheral */
<>	144:ef7eb2e8f9f7	1472	__HAL_SPI_ENABLE(hspi);
<>	144:ef7eb2e8f9f7	1473	}
<>	144:ef7eb2e8f9f7	1474
<>	144:ef7eb2e8f9f7	1475	/* Enable Tx DMA Request */
<>	144:ef7eb2e8f9f7	1476	SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
<>	144:ef7eb2e8f9f7	1477
<>	144:ef7eb2e8f9f7	1478	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	1479	__HAL_UNLOCK(hspi);
<>	144:ef7eb2e8f9f7	1480
<>	144:ef7eb2e8f9f7	1481	return HAL_OK;
<>	144:ef7eb2e8f9f7	1482	}
<>	144:ef7eb2e8f9f7	1483	else
<>	144:ef7eb2e8f9f7	1484	{
<>	144:ef7eb2e8f9f7	1485	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	1486	}
<>	144:ef7eb2e8f9f7	1487	}
<>	144:ef7eb2e8f9f7	1488
<>	144:ef7eb2e8f9f7	1489
<>	144:ef7eb2e8f9f7	1490	/**
<>	144:ef7eb2e8f9f7	1491	* @brief Pauses the DMA Transfer.
<>	144:ef7eb2e8f9f7	1492	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	1493	* the configuration information for the specified SPI module.
<>	144:ef7eb2e8f9f7	1494	* @retval HAL status
<>	144:ef7eb2e8f9f7	1495	*/
<>	144:ef7eb2e8f9f7	1496	HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi)
<>	144:ef7eb2e8f9f7	1497	{
<>	144:ef7eb2e8f9f7	1498	/* Process Locked */
<>	144:ef7eb2e8f9f7	1499	__HAL_LOCK(hspi);
<>	144:ef7eb2e8f9f7	1500
<>	144:ef7eb2e8f9f7	1501	/* Disable the SPI DMA Tx & Rx requests */
<>	144:ef7eb2e8f9f7	1502	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
<>	144:ef7eb2e8f9f7	1503	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
<>	144:ef7eb2e8f9f7	1504
<>	144:ef7eb2e8f9f7	1505	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	1506	__HAL_UNLOCK(hspi);
<>	144:ef7eb2e8f9f7	1507
<>	144:ef7eb2e8f9f7	1508	return HAL_OK;
<>	144:ef7eb2e8f9f7	1509	}
<>	144:ef7eb2e8f9f7	1510
<>	144:ef7eb2e8f9f7	1511	/**
<>	144:ef7eb2e8f9f7	1512	* @brief Resumes the DMA Transfer.
<>	144:ef7eb2e8f9f7	1513	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	1514	* the configuration information for the specified SPI module.
<>	144:ef7eb2e8f9f7	1515	* @retval HAL status
<>	144:ef7eb2e8f9f7	1516	*/
<>	144:ef7eb2e8f9f7	1517	HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi)
<>	144:ef7eb2e8f9f7	1518	{
<>	144:ef7eb2e8f9f7	1519	/* Process Locked */
<>	144:ef7eb2e8f9f7	1520	__HAL_LOCK(hspi);
<>	144:ef7eb2e8f9f7	1521
<>	144:ef7eb2e8f9f7	1522	/* Enable the SPI DMA Tx & Rx requests */
<>	144:ef7eb2e8f9f7	1523	SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
<>	144:ef7eb2e8f9f7	1524	SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
<>	144:ef7eb2e8f9f7	1525
<>	144:ef7eb2e8f9f7	1526	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	1527	__HAL_UNLOCK(hspi);
<>	144:ef7eb2e8f9f7	1528
<>	144:ef7eb2e8f9f7	1529	return HAL_OK;
<>	144:ef7eb2e8f9f7	1530	}
<>	144:ef7eb2e8f9f7	1531
<>	144:ef7eb2e8f9f7	1532	/**
<>	144:ef7eb2e8f9f7	1533	* @brief Stops the DMA Transfer.
<>	144:ef7eb2e8f9f7	1534	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	1535	* the configuration information for the specified SPI module.
<>	144:ef7eb2e8f9f7	1536	* @retval HAL status
<>	144:ef7eb2e8f9f7	1537	*/
<>	144:ef7eb2e8f9f7	1538	HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi)
<>	144:ef7eb2e8f9f7	1539	{
<>	144:ef7eb2e8f9f7	1540	/* The Lock is not implemented on this API to allow the user application
<>	144:ef7eb2e8f9f7	1541	to call the HAL SPI API under callbacks HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback():
<>	144:ef7eb2e8f9f7	1542	when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated
<>	144:ef7eb2e8f9f7	1543	and the correspond call back is executed HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback()
<>	144:ef7eb2e8f9f7	1544	*/
<>	144:ef7eb2e8f9f7	1545
<>	144:ef7eb2e8f9f7	1546	/* Abort the SPI DMA tx Channel */
<>	144:ef7eb2e8f9f7	1547	if(hspi->hdmatx != NULL)
<>	144:ef7eb2e8f9f7	1548	{
<>	144:ef7eb2e8f9f7	1549	HAL_DMA_Abort(hspi->hdmatx);
<>	144:ef7eb2e8f9f7	1550	}
<>	144:ef7eb2e8f9f7	1551	/* Abort the SPI DMA rx Channel */
<>	144:ef7eb2e8f9f7	1552	if(hspi->hdmarx != NULL)
<>	144:ef7eb2e8f9f7	1553	{
<>	144:ef7eb2e8f9f7	1554	HAL_DMA_Abort(hspi->hdmarx);
<>	144:ef7eb2e8f9f7	1555	}
<>	144:ef7eb2e8f9f7	1556
<>	144:ef7eb2e8f9f7	1557	/* Disable the SPI DMA Tx & Rx requests */
<>	144:ef7eb2e8f9f7	1558	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
<>	144:ef7eb2e8f9f7	1559	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
<>	144:ef7eb2e8f9f7	1560
<>	144:ef7eb2e8f9f7	1561	hspi->State = HAL_SPI_STATE_READY;
<>	144:ef7eb2e8f9f7	1562
<>	144:ef7eb2e8f9f7	1563	return HAL_OK;
<>	144:ef7eb2e8f9f7	1564	}
<>	144:ef7eb2e8f9f7	1565
<>	144:ef7eb2e8f9f7	1566	/**
<>	144:ef7eb2e8f9f7	1567	* @brief This function handles SPI interrupt request.
<>	144:ef7eb2e8f9f7	1568	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	1569	* the configuration information for SPI module.
<>	144:ef7eb2e8f9f7	1570	* @retval None
<>	144:ef7eb2e8f9f7	1571	*/
<>	144:ef7eb2e8f9f7	1572	void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi)
<>	144:ef7eb2e8f9f7	1573	{
<>	144:ef7eb2e8f9f7	1574	/* SPI in mode Receiver and Overrun not occurred ---------------------------*/
<>	144:ef7eb2e8f9f7	1575	if((__HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_RXNE) != RESET) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE) != RESET) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_OVR) == RESET))
<>	144:ef7eb2e8f9f7	1576	{
<>	144:ef7eb2e8f9f7	1577	hspi->RxISR(hspi);
<>	144:ef7eb2e8f9f7	1578	return;
<>	144:ef7eb2e8f9f7	1579	}
<>	144:ef7eb2e8f9f7	1580
<>	144:ef7eb2e8f9f7	1581	/* SPI in mode Tramitter ---------------------------------------------------*/
<>	144:ef7eb2e8f9f7	1582	if((__HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_TXE) != RESET) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE) != RESET))
<>	144:ef7eb2e8f9f7	1583	{
<>	144:ef7eb2e8f9f7	1584	hspi->TxISR(hspi);
<>	144:ef7eb2e8f9f7	1585	return;
<>	144:ef7eb2e8f9f7	1586	}
<>	144:ef7eb2e8f9f7	1587
<>	144:ef7eb2e8f9f7	1588	if(__HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_ERR) != RESET)
<>	144:ef7eb2e8f9f7	1589	{
<>	144:ef7eb2e8f9f7	1590	/* SPI CRC error interrupt occurred ---------------------------------------*/
<>	144:ef7eb2e8f9f7	1591	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
<>	144:ef7eb2e8f9f7	1592	{
<>	144:ef7eb2e8f9f7	1593	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
<>	144:ef7eb2e8f9f7	1594	__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
<>	144:ef7eb2e8f9f7	1595	}
<>	144:ef7eb2e8f9f7	1596	/* SPI Mode Fault error interrupt occurred --------------------------------*/
<>	144:ef7eb2e8f9f7	1597	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_MODF) != RESET)
<>	144:ef7eb2e8f9f7	1598	{
<>	144:ef7eb2e8f9f7	1599	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_MODF);
<>	144:ef7eb2e8f9f7	1600	__HAL_SPI_CLEAR_MODFFLAG(hspi);
<>	144:ef7eb2e8f9f7	1601	}
<>	144:ef7eb2e8f9f7	1602
<>	144:ef7eb2e8f9f7	1603	/* SPI Overrun error interrupt occurred -----------------------------------*/
<>	144:ef7eb2e8f9f7	1604	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_OVR) != RESET)
<>	144:ef7eb2e8f9f7	1605	{
<>	144:ef7eb2e8f9f7	1606	if(hspi->State != HAL_SPI_STATE_BUSY_TX)
<>	144:ef7eb2e8f9f7	1607	{
<>	144:ef7eb2e8f9f7	1608	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_OVR);
<>	144:ef7eb2e8f9f7	1609	__HAL_SPI_CLEAR_OVRFLAG(hspi);
<>	144:ef7eb2e8f9f7	1610	}
<>	144:ef7eb2e8f9f7	1611	}
<>	144:ef7eb2e8f9f7	1612
<>	144:ef7eb2e8f9f7	1613	/* Call the Error call Back in case of Errors */
<>	144:ef7eb2e8f9f7	1614	if(hspi->ErrorCode!=HAL_SPI_ERROR_NONE)
<>	144:ef7eb2e8f9f7	1615	{
<>	144:ef7eb2e8f9f7	1616	__HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE \| SPI_IT_TXE \| SPI_IT_ERR);
<>	144:ef7eb2e8f9f7	1617	hspi->State = HAL_SPI_STATE_READY;
<>	144:ef7eb2e8f9f7	1618	HAL_SPI_ErrorCallback(hspi);
<>	144:ef7eb2e8f9f7	1619	}
<>	144:ef7eb2e8f9f7	1620	}
<>	144:ef7eb2e8f9f7	1621	}
<>	144:ef7eb2e8f9f7	1622
<>	144:ef7eb2e8f9f7	1623	/**
<>	144:ef7eb2e8f9f7	1624	* @brief Tx Transfer completed callbacks
<>	144:ef7eb2e8f9f7	1625	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	1626	* the configuration information for SPI module.
<>	144:ef7eb2e8f9f7	1627	* @retval None
<>	144:ef7eb2e8f9f7	1628	*/
<>	144:ef7eb2e8f9f7	1629	__weak void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi)
<>	144:ef7eb2e8f9f7	1630	{
<>	144:ef7eb2e8f9f7	1631	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	1632	UNUSED(hspi);
<>	144:ef7eb2e8f9f7	1633	/* NOTE : This function Should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	1634	the HAL_SPI_TxCpltCallback could be implenetd in the user file
<>	144:ef7eb2e8f9f7	1635	*/
<>	144:ef7eb2e8f9f7	1636	}
<>	144:ef7eb2e8f9f7	1637
<>	144:ef7eb2e8f9f7	1638	/**
<>	144:ef7eb2e8f9f7	1639	* @brief Rx Transfer completed callbacks
<>	144:ef7eb2e8f9f7	1640	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	1641	* the configuration information for SPI module.
<>	144:ef7eb2e8f9f7	1642	* @retval None
<>	144:ef7eb2e8f9f7	1643	*/
<>	144:ef7eb2e8f9f7	1644	__weak void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi)
<>	144:ef7eb2e8f9f7	1645	{
<>	144:ef7eb2e8f9f7	1646	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	1647	UNUSED(hspi);
<>	144:ef7eb2e8f9f7	1648	/* NOTE : This function Should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	1649	the HAL_SPI_RxCpltCallback() could be implenetd in the user file
<>	144:ef7eb2e8f9f7	1650	*/
<>	144:ef7eb2e8f9f7	1651	}
<>	144:ef7eb2e8f9f7	1652
<>	144:ef7eb2e8f9f7	1653	/**
<>	144:ef7eb2e8f9f7	1654	* @brief Tx and Rx Transfer completed callbacks
<>	144:ef7eb2e8f9f7	1655	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	1656	* the configuration information for SPI module.
<>	144:ef7eb2e8f9f7	1657	* @retval None
<>	144:ef7eb2e8f9f7	1658	*/
<>	144:ef7eb2e8f9f7	1659	__weak void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi)
<>	144:ef7eb2e8f9f7	1660	{
<>	144:ef7eb2e8f9f7	1661	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	1662	UNUSED(hspi);
<>	144:ef7eb2e8f9f7	1663	/* NOTE : This function Should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	1664	the HAL_SPI_TxRxCpltCallback() could be implenetd in the user file
<>	144:ef7eb2e8f9f7	1665	*/
<>	144:ef7eb2e8f9f7	1666	}
<>	144:ef7eb2e8f9f7	1667
<>	144:ef7eb2e8f9f7	1668	/**
<>	144:ef7eb2e8f9f7	1669	* @brief Tx Half Transfer completed callbacks
<>	144:ef7eb2e8f9f7	1670	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	1671	* the configuration information for SPI module.
<>	144:ef7eb2e8f9f7	1672	* @retval None
<>	144:ef7eb2e8f9f7	1673	*/
<>	144:ef7eb2e8f9f7	1674	__weak void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi)
<>	144:ef7eb2e8f9f7	1675	{
<>	144:ef7eb2e8f9f7	1676	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	1677	UNUSED(hspi);
<>	144:ef7eb2e8f9f7	1678	/* NOTE : This function Should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	1679	the HAL_SPI_TxHalfCpltCallback could be implenetd in the user file
<>	144:ef7eb2e8f9f7	1680	*/
<>	144:ef7eb2e8f9f7	1681	}
<>	144:ef7eb2e8f9f7	1682
<>	144:ef7eb2e8f9f7	1683	/**
<>	144:ef7eb2e8f9f7	1684	* @brief Rx Half Transfer completed callbacks
<>	144:ef7eb2e8f9f7	1685	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	1686	* the configuration information for SPI module.
<>	144:ef7eb2e8f9f7	1687	* @retval None
<>	144:ef7eb2e8f9f7	1688	*/
<>	144:ef7eb2e8f9f7	1689	__weak void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi)
<>	144:ef7eb2e8f9f7	1690	{
<>	144:ef7eb2e8f9f7	1691	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	1692	UNUSED(hspi);
<>	144:ef7eb2e8f9f7	1693	/* NOTE : This function Should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	1694	the HAL_SPI_RxHalfCpltCallback() could be implenetd in the user file
<>	144:ef7eb2e8f9f7	1695	*/
<>	144:ef7eb2e8f9f7	1696	}
<>	144:ef7eb2e8f9f7	1697
<>	144:ef7eb2e8f9f7	1698	/**
<>	144:ef7eb2e8f9f7	1699	* @brief Tx and Rx Transfer completed callbacks
<>	144:ef7eb2e8f9f7	1700	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	1701	* the configuration information for SPI module.
<>	144:ef7eb2e8f9f7	1702	* @retval None
<>	144:ef7eb2e8f9f7	1703	*/
<>	144:ef7eb2e8f9f7	1704	__weak void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi)
<>	144:ef7eb2e8f9f7	1705	{
<>	144:ef7eb2e8f9f7	1706	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	1707	UNUSED(hspi);
<>	144:ef7eb2e8f9f7	1708	/* NOTE : This function Should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	1709	the HAL_SPI_TxRxHalfCpltCallback() could be implenetd in the user file
<>	144:ef7eb2e8f9f7	1710	*/
<>	144:ef7eb2e8f9f7	1711	}
<>	144:ef7eb2e8f9f7	1712
<>	144:ef7eb2e8f9f7	1713	/**
<>	144:ef7eb2e8f9f7	1714	* @brief SPI error callbacks
<>	144:ef7eb2e8f9f7	1715	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	1716	* the configuration information for SPI module.
<>	144:ef7eb2e8f9f7	1717	* @retval None
<>	144:ef7eb2e8f9f7	1718	*/
<>	144:ef7eb2e8f9f7	1719	__weak void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi)
<>	144:ef7eb2e8f9f7	1720	{
<>	144:ef7eb2e8f9f7	1721	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	1722	UNUSED(hspi);
<>	144:ef7eb2e8f9f7	1723	/* NOTE : - This function Should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	1724	the HAL_SPI_ErrorCallback() could be implenetd in the user file.
<>	144:ef7eb2e8f9f7	1725	- The ErrorCode parameter in the hspi handle is updated by the SPI processes
<>	144:ef7eb2e8f9f7	1726	and user can use HAL_SPI_GetError() API to check the latest error occurred.
<>	144:ef7eb2e8f9f7	1727	*/
<>	144:ef7eb2e8f9f7	1728	}
<>	144:ef7eb2e8f9f7	1729
<>	144:ef7eb2e8f9f7	1730	/**
<>	144:ef7eb2e8f9f7	1731	* @}
<>	144:ef7eb2e8f9f7	1732	*/
<>	144:ef7eb2e8f9f7	1733
<>	144:ef7eb2e8f9f7	1734	/** @defgroup SPI_Exported_Functions_Group3 Peripheral State and Errors functions
<>	144:ef7eb2e8f9f7	1735	* @brief SPI control functions
<>	144:ef7eb2e8f9f7	1736	*
<>	144:ef7eb2e8f9f7	1737	@verbatim
<>	144:ef7eb2e8f9f7	1738	===============================================================================
<>	144:ef7eb2e8f9f7	1739	##### Peripheral State and Errors functions #####
<>	144:ef7eb2e8f9f7	1740	===============================================================================
<>	144:ef7eb2e8f9f7	1741	[..]
<>	144:ef7eb2e8f9f7	1742	This subsection provides a set of functions allowing to control the SPI.
<>	144:ef7eb2e8f9f7	1743	(+) HAL_SPI_GetState() API can be helpful to check in run-time the state of the SPI peripheral
<>	144:ef7eb2e8f9f7	1744	(+) HAL_SPI_GetError() check in run-time Errors occurring during communication
<>	144:ef7eb2e8f9f7	1745	@endverbatim
<>	144:ef7eb2e8f9f7	1746	* @{
<>	144:ef7eb2e8f9f7	1747	*/
<>	144:ef7eb2e8f9f7	1748
<>	144:ef7eb2e8f9f7	1749	/**
<>	144:ef7eb2e8f9f7	1750	* @brief Return the SPI state
<>	144:ef7eb2e8f9f7	1751	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	1752	* the configuration information for SPI module.
<>	144:ef7eb2e8f9f7	1753	* @retval SPI state
<>	144:ef7eb2e8f9f7	1754	*/
<>	144:ef7eb2e8f9f7	1755	HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi)
<>	144:ef7eb2e8f9f7	1756	{
<>	144:ef7eb2e8f9f7	1757	return hspi->State;
<>	144:ef7eb2e8f9f7	1758	}
<>	144:ef7eb2e8f9f7	1759
<>	144:ef7eb2e8f9f7	1760	/**
<>	144:ef7eb2e8f9f7	1761	* @brief Return the SPI error code
<>	144:ef7eb2e8f9f7	1762	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	1763	* the configuration information for SPI module.
<>	144:ef7eb2e8f9f7	1764	* @retval SPI Error Code
<>	144:ef7eb2e8f9f7	1765	*/
<>	144:ef7eb2e8f9f7	1766	uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi)
<>	144:ef7eb2e8f9f7	1767	{
<>	144:ef7eb2e8f9f7	1768	return hspi->ErrorCode;
<>	144:ef7eb2e8f9f7	1769	}
<>	144:ef7eb2e8f9f7	1770
<>	144:ef7eb2e8f9f7	1771	/**
<>	144:ef7eb2e8f9f7	1772	* @}
<>	144:ef7eb2e8f9f7	1773	*/
<>	144:ef7eb2e8f9f7	1774
<>	144:ef7eb2e8f9f7	1775	/**
<>	144:ef7eb2e8f9f7	1776	* @}
<>	144:ef7eb2e8f9f7	1777	*/
<>	144:ef7eb2e8f9f7	1778
<>	144:ef7eb2e8f9f7	1779
<>	144:ef7eb2e8f9f7	1780
<>	144:ef7eb2e8f9f7	1781	/** @addtogroup SPI_Private_Functions
<>	144:ef7eb2e8f9f7	1782	* @{
<>	144:ef7eb2e8f9f7	1783	*/
<>	144:ef7eb2e8f9f7	1784
<>	144:ef7eb2e8f9f7	1785
<>	144:ef7eb2e8f9f7	1786	/**
<>	144:ef7eb2e8f9f7	1787	* @brief Interrupt Handler to close Tx transfer
<>	144:ef7eb2e8f9f7	1788	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	1789	* the configuration information for SPI module.
<>	144:ef7eb2e8f9f7	1790	* @retval None
<>	144:ef7eb2e8f9f7	1791	*/
<>	144:ef7eb2e8f9f7	1792	static void SPI_TxCloseIRQHandler(SPI_HandleTypeDef *hspi)
<>	144:ef7eb2e8f9f7	1793	{
<>	144:ef7eb2e8f9f7	1794	/* Wait until TXE flag is set to send data */
<>	144:ef7eb2e8f9f7	1795	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK)
<>	144:ef7eb2e8f9f7	1796	{
<>	144:ef7eb2e8f9f7	1797	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
<>	144:ef7eb2e8f9f7	1798	}
<>	144:ef7eb2e8f9f7	1799
<>	144:ef7eb2e8f9f7	1800	/* Disable TXE interrupt */
<>	144:ef7eb2e8f9f7	1801	__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE));
<>	144:ef7eb2e8f9f7	1802
<>	144:ef7eb2e8f9f7	1803	/* Disable ERR interrupt if Receive process is finished */
<>	144:ef7eb2e8f9f7	1804	if(__HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_RXNE) == RESET)
<>	144:ef7eb2e8f9f7	1805	{
<>	144:ef7eb2e8f9f7	1806	__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_ERR));
<>	144:ef7eb2e8f9f7	1807
<>	144:ef7eb2e8f9f7	1808	/* Wait until Busy flag is reset before disabling SPI */
<>	144:ef7eb2e8f9f7	1809	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_BSY, SET, SPI_TIMEOUT_VALUE) != HAL_OK)
<>	144:ef7eb2e8f9f7	1810	{
<>	144:ef7eb2e8f9f7	1811	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
<>	144:ef7eb2e8f9f7	1812	}
<>	144:ef7eb2e8f9f7	1813
<>	144:ef7eb2e8f9f7	1814	/* Clear OVERUN flag in 2 Lines communication mode because received is not read */
<>	144:ef7eb2e8f9f7	1815	if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
<>	144:ef7eb2e8f9f7	1816	{
<>	144:ef7eb2e8f9f7	1817	__HAL_SPI_CLEAR_OVRFLAG(hspi);
<>	144:ef7eb2e8f9f7	1818	}
<>	144:ef7eb2e8f9f7	1819
<>	144:ef7eb2e8f9f7	1820	/* Check if Errors has been detected during transfer */
<>	144:ef7eb2e8f9f7	1821	if(hspi->ErrorCode == HAL_SPI_ERROR_NONE)
<>	144:ef7eb2e8f9f7	1822	{
<>	144:ef7eb2e8f9f7	1823	/* Check if we are in Tx or in Rx/Tx Mode */
<>	144:ef7eb2e8f9f7	1824	if(hspi->State == HAL_SPI_STATE_BUSY_TX_RX)
<>	144:ef7eb2e8f9f7	1825	{
<>	144:ef7eb2e8f9f7	1826	/* Set state to READY before run the Callback Complete */
<>	144:ef7eb2e8f9f7	1827	hspi->State = HAL_SPI_STATE_READY;
<>	144:ef7eb2e8f9f7	1828	HAL_SPI_TxRxCpltCallback(hspi);
<>	144:ef7eb2e8f9f7	1829	}
<>	144:ef7eb2e8f9f7	1830	else
<>	144:ef7eb2e8f9f7	1831	{
<>	144:ef7eb2e8f9f7	1832	/* Set state to READY before run the Callback Complete */
<>	144:ef7eb2e8f9f7	1833	hspi->State = HAL_SPI_STATE_READY;
<>	144:ef7eb2e8f9f7	1834	HAL_SPI_TxCpltCallback(hspi);
<>	144:ef7eb2e8f9f7	1835	}
<>	144:ef7eb2e8f9f7	1836	}
<>	144:ef7eb2e8f9f7	1837	else
<>	144:ef7eb2e8f9f7	1838	{
<>	144:ef7eb2e8f9f7	1839	/* Set state to READY before run the Callback Complete */
<>	144:ef7eb2e8f9f7	1840	hspi->State = HAL_SPI_STATE_READY;
<>	144:ef7eb2e8f9f7	1841	/* Call Error call back in case of Error */
<>	144:ef7eb2e8f9f7	1842	HAL_SPI_ErrorCallback(hspi);
<>	144:ef7eb2e8f9f7	1843	}
<>	144:ef7eb2e8f9f7	1844	}
<>	144:ef7eb2e8f9f7	1845	}
<>	144:ef7eb2e8f9f7	1846
<>	144:ef7eb2e8f9f7	1847	/**
<>	144:ef7eb2e8f9f7	1848	* @brief Interrupt Handler to transmit amount of data in no-blocking mode
<>	144:ef7eb2e8f9f7	1849	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	1850	* the configuration information for SPI module.
<>	144:ef7eb2e8f9f7	1851	* @retval None
<>	144:ef7eb2e8f9f7	1852	*/
<>	144:ef7eb2e8f9f7	1853	static void SPI_TxISR(SPI_HandleTypeDef *hspi)
<>	144:ef7eb2e8f9f7	1854	{
<>	144:ef7eb2e8f9f7	1855	/* Transmit data in 8 Bit mode */
<>	144:ef7eb2e8f9f7	1856	if(hspi->Init.DataSize == SPI_DATASIZE_8BIT)
<>	144:ef7eb2e8f9f7	1857	{
<>	144:ef7eb2e8f9f7	1858	hspi->Instance->DR = (*hspi->pTxBuffPtr++);
<>	144:ef7eb2e8f9f7	1859	}
<>	144:ef7eb2e8f9f7	1860	/* Transmit data in 16 Bit mode */
<>	144:ef7eb2e8f9f7	1861	else
<>	144:ef7eb2e8f9f7	1862	{
<>	144:ef7eb2e8f9f7	1863	hspi->Instance->DR = ((uint16_t)hspi->pTxBuffPtr);
<>	144:ef7eb2e8f9f7	1864	hspi->pTxBuffPtr+=2;
<>	144:ef7eb2e8f9f7	1865	}
<>	144:ef7eb2e8f9f7	1866	hspi->TxXferCount--;
<>	144:ef7eb2e8f9f7	1867
<>	144:ef7eb2e8f9f7	1868	if(hspi->TxXferCount == 0)
<>	144:ef7eb2e8f9f7	1869	{
<>	144:ef7eb2e8f9f7	1870	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<>	144:ef7eb2e8f9f7	1871	{
<>	144:ef7eb2e8f9f7	1872	/* calculate and transfer CRC on Tx line */
<>	144:ef7eb2e8f9f7	1873	SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
<>	144:ef7eb2e8f9f7	1874	}
<>	144:ef7eb2e8f9f7	1875	SPI_TxCloseIRQHandler(hspi);
<>	144:ef7eb2e8f9f7	1876	}
<>	144:ef7eb2e8f9f7	1877	}
<>	144:ef7eb2e8f9f7	1878
<>	144:ef7eb2e8f9f7	1879	/**
<>	144:ef7eb2e8f9f7	1880	* @brief Interrupt Handler to close Rx transfer
<>	144:ef7eb2e8f9f7	1881	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	1882	* the configuration information for SPI module.
<>	144:ef7eb2e8f9f7	1883	* @retval None
<>	144:ef7eb2e8f9f7	1884	*/
<>	144:ef7eb2e8f9f7	1885	static void SPI_RxCloseIRQHandler(SPI_HandleTypeDef *hspi)
<>	144:ef7eb2e8f9f7	1886	{
<>	144:ef7eb2e8f9f7	1887	__IO uint16_t tmpreg = 0;
<>	144:ef7eb2e8f9f7	1888
<>	144:ef7eb2e8f9f7	1889	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<>	144:ef7eb2e8f9f7	1890	{
<>	144:ef7eb2e8f9f7	1891	/* Wait until RXNE flag is set to read CRC data */
<>	144:ef7eb2e8f9f7	1892	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK)
<>	144:ef7eb2e8f9f7	1893	{
<>	144:ef7eb2e8f9f7	1894	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
<>	144:ef7eb2e8f9f7	1895	}
<>	144:ef7eb2e8f9f7	1896
<>	144:ef7eb2e8f9f7	1897	/* Read CRC to reset RXNE flag */
<>	144:ef7eb2e8f9f7	1898	tmpreg = hspi->Instance->DR;
<>	144:ef7eb2e8f9f7	1899	UNUSED(tmpreg);
<>	144:ef7eb2e8f9f7	1900
<>	144:ef7eb2e8f9f7	1901	/* Wait until RXNE flag is reset */
<>	144:ef7eb2e8f9f7	1902	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_TIMEOUT_VALUE) != HAL_OK)
<>	144:ef7eb2e8f9f7	1903	{
<>	144:ef7eb2e8f9f7	1904	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
<>	144:ef7eb2e8f9f7	1905	}
<>	144:ef7eb2e8f9f7	1906
<>	144:ef7eb2e8f9f7	1907	/* Check if CRC error occurred */
<>	144:ef7eb2e8f9f7	1908	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
<>	144:ef7eb2e8f9f7	1909	{
<>	144:ef7eb2e8f9f7	1910	/* Check if CRC error is valid or not (workaround to be applied or not) */
<>	144:ef7eb2e8f9f7	1911	if ( (hspi->State != HAL_SPI_STATE_BUSY_RX)
<>	144:ef7eb2e8f9f7	1912	\|\| (SPI_ISCRCErrorValid(hspi) == SPI_VALID_CRC_ERROR) )
<>	144:ef7eb2e8f9f7	1913	{
<>	144:ef7eb2e8f9f7	1914	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
<>	144:ef7eb2e8f9f7	1915
<>	144:ef7eb2e8f9f7	1916	/* Reset CRC Calculation */
<>	144:ef7eb2e8f9f7	1917	SPI_RESET_CRC(hspi);
<>	144:ef7eb2e8f9f7	1918	}
<>	144:ef7eb2e8f9f7	1919	else
<>	144:ef7eb2e8f9f7	1920	{
<>	144:ef7eb2e8f9f7	1921	__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
<>	144:ef7eb2e8f9f7	1922	}
<>	144:ef7eb2e8f9f7	1923	}
<>	144:ef7eb2e8f9f7	1924	}
<>	144:ef7eb2e8f9f7	1925
<>	144:ef7eb2e8f9f7	1926	/* Disable RXNE interrupt */
<>	144:ef7eb2e8f9f7	1927	__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE));
<>	144:ef7eb2e8f9f7	1928
<>	144:ef7eb2e8f9f7	1929	/* if Transmit process is finished */
<>	144:ef7eb2e8f9f7	1930	if(__HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_TXE) == RESET)
<>	144:ef7eb2e8f9f7	1931	{
<>	144:ef7eb2e8f9f7	1932	/* Disable ERR interrupt */
<>	144:ef7eb2e8f9f7	1933	__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_ERR));
<>	144:ef7eb2e8f9f7	1934
<>	144:ef7eb2e8f9f7	1935	if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)\|\|(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
<>	144:ef7eb2e8f9f7	1936	{
<>	144:ef7eb2e8f9f7	1937	/* Disable SPI peripheral */
<>	144:ef7eb2e8f9f7	1938	__HAL_SPI_DISABLE(hspi);
<>	144:ef7eb2e8f9f7	1939	}
<>	144:ef7eb2e8f9f7	1940
<>	144:ef7eb2e8f9f7	1941	/* Check if Errors has been detected during transfer */
<>	144:ef7eb2e8f9f7	1942	if(hspi->ErrorCode == HAL_SPI_ERROR_NONE)
<>	144:ef7eb2e8f9f7	1943	{
<>	144:ef7eb2e8f9f7	1944	/* Check if we are in Rx or in Rx/Tx Mode */
<>	144:ef7eb2e8f9f7	1945	if(hspi->State == HAL_SPI_STATE_BUSY_TX_RX)
<>	144:ef7eb2e8f9f7	1946	{
<>	144:ef7eb2e8f9f7	1947	/* Set state to READY before run the Callback Complete */
<>	144:ef7eb2e8f9f7	1948	hspi->State = HAL_SPI_STATE_READY;
<>	144:ef7eb2e8f9f7	1949	HAL_SPI_TxRxCpltCallback(hspi);
<>	144:ef7eb2e8f9f7	1950	}
<>	144:ef7eb2e8f9f7	1951	else
<>	144:ef7eb2e8f9f7	1952	{
<>	144:ef7eb2e8f9f7	1953	/* Set state to READY before run the Callback Complete */
<>	144:ef7eb2e8f9f7	1954	hspi->State = HAL_SPI_STATE_READY;
<>	144:ef7eb2e8f9f7	1955	HAL_SPI_RxCpltCallback(hspi);
<>	144:ef7eb2e8f9f7	1956	}
<>	144:ef7eb2e8f9f7	1957	}
<>	144:ef7eb2e8f9f7	1958	else
<>	144:ef7eb2e8f9f7	1959	{
<>	144:ef7eb2e8f9f7	1960	/* Set state to READY before run the Callback Complete */
<>	144:ef7eb2e8f9f7	1961	hspi->State = HAL_SPI_STATE_READY;
<>	144:ef7eb2e8f9f7	1962	/* Call Error call back in case of Error */
<>	144:ef7eb2e8f9f7	1963	HAL_SPI_ErrorCallback(hspi);
<>	144:ef7eb2e8f9f7	1964	}
<>	144:ef7eb2e8f9f7	1965	}
<>	144:ef7eb2e8f9f7	1966	}
<>	144:ef7eb2e8f9f7	1967
<>	144:ef7eb2e8f9f7	1968	/**
<>	144:ef7eb2e8f9f7	1969	* @brief Interrupt Handler to receive amount of data in 2Lines mode
<>	144:ef7eb2e8f9f7	1970	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	1971	* the configuration information for SPI module.
<>	144:ef7eb2e8f9f7	1972	* @retval None
<>	144:ef7eb2e8f9f7	1973	*/
<>	144:ef7eb2e8f9f7	1974	static void SPI_2LinesRxISR(SPI_HandleTypeDef *hspi)
<>	144:ef7eb2e8f9f7	1975	{
<>	144:ef7eb2e8f9f7	1976	/* Receive data in 8 Bit mode */
<>	144:ef7eb2e8f9f7	1977	if(hspi->Init.DataSize == SPI_DATASIZE_8BIT)
<>	144:ef7eb2e8f9f7	1978	{
<>	144:ef7eb2e8f9f7	1979	(*hspi->pRxBuffPtr++) = hspi->Instance->DR;
<>	144:ef7eb2e8f9f7	1980	}
<>	144:ef7eb2e8f9f7	1981	/* Receive data in 16 Bit mode */
<>	144:ef7eb2e8f9f7	1982	else
<>	144:ef7eb2e8f9f7	1983	{
<>	144:ef7eb2e8f9f7	1984	((uint16_t)hspi->pRxBuffPtr) = hspi->Instance->DR;
<>	144:ef7eb2e8f9f7	1985	hspi->pRxBuffPtr+=2;
<>	144:ef7eb2e8f9f7	1986	}
<>	144:ef7eb2e8f9f7	1987	hspi->RxXferCount--;
<>	144:ef7eb2e8f9f7	1988
<>	144:ef7eb2e8f9f7	1989	if(hspi->RxXferCount==0)
<>	144:ef7eb2e8f9f7	1990	{
<>	144:ef7eb2e8f9f7	1991	SPI_RxCloseIRQHandler(hspi);
<>	144:ef7eb2e8f9f7	1992	}
<>	144:ef7eb2e8f9f7	1993	}
<>	144:ef7eb2e8f9f7	1994
<>	144:ef7eb2e8f9f7	1995	/**
<>	144:ef7eb2e8f9f7	1996	* @brief Interrupt Handler to receive amount of data in no-blocking mode
<>	144:ef7eb2e8f9f7	1997	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	1998	* the configuration information for SPI module.
<>	144:ef7eb2e8f9f7	1999	* @retval None
<>	144:ef7eb2e8f9f7	2000	*/
<>	144:ef7eb2e8f9f7	2001	static void SPI_RxISR(SPI_HandleTypeDef *hspi)
<>	144:ef7eb2e8f9f7	2002	{
<>	144:ef7eb2e8f9f7	2003	/* Receive data in 8 Bit mode */
<>	144:ef7eb2e8f9f7	2004	if(hspi->Init.DataSize == SPI_DATASIZE_8BIT)
<>	144:ef7eb2e8f9f7	2005	{
<>	144:ef7eb2e8f9f7	2006	(*hspi->pRxBuffPtr++) = hspi->Instance->DR;
<>	144:ef7eb2e8f9f7	2007	}
<>	144:ef7eb2e8f9f7	2008	/* Receive data in 16 Bit mode */
<>	144:ef7eb2e8f9f7	2009	else
<>	144:ef7eb2e8f9f7	2010	{
<>	144:ef7eb2e8f9f7	2011	((uint16_t)hspi->pRxBuffPtr) = hspi->Instance->DR;
<>	144:ef7eb2e8f9f7	2012	hspi->pRxBuffPtr+=2;
<>	144:ef7eb2e8f9f7	2013	}
<>	144:ef7eb2e8f9f7	2014	hspi->RxXferCount--;
<>	144:ef7eb2e8f9f7	2015
<>	144:ef7eb2e8f9f7	2016	/* Enable CRC Transmission */
<>	144:ef7eb2e8f9f7	2017	if((hspi->RxXferCount == 1) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
<>	144:ef7eb2e8f9f7	2018	{
<>	144:ef7eb2e8f9f7	2019	/* Set CRC Next to calculate CRC on Rx side */
<>	144:ef7eb2e8f9f7	2020	SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
<>	144:ef7eb2e8f9f7	2021	}
<>	144:ef7eb2e8f9f7	2022
<>	144:ef7eb2e8f9f7	2023	if(hspi->RxXferCount == 0)
<>	144:ef7eb2e8f9f7	2024	{
<>	144:ef7eb2e8f9f7	2025	SPI_RxCloseIRQHandler(hspi);
<>	144:ef7eb2e8f9f7	2026	}
<>	144:ef7eb2e8f9f7	2027	}
<>	144:ef7eb2e8f9f7	2028
<>	144:ef7eb2e8f9f7	2029	/**
<>	144:ef7eb2e8f9f7	2030	* @brief DMA SPI transmit process complete callback
<>	144:ef7eb2e8f9f7	2031	* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	2032	* the configuration information for the specified DMA module.
<>	144:ef7eb2e8f9f7	2033	* @retval None
<>	144:ef7eb2e8f9f7	2034	*/
<>	144:ef7eb2e8f9f7	2035	static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma)
<>	144:ef7eb2e8f9f7	2036	{
<>	144:ef7eb2e8f9f7	2037	SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<>	144:ef7eb2e8f9f7	2038
<>	144:ef7eb2e8f9f7	2039	/* DMA Normal Mode */
<>	144:ef7eb2e8f9f7	2040	if((hdma->Instance->CCR & DMA_CIRCULAR) == 0)
<>	144:ef7eb2e8f9f7	2041	{
<>	144:ef7eb2e8f9f7	2042	/* Wait until TXE flag is set to send data */
<>	144:ef7eb2e8f9f7	2043	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK)
<>	144:ef7eb2e8f9f7	2044	{
<>	144:ef7eb2e8f9f7	2045	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
<>	144:ef7eb2e8f9f7	2046	}
<>	144:ef7eb2e8f9f7	2047
<>	144:ef7eb2e8f9f7	2048	/* Disable Tx DMA Request */
<>	144:ef7eb2e8f9f7	2049	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
<>	144:ef7eb2e8f9f7	2050
<>	144:ef7eb2e8f9f7	2051	/* Wait until Busy flag is reset before disabling SPI */
<>	144:ef7eb2e8f9f7	2052	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_BSY, SET, SPI_TIMEOUT_VALUE) != HAL_OK)
<>	144:ef7eb2e8f9f7	2053	{
<>	144:ef7eb2e8f9f7	2054	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
<>	144:ef7eb2e8f9f7	2055	}
<>	144:ef7eb2e8f9f7	2056
<>	144:ef7eb2e8f9f7	2057	hspi->TxXferCount = 0;
<>	144:ef7eb2e8f9f7	2058	hspi->State = HAL_SPI_STATE_READY;
<>	144:ef7eb2e8f9f7	2059	}
<>	144:ef7eb2e8f9f7	2060
<>	144:ef7eb2e8f9f7	2061	/* Clear OVERUN flag in 2 Lines communication mode because received is not read */
<>	144:ef7eb2e8f9f7	2062	if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
<>	144:ef7eb2e8f9f7	2063	{
<>	144:ef7eb2e8f9f7	2064	__HAL_SPI_CLEAR_OVRFLAG(hspi);
<>	144:ef7eb2e8f9f7	2065	}
<>	144:ef7eb2e8f9f7	2066
<>	144:ef7eb2e8f9f7	2067	/* Check if Errors has been detected during transfer */
<>	144:ef7eb2e8f9f7	2068	if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
<>	144:ef7eb2e8f9f7	2069	{
<>	144:ef7eb2e8f9f7	2070	HAL_SPI_ErrorCallback(hspi);
<>	144:ef7eb2e8f9f7	2071	}
<>	144:ef7eb2e8f9f7	2072	else
<>	144:ef7eb2e8f9f7	2073	{
<>	144:ef7eb2e8f9f7	2074	HAL_SPI_TxCpltCallback(hspi);
<>	144:ef7eb2e8f9f7	2075	}
<>	144:ef7eb2e8f9f7	2076	}
<>	144:ef7eb2e8f9f7	2077
<>	144:ef7eb2e8f9f7	2078	/**
<>	144:ef7eb2e8f9f7	2079	* @brief DMA SPI receive process complete callback
<>	144:ef7eb2e8f9f7	2080	* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	2081	* the configuration information for the specified DMA module.
<>	144:ef7eb2e8f9f7	2082	* @retval None
<>	144:ef7eb2e8f9f7	2083	*/
<>	144:ef7eb2e8f9f7	2084	static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
<>	144:ef7eb2e8f9f7	2085	{
<>	144:ef7eb2e8f9f7	2086	__IO uint16_t tmpreg = 0;
<>	144:ef7eb2e8f9f7	2087	SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<>	144:ef7eb2e8f9f7	2088
<>	144:ef7eb2e8f9f7	2089	/* DMA Normal mode */
<>	144:ef7eb2e8f9f7	2090	if((hdma->Instance->CCR & DMA_CIRCULAR) == 0)
<>	144:ef7eb2e8f9f7	2091	{
<>	144:ef7eb2e8f9f7	2092	/* Disable Rx DMA Request */
<>	144:ef7eb2e8f9f7	2093	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
<>	144:ef7eb2e8f9f7	2094
<>	144:ef7eb2e8f9f7	2095	/* Disable Tx DMA Request (done by default to handle the case Master RX direction 2 lines) */
<>	144:ef7eb2e8f9f7	2096	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
<>	144:ef7eb2e8f9f7	2097
<>	144:ef7eb2e8f9f7	2098	/* CRC Calculation handling */
<>	144:ef7eb2e8f9f7	2099	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<>	144:ef7eb2e8f9f7	2100	{
<>	144:ef7eb2e8f9f7	2101	/* Wait until RXNE flag is set (CRC ready) */
<>	144:ef7eb2e8f9f7	2102	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK)
<>	144:ef7eb2e8f9f7	2103	{
<>	144:ef7eb2e8f9f7	2104	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
<>	144:ef7eb2e8f9f7	2105	}
<>	144:ef7eb2e8f9f7	2106
<>	144:ef7eb2e8f9f7	2107	/* Read CRC */
<>	144:ef7eb2e8f9f7	2108	tmpreg = hspi->Instance->DR;
<>	144:ef7eb2e8f9f7	2109	UNUSED(tmpreg);
<>	144:ef7eb2e8f9f7	2110
<>	144:ef7eb2e8f9f7	2111	/* Wait until RXNE flag is reset */
<>	144:ef7eb2e8f9f7	2112	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_TIMEOUT_VALUE) != HAL_OK)
<>	144:ef7eb2e8f9f7	2113	{
<>	144:ef7eb2e8f9f7	2114	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
<>	144:ef7eb2e8f9f7	2115	}
<>	144:ef7eb2e8f9f7	2116
<>	144:ef7eb2e8f9f7	2117	/* Check if CRC error occurred */
<>	144:ef7eb2e8f9f7	2118	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
<>	144:ef7eb2e8f9f7	2119	{
<>	144:ef7eb2e8f9f7	2120	/* Check if CRC error is valid or not (workaround to be applied or not) */
<>	144:ef7eb2e8f9f7	2121	if (SPI_ISCRCErrorValid(hspi) == SPI_VALID_CRC_ERROR)
<>	144:ef7eb2e8f9f7	2122	{
<>	144:ef7eb2e8f9f7	2123	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
<>	144:ef7eb2e8f9f7	2124
<>	144:ef7eb2e8f9f7	2125	/* Reset CRC Calculation */
<>	144:ef7eb2e8f9f7	2126	SPI_RESET_CRC(hspi);
<>	144:ef7eb2e8f9f7	2127	}
<>	144:ef7eb2e8f9f7	2128	__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
<>	144:ef7eb2e8f9f7	2129	}
<>	144:ef7eb2e8f9f7	2130	}
<>	144:ef7eb2e8f9f7	2131
<>	144:ef7eb2e8f9f7	2132	if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)\|\|(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
<>	144:ef7eb2e8f9f7	2133	{
<>	144:ef7eb2e8f9f7	2134	/* Disable SPI peripheral */
<>	144:ef7eb2e8f9f7	2135	__HAL_SPI_DISABLE(hspi);
<>	144:ef7eb2e8f9f7	2136	}
<>	144:ef7eb2e8f9f7	2137
<>	144:ef7eb2e8f9f7	2138	hspi->RxXferCount = 0;
<>	144:ef7eb2e8f9f7	2139	hspi->State = HAL_SPI_STATE_READY;
<>	144:ef7eb2e8f9f7	2140
<>	144:ef7eb2e8f9f7	2141	/* Check if Errors has been detected during transfer */
<>	144:ef7eb2e8f9f7	2142	if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
<>	144:ef7eb2e8f9f7	2143	{
<>	144:ef7eb2e8f9f7	2144	HAL_SPI_ErrorCallback(hspi);
<>	144:ef7eb2e8f9f7	2145	}
<>	144:ef7eb2e8f9f7	2146	else
<>	144:ef7eb2e8f9f7	2147	{
<>	144:ef7eb2e8f9f7	2148	HAL_SPI_RxCpltCallback(hspi);
<>	144:ef7eb2e8f9f7	2149	}
<>	144:ef7eb2e8f9f7	2150	}
<>	144:ef7eb2e8f9f7	2151	else
<>	144:ef7eb2e8f9f7	2152	{
<>	144:ef7eb2e8f9f7	2153	HAL_SPI_RxCpltCallback(hspi);
<>	144:ef7eb2e8f9f7	2154	}
<>	144:ef7eb2e8f9f7	2155	}
<>	144:ef7eb2e8f9f7	2156
<>	144:ef7eb2e8f9f7	2157	/**
<>	144:ef7eb2e8f9f7	2158	* @brief DMA SPI transmit receive process complete callback
<>	144:ef7eb2e8f9f7	2159	* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	2160	* the configuration information for the specified DMA module.
<>	144:ef7eb2e8f9f7	2161	* @retval None
<>	144:ef7eb2e8f9f7	2162	*/
<>	144:ef7eb2e8f9f7	2163	static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma)
<>	144:ef7eb2e8f9f7	2164	{
<>	144:ef7eb2e8f9f7	2165	__IO uint16_t tmpreg = 0;
<>	144:ef7eb2e8f9f7	2166
<>	144:ef7eb2e8f9f7	2167	SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<>	144:ef7eb2e8f9f7	2168
<>	144:ef7eb2e8f9f7	2169	if((hdma->Instance->CCR & DMA_CIRCULAR) == 0)
<>	144:ef7eb2e8f9f7	2170	{
<>	144:ef7eb2e8f9f7	2171	/* CRC Calculation handling */
<>	144:ef7eb2e8f9f7	2172	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<>	144:ef7eb2e8f9f7	2173	{
<>	144:ef7eb2e8f9f7	2174	/* Check if CRC is done on going (RXNE flag set) */
<>	144:ef7eb2e8f9f7	2175	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_TIMEOUT_VALUE) == HAL_OK)
<>	144:ef7eb2e8f9f7	2176	{
<>	144:ef7eb2e8f9f7	2177	/* Wait until RXNE flag is set to send data */
<>	144:ef7eb2e8f9f7	2178	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK)
<>	144:ef7eb2e8f9f7	2179	{
<>	144:ef7eb2e8f9f7	2180	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
<>	144:ef7eb2e8f9f7	2181	}
<>	144:ef7eb2e8f9f7	2182	}
<>	144:ef7eb2e8f9f7	2183	/* Read CRC */
<>	144:ef7eb2e8f9f7	2184	tmpreg = hspi->Instance->DR;
<>	144:ef7eb2e8f9f7	2185	UNUSED(tmpreg);
<>	144:ef7eb2e8f9f7	2186
<>	144:ef7eb2e8f9f7	2187	/* Check if CRC error occurred */
<>	144:ef7eb2e8f9f7	2188	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
<>	144:ef7eb2e8f9f7	2189	{
<>	144:ef7eb2e8f9f7	2190	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
<>	144:ef7eb2e8f9f7	2191	__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
<>	144:ef7eb2e8f9f7	2192	}
<>	144:ef7eb2e8f9f7	2193	}
<>	144:ef7eb2e8f9f7	2194
<>	144:ef7eb2e8f9f7	2195	/* Wait until TXE flag is set to send data */
<>	144:ef7eb2e8f9f7	2196	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK)
<>	144:ef7eb2e8f9f7	2197	{
<>	144:ef7eb2e8f9f7	2198	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
<>	144:ef7eb2e8f9f7	2199	}
<>	144:ef7eb2e8f9f7	2200
<>	144:ef7eb2e8f9f7	2201	/* Disable Tx DMA Request */
<>	144:ef7eb2e8f9f7	2202	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
<>	144:ef7eb2e8f9f7	2203
<>	144:ef7eb2e8f9f7	2204	/* Wait until Busy flag is reset before disabling SPI */
<>	144:ef7eb2e8f9f7	2205	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_BSY, SET, SPI_TIMEOUT_VALUE) != HAL_OK)
<>	144:ef7eb2e8f9f7	2206	{
<>	144:ef7eb2e8f9f7	2207	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
<>	144:ef7eb2e8f9f7	2208	}
<>	144:ef7eb2e8f9f7	2209
<>	144:ef7eb2e8f9f7	2210	/* Disable Rx DMA Request */
<>	144:ef7eb2e8f9f7	2211	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
<>	144:ef7eb2e8f9f7	2212
<>	144:ef7eb2e8f9f7	2213	hspi->TxXferCount = 0;
<>	144:ef7eb2e8f9f7	2214	hspi->RxXferCount = 0;
<>	144:ef7eb2e8f9f7	2215
<>	144:ef7eb2e8f9f7	2216	hspi->State = HAL_SPI_STATE_READY;
<>	144:ef7eb2e8f9f7	2217
<>	144:ef7eb2e8f9f7	2218	/* Check if Errors has been detected during transfer */
<>	144:ef7eb2e8f9f7	2219	if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
<>	144:ef7eb2e8f9f7	2220	{
<>	144:ef7eb2e8f9f7	2221	HAL_SPI_ErrorCallback(hspi);
<>	144:ef7eb2e8f9f7	2222	}
<>	144:ef7eb2e8f9f7	2223	else
<>	144:ef7eb2e8f9f7	2224	{
<>	144:ef7eb2e8f9f7	2225	HAL_SPI_TxRxCpltCallback(hspi);
<>	144:ef7eb2e8f9f7	2226	}
<>	144:ef7eb2e8f9f7	2227	}
<>	144:ef7eb2e8f9f7	2228	else
<>	144:ef7eb2e8f9f7	2229	{
<>	144:ef7eb2e8f9f7	2230	HAL_SPI_TxRxCpltCallback(hspi);
<>	144:ef7eb2e8f9f7	2231	}
<>	144:ef7eb2e8f9f7	2232	}
<>	144:ef7eb2e8f9f7	2233
<>	144:ef7eb2e8f9f7	2234	/**
<>	144:ef7eb2e8f9f7	2235	* @brief DMA SPI half transmit process complete callback
<>	144:ef7eb2e8f9f7	2236	* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	2237	* the configuration information for the specified DMA module.
<>	144:ef7eb2e8f9f7	2238	* @retval None
<>	144:ef7eb2e8f9f7	2239	*/
<>	144:ef7eb2e8f9f7	2240	static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma)
<>	144:ef7eb2e8f9f7	2241	{
<>	144:ef7eb2e8f9f7	2242	SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<>	144:ef7eb2e8f9f7	2243
<>	144:ef7eb2e8f9f7	2244	HAL_SPI_TxHalfCpltCallback(hspi);
<>	144:ef7eb2e8f9f7	2245	}
<>	144:ef7eb2e8f9f7	2246
<>	144:ef7eb2e8f9f7	2247	/**
<>	144:ef7eb2e8f9f7	2248	* @brief DMA SPI half receive process complete callback
<>	144:ef7eb2e8f9f7	2249	* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	2250	* the configuration information for the specified DMA module.
<>	144:ef7eb2e8f9f7	2251	* @retval None
<>	144:ef7eb2e8f9f7	2252	*/
<>	144:ef7eb2e8f9f7	2253	static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma)
<>	144:ef7eb2e8f9f7	2254	{
<>	144:ef7eb2e8f9f7	2255	SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<>	144:ef7eb2e8f9f7	2256
<>	144:ef7eb2e8f9f7	2257	HAL_SPI_RxHalfCpltCallback(hspi);
<>	144:ef7eb2e8f9f7	2258	}
<>	144:ef7eb2e8f9f7	2259
<>	144:ef7eb2e8f9f7	2260	/**
<>	144:ef7eb2e8f9f7	2261	* @brief DMA SPI Half transmit receive process complete callback
<>	144:ef7eb2e8f9f7	2262	* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	2263	* the configuration information for the specified DMA module.
<>	144:ef7eb2e8f9f7	2264	* @retval None
<>	144:ef7eb2e8f9f7	2265	*/
<>	144:ef7eb2e8f9f7	2266	static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma)
<>	144:ef7eb2e8f9f7	2267	{
<>	144:ef7eb2e8f9f7	2268	SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<>	144:ef7eb2e8f9f7	2269
<>	144:ef7eb2e8f9f7	2270	HAL_SPI_TxRxHalfCpltCallback(hspi);
<>	144:ef7eb2e8f9f7	2271	}
<>	144:ef7eb2e8f9f7	2272
<>	144:ef7eb2e8f9f7	2273	/**
<>	144:ef7eb2e8f9f7	2274	* @brief DMA SPI communication error callback
<>	144:ef7eb2e8f9f7	2275	* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	2276	* the configuration information for the specified DMA module.
<>	144:ef7eb2e8f9f7	2277	* @retval None
<>	144:ef7eb2e8f9f7	2278	*/
<>	144:ef7eb2e8f9f7	2279	static void SPI_DMAError(DMA_HandleTypeDef *hdma)
<>	144:ef7eb2e8f9f7	2280	{
<>	144:ef7eb2e8f9f7	2281	SPI_HandleTypeDef* hspi = (SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<>	144:ef7eb2e8f9f7	2282	hspi->TxXferCount = 0;
<>	144:ef7eb2e8f9f7	2283	hspi->RxXferCount = 0;
<>	144:ef7eb2e8f9f7	2284	hspi->State= HAL_SPI_STATE_READY;
<>	144:ef7eb2e8f9f7	2285	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
<>	144:ef7eb2e8f9f7	2286	HAL_SPI_ErrorCallback(hspi);
<>	144:ef7eb2e8f9f7	2287	}
<>	144:ef7eb2e8f9f7	2288
<>	144:ef7eb2e8f9f7	2289	/**
<>	144:ef7eb2e8f9f7	2290	* @brief This function handles SPI Communication Timeout.
<>	144:ef7eb2e8f9f7	2291	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	2292	* the configuration information for SPI module.
<>	144:ef7eb2e8f9f7	2293	* @param Flag: SPI flag to check
<>	144:ef7eb2e8f9f7	2294	* @param Status: Flag status to check: RESET or set
<>	144:ef7eb2e8f9f7	2295	* @param Timeout: Timeout duration
<>	144:ef7eb2e8f9f7	2296	* @retval HAL status
<>	144:ef7eb2e8f9f7	2297	*/
<>	144:ef7eb2e8f9f7	2298	static HAL_StatusTypeDef SPI_WaitOnFlagUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
<>	144:ef7eb2e8f9f7	2299	{
<>	144:ef7eb2e8f9f7	2300	uint32_t tickstart = 0;
<>	144:ef7eb2e8f9f7	2301
<>	144:ef7eb2e8f9f7	2302	/* Get tick */
<>	144:ef7eb2e8f9f7	2303	tickstart = HAL_GetTick();
<>	144:ef7eb2e8f9f7	2304
<>	144:ef7eb2e8f9f7	2305	/* Wait until flag is set */
<>	144:ef7eb2e8f9f7	2306	if(Status == RESET)
<>	144:ef7eb2e8f9f7	2307	{
<>	144:ef7eb2e8f9f7	2308	while(__HAL_SPI_GET_FLAG(hspi, Flag) == RESET)
<>	144:ef7eb2e8f9f7	2309	{
<>	144:ef7eb2e8f9f7	2310	if(Timeout != HAL_MAX_DELAY)
<>	144:ef7eb2e8f9f7	2311	{
<>	144:ef7eb2e8f9f7	2312	if((Timeout == 0) \|\| ((HAL_GetTick() - tickstart ) > Timeout))
<>	144:ef7eb2e8f9f7	2313	{
<>	144:ef7eb2e8f9f7	2314	/* Disable the SPI and reset the CRC: the CRC value should be cleared
<>	144:ef7eb2e8f9f7	2315	on both master and slave sides in order to resynchronize the master
<>	144:ef7eb2e8f9f7	2316	and slave for their respective CRC calculation */
<>	144:ef7eb2e8f9f7	2317
<>	144:ef7eb2e8f9f7	2318	/* Disable TXE, RXNE and ERR interrupts for the interrupt process */
<>	144:ef7eb2e8f9f7	2319	__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE \| SPI_IT_RXNE \| SPI_IT_ERR));
<>	144:ef7eb2e8f9f7	2320
<>	144:ef7eb2e8f9f7	2321	/* Disable SPI peripheral */
<>	144:ef7eb2e8f9f7	2322	__HAL_SPI_DISABLE(hspi);
<>	144:ef7eb2e8f9f7	2323
<>	144:ef7eb2e8f9f7	2324	/* Reset CRC Calculation */
<>	144:ef7eb2e8f9f7	2325	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<>	144:ef7eb2e8f9f7	2326	{
<>	144:ef7eb2e8f9f7	2327	SPI_RESET_CRC(hspi);
<>	144:ef7eb2e8f9f7	2328	}
<>	144:ef7eb2e8f9f7	2329
<>	144:ef7eb2e8f9f7	2330	hspi->State= HAL_SPI_STATE_READY;
<>	144:ef7eb2e8f9f7	2331
<>	144:ef7eb2e8f9f7	2332	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	2333	__HAL_UNLOCK(hspi);
<>	144:ef7eb2e8f9f7	2334
<>	144:ef7eb2e8f9f7	2335	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	2336	}
<>	144:ef7eb2e8f9f7	2337	}
<>	144:ef7eb2e8f9f7	2338	}
<>	144:ef7eb2e8f9f7	2339	}
<>	144:ef7eb2e8f9f7	2340	else
<>	144:ef7eb2e8f9f7	2341	{
<>	144:ef7eb2e8f9f7	2342	while(__HAL_SPI_GET_FLAG(hspi, Flag) != RESET)
<>	144:ef7eb2e8f9f7	2343	{
<>	144:ef7eb2e8f9f7	2344	if(Timeout != HAL_MAX_DELAY)
<>	144:ef7eb2e8f9f7	2345	{
<>	144:ef7eb2e8f9f7	2346	if((Timeout == 0) \|\| ((HAL_GetTick() - tickstart ) > Timeout))
<>	144:ef7eb2e8f9f7	2347	{
<>	144:ef7eb2e8f9f7	2348	/* Disable the SPI and reset the CRC: the CRC value should be cleared
<>	144:ef7eb2e8f9f7	2349	on both master and slave sides in order to resynchronize the master
<>	144:ef7eb2e8f9f7	2350	and slave for their respective CRC calculation */
<>	144:ef7eb2e8f9f7	2351
<>	144:ef7eb2e8f9f7	2352	/* Disable TXE, RXNE and ERR interrupts for the interrupt process */
<>	144:ef7eb2e8f9f7	2353	__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE \| SPI_IT_RXNE \| SPI_IT_ERR));
<>	144:ef7eb2e8f9f7	2354
<>	144:ef7eb2e8f9f7	2355	/* Disable SPI peripheral */
<>	144:ef7eb2e8f9f7	2356	__HAL_SPI_DISABLE(hspi);
<>	144:ef7eb2e8f9f7	2357
<>	144:ef7eb2e8f9f7	2358	/* Reset CRC Calculation */
<>	144:ef7eb2e8f9f7	2359	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<>	144:ef7eb2e8f9f7	2360	{
<>	144:ef7eb2e8f9f7	2361	SPI_RESET_CRC(hspi);
<>	144:ef7eb2e8f9f7	2362	}
<>	144:ef7eb2e8f9f7	2363
<>	144:ef7eb2e8f9f7	2364	hspi->State= HAL_SPI_STATE_READY;
<>	144:ef7eb2e8f9f7	2365
<>	144:ef7eb2e8f9f7	2366	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	2367	__HAL_UNLOCK(hspi);
<>	144:ef7eb2e8f9f7	2368
<>	144:ef7eb2e8f9f7	2369	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	2370	}
<>	144:ef7eb2e8f9f7	2371	}
<>	144:ef7eb2e8f9f7	2372	}
<>	144:ef7eb2e8f9f7	2373	}
<>	144:ef7eb2e8f9f7	2374	return HAL_OK;
<>	144:ef7eb2e8f9f7	2375	}
<>	144:ef7eb2e8f9f7	2376
<>	144:ef7eb2e8f9f7	2377	/**
<>	144:ef7eb2e8f9f7	2378	* @}
<>	144:ef7eb2e8f9f7	2379	*/
<>	144:ef7eb2e8f9f7	2380
<>	144:ef7eb2e8f9f7	2381	/** @addtogroup SPI_Private_Functions
<>	144:ef7eb2e8f9f7	2382	* @{
<>	144:ef7eb2e8f9f7	2383	*/
<>	144:ef7eb2e8f9f7	2384
<>	144:ef7eb2e8f9f7	2385	/**
<>	144:ef7eb2e8f9f7	2386	* @brief Checks if encountered CRC error could be corresponding to wrongly detected errors
<>	144:ef7eb2e8f9f7	2387	* according to SPI instance, Device type, and revision ID.
<>	144:ef7eb2e8f9f7	2388	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	2389	* the configuration information for SPI module.
<>	144:ef7eb2e8f9f7	2390	* @retval CRC error validity (SPI_INVALID_CRC_ERROR or SPI_VALID_CRC_ERROR).
<>	144:ef7eb2e8f9f7	2391	*/
<>	144:ef7eb2e8f9f7	2392	__weak uint8_t SPI_ISCRCErrorValid(SPI_HandleTypeDef *hspi)
<>	144:ef7eb2e8f9f7	2393	{
<>	144:ef7eb2e8f9f7	2394	return (SPI_VALID_CRC_ERROR);
<>	144:ef7eb2e8f9f7	2395	}
<>	144:ef7eb2e8f9f7	2396	/**
<>	144:ef7eb2e8f9f7	2397	* @}
<>	144:ef7eb2e8f9f7	2398	*/
<>	144:ef7eb2e8f9f7	2399
<>	144:ef7eb2e8f9f7	2400
<>	144:ef7eb2e8f9f7	2401	#endif /* HAL_SPI_MODULE_ENABLED */
<>	144:ef7eb2e8f9f7	2402	/**
<>	144:ef7eb2e8f9f7	2403	* @}
<>	144:ef7eb2e8f9f7	2404	*/
<>	144:ef7eb2e8f9f7	2405
<>	144:ef7eb2e8f9f7	2406	/**
<>	144:ef7eb2e8f9f7	2407	* @}
<>	144:ef7eb2e8f9f7	2408	*/
<>	144:ef7eb2e8f9f7	2409
<>	144:ef7eb2e8f9f7	2410	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/