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targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/TOOLCHAIN_GCC_ARM/startup_RZ1AH.S@181:57724642e740, 2018-02-16 (annotated)

Committer:
AnnaBridge
Date:
Fri Feb 16 16:09:33 2018 +0000
Revision:
181:57724642e740
Parent:
targets/TARGET_RENESAS/TARGET_RZ_A1H/device/TOOLCHAIN_GCC_ARM/startup_RZ1AH.S@180:96ed750bd169
Child:
189:f392fc9709a3
mbed-dev library. Release version 159.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /* File: startup_ARMCM3.s
<> 144:ef7eb2e8f9f7 2 * Purpose: startup file for Cortex-M3/M4 devices. Should use with
<> 144:ef7eb2e8f9f7 3 * GNU Tools for ARM Embedded Processors
<> 144:ef7eb2e8f9f7 4 * Version: V1.1
<> 144:ef7eb2e8f9f7 5 * Date: 17 June 2011
<> 144:ef7eb2e8f9f7 6 *
<> 144:ef7eb2e8f9f7 7 * Copyright (C) 2011 ARM Limited. All rights reserved.
<> 144:ef7eb2e8f9f7 8 * ARM Limited (ARM) is supplying this software for use with Cortex-M3/M4
<> 144:ef7eb2e8f9f7 9 * processor based microcontrollers. This file can be freely distributed
<> 144:ef7eb2e8f9f7 10 * within development tools that are supporting such ARM based processors.
<> 144:ef7eb2e8f9f7 11 *
<> 144:ef7eb2e8f9f7 12 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
<> 144:ef7eb2e8f9f7 13 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
<> 144:ef7eb2e8f9f7 14 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
<> 144:ef7eb2e8f9f7 15 * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
<> 144:ef7eb2e8f9f7 16 * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
<> 144:ef7eb2e8f9f7 17 */
<> 144:ef7eb2e8f9f7 18 .syntax unified
<> 144:ef7eb2e8f9f7 19 .extern _start
<> 144:ef7eb2e8f9f7 20
<> 144:ef7eb2e8f9f7 21 @ Standard definitions of mode bits and interrupt (I & F) flags in PSRs
<> 144:ef7eb2e8f9f7 22 .equ Mode_USR , 0x10
<> 144:ef7eb2e8f9f7 23 .equ Mode_FIQ , 0x11
<> 144:ef7eb2e8f9f7 24 .equ Mode_IRQ , 0x12
<> 144:ef7eb2e8f9f7 25 .equ Mode_SVC , 0x13
<> 144:ef7eb2e8f9f7 26 .equ Mode_ABT , 0x17
<> 144:ef7eb2e8f9f7 27 .equ Mode_UND , 0x1B
<> 144:ef7eb2e8f9f7 28 .equ Mode_SYS , 0x1F
<> 144:ef7eb2e8f9f7 29
<> 144:ef7eb2e8f9f7 30 .equ I_Bit , 0x80 @ when I bit is set, IRQ is disabled
<> 144:ef7eb2e8f9f7 31 .equ F_Bit , 0x40 @ when F bit is set, FIQ is disabled
<> 144:ef7eb2e8f9f7 32 .equ T_Bit , 0x20 @ when T bit is set, core is in Thumb state
Anna Bridge 180:96ed750bd169 33
<> 144:ef7eb2e8f9f7 34 @ Stack Configuration
<> 144:ef7eb2e8f9f7 35
<> 144:ef7eb2e8f9f7 36 .EQU UND_Stack_Size , 0x00000100
<> 144:ef7eb2e8f9f7 37 .EQU SVC_Stack_Size , 0x00008000
<> 144:ef7eb2e8f9f7 38 .EQU ABT_Stack_Size , 0x00000100
<> 144:ef7eb2e8f9f7 39 .EQU FIQ_Stack_Size , 0x00000100
Anna Bridge 180:96ed750bd169 40 .EQU IRQ_Stack_Size , 0x0000F000
<> 144:ef7eb2e8f9f7 41
<> 144:ef7eb2e8f9f7 42 .EQU ISR_Stack_Size, (UND_Stack_Size + SVC_Stack_Size + ABT_Stack_Size + FIQ_Stack_Size + IRQ_Stack_Size)
<> 144:ef7eb2e8f9f7 43
<> 144:ef7eb2e8f9f7 44 .section .stack
<> 144:ef7eb2e8f9f7 45 .align 3
<> 144:ef7eb2e8f9f7 46 .globl __StackTop
<> 144:ef7eb2e8f9f7 47 .globl __StackLimit
<> 144:ef7eb2e8f9f7 48 __StackLimit:
<> 144:ef7eb2e8f9f7 49 .space ISR_Stack_Size
<> 144:ef7eb2e8f9f7 50 __initial_sp:
<> 144:ef7eb2e8f9f7 51 .size __StackLimit, . - __StackLimit
<> 144:ef7eb2e8f9f7 52 __StackTop:
<> 144:ef7eb2e8f9f7 53 .size __StackTop, . - __StackTop
<> 144:ef7eb2e8f9f7 54
<> 144:ef7eb2e8f9f7 55
<> 144:ef7eb2e8f9f7 56 @ Heap Configuration
<> 144:ef7eb2e8f9f7 57
<> 144:ef7eb2e8f9f7 58 .EQU Heap_Size , 0x00080000
<> 144:ef7eb2e8f9f7 59
<> 144:ef7eb2e8f9f7 60 .section .heap
<> 144:ef7eb2e8f9f7 61 .align 3
<> 144:ef7eb2e8f9f7 62 .globl __HeapBase
<> 144:ef7eb2e8f9f7 63 .globl __HeapLimit
<> 144:ef7eb2e8f9f7 64 __HeapBase:
<> 144:ef7eb2e8f9f7 65 .space Heap_Size
<> 144:ef7eb2e8f9f7 66 .size __HeapBase, . - __HeapBase
<> 144:ef7eb2e8f9f7 67 __HeapLimit:
<> 144:ef7eb2e8f9f7 68 .size __HeapLimit, . - __HeapLimit
<> 144:ef7eb2e8f9f7 69
<> 144:ef7eb2e8f9f7 70
<> 144:ef7eb2e8f9f7 71 .section .isr_vector
<> 144:ef7eb2e8f9f7 72 .align 2
<> 144:ef7eb2e8f9f7 73 .globl __isr_vector
<> 144:ef7eb2e8f9f7 74 __isr_vector:
<> 144:ef7eb2e8f9f7 75 .long 0xe59ff018 /* 0x00 */
<> 144:ef7eb2e8f9f7 76 .long 0xe59ff018 /* 0x04 */
<> 144:ef7eb2e8f9f7 77 .long 0xe59ff018 /* 0x08 */
<> 144:ef7eb2e8f9f7 78 .long 0xe59ff018 /* 0x0c */
<> 144:ef7eb2e8f9f7 79 .long 0xe59ff018 /* 0x10 */
<> 144:ef7eb2e8f9f7 80 .long 0xe59ff018 /* 0x14 */
<> 144:ef7eb2e8f9f7 81 .long 0xe59ff018 /* 0x18 */
<> 144:ef7eb2e8f9f7 82 .long 0xe59ff018 /* 0x1c */
<> 144:ef7eb2e8f9f7 83
<> 144:ef7eb2e8f9f7 84 .long Reset_Handler /* 0x20 */
<> 144:ef7eb2e8f9f7 85 .long Undef_Handler /* 0x24 */
<> 144:ef7eb2e8f9f7 86 .long SVC_Handler /* 0x28 */
<> 144:ef7eb2e8f9f7 87 .long PAbt_Handler /* 0x2c */
<> 144:ef7eb2e8f9f7 88 .long DAbt_Handler /* 0x30 */
<> 144:ef7eb2e8f9f7 89 .long 0 /* Reserved */
<> 144:ef7eb2e8f9f7 90 .long IRQ_Handler /* IRQ */
<> 144:ef7eb2e8f9f7 91 .long FIQ_Handler /* FIQ */
<> 144:ef7eb2e8f9f7 92
<> 144:ef7eb2e8f9f7 93
<> 144:ef7eb2e8f9f7 94 .size __isr_vector, . - __isr_vector
<> 144:ef7eb2e8f9f7 95
<> 144:ef7eb2e8f9f7 96 .text
<> 144:ef7eb2e8f9f7 97 .align 2
Anna Bridge 180:96ed750bd169 98 .globl Reset_Handler
<> 144:ef7eb2e8f9f7 99 .type Reset_Handler, %function
<> 144:ef7eb2e8f9f7 100 Reset_Handler:
Anna Bridge 180:96ed750bd169 101 @ Mask interrupts
Anna Bridge 180:96ed750bd169 102 CPSID if
Anna Bridge 180:96ed750bd169 103
<> 144:ef7eb2e8f9f7 104 @ Put any cores other than 0 to sleep
<> 144:ef7eb2e8f9f7 105 mrc p15, 0, r0, c0, c0, 5 @ Read MPIDR
<> 144:ef7eb2e8f9f7 106 ands r0, r0, #3
<> 144:ef7eb2e8f9f7 107 goToSleep:
<> 144:ef7eb2e8f9f7 108 wfine
<> 144:ef7eb2e8f9f7 109 bne goToSleep
<> 144:ef7eb2e8f9f7 110
Anna Bridge 180:96ed750bd169 111 @ Reset SCTLR Settings
<> 144:ef7eb2e8f9f7 112 mrc p15, 0, r0, c1, c0, 0 @ Read CP15 System Control register
<> 144:ef7eb2e8f9f7 113 bic r0, r0, #(0x1 << 12) @ Clear I bit 12 to disable I Cache
<> 144:ef7eb2e8f9f7 114 bic r0, r0, #(0x1 << 2) @ Clear C bit 2 to disable D Cache
<> 144:ef7eb2e8f9f7 115 bic r0, r0, #0x1 @ Clear M bit 0 to disable MMU
<> 144:ef7eb2e8f9f7 116 bic r0, r0, #(0x1 << 11) @ Clear Z bit 11 to disable branch prediction
<> 144:ef7eb2e8f9f7 117 bic r0, r0, #(0x1 << 13) @ Clear V bit 13 to disable hivecs
<> 144:ef7eb2e8f9f7 118 mcr p15, 0, r0, c1, c0, 0 @ Write value back to CP15 System Control register
<> 144:ef7eb2e8f9f7 119 isb
<> 144:ef7eb2e8f9f7 120
Anna Bridge 180:96ed750bd169 121 @ Configure ACTLR
Anna Bridge 180:96ed750bd169 122 MRC p15, 0, r0, c1, c0, 1 @ Read CP15 Auxiliary Control Register
Anna Bridge 180:96ed750bd169 123 ORR r0, r0, #(1 << 1) @ Enable L2 prefetch hint (UNK/WI since r4p1)
Anna Bridge 180:96ed750bd169 124 MCR p15, 0, r0, c1, c0, 1 @ Write CP15 Auxiliary Control Register
Anna Bridge 180:96ed750bd169 125
Anna Bridge 180:96ed750bd169 126 @ Set Vector Base Address Register (VBAR) to point to this application's vector table
<> 144:ef7eb2e8f9f7 127 ldr r0, =__isr_vector
<> 144:ef7eb2e8f9f7 128 mcr p15, 0, r0, c12, c0, 0
<> 144:ef7eb2e8f9f7 129
<> 144:ef7eb2e8f9f7 130 @ Setup Stack for each exceptional mode
Anna Bridge 180:96ed750bd169 131 ldr r0, =__StackTop
<> 144:ef7eb2e8f9f7 132
<> 144:ef7eb2e8f9f7 133 @ Enter Undefined Instruction Mode and set its Stack Pointer
<> 144:ef7eb2e8f9f7 134 msr cpsr_c, #(Mode_UND | I_Bit | F_Bit)
<> 144:ef7eb2e8f9f7 135 mov sp, r0
<> 144:ef7eb2e8f9f7 136 sub r0, r0, #UND_Stack_Size
<> 144:ef7eb2e8f9f7 137
<> 144:ef7eb2e8f9f7 138 @ Enter Abort Mode and set its Stack Pointer
<> 144:ef7eb2e8f9f7 139 msr cpsr_c, #(Mode_ABT | I_Bit | F_Bit)
<> 144:ef7eb2e8f9f7 140 mov sp, r0
<> 144:ef7eb2e8f9f7 141 sub r0, r0, #ABT_Stack_Size
<> 144:ef7eb2e8f9f7 142
<> 144:ef7eb2e8f9f7 143 @ Enter FIQ Mode and set its Stack Pointer
<> 144:ef7eb2e8f9f7 144 msr cpsr_c, #(Mode_FIQ | I_Bit | F_Bit)
<> 144:ef7eb2e8f9f7 145 mov sp, r0
<> 144:ef7eb2e8f9f7 146 sub r0, r0, #FIQ_Stack_Size
<> 144:ef7eb2e8f9f7 147
<> 144:ef7eb2e8f9f7 148 @ Enter IRQ Mode and set its Stack Pointer
<> 144:ef7eb2e8f9f7 149 msr cpsr_c, #(Mode_IRQ | I_Bit | F_Bit)
<> 144:ef7eb2e8f9f7 150 mov sp, r0
<> 144:ef7eb2e8f9f7 151 sub r0, r0, #IRQ_Stack_Size
<> 144:ef7eb2e8f9f7 152
<> 144:ef7eb2e8f9f7 153 @ Enter Supervisor Mode and set its Stack Pointer
<> 144:ef7eb2e8f9f7 154 msr cpsr_c, #(Mode_SVC | I_Bit | F_Bit)
<> 144:ef7eb2e8f9f7 155 mov sp, r0
<> 144:ef7eb2e8f9f7 156
<> 144:ef7eb2e8f9f7 157 @ Enter System Mode to complete initialization and enter kernel
<> 144:ef7eb2e8f9f7 158 msr cpsr_c, #(Mode_SYS | I_Bit | F_Bit)
<> 144:ef7eb2e8f9f7 159 mov sp, r0
<> 144:ef7eb2e8f9f7 160
<> 144:ef7eb2e8f9f7 161 @ USR/SYS stack pointer will be set during kernel init
<> 144:ef7eb2e8f9f7 162 ldr r0, =SystemInit
<> 144:ef7eb2e8f9f7 163 blx r0
<> 144:ef7eb2e8f9f7 164
Anna Bridge 180:96ed750bd169 165 @ Unmask interrupts
Anna Bridge 180:96ed750bd169 166 CPSIE if
<> 144:ef7eb2e8f9f7 167
<> 144:ef7eb2e8f9f7 168 @ data sections copy
<> 144:ef7eb2e8f9f7 169 ldr r4, =__copy_table_start__
<> 144:ef7eb2e8f9f7 170 ldr r5, =__copy_table_end__
<> 144:ef7eb2e8f9f7 171
<> 144:ef7eb2e8f9f7 172 .L_loop0:
<> 144:ef7eb2e8f9f7 173 cmp r4, r5
<> 144:ef7eb2e8f9f7 174 bge .L_loop0_done
<> 144:ef7eb2e8f9f7 175 ldr r1, [r4]
<> 144:ef7eb2e8f9f7 176 ldr r2, [r4, #4]
<> 144:ef7eb2e8f9f7 177 ldr r3, [r4, #8]
<> 144:ef7eb2e8f9f7 178
<> 144:ef7eb2e8f9f7 179 .L_loop0_0:
<> 144:ef7eb2e8f9f7 180 subs r3, #4
<> 144:ef7eb2e8f9f7 181 ittt ge
<> 144:ef7eb2e8f9f7 182 ldrge r0, [r1, r3]
<> 144:ef7eb2e8f9f7 183 strge r0, [r2, r3]
<> 144:ef7eb2e8f9f7 184 bge .L_loop0_0
<> 144:ef7eb2e8f9f7 185
<> 144:ef7eb2e8f9f7 186 adds r4, #12
<> 144:ef7eb2e8f9f7 187 b .L_loop0
<> 144:ef7eb2e8f9f7 188
<> 144:ef7eb2e8f9f7 189 .L_loop0_done:
<> 144:ef7eb2e8f9f7 190
<> 144:ef7eb2e8f9f7 191 @ bss sections clear
<> 144:ef7eb2e8f9f7 192 ldr r3, =__zero_table_start__
<> 144:ef7eb2e8f9f7 193 ldr r4, =__zero_table_end__
<> 144:ef7eb2e8f9f7 194
<> 144:ef7eb2e8f9f7 195 .L_loop2:
<> 144:ef7eb2e8f9f7 196 cmp r3, r4
<> 144:ef7eb2e8f9f7 197 bge .L_loop2_done
<> 144:ef7eb2e8f9f7 198 ldr r1, [r3]
<> 144:ef7eb2e8f9f7 199 ldr r2, [r3, #4]
<> 144:ef7eb2e8f9f7 200 movs r0, 0
<> 144:ef7eb2e8f9f7 201
<> 144:ef7eb2e8f9f7 202 .L_loop2_0:
<> 144:ef7eb2e8f9f7 203 subs r2, #4
<> 144:ef7eb2e8f9f7 204 itt ge
<> 144:ef7eb2e8f9f7 205 strge r0, [r1, r2]
<> 144:ef7eb2e8f9f7 206 bge .L_loop2_0
<> 144:ef7eb2e8f9f7 207
<> 144:ef7eb2e8f9f7 208 adds r3, #8
<> 144:ef7eb2e8f9f7 209 b .L_loop2
<> 144:ef7eb2e8f9f7 210 .L_loop2_done:
<> 144:ef7eb2e8f9f7 211
<> 144:ef7eb2e8f9f7 212
<> 144:ef7eb2e8f9f7 213 ldr r0, =_start
<> 144:ef7eb2e8f9f7 214 bx r0
<> 144:ef7eb2e8f9f7 215
<> 144:ef7eb2e8f9f7 216 ldr r0, sf_boot @ dummy to keep boot loader area
<> 144:ef7eb2e8f9f7 217 loop_here:
<> 144:ef7eb2e8f9f7 218 b loop_here
<> 144:ef7eb2e8f9f7 219
<> 144:ef7eb2e8f9f7 220 sf_boot:
<> 144:ef7eb2e8f9f7 221 .word boot_loader
<> 144:ef7eb2e8f9f7 222
<> 144:ef7eb2e8f9f7 223 .pool
<> 144:ef7eb2e8f9f7 224 .size Reset_Handler, . - Reset_Handler
<> 144:ef7eb2e8f9f7 225
<> 144:ef7eb2e8f9f7 226
<> 144:ef7eb2e8f9f7 227 .text
<> 144:ef7eb2e8f9f7 228
<> 144:ef7eb2e8f9f7 229 /* Macro to define default handlers. Default handler
<> 144:ef7eb2e8f9f7 230 * will be weak symbol and just dead loops. They can be
<> 144:ef7eb2e8f9f7 231 * overwritten by other handlers */
<> 144:ef7eb2e8f9f7 232 .macro def_default_handler handler_name
<> 144:ef7eb2e8f9f7 233 .align 1
<> 144:ef7eb2e8f9f7 234 .thumb_func
<> 144:ef7eb2e8f9f7 235 .weak \handler_name
<> 144:ef7eb2e8f9f7 236 .type \handler_name, %function
<> 144:ef7eb2e8f9f7 237 \handler_name :
<> 144:ef7eb2e8f9f7 238 b .
<> 144:ef7eb2e8f9f7 239 .size \handler_name, . - \handler_name
<> 144:ef7eb2e8f9f7 240 .endm
<> 144:ef7eb2e8f9f7 241
Anna Bridge 180:96ed750bd169 242 def_default_handler Undef_Handler
<> 144:ef7eb2e8f9f7 243 def_default_handler SVC_Handler
Anna Bridge 180:96ed750bd169 244 def_default_handler PAbt_Handler
Anna Bridge 180:96ed750bd169 245 def_default_handler DAbt_Handler
Anna Bridge 180:96ed750bd169 246 def_default_handler IRQ_Handler
Anna Bridge 180:96ed750bd169 247 def_default_handler FIQ_Handler
<> 144:ef7eb2e8f9f7 248
<> 144:ef7eb2e8f9f7 249 .END