QSPI.h

00001 /* mbed Microcontroller Library
00002  * Copyright (c) 2006-2018 ARM Limited
00003  * SPDX-License-Identifier: Apache-2.0
00004  *
00005  * Licensed under the Apache License, Version 2.0 (the "License");
00006  * you may not use this file except in compliance with the License.
00007  * You may obtain a copy of the License at
00008  *
00009  *     http://www.apache.org/licenses/LICENSE-2.0
00010  *
00011  * Unless required by applicable law or agreed to in writing, software
00012  * distributed under the License is distributed on an "AS IS" BASIS,
00013  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
00014  * See the License for the specific language governing permissions and
00015  * limitations under the License.
00016  */
00017 #ifndef MBED_QSPI_H
00018 #define MBED_QSPI_H
00019 
00020 #include "platform/platform.h"
00021 
00022 #if DEVICE_QSPI || defined(DOXYGEN_ONLY)
00023 
00024 #include "hal/qspi_api.h"
00025 #include "platform/PlatformMutex.h"
00026 #include "platform/SingletonPtr.h"
00027 #include "platform/NonCopyable.h"
00028 
00029 #define ONE_MHZ     1000000
00030 
00031 namespace mbed {
00032 
00033 /** \addtogroup drivers */
00034 
00035 /** A QSPI Driver, used for communicating with QSPI slave devices
00036  *
00037  * The default format is set to Quad-SPI(1-1-1), and a clock frequency of 1MHz
00038  * Most QSPI devices will also require Chip Select which is indicated by ssel.
00039  *
00040  * @note Synchronization level: Thread safe
00041  *
00042  * Example:
00043  * @code
00044  * // Write 4 byte array to a QSPI slave, and read the response, note that each device will have its specific read/write/alt values defined
00045  *
00046  * #include "mbed.h"
00047  *
00048  * #define CMD_WRITE 0x02
00049  * #define CMD_READ  0x03
00050  * #define ADDRESS   0x1000
00051  *
00052  * // hardware ssel (where applicable)
00053  * QSPI qspi_device(QSPI_FLASH1_IO0, QSPI_FLASH1_IO1, QSPI_FLASH1_IO2, QSPI_FLASH1_IO3, QSPI_FLASH1_SCK, QSPI_FLASH1_CSN); // io0, io1, io2, io3, sclk, ssel
00054  *
00055  *
00056  * int main() {
00057  *     char tx_buf[] = { 0x11, 0x22, 0x33, 0x44 };
00058  *     char rx_buf[4];
00059  *     int buf_len = sizeof(tx_buf);
00060  *
00061  *     qspi_status_t result = qspi_device.write(CMD_WRITE, 0, ADDRESS, tx_buf, &buf_len);
00062  *     if (result != QSPI_STATUS_OK) {
00063  *        printf("Write failed");
00064  *     }
00065  *     result = qspi_device.read(CMD_READ, 0, ADDRESS, rx_buf, &buf_len);
00066  *     if (result != QSPI_STATUS_OK) {
00067  *        printf("Read failed");
00068  *     }
00069  *
00070  * }
00071  * @endcode
00072  * @ingroup drivers
00073  */
00074 class QSPI : private NonCopyable<QSPI> {
00075 
00076 public:
00077 
00078     /** Create a QSPI master connected to the specified pins
00079      *
00080      *  io0-io3 is used to specify the Pins used for Quad SPI mode
00081      *
00082      *  @param io0 1st IO pin used for sending/receiving data during data phase of a transaction
00083      *  @param io1 2nd IO pin used for sending/receiving data during data phase of a transaction
00084      *  @param io2 3rd IO pin used for sending/receiving data during data phase of a transaction
00085      *  @param io3 4th IO pin used for sending/receiving data during data phase of a transaction
00086      *  @param sclk QSPI Clock pin
00087      *  @param ssel QSPI chip select pin
00088      *  @param mode Clock polarity and phase mode (0 - 3) of SPI
00089      *         (Default: Mode=0 uses CPOL=0, CPHA=0, Mode=1 uses CPOL=1, CPHA=1)
00090      *
00091      */
00092     QSPI(PinName io0, PinName io1, PinName io2, PinName io3, PinName sclk, PinName ssel = NC, int mode = 0);
00093     virtual ~QSPI()
00094     {
00095     }
00096 
00097     /** Configure the data transmission format
00098      *
00099      *  @param inst_width Bus width used by instruction phase(Valid values are QSPI_CFG_BUS_SINGLE, QSPI_CFG_BUS_DUAL, QSPI_CFG_BUS_QUAD)
00100      *  @param address_width Bus width used by address phase(Valid values are QSPI_CFG_BUS_SINGLE, QSPI_CFG_BUS_DUAL, QSPI_CFG_BUS_QUAD)
00101      *  @param address_size Size in bits used by address phase(Valid values are QSPI_CFG_ADDR_SIZE_8, QSPI_CFG_ADDR_SIZE_16, QSPI_CFG_ADDR_SIZE_24, QSPI_CFG_ADDR_SIZE_32)
00102      *  @param alt_width Bus width used by alt phase(Valid values are QSPI_CFG_BUS_SINGLE, QSPI_CFG_BUS_DUAL, QSPI_CFG_BUS_QUAD)
00103      *  @param alt_size Size in bits used by alt phase(Valid values are QSPI_CFG_ALT_SIZE_8, QSPI_CFG_ALT_SIZE_16, QSPI_CFG_ALT_SIZE_24, QSPI_CFG_ALT_SIZE_32)
00104      *  @param data_width Bus width used by data phase(Valid values are QSPI_CFG_BUS_SINGLE, QSPI_CFG_BUS_DUAL, QSPI_CFG_BUS_QUAD)
00105      *  @param dummy_cycles Number of dummy clock cycles to be used after alt phase
00106      *
00107      */
00108     qspi_status_t configure_format(qspi_bus_width_t inst_width,
00109                                    qspi_bus_width_t address_width,
00110                                    qspi_address_size_t address_size,
00111                                    qspi_bus_width_t alt_width,
00112                                    qspi_alt_size_t alt_size,
00113                                    qspi_bus_width_t data_width,
00114                                    int dummy_cycles);
00115 
00116     /** Set the qspi bus clock frequency
00117      *
00118      *  @param hz SCLK frequency in hz (default = 1MHz)
00119      *  @returns
00120      *    Returns QSPI_STATUS_SUCCESS on successful, fails if the interface is already init-ed
00121      */
00122     qspi_status_t set_frequency(int hz = ONE_MHZ);
00123 
00124     /** Read from QSPI peripheral with the preset read_instruction and alt_value
00125      *
00126      *  @param address Address to be accessed in QSPI peripheral
00127      *  @param rx_buffer Buffer for data to be read from the peripheral
00128      *  @param rx_length Pointer to a variable containing the length of rx_buffer, and on return this variable will be updated with the actual number of bytes read
00129      *
00130      *  @returns
00131      *    Returns QSPI_STATUS_SUCCESS on successful reads and QSPI_STATUS_ERROR on failed reads.
00132      */
00133     qspi_status_t read(int address, char *rx_buffer, size_t *rx_length);
00134 
00135     /** Write to QSPI peripheral using custom write instruction
00136      *
00137      *  @param address Address to be accessed in QSPI peripheral
00138      *  @param tx_buffer Buffer containing data to be sent to peripheral
00139      *  @param tx_length Pointer to a variable containing the length of data to be transmitted, and on return this variable will be updated with the actual number of bytes written
00140      *
00141      *  @returns
00142      *    Returns QSPI_STATUS_SUCCESS on successful reads and QSPI_STATUS_ERROR on failed reads.
00143      */
00144     qspi_status_t write(int address, const char *tx_buffer, size_t *tx_length);
00145 
00146     /** Read from QSPI peripheral using custom read instruction, alt values
00147      *
00148      *  @param instruction Instruction value to be used in instruction phase
00149      *  @param alt Alt value to be used in Alternate-byte phase. Use -1 for ignoring Alternate-byte phase
00150      *  @param address Address to be accessed in QSPI peripheral
00151      *  @param rx_buffer Buffer for data to be read from the peripheral
00152      *  @param rx_length Pointer to a variable containing the length of rx_buffer, and on return this variable will be updated with the actual number of bytes read
00153      *
00154      *  @returns
00155      *    Returns QSPI_STATUS_SUCCESS on successful reads and QSPI_STATUS_ERROR on failed reads.
00156      */
00157     qspi_status_t read(int instruction, int alt, int address, char *rx_buffer, size_t *rx_length);
00158 
00159     /** Write to QSPI peripheral using custom write instruction, alt values
00160      *
00161      *  @param instruction Instruction value to be used in instruction phase
00162      *  @param alt Alt value to be used in Alternate-byte phase. Use -1 for ignoring Alternate-byte phase
00163      *  @param address Address to be accessed in QSPI peripheral
00164      *  @param tx_buffer Buffer containing data to be sent to peripheral
00165      *  @param tx_length Pointer to a variable containing the length of data to be transmitted, and on return this variable will be updated with the actual number of bytes written
00166      *
00167      *  @returns
00168      *    Returns QSPI_STATUS_SUCCESS on successful reads and QSPI_STATUS_ERROR on failed reads.
00169      */
00170     qspi_status_t write(int instruction, int alt, int address, const char *tx_buffer, size_t *tx_length);
00171 
00172     /** Perform a transaction to write to an address(a control register) and get the status results
00173      *
00174      *  @param instruction Instruction value to be used in instruction phase
00175      *  @param address Some instruction might require address. Use -1 if no address
00176      *  @param tx_buffer Buffer containing data to be sent to peripheral
00177      *  @param tx_length Pointer to a variable containing the length of data to be transmitted, and on return this variable will be updated with the actual number of bytes written
00178      *  @param rx_buffer Buffer for data to be read from the peripheral
00179      *  @param rx_length Pointer to a variable containing the length of rx_buffer, and on return this variable will be updated with the actual number of bytes read
00180      *
00181      *  @returns
00182      *    Returns QSPI_STATUS_SUCCESS on successful reads and QSPI_STATUS_ERROR on failed reads.
00183      */
00184     qspi_status_t command_transfer(int instruction, int address, const char *tx_buffer, size_t tx_length, const char *rx_buffer, size_t rx_length);
00185 
00186 #if !defined(DOXYGEN_ONLY)
00187 protected:
00188     /** Acquire exclusive access to this SPI bus
00189      */
00190     virtual void lock(void);
00191 
00192     /** Release exclusive access to this SPI bus
00193      */
00194     virtual void unlock(void);
00195 
00196     qspi_t _qspi;
00197 
00198     bool acquire(void);
00199     static QSPI *_owner;
00200     static SingletonPtr<PlatformMutex>  _mutex;
00201     qspi_bus_width_t _inst_width; //Bus width for Instruction phase
00202     qspi_bus_width_t _address_width; //Bus width for Address phase
00203     qspi_address_size_t _address_size;
00204     qspi_bus_width_t _alt_width; //Bus width for Alt phase
00205     qspi_alt_size_t _alt_size;
00206     qspi_bus_width_t _data_width; //Bus width for Data phase
00207     qspi_command_t _qspi_command; //QSPI Hal command struct
00208     unsigned int _num_dummy_cycles; //Number of dummy cycles to be used
00209     int _hz; //Bus Frequency
00210     int _mode; //SPI mode
00211     bool _initialized;
00212     PinName _qspi_io0, _qspi_io1, _qspi_io2, _qspi_io3, _qspi_clk, _qspi_cs; //IO lines, clock and chip select
00213 
00214 private:
00215     /* Private acquire function without locking/unlocking
00216      * Implemented in order to avoid duplicate locking and boost performance
00217      */
00218     bool _acquire(void);
00219     bool _initialize();
00220 
00221     /*
00222      * This function builds the qspi command struct to be send to Hal
00223      */
00224     inline void _build_qspi_command(int instruction, int address, int alt);
00225 #endif
00226 };
00227 
00228 } // namespace mbed
00229 
00230 #endif
00231 
00232 #endif