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targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_ll_tim.c@157:ff67d9f36b67, 2017-02-02 (annotated)

Committer:
<>
Date:
Thu Feb 02 17:01:33 2017 +0000
Revision:
157:ff67d9f36b67
Child:
186:707f6e361f3e
This updates the lib to the mbed lib v135

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 157:ff67d9f36b67 1 /**
<> 157:ff67d9f36b67 2 ******************************************************************************
<> 157:ff67d9f36b67 3 * @file stm32f3xx_ll_tim.c
<> 157:ff67d9f36b67 4 * @author MCD Application Team
<> 157:ff67d9f36b67 5 * @version V1.4.0
<> 157:ff67d9f36b67 6 * @date 16-December-2016
<> 157:ff67d9f36b67 7 * @brief TIM LL module driver.
<> 157:ff67d9f36b67 8 ******************************************************************************
<> 157:ff67d9f36b67 9 * @attention
<> 157:ff67d9f36b67 10 *
<> 157:ff67d9f36b67 11 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 157:ff67d9f36b67 12 *
<> 157:ff67d9f36b67 13 * Redistribution and use in source and binary forms, with or without modification,
<> 157:ff67d9f36b67 14 * are permitted provided that the following conditions are met:
<> 157:ff67d9f36b67 15 * 1. Redistributions of source code must retain the above copyright notice,
<> 157:ff67d9f36b67 16 * this list of conditions and the following disclaimer.
<> 157:ff67d9f36b67 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 157:ff67d9f36b67 18 * this list of conditions and the following disclaimer in the documentation
<> 157:ff67d9f36b67 19 * and/or other materials provided with the distribution.
<> 157:ff67d9f36b67 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 157:ff67d9f36b67 21 * may be used to endorse or promote products derived from this software
<> 157:ff67d9f36b67 22 * without specific prior written permission.
<> 157:ff67d9f36b67 23 *
<> 157:ff67d9f36b67 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 157:ff67d9f36b67 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 157:ff67d9f36b67 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 157:ff67d9f36b67 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 157:ff67d9f36b67 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 157:ff67d9f36b67 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 157:ff67d9f36b67 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 157:ff67d9f36b67 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 157:ff67d9f36b67 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 157:ff67d9f36b67 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 157:ff67d9f36b67 34 *
<> 157:ff67d9f36b67 35 ******************************************************************************
<> 157:ff67d9f36b67 36 */
<> 157:ff67d9f36b67 37 #if defined(USE_FULL_LL_DRIVER)
<> 157:ff67d9f36b67 38
<> 157:ff67d9f36b67 39 /* Includes ------------------------------------------------------------------*/
<> 157:ff67d9f36b67 40 #include "stm32f3xx_ll_tim.h"
<> 157:ff67d9f36b67 41 #include "stm32f3xx_ll_bus.h"
<> 157:ff67d9f36b67 42
<> 157:ff67d9f36b67 43 #ifdef USE_FULL_ASSERT
<> 157:ff67d9f36b67 44 #include "stm32_assert.h"
<> 157:ff67d9f36b67 45 #else
<> 157:ff67d9f36b67 46 #define assert_param(expr) ((void)0U)
<> 157:ff67d9f36b67 47 #endif
<> 157:ff67d9f36b67 48
<> 157:ff67d9f36b67 49 /** @addtogroup STM32F3xx_LL_Driver
<> 157:ff67d9f36b67 50 * @{
<> 157:ff67d9f36b67 51 */
<> 157:ff67d9f36b67 52
<> 157:ff67d9f36b67 53 #if defined (TIM1) || defined (TIM2) || defined (TIM3) || defined (TIM4) || defined (TIM5) || defined (TIM6) || defined (TIM7) || defined (TIM8) || defined (TIM12) || defined (TIM13) || defined (TIM14) || defined (TIM15) || defined (TIM16) || defined (TIM17) || defined (TIM18) || defined (TIM19) || defined (TIM20)
<> 157:ff67d9f36b67 54
<> 157:ff67d9f36b67 55 /** @addtogroup TIM_LL
<> 157:ff67d9f36b67 56 * @{
<> 157:ff67d9f36b67 57 */
<> 157:ff67d9f36b67 58
<> 157:ff67d9f36b67 59 /* Private types -------------------------------------------------------------*/
<> 157:ff67d9f36b67 60 /* Private variables ---------------------------------------------------------*/
<> 157:ff67d9f36b67 61 /* Private constants ---------------------------------------------------------*/
<> 157:ff67d9f36b67 62 /* Private macros ------------------------------------------------------------*/
<> 157:ff67d9f36b67 63 /** @addtogroup TIM_LL_Private_Macros
<> 157:ff67d9f36b67 64 * @{
<> 157:ff67d9f36b67 65 */
<> 157:ff67d9f36b67 66 #define IS_LL_TIM_COUNTERMODE(__VALUE__) (((__VALUE__) == LL_TIM_COUNTERMODE_UP) \
<> 157:ff67d9f36b67 67 || ((__VALUE__) == LL_TIM_COUNTERMODE_DOWN) \
<> 157:ff67d9f36b67 68 || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP) \
<> 157:ff67d9f36b67 69 || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_DOWN) \
<> 157:ff67d9f36b67 70 || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP_DOWN))
<> 157:ff67d9f36b67 71
<> 157:ff67d9f36b67 72 #define IS_LL_TIM_CLOCKDIVISION(__VALUE__) (((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV1) \
<> 157:ff67d9f36b67 73 || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV2) \
<> 157:ff67d9f36b67 74 || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV4))
<> 157:ff67d9f36b67 75
<> 157:ff67d9f36b67 76 #if defined(TIM_CCMR1_OC1M_3)
<> 157:ff67d9f36b67 77 #define IS_LL_TIM_OCMODE(__VALUE__) (((__VALUE__) == LL_TIM_OCMODE_FROZEN) \
<> 157:ff67d9f36b67 78 || ((__VALUE__) == LL_TIM_OCMODE_ACTIVE) \
<> 157:ff67d9f36b67 79 || ((__VALUE__) == LL_TIM_OCMODE_INACTIVE) \
<> 157:ff67d9f36b67 80 || ((__VALUE__) == LL_TIM_OCMODE_TOGGLE) \
<> 157:ff67d9f36b67 81 || ((__VALUE__) == LL_TIM_OCMODE_FORCED_INACTIVE) \
<> 157:ff67d9f36b67 82 || ((__VALUE__) == LL_TIM_OCMODE_FORCED_ACTIVE) \
<> 157:ff67d9f36b67 83 || ((__VALUE__) == LL_TIM_OCMODE_PWM1) \
<> 157:ff67d9f36b67 84 || ((__VALUE__) == LL_TIM_OCMODE_PWM2) \
<> 157:ff67d9f36b67 85 || ((__VALUE__) == LL_TIM_OCMODE_RETRIG_OPM1) \
<> 157:ff67d9f36b67 86 || ((__VALUE__) == LL_TIM_OCMODE_RETRIG_OPM2) \
<> 157:ff67d9f36b67 87 || ((__VALUE__) == LL_TIM_OCMODE_COMBINED_PWM1) \
<> 157:ff67d9f36b67 88 || ((__VALUE__) == LL_TIM_OCMODE_COMBINED_PWM2) \
<> 157:ff67d9f36b67 89 || ((__VALUE__) == LL_TIM_OCMODE_ASSYMETRIC_PWM1) \
<> 157:ff67d9f36b67 90 || ((__VALUE__) == LL_TIM_OCMODE_ASSYMETRIC_PWM2))
<> 157:ff67d9f36b67 91 #else
<> 157:ff67d9f36b67 92 #define IS_LL_TIM_OCMODE(__VALUE__) (((__VALUE__) == LL_TIM_OCMODE_FROZEN) \
<> 157:ff67d9f36b67 93 || ((__VALUE__) == LL_TIM_OCMODE_ACTIVE) \
<> 157:ff67d9f36b67 94 || ((__VALUE__) == LL_TIM_OCMODE_INACTIVE) \
<> 157:ff67d9f36b67 95 || ((__VALUE__) == LL_TIM_OCMODE_TOGGLE) \
<> 157:ff67d9f36b67 96 || ((__VALUE__) == LL_TIM_OCMODE_FORCED_INACTIVE) \
<> 157:ff67d9f36b67 97 || ((__VALUE__) == LL_TIM_OCMODE_FORCED_ACTIVE) \
<> 157:ff67d9f36b67 98 || ((__VALUE__) == LL_TIM_OCMODE_PWM1) \
<> 157:ff67d9f36b67 99 || ((__VALUE__) == LL_TIM_OCMODE_PWM2))
<> 157:ff67d9f36b67 100 #endif
<> 157:ff67d9f36b67 101
<> 157:ff67d9f36b67 102 #define IS_LL_TIM_OCSTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCSTATE_DISABLE) \
<> 157:ff67d9f36b67 103 || ((__VALUE__) == LL_TIM_OCSTATE_ENABLE))
<> 157:ff67d9f36b67 104
<> 157:ff67d9f36b67 105 #define IS_LL_TIM_OCPOLARITY(__VALUE__) (((__VALUE__) == LL_TIM_OCPOLARITY_HIGH) \
<> 157:ff67d9f36b67 106 || ((__VALUE__) == LL_TIM_OCPOLARITY_LOW))
<> 157:ff67d9f36b67 107
<> 157:ff67d9f36b67 108 #define IS_LL_TIM_OCIDLESTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCIDLESTATE_LOW) \
<> 157:ff67d9f36b67 109 || ((__VALUE__) == LL_TIM_OCIDLESTATE_HIGH))
<> 157:ff67d9f36b67 110
<> 157:ff67d9f36b67 111 #define IS_LL_TIM_ACTIVEINPUT(__VALUE__) (((__VALUE__) == LL_TIM_ACTIVEINPUT_DIRECTTI) \
<> 157:ff67d9f36b67 112 || ((__VALUE__) == LL_TIM_ACTIVEINPUT_INDIRECTTI) \
<> 157:ff67d9f36b67 113 || ((__VALUE__) == LL_TIM_ACTIVEINPUT_TRC))
<> 157:ff67d9f36b67 114
<> 157:ff67d9f36b67 115 #define IS_LL_TIM_ICPSC(__VALUE__) (((__VALUE__) == LL_TIM_ICPSC_DIV1) \
<> 157:ff67d9f36b67 116 || ((__VALUE__) == LL_TIM_ICPSC_DIV2) \
<> 157:ff67d9f36b67 117 || ((__VALUE__) == LL_TIM_ICPSC_DIV4) \
<> 157:ff67d9f36b67 118 || ((__VALUE__) == LL_TIM_ICPSC_DIV8))
<> 157:ff67d9f36b67 119
<> 157:ff67d9f36b67 120 #define IS_LL_TIM_IC_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_IC_FILTER_FDIV1) \
<> 157:ff67d9f36b67 121 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N2) \
<> 157:ff67d9f36b67 122 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N4) \
<> 157:ff67d9f36b67 123 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N8) \
<> 157:ff67d9f36b67 124 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N6) \
<> 157:ff67d9f36b67 125 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N8) \
<> 157:ff67d9f36b67 126 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N6) \
<> 157:ff67d9f36b67 127 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N8) \
<> 157:ff67d9f36b67 128 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N6) \
<> 157:ff67d9f36b67 129 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N8) \
<> 157:ff67d9f36b67 130 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N5) \
<> 157:ff67d9f36b67 131 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N6) \
<> 157:ff67d9f36b67 132 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N8) \
<> 157:ff67d9f36b67 133 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N5) \
<> 157:ff67d9f36b67 134 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N6) \
<> 157:ff67d9f36b67 135 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N8))
<> 157:ff67d9f36b67 136
<> 157:ff67d9f36b67 137 #define IS_LL_TIM_IC_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \
<> 157:ff67d9f36b67 138 || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING) \
<> 157:ff67d9f36b67 139 || ((__VALUE__) == LL_TIM_IC_POLARITY_BOTHEDGE))
<> 157:ff67d9f36b67 140
<> 157:ff67d9f36b67 141 #define IS_LL_TIM_ENCODERMODE(__VALUE__) (((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI1) \
<> 157:ff67d9f36b67 142 || ((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI2) \
<> 157:ff67d9f36b67 143 || ((__VALUE__) == LL_TIM_ENCODERMODE_X4_TI12))
<> 157:ff67d9f36b67 144
<> 157:ff67d9f36b67 145 #define IS_LL_TIM_IC_POLARITY_ENCODER(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \
<> 157:ff67d9f36b67 146 || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING))
<> 157:ff67d9f36b67 147
<> 157:ff67d9f36b67 148 #define IS_LL_TIM_OSSR_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSR_DISABLE) \
<> 157:ff67d9f36b67 149 || ((__VALUE__) == LL_TIM_OSSR_ENABLE))
<> 157:ff67d9f36b67 150
<> 157:ff67d9f36b67 151 #define IS_LL_TIM_OSSI_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSI_DISABLE) \
<> 157:ff67d9f36b67 152 || ((__VALUE__) == LL_TIM_OSSI_ENABLE))
<> 157:ff67d9f36b67 153
<> 157:ff67d9f36b67 154 #define IS_LL_TIM_LOCK_LEVEL(__VALUE__) (((__VALUE__) == LL_TIM_LOCKLEVEL_OFF) \
<> 157:ff67d9f36b67 155 || ((__VALUE__) == LL_TIM_LOCKLEVEL_1) \
<> 157:ff67d9f36b67 156 || ((__VALUE__) == LL_TIM_LOCKLEVEL_2) \
<> 157:ff67d9f36b67 157 || ((__VALUE__) == LL_TIM_LOCKLEVEL_3))
<> 157:ff67d9f36b67 158
<> 157:ff67d9f36b67 159 #define IS_LL_TIM_BREAK_STATE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_DISABLE) \
<> 157:ff67d9f36b67 160 || ((__VALUE__) == LL_TIM_BREAK_ENABLE))
<> 157:ff67d9f36b67 161
<> 157:ff67d9f36b67 162 #define IS_LL_TIM_BREAK_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_POLARITY_LOW) \
<> 157:ff67d9f36b67 163 || ((__VALUE__) == LL_TIM_BREAK_POLARITY_HIGH))
<> 157:ff67d9f36b67 164 #if defined(TIM_BDTR_BKF)
<> 157:ff67d9f36b67 165
<> 157:ff67d9f36b67 166 #define IS_LL_TIM_BREAK_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1) \
<> 157:ff67d9f36b67 167 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N2) \
<> 157:ff67d9f36b67 168 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N4) \
<> 157:ff67d9f36b67 169 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N8) \
<> 157:ff67d9f36b67 170 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV2_N6) \
<> 157:ff67d9f36b67 171 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV2_N8) \
<> 157:ff67d9f36b67 172 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV4_N6) \
<> 157:ff67d9f36b67 173 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV4_N8) \
<> 157:ff67d9f36b67 174 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV8_N6) \
<> 157:ff67d9f36b67 175 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV8_N8) \
<> 157:ff67d9f36b67 176 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N5) \
<> 157:ff67d9f36b67 177 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N6) \
<> 157:ff67d9f36b67 178 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N8) \
<> 157:ff67d9f36b67 179 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N5) \
<> 157:ff67d9f36b67 180 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N6) \
<> 157:ff67d9f36b67 181 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N8))
<> 157:ff67d9f36b67 182 #endif /* TIM_BDTR_BKF */
<> 157:ff67d9f36b67 183 #if defined(TIM_BDTR_BK2E)
<> 157:ff67d9f36b67 184
<> 157:ff67d9f36b67 185 #define IS_LL_TIM_BREAK2_STATE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_DISABLE) \
<> 157:ff67d9f36b67 186 || ((__VALUE__) == LL_TIM_BREAK2_ENABLE))
<> 157:ff67d9f36b67 187
<> 157:ff67d9f36b67 188 #define IS_LL_TIM_BREAK2_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_POLARITY_LOW) \
<> 157:ff67d9f36b67 189 || ((__VALUE__) == LL_TIM_BREAK2_POLARITY_HIGH))
<> 157:ff67d9f36b67 190
<> 157:ff67d9f36b67 191 #define IS_LL_TIM_BREAK2_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1) \
<> 157:ff67d9f36b67 192 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N2) \
<> 157:ff67d9f36b67 193 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N4) \
<> 157:ff67d9f36b67 194 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N8) \
<> 157:ff67d9f36b67 195 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV2_N6) \
<> 157:ff67d9f36b67 196 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV2_N8) \
<> 157:ff67d9f36b67 197 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV4_N6) \
<> 157:ff67d9f36b67 198 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV4_N8) \
<> 157:ff67d9f36b67 199 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV8_N6) \
<> 157:ff67d9f36b67 200 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV8_N8) \
<> 157:ff67d9f36b67 201 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N5) \
<> 157:ff67d9f36b67 202 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N6) \
<> 157:ff67d9f36b67 203 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N8) \
<> 157:ff67d9f36b67 204 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N5) \
<> 157:ff67d9f36b67 205 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N6) \
<> 157:ff67d9f36b67 206 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N8))
<> 157:ff67d9f36b67 207 #endif /* TIM_BDTR_BK2E */
<> 157:ff67d9f36b67 208
<> 157:ff67d9f36b67 209 #define IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(__VALUE__) (((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_DISABLE) \
<> 157:ff67d9f36b67 210 || ((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_ENABLE))
<> 157:ff67d9f36b67 211 /**
<> 157:ff67d9f36b67 212 * @}
<> 157:ff67d9f36b67 213 */
<> 157:ff67d9f36b67 214
<> 157:ff67d9f36b67 215
<> 157:ff67d9f36b67 216 /* Private function prototypes -----------------------------------------------*/
<> 157:ff67d9f36b67 217 /** @defgroup TIM_LL_Private_Functions TIM Private Functions
<> 157:ff67d9f36b67 218 * @{
<> 157:ff67d9f36b67 219 */
<> 157:ff67d9f36b67 220 static ErrorStatus OC1Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
<> 157:ff67d9f36b67 221 static ErrorStatus OC2Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
<> 157:ff67d9f36b67 222 static ErrorStatus OC3Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
<> 157:ff67d9f36b67 223 static ErrorStatus OC4Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
<> 157:ff67d9f36b67 224 #if defined(TIM_CCER_CC5E)
<> 157:ff67d9f36b67 225 static ErrorStatus OC5Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
<> 157:ff67d9f36b67 226 #endif /* TIM_CCER_CC5E */
<> 157:ff67d9f36b67 227 #if defined(TIM_CCER_CC6E)
<> 157:ff67d9f36b67 228 static ErrorStatus OC6Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
<> 157:ff67d9f36b67 229 #endif /* TIM_CCER_CC6E */
<> 157:ff67d9f36b67 230 static ErrorStatus IC1Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
<> 157:ff67d9f36b67 231 static ErrorStatus IC2Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
<> 157:ff67d9f36b67 232 static ErrorStatus IC3Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
<> 157:ff67d9f36b67 233 static ErrorStatus IC4Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
<> 157:ff67d9f36b67 234 /**
<> 157:ff67d9f36b67 235 * @}
<> 157:ff67d9f36b67 236 */
<> 157:ff67d9f36b67 237
<> 157:ff67d9f36b67 238 /* Exported functions --------------------------------------------------------*/
<> 157:ff67d9f36b67 239 /** @addtogroup TIM_LL_Exported_Functions
<> 157:ff67d9f36b67 240 * @{
<> 157:ff67d9f36b67 241 */
<> 157:ff67d9f36b67 242
<> 157:ff67d9f36b67 243 /** @addtogroup TIM_LL_EF_Init
<> 157:ff67d9f36b67 244 * @{
<> 157:ff67d9f36b67 245 */
<> 157:ff67d9f36b67 246
<> 157:ff67d9f36b67 247 /**
<> 157:ff67d9f36b67 248 * @brief Set TIMx registers to their reset values.
<> 157:ff67d9f36b67 249 * @param TIMx Timer instance
<> 157:ff67d9f36b67 250 * @retval An ErrorStatus enumeration value:
<> 157:ff67d9f36b67 251 * - SUCCESS: TIMx registers are de-initialized
<> 157:ff67d9f36b67 252 * - ERROR: invalid TIMx instance
<> 157:ff67d9f36b67 253 */
<> 157:ff67d9f36b67 254 ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx)
<> 157:ff67d9f36b67 255 {
<> 157:ff67d9f36b67 256 ErrorStatus result = SUCCESS;
<> 157:ff67d9f36b67 257
<> 157:ff67d9f36b67 258 /* Check the parameters */
<> 157:ff67d9f36b67 259 assert_param(IS_TIM_INSTANCE(TIMx));
<> 157:ff67d9f36b67 260
<> 157:ff67d9f36b67 261
<> 157:ff67d9f36b67 262 if (TIMx == TIM2)
<> 157:ff67d9f36b67 263 {
<> 157:ff67d9f36b67 264 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM2);
<> 157:ff67d9f36b67 265 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM2);
<> 157:ff67d9f36b67 266 }
<> 157:ff67d9f36b67 267
<> 157:ff67d9f36b67 268 #if defined(TIM1)
<> 157:ff67d9f36b67 269 else if (TIMx == TIM1)
<> 157:ff67d9f36b67 270 {
<> 157:ff67d9f36b67 271 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM1);
<> 157:ff67d9f36b67 272 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM1);
<> 157:ff67d9f36b67 273 }
<> 157:ff67d9f36b67 274 #endif
<> 157:ff67d9f36b67 275 #if defined(TIM3)
<> 157:ff67d9f36b67 276 else if (TIMx == TIM3)
<> 157:ff67d9f36b67 277 {
<> 157:ff67d9f36b67 278 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM3);
<> 157:ff67d9f36b67 279 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM3);
<> 157:ff67d9f36b67 280 }
<> 157:ff67d9f36b67 281 #endif
<> 157:ff67d9f36b67 282 #if defined(TIM4)
<> 157:ff67d9f36b67 283 else if (TIMx == TIM4)
<> 157:ff67d9f36b67 284 {
<> 157:ff67d9f36b67 285 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM4);
<> 157:ff67d9f36b67 286 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM4);
<> 157:ff67d9f36b67 287 }
<> 157:ff67d9f36b67 288 #endif
<> 157:ff67d9f36b67 289 #if defined(TIM5)
<> 157:ff67d9f36b67 290 else if (TIMx == TIM5)
<> 157:ff67d9f36b67 291 {
<> 157:ff67d9f36b67 292 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM5);
<> 157:ff67d9f36b67 293 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM5);
<> 157:ff67d9f36b67 294 }
<> 157:ff67d9f36b67 295 #endif
<> 157:ff67d9f36b67 296 #if defined(TIM6)
<> 157:ff67d9f36b67 297 else if (TIMx == TIM6)
<> 157:ff67d9f36b67 298 {
<> 157:ff67d9f36b67 299 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM6);
<> 157:ff67d9f36b67 300 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM6);
<> 157:ff67d9f36b67 301 }
<> 157:ff67d9f36b67 302 #endif
<> 157:ff67d9f36b67 303 #if defined(TIM7)
<> 157:ff67d9f36b67 304 else if (TIMx == TIM7)
<> 157:ff67d9f36b67 305 {
<> 157:ff67d9f36b67 306 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM7);
<> 157:ff67d9f36b67 307 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM7);
<> 157:ff67d9f36b67 308 }
<> 157:ff67d9f36b67 309 #endif
<> 157:ff67d9f36b67 310 #if defined(TIM8)
<> 157:ff67d9f36b67 311 else if (TIMx == TIM8)
<> 157:ff67d9f36b67 312 {
<> 157:ff67d9f36b67 313 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM8);
<> 157:ff67d9f36b67 314 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM8);
<> 157:ff67d9f36b67 315 }
<> 157:ff67d9f36b67 316 #endif
<> 157:ff67d9f36b67 317 #if defined(TIM12)
<> 157:ff67d9f36b67 318 else if (TIMx == TIM12)
<> 157:ff67d9f36b67 319 {
<> 157:ff67d9f36b67 320 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM12);
<> 157:ff67d9f36b67 321 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM12);
<> 157:ff67d9f36b67 322 }
<> 157:ff67d9f36b67 323 #endif
<> 157:ff67d9f36b67 324 #if defined(TIM13)
<> 157:ff67d9f36b67 325 else if (TIMx == TIM13)
<> 157:ff67d9f36b67 326 {
<> 157:ff67d9f36b67 327 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM13);
<> 157:ff67d9f36b67 328 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM13);
<> 157:ff67d9f36b67 329 }
<> 157:ff67d9f36b67 330 #endif
<> 157:ff67d9f36b67 331 #if defined(TIM14)
<> 157:ff67d9f36b67 332 else if (TIMx == TIM14)
<> 157:ff67d9f36b67 333 {
<> 157:ff67d9f36b67 334 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM14);
<> 157:ff67d9f36b67 335 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM14);
<> 157:ff67d9f36b67 336 }
<> 157:ff67d9f36b67 337 #endif
<> 157:ff67d9f36b67 338 #if defined(TIM15)
<> 157:ff67d9f36b67 339 else if (TIMx == TIM15)
<> 157:ff67d9f36b67 340 {
<> 157:ff67d9f36b67 341 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM15);
<> 157:ff67d9f36b67 342 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM15);
<> 157:ff67d9f36b67 343 }
<> 157:ff67d9f36b67 344 #endif
<> 157:ff67d9f36b67 345 #if defined(TIM16)
<> 157:ff67d9f36b67 346 else if (TIMx == TIM16)
<> 157:ff67d9f36b67 347 {
<> 157:ff67d9f36b67 348 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM16);
<> 157:ff67d9f36b67 349 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM16);
<> 157:ff67d9f36b67 350 }
<> 157:ff67d9f36b67 351 #endif
<> 157:ff67d9f36b67 352 #if defined(TIM17)
<> 157:ff67d9f36b67 353 else if (TIMx == TIM17)
<> 157:ff67d9f36b67 354 {
<> 157:ff67d9f36b67 355 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM17);
<> 157:ff67d9f36b67 356 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM17);
<> 157:ff67d9f36b67 357 }
<> 157:ff67d9f36b67 358 #endif
<> 157:ff67d9f36b67 359 #if defined(TIM18)
<> 157:ff67d9f36b67 360 else if (TIMx == TIM18)
<> 157:ff67d9f36b67 361 {
<> 157:ff67d9f36b67 362 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM18);
<> 157:ff67d9f36b67 363 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM18);
<> 157:ff67d9f36b67 364 }
<> 157:ff67d9f36b67 365 #endif
<> 157:ff67d9f36b67 366 #if defined(TIM19)
<> 157:ff67d9f36b67 367 else if (TIMx == TIM19)
<> 157:ff67d9f36b67 368 {
<> 157:ff67d9f36b67 369 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM19);
<> 157:ff67d9f36b67 370 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM19);
<> 157:ff67d9f36b67 371 }
<> 157:ff67d9f36b67 372 #endif
<> 157:ff67d9f36b67 373 #if defined(TIM20)
<> 157:ff67d9f36b67 374 else if (TIMx == TIM20)
<> 157:ff67d9f36b67 375 {
<> 157:ff67d9f36b67 376 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM20);
<> 157:ff67d9f36b67 377 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM20);
<> 157:ff67d9f36b67 378 }
<> 157:ff67d9f36b67 379 #endif
<> 157:ff67d9f36b67 380 else
<> 157:ff67d9f36b67 381 {
<> 157:ff67d9f36b67 382 result = ERROR;
<> 157:ff67d9f36b67 383 }
<> 157:ff67d9f36b67 384
<> 157:ff67d9f36b67 385
<> 157:ff67d9f36b67 386 return result;
<> 157:ff67d9f36b67 387 }
<> 157:ff67d9f36b67 388
<> 157:ff67d9f36b67 389 /**
<> 157:ff67d9f36b67 390 * @brief Set the fields of the time base unit configuration data structure
<> 157:ff67d9f36b67 391 * to their default values.
<> 157:ff67d9f36b67 392 * @param TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure (time base unit configuration data structure)
<> 157:ff67d9f36b67 393 * @retval None
<> 157:ff67d9f36b67 394 */
<> 157:ff67d9f36b67 395 void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct)
<> 157:ff67d9f36b67 396 {
<> 157:ff67d9f36b67 397 /* Set the default configuration */
<> 157:ff67d9f36b67 398 TIM_InitStruct->Prescaler = (uint16_t)0x0000U;
<> 157:ff67d9f36b67 399 TIM_InitStruct->CounterMode = LL_TIM_COUNTERMODE_UP;
<> 157:ff67d9f36b67 400 TIM_InitStruct->Autoreload = (uint32_t)0xFFFFFFFFU;
<> 157:ff67d9f36b67 401 TIM_InitStruct->ClockDivision = LL_TIM_CLOCKDIVISION_DIV1;
<> 157:ff67d9f36b67 402 TIM_InitStruct->RepetitionCounter = (uint8_t)0x00U;
<> 157:ff67d9f36b67 403 }
<> 157:ff67d9f36b67 404
<> 157:ff67d9f36b67 405 /**
<> 157:ff67d9f36b67 406 * @brief Configure the TIMx time base unit.
<> 157:ff67d9f36b67 407 * @param TIMx Timer Instance
<> 157:ff67d9f36b67 408 * @param TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure (TIMx time base unit configuration data structure)
<> 157:ff67d9f36b67 409 * @retval An ErrorStatus enumeration value:
<> 157:ff67d9f36b67 410 * - SUCCESS: TIMx registers are de-initialized
<> 157:ff67d9f36b67 411 * - ERROR: not applicable
<> 157:ff67d9f36b67 412 */
<> 157:ff67d9f36b67 413 ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, LL_TIM_InitTypeDef *TIM_InitStruct)
<> 157:ff67d9f36b67 414 {
<> 157:ff67d9f36b67 415 uint32_t tmpcr1 = 0U;
<> 157:ff67d9f36b67 416
<> 157:ff67d9f36b67 417 /* Check the parameters */
<> 157:ff67d9f36b67 418 assert_param(IS_TIM_INSTANCE(TIMx));
<> 157:ff67d9f36b67 419 assert_param(IS_LL_TIM_COUNTERMODE(TIM_InitStruct->CounterMode));
<> 157:ff67d9f36b67 420 assert_param(IS_LL_TIM_CLOCKDIVISION(TIM_InitStruct->ClockDivision));
<> 157:ff67d9f36b67 421
<> 157:ff67d9f36b67 422 tmpcr1 = LL_TIM_ReadReg(TIMx, CR1);
<> 157:ff67d9f36b67 423
<> 157:ff67d9f36b67 424 if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
<> 157:ff67d9f36b67 425 {
<> 157:ff67d9f36b67 426 /* Select the Counter Mode */
<> 157:ff67d9f36b67 427 MODIFY_REG(tmpcr1, (TIM_CR1_DIR | TIM_CR1_CMS), TIM_InitStruct->CounterMode);
<> 157:ff67d9f36b67 428 }
<> 157:ff67d9f36b67 429
<> 157:ff67d9f36b67 430 if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
<> 157:ff67d9f36b67 431 {
<> 157:ff67d9f36b67 432 /* Set the clock division */
<> 157:ff67d9f36b67 433 MODIFY_REG(tmpcr1, TIM_CR1_CKD, TIM_InitStruct->ClockDivision);
<> 157:ff67d9f36b67 434 }
<> 157:ff67d9f36b67 435
<> 157:ff67d9f36b67 436 /* Write to TIMx CR1 */
<> 157:ff67d9f36b67 437 LL_TIM_WriteReg(TIMx, CR1, tmpcr1);
<> 157:ff67d9f36b67 438
<> 157:ff67d9f36b67 439 /* Set the Autoreload value */
<> 157:ff67d9f36b67 440 LL_TIM_SetAutoReload(TIMx, TIM_InitStruct->Autoreload);
<> 157:ff67d9f36b67 441
<> 157:ff67d9f36b67 442 /* Set the Prescaler value */
<> 157:ff67d9f36b67 443 LL_TIM_SetPrescaler(TIMx, TIM_InitStruct->Prescaler);
<> 157:ff67d9f36b67 444
<> 157:ff67d9f36b67 445 if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
<> 157:ff67d9f36b67 446 {
<> 157:ff67d9f36b67 447 /* Set the Repetition Counter value */
<> 157:ff67d9f36b67 448 LL_TIM_SetRepetitionCounter(TIMx, TIM_InitStruct->RepetitionCounter);
<> 157:ff67d9f36b67 449 }
<> 157:ff67d9f36b67 450
<> 157:ff67d9f36b67 451 /* Generate an update event to reload the Prescaler
<> 157:ff67d9f36b67 452 and the repetition counter value (if applicable) immediately */
<> 157:ff67d9f36b67 453 LL_TIM_GenerateEvent_UPDATE(TIMx);
<> 157:ff67d9f36b67 454
<> 157:ff67d9f36b67 455 return SUCCESS;
<> 157:ff67d9f36b67 456 }
<> 157:ff67d9f36b67 457
<> 157:ff67d9f36b67 458 /**
<> 157:ff67d9f36b67 459 * @brief Set the fields of the TIMx output channel configuration data
<> 157:ff67d9f36b67 460 * structure to their default values.
<> 157:ff67d9f36b67 461 * @param TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure (the output channel configuration data structure)
<> 157:ff67d9f36b67 462 * @retval None
<> 157:ff67d9f36b67 463 */
<> 157:ff67d9f36b67 464 void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
<> 157:ff67d9f36b67 465 {
<> 157:ff67d9f36b67 466 /* Set the default configuration */
<> 157:ff67d9f36b67 467 TIM_OC_InitStruct->OCMode = LL_TIM_OCMODE_FROZEN;
<> 157:ff67d9f36b67 468 TIM_OC_InitStruct->OCState = LL_TIM_OCSTATE_DISABLE;
<> 157:ff67d9f36b67 469 TIM_OC_InitStruct->OCNState = LL_TIM_OCSTATE_DISABLE;
<> 157:ff67d9f36b67 470 TIM_OC_InitStruct->CompareValue = (uint32_t)0x00000000U;
<> 157:ff67d9f36b67 471 TIM_OC_InitStruct->OCPolarity = LL_TIM_OCPOLARITY_HIGH;
<> 157:ff67d9f36b67 472 TIM_OC_InitStruct->OCNPolarity = LL_TIM_OCPOLARITY_HIGH;
<> 157:ff67d9f36b67 473 TIM_OC_InitStruct->OCIdleState = LL_TIM_OCIDLESTATE_LOW;
<> 157:ff67d9f36b67 474 TIM_OC_InitStruct->OCNIdleState = LL_TIM_OCIDLESTATE_LOW;
<> 157:ff67d9f36b67 475 }
<> 157:ff67d9f36b67 476
<> 157:ff67d9f36b67 477 /**
<> 157:ff67d9f36b67 478 * @brief Configure the TIMx output channel.
<> 157:ff67d9f36b67 479 * @param TIMx Timer Instance
<> 157:ff67d9f36b67 480 * @param Channel This parameter can be one of the following values:
<> 157:ff67d9f36b67 481 * @arg @ref LL_TIM_CHANNEL_CH1
<> 157:ff67d9f36b67 482 * @arg @ref LL_TIM_CHANNEL_CH2
<> 157:ff67d9f36b67 483 * @arg @ref LL_TIM_CHANNEL_CH3
<> 157:ff67d9f36b67 484 * @arg @ref LL_TIM_CHANNEL_CH4
<> 157:ff67d9f36b67 485 * @arg @ref LL_TIM_CHANNEL_CH5
<> 157:ff67d9f36b67 486 * @arg @ref LL_TIM_CHANNEL_CH6
<> 157:ff67d9f36b67 487 * @param TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure (TIMx output channel configuration data structure)
<> 157:ff67d9f36b67 488 * @note OC5 and OC6 are not available for all F3 devices
<> 157:ff67d9f36b67 489 * @retval An ErrorStatus enumeration value:
<> 157:ff67d9f36b67 490 * - SUCCESS: TIMx output channel is initialized
<> 157:ff67d9f36b67 491 * - ERROR: TIMx output channel is not initialized
<> 157:ff67d9f36b67 492 */
<> 157:ff67d9f36b67 493 ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
<> 157:ff67d9f36b67 494 {
<> 157:ff67d9f36b67 495 ErrorStatus result = ERROR;
<> 157:ff67d9f36b67 496
<> 157:ff67d9f36b67 497 switch (Channel)
<> 157:ff67d9f36b67 498 {
<> 157:ff67d9f36b67 499 case LL_TIM_CHANNEL_CH1:
<> 157:ff67d9f36b67 500 result = OC1Config(TIMx, TIM_OC_InitStruct);
<> 157:ff67d9f36b67 501 break;
<> 157:ff67d9f36b67 502 case LL_TIM_CHANNEL_CH2:
<> 157:ff67d9f36b67 503 result = OC2Config(TIMx, TIM_OC_InitStruct);
<> 157:ff67d9f36b67 504 break;
<> 157:ff67d9f36b67 505 case LL_TIM_CHANNEL_CH3:
<> 157:ff67d9f36b67 506 result = OC3Config(TIMx, TIM_OC_InitStruct);
<> 157:ff67d9f36b67 507 break;
<> 157:ff67d9f36b67 508 case LL_TIM_CHANNEL_CH4:
<> 157:ff67d9f36b67 509 result = OC4Config(TIMx, TIM_OC_InitStruct);
<> 157:ff67d9f36b67 510 break;
<> 157:ff67d9f36b67 511 #if defined(TIM_CCER_CC5E)
<> 157:ff67d9f36b67 512 case LL_TIM_CHANNEL_CH5:
<> 157:ff67d9f36b67 513 result = OC5Config(TIMx, TIM_OC_InitStruct);
<> 157:ff67d9f36b67 514 break;
<> 157:ff67d9f36b67 515 case LL_TIM_CHANNEL_CH6:
<> 157:ff67d9f36b67 516 result = OC6Config(TIMx, TIM_OC_InitStruct);
<> 157:ff67d9f36b67 517 break;
<> 157:ff67d9f36b67 518 #endif /* TIM_CCER_CC5E */
<> 157:ff67d9f36b67 519 default:
<> 157:ff67d9f36b67 520 break;
<> 157:ff67d9f36b67 521 }
<> 157:ff67d9f36b67 522
<> 157:ff67d9f36b67 523 return result;
<> 157:ff67d9f36b67 524 }
<> 157:ff67d9f36b67 525
<> 157:ff67d9f36b67 526 /**
<> 157:ff67d9f36b67 527 * @brief Set the fields of the TIMx input channel configuration data
<> 157:ff67d9f36b67 528 * structure to their default values.
<> 157:ff67d9f36b67 529 * @param TIM_ICInitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (the input channel configuration data structure)
<> 157:ff67d9f36b67 530 * @retval None
<> 157:ff67d9f36b67 531 */
<> 157:ff67d9f36b67 532 void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
<> 157:ff67d9f36b67 533 {
<> 157:ff67d9f36b67 534 /* Set the default configuration */
<> 157:ff67d9f36b67 535 TIM_ICInitStruct->ICPolarity = LL_TIM_IC_POLARITY_RISING;
<> 157:ff67d9f36b67 536 TIM_ICInitStruct->ICActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
<> 157:ff67d9f36b67 537 TIM_ICInitStruct->ICPrescaler = LL_TIM_ICPSC_DIV1;
<> 157:ff67d9f36b67 538 TIM_ICInitStruct->ICFilter = LL_TIM_IC_FILTER_FDIV1;
<> 157:ff67d9f36b67 539 }
<> 157:ff67d9f36b67 540
<> 157:ff67d9f36b67 541 /**
<> 157:ff67d9f36b67 542 * @brief Configure the TIMx input channel.
<> 157:ff67d9f36b67 543 * @param TIMx Timer Instance
<> 157:ff67d9f36b67 544 * @param Channel This parameter can be one of the following values:
<> 157:ff67d9f36b67 545 * @arg @ref LL_TIM_CHANNEL_CH1
<> 157:ff67d9f36b67 546 * @arg @ref LL_TIM_CHANNEL_CH2
<> 157:ff67d9f36b67 547 * @arg @ref LL_TIM_CHANNEL_CH3
<> 157:ff67d9f36b67 548 * @arg @ref LL_TIM_CHANNEL_CH4
<> 157:ff67d9f36b67 549 * @param TIM_IC_InitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (TIMx input channel configuration data structure)
<> 157:ff67d9f36b67 550 * @retval An ErrorStatus enumeration value:
<> 157:ff67d9f36b67 551 * - SUCCESS: TIMx output channel is initialized
<> 157:ff67d9f36b67 552 * - ERROR: TIMx output channel is not initialized
<> 157:ff67d9f36b67 553 */
<> 157:ff67d9f36b67 554 ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct)
<> 157:ff67d9f36b67 555 {
<> 157:ff67d9f36b67 556 ErrorStatus result = ERROR;
<> 157:ff67d9f36b67 557
<> 157:ff67d9f36b67 558 switch (Channel)
<> 157:ff67d9f36b67 559 {
<> 157:ff67d9f36b67 560 case LL_TIM_CHANNEL_CH1:
<> 157:ff67d9f36b67 561 result = IC1Config(TIMx, TIM_IC_InitStruct);
<> 157:ff67d9f36b67 562 break;
<> 157:ff67d9f36b67 563 case LL_TIM_CHANNEL_CH2:
<> 157:ff67d9f36b67 564 result = IC2Config(TIMx, TIM_IC_InitStruct);
<> 157:ff67d9f36b67 565 break;
<> 157:ff67d9f36b67 566 case LL_TIM_CHANNEL_CH3:
<> 157:ff67d9f36b67 567 result = IC3Config(TIMx, TIM_IC_InitStruct);
<> 157:ff67d9f36b67 568 break;
<> 157:ff67d9f36b67 569 case LL_TIM_CHANNEL_CH4:
<> 157:ff67d9f36b67 570 result = IC4Config(TIMx, TIM_IC_InitStruct);
<> 157:ff67d9f36b67 571 break;
<> 157:ff67d9f36b67 572 default:
<> 157:ff67d9f36b67 573 break;
<> 157:ff67d9f36b67 574 }
<> 157:ff67d9f36b67 575
<> 157:ff67d9f36b67 576 return result;
<> 157:ff67d9f36b67 577 }
<> 157:ff67d9f36b67 578
<> 157:ff67d9f36b67 579 /**
<> 157:ff67d9f36b67 580 * @brief Fills each TIM_EncoderInitStruct field with its default value
<> 157:ff67d9f36b67 581 * @param TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (encoder interface configuration data structure)
<> 157:ff67d9f36b67 582 * @retval None
<> 157:ff67d9f36b67 583 */
<> 157:ff67d9f36b67 584 void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
<> 157:ff67d9f36b67 585 {
<> 157:ff67d9f36b67 586 /* Set the default configuration */
<> 157:ff67d9f36b67 587 TIM_EncoderInitStruct->EncoderMode = LL_TIM_ENCODERMODE_X2_TI1;
<> 157:ff67d9f36b67 588 TIM_EncoderInitStruct->IC1Polarity = LL_TIM_IC_POLARITY_RISING;
<> 157:ff67d9f36b67 589 TIM_EncoderInitStruct->IC1ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
<> 157:ff67d9f36b67 590 TIM_EncoderInitStruct->IC1Prescaler = LL_TIM_ICPSC_DIV1;
<> 157:ff67d9f36b67 591 TIM_EncoderInitStruct->IC1Filter = LL_TIM_IC_FILTER_FDIV1;
<> 157:ff67d9f36b67 592 TIM_EncoderInitStruct->IC2Polarity = LL_TIM_IC_POLARITY_RISING;
<> 157:ff67d9f36b67 593 TIM_EncoderInitStruct->IC2ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
<> 157:ff67d9f36b67 594 TIM_EncoderInitStruct->IC2Prescaler = LL_TIM_ICPSC_DIV1;
<> 157:ff67d9f36b67 595 TIM_EncoderInitStruct->IC2Filter = LL_TIM_IC_FILTER_FDIV1;
<> 157:ff67d9f36b67 596 }
<> 157:ff67d9f36b67 597
<> 157:ff67d9f36b67 598 /**
<> 157:ff67d9f36b67 599 * @brief Configure the encoder interface of the timer instance.
<> 157:ff67d9f36b67 600 * @param TIMx Timer Instance
<> 157:ff67d9f36b67 601 * @param TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (TIMx encoder interface configuration data structure)
<> 157:ff67d9f36b67 602 * @retval An ErrorStatus enumeration value:
<> 157:ff67d9f36b67 603 * - SUCCESS: TIMx registers are de-initialized
<> 157:ff67d9f36b67 604 * - ERROR: not applicable
<> 157:ff67d9f36b67 605 */
<> 157:ff67d9f36b67 606 ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
<> 157:ff67d9f36b67 607 {
<> 157:ff67d9f36b67 608 uint32_t tmpccmr1 = 0U;
<> 157:ff67d9f36b67 609 uint32_t tmpccer = 0U;
<> 157:ff67d9f36b67 610
<> 157:ff67d9f36b67 611 /* Check the parameters */
<> 157:ff67d9f36b67 612 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx));
<> 157:ff67d9f36b67 613 assert_param(IS_LL_TIM_ENCODERMODE(TIM_EncoderInitStruct->EncoderMode));
<> 157:ff67d9f36b67 614 assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC1Polarity));
<> 157:ff67d9f36b67 615 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC1ActiveInput));
<> 157:ff67d9f36b67 616 assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC1Prescaler));
<> 157:ff67d9f36b67 617 assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC1Filter));
<> 157:ff67d9f36b67 618 assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC2Polarity));
<> 157:ff67d9f36b67 619 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC2ActiveInput));
<> 157:ff67d9f36b67 620 assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC2Prescaler));
<> 157:ff67d9f36b67 621 assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC2Filter));
<> 157:ff67d9f36b67 622
<> 157:ff67d9f36b67 623 /* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */
<> 157:ff67d9f36b67 624 TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E);
<> 157:ff67d9f36b67 625
<> 157:ff67d9f36b67 626 /* Get the TIMx CCMR1 register value */
<> 157:ff67d9f36b67 627 tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
<> 157:ff67d9f36b67 628
<> 157:ff67d9f36b67 629 /* Get the TIMx CCER register value */
<> 157:ff67d9f36b67 630 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
<> 157:ff67d9f36b67 631
<> 157:ff67d9f36b67 632 /* Configure TI1 */
<> 157:ff67d9f36b67 633 tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC);
<> 157:ff67d9f36b67 634 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1ActiveInput >> 16U);
<> 157:ff67d9f36b67 635 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Filter >> 16U);
<> 157:ff67d9f36b67 636 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Prescaler >> 16U);
<> 157:ff67d9f36b67 637
<> 157:ff67d9f36b67 638 /* Configure TI2 */
<> 157:ff67d9f36b67 639 tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC2S | TIM_CCMR1_IC2F | TIM_CCMR1_IC2PSC);
<> 157:ff67d9f36b67 640 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2ActiveInput >> 8U);
<> 157:ff67d9f36b67 641 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Filter >> 8U);
<> 157:ff67d9f36b67 642 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Prescaler >> 8U);
<> 157:ff67d9f36b67 643
<> 157:ff67d9f36b67 644 /* Set TI1 and TI2 polarity and enable TI1 and TI2 */
<> 157:ff67d9f36b67 645 tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP);
<> 157:ff67d9f36b67 646 tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC1Polarity);
<> 157:ff67d9f36b67 647 tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC2Polarity << 4U);
<> 157:ff67d9f36b67 648 tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E);
<> 157:ff67d9f36b67 649
<> 157:ff67d9f36b67 650 /* Set encoder mode */
<> 157:ff67d9f36b67 651 LL_TIM_SetEncoderMode(TIMx, TIM_EncoderInitStruct->EncoderMode);
<> 157:ff67d9f36b67 652
<> 157:ff67d9f36b67 653 /* Write to TIMx CCMR1 */
<> 157:ff67d9f36b67 654 LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
<> 157:ff67d9f36b67 655
<> 157:ff67d9f36b67 656 /* Write to TIMx CCER */
<> 157:ff67d9f36b67 657 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
<> 157:ff67d9f36b67 658
<> 157:ff67d9f36b67 659 return SUCCESS;
<> 157:ff67d9f36b67 660 }
<> 157:ff67d9f36b67 661
<> 157:ff67d9f36b67 662 #if defined TIM_CR2_MMS2
<> 157:ff67d9f36b67 663 /**
<> 157:ff67d9f36b67 664 * @brief Set the fields of the TIMx Hall sensor interface configuration data
<> 157:ff67d9f36b67 665 * structure to their default values.
<> 157:ff67d9f36b67 666 * @param TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (HALL sensor interface configuration data structure)
<> 157:ff67d9f36b67 667 * @retval None
<> 157:ff67d9f36b67 668 */
<> 157:ff67d9f36b67 669 void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct)
<> 157:ff67d9f36b67 670 {
<> 157:ff67d9f36b67 671 /* Set the default configuration */
<> 157:ff67d9f36b67 672 TIM_HallSensorInitStruct->IC1Polarity = LL_TIM_IC_POLARITY_RISING;
<> 157:ff67d9f36b67 673 TIM_HallSensorInitStruct->IC1Prescaler = LL_TIM_ICPSC_DIV1;
<> 157:ff67d9f36b67 674 TIM_HallSensorInitStruct->IC1Filter = LL_TIM_IC_FILTER_FDIV1;
<> 157:ff67d9f36b67 675 TIM_HallSensorInitStruct->CommutationDelay = (uint32_t)0U;
<> 157:ff67d9f36b67 676 }
<> 157:ff67d9f36b67 677
<> 157:ff67d9f36b67 678 /**
<> 157:ff67d9f36b67 679 * @brief Configure the Hall sensor interface of the timer instance.
<> 157:ff67d9f36b67 680 * @note TIMx CH1, CH2 and CH3 inputs connected through a XOR
<> 157:ff67d9f36b67 681 * to the TI1 input channel
<> 157:ff67d9f36b67 682 * @note TIMx slave mode controller is configured in reset mode.
<> 157:ff67d9f36b67 683 Selected internal trigger is TI1F_ED.
<> 157:ff67d9f36b67 684 * @note Channel 1 is configured as input, IC1 is mapped on TRC.
<> 157:ff67d9f36b67 685 * @note Captured value stored in TIMx_CCR1 correspond to the time elapsed
<> 157:ff67d9f36b67 686 * between 2 changes on the inputs. It gives information about motor speed.
<> 157:ff67d9f36b67 687 * @note Channel 2 is configured in output PWM 2 mode.
<> 157:ff67d9f36b67 688 * @note Compare value stored in TIMx_CCR2 corresponds to the commutation delay.
<> 157:ff67d9f36b67 689 * @note OC2REF is selected as trigger output on TRGO.
<> 157:ff67d9f36b67 690 * @note LL_TIM_IC_POLARITY_BOTHEDGE must not be used for TI1 when it is used
<> 157:ff67d9f36b67 691 * when TIMx operates in Hall sensor interface mode.
<> 157:ff67d9f36b67 692 * @param TIMx Timer Instance
<> 157:ff67d9f36b67 693 * @param TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (TIMx HALL sensor interface configuration data structure)
<> 157:ff67d9f36b67 694 * @retval An ErrorStatus enumeration value:
<> 157:ff67d9f36b67 695 * - SUCCESS: TIMx registers are de-initialized
<> 157:ff67d9f36b67 696 * - ERROR: not applicable
<> 157:ff67d9f36b67 697 */
<> 157:ff67d9f36b67 698 ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct)
<> 157:ff67d9f36b67 699 {
<> 157:ff67d9f36b67 700 uint32_t tmpcr2 = 0U;
<> 157:ff67d9f36b67 701 uint32_t tmpccmr1 = 0U;
<> 157:ff67d9f36b67 702 uint32_t tmpccer = 0U;
<> 157:ff67d9f36b67 703 uint32_t tmpsmcr = 0U;
<> 157:ff67d9f36b67 704
<> 157:ff67d9f36b67 705 /* Check the parameters */
<> 157:ff67d9f36b67 706 assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(TIMx));
<> 157:ff67d9f36b67 707 assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_HallSensorInitStruct->IC1Polarity));
<> 157:ff67d9f36b67 708 assert_param(IS_LL_TIM_ICPSC(TIM_HallSensorInitStruct->IC1Prescaler));
<> 157:ff67d9f36b67 709 assert_param(IS_LL_TIM_IC_FILTER(TIM_HallSensorInitStruct->IC1Filter));
<> 157:ff67d9f36b67 710
<> 157:ff67d9f36b67 711 /* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */
<> 157:ff67d9f36b67 712 TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E);
<> 157:ff67d9f36b67 713
<> 157:ff67d9f36b67 714 /* Get the TIMx CR2 register value */
<> 157:ff67d9f36b67 715 tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
<> 157:ff67d9f36b67 716
<> 157:ff67d9f36b67 717 /* Get the TIMx CCMR1 register value */
<> 157:ff67d9f36b67 718 tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
<> 157:ff67d9f36b67 719
<> 157:ff67d9f36b67 720 /* Get the TIMx CCER register value */
<> 157:ff67d9f36b67 721 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
<> 157:ff67d9f36b67 722
<> 157:ff67d9f36b67 723 /* Get the TIMx SMCR register value */
<> 157:ff67d9f36b67 724 tmpsmcr = LL_TIM_ReadReg(TIMx, SMCR);
<> 157:ff67d9f36b67 725
<> 157:ff67d9f36b67 726 /* Connect TIMx_CH1, CH2 and CH3 pins to the TI1 input */
<> 157:ff67d9f36b67 727 tmpcr2 |= TIM_CR2_TI1S;
<> 157:ff67d9f36b67 728
<> 157:ff67d9f36b67 729 /* OC2REF signal is used as trigger output (TRGO) */
<> 157:ff67d9f36b67 730 tmpcr2 |= LL_TIM_TRGO_OC2REF;
<> 157:ff67d9f36b67 731
<> 157:ff67d9f36b67 732 /* Configure the slave mode controller */
<> 157:ff67d9f36b67 733 tmpsmcr &= (uint32_t)~(TIM_SMCR_TS | TIM_SMCR_SMS);
<> 157:ff67d9f36b67 734 tmpsmcr |= LL_TIM_TS_TI1F_ED;
<> 157:ff67d9f36b67 735 tmpsmcr |= LL_TIM_SLAVEMODE_RESET;
<> 157:ff67d9f36b67 736
<> 157:ff67d9f36b67 737 /* Configure input channel 1 */
<> 157:ff67d9f36b67 738 tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC);
<> 157:ff67d9f36b67 739 tmpccmr1 |= (uint32_t)(LL_TIM_ACTIVEINPUT_TRC >> 16U);
<> 157:ff67d9f36b67 740 tmpccmr1 |= (uint32_t)(TIM_HallSensorInitStruct->IC1Filter >> 16U);
<> 157:ff67d9f36b67 741 tmpccmr1 |= (uint32_t)(TIM_HallSensorInitStruct->IC1Prescaler >> 16U);
<> 157:ff67d9f36b67 742
<> 157:ff67d9f36b67 743 /* Configure input channel 2 */
<> 157:ff67d9f36b67 744 tmpccmr1 &= (uint32_t)~(TIM_CCMR1_OC2M | TIM_CCMR1_OC2FE | TIM_CCMR1_OC2PE | TIM_CCMR1_OC2CE);
<> 157:ff67d9f36b67 745 tmpccmr1 |= (uint32_t)(LL_TIM_OCMODE_PWM2 << 8U);
<> 157:ff67d9f36b67 746
<> 157:ff67d9f36b67 747 /* Set Channel 1 polarity and enable Channel 1 and Channel2 */
<> 157:ff67d9f36b67 748 tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP);
<> 157:ff67d9f36b67 749 tmpccer |= (uint32_t)(TIM_HallSensorInitStruct->IC1Polarity);
<> 157:ff67d9f36b67 750 tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E);
<> 157:ff67d9f36b67 751
<> 157:ff67d9f36b67 752 /* Write to TIMx CR2 */
<> 157:ff67d9f36b67 753 LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
<> 157:ff67d9f36b67 754
<> 157:ff67d9f36b67 755 /* Write to TIMx SMCR */
<> 157:ff67d9f36b67 756 LL_TIM_WriteReg(TIMx, SMCR, tmpsmcr);
<> 157:ff67d9f36b67 757
<> 157:ff67d9f36b67 758 /* Write to TIMx CCMR1 */
<> 157:ff67d9f36b67 759 LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
<> 157:ff67d9f36b67 760
<> 157:ff67d9f36b67 761 /* Write to TIMx CCER */
<> 157:ff67d9f36b67 762 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
<> 157:ff67d9f36b67 763
<> 157:ff67d9f36b67 764 /* Write to TIMx CCR2 */
<> 157:ff67d9f36b67 765 LL_TIM_OC_SetCompareCH2(TIMx, TIM_HallSensorInitStruct->CommutationDelay);
<> 157:ff67d9f36b67 766
<> 157:ff67d9f36b67 767 return SUCCESS;
<> 157:ff67d9f36b67 768 }
<> 157:ff67d9f36b67 769 #endif /* TIM_CR2_MMS2 */
<> 157:ff67d9f36b67 770
<> 157:ff67d9f36b67 771 /**
<> 157:ff67d9f36b67 772 * @brief Set the fields of the Break and Dead Time configuration data structure
<> 157:ff67d9f36b67 773 * to their default values.
<> 157:ff67d9f36b67 774 * @param TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration data structure)
<> 157:ff67d9f36b67 775 * @retval None
<> 157:ff67d9f36b67 776 */
<> 157:ff67d9f36b67 777 void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
<> 157:ff67d9f36b67 778 {
<> 157:ff67d9f36b67 779 /* Set the default configuration */
<> 157:ff67d9f36b67 780 TIM_BDTRInitStruct->OSSRState = LL_TIM_OSSR_DISABLE;
<> 157:ff67d9f36b67 781 TIM_BDTRInitStruct->OSSIState = LL_TIM_OSSI_DISABLE;
<> 157:ff67d9f36b67 782 TIM_BDTRInitStruct->LockLevel = LL_TIM_LOCKLEVEL_OFF;
<> 157:ff67d9f36b67 783 TIM_BDTRInitStruct->DeadTime = (uint8_t)0x00U;
<> 157:ff67d9f36b67 784 TIM_BDTRInitStruct->BreakState = LL_TIM_BREAK_DISABLE;
<> 157:ff67d9f36b67 785 TIM_BDTRInitStruct->BreakPolarity = LL_TIM_BREAK_POLARITY_LOW;
<> 157:ff67d9f36b67 786 #if defined(TIM_BDTR_BKF)
<> 157:ff67d9f36b67 787 TIM_BDTRInitStruct->BreakFilter = LL_TIM_BREAK_FILTER_FDIV1;
<> 157:ff67d9f36b67 788 #endif /* TIM_BDTR_BKF */
<> 157:ff67d9f36b67 789 #if defined(TIM_BDTR_BK2E)
<> 157:ff67d9f36b67 790 TIM_BDTRInitStruct->Break2State = LL_TIM_BREAK2_DISABLE;
<> 157:ff67d9f36b67 791 TIM_BDTRInitStruct->Break2Polarity = LL_TIM_BREAK2_POLARITY_LOW;
<> 157:ff67d9f36b67 792 TIM_BDTRInitStruct->Break2Filter = LL_TIM_BREAK2_FILTER_FDIV1;
<> 157:ff67d9f36b67 793 TIM_BDTRInitStruct->AutomaticOutput = LL_TIM_AUTOMATICOUTPUT_DISABLE;
<> 157:ff67d9f36b67 794 #endif /* TIM_BDTR_BK2E */
<> 157:ff67d9f36b67 795 }
<> 157:ff67d9f36b67 796
<> 157:ff67d9f36b67 797 /**
<> 157:ff67d9f36b67 798 * @brief Configure the Break and Dead Time feature of the timer instance.
<> 157:ff67d9f36b67 799 * @note As the bits BK2P, BK2E, BK2F[3:0], BKF[3:0], AOE, BKP, BKE, OSSI, OSSR
<> 157:ff67d9f36b67 800 * and DTG[7:0] can be write-locked depending on the LOCK configuration, it
<> 157:ff67d9f36b67 801 * can be necessary to configure all of them during the first write access to
<> 157:ff67d9f36b67 802 * the TIMx_BDTR register.
<> 157:ff67d9f36b67 803 * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
<> 157:ff67d9f36b67 804 * a timer instance provides a break input.
<> 157:ff67d9f36b67 805 * @note Macro @ref IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
<> 157:ff67d9f36b67 806 * a timer instance provides a second break input.
<> 157:ff67d9f36b67 807 * @param TIMx Timer Instance
<> 157:ff67d9f36b67 808 * @param TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration data structure)
<> 157:ff67d9f36b67 809 * @retval An ErrorStatus enumeration value:
<> 157:ff67d9f36b67 810 * - SUCCESS: Break and Dead Time is initialized
<> 157:ff67d9f36b67 811 * - ERROR: not applicable
<> 157:ff67d9f36b67 812 */
<> 157:ff67d9f36b67 813 ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
<> 157:ff67d9f36b67 814 {
<> 157:ff67d9f36b67 815 uint32_t tmpbdtr = 0;
<> 157:ff67d9f36b67 816
<> 157:ff67d9f36b67 817 /* Check the parameters */
<> 157:ff67d9f36b67 818 assert_param(IS_TIM_BREAK_INSTANCE(TIMx));
<> 157:ff67d9f36b67 819 assert_param(IS_LL_TIM_OSSR_STATE(TIM_BDTRInitStruct->OSSRState));
<> 157:ff67d9f36b67 820 assert_param(IS_LL_TIM_OSSI_STATE(TIM_BDTRInitStruct->OSSIState));
<> 157:ff67d9f36b67 821 assert_param(IS_LL_TIM_LOCK_LEVEL(TIM_BDTRInitStruct->LockLevel));
<> 157:ff67d9f36b67 822 assert_param(IS_LL_TIM_BREAK_STATE(TIM_BDTRInitStruct->BreakState));
<> 157:ff67d9f36b67 823 assert_param(IS_LL_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->BreakPolarity));
<> 157:ff67d9f36b67 824 assert_param(IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->AutomaticOutput));
<> 157:ff67d9f36b67 825
<> 157:ff67d9f36b67 826 /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
<> 157:ff67d9f36b67 827 the OSSI State, the dead time value and the Automatic Output Enable Bit */
<> 157:ff67d9f36b67 828
<> 157:ff67d9f36b67 829 /* Set the BDTR bits */
<> 157:ff67d9f36b67 830 MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, TIM_BDTRInitStruct->DeadTime);
<> 157:ff67d9f36b67 831 MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, TIM_BDTRInitStruct->LockLevel);
<> 157:ff67d9f36b67 832 MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, TIM_BDTRInitStruct->OSSIState);
<> 157:ff67d9f36b67 833 MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, TIM_BDTRInitStruct->OSSRState);
<> 157:ff67d9f36b67 834 MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, TIM_BDTRInitStruct->BreakState);
<> 157:ff67d9f36b67 835 MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, TIM_BDTRInitStruct->BreakPolarity);
<> 157:ff67d9f36b67 836 MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, TIM_BDTRInitStruct->AutomaticOutput);
<> 157:ff67d9f36b67 837 MODIFY_REG(tmpbdtr, TIM_BDTR_MOE, TIM_BDTRInitStruct->AutomaticOutput);
<> 157:ff67d9f36b67 838 #if defined(TIM_BDTR_BKF)
<> 157:ff67d9f36b67 839 if (IS_TIM_ADVANCED_INSTANCE(TIMx))
<> 157:ff67d9f36b67 840 {
<> 157:ff67d9f36b67 841 assert_param(IS_LL_TIM_BREAK_FILTER(TIM_BDTRInitStruct->BreakFilter));
<> 157:ff67d9f36b67 842 MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, TIM_BDTRInitStruct->BreakFilter);
<> 157:ff67d9f36b67 843 }
<> 157:ff67d9f36b67 844 #endif /* TIM_BDTR_BKF */
<> 157:ff67d9f36b67 845 #if defined(TIM_BDTR_BK2E)
<> 157:ff67d9f36b67 846
<> 157:ff67d9f36b67 847 if (IS_TIM_BKIN2_INSTANCE(TIMx))
<> 157:ff67d9f36b67 848 {
<> 157:ff67d9f36b67 849 assert_param(IS_LL_TIM_BREAK2_STATE(TIM_BDTRInitStruct->Break2State));
<> 157:ff67d9f36b67 850 assert_param(IS_LL_TIM_BREAK2_POLARITY(TIM_BDTRInitStruct->Break2Polarity));
<> 157:ff67d9f36b67 851 assert_param(IS_LL_TIM_BREAK2_FILTER(TIM_BDTRInitStruct->Break2Filter));
<> 157:ff67d9f36b67 852
<> 157:ff67d9f36b67 853 /* Set the BREAK2 input related BDTR bit-fields */
<> 157:ff67d9f36b67 854 MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F, (TIM_BDTRInitStruct->Break2Filter));
<> 157:ff67d9f36b67 855 MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, TIM_BDTRInitStruct->Break2State);
<> 157:ff67d9f36b67 856 MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, TIM_BDTRInitStruct->Break2Polarity);
<> 157:ff67d9f36b67 857 }
<> 157:ff67d9f36b67 858 #endif /* TIM_BDTR_BK2E */
<> 157:ff67d9f36b67 859
<> 157:ff67d9f36b67 860 /* Set TIMx_BDTR */
<> 157:ff67d9f36b67 861 LL_TIM_WriteReg(TIMx, BDTR, tmpbdtr);
<> 157:ff67d9f36b67 862
<> 157:ff67d9f36b67 863 return SUCCESS;
<> 157:ff67d9f36b67 864 }
<> 157:ff67d9f36b67 865 /**
<> 157:ff67d9f36b67 866 * @}
<> 157:ff67d9f36b67 867 */
<> 157:ff67d9f36b67 868
<> 157:ff67d9f36b67 869 /**
<> 157:ff67d9f36b67 870 * @}
<> 157:ff67d9f36b67 871 */
<> 157:ff67d9f36b67 872
<> 157:ff67d9f36b67 873 /** @addtogroup TIM_LL_Private_Functions TIM Private Functions
<> 157:ff67d9f36b67 874 * @brief Private functions
<> 157:ff67d9f36b67 875 * @{
<> 157:ff67d9f36b67 876 */
<> 157:ff67d9f36b67 877 /**
<> 157:ff67d9f36b67 878 * @brief Configure the TIMx output channel 1.
<> 157:ff67d9f36b67 879 * @param TIMx Timer Instance
<> 157:ff67d9f36b67 880 * @param TIM_OCInitStruct pointer to the the TIMx output channel 1 configuration data structure
<> 157:ff67d9f36b67 881 * @retval An ErrorStatus enumeration value:
<> 157:ff67d9f36b67 882 * - SUCCESS: TIMx registers are de-initialized
<> 157:ff67d9f36b67 883 * - ERROR: not applicable
<> 157:ff67d9f36b67 884 */
<> 157:ff67d9f36b67 885 static ErrorStatus OC1Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
<> 157:ff67d9f36b67 886 {
<> 157:ff67d9f36b67 887 uint32_t tmpccmr1 = 0U;
<> 157:ff67d9f36b67 888 uint32_t tmpccer = 0U;
<> 157:ff67d9f36b67 889 uint32_t tmpcr2 = 0U;
<> 157:ff67d9f36b67 890
<> 157:ff67d9f36b67 891 /* Check the parameters */
<> 157:ff67d9f36b67 892 assert_param(IS_TIM_CC1_INSTANCE(TIMx));
<> 157:ff67d9f36b67 893 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
<> 157:ff67d9f36b67 894 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
<> 157:ff67d9f36b67 895 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
<> 157:ff67d9f36b67 896 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
<> 157:ff67d9f36b67 897 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
<> 157:ff67d9f36b67 898
<> 157:ff67d9f36b67 899 /* Disable the Channel 1: Reset the CC1E Bit */
<> 157:ff67d9f36b67 900 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC1E);
<> 157:ff67d9f36b67 901
<> 157:ff67d9f36b67 902 /* Get the TIMx CCER register value */
<> 157:ff67d9f36b67 903 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
<> 157:ff67d9f36b67 904
<> 157:ff67d9f36b67 905 /* Get the TIMx CR2 register value */
<> 157:ff67d9f36b67 906 tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
<> 157:ff67d9f36b67 907
<> 157:ff67d9f36b67 908 /* Get the TIMx CCMR1 register value */
<> 157:ff67d9f36b67 909 tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
<> 157:ff67d9f36b67 910
<> 157:ff67d9f36b67 911 /* Reset Capture/Compare selection Bits */
<> 157:ff67d9f36b67 912 CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC1S);
<> 157:ff67d9f36b67 913
<> 157:ff67d9f36b67 914 /* Set the Output Compare Mode */
<> 157:ff67d9f36b67 915 MODIFY_REG(tmpccmr1, TIM_CCMR1_OC1M, TIM_OCInitStruct->OCMode);
<> 157:ff67d9f36b67 916
<> 157:ff67d9f36b67 917 /* Set the Output Compare Polarity */
<> 157:ff67d9f36b67 918 MODIFY_REG(tmpccer, TIM_CCER_CC1P, TIM_OCInitStruct->OCPolarity);
<> 157:ff67d9f36b67 919
<> 157:ff67d9f36b67 920 /* Set the Output State */
<> 157:ff67d9f36b67 921 MODIFY_REG(tmpccer, TIM_CCER_CC1E, TIM_OCInitStruct->OCState);
<> 157:ff67d9f36b67 922
<> 157:ff67d9f36b67 923 if (IS_TIM_BREAK_INSTANCE(TIMx))
<> 157:ff67d9f36b67 924 {
<> 157:ff67d9f36b67 925 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
<> 157:ff67d9f36b67 926 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
<> 157:ff67d9f36b67 927
<> 157:ff67d9f36b67 928 /* Set the complementary output Polarity */
<> 157:ff67d9f36b67 929 MODIFY_REG(tmpccer, TIM_CCER_CC1NP, TIM_OCInitStruct->OCNPolarity << 2U);
<> 157:ff67d9f36b67 930
<> 157:ff67d9f36b67 931 /* Set the complementary output State */
<> 157:ff67d9f36b67 932 MODIFY_REG(tmpccer, TIM_CCER_CC1NE, TIM_OCInitStruct->OCNState << 2U);
<> 157:ff67d9f36b67 933
<> 157:ff67d9f36b67 934 /* Set the Output Idle state */
<> 157:ff67d9f36b67 935 MODIFY_REG(tmpcr2, TIM_CR2_OIS1, TIM_OCInitStruct->OCIdleState);
<> 157:ff67d9f36b67 936
<> 157:ff67d9f36b67 937 /* Set the complementary output Idle state */
<> 157:ff67d9f36b67 938 MODIFY_REG(tmpcr2, TIM_CR2_OIS1N, TIM_OCInitStruct->OCNIdleState << 1U);
<> 157:ff67d9f36b67 939 }
<> 157:ff67d9f36b67 940
<> 157:ff67d9f36b67 941 /* Write to TIMx CR2 */
<> 157:ff67d9f36b67 942 LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
<> 157:ff67d9f36b67 943
<> 157:ff67d9f36b67 944 /* Write to TIMx CCMR1 */
<> 157:ff67d9f36b67 945 LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
<> 157:ff67d9f36b67 946
<> 157:ff67d9f36b67 947 /* Set the Capture Compare Register value */
<> 157:ff67d9f36b67 948 LL_TIM_OC_SetCompareCH1(TIMx, TIM_OCInitStruct->CompareValue);
<> 157:ff67d9f36b67 949
<> 157:ff67d9f36b67 950 /* Write to TIMx CCER */
<> 157:ff67d9f36b67 951 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
<> 157:ff67d9f36b67 952
<> 157:ff67d9f36b67 953 return SUCCESS;
<> 157:ff67d9f36b67 954 }
<> 157:ff67d9f36b67 955
<> 157:ff67d9f36b67 956 /**
<> 157:ff67d9f36b67 957 * @brief Configure the TIMx output channel 2.
<> 157:ff67d9f36b67 958 * @param TIMx Timer Instance
<> 157:ff67d9f36b67 959 * @param TIM_OCInitStruct pointer to the the TIMx output channel 2 configuration data structure
<> 157:ff67d9f36b67 960 * @retval An ErrorStatus enumeration value:
<> 157:ff67d9f36b67 961 * - SUCCESS: TIMx registers are de-initialized
<> 157:ff67d9f36b67 962 * - ERROR: not applicable
<> 157:ff67d9f36b67 963 */
<> 157:ff67d9f36b67 964 static ErrorStatus OC2Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
<> 157:ff67d9f36b67 965 {
<> 157:ff67d9f36b67 966 uint32_t tmpccmr1 = 0U;
<> 157:ff67d9f36b67 967 uint32_t tmpccer = 0U;
<> 157:ff67d9f36b67 968 uint32_t tmpcr2 = 0U;
<> 157:ff67d9f36b67 969
<> 157:ff67d9f36b67 970 /* Check the parameters */
<> 157:ff67d9f36b67 971 assert_param(IS_TIM_CC2_INSTANCE(TIMx));
<> 157:ff67d9f36b67 972 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
<> 157:ff67d9f36b67 973 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
<> 157:ff67d9f36b67 974 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
<> 157:ff67d9f36b67 975 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
<> 157:ff67d9f36b67 976 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
<> 157:ff67d9f36b67 977
<> 157:ff67d9f36b67 978 /* Disable the Channel 2: Reset the CC2E Bit */
<> 157:ff67d9f36b67 979 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC2E);
<> 157:ff67d9f36b67 980
<> 157:ff67d9f36b67 981 /* Get the TIMx CCER register value */
<> 157:ff67d9f36b67 982 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
<> 157:ff67d9f36b67 983
<> 157:ff67d9f36b67 984 /* Get the TIMx CR2 register value */
<> 157:ff67d9f36b67 985 tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
<> 157:ff67d9f36b67 986
<> 157:ff67d9f36b67 987 /* Get the TIMx CCMR1 register value */
<> 157:ff67d9f36b67 988 tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
<> 157:ff67d9f36b67 989
<> 157:ff67d9f36b67 990 /* Reset Capture/Compare selection Bits */
<> 157:ff67d9f36b67 991 CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC2S);
<> 157:ff67d9f36b67 992
<> 157:ff67d9f36b67 993 /* Select the Output Compare Mode */
<> 157:ff67d9f36b67 994 MODIFY_REG(tmpccmr1, TIM_CCMR1_OC2M, TIM_OCInitStruct->OCMode << 8U);
<> 157:ff67d9f36b67 995
<> 157:ff67d9f36b67 996 /* Set the Output Compare Polarity */
<> 157:ff67d9f36b67 997 MODIFY_REG(tmpccer, TIM_CCER_CC2P, TIM_OCInitStruct->OCPolarity << 4U);
<> 157:ff67d9f36b67 998
<> 157:ff67d9f36b67 999 /* Set the Output State */
<> 157:ff67d9f36b67 1000 MODIFY_REG(tmpccer, TIM_CCER_CC2E, TIM_OCInitStruct->OCState << 4U);
<> 157:ff67d9f36b67 1001
<> 157:ff67d9f36b67 1002 if (IS_TIM_BREAK_INSTANCE(TIMx))
<> 157:ff67d9f36b67 1003 {
<> 157:ff67d9f36b67 1004 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
<> 157:ff67d9f36b67 1005 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
<> 157:ff67d9f36b67 1006
<> 157:ff67d9f36b67 1007 /* Set the complementary output Polarity */
<> 157:ff67d9f36b67 1008 MODIFY_REG(tmpccer, TIM_CCER_CC2NP, TIM_OCInitStruct->OCNPolarity << 6U);
<> 157:ff67d9f36b67 1009
<> 157:ff67d9f36b67 1010 /* Set the complementary output State */
<> 157:ff67d9f36b67 1011 MODIFY_REG(tmpccer, TIM_CCER_CC2NE, TIM_OCInitStruct->OCNState << 6U);
<> 157:ff67d9f36b67 1012
<> 157:ff67d9f36b67 1013 /* Set the Output Idle state */
<> 157:ff67d9f36b67 1014 MODIFY_REG(tmpcr2, TIM_CR2_OIS2, TIM_OCInitStruct->OCIdleState << 2U);
<> 157:ff67d9f36b67 1015
<> 157:ff67d9f36b67 1016 #if defined(STM32F373xC) || defined(STM32F378xx)
<> 157:ff67d9f36b67 1017 #else
<> 157:ff67d9f36b67 1018 /* Set the complementary output Idle state */
<> 157:ff67d9f36b67 1019 MODIFY_REG(tmpcr2, TIM_CR2_OIS2N, TIM_OCInitStruct->OCNIdleState << 3U);
<> 157:ff67d9f36b67 1020 #endif
<> 157:ff67d9f36b67 1021 }
<> 157:ff67d9f36b67 1022
<> 157:ff67d9f36b67 1023 /* Write to TIMx CR2 */
<> 157:ff67d9f36b67 1024 LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
<> 157:ff67d9f36b67 1025
<> 157:ff67d9f36b67 1026 /* Write to TIMx CCMR1 */
<> 157:ff67d9f36b67 1027 LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
<> 157:ff67d9f36b67 1028
<> 157:ff67d9f36b67 1029 /* Set the Capture Compare Register value */
<> 157:ff67d9f36b67 1030 LL_TIM_OC_SetCompareCH2(TIMx, TIM_OCInitStruct->CompareValue);
<> 157:ff67d9f36b67 1031
<> 157:ff67d9f36b67 1032 /* Write to TIMx CCER */
<> 157:ff67d9f36b67 1033 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
<> 157:ff67d9f36b67 1034
<> 157:ff67d9f36b67 1035 return SUCCESS;
<> 157:ff67d9f36b67 1036 }
<> 157:ff67d9f36b67 1037
<> 157:ff67d9f36b67 1038 /**
<> 157:ff67d9f36b67 1039 * @brief Configure the TIMx output channel 3.
<> 157:ff67d9f36b67 1040 * @param TIMx Timer Instance
<> 157:ff67d9f36b67 1041 * @param TIM_OCInitStruct pointer to the the TIMx output channel 3 configuration data structure
<> 157:ff67d9f36b67 1042 * @retval An ErrorStatus enumeration value:
<> 157:ff67d9f36b67 1043 * - SUCCESS: TIMx registers are de-initialized
<> 157:ff67d9f36b67 1044 * - ERROR: not applicable
<> 157:ff67d9f36b67 1045 */
<> 157:ff67d9f36b67 1046 static ErrorStatus OC3Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
<> 157:ff67d9f36b67 1047 {
<> 157:ff67d9f36b67 1048 uint32_t tmpccmr2 = 0U;
<> 157:ff67d9f36b67 1049 uint32_t tmpccer = 0U;
<> 157:ff67d9f36b67 1050 uint32_t tmpcr2 = 0U;
<> 157:ff67d9f36b67 1051
<> 157:ff67d9f36b67 1052 /* Check the parameters */
<> 157:ff67d9f36b67 1053 assert_param(IS_TIM_CC3_INSTANCE(TIMx));
<> 157:ff67d9f36b67 1054 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
<> 157:ff67d9f36b67 1055 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
<> 157:ff67d9f36b67 1056 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
<> 157:ff67d9f36b67 1057 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
<> 157:ff67d9f36b67 1058 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
<> 157:ff67d9f36b67 1059
<> 157:ff67d9f36b67 1060 /* Disable the Channel 3: Reset the CC3E Bit */
<> 157:ff67d9f36b67 1061 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC3E);
<> 157:ff67d9f36b67 1062
<> 157:ff67d9f36b67 1063 /* Get the TIMx CCER register value */
<> 157:ff67d9f36b67 1064 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
<> 157:ff67d9f36b67 1065
<> 157:ff67d9f36b67 1066 /* Get the TIMx CR2 register value */
<> 157:ff67d9f36b67 1067 tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
<> 157:ff67d9f36b67 1068
<> 157:ff67d9f36b67 1069 /* Get the TIMx CCMR2 register value */
<> 157:ff67d9f36b67 1070 tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2);
<> 157:ff67d9f36b67 1071
<> 157:ff67d9f36b67 1072 /* Reset Capture/Compare selection Bits */
<> 157:ff67d9f36b67 1073 CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC3S);
<> 157:ff67d9f36b67 1074
<> 157:ff67d9f36b67 1075 /* Select the Output Compare Mode */
<> 157:ff67d9f36b67 1076 MODIFY_REG(tmpccmr2, TIM_CCMR2_OC3M, TIM_OCInitStruct->OCMode);
<> 157:ff67d9f36b67 1077
<> 157:ff67d9f36b67 1078 /* Set the Output Compare Polarity */
<> 157:ff67d9f36b67 1079 MODIFY_REG(tmpccer, TIM_CCER_CC3P, TIM_OCInitStruct->OCPolarity << 8U);
<> 157:ff67d9f36b67 1080
<> 157:ff67d9f36b67 1081 /* Set the Output State */
<> 157:ff67d9f36b67 1082 MODIFY_REG(tmpccer, TIM_CCER_CC3E, TIM_OCInitStruct->OCState << 8U);
<> 157:ff67d9f36b67 1083
<> 157:ff67d9f36b67 1084 if (IS_TIM_BREAK_INSTANCE(TIMx))
<> 157:ff67d9f36b67 1085 {
<> 157:ff67d9f36b67 1086 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
<> 157:ff67d9f36b67 1087 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
<> 157:ff67d9f36b67 1088
<> 157:ff67d9f36b67 1089 /* Set the complementary output Polarity */
<> 157:ff67d9f36b67 1090 MODIFY_REG(tmpccer, TIM_CCER_CC3NP, TIM_OCInitStruct->OCNPolarity << 10U);
<> 157:ff67d9f36b67 1091
<> 157:ff67d9f36b67 1092 /* Set the complementary output State */
<> 157:ff67d9f36b67 1093 MODIFY_REG(tmpccer, TIM_CCER_CC3NE, TIM_OCInitStruct->OCNState << 10U);
<> 157:ff67d9f36b67 1094
<> 157:ff67d9f36b67 1095 #if defined(STM32F373xC) || defined(STM32F378xx)
<> 157:ff67d9f36b67 1096 #else
<> 157:ff67d9f36b67 1097 /* Set the Output Idle state */
<> 157:ff67d9f36b67 1098 MODIFY_REG(tmpcr2, TIM_CR2_OIS3, TIM_OCInitStruct->OCIdleState << 4U);
<> 157:ff67d9f36b67 1099
<> 157:ff67d9f36b67 1100 /* Set the complementary output Idle state */
<> 157:ff67d9f36b67 1101 MODIFY_REG(tmpcr2, TIM_CR2_OIS3N, TIM_OCInitStruct->OCNIdleState << 5U);
<> 157:ff67d9f36b67 1102 #endif
<> 157:ff67d9f36b67 1103 }
<> 157:ff67d9f36b67 1104
<> 157:ff67d9f36b67 1105 /* Write to TIMx CR2 */
<> 157:ff67d9f36b67 1106 LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
<> 157:ff67d9f36b67 1107
<> 157:ff67d9f36b67 1108 /* Write to TIMx CCMR2 */
<> 157:ff67d9f36b67 1109 LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2);
<> 157:ff67d9f36b67 1110
<> 157:ff67d9f36b67 1111 /* Set the Capture Compare Register value */
<> 157:ff67d9f36b67 1112 LL_TIM_OC_SetCompareCH3(TIMx, TIM_OCInitStruct->CompareValue);
<> 157:ff67d9f36b67 1113
<> 157:ff67d9f36b67 1114 /* Write to TIMx CCER */
<> 157:ff67d9f36b67 1115 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
<> 157:ff67d9f36b67 1116
<> 157:ff67d9f36b67 1117 return SUCCESS;
<> 157:ff67d9f36b67 1118 }
<> 157:ff67d9f36b67 1119
<> 157:ff67d9f36b67 1120 /**
<> 157:ff67d9f36b67 1121 * @brief Configure the TIMx output channel 4.
<> 157:ff67d9f36b67 1122 * @param TIMx Timer Instance
<> 157:ff67d9f36b67 1123 * @param TIM_OCInitStruct pointer to the the TIMx output channel 4 configuration data structure
<> 157:ff67d9f36b67 1124 * @retval An ErrorStatus enumeration value:
<> 157:ff67d9f36b67 1125 * - SUCCESS: TIMx registers are de-initialized
<> 157:ff67d9f36b67 1126 * - ERROR: not applicable
<> 157:ff67d9f36b67 1127 */
<> 157:ff67d9f36b67 1128 static ErrorStatus OC4Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
<> 157:ff67d9f36b67 1129 {
<> 157:ff67d9f36b67 1130 uint32_t tmpccmr2 = 0U;
<> 157:ff67d9f36b67 1131 uint32_t tmpccer = 0U;
<> 157:ff67d9f36b67 1132 uint32_t tmpcr2 = 0U;
<> 157:ff67d9f36b67 1133
<> 157:ff67d9f36b67 1134 /* Check the parameters */
<> 157:ff67d9f36b67 1135 assert_param(IS_TIM_CC4_INSTANCE(TIMx));
<> 157:ff67d9f36b67 1136 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
<> 157:ff67d9f36b67 1137 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
<> 157:ff67d9f36b67 1138 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
<> 157:ff67d9f36b67 1139 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
<> 157:ff67d9f36b67 1140 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
<> 157:ff67d9f36b67 1141
<> 157:ff67d9f36b67 1142 /* Disable the Channel 4: Reset the CC4E Bit */
<> 157:ff67d9f36b67 1143 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC4E);
<> 157:ff67d9f36b67 1144
<> 157:ff67d9f36b67 1145 /* Get the TIMx CCER register value */
<> 157:ff67d9f36b67 1146 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
<> 157:ff67d9f36b67 1147
<> 157:ff67d9f36b67 1148 /* Get the TIMx CR2 register value */
<> 157:ff67d9f36b67 1149 tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
<> 157:ff67d9f36b67 1150
<> 157:ff67d9f36b67 1151 /* Get the TIMx CCMR2 register value */
<> 157:ff67d9f36b67 1152 tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2);
<> 157:ff67d9f36b67 1153
<> 157:ff67d9f36b67 1154 /* Reset Capture/Compare selection Bits */
<> 157:ff67d9f36b67 1155 CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC4S);
<> 157:ff67d9f36b67 1156
<> 157:ff67d9f36b67 1157 /* Select the Output Compare Mode */
<> 157:ff67d9f36b67 1158 MODIFY_REG(tmpccmr2, TIM_CCMR2_OC4M, TIM_OCInitStruct->OCMode << 8U);
<> 157:ff67d9f36b67 1159
<> 157:ff67d9f36b67 1160 /* Set the Output Compare Polarity */
<> 157:ff67d9f36b67 1161 MODIFY_REG(tmpccer, TIM_CCER_CC4P, TIM_OCInitStruct->OCPolarity << 12U);
<> 157:ff67d9f36b67 1162
<> 157:ff67d9f36b67 1163 /* Set the Output State */
<> 157:ff67d9f36b67 1164 MODIFY_REG(tmpccer, TIM_CCER_CC4E, TIM_OCInitStruct->OCState << 12U);
<> 157:ff67d9f36b67 1165
<> 157:ff67d9f36b67 1166 if (IS_TIM_BREAK_INSTANCE(TIMx))
<> 157:ff67d9f36b67 1167 {
<> 157:ff67d9f36b67 1168 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
<> 157:ff67d9f36b67 1169 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
<> 157:ff67d9f36b67 1170
<> 157:ff67d9f36b67 1171 #if defined(STM32F373xC) || defined(STM32F378xx)
<> 157:ff67d9f36b67 1172 #else
<> 157:ff67d9f36b67 1173 /* Set the Output Idle state */
<> 157:ff67d9f36b67 1174 MODIFY_REG(tmpcr2, TIM_CR2_OIS4, TIM_OCInitStruct->OCIdleState << 6U);
<> 157:ff67d9f36b67 1175 #endif
<> 157:ff67d9f36b67 1176 }
<> 157:ff67d9f36b67 1177
<> 157:ff67d9f36b67 1178 /* Write to TIMx CR2 */
<> 157:ff67d9f36b67 1179 LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
<> 157:ff67d9f36b67 1180
<> 157:ff67d9f36b67 1181 /* Write to TIMx CCMR2 */
<> 157:ff67d9f36b67 1182 LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2);
<> 157:ff67d9f36b67 1183
<> 157:ff67d9f36b67 1184 /* Set the Capture Compare Register value */
<> 157:ff67d9f36b67 1185 LL_TIM_OC_SetCompareCH4(TIMx, TIM_OCInitStruct->CompareValue);
<> 157:ff67d9f36b67 1186
<> 157:ff67d9f36b67 1187 /* Write to TIMx CCER */
<> 157:ff67d9f36b67 1188 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
<> 157:ff67d9f36b67 1189
<> 157:ff67d9f36b67 1190 return SUCCESS;
<> 157:ff67d9f36b67 1191 }
<> 157:ff67d9f36b67 1192
<> 157:ff67d9f36b67 1193 #if defined(TIM_CCER_CC5E)
<> 157:ff67d9f36b67 1194 /**
<> 157:ff67d9f36b67 1195 * @brief Configure the TIMx output channel 5.
<> 157:ff67d9f36b67 1196 * @param TIMx Timer Instance
<> 157:ff67d9f36b67 1197 * @param TIM_OCInitStruct pointer to the the TIMx output channel 5 configuration data structure
<> 157:ff67d9f36b67 1198 * @note OC5 is not available for all F3 devices
<> 157:ff67d9f36b67 1199 * @retval An ErrorStatus enumeration value:
<> 157:ff67d9f36b67 1200 * - SUCCESS: TIMx registers are de-initialized
<> 157:ff67d9f36b67 1201 * - ERROR: not applicable
<> 157:ff67d9f36b67 1202 */
<> 157:ff67d9f36b67 1203 static ErrorStatus OC5Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
<> 157:ff67d9f36b67 1204 {
<> 157:ff67d9f36b67 1205 uint32_t tmpccmr3 = 0U;
<> 157:ff67d9f36b67 1206 uint32_t tmpccer = 0U;
<> 157:ff67d9f36b67 1207
<> 157:ff67d9f36b67 1208 /* Check the parameters */
<> 157:ff67d9f36b67 1209 assert_param(IS_TIM_CC5_INSTANCE(TIMx));
<> 157:ff67d9f36b67 1210 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
<> 157:ff67d9f36b67 1211 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
<> 157:ff67d9f36b67 1212 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
<> 157:ff67d9f36b67 1213 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
<> 157:ff67d9f36b67 1214 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
<> 157:ff67d9f36b67 1215
<> 157:ff67d9f36b67 1216 /* Disable the Channel 5: Reset the CC5E Bit */
<> 157:ff67d9f36b67 1217 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC5E);
<> 157:ff67d9f36b67 1218
<> 157:ff67d9f36b67 1219 /* Get the TIMx CCER register value */
<> 157:ff67d9f36b67 1220 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
<> 157:ff67d9f36b67 1221
<> 157:ff67d9f36b67 1222 /* Get the TIMx CCMR3 register value */
<> 157:ff67d9f36b67 1223 tmpccmr3 = LL_TIM_ReadReg(TIMx, CCMR3);
<> 157:ff67d9f36b67 1224
<> 157:ff67d9f36b67 1225 /* Select the Output Compare Mode */
<> 157:ff67d9f36b67 1226 MODIFY_REG(tmpccmr3, TIM_CCMR3_OC5M, TIM_OCInitStruct->OCMode);
<> 157:ff67d9f36b67 1227
<> 157:ff67d9f36b67 1228 /* Set the Output Compare Polarity */
<> 157:ff67d9f36b67 1229 MODIFY_REG(tmpccer, TIM_CCER_CC5P, TIM_OCInitStruct->OCPolarity << 16U);
<> 157:ff67d9f36b67 1230
<> 157:ff67d9f36b67 1231 /* Set the Output State */
<> 157:ff67d9f36b67 1232 MODIFY_REG(tmpccer, TIM_CCER_CC5E, TIM_OCInitStruct->OCState << 16U);
<> 157:ff67d9f36b67 1233
<> 157:ff67d9f36b67 1234 if (IS_TIM_BREAK_INSTANCE(TIMx))
<> 157:ff67d9f36b67 1235 {
<> 157:ff67d9f36b67 1236 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
<> 157:ff67d9f36b67 1237 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
<> 157:ff67d9f36b67 1238
<> 157:ff67d9f36b67 1239 /* Set the Output Idle state */
<> 157:ff67d9f36b67 1240 MODIFY_REG(TIMx->CR2, TIM_CR2_OIS5, TIM_OCInitStruct->OCIdleState << 8U);
<> 157:ff67d9f36b67 1241
<> 157:ff67d9f36b67 1242 }
<> 157:ff67d9f36b67 1243
<> 157:ff67d9f36b67 1244 /* Write to TIMx CCMR3 */
<> 157:ff67d9f36b67 1245 LL_TIM_WriteReg(TIMx, CCMR3, tmpccmr3);
<> 157:ff67d9f36b67 1246
<> 157:ff67d9f36b67 1247 /* Set the Capture Compare Register value */
<> 157:ff67d9f36b67 1248 LL_TIM_OC_SetCompareCH5(TIMx, TIM_OCInitStruct->CompareValue);
<> 157:ff67d9f36b67 1249
<> 157:ff67d9f36b67 1250 /* Write to TIMx CCER */
<> 157:ff67d9f36b67 1251 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
<> 157:ff67d9f36b67 1252
<> 157:ff67d9f36b67 1253 return SUCCESS;
<> 157:ff67d9f36b67 1254 }
<> 157:ff67d9f36b67 1255
<> 157:ff67d9f36b67 1256 /**
<> 157:ff67d9f36b67 1257 * @brief Configure the TIMx output channel 6.
<> 157:ff67d9f36b67 1258 * @param TIMx Timer Instance
<> 157:ff67d9f36b67 1259 * @param TIM_OCInitStruct pointer to the the TIMx output channel 6 configuration data structure
<> 157:ff67d9f36b67 1260 * @note OC6 is not available for all F3 devices
<> 157:ff67d9f36b67 1261 * @retval An ErrorStatus enumeration value:
<> 157:ff67d9f36b67 1262 * - SUCCESS: TIMx registers are de-initialized
<> 157:ff67d9f36b67 1263 * - ERROR: not applicable
<> 157:ff67d9f36b67 1264 */
<> 157:ff67d9f36b67 1265 static ErrorStatus OC6Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
<> 157:ff67d9f36b67 1266 {
<> 157:ff67d9f36b67 1267 uint32_t tmpccmr3 = 0U;
<> 157:ff67d9f36b67 1268 uint32_t tmpccer = 0U;
<> 157:ff67d9f36b67 1269
<> 157:ff67d9f36b67 1270 /* Check the parameters */
<> 157:ff67d9f36b67 1271 assert_param(IS_TIM_CC6_INSTANCE(TIMx));
<> 157:ff67d9f36b67 1272 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
<> 157:ff67d9f36b67 1273 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
<> 157:ff67d9f36b67 1274 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
<> 157:ff67d9f36b67 1275 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
<> 157:ff67d9f36b67 1276 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
<> 157:ff67d9f36b67 1277
<> 157:ff67d9f36b67 1278 /* Disable the Channel 5: Reset the CC6E Bit */
<> 157:ff67d9f36b67 1279 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC6E);
<> 157:ff67d9f36b67 1280
<> 157:ff67d9f36b67 1281 /* Get the TIMx CCER register value */
<> 157:ff67d9f36b67 1282 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
<> 157:ff67d9f36b67 1283
<> 157:ff67d9f36b67 1284 /* Get the TIMx CCMR3 register value */
<> 157:ff67d9f36b67 1285 tmpccmr3 = LL_TIM_ReadReg(TIMx, CCMR3);
<> 157:ff67d9f36b67 1286
<> 157:ff67d9f36b67 1287 /* Select the Output Compare Mode */
<> 157:ff67d9f36b67 1288 MODIFY_REG(tmpccmr3, TIM_CCMR3_OC6M, TIM_OCInitStruct->OCMode << 8U);
<> 157:ff67d9f36b67 1289
<> 157:ff67d9f36b67 1290 /* Set the Output Compare Polarity */
<> 157:ff67d9f36b67 1291 MODIFY_REG(tmpccer, TIM_CCER_CC6P, TIM_OCInitStruct->OCPolarity << 20U);
<> 157:ff67d9f36b67 1292
<> 157:ff67d9f36b67 1293 /* Set the Output State */
<> 157:ff67d9f36b67 1294 MODIFY_REG(tmpccer, TIM_CCER_CC6E, TIM_OCInitStruct->OCState << 20U);
<> 157:ff67d9f36b67 1295
<> 157:ff67d9f36b67 1296 if (IS_TIM_BREAK_INSTANCE(TIMx))
<> 157:ff67d9f36b67 1297 {
<> 157:ff67d9f36b67 1298 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
<> 157:ff67d9f36b67 1299 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
<> 157:ff67d9f36b67 1300
<> 157:ff67d9f36b67 1301 /* Set the Output Idle state */
<> 157:ff67d9f36b67 1302 MODIFY_REG(TIMx->CR2, TIM_CR2_OIS6, TIM_OCInitStruct->OCIdleState << 10U);
<> 157:ff67d9f36b67 1303 }
<> 157:ff67d9f36b67 1304
<> 157:ff67d9f36b67 1305 /* Write to TIMx CCMR3 */
<> 157:ff67d9f36b67 1306 LL_TIM_WriteReg(TIMx, CCMR3, tmpccmr3);
<> 157:ff67d9f36b67 1307
<> 157:ff67d9f36b67 1308 /* Set the Capture Compare Register value */
<> 157:ff67d9f36b67 1309 LL_TIM_OC_SetCompareCH6(TIMx, TIM_OCInitStruct->CompareValue);
<> 157:ff67d9f36b67 1310
<> 157:ff67d9f36b67 1311 /* Write to TIMx CCER */
<> 157:ff67d9f36b67 1312 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
<> 157:ff67d9f36b67 1313
<> 157:ff67d9f36b67 1314 return SUCCESS;
<> 157:ff67d9f36b67 1315 }
<> 157:ff67d9f36b67 1316 #endif /* TIM_CCER_CC5E */
<> 157:ff67d9f36b67 1317
<> 157:ff67d9f36b67 1318 /**
<> 157:ff67d9f36b67 1319 * @brief Configure the TIMx input channel 1.
<> 157:ff67d9f36b67 1320 * @param TIMx Timer Instance
<> 157:ff67d9f36b67 1321 * @param TIM_ICInitStruct pointer to the the TIMx input channel 1 configuration data structure
<> 157:ff67d9f36b67 1322 * @retval An ErrorStatus enumeration value:
<> 157:ff67d9f36b67 1323 * - SUCCESS: TIMx registers are de-initialized
<> 157:ff67d9f36b67 1324 * - ERROR: not applicable
<> 157:ff67d9f36b67 1325 */
<> 157:ff67d9f36b67 1326 static ErrorStatus IC1Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
<> 157:ff67d9f36b67 1327 {
<> 157:ff67d9f36b67 1328 /* Check the parameters */
<> 157:ff67d9f36b67 1329 assert_param(IS_TIM_CC1_INSTANCE(TIMx));
<> 157:ff67d9f36b67 1330 assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
<> 157:ff67d9f36b67 1331 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
<> 157:ff67d9f36b67 1332 assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
<> 157:ff67d9f36b67 1333 assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
<> 157:ff67d9f36b67 1334
<> 157:ff67d9f36b67 1335 /* Disable the Channel 1: Reset the CC1E Bit */
<> 157:ff67d9f36b67 1336 TIMx->CCER &= (uint32_t)~TIM_CCER_CC1E;
<> 157:ff67d9f36b67 1337
<> 157:ff67d9f36b67 1338 /* Select the Input and set the filter and the prescaler value */
<> 157:ff67d9f36b67 1339 MODIFY_REG(TIMx->CCMR1,
<> 157:ff67d9f36b67 1340 (TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC),
<> 157:ff67d9f36b67 1341 (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 16U);
<> 157:ff67d9f36b67 1342
<> 157:ff67d9f36b67 1343 /* Select the Polarity and set the CC1E Bit */
<> 157:ff67d9f36b67 1344 MODIFY_REG(TIMx->CCER,
<> 157:ff67d9f36b67 1345 (TIM_CCER_CC1P | TIM_CCER_CC1NP),
<> 157:ff67d9f36b67 1346 (TIM_ICInitStruct->ICPolarity | TIM_CCER_CC1E));
<> 157:ff67d9f36b67 1347
<> 157:ff67d9f36b67 1348 return SUCCESS;
<> 157:ff67d9f36b67 1349 }
<> 157:ff67d9f36b67 1350
<> 157:ff67d9f36b67 1351 /**
<> 157:ff67d9f36b67 1352 * @brief Configure the TIMx input channel 2.
<> 157:ff67d9f36b67 1353 * @param TIMx Timer Instance
<> 157:ff67d9f36b67 1354 * @param TIM_ICInitStruct pointer to the the TIMx input channel 2 configuration data structure
<> 157:ff67d9f36b67 1355 * @retval An ErrorStatus enumeration value:
<> 157:ff67d9f36b67 1356 * - SUCCESS: TIMx registers are de-initialized
<> 157:ff67d9f36b67 1357 * - ERROR: not applicable
<> 157:ff67d9f36b67 1358 */
<> 157:ff67d9f36b67 1359 static ErrorStatus IC2Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
<> 157:ff67d9f36b67 1360 {
<> 157:ff67d9f36b67 1361 /* Check the parameters */
<> 157:ff67d9f36b67 1362 assert_param(IS_TIM_CC2_INSTANCE(TIMx));
<> 157:ff67d9f36b67 1363 assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
<> 157:ff67d9f36b67 1364 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
<> 157:ff67d9f36b67 1365 assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
<> 157:ff67d9f36b67 1366 assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
<> 157:ff67d9f36b67 1367
<> 157:ff67d9f36b67 1368 /* Disable the Channel 2: Reset the CC2E Bit */
<> 157:ff67d9f36b67 1369 TIMx->CCER &= (uint32_t)~TIM_CCER_CC2E;
<> 157:ff67d9f36b67 1370
<> 157:ff67d9f36b67 1371 /* Select the Input and set the filter and the prescaler value */
<> 157:ff67d9f36b67 1372 MODIFY_REG(TIMx->CCMR1,
<> 157:ff67d9f36b67 1373 (TIM_CCMR1_CC2S | TIM_CCMR1_IC2F | TIM_CCMR1_IC2PSC),
<> 157:ff67d9f36b67 1374 (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U);
<> 157:ff67d9f36b67 1375
<> 157:ff67d9f36b67 1376 /* Select the Polarity and set the CC2E Bit */
<> 157:ff67d9f36b67 1377 MODIFY_REG(TIMx->CCER,
<> 157:ff67d9f36b67 1378 (TIM_CCER_CC2P | TIM_CCER_CC2NP),
<> 157:ff67d9f36b67 1379 ((TIM_ICInitStruct->ICPolarity << 4U) | TIM_CCER_CC2E));
<> 157:ff67d9f36b67 1380
<> 157:ff67d9f36b67 1381 return SUCCESS;
<> 157:ff67d9f36b67 1382 }
<> 157:ff67d9f36b67 1383
<> 157:ff67d9f36b67 1384 /**
<> 157:ff67d9f36b67 1385 * @brief Configure the TIMx input channel 3.
<> 157:ff67d9f36b67 1386 * @param TIMx Timer Instance
<> 157:ff67d9f36b67 1387 * @param TIM_ICInitStruct pointer to the the TIMx input channel 3 configuration data structure
<> 157:ff67d9f36b67 1388 * @retval An ErrorStatus enumeration value:
<> 157:ff67d9f36b67 1389 * - SUCCESS: TIMx registers are de-initialized
<> 157:ff67d9f36b67 1390 * - ERROR: not applicable
<> 157:ff67d9f36b67 1391 */
<> 157:ff67d9f36b67 1392 static ErrorStatus IC3Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
<> 157:ff67d9f36b67 1393 {
<> 157:ff67d9f36b67 1394 /* Check the parameters */
<> 157:ff67d9f36b67 1395 assert_param(IS_TIM_CC3_INSTANCE(TIMx));
<> 157:ff67d9f36b67 1396 assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
<> 157:ff67d9f36b67 1397 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
<> 157:ff67d9f36b67 1398 assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
<> 157:ff67d9f36b67 1399 assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
<> 157:ff67d9f36b67 1400
<> 157:ff67d9f36b67 1401 /* Disable the Channel 3: Reset the CC3E Bit */
<> 157:ff67d9f36b67 1402 TIMx->CCER &= (uint32_t)~TIM_CCER_CC3E;
<> 157:ff67d9f36b67 1403
<> 157:ff67d9f36b67 1404 /* Select the Input and set the filter and the prescaler value */
<> 157:ff67d9f36b67 1405 MODIFY_REG(TIMx->CCMR2,
<> 157:ff67d9f36b67 1406 (TIM_CCMR2_CC3S | TIM_CCMR2_IC3F | TIM_CCMR2_IC3PSC),
<> 157:ff67d9f36b67 1407 (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 16U);
<> 157:ff67d9f36b67 1408
<> 157:ff67d9f36b67 1409 /* Select the Polarity and set the CC3E Bit */
<> 157:ff67d9f36b67 1410 MODIFY_REG(TIMx->CCER,
<> 157:ff67d9f36b67 1411 (TIM_CCER_CC3P | TIM_CCER_CC3NP),
<> 157:ff67d9f36b67 1412 ((TIM_ICInitStruct->ICPolarity << 8U) | TIM_CCER_CC3E));
<> 157:ff67d9f36b67 1413
<> 157:ff67d9f36b67 1414 return SUCCESS;
<> 157:ff67d9f36b67 1415 }
<> 157:ff67d9f36b67 1416
<> 157:ff67d9f36b67 1417 /**
<> 157:ff67d9f36b67 1418 * @brief Configure the TIMx input channel 4.
<> 157:ff67d9f36b67 1419 * @param TIMx Timer Instance
<> 157:ff67d9f36b67 1420 * @param TIM_ICInitStruct pointer to the the TIMx input channel 4 configuration data structure
<> 157:ff67d9f36b67 1421 * @retval An ErrorStatus enumeration value:
<> 157:ff67d9f36b67 1422 * - SUCCESS: TIMx registers are de-initialized
<> 157:ff67d9f36b67 1423 * - ERROR: not applicable
<> 157:ff67d9f36b67 1424 */
<> 157:ff67d9f36b67 1425 static ErrorStatus IC4Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
<> 157:ff67d9f36b67 1426 {
<> 157:ff67d9f36b67 1427 /* Check the parameters */
<> 157:ff67d9f36b67 1428 assert_param(IS_TIM_CC4_INSTANCE(TIMx));
<> 157:ff67d9f36b67 1429 assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
<> 157:ff67d9f36b67 1430 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
<> 157:ff67d9f36b67 1431 assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
<> 157:ff67d9f36b67 1432 assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
<> 157:ff67d9f36b67 1433
<> 157:ff67d9f36b67 1434 /* Disable the Channel 4: Reset the CC4E Bit */
<> 157:ff67d9f36b67 1435 TIMx->CCER &= (uint32_t)~TIM_CCER_CC4E;
<> 157:ff67d9f36b67 1436
<> 157:ff67d9f36b67 1437 /* Select the Input and set the filter and the prescaler value */
<> 157:ff67d9f36b67 1438 MODIFY_REG(TIMx->CCMR2,
<> 157:ff67d9f36b67 1439 (TIM_CCMR2_CC4S | TIM_CCMR2_IC4F | TIM_CCMR2_IC4PSC),
<> 157:ff67d9f36b67 1440 (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U);
<> 157:ff67d9f36b67 1441
<> 157:ff67d9f36b67 1442 /* Select the Polarity and set the CC2E Bit */
<> 157:ff67d9f36b67 1443 MODIFY_REG(TIMx->CCER,
<> 157:ff67d9f36b67 1444 (TIM_CCER_CC4P | TIM_CCER_CC4NP),
<> 157:ff67d9f36b67 1445 ((TIM_ICInitStruct->ICPolarity << 12U) | TIM_CCER_CC4E));
<> 157:ff67d9f36b67 1446
<> 157:ff67d9f36b67 1447 return SUCCESS;
<> 157:ff67d9f36b67 1448 }
<> 157:ff67d9f36b67 1449
<> 157:ff67d9f36b67 1450
<> 157:ff67d9f36b67 1451 /**
<> 157:ff67d9f36b67 1452 * @}
<> 157:ff67d9f36b67 1453 */
<> 157:ff67d9f36b67 1454
<> 157:ff67d9f36b67 1455 /**
<> 157:ff67d9f36b67 1456 * @}
<> 157:ff67d9f36b67 1457 */
<> 157:ff67d9f36b67 1458
<> 157:ff67d9f36b67 1459 #endif /* TIM1 || TIM2 || TIM3 || TIM4 || TIM5 || TIM6 || TIM7 || TIM8 || TIM12 || TIM13 || TIM14 || TIM15 || TIM16 || TIM17 || TIM18 || TIM19 || TIM20 */
<> 157:ff67d9f36b67 1460
<> 157:ff67d9f36b67 1461 /**
<> 157:ff67d9f36b67 1462 * @}
<> 157:ff67d9f36b67 1463 */
<> 157:ff67d9f36b67 1464
<> 157:ff67d9f36b67 1465 #endif /* USE_FULL_LL_DRIVER */
<> 157:ff67d9f36b67 1466
<> 157:ff67d9f36b67 1467 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/