mbed official / mbed-dev

Important changes to repositories hosted on mbed.com

Mbed hosted mercurial repositories are deprecated and are due to be permanently deleted in July 2026.

To keep a copy of this software download the repository Zip archive or clone locally using Mercurial.

It is also possible to export all your personal repositories from the account settings page.

Dependents:   Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_ll_fmc.c@157:ff67d9f36b67, 2017-02-02 (annotated)

Committer:
<>
Date:
Thu Feb 02 17:01:33 2017 +0000
Revision:
157:ff67d9f36b67
Parent:
149:156823d33999
Child:
186:707f6e361f3e
This updates the lib to the mbed lib v135

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f3xx_ll_fmc.c
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 157:ff67d9f36b67 5 * @version V1.4.0
<> 157:ff67d9f36b67 6 * @date 16-December-2016
<> 144:ef7eb2e8f9f7 7 * @brief FMC Low Layer HAL module driver.
<> 157:ff67d9f36b67 8 *
<> 157:ff67d9f36b67 9 * This file provides firmware functions to manage the following
<> 144:ef7eb2e8f9f7 10 * functionalities of the Flexible Memory Controller (FMC) peripheral memories:
<> 144:ef7eb2e8f9f7 11 * + Initialization/de-initialization functions
<> 157:ff67d9f36b67 12 * + Peripheral Control functions
<> 144:ef7eb2e8f9f7 13 * + Peripheral State functions
<> 157:ff67d9f36b67 14 *
<> 144:ef7eb2e8f9f7 15 @verbatim
<> 157:ff67d9f36b67 16 =============================================================================
<> 144:ef7eb2e8f9f7 17 ##### FMC peripheral features #####
<> 157:ff67d9f36b67 18 =============================================================================
<> 157:ff67d9f36b67 19 [..] The Flexible memory controller (FMC) includes following memory controllers:
<> 157:ff67d9f36b67 20 (+) The NOR/PSRAM memory controller
<> 157:ff67d9f36b67 21 (+) The PC Card memory controller
<> 157:ff67d9f36b67 22 (+) The NAND memory controller
<> 157:ff67d9f36b67 23
<> 157:ff67d9f36b67 24 [..] The FMC functional block makes the interface with synchronous and asynchronous static
<> 157:ff67d9f36b67 25 memories and 16-bit PC memory cards. Its main purposes are:
<> 157:ff67d9f36b67 26 (+) to translate AHB transactions into the appropriate external device protocol.
<> 157:ff67d9f36b67 27 (+) to meet the access time requirements of the external memory devices.
<> 157:ff67d9f36b67 28
<> 157:ff67d9f36b67 29 [..] All external memories share the addresses, data and control signals with the controller.
<> 157:ff67d9f36b67 30 Each external device is accessed by means of a unique Chip Select. The FMC performs
<> 157:ff67d9f36b67 31 only one access at a time to an external device.
<> 157:ff67d9f36b67 32 The main features of the FMC controller are the following:
<> 157:ff67d9f36b67 33 (+) Interface with static-memory mapped devices including:
<> 157:ff67d9f36b67 34 (++) Static random access memory (SRAM).
<> 157:ff67d9f36b67 35 (++) NOR Flash memory.
<> 157:ff67d9f36b67 36 (++) PSRAM (4 memory banks).
<> 157:ff67d9f36b67 37 (++) 16-bit PC Card compatible devices
<> 157:ff67d9f36b67 38 (++) Two banks of NAND Flash memory with ECC hardware to check up to 8 Kbytes of
<> 144:ef7eb2e8f9f7 39 data
<> 157:ff67d9f36b67 40 (+) Independent Chip Select control for each memory bank
<> 157:ff67d9f36b67 41 (+) Independent configuration for each memory bank
<> 157:ff67d9f36b67 42
<> 144:ef7eb2e8f9f7 43 @endverbatim
<> 144:ef7eb2e8f9f7 44 ******************************************************************************
<> 144:ef7eb2e8f9f7 45 * @attention
<> 144:ef7eb2e8f9f7 46 *
<> 157:ff67d9f36b67 47 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 48 *
<> 144:ef7eb2e8f9f7 49 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 50 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 51 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 52 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 53 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 54 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 55 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 56 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 57 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 58 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 59 *
<> 144:ef7eb2e8f9f7 60 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 61 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 62 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 63 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 64 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 65 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 66 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 67 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 68 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 69 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 70 *
<> 144:ef7eb2e8f9f7 71 ******************************************************************************
<> 157:ff67d9f36b67 72 */
<> 144:ef7eb2e8f9f7 73
<> 144:ef7eb2e8f9f7 74 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 75 #include "stm32f3xx_hal.h"
<> 144:ef7eb2e8f9f7 76
<> 144:ef7eb2e8f9f7 77 /** @addtogroup STM32F3xx_HAL_Driver
<> 144:ef7eb2e8f9f7 78 * @{
<> 144:ef7eb2e8f9f7 79 */
<> 144:ef7eb2e8f9f7 80
<> 157:ff67d9f36b67 81 #if defined(FMC_BANK1)
<> 157:ff67d9f36b67 82
<> 157:ff67d9f36b67 83 #if defined(HAL_SRAM_MODULE_ENABLED) || defined(HAL_NOR_MODULE_ENABLED) || defined(HAL_PCCARD_MODULE_ENABLED) || defined(HAL_NAND_MODULE_ENABLED)
<> 157:ff67d9f36b67 84
<> 157:ff67d9f36b67 85 /** @defgroup FMC_LL FMC Low Layer
<> 144:ef7eb2e8f9f7 86 * @brief FMC driver modules
<> 144:ef7eb2e8f9f7 87 * @{
<> 144:ef7eb2e8f9f7 88 */
<> 144:ef7eb2e8f9f7 89
<> 144:ef7eb2e8f9f7 90 /* Private typedef -----------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 91 /* Private define ------------------------------------------------------------*/
<> 157:ff67d9f36b67 92 /** @defgroup FMC_LL_Private_Constants FMC Low Layer Private Constants
<> 144:ef7eb2e8f9f7 93 * @{
<> 144:ef7eb2e8f9f7 94 */
<> 144:ef7eb2e8f9f7 95
<> 157:ff67d9f36b67 96 /* ----------------------- FMC registers bit mask --------------------------- */
<> 157:ff67d9f36b67 97 /* --- PCR Register ---*/
<> 157:ff67d9f36b67 98 /* PCR register clear mask */
<> 157:ff67d9f36b67 99 #define PCR_CLEAR_MASK ((uint32_t)(FMC_PCRx_PWAITEN | FMC_PCRx_PBKEN | \
<> 157:ff67d9f36b67 100 FMC_PCRx_PTYP | FMC_PCRx_PWID | \
<> 157:ff67d9f36b67 101 FMC_PCRx_ECCEN | FMC_PCRx_TCLR | \
<> 157:ff67d9f36b67 102 FMC_PCRx_TAR | FMC_PCRx_ECCPS))
<> 157:ff67d9f36b67 103
<> 157:ff67d9f36b67 104 /* --- PMEM Register ---*/
<> 157:ff67d9f36b67 105 /* PMEM register clear mask */
<> 157:ff67d9f36b67 106 #define PMEM_CLEAR_MASK ((uint32_t)(FMC_PMEMx_MEMSETx | FMC_PMEMx_MEMWAITx |\
<> 157:ff67d9f36b67 107 FMC_PMEMx_MEMHOLDx | FMC_PMEMx_MEMHIZx))
<> 157:ff67d9f36b67 108
<> 157:ff67d9f36b67 109 /* --- PATT Register ---*/
<> 157:ff67d9f36b67 110 /* PATT register clear mask */
<> 157:ff67d9f36b67 111 #define PATT_CLEAR_MASK ((uint32_t)(FMC_PATTx_ATTSETx | FMC_PATTx_ATTWAITx |\
<> 157:ff67d9f36b67 112 FMC_PATTx_ATTHOLDx | FMC_PATTx_ATTHIZx))
<> 157:ff67d9f36b67 113
<> 157:ff67d9f36b67 114 /* --- BCR Register ---*/
<> 157:ff67d9f36b67 115 /* BCR register clear mask */
<> 157:ff67d9f36b67 116 #define BCR_CLEAR_MASK ((uint32_t)(FMC_BCRx_MBKEN | FMC_BCRx_MUXEN |\
<> 157:ff67d9f36b67 117 FMC_BCRx_MTYP | FMC_BCRx_MWID |\
<> 157:ff67d9f36b67 118 FMC_BCRx_FACCEN | FMC_BCRx_BURSTEN |\
<> 157:ff67d9f36b67 119 FMC_BCRx_WAITPOL | FMC_BCRx_WRAPMOD |\
<> 157:ff67d9f36b67 120 FMC_BCRx_WAITCFG | FMC_BCRx_WREN |\
<> 157:ff67d9f36b67 121 FMC_BCRx_WAITEN | FMC_BCRx_EXTMOD |\
<> 157:ff67d9f36b67 122 FMC_BCRx_ASYNCWAIT | FMC_BCRx_CBURSTRW |\
<> 157:ff67d9f36b67 123 FMC_BCR1_CCLKEN))
<> 157:ff67d9f36b67 124
<> 157:ff67d9f36b67 125 /* --- BTR Register ---*/
<> 157:ff67d9f36b67 126 /* BTR register clear mask */
<> 157:ff67d9f36b67 127 #define BTR_CLEAR_MASK ((uint32_t)(FMC_BTRx_ADDSET | FMC_BTRx_ADDHLD |\
<> 157:ff67d9f36b67 128 FMC_BTRx_DATAST | FMC_BTRx_BUSTURN |\
<> 157:ff67d9f36b67 129 FMC_BTRx_CLKDIV | FMC_BTRx_DATLAT |\
<> 157:ff67d9f36b67 130 FMC_BTRx_ACCMOD))
<> 157:ff67d9f36b67 131
<> 157:ff67d9f36b67 132 /* --- BWTR Register ---*/
<> 157:ff67d9f36b67 133 /* BWTR register clear mask */
<> 157:ff67d9f36b67 134 #define BWTR_CLEAR_MASK ((uint32_t)(FMC_BWTRx_ADDSET | FMC_BWTRx_ADDHLD |\
<> 157:ff67d9f36b67 135 FMC_BWTRx_DATAST | FMC_BWTRx_ACCMOD))
<> 157:ff67d9f36b67 136
<> 157:ff67d9f36b67 137 /* --- PIO4 Register ---*/
<> 157:ff67d9f36b67 138 /* PIO4 register clear mask */
<> 157:ff67d9f36b67 139 #define PIO4_CLEAR_MASK ((uint32_t)(FMC_PIO4_IOSET4 | FMC_PIO4_IOWAIT4 | \
<> 157:ff67d9f36b67 140 FMC_PIO4_IOHOLD4 | FMC_PIO4_IOHIZ4))
<> 157:ff67d9f36b67 141 /**
<> 157:ff67d9f36b67 142 * @}
<> 157:ff67d9f36b67 143 */
<> 157:ff67d9f36b67 144
<> 157:ff67d9f36b67 145 /* Private macro -------------------------------------------------------------*/
<> 157:ff67d9f36b67 146 /** @defgroup FMC_LL_Private_Macros FMC Low Layer Private Macros
<> 157:ff67d9f36b67 147 * @{
<> 157:ff67d9f36b67 148 */
<> 157:ff67d9f36b67 149
<> 157:ff67d9f36b67 150 /**
<> 157:ff67d9f36b67 151 * @}
<> 157:ff67d9f36b67 152 */
<> 157:ff67d9f36b67 153
<> 157:ff67d9f36b67 154 /* Private variables ---------------------------------------------------------*/
<> 157:ff67d9f36b67 155 /* Private function prototypes -----------------------------------------------*/
<> 157:ff67d9f36b67 156 /* Exported functions --------------------------------------------------------*/
<> 157:ff67d9f36b67 157
<> 157:ff67d9f36b67 158 /** @defgroup FMC_LL_Exported_Functions FMC Low Layer Exported Functions
<> 157:ff67d9f36b67 159 * @{
<> 157:ff67d9f36b67 160 */
<> 157:ff67d9f36b67 161
<> 157:ff67d9f36b67 162 /** @defgroup FMC_NORSRAM FMC NORSRAM Controller functions
<> 157:ff67d9f36b67 163 * @brief NORSRAM Controller functions
<> 144:ef7eb2e8f9f7 164 *
<> 157:ff67d9f36b67 165 @verbatim
<> 157:ff67d9f36b67 166 ==============================================================================
<> 144:ef7eb2e8f9f7 167 ##### How to use NORSRAM device driver #####
<> 144:ef7eb2e8f9f7 168 ==============================================================================
<> 157:ff67d9f36b67 169
<> 157:ff67d9f36b67 170 [..]
<> 144:ef7eb2e8f9f7 171 This driver contains a set of APIs to interface with the FMC NORSRAM banks in order
<> 144:ef7eb2e8f9f7 172 to run the NORSRAM external devices.
<> 157:ff67d9f36b67 173
<> 157:ff67d9f36b67 174 (+) FMC NORSRAM bank reset using the function FMC_NORSRAM_DeInit()
<> 144:ef7eb2e8f9f7 175 (+) FMC NORSRAM bank control configuration using the function FMC_NORSRAM_Init()
<> 144:ef7eb2e8f9f7 176 (+) FMC NORSRAM bank timing configuration using the function FMC_NORSRAM_Timing_Init()
<> 157:ff67d9f36b67 177 (+) FMC NORSRAM bank extended timing configuration using the function
<> 144:ef7eb2e8f9f7 178 FMC_NORSRAM_Extended_Timing_Init()
<> 144:ef7eb2e8f9f7 179 (+) FMC NORSRAM bank enable/disable write operation using the functions
<> 144:ef7eb2e8f9f7 180 FMC_NORSRAM_WriteOperation_Enable()/FMC_NORSRAM_WriteOperation_Disable()
<> 157:ff67d9f36b67 181
<> 144:ef7eb2e8f9f7 182
<> 144:ef7eb2e8f9f7 183 @endverbatim
<> 144:ef7eb2e8f9f7 184 * @{
<> 144:ef7eb2e8f9f7 185 */
<> 157:ff67d9f36b67 186
<> 157:ff67d9f36b67 187 /** @defgroup FMC_NORSRAM_Group1 Initialization/de-initialization functions
<> 157:ff67d9f36b67 188 * @brief Initialization and Configuration functions
<> 144:ef7eb2e8f9f7 189 *
<> 157:ff67d9f36b67 190 @verbatim
<> 144:ef7eb2e8f9f7 191 ==============================================================================
<> 144:ef7eb2e8f9f7 192 ##### Initialization and de_initialization functions #####
<> 144:ef7eb2e8f9f7 193 ==============================================================================
<> 157:ff67d9f36b67 194 [..]
<> 144:ef7eb2e8f9f7 195 This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 196 (+) Initialize and configure the FMC NORSRAM interface
<> 157:ff67d9f36b67 197 (+) De-initialize the FMC NORSRAM interface
<> 157:ff67d9f36b67 198 (+) Configure the FMC clock and associated GPIOs
<> 157:ff67d9f36b67 199
<> 144:ef7eb2e8f9f7 200 @endverbatim
<> 144:ef7eb2e8f9f7 201 * @{
<> 144:ef7eb2e8f9f7 202 */
<> 157:ff67d9f36b67 203
<> 144:ef7eb2e8f9f7 204 /**
<> 144:ef7eb2e8f9f7 205 * @brief Initialize the FMC_NORSRAM device according to the specified
<> 144:ef7eb2e8f9f7 206 * control parameters in the FMC_NORSRAM_InitTypeDef
<> 157:ff67d9f36b67 207 * @param Device Pointer to NORSRAM device instance
<> 157:ff67d9f36b67 208 * @param Init Pointer to NORSRAM Initialization structure
<> 144:ef7eb2e8f9f7 209 * @retval HAL status
<> 144:ef7eb2e8f9f7 210 */
<> 157:ff67d9f36b67 211 HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_InitTypeDef *Init)
<> 157:ff67d9f36b67 212 {
<> 144:ef7eb2e8f9f7 213 /* Check the parameters */
<> 144:ef7eb2e8f9f7 214 assert_param(IS_FMC_NORSRAM_DEVICE(Device));
<> 144:ef7eb2e8f9f7 215 assert_param(IS_FMC_NORSRAM_BANK(Init->NSBank));
<> 144:ef7eb2e8f9f7 216 assert_param(IS_FMC_MUX(Init->DataAddressMux));
<> 144:ef7eb2e8f9f7 217 assert_param(IS_FMC_MEMORY(Init->MemoryType));
<> 144:ef7eb2e8f9f7 218 assert_param(IS_FMC_NORSRAM_MEMORY_WIDTH(Init->MemoryDataWidth));
<> 144:ef7eb2e8f9f7 219 assert_param(IS_FMC_BURSTMODE(Init->BurstAccessMode));
<> 144:ef7eb2e8f9f7 220 assert_param(IS_FMC_WAIT_POLARITY(Init->WaitSignalPolarity));
<> 144:ef7eb2e8f9f7 221 assert_param(IS_FMC_WRAP_MODE(Init->WrapMode));
<> 144:ef7eb2e8f9f7 222 assert_param(IS_FMC_WAIT_SIGNAL_ACTIVE(Init->WaitSignalActive));
<> 144:ef7eb2e8f9f7 223 assert_param(IS_FMC_WRITE_OPERATION(Init->WriteOperation));
<> 144:ef7eb2e8f9f7 224 assert_param(IS_FMC_WAITE_SIGNAL(Init->WaitSignal));
<> 144:ef7eb2e8f9f7 225 assert_param(IS_FMC_EXTENDED_MODE(Init->ExtendedMode));
<> 144:ef7eb2e8f9f7 226 assert_param(IS_FMC_ASYNWAIT(Init->AsynchronousWait));
<> 144:ef7eb2e8f9f7 227 assert_param(IS_FMC_WRITE_BURST(Init->WriteBurst));
<> 157:ff67d9f36b67 228 assert_param(IS_FMC_CONTINOUS_CLOCK(Init->ContinuousClock));
<> 157:ff67d9f36b67 229
<> 157:ff67d9f36b67 230 /* Disable NORSRAM Device */
<> 157:ff67d9f36b67 231 __FMC_NORSRAM_DISABLE(Device, Init->NSBank);
<> 157:ff67d9f36b67 232
<> 144:ef7eb2e8f9f7 233 /* Set NORSRAM device control parameters */
<> 157:ff67d9f36b67 234 if (Init->MemoryType == FMC_MEMORY_TYPE_NOR)
<> 144:ef7eb2e8f9f7 235 {
<> 157:ff67d9f36b67 236 MODIFY_REG(Device->BTCR[Init->NSBank], BCR_CLEAR_MASK, (uint32_t)(FMC_NORSRAM_FLASH_ACCESS_ENABLE
<> 157:ff67d9f36b67 237 | Init->DataAddressMux
<> 157:ff67d9f36b67 238 | Init->MemoryType
<> 157:ff67d9f36b67 239 | Init->MemoryDataWidth
<> 157:ff67d9f36b67 240 | Init->BurstAccessMode
<> 157:ff67d9f36b67 241 | Init->WaitSignalPolarity
<> 157:ff67d9f36b67 242 | Init->WrapMode
<> 157:ff67d9f36b67 243 | Init->WaitSignalActive
<> 157:ff67d9f36b67 244 | Init->WriteOperation
<> 157:ff67d9f36b67 245 | Init->WaitSignal
<> 157:ff67d9f36b67 246 | Init->ExtendedMode
<> 157:ff67d9f36b67 247 | Init->AsynchronousWait
<> 157:ff67d9f36b67 248 | Init->WriteBurst
<> 157:ff67d9f36b67 249 | Init->ContinuousClock
<> 157:ff67d9f36b67 250 )
<> 157:ff67d9f36b67 251 );
<> 144:ef7eb2e8f9f7 252 }
<> 157:ff67d9f36b67 253 else
<> 157:ff67d9f36b67 254 {
<> 157:ff67d9f36b67 255 MODIFY_REG(Device->BTCR[Init->NSBank], BCR_CLEAR_MASK, (uint32_t)(FMC_NORSRAM_FLASH_ACCESS_DISABLE
<> 157:ff67d9f36b67 256 | Init->DataAddressMux
<> 157:ff67d9f36b67 257 | Init->MemoryType
<> 157:ff67d9f36b67 258 | Init->MemoryDataWidth
<> 157:ff67d9f36b67 259 | Init->BurstAccessMode
<> 157:ff67d9f36b67 260 | Init->WaitSignalPolarity
<> 157:ff67d9f36b67 261 | Init->WrapMode
<> 157:ff67d9f36b67 262 | Init->WaitSignalActive
<> 157:ff67d9f36b67 263 | Init->WriteOperation
<> 157:ff67d9f36b67 264 | Init->WaitSignal
<> 157:ff67d9f36b67 265 | Init->ExtendedMode
<> 157:ff67d9f36b67 266 | Init->AsynchronousWait
<> 157:ff67d9f36b67 267 | Init->WriteBurst
<> 157:ff67d9f36b67 268 | Init->ContinuousClock
<> 157:ff67d9f36b67 269 )
<> 157:ff67d9f36b67 270 );
<> 157:ff67d9f36b67 271 }
<> 144:ef7eb2e8f9f7 272
<> 144:ef7eb2e8f9f7 273 /* Configure synchronous mode when Continuous clock is enabled for bank2..4 */
<> 157:ff67d9f36b67 274 if ((Init->ContinuousClock == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC) && (Init->NSBank != FMC_NORSRAM_BANK1))
<> 157:ff67d9f36b67 275 {
<> 157:ff67d9f36b67 276 MODIFY_REG(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN, Init->ContinuousClock);
<> 157:ff67d9f36b67 277 }
<> 157:ff67d9f36b67 278
<> 144:ef7eb2e8f9f7 279 return HAL_OK;
<> 144:ef7eb2e8f9f7 280 }
<> 144:ef7eb2e8f9f7 281
<> 144:ef7eb2e8f9f7 282
<> 144:ef7eb2e8f9f7 283 /**
<> 157:ff67d9f36b67 284 * @brief DeInitialize the FMC_NORSRAM peripheral
<> 157:ff67d9f36b67 285 * @param Device Pointer to NORSRAM device instance
<> 157:ff67d9f36b67 286 * @param ExDevice Pointer to NORSRAM extended mode device instance
<> 157:ff67d9f36b67 287 * @param Bank NORSRAM bank number
<> 144:ef7eb2e8f9f7 288 * @retval HAL status
<> 144:ef7eb2e8f9f7 289 */
<> 144:ef7eb2e8f9f7 290 HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank)
<> 144:ef7eb2e8f9f7 291 {
<> 144:ef7eb2e8f9f7 292 /* Check the parameters */
<> 144:ef7eb2e8f9f7 293 assert_param(IS_FMC_NORSRAM_DEVICE(Device));
<> 144:ef7eb2e8f9f7 294 assert_param(IS_FMC_NORSRAM_EXTENDED_DEVICE(ExDevice));
<> 144:ef7eb2e8f9f7 295 assert_param(IS_FMC_NORSRAM_BANK(Bank));
<> 157:ff67d9f36b67 296
<> 144:ef7eb2e8f9f7 297 /* Disable the FMC_NORSRAM device */
<> 144:ef7eb2e8f9f7 298 __FMC_NORSRAM_DISABLE(Device, Bank);
<> 157:ff67d9f36b67 299
<> 144:ef7eb2e8f9f7 300 /* De-initialize the FMC_NORSRAM device */
<> 144:ef7eb2e8f9f7 301 /* FMC_NORSRAM_BANK1 */
<> 157:ff67d9f36b67 302 if (Bank == FMC_NORSRAM_BANK1)
<> 144:ef7eb2e8f9f7 303 {
<> 157:ff67d9f36b67 304 Device->BTCR[Bank] = 0x000030DB;
<> 144:ef7eb2e8f9f7 305 }
<> 144:ef7eb2e8f9f7 306 /* FMC_NORSRAM_BANK2, FMC_NORSRAM_BANK3 or FMC_NORSRAM_BANK4 */
<> 144:ef7eb2e8f9f7 307 else
<> 157:ff67d9f36b67 308 {
<> 157:ff67d9f36b67 309 Device->BTCR[Bank] = 0x000030D2;
<> 144:ef7eb2e8f9f7 310 }
<> 157:ff67d9f36b67 311
<> 144:ef7eb2e8f9f7 312 Device->BTCR[Bank + 1] = 0x0FFFFFFF;
<> 144:ef7eb2e8f9f7 313 ExDevice->BWTR[Bank] = 0x0FFFFFFF;
<> 157:ff67d9f36b67 314
<> 144:ef7eb2e8f9f7 315 return HAL_OK;
<> 144:ef7eb2e8f9f7 316 }
<> 144:ef7eb2e8f9f7 317
<> 144:ef7eb2e8f9f7 318
<> 144:ef7eb2e8f9f7 319 /**
<> 144:ef7eb2e8f9f7 320 * @brief Initialize the FMC_NORSRAM Timing according to the specified
<> 144:ef7eb2e8f9f7 321 * parameters in the FMC_NORSRAM_TimingTypeDef
<> 157:ff67d9f36b67 322 * @param Device Pointer to NORSRAM device instance
<> 157:ff67d9f36b67 323 * @param Timing Pointer to NORSRAM Timing structure
<> 157:ff67d9f36b67 324 * @param Bank NORSRAM bank number
<> 144:ef7eb2e8f9f7 325 * @retval HAL status
<> 144:ef7eb2e8f9f7 326 */
<> 144:ef7eb2e8f9f7 327 HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank)
<> 144:ef7eb2e8f9f7 328 {
<> 144:ef7eb2e8f9f7 329 uint32_t tmpr = 0;
<> 157:ff67d9f36b67 330
<> 144:ef7eb2e8f9f7 331 /* Check the parameters */
<> 144:ef7eb2e8f9f7 332 assert_param(IS_FMC_NORSRAM_DEVICE(Device));
<> 144:ef7eb2e8f9f7 333 assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime));
<> 144:ef7eb2e8f9f7 334 assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));
<> 144:ef7eb2e8f9f7 335 assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime));
<> 144:ef7eb2e8f9f7 336 assert_param(IS_FMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration));
<> 144:ef7eb2e8f9f7 337 assert_param(IS_FMC_CLK_DIV(Timing->CLKDivision));
<> 144:ef7eb2e8f9f7 338 assert_param(IS_FMC_DATA_LATENCY(Timing->DataLatency));
<> 144:ef7eb2e8f9f7 339 assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode));
<> 144:ef7eb2e8f9f7 340 assert_param(IS_FMC_NORSRAM_BANK(Bank));
<> 157:ff67d9f36b67 341
<> 157:ff67d9f36b67 342 /* Set FMC_NORSRAM device timing parameters */
<> 157:ff67d9f36b67 343 MODIFY_REG(Device->BTCR[Bank + 1], \
<> 157:ff67d9f36b67 344 BTR_CLEAR_MASK, \
<> 157:ff67d9f36b67 345 (uint32_t)(Timing->AddressSetupTime | \
<> 157:ff67d9f36b67 346 ((Timing->AddressHoldTime) << POSITION_VAL(FMC_BTRx_ADDHLD)) | \
<> 157:ff67d9f36b67 347 ((Timing->DataSetupTime) << POSITION_VAL(FMC_BTRx_DATAST)) | \
<> 157:ff67d9f36b67 348 ((Timing->BusTurnAroundDuration) << POSITION_VAL(FMC_BTRx_BUSTURN)) | \
<> 157:ff67d9f36b67 349 (((Timing->CLKDivision) - 1) << POSITION_VAL(FMC_BTRx_CLKDIV)) | \
<> 157:ff67d9f36b67 350 (((Timing->DataLatency) - 2) << POSITION_VAL(FMC_BTRx_DATLAT)) | \
<> 157:ff67d9f36b67 351 (Timing->AccessMode)));
<> 157:ff67d9f36b67 352
<> 144:ef7eb2e8f9f7 353 /* Configure Clock division value (in NORSRAM bank 1) when continuous clock is enabled */
<> 157:ff67d9f36b67 354 if (HAL_IS_BIT_SET(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN))
<> 144:ef7eb2e8f9f7 355 {
<> 157:ff67d9f36b67 356 tmpr = (uint32_t)(Device->BTCR[FMC_NORSRAM_BANK1 + 1] & ~(((uint32_t)0x0F) << POSITION_VAL(FMC_BTRx_CLKDIV)));
<> 157:ff67d9f36b67 357 tmpr |= (uint32_t)(((Timing->CLKDivision) - 1) << POSITION_VAL(FMC_BTRx_CLKDIV));
<> 157:ff67d9f36b67 358 MODIFY_REG(Device->BTCR[FMC_NORSRAM_BANK1 + 1], FMC_BTRx_CLKDIV, tmpr);
<> 157:ff67d9f36b67 359 }
<> 157:ff67d9f36b67 360
<> 157:ff67d9f36b67 361 return HAL_OK;
<> 144:ef7eb2e8f9f7 362 }
<> 144:ef7eb2e8f9f7 363
<> 144:ef7eb2e8f9f7 364 /**
<> 144:ef7eb2e8f9f7 365 * @brief Initialize the FMC_NORSRAM Extended mode Timing according to the specified
<> 144:ef7eb2e8f9f7 366 * parameters in the FMC_NORSRAM_TimingTypeDef
<> 157:ff67d9f36b67 367 * @param Device Pointer to NORSRAM device instance
<> 157:ff67d9f36b67 368 * @param Timing Pointer to NORSRAM Timing structure
<> 157:ff67d9f36b67 369 * @param Bank NORSRAM bank number
<> 157:ff67d9f36b67 370 * @param ExtendedMode FMC Extended Mode
<> 157:ff67d9f36b67 371 * This parameter can be one of the following values:
<> 157:ff67d9f36b67 372 * @arg FMC_EXTENDED_MODE_DISABLE
<> 157:ff67d9f36b67 373 * @arg FMC_EXTENDED_MODE_ENABLE
<> 144:ef7eb2e8f9f7 374 * @retval HAL status
<> 144:ef7eb2e8f9f7 375 */
<> 144:ef7eb2e8f9f7 376 HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode)
<> 157:ff67d9f36b67 377 {
<> 144:ef7eb2e8f9f7 378 /* Check the parameters */
<> 144:ef7eb2e8f9f7 379 assert_param(IS_FMC_EXTENDED_MODE(ExtendedMode));
<> 157:ff67d9f36b67 380
<> 144:ef7eb2e8f9f7 381 /* Set NORSRAM device timing register for write configuration, if extended mode is used */
<> 157:ff67d9f36b67 382 if (ExtendedMode == FMC_EXTENDED_MODE_ENABLE)
<> 144:ef7eb2e8f9f7 383 {
<> 157:ff67d9f36b67 384 /* Check the parameters */
<> 157:ff67d9f36b67 385 assert_param(IS_FMC_NORSRAM_EXTENDED_DEVICE(Device));
<> 144:ef7eb2e8f9f7 386 assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime));
<> 144:ef7eb2e8f9f7 387 assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));
<> 144:ef7eb2e8f9f7 388 assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime));
<> 144:ef7eb2e8f9f7 389 assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode));
<> 157:ff67d9f36b67 390 assert_param(IS_FMC_NORSRAM_BANK(Bank));
<> 157:ff67d9f36b67 391
<> 157:ff67d9f36b67 392 /* Set NORSRAM device timing register for write configuration, if extended mode is used */
<> 157:ff67d9f36b67 393 MODIFY_REG(Device->BWTR[Bank], \
<> 157:ff67d9f36b67 394 BWTR_CLEAR_MASK, \
<> 157:ff67d9f36b67 395 (uint32_t)(Timing->AddressSetupTime | \
<> 157:ff67d9f36b67 396 ((Timing->AddressHoldTime) << POSITION_VAL(FMC_BWTRx_ADDHLD)) | \
<> 157:ff67d9f36b67 397 ((Timing->DataSetupTime) << POSITION_VAL(FMC_BWTRx_DATAST)) | \
<> 157:ff67d9f36b67 398 (Timing->AccessMode)));
<> 144:ef7eb2e8f9f7 399 }
<> 157:ff67d9f36b67 400 else
<> 144:ef7eb2e8f9f7 401 {
<> 144:ef7eb2e8f9f7 402 Device->BWTR[Bank] = 0x0FFFFFFF;
<> 157:ff67d9f36b67 403 }
<> 157:ff67d9f36b67 404
<> 157:ff67d9f36b67 405 return HAL_OK;
<> 144:ef7eb2e8f9f7 406 }
<> 144:ef7eb2e8f9f7 407
<> 144:ef7eb2e8f9f7 408
<> 144:ef7eb2e8f9f7 409 /**
<> 144:ef7eb2e8f9f7 410 * @}
<> 144:ef7eb2e8f9f7 411 */
<> 157:ff67d9f36b67 412
<> 157:ff67d9f36b67 413
<> 157:ff67d9f36b67 414 /** @defgroup FMC_NORSRAM_Group2 Control functions
<> 157:ff67d9f36b67 415 * @brief management functions
<> 144:ef7eb2e8f9f7 416 *
<> 157:ff67d9f36b67 417 @verbatim
<> 144:ef7eb2e8f9f7 418 ==============================================================================
<> 144:ef7eb2e8f9f7 419 ##### FMC_NORSRAM Control functions #####
<> 157:ff67d9f36b67 420 ==============================================================================
<> 144:ef7eb2e8f9f7 421 [..]
<> 144:ef7eb2e8f9f7 422 This subsection provides a set of functions allowing to control dynamically
<> 144:ef7eb2e8f9f7 423 the FMC NORSRAM interface.
<> 144:ef7eb2e8f9f7 424
<> 144:ef7eb2e8f9f7 425 @endverbatim
<> 144:ef7eb2e8f9f7 426 * @{
<> 144:ef7eb2e8f9f7 427 */
<> 157:ff67d9f36b67 428
<> 144:ef7eb2e8f9f7 429 /**
<> 144:ef7eb2e8f9f7 430 * @brief Enables dynamically FMC_NORSRAM write operation.
<> 157:ff67d9f36b67 431 * @param Device Pointer to NORSRAM device instance
<> 157:ff67d9f36b67 432 * @param Bank NORSRAM bank number
<> 144:ef7eb2e8f9f7 433 * @retval HAL status
<> 144:ef7eb2e8f9f7 434 */
<> 144:ef7eb2e8f9f7 435 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank)
<> 144:ef7eb2e8f9f7 436 {
<> 144:ef7eb2e8f9f7 437 /* Check the parameters */
<> 144:ef7eb2e8f9f7 438 assert_param(IS_FMC_NORSRAM_DEVICE(Device));
<> 144:ef7eb2e8f9f7 439 assert_param(IS_FMC_NORSRAM_BANK(Bank));
<> 157:ff67d9f36b67 440
<> 144:ef7eb2e8f9f7 441 /* Enable write operation */
<> 157:ff67d9f36b67 442 SET_BIT(Device->BTCR[Bank], FMC_WRITE_OPERATION_ENABLE);
<> 144:ef7eb2e8f9f7 443
<> 157:ff67d9f36b67 444 return HAL_OK;
<> 144:ef7eb2e8f9f7 445 }
<> 144:ef7eb2e8f9f7 446
<> 144:ef7eb2e8f9f7 447 /**
<> 144:ef7eb2e8f9f7 448 * @brief Disables dynamically FMC_NORSRAM write operation.
<> 157:ff67d9f36b67 449 * @param Device Pointer to NORSRAM device instance
<> 157:ff67d9f36b67 450 * @param Bank NORSRAM bank number
<> 144:ef7eb2e8f9f7 451 * @retval HAL status
<> 144:ef7eb2e8f9f7 452 */
<> 144:ef7eb2e8f9f7 453 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank)
<> 157:ff67d9f36b67 454 {
<> 144:ef7eb2e8f9f7 455 /* Check the parameters */
<> 144:ef7eb2e8f9f7 456 assert_param(IS_FMC_NORSRAM_DEVICE(Device));
<> 144:ef7eb2e8f9f7 457 assert_param(IS_FMC_NORSRAM_BANK(Bank));
<> 157:ff67d9f36b67 458
<> 144:ef7eb2e8f9f7 459 /* Disable write operation */
<> 157:ff67d9f36b67 460 CLEAR_BIT(Device->BTCR[Bank], FMC_WRITE_OPERATION_ENABLE);
<> 144:ef7eb2e8f9f7 461
<> 157:ff67d9f36b67 462 return HAL_OK;
<> 144:ef7eb2e8f9f7 463 }
<> 144:ef7eb2e8f9f7 464
<> 144:ef7eb2e8f9f7 465 /**
<> 144:ef7eb2e8f9f7 466 * @}
<> 144:ef7eb2e8f9f7 467 */
<> 144:ef7eb2e8f9f7 468
<> 144:ef7eb2e8f9f7 469 /**
<> 144:ef7eb2e8f9f7 470 * @}
<> 144:ef7eb2e8f9f7 471 */
<> 157:ff67d9f36b67 472 /** @defgroup FMC_NAND FMC NAND Controller functions
<> 157:ff67d9f36b67 473 * @brief NAND Controller functions
<> 144:ef7eb2e8f9f7 474 *
<> 157:ff67d9f36b67 475 @verbatim
<> 144:ef7eb2e8f9f7 476 ==============================================================================
<> 144:ef7eb2e8f9f7 477 ##### How to use NAND device driver #####
<> 144:ef7eb2e8f9f7 478 ==============================================================================
<> 144:ef7eb2e8f9f7 479 [..]
<> 144:ef7eb2e8f9f7 480 This driver contains a set of APIs to interface with the FMC NAND banks in order
<> 144:ef7eb2e8f9f7 481 to run the NAND external devices.
<> 157:ff67d9f36b67 482
<> 157:ff67d9f36b67 483 (+) FMC NAND bank reset using the function FMC_NAND_DeInit()
<> 144:ef7eb2e8f9f7 484 (+) FMC NAND bank control configuration using the function FMC_NAND_Init()
<> 157:ff67d9f36b67 485 (+) FMC NAND bank common space timing configuration using the function
<> 144:ef7eb2e8f9f7 486 FMC_NAND_CommonSpace_Timing_Init()
<> 157:ff67d9f36b67 487 (+) FMC NAND bank attribute space timing configuration using the function
<> 144:ef7eb2e8f9f7 488 FMC_NAND_AttributeSpace_Timing_Init()
<> 144:ef7eb2e8f9f7 489 (+) FMC NAND bank enable/disable ECC correction feature using the functions
<> 144:ef7eb2e8f9f7 490 FMC_NAND_ECC_Enable()/FMC_NAND_ECC_Disable()
<> 157:ff67d9f36b67 491 (+) FMC NAND bank get ECC correction code using the function FMC_NAND_GetECC()
<> 144:ef7eb2e8f9f7 492
<> 144:ef7eb2e8f9f7 493 @endverbatim
<> 144:ef7eb2e8f9f7 494 * @{
<> 144:ef7eb2e8f9f7 495 */
<> 157:ff67d9f36b67 496
<> 144:ef7eb2e8f9f7 497 /** @defgroup FMC_NAND_Exported_Functions_Group1 Initialization and de-initialization functions
<> 157:ff67d9f36b67 498 * @brief Initialization and Configuration functions
<> 144:ef7eb2e8f9f7 499 *
<> 157:ff67d9f36b67 500 @verbatim
<> 144:ef7eb2e8f9f7 501 ==============================================================================
<> 144:ef7eb2e8f9f7 502 ##### Initialization and de_initialization functions #####
<> 144:ef7eb2e8f9f7 503 ==============================================================================
<> 157:ff67d9f36b67 504 [..]
<> 144:ef7eb2e8f9f7 505 This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 506 (+) Initialize and configure the FMC NAND interface
<> 157:ff67d9f36b67 507 (+) De-initialize the FMC NAND interface
<> 144:ef7eb2e8f9f7 508 (+) Configure the FMC clock and associated GPIOs
<> 157:ff67d9f36b67 509
<> 144:ef7eb2e8f9f7 510 @endverbatim
<> 144:ef7eb2e8f9f7 511 * @{
<> 144:ef7eb2e8f9f7 512 */
<> 157:ff67d9f36b67 513
<> 144:ef7eb2e8f9f7 514 /**
<> 144:ef7eb2e8f9f7 515 * @brief Initializes the FMC_NAND device according to the specified
<> 144:ef7eb2e8f9f7 516 * control parameters in the FMC_NAND_HandleTypeDef
<> 157:ff67d9f36b67 517 * @param Device Pointer to NAND device instance
<> 157:ff67d9f36b67 518 * @param Init Pointer to NAND Initialization structure
<> 144:ef7eb2e8f9f7 519 * @retval HAL status
<> 144:ef7eb2e8f9f7 520 */
<> 144:ef7eb2e8f9f7 521 HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init)
<> 144:ef7eb2e8f9f7 522 {
<> 144:ef7eb2e8f9f7 523 /* Check the parameters */
<> 144:ef7eb2e8f9f7 524 assert_param(IS_FMC_NAND_DEVICE(Device));
<> 144:ef7eb2e8f9f7 525 assert_param(IS_FMC_NAND_BANK(Init->NandBank));
<> 144:ef7eb2e8f9f7 526 assert_param(IS_FMC_WAIT_FEATURE(Init->Waitfeature));
<> 144:ef7eb2e8f9f7 527 assert_param(IS_FMC_NAND_MEMORY_WIDTH(Init->MemoryDataWidth));
<> 144:ef7eb2e8f9f7 528 assert_param(IS_FMC_ECC_STATE(Init->EccComputation));
<> 144:ef7eb2e8f9f7 529 assert_param(IS_FMC_ECCPAGE_SIZE(Init->ECCPageSize));
<> 144:ef7eb2e8f9f7 530 assert_param(IS_FMC_TCLR_TIME(Init->TCLRSetupTime));
<> 157:ff67d9f36b67 531 assert_param(IS_FMC_TAR_TIME(Init->TARSetupTime));
<> 144:ef7eb2e8f9f7 532
<> 144:ef7eb2e8f9f7 533 /* Set NAND device control parameters */
<> 157:ff67d9f36b67 534 if (Init->NandBank == FMC_NAND_BANK2)
<> 144:ef7eb2e8f9f7 535 {
<> 144:ef7eb2e8f9f7 536 /* NAND bank 2 registers configuration */
<> 157:ff67d9f36b67 537 MODIFY_REG(Device->PCR2, PCR_CLEAR_MASK, (Init->Waitfeature |
<> 157:ff67d9f36b67 538 FMC_PCR_MEMORY_TYPE_NAND |
<> 157:ff67d9f36b67 539 Init->MemoryDataWidth |
<> 157:ff67d9f36b67 540 Init->EccComputation |
<> 157:ff67d9f36b67 541 Init->ECCPageSize |
<> 157:ff67d9f36b67 542 ((Init->TCLRSetupTime) << POSITION_VAL(FMC_PCRx_TCLR)) |
<> 157:ff67d9f36b67 543 ((Init->TARSetupTime) << POSITION_VAL(FMC_PCRx_TAR))));
<> 144:ef7eb2e8f9f7 544 }
<> 144:ef7eb2e8f9f7 545 else
<> 144:ef7eb2e8f9f7 546 {
<> 144:ef7eb2e8f9f7 547 /* NAND bank 3 registers configuration */
<> 157:ff67d9f36b67 548 MODIFY_REG(Device->PCR3, PCR_CLEAR_MASK, (Init->Waitfeature |
<> 157:ff67d9f36b67 549 FMC_PCR_MEMORY_TYPE_NAND |
<> 157:ff67d9f36b67 550 Init->MemoryDataWidth |
<> 157:ff67d9f36b67 551 Init->EccComputation |
<> 157:ff67d9f36b67 552 Init->ECCPageSize |
<> 157:ff67d9f36b67 553 ((Init->TCLRSetupTime) << POSITION_VAL(FMC_PCRx_TCLR)) |
<> 157:ff67d9f36b67 554 ((Init->TARSetupTime) << POSITION_VAL(FMC_PCRx_TAR))));
<> 144:ef7eb2e8f9f7 555 }
<> 157:ff67d9f36b67 556
<> 144:ef7eb2e8f9f7 557 return HAL_OK;
<> 144:ef7eb2e8f9f7 558
<> 144:ef7eb2e8f9f7 559 }
<> 144:ef7eb2e8f9f7 560
<> 144:ef7eb2e8f9f7 561 /**
<> 144:ef7eb2e8f9f7 562 * @brief Initializes the FMC_NAND Common space Timing according to the specified
<> 144:ef7eb2e8f9f7 563 * parameters in the FMC_NAND_PCC_TimingTypeDef
<> 157:ff67d9f36b67 564 * @param Device Pointer to NAND device instance
<> 157:ff67d9f36b67 565 * @param Timing Pointer to NAND timing structure
<> 157:ff67d9f36b67 566 * @param Bank NAND bank number
<> 144:ef7eb2e8f9f7 567 * @retval HAL status
<> 144:ef7eb2e8f9f7 568 */
<> 144:ef7eb2e8f9f7 569 HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
<> 144:ef7eb2e8f9f7 570 {
<> 157:ff67d9f36b67 571 /* Check the parameters */
<> 157:ff67d9f36b67 572 assert_param(IS_FMC_NAND_DEVICE(Device));
<> 157:ff67d9f36b67 573 assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
<> 157:ff67d9f36b67 574 assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
<> 157:ff67d9f36b67 575 assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
<> 157:ff67d9f36b67 576 assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
<> 157:ff67d9f36b67 577 assert_param(IS_FMC_NAND_BANK(Bank));
<> 157:ff67d9f36b67 578
<> 157:ff67d9f36b67 579 /* Set FMC_NAND device timing parameters */
<> 157:ff67d9f36b67 580 if (Bank == FMC_NAND_BANK2)
<> 157:ff67d9f36b67 581 {
<> 157:ff67d9f36b67 582 /* NAND bank 2 registers configuration */
<> 157:ff67d9f36b67 583 MODIFY_REG(Device->PMEM2, PMEM_CLEAR_MASK, (Timing->SetupTime | \
<> 157:ff67d9f36b67 584 ((Timing->WaitSetupTime) << POSITION_VAL(FMC_PMEMx_MEMWAITx)) | \
<> 157:ff67d9f36b67 585 ((Timing->HoldSetupTime) << POSITION_VAL(FMC_PMEMx_MEMHOLDx)) | \
<> 157:ff67d9f36b67 586 ((Timing->HiZSetupTime) << POSITION_VAL(FMC_PMEMx_MEMHIZx))));
<> 157:ff67d9f36b67 587 }
<> 157:ff67d9f36b67 588 else
<> 157:ff67d9f36b67 589 {
<> 157:ff67d9f36b67 590 /* NAND bank 3 registers configuration */
<> 157:ff67d9f36b67 591 MODIFY_REG(Device->PMEM3, PMEM_CLEAR_MASK, (Timing->SetupTime | \
<> 157:ff67d9f36b67 592 ((Timing->WaitSetupTime) << POSITION_VAL(FMC_PMEMx_MEMWAITx)) | \
<> 157:ff67d9f36b67 593 ((Timing->HoldSetupTime) << POSITION_VAL(FMC_PMEMx_MEMHOLDx)) | \
<> 157:ff67d9f36b67 594 ((Timing->HiZSetupTime) << POSITION_VAL(FMC_PMEMx_MEMHIZx))));
<> 157:ff67d9f36b67 595 }
<> 157:ff67d9f36b67 596
<> 157:ff67d9f36b67 597 return HAL_OK;
<> 157:ff67d9f36b67 598 }
<> 157:ff67d9f36b67 599
<> 157:ff67d9f36b67 600 /**
<> 157:ff67d9f36b67 601 * @brief Initializes the FMC_NAND Attribute space Timing according to the specified
<> 157:ff67d9f36b67 602 * parameters in the FMC_NAND_PCC_TimingTypeDef
<> 157:ff67d9f36b67 603 * @param Device Pointer to NAND device instance
<> 157:ff67d9f36b67 604 * @param Timing Pointer to NAND timing structure
<> 157:ff67d9f36b67 605 * @param Bank NAND bank number
<> 157:ff67d9f36b67 606 * @retval HAL status
<> 157:ff67d9f36b67 607 */
<> 157:ff67d9f36b67 608 HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
<> 157:ff67d9f36b67 609 {
<> 144:ef7eb2e8f9f7 610 /* Check the parameters */
<> 144:ef7eb2e8f9f7 611 assert_param(IS_FMC_NAND_DEVICE(Device));
<> 144:ef7eb2e8f9f7 612 assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
<> 144:ef7eb2e8f9f7 613 assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
<> 144:ef7eb2e8f9f7 614 assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
<> 144:ef7eb2e8f9f7 615 assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
<> 144:ef7eb2e8f9f7 616 assert_param(IS_FMC_NAND_BANK(Bank));
<> 157:ff67d9f36b67 617
<> 144:ef7eb2e8f9f7 618 /* Set FMC_NAND device timing parameters */
<> 157:ff67d9f36b67 619 if (Bank == FMC_NAND_BANK2)
<> 144:ef7eb2e8f9f7 620 {
<> 144:ef7eb2e8f9f7 621 /* NAND bank 2 registers configuration */
<> 157:ff67d9f36b67 622 MODIFY_REG(Device->PATT2, PATT_CLEAR_MASK, (Timing->SetupTime | \
<> 157:ff67d9f36b67 623 ((Timing->WaitSetupTime) << POSITION_VAL(FMC_PATTx_ATTWAITx)) | \
<> 157:ff67d9f36b67 624 ((Timing->HoldSetupTime) << POSITION_VAL(FMC_PATTx_ATTHOLDx)) | \
<> 157:ff67d9f36b67 625 ((Timing->HiZSetupTime) << POSITION_VAL(FMC_PATTx_ATTHIZx))));
<> 144:ef7eb2e8f9f7 626 }
<> 144:ef7eb2e8f9f7 627 else
<> 144:ef7eb2e8f9f7 628 {
<> 144:ef7eb2e8f9f7 629 /* NAND bank 3 registers configuration */
<> 157:ff67d9f36b67 630 MODIFY_REG(Device->PATT3, PATT_CLEAR_MASK, (Timing->SetupTime | \
<> 157:ff67d9f36b67 631 ((Timing->WaitSetupTime) << POSITION_VAL(FMC_PATTx_ATTWAITx)) | \
<> 157:ff67d9f36b67 632 ((Timing->HoldSetupTime) << POSITION_VAL(FMC_PATTx_ATTHOLDx)) | \
<> 157:ff67d9f36b67 633 ((Timing->HiZSetupTime) << POSITION_VAL(FMC_PATTx_ATTHIZx))));
<> 157:ff67d9f36b67 634 }
<> 144:ef7eb2e8f9f7 635
<> 144:ef7eb2e8f9f7 636 return HAL_OK;
<> 144:ef7eb2e8f9f7 637 }
<> 144:ef7eb2e8f9f7 638
<> 144:ef7eb2e8f9f7 639
<> 144:ef7eb2e8f9f7 640 /**
<> 157:ff67d9f36b67 641 * @brief DeInitialize the FMC_NAND device
<> 157:ff67d9f36b67 642 * @param Device Pointer to NAND device instance
<> 157:ff67d9f36b67 643 * @param Bank NAND bank number
<> 144:ef7eb2e8f9f7 644 * @retval HAL status
<> 144:ef7eb2e8f9f7 645 */
<> 144:ef7eb2e8f9f7 646 HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank)
<> 144:ef7eb2e8f9f7 647 {
<> 157:ff67d9f36b67 648 /* Check the parameters */
<> 157:ff67d9f36b67 649 assert_param(IS_FMC_NAND_DEVICE(Device));
<> 144:ef7eb2e8f9f7 650 assert_param(IS_FMC_NAND_BANK(Bank));
<> 157:ff67d9f36b67 651
<> 144:ef7eb2e8f9f7 652 /* Disable the NAND Bank */
<> 144:ef7eb2e8f9f7 653 __FMC_NAND_DISABLE(Device, Bank);
<> 157:ff67d9f36b67 654
<> 144:ef7eb2e8f9f7 655 /* De-initialize the NAND Bank */
<> 157:ff67d9f36b67 656 if (Bank == FMC_NAND_BANK2)
<> 144:ef7eb2e8f9f7 657 {
<> 144:ef7eb2e8f9f7 658 /* Set the FMC_NAND_BANK2 registers to their reset values */
<> 157:ff67d9f36b67 659 WRITE_REG(Device->PCR2, 0x00000018);
<> 157:ff67d9f36b67 660 WRITE_REG(Device->SR2, 0x00000040);
<> 157:ff67d9f36b67 661 WRITE_REG(Device->PMEM2, 0xFCFCFCFC);
<> 157:ff67d9f36b67 662 WRITE_REG(Device->PATT2, 0xFCFCFCFC);
<> 144:ef7eb2e8f9f7 663 }
<> 157:ff67d9f36b67 664 /* FMC_Bank3_NAND */
<> 144:ef7eb2e8f9f7 665 else
<> 144:ef7eb2e8f9f7 666 {
<> 144:ef7eb2e8f9f7 667 /* Set the FMC_NAND_BANK3 registers to their reset values */
<> 157:ff67d9f36b67 668 WRITE_REG(Device->PCR3, 0x00000018);
<> 157:ff67d9f36b67 669 WRITE_REG(Device->SR3, 0x00000040);
<> 157:ff67d9f36b67 670 WRITE_REG(Device->PMEM3, 0xFCFCFCFC);
<> 157:ff67d9f36b67 671 WRITE_REG(Device->PATT3, 0xFCFCFCFC);
<> 144:ef7eb2e8f9f7 672 }
<> 157:ff67d9f36b67 673
<> 144:ef7eb2e8f9f7 674 return HAL_OK;
<> 144:ef7eb2e8f9f7 675 }
<> 144:ef7eb2e8f9f7 676
<> 144:ef7eb2e8f9f7 677 /**
<> 144:ef7eb2e8f9f7 678 * @}
<> 144:ef7eb2e8f9f7 679 */
<> 157:ff67d9f36b67 680
<> 157:ff67d9f36b67 681
<> 157:ff67d9f36b67 682 /** @defgroup FMC_NAND_Exported_Functions_Group2 Peripheral Control functions
<> 157:ff67d9f36b67 683 * @brief management functions
<> 144:ef7eb2e8f9f7 684 *
<> 157:ff67d9f36b67 685 @verbatim
<> 144:ef7eb2e8f9f7 686 ==============================================================================
<> 144:ef7eb2e8f9f7 687 ##### FMC_NAND Control functions #####
<> 157:ff67d9f36b67 688 ==============================================================================
<> 144:ef7eb2e8f9f7 689 [..]
<> 144:ef7eb2e8f9f7 690 This subsection provides a set of functions allowing to control dynamically
<> 144:ef7eb2e8f9f7 691 the FMC NAND interface.
<> 144:ef7eb2e8f9f7 692
<> 144:ef7eb2e8f9f7 693 @endverbatim
<> 144:ef7eb2e8f9f7 694 * @{
<> 157:ff67d9f36b67 695 */
<> 144:ef7eb2e8f9f7 696
<> 157:ff67d9f36b67 697
<> 144:ef7eb2e8f9f7 698 /**
<> 144:ef7eb2e8f9f7 699 * @brief Enables dynamically FMC_NAND ECC feature.
<> 157:ff67d9f36b67 700 * @param Device Pointer to NAND device instance
<> 157:ff67d9f36b67 701 * @param Bank NAND bank number
<> 144:ef7eb2e8f9f7 702 * @retval HAL status
<> 157:ff67d9f36b67 703 */
<> 144:ef7eb2e8f9f7 704 HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank)
<> 144:ef7eb2e8f9f7 705 {
<> 157:ff67d9f36b67 706 /* Check the parameters */
<> 157:ff67d9f36b67 707 assert_param(IS_FMC_NAND_DEVICE(Device));
<> 144:ef7eb2e8f9f7 708 assert_param(IS_FMC_NAND_BANK(Bank));
<> 157:ff67d9f36b67 709
<> 144:ef7eb2e8f9f7 710 /* Enable ECC feature */
<> 157:ff67d9f36b67 711 if (Bank == FMC_NAND_BANK2)
<> 144:ef7eb2e8f9f7 712 {
<> 157:ff67d9f36b67 713 SET_BIT(Device->PCR2, FMC_PCRx_ECCEN);
<> 144:ef7eb2e8f9f7 714 }
<> 144:ef7eb2e8f9f7 715 else
<> 144:ef7eb2e8f9f7 716 {
<> 157:ff67d9f36b67 717 SET_BIT(Device->PCR3, FMC_PCRx_ECCEN);
<> 157:ff67d9f36b67 718 }
<> 157:ff67d9f36b67 719
<> 157:ff67d9f36b67 720 return HAL_OK;
<> 144:ef7eb2e8f9f7 721 }
<> 144:ef7eb2e8f9f7 722
<> 144:ef7eb2e8f9f7 723
<> 144:ef7eb2e8f9f7 724 /**
<> 144:ef7eb2e8f9f7 725 * @brief Disables dynamically FMC_NAND ECC feature.
<> 157:ff67d9f36b67 726 * @param Device Pointer to NAND device instance
<> 157:ff67d9f36b67 727 * @param Bank NAND bank number
<> 144:ef7eb2e8f9f7 728 * @retval HAL status
<> 157:ff67d9f36b67 729 */
<> 157:ff67d9f36b67 730 HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank)
<> 157:ff67d9f36b67 731 {
<> 157:ff67d9f36b67 732 /* Check the parameters */
<> 157:ff67d9f36b67 733 assert_param(IS_FMC_NAND_DEVICE(Device));
<> 144:ef7eb2e8f9f7 734 assert_param(IS_FMC_NAND_BANK(Bank));
<> 157:ff67d9f36b67 735
<> 144:ef7eb2e8f9f7 736 /* Disable ECC feature */
<> 157:ff67d9f36b67 737 if (Bank == FMC_NAND_BANK2)
<> 144:ef7eb2e8f9f7 738 {
<> 157:ff67d9f36b67 739 CLEAR_BIT(Device->PCR2, FMC_PCRx_ECCEN);
<> 144:ef7eb2e8f9f7 740 }
<> 144:ef7eb2e8f9f7 741 else
<> 144:ef7eb2e8f9f7 742 {
<> 157:ff67d9f36b67 743 CLEAR_BIT(Device->PCR3, FMC_PCRx_ECCEN);
<> 157:ff67d9f36b67 744 }
<> 144:ef7eb2e8f9f7 745
<> 157:ff67d9f36b67 746 return HAL_OK;
<> 144:ef7eb2e8f9f7 747 }
<> 144:ef7eb2e8f9f7 748
<> 144:ef7eb2e8f9f7 749 /**
<> 144:ef7eb2e8f9f7 750 * @brief Disables dynamically FMC_NAND ECC feature.
<> 157:ff67d9f36b67 751 * @param Device Pointer to NAND device instance
<> 157:ff67d9f36b67 752 * @param ECCval Pointer to ECC value
<> 157:ff67d9f36b67 753 * @param Bank NAND bank number
<> 157:ff67d9f36b67 754 * @param Timeout Timeout wait value
<> 144:ef7eb2e8f9f7 755 * @retval HAL status
<> 144:ef7eb2e8f9f7 756 */
<> 144:ef7eb2e8f9f7 757 HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout)
<> 144:ef7eb2e8f9f7 758 {
<> 157:ff67d9f36b67 759 uint32_t tickstart = 0;
<> 144:ef7eb2e8f9f7 760
<> 157:ff67d9f36b67 761 /* Check the parameters */
<> 157:ff67d9f36b67 762 assert_param(IS_FMC_NAND_DEVICE(Device));
<> 144:ef7eb2e8f9f7 763 assert_param(IS_FMC_NAND_BANK(Bank));
<> 157:ff67d9f36b67 764
<> 157:ff67d9f36b67 765 /* Get tick */
<> 157:ff67d9f36b67 766 tickstart = HAL_GetTick();
<> 157:ff67d9f36b67 767
<> 157:ff67d9f36b67 768 /* Wait until FIFO is empty */
<> 157:ff67d9f36b67 769 while (__FMC_NAND_GET_FLAG(Device, Bank, FMC_FLAG_FEMPT) == RESET)
<> 144:ef7eb2e8f9f7 770 {
<> 144:ef7eb2e8f9f7 771 /* Check for the Timeout */
<> 157:ff67d9f36b67 772 if (Timeout != HAL_MAX_DELAY)
<> 144:ef7eb2e8f9f7 773 {
<> 157:ff67d9f36b67 774 if ((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout))
<> 144:ef7eb2e8f9f7 775 {
<> 144:ef7eb2e8f9f7 776 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 777 }
<> 157:ff67d9f36b67 778 }
<> 144:ef7eb2e8f9f7 779 }
<> 157:ff67d9f36b67 780
<> 157:ff67d9f36b67 781 if (Bank == FMC_NAND_BANK2)
<> 157:ff67d9f36b67 782 {
<> 144:ef7eb2e8f9f7 783 /* Get the ECCR2 register value */
<> 144:ef7eb2e8f9f7 784 *ECCval = (uint32_t)Device->ECCR2;
<> 144:ef7eb2e8f9f7 785 }
<> 144:ef7eb2e8f9f7 786 else
<> 157:ff67d9f36b67 787 {
<> 144:ef7eb2e8f9f7 788 /* Get the ECCR3 register value */
<> 144:ef7eb2e8f9f7 789 *ECCval = (uint32_t)Device->ECCR3;
<> 144:ef7eb2e8f9f7 790 }
<> 144:ef7eb2e8f9f7 791
<> 157:ff67d9f36b67 792 return HAL_OK;
<> 144:ef7eb2e8f9f7 793 }
<> 144:ef7eb2e8f9f7 794
<> 144:ef7eb2e8f9f7 795 /**
<> 144:ef7eb2e8f9f7 796 * @}
<> 144:ef7eb2e8f9f7 797 */
<> 157:ff67d9f36b67 798
<> 144:ef7eb2e8f9f7 799 /**
<> 144:ef7eb2e8f9f7 800 * @}
<> 144:ef7eb2e8f9f7 801 */
<> 157:ff67d9f36b67 802
<> 157:ff67d9f36b67 803 /** @defgroup FMC_PCCARD FMC PCCARD Controller functions
<> 157:ff67d9f36b67 804 * @brief PCCARD Controller functions
<> 144:ef7eb2e8f9f7 805 *
<> 157:ff67d9f36b67 806 @verbatim
<> 157:ff67d9f36b67 807 ==============================================================================
<> 144:ef7eb2e8f9f7 808 ##### How to use PCCARD device driver #####
<> 144:ef7eb2e8f9f7 809 ==============================================================================
<> 144:ef7eb2e8f9f7 810 [..]
<> 144:ef7eb2e8f9f7 811 This driver contains a set of APIs to interface with the FMC PCCARD bank in order
<> 144:ef7eb2e8f9f7 812 to run the PCCARD/compact flash external devices.
<> 157:ff67d9f36b67 813
<> 157:ff67d9f36b67 814 (+) FMC PCCARD bank reset using the function FMC_PCCARD_DeInit()
<> 144:ef7eb2e8f9f7 815 (+) FMC PCCARD bank control configuration using the function FMC_PCCARD_Init()
<> 157:ff67d9f36b67 816 (+) FMC PCCARD bank common space timing configuration using the function
<> 144:ef7eb2e8f9f7 817 FMC_PCCARD_CommonSpace_Timing_Init()
<> 157:ff67d9f36b67 818 (+) FMC PCCARD bank attribute space timing configuration using the function
<> 144:ef7eb2e8f9f7 819 FMC_PCCARD_AttributeSpace_Timing_Init()
<> 157:ff67d9f36b67 820 (+) FMC PCCARD bank IO space timing configuration using the function
<> 144:ef7eb2e8f9f7 821 FMC_PCCARD_IOSpace_Timing_Init()
<> 144:ef7eb2e8f9f7 822
<> 157:ff67d9f36b67 823
<> 144:ef7eb2e8f9f7 824 @endverbatim
<> 144:ef7eb2e8f9f7 825 * @{
<> 144:ef7eb2e8f9f7 826 */
<> 157:ff67d9f36b67 827
<> 144:ef7eb2e8f9f7 828 /** @defgroup FMC_PCCARD_Exported_Functions_Group1 Initialization and de-initialization functions
<> 157:ff67d9f36b67 829 * @brief Initialization and Configuration functions
<> 144:ef7eb2e8f9f7 830 *
<> 157:ff67d9f36b67 831 @verbatim
<> 144:ef7eb2e8f9f7 832 ==============================================================================
<> 144:ef7eb2e8f9f7 833 ##### Initialization and de_initialization functions #####
<> 144:ef7eb2e8f9f7 834 ==============================================================================
<> 157:ff67d9f36b67 835 [..]
<> 144:ef7eb2e8f9f7 836 This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 837 (+) Initialize and configure the FMC PCCARD interface
<> 157:ff67d9f36b67 838 (+) De-initialize the FMC PCCARD interface
<> 144:ef7eb2e8f9f7 839 (+) Configure the FMC clock and associated GPIOs
<> 157:ff67d9f36b67 840
<> 144:ef7eb2e8f9f7 841 @endverbatim
<> 144:ef7eb2e8f9f7 842 * @{
<> 144:ef7eb2e8f9f7 843 */
<> 157:ff67d9f36b67 844
<> 144:ef7eb2e8f9f7 845 /**
<> 144:ef7eb2e8f9f7 846 * @brief Initializes the FMC_PCCARD device according to the specified
<> 144:ef7eb2e8f9f7 847 * control parameters in the FMC_PCCARD_HandleTypeDef
<> 157:ff67d9f36b67 848 * @param Device Pointer to PCCARD device instance
<> 157:ff67d9f36b67 849 * @param Init Pointer to PCCARD Initialization structure
<> 144:ef7eb2e8f9f7 850 * @retval HAL status
<> 144:ef7eb2e8f9f7 851 */
<> 144:ef7eb2e8f9f7 852 HAL_StatusTypeDef FMC_PCCARD_Init(FMC_PCCARD_TypeDef *Device, FMC_PCCARD_InitTypeDef *Init)
<> 144:ef7eb2e8f9f7 853 {
<> 157:ff67d9f36b67 854 /* Check the parameters */
<> 144:ef7eb2e8f9f7 855 assert_param(IS_FMC_PCCARD_DEVICE(Device));
<> 144:ef7eb2e8f9f7 856 assert_param(IS_FMC_WAIT_FEATURE(Init->Waitfeature));
<> 144:ef7eb2e8f9f7 857 assert_param(IS_FMC_TCLR_TIME(Init->TCLRSetupTime));
<> 157:ff67d9f36b67 858 assert_param(IS_FMC_TAR_TIME(Init->TARSetupTime));
<> 157:ff67d9f36b67 859
<> 144:ef7eb2e8f9f7 860 /* Set FMC_PCCARD device control parameters */
<> 157:ff67d9f36b67 861 MODIFY_REG(Device->PCR4,
<> 157:ff67d9f36b67 862 (FMC_PCRx_PTYP | FMC_PCRx_PWAITEN | FMC_PCRx_PWID |
<> 157:ff67d9f36b67 863 FMC_PCRx_TCLR | FMC_PCRx_TAR),
<> 157:ff67d9f36b67 864 (FMC_PCR_MEMORY_TYPE_PCCARD |
<> 157:ff67d9f36b67 865 Init->Waitfeature |
<> 157:ff67d9f36b67 866 FMC_NAND_PCC_MEM_BUS_WIDTH_16 |
<> 157:ff67d9f36b67 867 (Init->TCLRSetupTime << POSITION_VAL(FMC_PCRx_TCLR)) |
<> 157:ff67d9f36b67 868 (Init->TARSetupTime << POSITION_VAL(FMC_PCRx_TAR))));
<> 157:ff67d9f36b67 869
<> 144:ef7eb2e8f9f7 870 return HAL_OK;
<> 144:ef7eb2e8f9f7 871
<> 144:ef7eb2e8f9f7 872 }
<> 144:ef7eb2e8f9f7 873
<> 144:ef7eb2e8f9f7 874 /**
<> 144:ef7eb2e8f9f7 875 * @brief Initializes the FMC_PCCARD Common space Timing according to the specified
<> 144:ef7eb2e8f9f7 876 * parameters in the FMC_NAND_PCC_TimingTypeDef
<> 157:ff67d9f36b67 877 * @param Device Pointer to PCCARD device instance
<> 157:ff67d9f36b67 878 * @param Timing Pointer to PCCARD timing structure
<> 144:ef7eb2e8f9f7 879 * @retval HAL status
<> 144:ef7eb2e8f9f7 880 */
<> 144:ef7eb2e8f9f7 881 HAL_StatusTypeDef FMC_PCCARD_CommonSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing)
<> 144:ef7eb2e8f9f7 882 {
<> 144:ef7eb2e8f9f7 883 /* Check the parameters */
<> 144:ef7eb2e8f9f7 884 assert_param(IS_FMC_PCCARD_DEVICE(Device));
<> 144:ef7eb2e8f9f7 885 assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
<> 144:ef7eb2e8f9f7 886 assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
<> 144:ef7eb2e8f9f7 887 assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
<> 144:ef7eb2e8f9f7 888 assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
<> 144:ef7eb2e8f9f7 889
<> 144:ef7eb2e8f9f7 890 /* Set PCCARD timing parameters */
<> 157:ff67d9f36b67 891 MODIFY_REG(Device->PMEM4, PMEM_CLEAR_MASK,
<> 157:ff67d9f36b67 892 (Timing->SetupTime |
<> 157:ff67d9f36b67 893 ((Timing->WaitSetupTime) << POSITION_VAL(FMC_PMEMx_MEMWAITx)) |
<> 157:ff67d9f36b67 894 ((Timing->HoldSetupTime) << POSITION_VAL(FMC_PMEMx_MEMHOLDx)) |
<> 157:ff67d9f36b67 895 ((Timing->HiZSetupTime) << POSITION_VAL(FMC_PMEMx_MEMHIZx))));
<> 144:ef7eb2e8f9f7 896
<> 157:ff67d9f36b67 897 return HAL_OK;
<> 144:ef7eb2e8f9f7 898 }
<> 144:ef7eb2e8f9f7 899
<> 144:ef7eb2e8f9f7 900 /**
<> 144:ef7eb2e8f9f7 901 * @brief Initializes the FMC_PCCARD Attribute space Timing according to the specified
<> 144:ef7eb2e8f9f7 902 * parameters in the FMC_NAND_PCC_TimingTypeDef
<> 157:ff67d9f36b67 903 * @param Device Pointer to PCCARD device instance
<> 157:ff67d9f36b67 904 * @param Timing Pointer to PCCARD timing structure
<> 144:ef7eb2e8f9f7 905 * @retval HAL status
<> 144:ef7eb2e8f9f7 906 */
<> 144:ef7eb2e8f9f7 907 HAL_StatusTypeDef FMC_PCCARD_AttributeSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing)
<> 144:ef7eb2e8f9f7 908 {
<> 157:ff67d9f36b67 909 /* Check the parameters */
<> 157:ff67d9f36b67 910 assert_param(IS_FMC_PCCARD_DEVICE(Device));
<> 144:ef7eb2e8f9f7 911 assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
<> 144:ef7eb2e8f9f7 912 assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
<> 144:ef7eb2e8f9f7 913 assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
<> 144:ef7eb2e8f9f7 914 assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
<> 144:ef7eb2e8f9f7 915
<> 144:ef7eb2e8f9f7 916 /* Set PCCARD timing parameters */
<> 157:ff67d9f36b67 917 MODIFY_REG(Device->PATT4, PATT_CLEAR_MASK, \
<> 157:ff67d9f36b67 918 (Timing->SetupTime | \
<> 157:ff67d9f36b67 919 ((Timing->WaitSetupTime) << POSITION_VAL(FMC_PATTx_ATTWAITx)) | \
<> 157:ff67d9f36b67 920 ((Timing->HoldSetupTime) << POSITION_VAL(FMC_PATTx_ATTHOLDx)) | \
<> 157:ff67d9f36b67 921 ((Timing->HiZSetupTime) << POSITION_VAL(FMC_PATTx_ATTHIZx))));
<> 157:ff67d9f36b67 922
<> 144:ef7eb2e8f9f7 923 return HAL_OK;
<> 144:ef7eb2e8f9f7 924 }
<> 144:ef7eb2e8f9f7 925
<> 144:ef7eb2e8f9f7 926 /**
<> 144:ef7eb2e8f9f7 927 * @brief Initializes the FMC_PCCARD IO space Timing according to the specified
<> 144:ef7eb2e8f9f7 928 * parameters in the FMC_NAND_PCC_TimingTypeDef
<> 157:ff67d9f36b67 929 * @param Device Pointer to PCCARD device instance
<> 157:ff67d9f36b67 930 * @param Timing Pointer to PCCARD timing structure
<> 144:ef7eb2e8f9f7 931 * @retval HAL status
<> 144:ef7eb2e8f9f7 932 */
<> 144:ef7eb2e8f9f7 933 HAL_StatusTypeDef FMC_PCCARD_IOSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing)
<> 144:ef7eb2e8f9f7 934 {
<> 157:ff67d9f36b67 935 /* Check the parameters */
<> 144:ef7eb2e8f9f7 936 assert_param(IS_FMC_PCCARD_DEVICE(Device));
<> 144:ef7eb2e8f9f7 937 assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
<> 144:ef7eb2e8f9f7 938 assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
<> 144:ef7eb2e8f9f7 939 assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
<> 144:ef7eb2e8f9f7 940 assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
<> 144:ef7eb2e8f9f7 941
<> 144:ef7eb2e8f9f7 942 /* Set FMC_PCCARD device timing parameters */
<> 157:ff67d9f36b67 943 MODIFY_REG(Device->PIO4, PIO4_CLEAR_MASK, \
<> 157:ff67d9f36b67 944 (Timing->SetupTime | \
<> 157:ff67d9f36b67 945 (Timing->WaitSetupTime << POSITION_VAL(FMC_PIO4_IOWAIT4)) | \
<> 157:ff67d9f36b67 946 (Timing->HoldSetupTime << POSITION_VAL(FMC_PIO4_IOHOLD4)) | \
<> 157:ff67d9f36b67 947 (Timing->HiZSetupTime << POSITION_VAL(FMC_PIO4_IOHIZ4))));
<> 157:ff67d9f36b67 948
<> 144:ef7eb2e8f9f7 949 return HAL_OK;
<> 144:ef7eb2e8f9f7 950 }
<> 157:ff67d9f36b67 951
<> 144:ef7eb2e8f9f7 952 /**
<> 157:ff67d9f36b67 953 * @brief DeInitialize the FMC_PCCARD device
<> 157:ff67d9f36b67 954 * @param Device Pointer to PCCARD device instance
<> 144:ef7eb2e8f9f7 955 * @retval HAL status
<> 144:ef7eb2e8f9f7 956 */
<> 144:ef7eb2e8f9f7 957 HAL_StatusTypeDef FMC_PCCARD_DeInit(FMC_PCCARD_TypeDef *Device)
<> 144:ef7eb2e8f9f7 958 {
<> 157:ff67d9f36b67 959 /* Check the parameters */
<> 144:ef7eb2e8f9f7 960 assert_param(IS_FMC_PCCARD_DEVICE(Device));
<> 157:ff67d9f36b67 961
<> 144:ef7eb2e8f9f7 962 /* Disable the FMC_PCCARD device */
<> 144:ef7eb2e8f9f7 963 __FMC_PCCARD_DISABLE(Device);
<> 157:ff67d9f36b67 964
<> 144:ef7eb2e8f9f7 965 /* De-initialize the FMC_PCCARD device */
<> 157:ff67d9f36b67 966 WRITE_REG(Device->PCR4, 0x00000018);
<> 157:ff67d9f36b67 967 WRITE_REG(Device->SR4, 0x00000040);
<> 157:ff67d9f36b67 968 WRITE_REG(Device->PMEM4, 0xFCFCFCFC);
<> 157:ff67d9f36b67 969 WRITE_REG(Device->PATT4, 0xFCFCFCFC);
<> 157:ff67d9f36b67 970 WRITE_REG(Device->PIO4, 0xFCFCFCFC);
<> 157:ff67d9f36b67 971
<> 144:ef7eb2e8f9f7 972 return HAL_OK;
<> 144:ef7eb2e8f9f7 973 }
<> 144:ef7eb2e8f9f7 974
<> 144:ef7eb2e8f9f7 975 /**
<> 144:ef7eb2e8f9f7 976 * @}
<> 144:ef7eb2e8f9f7 977 */
<> 144:ef7eb2e8f9f7 978
<> 144:ef7eb2e8f9f7 979 /**
<> 144:ef7eb2e8f9f7 980 * @}
<> 144:ef7eb2e8f9f7 981 */
<> 144:ef7eb2e8f9f7 982
<> 144:ef7eb2e8f9f7 983 /**
<> 144:ef7eb2e8f9f7 984 * @}
<> 144:ef7eb2e8f9f7 985 */
<> 144:ef7eb2e8f9f7 986
<> 144:ef7eb2e8f9f7 987 /**
<> 144:ef7eb2e8f9f7 988 * @}
<> 144:ef7eb2e8f9f7 989 */
<> 144:ef7eb2e8f9f7 990
<> 157:ff67d9f36b67 991 #endif /* defined(HAL_SRAM_MODULE_ENABLED) || defined(HAL_NOR_MODULE_ENABLED) || defined(HAL_PCCARD_MODULE_ENABLED) || defined(HAL_NAND_MODULE_ENABLED) */
<> 157:ff67d9f36b67 992
<> 157:ff67d9f36b67 993 #endif /* FMC_BANK1 */
<> 157:ff67d9f36b67 994
<> 144:ef7eb2e8f9f7 995 /**
<> 144:ef7eb2e8f9f7 996 * @}
<> 144:ef7eb2e8f9f7 997 */
<> 144:ef7eb2e8f9f7 998
<> 144:ef7eb2e8f9f7 999 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/