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mbed library sources. Supersedes mbed-src.

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targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_dma.c@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
Parent:
180:96ed750bd169 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 156:95d6b41a828b 1 /**
<> 156:95d6b41a828b 2 ******************************************************************************
<> 156:95d6b41a828b 3 * @file stm32f0xx_ll_dma.c
<> 156:95d6b41a828b 4 * @author MCD Application Team
<> 156:95d6b41a828b 5 * @brief DMA LL module driver.
<> 156:95d6b41a828b 6 ******************************************************************************
<> 156:95d6b41a828b 7 * @attention
<> 156:95d6b41a828b 8 *
<> 156:95d6b41a828b 9 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 156:95d6b41a828b 10 *
<> 156:95d6b41a828b 11 * Redistribution and use in source and binary forms, with or without modification,
<> 156:95d6b41a828b 12 * are permitted provided that the following conditions are met:
<> 156:95d6b41a828b 13 * 1. Redistributions of source code must retain the above copyright notice,
<> 156:95d6b41a828b 14 * this list of conditions and the following disclaimer.
<> 156:95d6b41a828b 15 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 156:95d6b41a828b 16 * this list of conditions and the following disclaimer in the documentation
<> 156:95d6b41a828b 17 * and/or other materials provided with the distribution.
<> 156:95d6b41a828b 18 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 156:95d6b41a828b 19 * may be used to endorse or promote products derived from this software
<> 156:95d6b41a828b 20 * without specific prior written permission.
<> 156:95d6b41a828b 21 *
<> 156:95d6b41a828b 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 156:95d6b41a828b 23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 156:95d6b41a828b 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 156:95d6b41a828b 25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 156:95d6b41a828b 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 156:95d6b41a828b 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 156:95d6b41a828b 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 156:95d6b41a828b 29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 156:95d6b41a828b 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 156:95d6b41a828b 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 156:95d6b41a828b 32 *
<> 156:95d6b41a828b 33 ******************************************************************************
<> 156:95d6b41a828b 34 */
<> 156:95d6b41a828b 35 #if defined(USE_FULL_LL_DRIVER)
<> 156:95d6b41a828b 36
<> 156:95d6b41a828b 37 /* Includes ------------------------------------------------------------------*/
<> 156:95d6b41a828b 38 #include "stm32f0xx_ll_dma.h"
<> 156:95d6b41a828b 39 #include "stm32f0xx_ll_bus.h"
<> 156:95d6b41a828b 40 #ifdef USE_FULL_ASSERT
<> 156:95d6b41a828b 41 #include "stm32_assert.h"
<> 156:95d6b41a828b 42 #else
<> 156:95d6b41a828b 43 #define assert_param(expr) ((void)0U)
<> 156:95d6b41a828b 44 #endif
<> 156:95d6b41a828b 45
<> 156:95d6b41a828b 46 /** @addtogroup STM32F0xx_LL_Driver
<> 156:95d6b41a828b 47 * @{
<> 156:95d6b41a828b 48 */
<> 156:95d6b41a828b 49
<> 156:95d6b41a828b 50 #if defined (DMA1) || defined (DMA2)
<> 156:95d6b41a828b 51
<> 156:95d6b41a828b 52 /** @defgroup DMA_LL DMA
<> 156:95d6b41a828b 53 * @{
<> 156:95d6b41a828b 54 */
<> 156:95d6b41a828b 55
<> 156:95d6b41a828b 56 /* Private types -------------------------------------------------------------*/
<> 156:95d6b41a828b 57 /* Private variables ---------------------------------------------------------*/
<> 156:95d6b41a828b 58 /* Private constants ---------------------------------------------------------*/
<> 156:95d6b41a828b 59 /* Private macros ------------------------------------------------------------*/
<> 156:95d6b41a828b 60 /** @addtogroup DMA_LL_Private_Macros
<> 156:95d6b41a828b 61 * @{
<> 156:95d6b41a828b 62 */
<> 156:95d6b41a828b 63 #define IS_LL_DMA_DIRECTION(__VALUE__) (((__VALUE__) == LL_DMA_DIRECTION_PERIPH_TO_MEMORY) || \
<> 156:95d6b41a828b 64 ((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_PERIPH) || \
<> 156:95d6b41a828b 65 ((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_MEMORY))
<> 156:95d6b41a828b 66
<> 156:95d6b41a828b 67 #define IS_LL_DMA_MODE(__VALUE__) (((__VALUE__) == LL_DMA_MODE_NORMAL) || \
<> 156:95d6b41a828b 68 ((__VALUE__) == LL_DMA_MODE_CIRCULAR))
<> 156:95d6b41a828b 69
<> 156:95d6b41a828b 70 #define IS_LL_DMA_PERIPHINCMODE(__VALUE__) (((__VALUE__) == LL_DMA_PERIPH_INCREMENT) || \
<> 156:95d6b41a828b 71 ((__VALUE__) == LL_DMA_PERIPH_NOINCREMENT))
<> 156:95d6b41a828b 72
<> 156:95d6b41a828b 73 #define IS_LL_DMA_MEMORYINCMODE(__VALUE__) (((__VALUE__) == LL_DMA_MEMORY_INCREMENT) || \
<> 156:95d6b41a828b 74 ((__VALUE__) == LL_DMA_MEMORY_NOINCREMENT))
<> 156:95d6b41a828b 75
<> 156:95d6b41a828b 76 #define IS_LL_DMA_PERIPHDATASIZE(__VALUE__) (((__VALUE__) == LL_DMA_PDATAALIGN_BYTE) || \
<> 156:95d6b41a828b 77 ((__VALUE__) == LL_DMA_PDATAALIGN_HALFWORD) || \
<> 156:95d6b41a828b 78 ((__VALUE__) == LL_DMA_PDATAALIGN_WORD))
<> 156:95d6b41a828b 79
<> 156:95d6b41a828b 80 #define IS_LL_DMA_MEMORYDATASIZE(__VALUE__) (((__VALUE__) == LL_DMA_MDATAALIGN_BYTE) || \
<> 156:95d6b41a828b 81 ((__VALUE__) == LL_DMA_MDATAALIGN_HALFWORD) || \
<> 156:95d6b41a828b 82 ((__VALUE__) == LL_DMA_MDATAALIGN_WORD))
<> 156:95d6b41a828b 83
Anna Bridge 180:96ed750bd169 84 #define IS_LL_DMA_NBDATA(__VALUE__) ((__VALUE__) <= 0x0000FFFFU)
<> 156:95d6b41a828b 85
<> 156:95d6b41a828b 86 #if (defined(DMA1_CSELR_DEFAULT)||defined(DMA2_CSELR_DEFAULT))
<> 156:95d6b41a828b 87 #define IS_LL_DMA_PERIPHREQUEST(__VALUE__) (((__VALUE__) == LL_DMA_REQUEST_0) || \
<> 156:95d6b41a828b 88 ((__VALUE__) == LL_DMA_REQUEST_1) || \
<> 156:95d6b41a828b 89 ((__VALUE__) == LL_DMA_REQUEST_2) || \
<> 156:95d6b41a828b 90 ((__VALUE__) == LL_DMA_REQUEST_3) || \
<> 156:95d6b41a828b 91 ((__VALUE__) == LL_DMA_REQUEST_4) || \
<> 156:95d6b41a828b 92 ((__VALUE__) == LL_DMA_REQUEST_5) || \
<> 156:95d6b41a828b 93 ((__VALUE__) == LL_DMA_REQUEST_6) || \
<> 156:95d6b41a828b 94 ((__VALUE__) == LL_DMA_REQUEST_7) || \
<> 156:95d6b41a828b 95 ((__VALUE__) == LL_DMA_REQUEST_8) || \
<> 156:95d6b41a828b 96 ((__VALUE__) == LL_DMA_REQUEST_9) || \
<> 156:95d6b41a828b 97 ((__VALUE__) == LL_DMA_REQUEST_10) || \
<> 156:95d6b41a828b 98 ((__VALUE__) == LL_DMA_REQUEST_11) || \
<> 156:95d6b41a828b 99 ((__VALUE__) == LL_DMA_REQUEST_12) || \
<> 156:95d6b41a828b 100 ((__VALUE__) == LL_DMA_REQUEST_13) || \
<> 156:95d6b41a828b 101 ((__VALUE__) == LL_DMA_REQUEST_14) || \
<> 156:95d6b41a828b 102 ((__VALUE__) == LL_DMA_REQUEST_15))
<> 156:95d6b41a828b 103 #endif
<> 156:95d6b41a828b 104
<> 156:95d6b41a828b 105 #define IS_LL_DMA_PRIORITY(__VALUE__) (((__VALUE__) == LL_DMA_PRIORITY_LOW) || \
<> 156:95d6b41a828b 106 ((__VALUE__) == LL_DMA_PRIORITY_MEDIUM) || \
<> 156:95d6b41a828b 107 ((__VALUE__) == LL_DMA_PRIORITY_HIGH) || \
<> 156:95d6b41a828b 108 ((__VALUE__) == LL_DMA_PRIORITY_VERYHIGH))
<> 156:95d6b41a828b 109
<> 156:95d6b41a828b 110 #if defined (DMA2)
<> 156:95d6b41a828b 111 #if defined (DMA2_Channel6) && defined (DMA2_Channel7)
<> 156:95d6b41a828b 112 #define IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL) ((((INSTANCE) == DMA1) && \
<> 156:95d6b41a828b 113 (((CHANNEL) == LL_DMA_CHANNEL_1) || \
<> 156:95d6b41a828b 114 ((CHANNEL) == LL_DMA_CHANNEL_2) || \
<> 156:95d6b41a828b 115 ((CHANNEL) == LL_DMA_CHANNEL_3) || \
<> 156:95d6b41a828b 116 ((CHANNEL) == LL_DMA_CHANNEL_4) || \
<> 156:95d6b41a828b 117 ((CHANNEL) == LL_DMA_CHANNEL_5) || \
<> 156:95d6b41a828b 118 ((CHANNEL) == LL_DMA_CHANNEL_6) || \
<> 156:95d6b41a828b 119 ((CHANNEL) == LL_DMA_CHANNEL_7))) || \
<> 156:95d6b41a828b 120 (((INSTANCE) == DMA2) && \
<> 156:95d6b41a828b 121 (((CHANNEL) == LL_DMA_CHANNEL_1) || \
<> 156:95d6b41a828b 122 ((CHANNEL) == LL_DMA_CHANNEL_2) || \
<> 156:95d6b41a828b 123 ((CHANNEL) == LL_DMA_CHANNEL_3) || \
<> 156:95d6b41a828b 124 ((CHANNEL) == LL_DMA_CHANNEL_4) || \
<> 156:95d6b41a828b 125 ((CHANNEL) == LL_DMA_CHANNEL_5) || \
<> 156:95d6b41a828b 126 ((CHANNEL) == LL_DMA_CHANNEL_6) || \
<> 156:95d6b41a828b 127 ((CHANNEL) == LL_DMA_CHANNEL_7))))
<> 156:95d6b41a828b 128 #else
<> 156:95d6b41a828b 129 #define IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL) ((((INSTANCE) == DMA1) && \
<> 156:95d6b41a828b 130 (((CHANNEL) == LL_DMA_CHANNEL_1) || \
<> 156:95d6b41a828b 131 ((CHANNEL) == LL_DMA_CHANNEL_2) || \
<> 156:95d6b41a828b 132 ((CHANNEL) == LL_DMA_CHANNEL_3) || \
<> 156:95d6b41a828b 133 ((CHANNEL) == LL_DMA_CHANNEL_4) || \
<> 156:95d6b41a828b 134 ((CHANNEL) == LL_DMA_CHANNEL_5) || \
<> 156:95d6b41a828b 135 ((CHANNEL) == LL_DMA_CHANNEL_6) || \
<> 156:95d6b41a828b 136 ((CHANNEL) == LL_DMA_CHANNEL_7))) || \
<> 156:95d6b41a828b 137 (((INSTANCE) == DMA2) && \
<> 156:95d6b41a828b 138 (((CHANNEL) == LL_DMA_CHANNEL_1) || \
<> 156:95d6b41a828b 139 ((CHANNEL) == LL_DMA_CHANNEL_2) || \
<> 156:95d6b41a828b 140 ((CHANNEL) == LL_DMA_CHANNEL_3) || \
<> 156:95d6b41a828b 141 ((CHANNEL) == LL_DMA_CHANNEL_4) || \
<> 156:95d6b41a828b 142 ((CHANNEL) == LL_DMA_CHANNEL_5))))
<> 156:95d6b41a828b 143 #endif
<> 156:95d6b41a828b 144 #else
<> 156:95d6b41a828b 145 #if defined(DMA1_Channel6) && defined(DMA1_Channel7)
<> 156:95d6b41a828b 146 #define IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL) ((((INSTANCE) == DMA1) && \
<> 156:95d6b41a828b 147 (((CHANNEL) == LL_DMA_CHANNEL_1)|| \
<> 156:95d6b41a828b 148 ((CHANNEL) == LL_DMA_CHANNEL_2) || \
<> 156:95d6b41a828b 149 ((CHANNEL) == LL_DMA_CHANNEL_3) || \
<> 156:95d6b41a828b 150 ((CHANNEL) == LL_DMA_CHANNEL_4) || \
<> 156:95d6b41a828b 151 ((CHANNEL) == LL_DMA_CHANNEL_5) || \
<> 156:95d6b41a828b 152 ((CHANNEL) == LL_DMA_CHANNEL_6) || \
<> 156:95d6b41a828b 153 ((CHANNEL) == LL_DMA_CHANNEL_7))))
<> 156:95d6b41a828b 154 #elif defined (DMA1_Channel6)
<> 156:95d6b41a828b 155 #define IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL) ((((INSTANCE) == DMA1) && \
<> 156:95d6b41a828b 156 (((CHANNEL) == LL_DMA_CHANNEL_1)|| \
<> 156:95d6b41a828b 157 ((CHANNEL) == LL_DMA_CHANNEL_2) || \
<> 156:95d6b41a828b 158 ((CHANNEL) == LL_DMA_CHANNEL_3) || \
<> 156:95d6b41a828b 159 ((CHANNEL) == LL_DMA_CHANNEL_4) || \
<> 156:95d6b41a828b 160 ((CHANNEL) == LL_DMA_CHANNEL_5) || \
<> 156:95d6b41a828b 161 ((CHANNEL) == LL_DMA_CHANNEL_6))))
<> 156:95d6b41a828b 162 #else
<> 156:95d6b41a828b 163 #define IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL) ((((INSTANCE) == DMA1) && \
<> 156:95d6b41a828b 164 (((CHANNEL) == LL_DMA_CHANNEL_1)|| \
<> 156:95d6b41a828b 165 ((CHANNEL) == LL_DMA_CHANNEL_2) || \
<> 156:95d6b41a828b 166 ((CHANNEL) == LL_DMA_CHANNEL_3) || \
<> 156:95d6b41a828b 167 ((CHANNEL) == LL_DMA_CHANNEL_4) || \
<> 156:95d6b41a828b 168 ((CHANNEL) == LL_DMA_CHANNEL_5))))
<> 156:95d6b41a828b 169 #endif /* DMA1_Channel6 && DMA1_Channel7 */
<> 156:95d6b41a828b 170 #endif
<> 156:95d6b41a828b 171 /**
<> 156:95d6b41a828b 172 * @}
<> 156:95d6b41a828b 173 */
<> 156:95d6b41a828b 174
<> 156:95d6b41a828b 175 /* Private function prototypes -----------------------------------------------*/
<> 156:95d6b41a828b 176
<> 156:95d6b41a828b 177 /* Exported functions --------------------------------------------------------*/
<> 156:95d6b41a828b 178 /** @addtogroup DMA_LL_Exported_Functions
<> 156:95d6b41a828b 179 * @{
<> 156:95d6b41a828b 180 */
<> 156:95d6b41a828b 181
<> 156:95d6b41a828b 182 /** @addtogroup DMA_LL_EF_Init
<> 156:95d6b41a828b 183 * @{
<> 156:95d6b41a828b 184 */
<> 156:95d6b41a828b 185
<> 156:95d6b41a828b 186 /**
<> 156:95d6b41a828b 187 * @brief De-initialize the DMA registers to their default reset values.
<> 156:95d6b41a828b 188 * @param DMAx DMAx Instance
<> 156:95d6b41a828b 189 * @param Channel This parameter can be one of the following values:
<> 156:95d6b41a828b 190 * @arg @ref LL_DMA_CHANNEL_1
<> 156:95d6b41a828b 191 * @arg @ref LL_DMA_CHANNEL_2
<> 156:95d6b41a828b 192 * @arg @ref LL_DMA_CHANNEL_3
<> 156:95d6b41a828b 193 * @arg @ref LL_DMA_CHANNEL_4
<> 156:95d6b41a828b 194 * @arg @ref LL_DMA_CHANNEL_5
<> 156:95d6b41a828b 195 * @arg @ref LL_DMA_CHANNEL_6 (*)
<> 156:95d6b41a828b 196 * @arg @ref LL_DMA_CHANNEL_7 (*)
<> 156:95d6b41a828b 197 *
<> 156:95d6b41a828b 198 * (*) value not defined in all devices
<> 156:95d6b41a828b 199 * @retval An ErrorStatus enumeration value:
<> 156:95d6b41a828b 200 * - SUCCESS: DMA registers are de-initialized
<> 156:95d6b41a828b 201 * - ERROR: DMA registers are not de-initialized
<> 156:95d6b41a828b 202 */
<> 156:95d6b41a828b 203 uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel)
<> 156:95d6b41a828b 204 {
<> 156:95d6b41a828b 205 DMA_Channel_TypeDef *tmp = (DMA_Channel_TypeDef *)DMA1_Channel1;
<> 156:95d6b41a828b 206 ErrorStatus status = SUCCESS;
<> 156:95d6b41a828b 207
<> 156:95d6b41a828b 208 /* Check the DMA Instance DMAx and Channel parameters*/
<> 156:95d6b41a828b 209 assert_param(IS_LL_DMA_ALL_CHANNEL_INSTANCE(DMAx, Channel));
<> 156:95d6b41a828b 210
<> 156:95d6b41a828b 211 tmp = (DMA_Channel_TypeDef *)(__LL_DMA_GET_CHANNEL_INSTANCE(DMAx, Channel));
<> 156:95d6b41a828b 212
<> 156:95d6b41a828b 213 /* Disable the selected DMAx_Channely */
<> 156:95d6b41a828b 214 CLEAR_BIT(tmp->CCR, DMA_CCR_EN);
<> 156:95d6b41a828b 215
<> 156:95d6b41a828b 216 /* Reset DMAx_Channely control register */
<> 156:95d6b41a828b 217 LL_DMA_WriteReg(tmp, CCR, 0U);
<> 156:95d6b41a828b 218
<> 156:95d6b41a828b 219 /* Reset DMAx_Channely remaining bytes register */
<> 156:95d6b41a828b 220 LL_DMA_WriteReg(tmp, CNDTR, 0U);
<> 156:95d6b41a828b 221
<> 156:95d6b41a828b 222 /* Reset DMAx_Channely peripheral address register */
<> 156:95d6b41a828b 223 LL_DMA_WriteReg(tmp, CPAR, 0U);
<> 156:95d6b41a828b 224
<> 156:95d6b41a828b 225 /* Reset DMAx_Channely memory address register */
<> 156:95d6b41a828b 226 LL_DMA_WriteReg(tmp, CMAR, 0U);
<> 156:95d6b41a828b 227
<> 156:95d6b41a828b 228 #if (defined(DMA1_CSELR_DEFAULT)||defined(DMA2_CSELR_DEFAULT))
<> 156:95d6b41a828b 229 /* Reset Request register field for DMAx Channel */
<> 156:95d6b41a828b 230 LL_DMA_SetPeriphRequest(DMAx, Channel, LL_DMA_REQUEST_0);
<> 156:95d6b41a828b 231 #endif
<> 156:95d6b41a828b 232
<> 156:95d6b41a828b 233 if (Channel == LL_DMA_CHANNEL_1)
<> 156:95d6b41a828b 234 {
<> 156:95d6b41a828b 235 /* Reset interrupt pending bits for DMAx Channel1 */
<> 156:95d6b41a828b 236 LL_DMA_ClearFlag_GI1(DMAx);
<> 156:95d6b41a828b 237 }
<> 156:95d6b41a828b 238 else if (Channel == LL_DMA_CHANNEL_2)
<> 156:95d6b41a828b 239 {
<> 156:95d6b41a828b 240 /* Reset interrupt pending bits for DMAx Channel2 */
<> 156:95d6b41a828b 241 LL_DMA_ClearFlag_GI2(DMAx);
<> 156:95d6b41a828b 242 }
<> 156:95d6b41a828b 243 else if (Channel == LL_DMA_CHANNEL_3)
<> 156:95d6b41a828b 244 {
<> 156:95d6b41a828b 245 /* Reset interrupt pending bits for DMAx Channel3 */
<> 156:95d6b41a828b 246 LL_DMA_ClearFlag_GI3(DMAx);
<> 156:95d6b41a828b 247 }
<> 156:95d6b41a828b 248 else if (Channel == LL_DMA_CHANNEL_4)
<> 156:95d6b41a828b 249 {
<> 156:95d6b41a828b 250 /* Reset interrupt pending bits for DMAx Channel4 */
<> 156:95d6b41a828b 251 LL_DMA_ClearFlag_GI4(DMAx);
<> 156:95d6b41a828b 252 }
<> 156:95d6b41a828b 253 else if (Channel == LL_DMA_CHANNEL_5)
<> 156:95d6b41a828b 254 {
<> 156:95d6b41a828b 255 /* Reset interrupt pending bits for DMAx Channel5 */
<> 156:95d6b41a828b 256 LL_DMA_ClearFlag_GI5(DMAx);
<> 156:95d6b41a828b 257 }
<> 156:95d6b41a828b 258
<> 156:95d6b41a828b 259 #if defined(DMA1_Channel6)
<> 156:95d6b41a828b 260 else if (Channel == LL_DMA_CHANNEL_6)
<> 156:95d6b41a828b 261 {
<> 156:95d6b41a828b 262 /* Reset interrupt pending bits for DMAx Channel6 */
<> 156:95d6b41a828b 263 LL_DMA_ClearFlag_GI6(DMAx);
<> 156:95d6b41a828b 264 }
<> 156:95d6b41a828b 265 #endif
<> 156:95d6b41a828b 266 #if defined(DMA1_Channel7)
<> 156:95d6b41a828b 267 else if (Channel == LL_DMA_CHANNEL_7)
<> 156:95d6b41a828b 268 {
<> 156:95d6b41a828b 269 /* Reset interrupt pending bits for DMAx Channel7 */
<> 156:95d6b41a828b 270 LL_DMA_ClearFlag_GI7(DMAx);
<> 156:95d6b41a828b 271 }
<> 156:95d6b41a828b 272 #endif
<> 156:95d6b41a828b 273 else
<> 156:95d6b41a828b 274 {
<> 156:95d6b41a828b 275 status = ERROR;
<> 156:95d6b41a828b 276 }
<> 156:95d6b41a828b 277
<> 156:95d6b41a828b 278 return status;
<> 156:95d6b41a828b 279 }
<> 156:95d6b41a828b 280
<> 156:95d6b41a828b 281 /**
<> 156:95d6b41a828b 282 * @brief Initialize the DMA registers according to the specified parameters in DMA_InitStruct.
<> 156:95d6b41a828b 283 * @note To convert DMAx_Channely Instance to DMAx Instance and Channely, use helper macros :
<> 156:95d6b41a828b 284 * @arg @ref __LL_DMA_GET_INSTANCE
<> 156:95d6b41a828b 285 * @arg @ref __LL_DMA_GET_CHANNEL
<> 156:95d6b41a828b 286 * @param DMAx DMAx Instance
<> 156:95d6b41a828b 287 * @param Channel This parameter can be one of the following values:
<> 156:95d6b41a828b 288 * @arg @ref LL_DMA_CHANNEL_1
<> 156:95d6b41a828b 289 * @arg @ref LL_DMA_CHANNEL_2
<> 156:95d6b41a828b 290 * @arg @ref LL_DMA_CHANNEL_3
<> 156:95d6b41a828b 291 * @arg @ref LL_DMA_CHANNEL_4
<> 156:95d6b41a828b 292 * @arg @ref LL_DMA_CHANNEL_5
<> 156:95d6b41a828b 293 * @arg @ref LL_DMA_CHANNEL_6 (*)
<> 156:95d6b41a828b 294 * @arg @ref LL_DMA_CHANNEL_7 (*)
<> 156:95d6b41a828b 295 *
<> 156:95d6b41a828b 296 * (*) value not defined in all devices
<> 156:95d6b41a828b 297 * @param DMA_InitStruct pointer to a @ref LL_DMA_InitTypeDef structure.
<> 156:95d6b41a828b 298 * @retval An ErrorStatus enumeration value:
<> 156:95d6b41a828b 299 * - SUCCESS: DMA registers are initialized
<> 156:95d6b41a828b 300 * - ERROR: Not applicable
<> 156:95d6b41a828b 301 */
<> 156:95d6b41a828b 302 uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DMA_InitStruct)
<> 156:95d6b41a828b 303 {
<> 156:95d6b41a828b 304 /* Check the DMA Instance DMAx and Channel parameters*/
<> 156:95d6b41a828b 305 assert_param(IS_LL_DMA_ALL_CHANNEL_INSTANCE(DMAx, Channel));
<> 156:95d6b41a828b 306
<> 156:95d6b41a828b 307 /* Check the DMA parameters from DMA_InitStruct */
<> 156:95d6b41a828b 308 assert_param(IS_LL_DMA_DIRECTION(DMA_InitStruct->Direction));
<> 156:95d6b41a828b 309 assert_param(IS_LL_DMA_MODE(DMA_InitStruct->Mode));
<> 156:95d6b41a828b 310 assert_param(IS_LL_DMA_PERIPHINCMODE(DMA_InitStruct->PeriphOrM2MSrcIncMode));
<> 156:95d6b41a828b 311 assert_param(IS_LL_DMA_MEMORYINCMODE(DMA_InitStruct->MemoryOrM2MDstIncMode));
<> 156:95d6b41a828b 312 assert_param(IS_LL_DMA_PERIPHDATASIZE(DMA_InitStruct->PeriphOrM2MSrcDataSize));
<> 156:95d6b41a828b 313 assert_param(IS_LL_DMA_MEMORYDATASIZE(DMA_InitStruct->MemoryOrM2MDstDataSize));
<> 156:95d6b41a828b 314 assert_param(IS_LL_DMA_NBDATA(DMA_InitStruct->NbData));
<> 156:95d6b41a828b 315 #if (defined(DMA1_CSELR_DEFAULT)||defined(DMA2_CSELR_DEFAULT))
<> 156:95d6b41a828b 316 assert_param(IS_LL_DMA_PERIPHREQUEST(DMA_InitStruct->PeriphRequest));
<> 156:95d6b41a828b 317 #endif
<> 156:95d6b41a828b 318 assert_param(IS_LL_DMA_PRIORITY(DMA_InitStruct->Priority));
<> 156:95d6b41a828b 319
<> 156:95d6b41a828b 320 /*---------------------------- DMAx CCR Configuration ------------------------
<> 156:95d6b41a828b 321 * Configure DMAx_Channely: data transfer direction, data transfer mode,
<> 156:95d6b41a828b 322 * peripheral and memory increment mode,
<> 156:95d6b41a828b 323 * data size alignment and priority level with parameters :
<> 156:95d6b41a828b 324 * - Direction: DMA_CCR_DIR and DMA_CCR_MEM2MEM bits
<> 156:95d6b41a828b 325 * - Mode: DMA_CCR_CIRC bit
<> 156:95d6b41a828b 326 * - PeriphOrM2MSrcIncMode: DMA_CCR_PINC bit
<> 156:95d6b41a828b 327 * - MemoryOrM2MDstIncMode: DMA_CCR_MINC bit
<> 156:95d6b41a828b 328 * - PeriphOrM2MSrcDataSize: DMA_CCR_PSIZE[1:0] bits
<> 156:95d6b41a828b 329 * - MemoryOrM2MDstDataSize: DMA_CCR_MSIZE[1:0] bits
<> 156:95d6b41a828b 330 * - Priority: DMA_CCR_PL[1:0] bits
<> 156:95d6b41a828b 331 */
<> 156:95d6b41a828b 332 LL_DMA_ConfigTransfer(DMAx, Channel, DMA_InitStruct->Direction | \
<> 156:95d6b41a828b 333 DMA_InitStruct->Mode | \
<> 156:95d6b41a828b 334 DMA_InitStruct->PeriphOrM2MSrcIncMode | \
<> 156:95d6b41a828b 335 DMA_InitStruct->MemoryOrM2MDstIncMode | \
<> 156:95d6b41a828b 336 DMA_InitStruct->PeriphOrM2MSrcDataSize | \
<> 156:95d6b41a828b 337 DMA_InitStruct->MemoryOrM2MDstDataSize | \
<> 156:95d6b41a828b 338 DMA_InitStruct->Priority);
<> 156:95d6b41a828b 339
<> 156:95d6b41a828b 340 /*-------------------------- DMAx CMAR Configuration -------------------------
<> 156:95d6b41a828b 341 * Configure the memory or destination base address with parameter :
<> 156:95d6b41a828b 342 * - MemoryOrM2MDstAddress: DMA_CMAR_MA[31:0] bits
<> 156:95d6b41a828b 343 */
<> 156:95d6b41a828b 344 LL_DMA_SetMemoryAddress(DMAx, Channel, DMA_InitStruct->MemoryOrM2MDstAddress);
<> 156:95d6b41a828b 345
<> 156:95d6b41a828b 346 /*-------------------------- DMAx CPAR Configuration -------------------------
<> 156:95d6b41a828b 347 * Configure the peripheral or source base address with parameter :
<> 156:95d6b41a828b 348 * - PeriphOrM2MSrcAddress: DMA_CPAR_PA[31:0] bits
<> 156:95d6b41a828b 349 */
<> 156:95d6b41a828b 350 LL_DMA_SetPeriphAddress(DMAx, Channel, DMA_InitStruct->PeriphOrM2MSrcAddress);
<> 156:95d6b41a828b 351
<> 156:95d6b41a828b 352 /*--------------------------- DMAx CNDTR Configuration -----------------------
<> 156:95d6b41a828b 353 * Configure the peripheral base address with parameter :
<> 156:95d6b41a828b 354 * - NbData: DMA_CNDTR_NDT[15:0] bits
<> 156:95d6b41a828b 355 */
<> 156:95d6b41a828b 356 LL_DMA_SetDataLength(DMAx, Channel, DMA_InitStruct->NbData);
<> 156:95d6b41a828b 357
<> 156:95d6b41a828b 358 #if (defined(DMA1_CSELR_DEFAULT)||defined(DMA2_CSELR_DEFAULT))
<> 156:95d6b41a828b 359 /*--------------------------- DMAx CSELR Configuration -----------------------
Anna Bridge 180:96ed750bd169 360 * Configure the DMA request for DMA instance on Channel x with parameter :
<> 156:95d6b41a828b 361 * - PeriphRequest: DMA_CSELR[31:0] bits
<> 156:95d6b41a828b 362 */
<> 156:95d6b41a828b 363 LL_DMA_SetPeriphRequest(DMAx, Channel, DMA_InitStruct->PeriphRequest);
<> 156:95d6b41a828b 364 #endif
<> 156:95d6b41a828b 365
<> 156:95d6b41a828b 366 return SUCCESS;
<> 156:95d6b41a828b 367 }
<> 156:95d6b41a828b 368
<> 156:95d6b41a828b 369 /**
<> 156:95d6b41a828b 370 * @brief Set each @ref LL_DMA_InitTypeDef field to default value.
<> 156:95d6b41a828b 371 * @param DMA_InitStruct Pointer to a @ref LL_DMA_InitTypeDef structure.
<> 156:95d6b41a828b 372 * @retval None
<> 156:95d6b41a828b 373 */
<> 156:95d6b41a828b 374 void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct)
<> 156:95d6b41a828b 375 {
<> 156:95d6b41a828b 376 /* Set DMA_InitStruct fields to default values */
Anna Bridge 180:96ed750bd169 377 DMA_InitStruct->PeriphOrM2MSrcAddress = 0x00000000U;
Anna Bridge 180:96ed750bd169 378 DMA_InitStruct->MemoryOrM2MDstAddress = 0x00000000U;
<> 156:95d6b41a828b 379 DMA_InitStruct->Direction = LL_DMA_DIRECTION_PERIPH_TO_MEMORY;
<> 156:95d6b41a828b 380 DMA_InitStruct->Mode = LL_DMA_MODE_NORMAL;
<> 156:95d6b41a828b 381 DMA_InitStruct->PeriphOrM2MSrcIncMode = LL_DMA_PERIPH_NOINCREMENT;
<> 156:95d6b41a828b 382 DMA_InitStruct->MemoryOrM2MDstIncMode = LL_DMA_MEMORY_NOINCREMENT;
<> 156:95d6b41a828b 383 DMA_InitStruct->PeriphOrM2MSrcDataSize = LL_DMA_PDATAALIGN_BYTE;
<> 156:95d6b41a828b 384 DMA_InitStruct->MemoryOrM2MDstDataSize = LL_DMA_MDATAALIGN_BYTE;
Anna Bridge 180:96ed750bd169 385 DMA_InitStruct->NbData = 0x00000000U;
<> 156:95d6b41a828b 386 #if (defined(DMA1_CSELR_DEFAULT)||defined(DMA2_CSELR_DEFAULT))
<> 156:95d6b41a828b 387 DMA_InitStruct->PeriphRequest = LL_DMA_REQUEST_0;
<> 156:95d6b41a828b 388 #endif
<> 156:95d6b41a828b 389 DMA_InitStruct->Priority = LL_DMA_PRIORITY_LOW;
<> 156:95d6b41a828b 390 }
<> 156:95d6b41a828b 391
<> 156:95d6b41a828b 392 /**
<> 156:95d6b41a828b 393 * @}
<> 156:95d6b41a828b 394 */
<> 156:95d6b41a828b 395
<> 156:95d6b41a828b 396 /**
<> 156:95d6b41a828b 397 * @}
<> 156:95d6b41a828b 398 */
<> 156:95d6b41a828b 399
<> 156:95d6b41a828b 400 /**
<> 156:95d6b41a828b 401 * @}
<> 156:95d6b41a828b 402 */
<> 156:95d6b41a828b 403
<> 156:95d6b41a828b 404 #endif /* DMA1 || DMA2 */
<> 156:95d6b41a828b 405
<> 156:95d6b41a828b 406 /**
<> 156:95d6b41a828b 407 * @}
<> 156:95d6b41a828b 408 */
<> 156:95d6b41a828b 409
<> 156:95d6b41a828b 410 #endif /* USE_FULL_LL_DRIVER */
<> 156:95d6b41a828b 411
<> 156:95d6b41a828b 412 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/