mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

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targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_dma.c@156:95d6b41a828b, 2017-01-16 (annotated)

Committer:
<>
Date:
Mon Jan 16 15:03:32 2017 +0000
Revision:
156:95d6b41a828b
Child:
180:96ed750bd169
This updates the lib to the mbed lib v134

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 156:95d6b41a828b 1 /**
<> 156:95d6b41a828b 2 ******************************************************************************
<> 156:95d6b41a828b 3 * @file stm32f0xx_ll_dma.c
<> 156:95d6b41a828b 4 * @author MCD Application Team
<> 156:95d6b41a828b 5 * @version V1.4.0
<> 156:95d6b41a828b 6 * @date 27-May-2016
<> 156:95d6b41a828b 7 * @brief DMA LL module driver.
<> 156:95d6b41a828b 8 ******************************************************************************
<> 156:95d6b41a828b 9 * @attention
<> 156:95d6b41a828b 10 *
<> 156:95d6b41a828b 11 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 156:95d6b41a828b 12 *
<> 156:95d6b41a828b 13 * Redistribution and use in source and binary forms, with or without modification,
<> 156:95d6b41a828b 14 * are permitted provided that the following conditions are met:
<> 156:95d6b41a828b 15 * 1. Redistributions of source code must retain the above copyright notice,
<> 156:95d6b41a828b 16 * this list of conditions and the following disclaimer.
<> 156:95d6b41a828b 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 156:95d6b41a828b 18 * this list of conditions and the following disclaimer in the documentation
<> 156:95d6b41a828b 19 * and/or other materials provided with the distribution.
<> 156:95d6b41a828b 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 156:95d6b41a828b 21 * may be used to endorse or promote products derived from this software
<> 156:95d6b41a828b 22 * without specific prior written permission.
<> 156:95d6b41a828b 23 *
<> 156:95d6b41a828b 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 156:95d6b41a828b 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 156:95d6b41a828b 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 156:95d6b41a828b 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 156:95d6b41a828b 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 156:95d6b41a828b 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 156:95d6b41a828b 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 156:95d6b41a828b 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 156:95d6b41a828b 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 156:95d6b41a828b 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 156:95d6b41a828b 34 *
<> 156:95d6b41a828b 35 ******************************************************************************
<> 156:95d6b41a828b 36 */
<> 156:95d6b41a828b 37 #if defined(USE_FULL_LL_DRIVER)
<> 156:95d6b41a828b 38
<> 156:95d6b41a828b 39 /* Includes ------------------------------------------------------------------*/
<> 156:95d6b41a828b 40 #include "stm32f0xx_ll_dma.h"
<> 156:95d6b41a828b 41 #include "stm32f0xx_ll_bus.h"
<> 156:95d6b41a828b 42 #ifdef USE_FULL_ASSERT
<> 156:95d6b41a828b 43 #include "stm32_assert.h"
<> 156:95d6b41a828b 44 #else
<> 156:95d6b41a828b 45 #define assert_param(expr) ((void)0U)
<> 156:95d6b41a828b 46 #endif
<> 156:95d6b41a828b 47
<> 156:95d6b41a828b 48 /** @addtogroup STM32F0xx_LL_Driver
<> 156:95d6b41a828b 49 * @{
<> 156:95d6b41a828b 50 */
<> 156:95d6b41a828b 51
<> 156:95d6b41a828b 52 #if defined (DMA1) || defined (DMA2)
<> 156:95d6b41a828b 53
<> 156:95d6b41a828b 54 /** @defgroup DMA_LL DMA
<> 156:95d6b41a828b 55 * @{
<> 156:95d6b41a828b 56 */
<> 156:95d6b41a828b 57
<> 156:95d6b41a828b 58 /* Private types -------------------------------------------------------------*/
<> 156:95d6b41a828b 59 /* Private variables ---------------------------------------------------------*/
<> 156:95d6b41a828b 60 /* Private constants ---------------------------------------------------------*/
<> 156:95d6b41a828b 61 /* Private macros ------------------------------------------------------------*/
<> 156:95d6b41a828b 62 /** @addtogroup DMA_LL_Private_Macros
<> 156:95d6b41a828b 63 * @{
<> 156:95d6b41a828b 64 */
<> 156:95d6b41a828b 65 #define IS_LL_DMA_DIRECTION(__VALUE__) (((__VALUE__) == LL_DMA_DIRECTION_PERIPH_TO_MEMORY) || \
<> 156:95d6b41a828b 66 ((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_PERIPH) || \
<> 156:95d6b41a828b 67 ((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_MEMORY))
<> 156:95d6b41a828b 68
<> 156:95d6b41a828b 69 #define IS_LL_DMA_MODE(__VALUE__) (((__VALUE__) == LL_DMA_MODE_NORMAL) || \
<> 156:95d6b41a828b 70 ((__VALUE__) == LL_DMA_MODE_CIRCULAR))
<> 156:95d6b41a828b 71
<> 156:95d6b41a828b 72 #define IS_LL_DMA_PERIPHINCMODE(__VALUE__) (((__VALUE__) == LL_DMA_PERIPH_INCREMENT) || \
<> 156:95d6b41a828b 73 ((__VALUE__) == LL_DMA_PERIPH_NOINCREMENT))
<> 156:95d6b41a828b 74
<> 156:95d6b41a828b 75 #define IS_LL_DMA_MEMORYINCMODE(__VALUE__) (((__VALUE__) == LL_DMA_MEMORY_INCREMENT) || \
<> 156:95d6b41a828b 76 ((__VALUE__) == LL_DMA_MEMORY_NOINCREMENT))
<> 156:95d6b41a828b 77
<> 156:95d6b41a828b 78 #define IS_LL_DMA_PERIPHDATASIZE(__VALUE__) (((__VALUE__) == LL_DMA_PDATAALIGN_BYTE) || \
<> 156:95d6b41a828b 79 ((__VALUE__) == LL_DMA_PDATAALIGN_HALFWORD) || \
<> 156:95d6b41a828b 80 ((__VALUE__) == LL_DMA_PDATAALIGN_WORD))
<> 156:95d6b41a828b 81
<> 156:95d6b41a828b 82 #define IS_LL_DMA_MEMORYDATASIZE(__VALUE__) (((__VALUE__) == LL_DMA_MDATAALIGN_BYTE) || \
<> 156:95d6b41a828b 83 ((__VALUE__) == LL_DMA_MDATAALIGN_HALFWORD) || \
<> 156:95d6b41a828b 84 ((__VALUE__) == LL_DMA_MDATAALIGN_WORD))
<> 156:95d6b41a828b 85
<> 156:95d6b41a828b 86 #define IS_LL_DMA_NBDATA(__VALUE__) ((__VALUE__) <= (uint32_t)0x0000FFFFU)
<> 156:95d6b41a828b 87
<> 156:95d6b41a828b 88 #if (defined(DMA1_CSELR_DEFAULT)||defined(DMA2_CSELR_DEFAULT))
<> 156:95d6b41a828b 89 #define IS_LL_DMA_PERIPHREQUEST(__VALUE__) (((__VALUE__) == LL_DMA_REQUEST_0) || \
<> 156:95d6b41a828b 90 ((__VALUE__) == LL_DMA_REQUEST_1) || \
<> 156:95d6b41a828b 91 ((__VALUE__) == LL_DMA_REQUEST_2) || \
<> 156:95d6b41a828b 92 ((__VALUE__) == LL_DMA_REQUEST_3) || \
<> 156:95d6b41a828b 93 ((__VALUE__) == LL_DMA_REQUEST_4) || \
<> 156:95d6b41a828b 94 ((__VALUE__) == LL_DMA_REQUEST_5) || \
<> 156:95d6b41a828b 95 ((__VALUE__) == LL_DMA_REQUEST_6) || \
<> 156:95d6b41a828b 96 ((__VALUE__) == LL_DMA_REQUEST_7) || \
<> 156:95d6b41a828b 97 ((__VALUE__) == LL_DMA_REQUEST_8) || \
<> 156:95d6b41a828b 98 ((__VALUE__) == LL_DMA_REQUEST_9) || \
<> 156:95d6b41a828b 99 ((__VALUE__) == LL_DMA_REQUEST_10) || \
<> 156:95d6b41a828b 100 ((__VALUE__) == LL_DMA_REQUEST_11) || \
<> 156:95d6b41a828b 101 ((__VALUE__) == LL_DMA_REQUEST_12) || \
<> 156:95d6b41a828b 102 ((__VALUE__) == LL_DMA_REQUEST_13) || \
<> 156:95d6b41a828b 103 ((__VALUE__) == LL_DMA_REQUEST_14) || \
<> 156:95d6b41a828b 104 ((__VALUE__) == LL_DMA_REQUEST_15))
<> 156:95d6b41a828b 105 #endif
<> 156:95d6b41a828b 106
<> 156:95d6b41a828b 107 #define IS_LL_DMA_PRIORITY(__VALUE__) (((__VALUE__) == LL_DMA_PRIORITY_LOW) || \
<> 156:95d6b41a828b 108 ((__VALUE__) == LL_DMA_PRIORITY_MEDIUM) || \
<> 156:95d6b41a828b 109 ((__VALUE__) == LL_DMA_PRIORITY_HIGH) || \
<> 156:95d6b41a828b 110 ((__VALUE__) == LL_DMA_PRIORITY_VERYHIGH))
<> 156:95d6b41a828b 111
<> 156:95d6b41a828b 112 #if defined (DMA2)
<> 156:95d6b41a828b 113 #if defined (DMA2_Channel6) && defined (DMA2_Channel7)
<> 156:95d6b41a828b 114 #define IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL) ((((INSTANCE) == DMA1) && \
<> 156:95d6b41a828b 115 (((CHANNEL) == LL_DMA_CHANNEL_1) || \
<> 156:95d6b41a828b 116 ((CHANNEL) == LL_DMA_CHANNEL_2) || \
<> 156:95d6b41a828b 117 ((CHANNEL) == LL_DMA_CHANNEL_3) || \
<> 156:95d6b41a828b 118 ((CHANNEL) == LL_DMA_CHANNEL_4) || \
<> 156:95d6b41a828b 119 ((CHANNEL) == LL_DMA_CHANNEL_5) || \
<> 156:95d6b41a828b 120 ((CHANNEL) == LL_DMA_CHANNEL_6) || \
<> 156:95d6b41a828b 121 ((CHANNEL) == LL_DMA_CHANNEL_7))) || \
<> 156:95d6b41a828b 122 (((INSTANCE) == DMA2) && \
<> 156:95d6b41a828b 123 (((CHANNEL) == LL_DMA_CHANNEL_1) || \
<> 156:95d6b41a828b 124 ((CHANNEL) == LL_DMA_CHANNEL_2) || \
<> 156:95d6b41a828b 125 ((CHANNEL) == LL_DMA_CHANNEL_3) || \
<> 156:95d6b41a828b 126 ((CHANNEL) == LL_DMA_CHANNEL_4) || \
<> 156:95d6b41a828b 127 ((CHANNEL) == LL_DMA_CHANNEL_5) || \
<> 156:95d6b41a828b 128 ((CHANNEL) == LL_DMA_CHANNEL_6) || \
<> 156:95d6b41a828b 129 ((CHANNEL) == LL_DMA_CHANNEL_7))))
<> 156:95d6b41a828b 130 #else
<> 156:95d6b41a828b 131 #define IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL) ((((INSTANCE) == DMA1) && \
<> 156:95d6b41a828b 132 (((CHANNEL) == LL_DMA_CHANNEL_1) || \
<> 156:95d6b41a828b 133 ((CHANNEL) == LL_DMA_CHANNEL_2) || \
<> 156:95d6b41a828b 134 ((CHANNEL) == LL_DMA_CHANNEL_3) || \
<> 156:95d6b41a828b 135 ((CHANNEL) == LL_DMA_CHANNEL_4) || \
<> 156:95d6b41a828b 136 ((CHANNEL) == LL_DMA_CHANNEL_5) || \
<> 156:95d6b41a828b 137 ((CHANNEL) == LL_DMA_CHANNEL_6) || \
<> 156:95d6b41a828b 138 ((CHANNEL) == LL_DMA_CHANNEL_7))) || \
<> 156:95d6b41a828b 139 (((INSTANCE) == DMA2) && \
<> 156:95d6b41a828b 140 (((CHANNEL) == LL_DMA_CHANNEL_1) || \
<> 156:95d6b41a828b 141 ((CHANNEL) == LL_DMA_CHANNEL_2) || \
<> 156:95d6b41a828b 142 ((CHANNEL) == LL_DMA_CHANNEL_3) || \
<> 156:95d6b41a828b 143 ((CHANNEL) == LL_DMA_CHANNEL_4) || \
<> 156:95d6b41a828b 144 ((CHANNEL) == LL_DMA_CHANNEL_5))))
<> 156:95d6b41a828b 145 #endif
<> 156:95d6b41a828b 146 #else
<> 156:95d6b41a828b 147 #if defined(DMA1_Channel6) && defined(DMA1_Channel7)
<> 156:95d6b41a828b 148 #define IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL) ((((INSTANCE) == DMA1) && \
<> 156:95d6b41a828b 149 (((CHANNEL) == LL_DMA_CHANNEL_1)|| \
<> 156:95d6b41a828b 150 ((CHANNEL) == LL_DMA_CHANNEL_2) || \
<> 156:95d6b41a828b 151 ((CHANNEL) == LL_DMA_CHANNEL_3) || \
<> 156:95d6b41a828b 152 ((CHANNEL) == LL_DMA_CHANNEL_4) || \
<> 156:95d6b41a828b 153 ((CHANNEL) == LL_DMA_CHANNEL_5) || \
<> 156:95d6b41a828b 154 ((CHANNEL) == LL_DMA_CHANNEL_6) || \
<> 156:95d6b41a828b 155 ((CHANNEL) == LL_DMA_CHANNEL_7))))
<> 156:95d6b41a828b 156 #elif defined (DMA1_Channel6)
<> 156:95d6b41a828b 157 #define IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL) ((((INSTANCE) == DMA1) && \
<> 156:95d6b41a828b 158 (((CHANNEL) == LL_DMA_CHANNEL_1)|| \
<> 156:95d6b41a828b 159 ((CHANNEL) == LL_DMA_CHANNEL_2) || \
<> 156:95d6b41a828b 160 ((CHANNEL) == LL_DMA_CHANNEL_3) || \
<> 156:95d6b41a828b 161 ((CHANNEL) == LL_DMA_CHANNEL_4) || \
<> 156:95d6b41a828b 162 ((CHANNEL) == LL_DMA_CHANNEL_5) || \
<> 156:95d6b41a828b 163 ((CHANNEL) == LL_DMA_CHANNEL_6))))
<> 156:95d6b41a828b 164 #else
<> 156:95d6b41a828b 165 #define IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL) ((((INSTANCE) == DMA1) && \
<> 156:95d6b41a828b 166 (((CHANNEL) == LL_DMA_CHANNEL_1)|| \
<> 156:95d6b41a828b 167 ((CHANNEL) == LL_DMA_CHANNEL_2) || \
<> 156:95d6b41a828b 168 ((CHANNEL) == LL_DMA_CHANNEL_3) || \
<> 156:95d6b41a828b 169 ((CHANNEL) == LL_DMA_CHANNEL_4) || \
<> 156:95d6b41a828b 170 ((CHANNEL) == LL_DMA_CHANNEL_5))))
<> 156:95d6b41a828b 171 #endif /* DMA1_Channel6 && DMA1_Channel7 */
<> 156:95d6b41a828b 172 #endif
<> 156:95d6b41a828b 173 /**
<> 156:95d6b41a828b 174 * @}
<> 156:95d6b41a828b 175 */
<> 156:95d6b41a828b 176
<> 156:95d6b41a828b 177 /* Private function prototypes -----------------------------------------------*/
<> 156:95d6b41a828b 178
<> 156:95d6b41a828b 179 /* Exported functions --------------------------------------------------------*/
<> 156:95d6b41a828b 180 /** @addtogroup DMA_LL_Exported_Functions
<> 156:95d6b41a828b 181 * @{
<> 156:95d6b41a828b 182 */
<> 156:95d6b41a828b 183
<> 156:95d6b41a828b 184 /** @addtogroup DMA_LL_EF_Init
<> 156:95d6b41a828b 185 * @{
<> 156:95d6b41a828b 186 */
<> 156:95d6b41a828b 187
<> 156:95d6b41a828b 188 /**
<> 156:95d6b41a828b 189 * @brief De-initialize the DMA registers to their default reset values.
<> 156:95d6b41a828b 190 * @param DMAx DMAx Instance
<> 156:95d6b41a828b 191 * @param Channel This parameter can be one of the following values:
<> 156:95d6b41a828b 192 * @arg @ref LL_DMA_CHANNEL_1
<> 156:95d6b41a828b 193 * @arg @ref LL_DMA_CHANNEL_2
<> 156:95d6b41a828b 194 * @arg @ref LL_DMA_CHANNEL_3
<> 156:95d6b41a828b 195 * @arg @ref LL_DMA_CHANNEL_4
<> 156:95d6b41a828b 196 * @arg @ref LL_DMA_CHANNEL_5
<> 156:95d6b41a828b 197 * @arg @ref LL_DMA_CHANNEL_6 (*)
<> 156:95d6b41a828b 198 * @arg @ref LL_DMA_CHANNEL_7 (*)
<> 156:95d6b41a828b 199 *
<> 156:95d6b41a828b 200 * (*) value not defined in all devices
<> 156:95d6b41a828b 201 * @retval An ErrorStatus enumeration value:
<> 156:95d6b41a828b 202 * - SUCCESS: DMA registers are de-initialized
<> 156:95d6b41a828b 203 * - ERROR: DMA registers are not de-initialized
<> 156:95d6b41a828b 204 */
<> 156:95d6b41a828b 205 uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel)
<> 156:95d6b41a828b 206 {
<> 156:95d6b41a828b 207 DMA_Channel_TypeDef *tmp = (DMA_Channel_TypeDef *)DMA1_Channel1;
<> 156:95d6b41a828b 208 ErrorStatus status = SUCCESS;
<> 156:95d6b41a828b 209
<> 156:95d6b41a828b 210 /* Check the DMA Instance DMAx and Channel parameters*/
<> 156:95d6b41a828b 211 assert_param(IS_LL_DMA_ALL_CHANNEL_INSTANCE(DMAx, Channel));
<> 156:95d6b41a828b 212
<> 156:95d6b41a828b 213 tmp = (DMA_Channel_TypeDef *)(__LL_DMA_GET_CHANNEL_INSTANCE(DMAx, Channel));
<> 156:95d6b41a828b 214
<> 156:95d6b41a828b 215 /* Disable the selected DMAx_Channely */
<> 156:95d6b41a828b 216 CLEAR_BIT(tmp->CCR, DMA_CCR_EN);
<> 156:95d6b41a828b 217
<> 156:95d6b41a828b 218 /* Reset DMAx_Channely control register */
<> 156:95d6b41a828b 219 LL_DMA_WriteReg(tmp, CCR, 0U);
<> 156:95d6b41a828b 220
<> 156:95d6b41a828b 221 /* Reset DMAx_Channely remaining bytes register */
<> 156:95d6b41a828b 222 LL_DMA_WriteReg(tmp, CNDTR, 0U);
<> 156:95d6b41a828b 223
<> 156:95d6b41a828b 224 /* Reset DMAx_Channely peripheral address register */
<> 156:95d6b41a828b 225 LL_DMA_WriteReg(tmp, CPAR, 0U);
<> 156:95d6b41a828b 226
<> 156:95d6b41a828b 227 /* Reset DMAx_Channely memory address register */
<> 156:95d6b41a828b 228 LL_DMA_WriteReg(tmp, CMAR, 0U);
<> 156:95d6b41a828b 229
<> 156:95d6b41a828b 230 #if (defined(DMA1_CSELR_DEFAULT)||defined(DMA2_CSELR_DEFAULT))
<> 156:95d6b41a828b 231 /* Reset Request register field for DMAx Channel */
<> 156:95d6b41a828b 232 LL_DMA_SetPeriphRequest(DMAx, Channel, LL_DMA_REQUEST_0);
<> 156:95d6b41a828b 233 #endif
<> 156:95d6b41a828b 234
<> 156:95d6b41a828b 235 if (Channel == LL_DMA_CHANNEL_1)
<> 156:95d6b41a828b 236 {
<> 156:95d6b41a828b 237 /* Reset interrupt pending bits for DMAx Channel1 */
<> 156:95d6b41a828b 238 LL_DMA_ClearFlag_GI1(DMAx);
<> 156:95d6b41a828b 239 }
<> 156:95d6b41a828b 240 else if (Channel == LL_DMA_CHANNEL_2)
<> 156:95d6b41a828b 241 {
<> 156:95d6b41a828b 242 /* Reset interrupt pending bits for DMAx Channel2 */
<> 156:95d6b41a828b 243 LL_DMA_ClearFlag_GI2(DMAx);
<> 156:95d6b41a828b 244 }
<> 156:95d6b41a828b 245 else if (Channel == LL_DMA_CHANNEL_3)
<> 156:95d6b41a828b 246 {
<> 156:95d6b41a828b 247 /* Reset interrupt pending bits for DMAx Channel3 */
<> 156:95d6b41a828b 248 LL_DMA_ClearFlag_GI3(DMAx);
<> 156:95d6b41a828b 249 }
<> 156:95d6b41a828b 250 else if (Channel == LL_DMA_CHANNEL_4)
<> 156:95d6b41a828b 251 {
<> 156:95d6b41a828b 252 /* Reset interrupt pending bits for DMAx Channel4 */
<> 156:95d6b41a828b 253 LL_DMA_ClearFlag_GI4(DMAx);
<> 156:95d6b41a828b 254 }
<> 156:95d6b41a828b 255 else if (Channel == LL_DMA_CHANNEL_5)
<> 156:95d6b41a828b 256 {
<> 156:95d6b41a828b 257 /* Reset interrupt pending bits for DMAx Channel5 */
<> 156:95d6b41a828b 258 LL_DMA_ClearFlag_GI5(DMAx);
<> 156:95d6b41a828b 259 }
<> 156:95d6b41a828b 260
<> 156:95d6b41a828b 261 #if defined(DMA1_Channel6)
<> 156:95d6b41a828b 262 else if (Channel == LL_DMA_CHANNEL_6)
<> 156:95d6b41a828b 263 {
<> 156:95d6b41a828b 264 /* Reset interrupt pending bits for DMAx Channel6 */
<> 156:95d6b41a828b 265 LL_DMA_ClearFlag_GI6(DMAx);
<> 156:95d6b41a828b 266 }
<> 156:95d6b41a828b 267 #endif
<> 156:95d6b41a828b 268 #if defined(DMA1_Channel7)
<> 156:95d6b41a828b 269 else if (Channel == LL_DMA_CHANNEL_7)
<> 156:95d6b41a828b 270 {
<> 156:95d6b41a828b 271 /* Reset interrupt pending bits for DMAx Channel7 */
<> 156:95d6b41a828b 272 LL_DMA_ClearFlag_GI7(DMAx);
<> 156:95d6b41a828b 273 }
<> 156:95d6b41a828b 274 #endif
<> 156:95d6b41a828b 275 else
<> 156:95d6b41a828b 276 {
<> 156:95d6b41a828b 277 status = ERROR;
<> 156:95d6b41a828b 278 }
<> 156:95d6b41a828b 279
<> 156:95d6b41a828b 280 return status;
<> 156:95d6b41a828b 281 }
<> 156:95d6b41a828b 282
<> 156:95d6b41a828b 283 /**
<> 156:95d6b41a828b 284 * @brief Initialize the DMA registers according to the specified parameters in DMA_InitStruct.
<> 156:95d6b41a828b 285 * @note To convert DMAx_Channely Instance to DMAx Instance and Channely, use helper macros :
<> 156:95d6b41a828b 286 * @arg @ref __LL_DMA_GET_INSTANCE
<> 156:95d6b41a828b 287 * @arg @ref __LL_DMA_GET_CHANNEL
<> 156:95d6b41a828b 288 * @param DMAx DMAx Instance
<> 156:95d6b41a828b 289 * @param Channel This parameter can be one of the following values:
<> 156:95d6b41a828b 290 * @arg @ref LL_DMA_CHANNEL_1
<> 156:95d6b41a828b 291 * @arg @ref LL_DMA_CHANNEL_2
<> 156:95d6b41a828b 292 * @arg @ref LL_DMA_CHANNEL_3
<> 156:95d6b41a828b 293 * @arg @ref LL_DMA_CHANNEL_4
<> 156:95d6b41a828b 294 * @arg @ref LL_DMA_CHANNEL_5
<> 156:95d6b41a828b 295 * @arg @ref LL_DMA_CHANNEL_6 (*)
<> 156:95d6b41a828b 296 * @arg @ref LL_DMA_CHANNEL_7 (*)
<> 156:95d6b41a828b 297 *
<> 156:95d6b41a828b 298 * (*) value not defined in all devices
<> 156:95d6b41a828b 299 * @param DMA_InitStruct pointer to a @ref LL_DMA_InitTypeDef structure.
<> 156:95d6b41a828b 300 * @retval An ErrorStatus enumeration value:
<> 156:95d6b41a828b 301 * - SUCCESS: DMA registers are initialized
<> 156:95d6b41a828b 302 * - ERROR: Not applicable
<> 156:95d6b41a828b 303 */
<> 156:95d6b41a828b 304 uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DMA_InitStruct)
<> 156:95d6b41a828b 305 {
<> 156:95d6b41a828b 306 /* Check the DMA Instance DMAx and Channel parameters*/
<> 156:95d6b41a828b 307 assert_param(IS_LL_DMA_ALL_CHANNEL_INSTANCE(DMAx, Channel));
<> 156:95d6b41a828b 308
<> 156:95d6b41a828b 309 /* Check the DMA parameters from DMA_InitStruct */
<> 156:95d6b41a828b 310 assert_param(IS_LL_DMA_DIRECTION(DMA_InitStruct->Direction));
<> 156:95d6b41a828b 311 assert_param(IS_LL_DMA_MODE(DMA_InitStruct->Mode));
<> 156:95d6b41a828b 312 assert_param(IS_LL_DMA_PERIPHINCMODE(DMA_InitStruct->PeriphOrM2MSrcIncMode));
<> 156:95d6b41a828b 313 assert_param(IS_LL_DMA_MEMORYINCMODE(DMA_InitStruct->MemoryOrM2MDstIncMode));
<> 156:95d6b41a828b 314 assert_param(IS_LL_DMA_PERIPHDATASIZE(DMA_InitStruct->PeriphOrM2MSrcDataSize));
<> 156:95d6b41a828b 315 assert_param(IS_LL_DMA_MEMORYDATASIZE(DMA_InitStruct->MemoryOrM2MDstDataSize));
<> 156:95d6b41a828b 316 assert_param(IS_LL_DMA_NBDATA(DMA_InitStruct->NbData));
<> 156:95d6b41a828b 317 #if (defined(DMA1_CSELR_DEFAULT)||defined(DMA2_CSELR_DEFAULT))
<> 156:95d6b41a828b 318 assert_param(IS_LL_DMA_PERIPHREQUEST(DMA_InitStruct->PeriphRequest));
<> 156:95d6b41a828b 319 #endif
<> 156:95d6b41a828b 320 assert_param(IS_LL_DMA_PRIORITY(DMA_InitStruct->Priority));
<> 156:95d6b41a828b 321
<> 156:95d6b41a828b 322 /*---------------------------- DMAx CCR Configuration ------------------------
<> 156:95d6b41a828b 323 * Configure DMAx_Channely: data transfer direction, data transfer mode,
<> 156:95d6b41a828b 324 * peripheral and memory increment mode,
<> 156:95d6b41a828b 325 * data size alignment and priority level with parameters :
<> 156:95d6b41a828b 326 * - Direction: DMA_CCR_DIR and DMA_CCR_MEM2MEM bits
<> 156:95d6b41a828b 327 * - Mode: DMA_CCR_CIRC bit
<> 156:95d6b41a828b 328 * - PeriphOrM2MSrcIncMode: DMA_CCR_PINC bit
<> 156:95d6b41a828b 329 * - MemoryOrM2MDstIncMode: DMA_CCR_MINC bit
<> 156:95d6b41a828b 330 * - PeriphOrM2MSrcDataSize: DMA_CCR_PSIZE[1:0] bits
<> 156:95d6b41a828b 331 * - MemoryOrM2MDstDataSize: DMA_CCR_MSIZE[1:0] bits
<> 156:95d6b41a828b 332 * - Priority: DMA_CCR_PL[1:0] bits
<> 156:95d6b41a828b 333 */
<> 156:95d6b41a828b 334 LL_DMA_ConfigTransfer(DMAx, Channel, DMA_InitStruct->Direction | \
<> 156:95d6b41a828b 335 DMA_InitStruct->Mode | \
<> 156:95d6b41a828b 336 DMA_InitStruct->PeriphOrM2MSrcIncMode | \
<> 156:95d6b41a828b 337 DMA_InitStruct->MemoryOrM2MDstIncMode | \
<> 156:95d6b41a828b 338 DMA_InitStruct->PeriphOrM2MSrcDataSize | \
<> 156:95d6b41a828b 339 DMA_InitStruct->MemoryOrM2MDstDataSize | \
<> 156:95d6b41a828b 340 DMA_InitStruct->Priority);
<> 156:95d6b41a828b 341
<> 156:95d6b41a828b 342 /*-------------------------- DMAx CMAR Configuration -------------------------
<> 156:95d6b41a828b 343 * Configure the memory or destination base address with parameter :
<> 156:95d6b41a828b 344 * - MemoryOrM2MDstAddress: DMA_CMAR_MA[31:0] bits
<> 156:95d6b41a828b 345 */
<> 156:95d6b41a828b 346 LL_DMA_SetMemoryAddress(DMAx, Channel, DMA_InitStruct->MemoryOrM2MDstAddress);
<> 156:95d6b41a828b 347
<> 156:95d6b41a828b 348 /*-------------------------- DMAx CPAR Configuration -------------------------
<> 156:95d6b41a828b 349 * Configure the peripheral or source base address with parameter :
<> 156:95d6b41a828b 350 * - PeriphOrM2MSrcAddress: DMA_CPAR_PA[31:0] bits
<> 156:95d6b41a828b 351 */
<> 156:95d6b41a828b 352 LL_DMA_SetPeriphAddress(DMAx, Channel, DMA_InitStruct->PeriphOrM2MSrcAddress);
<> 156:95d6b41a828b 353
<> 156:95d6b41a828b 354 /*--------------------------- DMAx CNDTR Configuration -----------------------
<> 156:95d6b41a828b 355 * Configure the peripheral base address with parameter :
<> 156:95d6b41a828b 356 * - NbData: DMA_CNDTR_NDT[15:0] bits
<> 156:95d6b41a828b 357 */
<> 156:95d6b41a828b 358 LL_DMA_SetDataLength(DMAx, Channel, DMA_InitStruct->NbData);
<> 156:95d6b41a828b 359
<> 156:95d6b41a828b 360 #if (defined(DMA1_CSELR_DEFAULT)||defined(DMA2_CSELR_DEFAULT))
<> 156:95d6b41a828b 361 /*--------------------------- DMAx CSELR Configuration -----------------------
<> 156:95d6b41a828b 362 * Configure the peripheral base address with parameter :
<> 156:95d6b41a828b 363 * - PeriphRequest: DMA_CSELR[31:0] bits
<> 156:95d6b41a828b 364 */
<> 156:95d6b41a828b 365 LL_DMA_SetPeriphRequest(DMAx, Channel, DMA_InitStruct->PeriphRequest);
<> 156:95d6b41a828b 366 #endif
<> 156:95d6b41a828b 367
<> 156:95d6b41a828b 368 return SUCCESS;
<> 156:95d6b41a828b 369 }
<> 156:95d6b41a828b 370
<> 156:95d6b41a828b 371 /**
<> 156:95d6b41a828b 372 * @brief Set each @ref LL_DMA_InitTypeDef field to default value.
<> 156:95d6b41a828b 373 * @param DMA_InitStruct Pointer to a @ref LL_DMA_InitTypeDef structure.
<> 156:95d6b41a828b 374 * @retval None
<> 156:95d6b41a828b 375 */
<> 156:95d6b41a828b 376 void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct)
<> 156:95d6b41a828b 377 {
<> 156:95d6b41a828b 378 /* Set DMA_InitStruct fields to default values */
<> 156:95d6b41a828b 379 DMA_InitStruct->PeriphOrM2MSrcAddress = (uint32_t)0x00000000U;
<> 156:95d6b41a828b 380 DMA_InitStruct->MemoryOrM2MDstAddress = (uint32_t)0x00000000U;
<> 156:95d6b41a828b 381 DMA_InitStruct->Direction = LL_DMA_DIRECTION_PERIPH_TO_MEMORY;
<> 156:95d6b41a828b 382 DMA_InitStruct->Mode = LL_DMA_MODE_NORMAL;
<> 156:95d6b41a828b 383 DMA_InitStruct->PeriphOrM2MSrcIncMode = LL_DMA_PERIPH_NOINCREMENT;
<> 156:95d6b41a828b 384 DMA_InitStruct->MemoryOrM2MDstIncMode = LL_DMA_MEMORY_NOINCREMENT;
<> 156:95d6b41a828b 385 DMA_InitStruct->PeriphOrM2MSrcDataSize = LL_DMA_PDATAALIGN_BYTE;
<> 156:95d6b41a828b 386 DMA_InitStruct->MemoryOrM2MDstDataSize = LL_DMA_MDATAALIGN_BYTE;
<> 156:95d6b41a828b 387 DMA_InitStruct->NbData = (uint32_t)0x00000000U;
<> 156:95d6b41a828b 388 #if (defined(DMA1_CSELR_DEFAULT)||defined(DMA2_CSELR_DEFAULT))
<> 156:95d6b41a828b 389 DMA_InitStruct->PeriphRequest = LL_DMA_REQUEST_0;
<> 156:95d6b41a828b 390 #endif
<> 156:95d6b41a828b 391 DMA_InitStruct->Priority = LL_DMA_PRIORITY_LOW;
<> 156:95d6b41a828b 392 }
<> 156:95d6b41a828b 393
<> 156:95d6b41a828b 394 /**
<> 156:95d6b41a828b 395 * @}
<> 156:95d6b41a828b 396 */
<> 156:95d6b41a828b 397
<> 156:95d6b41a828b 398 /**
<> 156:95d6b41a828b 399 * @}
<> 156:95d6b41a828b 400 */
<> 156:95d6b41a828b 401
<> 156:95d6b41a828b 402 /**
<> 156:95d6b41a828b 403 * @}
<> 156:95d6b41a828b 404 */
<> 156:95d6b41a828b 405
<> 156:95d6b41a828b 406 #endif /* DMA1 || DMA2 */
<> 156:95d6b41a828b 407
<> 156:95d6b41a828b 408 /**
<> 156:95d6b41a828b 409 * @}
<> 156:95d6b41a828b 410 */
<> 156:95d6b41a828b 411
<> 156:95d6b41a828b 412 #endif /* USE_FULL_LL_DRIVER */
<> 156:95d6b41a828b 413
<> 156:95d6b41a828b 414 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/