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mbed library sources. Supersedes mbed-src.

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targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_iwdg.c@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
Parent:
180:96ed750bd169 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f0xx_hal_iwdg.c
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @brief IWDG HAL module driver.
<> 144:ef7eb2e8f9f7 6 * This file provides firmware functions to manage the following
<> 144:ef7eb2e8f9f7 7 * functionalities of the Independent Watchdog (IWDG) peripheral:
<> 156:95d6b41a828b 8 * + Initialization and Start functions
<> 144:ef7eb2e8f9f7 9 * + IO operation functions
<> 156:95d6b41a828b 10 *
<> 144:ef7eb2e8f9f7 11 @verbatim
<> 156:95d6b41a828b 12 ==============================================================================
<> 156:95d6b41a828b 13 ##### IWDG Generic features #####
<> 156:95d6b41a828b 14 ==============================================================================
<> 156:95d6b41a828b 15 [..]
<> 156:95d6b41a828b 16 (+) The IWDG can be started by either software or hardware (configurable
<> 156:95d6b41a828b 17 through option byte).
<> 156:95d6b41a828b 18
<> 156:95d6b41a828b 19 (+) The IWDG is clocked by Low-Speed clock (LSI) and thus stays active even
<> 156:95d6b41a828b 20 if the main clock fails.
<> 156:95d6b41a828b 21
<> 156:95d6b41a828b 22 (+) Once the IWDG is started, the LSI is forced ON and both can not be
<> 156:95d6b41a828b 23 disabled. The counter starts counting down from the reset value (0xFFF).
<> 156:95d6b41a828b 24 When it reaches the end of count value (0x000) a reset signal is
<> 156:95d6b41a828b 25 generated (IWDG reset).
<> 156:95d6b41a828b 26
<> 156:95d6b41a828b 27 (+) Whenever the key value 0x0000 AAAA is written in the IWDG_KR register,
<> 156:95d6b41a828b 28 the IWDG_RLR value is reloaded in the counter and the watchdog reset is
<> 156:95d6b41a828b 29 prevented.
<> 156:95d6b41a828b 30
<> 156:95d6b41a828b 31 (+) The IWDG is implemented in the VDD voltage domain that is still functional
<> 156:95d6b41a828b 32 in STOP and STANDBY mode (IWDG reset can wake-up from STANDBY).
<> 156:95d6b41a828b 33 IWDGRST flag in RCC_CSR register can be used to inform when an IWDG
<> 156:95d6b41a828b 34 reset occurs.
<> 156:95d6b41a828b 35
<> 156:95d6b41a828b 36 (+) Debug mode : When the microcontroller enters debug mode (core halted),
<> 156:95d6b41a828b 37 the IWDG counter either continues to work normally or stops, depending
<> 156:95d6b41a828b 38 on DBG_IWDG_STOP configuration bit in DBG module, accessible through
<> 156:95d6b41a828b 39 __HAL_DBGMCU_FREEZE_IWDG() and __HAL_DBGMCU_UNFREEZE_IWDG() macros
<> 144:ef7eb2e8f9f7 40
<> 156:95d6b41a828b 41 [..] Min-max timeout value @40KHz (LSI): ~0.1ms / ~26.2s
<> 156:95d6b41a828b 42 The IWDG timeout may vary due to LSI frequency dispersion. STM32F0xx
<> 156:95d6b41a828b 43 devices provide the capability to measure the LSI frequency (LSI clock
<> 156:95d6b41a828b 44 connected internally to TIM16 CH1 input capture). The measured value
<> 156:95d6b41a828b 45 can be used to have an IWDG timeout with an acceptable accuracy.
<> 156:95d6b41a828b 46
<> 156:95d6b41a828b 47 ##### How to use this driver #####
<> 156:95d6b41a828b 48 ==============================================================================
<> 156:95d6b41a828b 49 [..]
<> 156:95d6b41a828b 50 (#) Use IWDG using HAL_IWDG_Init() function to :
<> 156:95d6b41a828b 51 (++) Enable instance by writing Start keyword in IWDG_KEY register. LSI
<> 156:95d6b41a828b 52 clock is forced ON and IWDG counter starts downcounting.
<> 156:95d6b41a828b 53 (++) Enable write access to configuration register: IWDG_PR, IWDG_RLR &
<> 156:95d6b41a828b 54 IWDG_WINR.
<> 156:95d6b41a828b 55 (++) Configure the IWDG prescaler and counter reload value. This reload
<> 156:95d6b41a828b 56 value will be loaded in the IWDG counter each time the watchdog is
<> 156:95d6b41a828b 57 reloaded, then the IWDG will start counting down from this value.
<> 156:95d6b41a828b 58 (++) wait for status flags to be reset"
<> 156:95d6b41a828b 59 (++) Depending on window parameter:
<> 156:95d6b41a828b 60 (+++) If Window Init parameter is same as Window register value,
<> 156:95d6b41a828b 61 nothing more is done but reload counter value in order to exit
<> 156:95d6b41a828b 62 function withy exact time base.
<> 156:95d6b41a828b 63 (+++) Else modify Window register. This will automatically reload
<> 156:95d6b41a828b 64 watchdog counter.
<> 156:95d6b41a828b 65
<> 156:95d6b41a828b 66 (#) Then the application program must refresh the IWDG counter at regular
<> 156:95d6b41a828b 67 intervals during normal operation to prevent an MCU reset, using
<> 156:95d6b41a828b 68 HAL_IWDG_Refresh() function.
<> 144:ef7eb2e8f9f7 69
<> 144:ef7eb2e8f9f7 70 *** IWDG HAL driver macros list ***
<> 144:ef7eb2e8f9f7 71 ====================================
<> 144:ef7eb2e8f9f7 72 [..]
<> 156:95d6b41a828b 73 Below the list of most used macros in IWDG HAL driver:
<> 144:ef7eb2e8f9f7 74 (+) __HAL_IWDG_START: Enable the IWDG peripheral
<> 156:95d6b41a828b 75 (+) __HAL_IWDG_RELOAD_COUNTER: Reloads IWDG counter with value defined in
<> 156:95d6b41a828b 76 the reload register
<> 144:ef7eb2e8f9f7 77
<> 144:ef7eb2e8f9f7 78 @endverbatim
<> 144:ef7eb2e8f9f7 79 ******************************************************************************
<> 144:ef7eb2e8f9f7 80 * @attention
<> 144:ef7eb2e8f9f7 81 *
<> 144:ef7eb2e8f9f7 82 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 83 *
<> 144:ef7eb2e8f9f7 84 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 85 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 86 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 87 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 88 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 89 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 90 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 91 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 92 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 93 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 94 *
<> 144:ef7eb2e8f9f7 95 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 96 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 97 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 98 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 99 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 100 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 101 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 102 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 103 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 104 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 105 *
<> 144:ef7eb2e8f9f7 106 ******************************************************************************
<> 144:ef7eb2e8f9f7 107 */
<> 144:ef7eb2e8f9f7 108
<> 144:ef7eb2e8f9f7 109 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 110 #include "stm32f0xx_hal.h"
<> 144:ef7eb2e8f9f7 111
<> 144:ef7eb2e8f9f7 112 /** @addtogroup STM32F0xx_HAL_Driver
<> 144:ef7eb2e8f9f7 113 * @{
<> 144:ef7eb2e8f9f7 114 */
<> 144:ef7eb2e8f9f7 115
<> 156:95d6b41a828b 116 #ifdef HAL_IWDG_MODULE_ENABLED
<> 156:95d6b41a828b 117 /** @addtogroup IWDG
<> 144:ef7eb2e8f9f7 118 * @brief IWDG HAL module driver.
<> 144:ef7eb2e8f9f7 119 * @{
<> 144:ef7eb2e8f9f7 120 */
<> 144:ef7eb2e8f9f7 121
<> 144:ef7eb2e8f9f7 122 /* Private typedef -----------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 123 /* Private define ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 124 /** @defgroup IWDG_Private_Defines IWDG Private Defines
<> 144:ef7eb2e8f9f7 125 * @{
<> 144:ef7eb2e8f9f7 126 */
<> 156:95d6b41a828b 127 /* Status register need 5 RC LSI divided by prescaler clock to be updated. With
<> 156:95d6b41a828b 128 higher prescaler (256), and according to LSI variation, we need to wait at
<> 156:95d6b41a828b 129 least 6 cycles so 39 ms. */
<> 156:95d6b41a828b 130 #define HAL_IWDG_DEFAULT_TIMEOUT 39U
<> 144:ef7eb2e8f9f7 131 /**
<> 144:ef7eb2e8f9f7 132 * @}
<> 144:ef7eb2e8f9f7 133 */
<> 156:95d6b41a828b 134
<> 144:ef7eb2e8f9f7 135 /* Private macro -------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 136 /* Private variables ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 137 /* Private function prototypes -----------------------------------------------*/
<> 144:ef7eb2e8f9f7 138 /* Exported functions --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 139
<> 156:95d6b41a828b 140 /** @addtogroup IWDG_Exported_Functions
<> 144:ef7eb2e8f9f7 141 * @{
<> 144:ef7eb2e8f9f7 142 */
<> 144:ef7eb2e8f9f7 143
<> 156:95d6b41a828b 144 /** @addtogroup IWDG_Exported_Functions_Group1
<> 156:95d6b41a828b 145 * @brief Initialization and Start functions.
<> 144:ef7eb2e8f9f7 146 *
<> 144:ef7eb2e8f9f7 147 @verbatim
<> 144:ef7eb2e8f9f7 148 ===============================================================================
<> 156:95d6b41a828b 149 ##### Initialization and Start functions #####
<> 144:ef7eb2e8f9f7 150 ===============================================================================
<> 156:95d6b41a828b 151 [..] This section provides functions allowing to:
<> 156:95d6b41a828b 152 (+) Initialize the IWDG according to the specified parameters in the
<> 156:95d6b41a828b 153 IWDG_InitTypeDef of associated handle.
<> 156:95d6b41a828b 154 (+) Manage Window option.
<> 156:95d6b41a828b 155 (+) Once initialization is performed in HAL_IWDG_Init function, Watchdog
<> 156:95d6b41a828b 156 is reloaded in order to exit function with correct time base.
<> 144:ef7eb2e8f9f7 157
<> 144:ef7eb2e8f9f7 158 @endverbatim
<> 144:ef7eb2e8f9f7 159 * @{
<> 144:ef7eb2e8f9f7 160 */
<> 144:ef7eb2e8f9f7 161
<> 144:ef7eb2e8f9f7 162 /**
<> 156:95d6b41a828b 163 * @brief Initialize the IWDG according to the specified parameters in the
<> 156:95d6b41a828b 164 * IWDG_InitTypeDef and start watchdog. Before exiting function,
<> 156:95d6b41a828b 165 * watchdog is refreshed in order to have correct time base.
<> 156:95d6b41a828b 166 * @param hiwdg pointer to a IWDG_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 167 * the configuration information for the specified IWDG module.
<> 144:ef7eb2e8f9f7 168 * @retval HAL status
<> 144:ef7eb2e8f9f7 169 */
<> 144:ef7eb2e8f9f7 170 HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg)
<> 144:ef7eb2e8f9f7 171 {
<> 156:95d6b41a828b 172 uint32_t tickstart;
<> 144:ef7eb2e8f9f7 173
<> 144:ef7eb2e8f9f7 174 /* Check the IWDG handle allocation */
<> 144:ef7eb2e8f9f7 175 if(hiwdg == NULL)
<> 144:ef7eb2e8f9f7 176 {
<> 144:ef7eb2e8f9f7 177 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 178 }
<> 144:ef7eb2e8f9f7 179
<> 144:ef7eb2e8f9f7 180 /* Check the parameters */
<> 144:ef7eb2e8f9f7 181 assert_param(IS_IWDG_ALL_INSTANCE(hiwdg->Instance));
<> 144:ef7eb2e8f9f7 182 assert_param(IS_IWDG_PRESCALER(hiwdg->Init.Prescaler));
<> 144:ef7eb2e8f9f7 183 assert_param(IS_IWDG_RELOAD(hiwdg->Init.Reload));
<> 144:ef7eb2e8f9f7 184 assert_param(IS_IWDG_WINDOW(hiwdg->Init.Window));
<> 144:ef7eb2e8f9f7 185
<> 156:95d6b41a828b 186 /* Enable IWDG. LSI is turned on automaticaly */
<> 156:95d6b41a828b 187 __HAL_IWDG_START(hiwdg);
<> 144:ef7eb2e8f9f7 188
<> 156:95d6b41a828b 189 /* Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers by writing
<> 156:95d6b41a828b 190 0x5555 in KR */
<> 144:ef7eb2e8f9f7 191 IWDG_ENABLE_WRITE_ACCESS(hiwdg);
<> 144:ef7eb2e8f9f7 192
<> 156:95d6b41a828b 193 /* Write to IWDG registers the Prescaler & Reload values to work with */
<> 156:95d6b41a828b 194 hiwdg->Instance->PR = hiwdg->Init.Prescaler;
<> 156:95d6b41a828b 195 hiwdg->Instance->RLR = hiwdg->Init.Reload;
<> 144:ef7eb2e8f9f7 196
<> 156:95d6b41a828b 197 /* Check pending flag, if previous update not done, return timeout */
<> 144:ef7eb2e8f9f7 198 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 199
<> 156:95d6b41a828b 200 /* Wait for register to be updated */
<> 156:95d6b41a828b 201 while(hiwdg->Instance->SR != RESET)
<> 144:ef7eb2e8f9f7 202 {
<> 144:ef7eb2e8f9f7 203 if((HAL_GetTick() - tickstart ) > HAL_IWDG_DEFAULT_TIMEOUT)
<> 144:ef7eb2e8f9f7 204 {
<> 144:ef7eb2e8f9f7 205 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 206 }
<> 144:ef7eb2e8f9f7 207 }
<> 144:ef7eb2e8f9f7 208
<> 156:95d6b41a828b 209 /* If window parameter is different than current value, modify window
<> 156:95d6b41a828b 210 register */
<> 156:95d6b41a828b 211 if(hiwdg->Instance->WINR != hiwdg->Init.Window)
<> 144:ef7eb2e8f9f7 212 {
<> 156:95d6b41a828b 213 /* Write to IWDG WINR the IWDG_Window value to compare with. In any case,
<> 156:95d6b41a828b 214 even if window feature is disabled, Watchdog will be reloaded by writing
<> 156:95d6b41a828b 215 windows register */
<> 156:95d6b41a828b 216 hiwdg->Instance->WINR = hiwdg->Init.Window;
<> 144:ef7eb2e8f9f7 217 }
<> 156:95d6b41a828b 218 else
<> 156:95d6b41a828b 219 {
<> 156:95d6b41a828b 220 /* Reload IWDG counter with value defined in the reload register */
<> 156:95d6b41a828b 221 __HAL_IWDG_RELOAD_COUNTER(hiwdg);
<> 156:95d6b41a828b 222 }
<> 144:ef7eb2e8f9f7 223
<> 144:ef7eb2e8f9f7 224 /* Return function status */
<> 144:ef7eb2e8f9f7 225 return HAL_OK;
<> 144:ef7eb2e8f9f7 226 }
<> 144:ef7eb2e8f9f7 227
<> 144:ef7eb2e8f9f7 228 /**
<> 144:ef7eb2e8f9f7 229 * @}
<> 144:ef7eb2e8f9f7 230 */
<> 144:ef7eb2e8f9f7 231
<> 156:95d6b41a828b 232
<> 156:95d6b41a828b 233 /** @addtogroup IWDG_Exported_Functions_Group2
<> 156:95d6b41a828b 234 * @brief IO operation functions
<> 144:ef7eb2e8f9f7 235 *
<> 144:ef7eb2e8f9f7 236 @verbatim
<> 144:ef7eb2e8f9f7 237 ===============================================================================
<> 156:95d6b41a828b 238 ##### IO operation functions #####
<> 144:ef7eb2e8f9f7 239 ===============================================================================
<> 156:95d6b41a828b 240 [..] This section provides functions allowing to:
<> 156:95d6b41a828b 241 (+) Refresh the IWDG.
<> 144:ef7eb2e8f9f7 242
<> 144:ef7eb2e8f9f7 243 @endverbatim
<> 144:ef7eb2e8f9f7 244 * @{
<> 144:ef7eb2e8f9f7 245 */
<> 144:ef7eb2e8f9f7 246
<> 156:95d6b41a828b 247
<> 144:ef7eb2e8f9f7 248 /**
<> 156:95d6b41a828b 249 * @brief Refresh the IWDG.
<> 156:95d6b41a828b 250 * @param hiwdg pointer to a IWDG_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 251 * the configuration information for the specified IWDG module.
<> 156:95d6b41a828b 252 * @retval HAL status
<> 144:ef7eb2e8f9f7 253 */
<> 156:95d6b41a828b 254 HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg)
<> 144:ef7eb2e8f9f7 255 {
<> 156:95d6b41a828b 256 /* Reload IWDG counter with value defined in the reload register */
<> 156:95d6b41a828b 257 __HAL_IWDG_RELOAD_COUNTER(hiwdg);
<> 156:95d6b41a828b 258
<> 156:95d6b41a828b 259 /* Return function status */
<> 156:95d6b41a828b 260 return HAL_OK;
<> 144:ef7eb2e8f9f7 261 }
<> 144:ef7eb2e8f9f7 262
<> 144:ef7eb2e8f9f7 263 /**
<> 144:ef7eb2e8f9f7 264 * @}
<> 144:ef7eb2e8f9f7 265 */
<> 144:ef7eb2e8f9f7 266
<> 144:ef7eb2e8f9f7 267 /**
<> 144:ef7eb2e8f9f7 268 * @}
<> 144:ef7eb2e8f9f7 269 */
<> 144:ef7eb2e8f9f7 270
<> 144:ef7eb2e8f9f7 271 #endif /* HAL_IWDG_MODULE_ENABLED */
<> 144:ef7eb2e8f9f7 272 /**
<> 144:ef7eb2e8f9f7 273 * @}
<> 144:ef7eb2e8f9f7 274 */
<> 144:ef7eb2e8f9f7 275
<> 144:ef7eb2e8f9f7 276 /**
<> 144:ef7eb2e8f9f7 277 * @}
<> 144:ef7eb2e8f9f7 278 */
<> 144:ef7eb2e8f9f7 279
<> 144:ef7eb2e8f9f7 280 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/