mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

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targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_iwdg.c@156:95d6b41a828b, 2017-01-16 (annotated)

Committer:
<>
Date:
Mon Jan 16 15:03:32 2017 +0000
Revision:
156:95d6b41a828b
Parent:
149:156823d33999
Child:
180:96ed750bd169
This updates the lib to the mbed lib v134

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f0xx_hal_iwdg.c
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 156:95d6b41a828b 5 * @version V1.5.0
<> 156:95d6b41a828b 6 * @date 04-November-2016
<> 144:ef7eb2e8f9f7 7 * @brief IWDG HAL module driver.
<> 144:ef7eb2e8f9f7 8 * This file provides firmware functions to manage the following
<> 144:ef7eb2e8f9f7 9 * functionalities of the Independent Watchdog (IWDG) peripheral:
<> 156:95d6b41a828b 10 * + Initialization and Start functions
<> 144:ef7eb2e8f9f7 11 * + IO operation functions
<> 156:95d6b41a828b 12 *
<> 144:ef7eb2e8f9f7 13 @verbatim
<> 156:95d6b41a828b 14 ==============================================================================
<> 156:95d6b41a828b 15 ##### IWDG Generic features #####
<> 156:95d6b41a828b 16 ==============================================================================
<> 156:95d6b41a828b 17 [..]
<> 156:95d6b41a828b 18 (+) The IWDG can be started by either software or hardware (configurable
<> 156:95d6b41a828b 19 through option byte).
<> 156:95d6b41a828b 20
<> 156:95d6b41a828b 21 (+) The IWDG is clocked by Low-Speed clock (LSI) and thus stays active even
<> 156:95d6b41a828b 22 if the main clock fails.
<> 156:95d6b41a828b 23
<> 156:95d6b41a828b 24 (+) Once the IWDG is started, the LSI is forced ON and both can not be
<> 156:95d6b41a828b 25 disabled. The counter starts counting down from the reset value (0xFFF).
<> 156:95d6b41a828b 26 When it reaches the end of count value (0x000) a reset signal is
<> 156:95d6b41a828b 27 generated (IWDG reset).
<> 156:95d6b41a828b 28
<> 156:95d6b41a828b 29 (+) Whenever the key value 0x0000 AAAA is written in the IWDG_KR register,
<> 156:95d6b41a828b 30 the IWDG_RLR value is reloaded in the counter and the watchdog reset is
<> 156:95d6b41a828b 31 prevented.
<> 156:95d6b41a828b 32
<> 156:95d6b41a828b 33 (+) The IWDG is implemented in the VDD voltage domain that is still functional
<> 156:95d6b41a828b 34 in STOP and STANDBY mode (IWDG reset can wake-up from STANDBY).
<> 156:95d6b41a828b 35 IWDGRST flag in RCC_CSR register can be used to inform when an IWDG
<> 156:95d6b41a828b 36 reset occurs.
<> 156:95d6b41a828b 37
<> 156:95d6b41a828b 38 (+) Debug mode : When the microcontroller enters debug mode (core halted),
<> 156:95d6b41a828b 39 the IWDG counter either continues to work normally or stops, depending
<> 156:95d6b41a828b 40 on DBG_IWDG_STOP configuration bit in DBG module, accessible through
<> 156:95d6b41a828b 41 __HAL_DBGMCU_FREEZE_IWDG() and __HAL_DBGMCU_UNFREEZE_IWDG() macros
<> 144:ef7eb2e8f9f7 42
<> 156:95d6b41a828b 43 [..] Min-max timeout value @40KHz (LSI): ~0.1ms / ~26.2s
<> 156:95d6b41a828b 44 The IWDG timeout may vary due to LSI frequency dispersion. STM32F0xx
<> 156:95d6b41a828b 45 devices provide the capability to measure the LSI frequency (LSI clock
<> 156:95d6b41a828b 46 connected internally to TIM16 CH1 input capture). The measured value
<> 156:95d6b41a828b 47 can be used to have an IWDG timeout with an acceptable accuracy.
<> 156:95d6b41a828b 48
<> 156:95d6b41a828b 49 ##### How to use this driver #####
<> 156:95d6b41a828b 50 ==============================================================================
<> 156:95d6b41a828b 51 [..]
<> 156:95d6b41a828b 52 (#) Use IWDG using HAL_IWDG_Init() function to :
<> 156:95d6b41a828b 53 (++) Enable instance by writing Start keyword in IWDG_KEY register. LSI
<> 156:95d6b41a828b 54 clock is forced ON and IWDG counter starts downcounting.
<> 156:95d6b41a828b 55 (++) Enable write access to configuration register: IWDG_PR, IWDG_RLR &
<> 156:95d6b41a828b 56 IWDG_WINR.
<> 156:95d6b41a828b 57 (++) Configure the IWDG prescaler and counter reload value. This reload
<> 156:95d6b41a828b 58 value will be loaded in the IWDG counter each time the watchdog is
<> 156:95d6b41a828b 59 reloaded, then the IWDG will start counting down from this value.
<> 156:95d6b41a828b 60 (++) wait for status flags to be reset"
<> 156:95d6b41a828b 61 (++) Depending on window parameter:
<> 156:95d6b41a828b 62 (+++) If Window Init parameter is same as Window register value,
<> 156:95d6b41a828b 63 nothing more is done but reload counter value in order to exit
<> 156:95d6b41a828b 64 function withy exact time base.
<> 156:95d6b41a828b 65 (+++) Else modify Window register. This will automatically reload
<> 156:95d6b41a828b 66 watchdog counter.
<> 156:95d6b41a828b 67
<> 156:95d6b41a828b 68 (#) Then the application program must refresh the IWDG counter at regular
<> 156:95d6b41a828b 69 intervals during normal operation to prevent an MCU reset, using
<> 156:95d6b41a828b 70 HAL_IWDG_Refresh() function.
<> 144:ef7eb2e8f9f7 71
<> 144:ef7eb2e8f9f7 72 *** IWDG HAL driver macros list ***
<> 144:ef7eb2e8f9f7 73 ====================================
<> 144:ef7eb2e8f9f7 74 [..]
<> 156:95d6b41a828b 75 Below the list of most used macros in IWDG HAL driver:
<> 144:ef7eb2e8f9f7 76 (+) __HAL_IWDG_START: Enable the IWDG peripheral
<> 156:95d6b41a828b 77 (+) __HAL_IWDG_RELOAD_COUNTER: Reloads IWDG counter with value defined in
<> 156:95d6b41a828b 78 the reload register
<> 144:ef7eb2e8f9f7 79
<> 144:ef7eb2e8f9f7 80 @endverbatim
<> 144:ef7eb2e8f9f7 81 ******************************************************************************
<> 144:ef7eb2e8f9f7 82 * @attention
<> 144:ef7eb2e8f9f7 83 *
<> 144:ef7eb2e8f9f7 84 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 85 *
<> 144:ef7eb2e8f9f7 86 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 87 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 88 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 89 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 90 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 91 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 92 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 93 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 94 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 95 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 96 *
<> 144:ef7eb2e8f9f7 97 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 98 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 99 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 100 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 101 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 102 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 103 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 104 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 105 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 106 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 107 *
<> 144:ef7eb2e8f9f7 108 ******************************************************************************
<> 144:ef7eb2e8f9f7 109 */
<> 144:ef7eb2e8f9f7 110
<> 144:ef7eb2e8f9f7 111 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 112 #include "stm32f0xx_hal.h"
<> 144:ef7eb2e8f9f7 113
<> 144:ef7eb2e8f9f7 114 /** @addtogroup STM32F0xx_HAL_Driver
<> 144:ef7eb2e8f9f7 115 * @{
<> 144:ef7eb2e8f9f7 116 */
<> 144:ef7eb2e8f9f7 117
<> 156:95d6b41a828b 118 #ifdef HAL_IWDG_MODULE_ENABLED
<> 156:95d6b41a828b 119 /** @addtogroup IWDG
<> 144:ef7eb2e8f9f7 120 * @brief IWDG HAL module driver.
<> 144:ef7eb2e8f9f7 121 * @{
<> 144:ef7eb2e8f9f7 122 */
<> 144:ef7eb2e8f9f7 123
<> 144:ef7eb2e8f9f7 124 /* Private typedef -----------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 125 /* Private define ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 126 /** @defgroup IWDG_Private_Defines IWDG Private Defines
<> 144:ef7eb2e8f9f7 127 * @{
<> 144:ef7eb2e8f9f7 128 */
<> 156:95d6b41a828b 129 /* Status register need 5 RC LSI divided by prescaler clock to be updated. With
<> 156:95d6b41a828b 130 higher prescaler (256), and according to LSI variation, we need to wait at
<> 156:95d6b41a828b 131 least 6 cycles so 39 ms. */
<> 156:95d6b41a828b 132 #define HAL_IWDG_DEFAULT_TIMEOUT 39U
<> 144:ef7eb2e8f9f7 133 /**
<> 144:ef7eb2e8f9f7 134 * @}
<> 144:ef7eb2e8f9f7 135 */
<> 156:95d6b41a828b 136
<> 144:ef7eb2e8f9f7 137 /* Private macro -------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 138 /* Private variables ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 139 /* Private function prototypes -----------------------------------------------*/
<> 144:ef7eb2e8f9f7 140 /* Exported functions --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 141
<> 156:95d6b41a828b 142 /** @addtogroup IWDG_Exported_Functions
<> 144:ef7eb2e8f9f7 143 * @{
<> 144:ef7eb2e8f9f7 144 */
<> 144:ef7eb2e8f9f7 145
<> 156:95d6b41a828b 146 /** @addtogroup IWDG_Exported_Functions_Group1
<> 156:95d6b41a828b 147 * @brief Initialization and Start functions.
<> 144:ef7eb2e8f9f7 148 *
<> 144:ef7eb2e8f9f7 149 @verbatim
<> 144:ef7eb2e8f9f7 150 ===============================================================================
<> 156:95d6b41a828b 151 ##### Initialization and Start functions #####
<> 144:ef7eb2e8f9f7 152 ===============================================================================
<> 156:95d6b41a828b 153 [..] This section provides functions allowing to:
<> 156:95d6b41a828b 154 (+) Initialize the IWDG according to the specified parameters in the
<> 156:95d6b41a828b 155 IWDG_InitTypeDef of associated handle.
<> 156:95d6b41a828b 156 (+) Manage Window option.
<> 156:95d6b41a828b 157 (+) Once initialization is performed in HAL_IWDG_Init function, Watchdog
<> 156:95d6b41a828b 158 is reloaded in order to exit function with correct time base.
<> 144:ef7eb2e8f9f7 159
<> 144:ef7eb2e8f9f7 160 @endverbatim
<> 144:ef7eb2e8f9f7 161 * @{
<> 144:ef7eb2e8f9f7 162 */
<> 144:ef7eb2e8f9f7 163
<> 144:ef7eb2e8f9f7 164 /**
<> 156:95d6b41a828b 165 * @brief Initialize the IWDG according to the specified parameters in the
<> 156:95d6b41a828b 166 * IWDG_InitTypeDef and start watchdog. Before exiting function,
<> 156:95d6b41a828b 167 * watchdog is refreshed in order to have correct time base.
<> 156:95d6b41a828b 168 * @param hiwdg pointer to a IWDG_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 169 * the configuration information for the specified IWDG module.
<> 144:ef7eb2e8f9f7 170 * @retval HAL status
<> 144:ef7eb2e8f9f7 171 */
<> 144:ef7eb2e8f9f7 172 HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg)
<> 144:ef7eb2e8f9f7 173 {
<> 156:95d6b41a828b 174 uint32_t tickstart;
<> 144:ef7eb2e8f9f7 175
<> 144:ef7eb2e8f9f7 176 /* Check the IWDG handle allocation */
<> 144:ef7eb2e8f9f7 177 if(hiwdg == NULL)
<> 144:ef7eb2e8f9f7 178 {
<> 144:ef7eb2e8f9f7 179 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 180 }
<> 144:ef7eb2e8f9f7 181
<> 144:ef7eb2e8f9f7 182 /* Check the parameters */
<> 144:ef7eb2e8f9f7 183 assert_param(IS_IWDG_ALL_INSTANCE(hiwdg->Instance));
<> 144:ef7eb2e8f9f7 184 assert_param(IS_IWDG_PRESCALER(hiwdg->Init.Prescaler));
<> 144:ef7eb2e8f9f7 185 assert_param(IS_IWDG_RELOAD(hiwdg->Init.Reload));
<> 144:ef7eb2e8f9f7 186 assert_param(IS_IWDG_WINDOW(hiwdg->Init.Window));
<> 144:ef7eb2e8f9f7 187
<> 156:95d6b41a828b 188 /* Enable IWDG. LSI is turned on automaticaly */
<> 156:95d6b41a828b 189 __HAL_IWDG_START(hiwdg);
<> 144:ef7eb2e8f9f7 190
<> 156:95d6b41a828b 191 /* Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers by writing
<> 156:95d6b41a828b 192 0x5555 in KR */
<> 144:ef7eb2e8f9f7 193 IWDG_ENABLE_WRITE_ACCESS(hiwdg);
<> 144:ef7eb2e8f9f7 194
<> 156:95d6b41a828b 195 /* Write to IWDG registers the Prescaler & Reload values to work with */
<> 156:95d6b41a828b 196 hiwdg->Instance->PR = hiwdg->Init.Prescaler;
<> 156:95d6b41a828b 197 hiwdg->Instance->RLR = hiwdg->Init.Reload;
<> 144:ef7eb2e8f9f7 198
<> 156:95d6b41a828b 199 /* Check pending flag, if previous update not done, return timeout */
<> 144:ef7eb2e8f9f7 200 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 201
<> 156:95d6b41a828b 202 /* Wait for register to be updated */
<> 156:95d6b41a828b 203 while(hiwdg->Instance->SR != RESET)
<> 144:ef7eb2e8f9f7 204 {
<> 144:ef7eb2e8f9f7 205 if((HAL_GetTick() - tickstart ) > HAL_IWDG_DEFAULT_TIMEOUT)
<> 144:ef7eb2e8f9f7 206 {
<> 144:ef7eb2e8f9f7 207 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 208 }
<> 144:ef7eb2e8f9f7 209 }
<> 144:ef7eb2e8f9f7 210
<> 156:95d6b41a828b 211 /* If window parameter is different than current value, modify window
<> 156:95d6b41a828b 212 register */
<> 156:95d6b41a828b 213 if(hiwdg->Instance->WINR != hiwdg->Init.Window)
<> 144:ef7eb2e8f9f7 214 {
<> 156:95d6b41a828b 215 /* Write to IWDG WINR the IWDG_Window value to compare with. In any case,
<> 156:95d6b41a828b 216 even if window feature is disabled, Watchdog will be reloaded by writing
<> 156:95d6b41a828b 217 windows register */
<> 156:95d6b41a828b 218 hiwdg->Instance->WINR = hiwdg->Init.Window;
<> 144:ef7eb2e8f9f7 219 }
<> 156:95d6b41a828b 220 else
<> 156:95d6b41a828b 221 {
<> 156:95d6b41a828b 222 /* Reload IWDG counter with value defined in the reload register */
<> 156:95d6b41a828b 223 __HAL_IWDG_RELOAD_COUNTER(hiwdg);
<> 156:95d6b41a828b 224 }
<> 144:ef7eb2e8f9f7 225
<> 144:ef7eb2e8f9f7 226 /* Return function status */
<> 144:ef7eb2e8f9f7 227 return HAL_OK;
<> 144:ef7eb2e8f9f7 228 }
<> 144:ef7eb2e8f9f7 229
<> 144:ef7eb2e8f9f7 230 /**
<> 144:ef7eb2e8f9f7 231 * @}
<> 144:ef7eb2e8f9f7 232 */
<> 144:ef7eb2e8f9f7 233
<> 156:95d6b41a828b 234
<> 156:95d6b41a828b 235 /** @addtogroup IWDG_Exported_Functions_Group2
<> 156:95d6b41a828b 236 * @brief IO operation functions
<> 144:ef7eb2e8f9f7 237 *
<> 144:ef7eb2e8f9f7 238 @verbatim
<> 144:ef7eb2e8f9f7 239 ===============================================================================
<> 156:95d6b41a828b 240 ##### IO operation functions #####
<> 144:ef7eb2e8f9f7 241 ===============================================================================
<> 156:95d6b41a828b 242 [..] This section provides functions allowing to:
<> 156:95d6b41a828b 243 (+) Refresh the IWDG.
<> 144:ef7eb2e8f9f7 244
<> 144:ef7eb2e8f9f7 245 @endverbatim
<> 144:ef7eb2e8f9f7 246 * @{
<> 144:ef7eb2e8f9f7 247 */
<> 144:ef7eb2e8f9f7 248
<> 156:95d6b41a828b 249
<> 144:ef7eb2e8f9f7 250 /**
<> 156:95d6b41a828b 251 * @brief Refresh the IWDG.
<> 156:95d6b41a828b 252 * @param hiwdg pointer to a IWDG_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 253 * the configuration information for the specified IWDG module.
<> 156:95d6b41a828b 254 * @retval HAL status
<> 144:ef7eb2e8f9f7 255 */
<> 156:95d6b41a828b 256 HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg)
<> 144:ef7eb2e8f9f7 257 {
<> 156:95d6b41a828b 258 /* Reload IWDG counter with value defined in the reload register */
<> 156:95d6b41a828b 259 __HAL_IWDG_RELOAD_COUNTER(hiwdg);
<> 156:95d6b41a828b 260
<> 156:95d6b41a828b 261 /* Return function status */
<> 156:95d6b41a828b 262 return HAL_OK;
<> 144:ef7eb2e8f9f7 263 }
<> 144:ef7eb2e8f9f7 264
<> 144:ef7eb2e8f9f7 265 /**
<> 144:ef7eb2e8f9f7 266 * @}
<> 144:ef7eb2e8f9f7 267 */
<> 144:ef7eb2e8f9f7 268
<> 144:ef7eb2e8f9f7 269 /**
<> 144:ef7eb2e8f9f7 270 * @}
<> 144:ef7eb2e8f9f7 271 */
<> 144:ef7eb2e8f9f7 272
<> 144:ef7eb2e8f9f7 273 #endif /* HAL_IWDG_MODULE_ENABLED */
<> 144:ef7eb2e8f9f7 274 /**
<> 144:ef7eb2e8f9f7 275 * @}
<> 144:ef7eb2e8f9f7 276 */
<> 144:ef7eb2e8f9f7 277
<> 144:ef7eb2e8f9f7 278 /**
<> 144:ef7eb2e8f9f7 279 * @}
<> 144:ef7eb2e8f9f7 280 */
<> 144:ef7eb2e8f9f7 281
<> 144:ef7eb2e8f9f7 282 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/