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targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_src.h@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
Parent:
187:0387e8f68319 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 181:57724642e740 1 /*
AnnaBridge 187:0387e8f68319 2 * The Clear BSD License
AnnaBridge 181:57724642e740 3 * Copyright (c) 2016, Freescale Semiconductor, Inc.
AnnaBridge 181:57724642e740 4 * Copyright 2016-2017 NXP
AnnaBridge 187:0387e8f68319 5 * All rights reserved.
AnnaBridge 187:0387e8f68319 6 *
AnnaBridge 181:57724642e740 7 * Redistribution and use in source and binary forms, with or without modification,
AnnaBridge 187:0387e8f68319 8 * are permitted (subject to the limitations in the disclaimer below) provided
AnnaBridge 187:0387e8f68319 9 * that the following conditions are met:
AnnaBridge 181:57724642e740 10 *
AnnaBridge 181:57724642e740 11 * o Redistributions of source code must retain the above copyright notice, this list
AnnaBridge 181:57724642e740 12 * of conditions and the following disclaimer.
AnnaBridge 181:57724642e740 13 *
AnnaBridge 181:57724642e740 14 * o Redistributions in binary form must reproduce the above copyright notice, this
AnnaBridge 181:57724642e740 15 * list of conditions and the following disclaimer in the documentation and/or
AnnaBridge 181:57724642e740 16 * other materials provided with the distribution.
AnnaBridge 181:57724642e740 17 *
AnnaBridge 181:57724642e740 18 * o Neither the name of the copyright holder nor the names of its
AnnaBridge 181:57724642e740 19 * contributors may be used to endorse or promote products derived from this
AnnaBridge 181:57724642e740 20 * software without specific prior written permission.
AnnaBridge 181:57724642e740 21 *
AnnaBridge 187:0387e8f68319 22 * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
AnnaBridge 181:57724642e740 23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
AnnaBridge 181:57724642e740 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
AnnaBridge 181:57724642e740 25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge 181:57724642e740 26 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
AnnaBridge 181:57724642e740 27 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
AnnaBridge 181:57724642e740 28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
AnnaBridge 181:57724642e740 29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
AnnaBridge 181:57724642e740 30 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
AnnaBridge 181:57724642e740 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
AnnaBridge 181:57724642e740 32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge 181:57724642e740 33 */
AnnaBridge 181:57724642e740 34
AnnaBridge 181:57724642e740 35 #ifndef _FSL_SRC_H_
AnnaBridge 181:57724642e740 36 #define _FSL_SRC_H_
AnnaBridge 181:57724642e740 37
AnnaBridge 181:57724642e740 38 #include "fsl_common.h"
AnnaBridge 181:57724642e740 39
AnnaBridge 181:57724642e740 40 /*!
AnnaBridge 181:57724642e740 41 * @addtogroup src
AnnaBridge 181:57724642e740 42 * @{
AnnaBridge 181:57724642e740 43 */
AnnaBridge 181:57724642e740 44
AnnaBridge 181:57724642e740 45 /*******************************************************************************
AnnaBridge 181:57724642e740 46 * Definitions
AnnaBridge 181:57724642e740 47 ******************************************************************************/
AnnaBridge 181:57724642e740 48
AnnaBridge 181:57724642e740 49 /*! @name Driver version */
AnnaBridge 181:57724642e740 50 /*@{*/
AnnaBridge 181:57724642e740 51 /*! @brief SRC driver version 2.0.0. */
AnnaBridge 181:57724642e740 52 #define FSL_SRC_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
AnnaBridge 181:57724642e740 53 /*@}*/
AnnaBridge 181:57724642e740 54
AnnaBridge 181:57724642e740 55 /*!
AnnaBridge 181:57724642e740 56 * @brief SRC reset status flags.
AnnaBridge 181:57724642e740 57 */
AnnaBridge 181:57724642e740 58 enum _src_reset_status_flags
AnnaBridge 181:57724642e740 59 {
AnnaBridge 181:57724642e740 60 #if (defined(FSL_FEATURE_SRC_HAS_SRSR_RESET_OUT) && FSL_FEATURE_SRC_HAS_SRSR_RESET_OUT)
AnnaBridge 181:57724642e740 61 kSRC_ResetOutputEnableFlag = SRC_SRSR_RESET_OUT_MASK, /*!< This bit indicates if RESET status is
AnnaBridge 181:57724642e740 62 driven out on PTE0 pin. */
AnnaBridge 181:57724642e740 63 #endif /* FSL_FEATURE_SRC_HAS_SRSR_RESET_OUT */
AnnaBridge 181:57724642e740 64 #if !(defined(FSL_FEATURE_SRC_HAS_NO_SRSR_WBI) && FSL_FEATURE_SRC_HAS_NO_SRSR_WBI)
AnnaBridge 181:57724642e740 65 kSRC_WarmBootIndicationFlag = SRC_SRSR_WBI_MASK, /*!< WARM boot indication shows that WARM boot
AnnaBridge 181:57724642e740 66 was initiated by software. */
AnnaBridge 181:57724642e740 67 #endif /* FSL_FEATURE_SRC_HAS_NO_SRSR_WBI */
AnnaBridge 181:57724642e740 68 kSRC_TemperatureSensorResetFlag = SRC_SRSR_TSR_MASK, /*!< Indicates whether the reset was the
AnnaBridge 181:57724642e740 69 result of software reset from on-chip
AnnaBridge 181:57724642e740 70 Temperature Sensor. Temperature Sensor
AnnaBridge 181:57724642e740 71 Interrupt need be served before this
AnnaBridge 181:57724642e740 72 bit can be cleaned.*/
AnnaBridge 181:57724642e740 73 #if (defined(FSL_FEATURE_SRC_HAS_SRSR_WDOG3_RST_B) && FSL_FEATURE_SRC_HAS_SRSR_WDOG3_RST_B)
AnnaBridge 181:57724642e740 74 kSRC_Wdog3ResetFlag = SRC_SRSR_WDOG3_RST_B_MASK, /*!< IC Watchdog3 Time-out reset. Indicates
AnnaBridge 181:57724642e740 75 whether the reset was the result of the
AnnaBridge 181:57724642e740 76 watchdog3 time-out event. */
AnnaBridge 181:57724642e740 77 #endif /* FSL_FEATURE_SRC_HAS_SRSR_WDOG3_RST_B */
AnnaBridge 181:57724642e740 78 #if (defined(FSL_FEATURE_SRC_HAS_SRSR_SW) && FSL_FEATURE_SRC_HAS_SRSR_SW)
AnnaBridge 181:57724642e740 79 kSRC_SoftwareResetFlag = SRC_SRSR_SW_MASK, /*!< Indicates a reset has been caused by software
AnnaBridge 181:57724642e740 80 setting of SYSRESETREQ bit in Application
AnnaBridge 181:57724642e740 81 Interrupt and Reset Control Register in the
AnnaBridge 181:57724642e740 82 ARM core. */
AnnaBridge 181:57724642e740 83 #endif /* FSL_FEATURE_SRC_HAS_SRSR_SW */
AnnaBridge 181:57724642e740 84 kSRC_JTAGSoftwareResetFlag = SRC_SRSR_SJC_MASK, /*!< Indicates whether the reset was the result of
AnnaBridge 181:57724642e740 85 setting SJC_GPCCR bit 31. */
AnnaBridge 181:57724642e740 86 kSRC_JTAGGeneratedResetFlag = SRC_SRSR_JTAG_MASK, /*!< Indicates a reset has been caused by JTAG
AnnaBridge 181:57724642e740 87 selection of certain IR codes: EXTEST or
AnnaBridge 181:57724642e740 88 HIGHZ. */
AnnaBridge 181:57724642e740 89 kSRC_WatchdogResetFlag = SRC_SRSR_WDOG_MASK, /*!< Indicates a reset has been caused by the
AnnaBridge 181:57724642e740 90 watchdog timer timing out. This reset source
AnnaBridge 181:57724642e740 91 can be blocked by disabling the watchdog. */
AnnaBridge 181:57724642e740 92 #if (defined(FSL_FEATURE_SRC_HAS_SRSR_IPP_USER_RESET_B) && FSL_FEATURE_SRC_HAS_SRSR_IPP_USER_RESET_B)
AnnaBridge 181:57724642e740 93 kSRC_IppUserResetFlag = SRC_SRSR_IPP_USER_RESET_B_MASK, /*!< Indicates whether the reset was the
AnnaBridge 181:57724642e740 94 result of the ipp_user_reset_b
AnnaBridge 181:57724642e740 95 qualified reset. */
AnnaBridge 181:57724642e740 96 #endif /* FSL_FEATURE_SRC_HAS_SRSR_IPP_USER_RESET_B */
AnnaBridge 181:57724642e740 97 #if (defined(FSL_FEATURE_SRC_HAS_SRSR_SNVS) && FSL_FEATURE_SRC_HAS_SRSR_SNVS)
AnnaBridge 181:57724642e740 98 kSRC_SNVSFailResetFlag = SRC_SRSR_SNVS_MASK, /*!< SNVS hardware failure will always cause a cold
AnnaBridge 181:57724642e740 99 reset. This flag indicates whether the reset
AnnaBridge 181:57724642e740 100 is a result of SNVS hardware failure. */
AnnaBridge 181:57724642e740 101 #endif /* FSL_FEATURE_SRC_HAS_SRSR_SNVS */
AnnaBridge 181:57724642e740 102 #if (defined(FSL_FEATURE_SRC_HAS_SRSR_CSU_RESET_B) && FSL_FEATURE_SRC_HAS_SRSR_CSU_RESET_B)
AnnaBridge 181:57724642e740 103 kSRC_CsuResetFlag = SRC_SRSR_CSU_RESET_B_MASK, /*!< Indicates whether the reset was the result
AnnaBridge 181:57724642e740 104 of the csu_reset_b input. */
AnnaBridge 181:57724642e740 105 #endif /* FSL_FEATURE_SRC_HAS_SRSR_CSU_RESET_B */
AnnaBridge 181:57724642e740 106 #if (defined(FSL_FEATURE_SRC_HAS_SRSR_LOCKUP) && FSL_FEATURE_SRC_HAS_SRSR_LOCKUP)
AnnaBridge 181:57724642e740 107 kSRC_CoreLockupResetFlag = SRC_SRSR_LOCKUP_MASK, /*!< Indicates a reset has been caused by the
AnnaBridge 181:57724642e740 108 ARM core indication of a LOCKUP event. */
AnnaBridge 181:57724642e740 109 #endif /* FSL_FEATURE_SRC_HAS_SRSR_LOCKUP */
AnnaBridge 181:57724642e740 110 #if (defined(FSL_FEATURE_SRC_HAS_SRSR_POR) && FSL_FEATURE_SRC_HAS_SRSR_POR)
AnnaBridge 181:57724642e740 111 kSRC_PowerOnResetFlag = SRC_SRSR_POR_MASK, /*!< Indicates a reset has been caused by the
AnnaBridge 181:57724642e740 112 power-on detection logic. */
AnnaBridge 181:57724642e740 113 #endif /* FSL_FEATURE_SRC_HAS_SRSR_POR */
AnnaBridge 181:57724642e740 114 #if (defined(FSL_FEATURE_SRC_HAS_SRSR_LOCKUP_SYSRESETREQ) && FSL_FEATURE_SRC_HAS_SRSR_LOCKUP_SYSRESETREQ)
AnnaBridge 181:57724642e740 115 kSRC_LockupSysResetFlag = SRC_SRSR_LOCKUP_SYSRESETREQ_MASK, /*!< Indicates a reset has been caused by CPU lockup or software
AnnaBridge 181:57724642e740 116 setting of SYSRESETREQ bit in Application Interrupt and
AnnaBridge 181:57724642e740 117 Reset Control Register of the ARM core. */
AnnaBridge 181:57724642e740 118 #endif /* FSL_FEATURE_SRC_HAS_SRSR_LOCKUP_SYSRESETREQ */
AnnaBridge 181:57724642e740 119 #if (defined(FSL_FEATURE_SRC_HAS_SRSR_IPP_RESET_B) && FSL_FEATURE_SRC_HAS_SRSR_IPP_RESET_B)
AnnaBridge 181:57724642e740 120 kSRC_IppResetPinFlag = SRC_SRSR_IPP_RESET_B_MASK, /*!< Indicates whether reset was the result of
AnnaBridge 181:57724642e740 121 ipp_reset_b pin (Power-up sequence). */
AnnaBridge 181:57724642e740 122 #endif /* FSL_FEATURE_SRC_HAS_SRSR_IPP_RESET_B */
AnnaBridge 181:57724642e740 123 };
AnnaBridge 181:57724642e740 124
AnnaBridge 181:57724642e740 125 #if (defined(FSL_FEATURE_SRC_HAS_SISR) && FSL_FEATURE_SRC_HAS_SISR)
AnnaBridge 181:57724642e740 126 /*!
AnnaBridge 181:57724642e740 127 * @brief SRC interrupt status flag.
AnnaBridge 181:57724642e740 128 */
AnnaBridge 181:57724642e740 129 enum _src_status_flags
AnnaBridge 181:57724642e740 130 {
AnnaBridge 181:57724642e740 131 kSRC_Core0WdogResetReqFlag =
AnnaBridge 181:57724642e740 132 SRC_SISR_CORE0_WDOG_RST_REQ_MASK, /*!< WDOG reset request from core0. Read-only status bit. */
AnnaBridge 181:57724642e740 133 };
AnnaBridge 181:57724642e740 134 #endif /* FSL_FEATURE_SRC_HAS_SISR */
AnnaBridge 181:57724642e740 135
AnnaBridge 181:57724642e740 136 #if (defined(FSL_FEATURE_SRC_HAS_SCR_MIX_RST_STRCH) && FSL_FEATURE_SRC_HAS_SCR_MIX_RST_STRCH)
AnnaBridge 181:57724642e740 137 /*!
AnnaBridge 181:57724642e740 138 * @brief Selection of SoC mix power reset stretch.
AnnaBridge 181:57724642e740 139 *
AnnaBridge 181:57724642e740 140 * This type defines the SoC mix (Audio, ENET, uSDHC, EIM, QSPI, OCRAM, MMDC, etc) power up reset
AnnaBridge 181:57724642e740 141 * stretch mix reset width with the optional count of cycles
AnnaBridge 181:57724642e740 142 */
AnnaBridge 181:57724642e740 143 typedef enum _src_mix_reset_stretch_cycles
AnnaBridge 181:57724642e740 144 {
AnnaBridge 181:57724642e740 145 kSRC_MixResetStretchCycleAlt0 = 0U, /*!< mix reset width is 1 x 88 ipg_cycle cycles. */
AnnaBridge 181:57724642e740 146 kSRC_MixResetStretchCycleAlt1 = 1U, /*!< mix reset width is 2 x 88 ipg_cycle cycles. */
AnnaBridge 181:57724642e740 147 kSRC_MixResetStretchCycleAlt2 = 2U, /*!< mix reset width is 3 x 88 ipg_cycle cycles. */
AnnaBridge 181:57724642e740 148 kSRC_MixResetStretchCycleAlt3 = 3U, /*!< mix reset width is 4 x 88 ipg_cycle cycles. */
AnnaBridge 181:57724642e740 149 } src_mix_reset_stretch_cycles_t;
AnnaBridge 181:57724642e740 150 #endif /* FSL_FEATURE_SRC_HAS_SCR_MIX_RST_STRCH */
AnnaBridge 181:57724642e740 151
AnnaBridge 181:57724642e740 152 #if (defined(FSL_FEATURE_SRC_HAS_SCR_WDOG3_RST_OPTN) && FSL_FEATURE_SRC_HAS_SCR_WDOG3_RST_OPTN)
AnnaBridge 181:57724642e740 153 /*!
AnnaBridge 181:57724642e740 154 * @brief Selection of WDOG3 reset option.
AnnaBridge 181:57724642e740 155 */
AnnaBridge 181:57724642e740 156 typedef enum _src_wdog3_reset_option
AnnaBridge 181:57724642e740 157 {
AnnaBridge 181:57724642e740 158 kSRC_Wdog3ResetOptionAlt0 = 0U, /*!< Wdog3_rst_b asserts M4 reset (default). */
AnnaBridge 181:57724642e740 159 kSRC_Wdog3ResetOptionAlt1 = 1U, /*!< Wdog3_rst_b asserts global reset. */
AnnaBridge 181:57724642e740 160 } src_wdog3_reset_option_t;
AnnaBridge 181:57724642e740 161 #endif /* FSL_FEATURE_SRC_HAS_SCR_WDOG3_RST_OPTN */
AnnaBridge 181:57724642e740 162
AnnaBridge 181:57724642e740 163 /*!
AnnaBridge 181:57724642e740 164 * @brief Selection of WARM reset bypass count.
AnnaBridge 181:57724642e740 165 *
AnnaBridge 181:57724642e740 166 * This type defines the 32KHz clock cycles to count before bypassing the MMDC acknowledge for WARM
AnnaBridge 181:57724642e740 167 * reset. If the MMDC acknowledge is not asserted before this counter is elapsed, a COLD reset will
AnnaBridge 181:57724642e740 168 * be initiated.
AnnaBridge 181:57724642e740 169 */
AnnaBridge 181:57724642e740 170 typedef enum _src_warm_reset_bypass_count
AnnaBridge 181:57724642e740 171 {
AnnaBridge 181:57724642e740 172 kSRC_WarmResetWaitAlways = 0U, /*!< System will wait until MMDC acknowledge is asserted. */
AnnaBridge 181:57724642e740 173 kSRC_WarmResetWaitClk16 = 1U, /*!< Wait 16 32KHz clock cycles before switching the reset. */
AnnaBridge 181:57724642e740 174 kSRC_WarmResetWaitClk32 = 2U, /*!< Wait 32 32KHz clock cycles before switching the reset. */
AnnaBridge 181:57724642e740 175 kSRC_WarmResetWaitClk64 = 3U, /*!< Wait 64 32KHz clock cycles before switching the reset. */
AnnaBridge 181:57724642e740 176 } src_warm_reset_bypass_count_t;
AnnaBridge 181:57724642e740 177
AnnaBridge 181:57724642e740 178 #if defined(__cplusplus)
AnnaBridge 181:57724642e740 179 extern "C" {
AnnaBridge 181:57724642e740 180 #endif
AnnaBridge 181:57724642e740 181
AnnaBridge 181:57724642e740 182 /*******************************************************************************
AnnaBridge 181:57724642e740 183 * API
AnnaBridge 181:57724642e740 184 ******************************************************************************/
AnnaBridge 181:57724642e740 185
AnnaBridge 181:57724642e740 186 #if (defined(FSL_FEATURE_SRC_HAS_SCR_MASK_WDOG3_RST) && FSL_FEATURE_SRC_HAS_SCR_MASK_WDOG3_RST)
AnnaBridge 181:57724642e740 187 /*!
AnnaBridge 181:57724642e740 188 * @brief Enable the WDOG3 reset.
AnnaBridge 181:57724642e740 189 *
AnnaBridge 181:57724642e740 190 * The WDOG3 reset is enabled by default.
AnnaBridge 181:57724642e740 191 *
AnnaBridge 181:57724642e740 192 * @param base SRC peripheral base address.
AnnaBridge 181:57724642e740 193 * @param enable Enable the reset or not.
AnnaBridge 181:57724642e740 194 */
AnnaBridge 181:57724642e740 195 static inline void SRC_EnableWDOG3Reset(SRC_Type *base, bool enable)
AnnaBridge 181:57724642e740 196 {
AnnaBridge 181:57724642e740 197 if (enable)
AnnaBridge 181:57724642e740 198 {
AnnaBridge 181:57724642e740 199 base->SCR = (base->SCR & ~SRC_SCR_MASK_WDOG3_RST_MASK) | SRC_SCR_MASK_WDOG3_RST(0xA);
AnnaBridge 181:57724642e740 200 }
AnnaBridge 181:57724642e740 201 else
AnnaBridge 181:57724642e740 202 {
AnnaBridge 181:57724642e740 203 base->SCR = (base->SCR & ~SRC_SCR_MASK_WDOG3_RST_MASK) | SRC_SCR_MASK_WDOG3_RST(0x5);
AnnaBridge 181:57724642e740 204 }
AnnaBridge 181:57724642e740 205 }
AnnaBridge 181:57724642e740 206 #endif /* FSL_FEATURE_SRC_HAS_SCR_MASK_WDOG3_RST */
AnnaBridge 181:57724642e740 207
AnnaBridge 181:57724642e740 208 #if (defined(FSL_FEATURE_SRC_HAS_SCR_MIX_RST_STRCH) && FSL_FEATURE_SRC_HAS_SCR_MIX_RST_STRCH)
AnnaBridge 181:57724642e740 209 /*!
AnnaBridge 181:57724642e740 210 * @brief Set the mix power up reset stretch mix reset width.
AnnaBridge 181:57724642e740 211 *
AnnaBridge 181:57724642e740 212 * @param base SRC peripheral base address.
AnnaBridge 181:57724642e740 213 * @param option Setting option, see to #src_mix_reset_stretch_cycles_t.
AnnaBridge 181:57724642e740 214 */
AnnaBridge 181:57724642e740 215 static inline void SRC_SetMixResetStretchCycles(SRC_Type *base, src_mix_reset_stretch_cycles_t option)
AnnaBridge 181:57724642e740 216 {
AnnaBridge 181:57724642e740 217 base->SCR = (base->SCR & ~SRC_SCR_MIX_RST_STRCH_MASK) | SRC_SCR_MIX_RST_STRCH(option);
AnnaBridge 181:57724642e740 218 }
AnnaBridge 181:57724642e740 219 #endif /* FSL_FEATURE_SRC_HAS_SCR_MIX_RST_STRCH */
AnnaBridge 181:57724642e740 220
AnnaBridge 181:57724642e740 221 #if (defined(FSL_FEATURE_SRC_HAS_SCR_DBG_RST_MSK_PG) && FSL_FEATURE_SRC_HAS_SCR_DBG_RST_MSK_PG)
AnnaBridge 181:57724642e740 222 /*!
AnnaBridge 181:57724642e740 223 * @brief Debug reset would be asserted after power gating event.
AnnaBridge 181:57724642e740 224 *
AnnaBridge 181:57724642e740 225 * @param base SRC peripheral base address.
AnnaBridge 181:57724642e740 226 * @param enable Enable the reset or not.
AnnaBridge 181:57724642e740 227 */
AnnaBridge 181:57724642e740 228 static inline void SRC_EnableCoreDebugResetAfterPowerGate(SRC_Type *base, bool enable)
AnnaBridge 181:57724642e740 229 {
AnnaBridge 181:57724642e740 230 if (enable)
AnnaBridge 181:57724642e740 231 {
AnnaBridge 181:57724642e740 232 base->SCR &= ~SRC_SCR_DBG_RST_MSK_PG_MASK;
AnnaBridge 181:57724642e740 233 }
AnnaBridge 181:57724642e740 234 else
AnnaBridge 181:57724642e740 235 {
AnnaBridge 181:57724642e740 236 base->SCR |= SRC_SCR_DBG_RST_MSK_PG_MASK;
AnnaBridge 181:57724642e740 237 }
AnnaBridge 181:57724642e740 238 }
AnnaBridge 181:57724642e740 239 #endif /* FSL_FEATURE_SRC_HAS_SCR_DBG_RST_MSK_PG */
AnnaBridge 181:57724642e740 240
AnnaBridge 181:57724642e740 241 #if (defined(FSL_FEATURE_SRC_HAS_SCR_WDOG3_RST_OPTN) && FSL_FEATURE_SRC_HAS_SCR_WDOG3_RST_OPTN)
AnnaBridge 181:57724642e740 242 /*!
AnnaBridge 181:57724642e740 243 * @brief Set the Wdog3_rst_b option.
AnnaBridge 181:57724642e740 244 *
AnnaBridge 181:57724642e740 245 * @param base SRC peripheral base address.
AnnaBridge 181:57724642e740 246 * @param option Setting option, see to #src_wdog3_reset_option_t.
AnnaBridge 181:57724642e740 247 */
AnnaBridge 181:57724642e740 248 static inline void SRC_SetWdog3ResetOption(SRC_Type *base, src_wdog3_reset_option_t option)
AnnaBridge 181:57724642e740 249 {
AnnaBridge 181:57724642e740 250 base->SCR = (base->SCR & ~SRC_SCR_WDOG3_RST_OPTN_MASK) | SRC_SCR_WDOG3_RST_OPTN(option);
AnnaBridge 181:57724642e740 251 }
AnnaBridge 181:57724642e740 252 #endif /* FSL_FEATURE_SRC_HAS_SCR_WDOG3_RST_OPTN */
AnnaBridge 181:57724642e740 253
AnnaBridge 181:57724642e740 254 #if (defined(FSL_FEATURE_SRC_HAS_SCR_CORES_DBG_RST) && FSL_FEATURE_SRC_HAS_SCR_CORES_DBG_RST)
AnnaBridge 181:57724642e740 255 /*!
AnnaBridge 181:57724642e740 256 * @brief Software reset for debug of arm platform only.
AnnaBridge 181:57724642e740 257 *
AnnaBridge 181:57724642e740 258 * @param base SRC peripheral base address.
AnnaBridge 181:57724642e740 259 */
AnnaBridge 181:57724642e740 260 static inline void SRC_DoSoftwareResetARMCoreDebug(SRC_Type *base)
AnnaBridge 181:57724642e740 261 {
AnnaBridge 181:57724642e740 262 base->SCR |= SRC_SCR_CORES_DBG_RST_MASK;
AnnaBridge 181:57724642e740 263 }
AnnaBridge 181:57724642e740 264
AnnaBridge 181:57724642e740 265 /*!
AnnaBridge 181:57724642e740 266 * @brief Check if the software reset for debug of arm platform only is done.
AnnaBridge 181:57724642e740 267 *
AnnaBridge 181:57724642e740 268 * @param base SRC peripheral base address.
AnnaBridge 181:57724642e740 269 */
AnnaBridge 181:57724642e740 270 static inline bool SRC_GetSoftwareResetARMCoreDebugDone(SRC_Type *base)
AnnaBridge 181:57724642e740 271 {
AnnaBridge 181:57724642e740 272 return (0U == (base->SCR & SRC_SCR_CORES_DBG_RST_MASK));
AnnaBridge 181:57724642e740 273 }
AnnaBridge 181:57724642e740 274 #endif /* FSL_FEATURE_SRC_HAS_SCR_CORES_DBG_RST */
AnnaBridge 181:57724642e740 275
AnnaBridge 181:57724642e740 276 #if (defined(FSL_FEATURE_SRC_HAS_SCR_MTSR) && FSL_FEATURE_SRC_HAS_SCR_MTSR)
AnnaBridge 181:57724642e740 277 /*!
AnnaBridge 181:57724642e740 278 * @brief Enable the temperature sensor reset.
AnnaBridge 181:57724642e740 279 *
AnnaBridge 181:57724642e740 280 * The temperature sersor reset is enabled by default. When the sensor reset happens, an flag bit
AnnaBridge 181:57724642e740 281 * would be asserted. This flag bit can be cleared only by the hardware reset.
AnnaBridge 181:57724642e740 282 *
AnnaBridge 181:57724642e740 283 * @param base SRC peripheral base address.
AnnaBridge 181:57724642e740 284 * @param enable Enable the reset or not.
AnnaBridge 181:57724642e740 285 */
AnnaBridge 181:57724642e740 286 static inline void SRC_EnableTemperatureSensorReset(SRC_Type *base, bool enable)
AnnaBridge 181:57724642e740 287 {
AnnaBridge 181:57724642e740 288 if (enable) /* Temperature sensor reset is not masked. (default) */
AnnaBridge 181:57724642e740 289 {
AnnaBridge 181:57724642e740 290 base->SCR = (base->SCR & ~SRC_SCR_MTSR_MASK) | SRC_SCR_MTSR(0x2);
AnnaBridge 181:57724642e740 291 }
AnnaBridge 181:57724642e740 292 else /* The on-chip temperature sensor interrupt will not create a reset to the chip. */
AnnaBridge 181:57724642e740 293 {
AnnaBridge 181:57724642e740 294 base->SCR = (base->SCR & ~SRC_SCR_MTSR_MASK) | SRC_SCR_MTSR(0x5);
AnnaBridge 181:57724642e740 295 }
AnnaBridge 181:57724642e740 296 }
AnnaBridge 181:57724642e740 297 #endif /* FSL_FEATURE_SRC_HAS_SCR_MTSR */
AnnaBridge 181:57724642e740 298
AnnaBridge 181:57724642e740 299 #if (defined(FSL_FEATURE_SCR_HAS_SCR_CORE0_DBG_RST) && FSL_FEATURE_SCR_HAS_SCR_CORE0_DBG_RST)
AnnaBridge 181:57724642e740 300 /*!
AnnaBridge 181:57724642e740 301 * @brief Do assert the core0 debug reset.
AnnaBridge 181:57724642e740 302 *
AnnaBridge 181:57724642e740 303 * @param base SRC peripheral base address.
AnnaBridge 181:57724642e740 304 */
AnnaBridge 181:57724642e740 305 static inline void SRC_DoAssertCore0DebugReset(SRC_Type *base)
AnnaBridge 181:57724642e740 306 {
AnnaBridge 181:57724642e740 307 base->SCR |= SRC_SCR_CORE0_DBG_RST_MASK;
AnnaBridge 181:57724642e740 308 }
AnnaBridge 181:57724642e740 309
AnnaBridge 181:57724642e740 310 /*!
AnnaBridge 181:57724642e740 311 * @brief Check if the core0 debug reset is done.
AnnaBridge 181:57724642e740 312 *
AnnaBridge 181:57724642e740 313 * @param base SRC peripheral base address.
AnnaBridge 181:57724642e740 314 */
AnnaBridge 181:57724642e740 315 static inline bool SRC_GetAssertCore0DebugResetDone(SRC_Type *base)
AnnaBridge 181:57724642e740 316 {
AnnaBridge 181:57724642e740 317 return (0U == (base->SCR & SRC_SCR_CORE0_DBG_RST_MASK));
AnnaBridge 181:57724642e740 318 }
AnnaBridge 181:57724642e740 319 #endif /* FSL_FEATURE_SCR_HAS_SCR_CORE0_DBG_RST */
AnnaBridge 181:57724642e740 320
AnnaBridge 181:57724642e740 321 #if (defined(FSL_FEATURE_SRC_HAS_SCR_CORE0_RST) && FSL_FEATURE_SRC_HAS_SCR_CORE0_RST)
AnnaBridge 181:57724642e740 322 /*!
AnnaBridge 181:57724642e740 323 * @brief Do software reset the ARM core0 only.
AnnaBridge 181:57724642e740 324 *
AnnaBridge 181:57724642e740 325 * @param base SRC peripheral base address.
AnnaBridge 181:57724642e740 326 */
AnnaBridge 181:57724642e740 327 static inline void SRC_DoSoftwareResetARMCore0(SRC_Type *base)
AnnaBridge 181:57724642e740 328 {
AnnaBridge 181:57724642e740 329 base->SCR |= SRC_SCR_CORE0_RST_MASK;
AnnaBridge 181:57724642e740 330 }
AnnaBridge 181:57724642e740 331
AnnaBridge 181:57724642e740 332 /*!
AnnaBridge 181:57724642e740 333 * @brief Check if the software for ARM core0 is done.
AnnaBridge 181:57724642e740 334 *
AnnaBridge 181:57724642e740 335 * @param base SRC peripheral base address.
AnnaBridge 181:57724642e740 336 * @return If the reset is done.
AnnaBridge 181:57724642e740 337 */
AnnaBridge 181:57724642e740 338 static inline bool SRC_GetSoftwareResetARMCore0Done(SRC_Type *base)
AnnaBridge 181:57724642e740 339 {
AnnaBridge 181:57724642e740 340 return (0U == (base->SCR & SRC_SCR_CORE0_RST_MASK));
AnnaBridge 181:57724642e740 341 }
AnnaBridge 181:57724642e740 342 #endif /* FSL_FEATURE_SRC_HAS_SCR_CORE0_RST */
AnnaBridge 181:57724642e740 343
AnnaBridge 181:57724642e740 344 #if (defined(FSL_FEATURE_SRC_HAS_SCR_SWRC) && FSL_FEATURE_SRC_HAS_SCR_SWRC)
AnnaBridge 181:57724642e740 345 /*!
AnnaBridge 181:57724642e740 346 * @brief Do software reset for ARM core.
AnnaBridge 181:57724642e740 347 *
AnnaBridge 181:57724642e740 348 * This function can be used to assert the ARM core reset. Once it is called, the reset process will
AnnaBridge 181:57724642e740 349 * begin. After the reset process is finished, the command bit would be self cleared.
AnnaBridge 181:57724642e740 350 *
AnnaBridge 181:57724642e740 351 * @param base SRC peripheral base address.
AnnaBridge 181:57724642e740 352 */
AnnaBridge 181:57724642e740 353 static inline void SRC_DoSoftwareResetARMCore(SRC_Type *base)
AnnaBridge 181:57724642e740 354 {
AnnaBridge 181:57724642e740 355 base->SCR |= SRC_SCR_SWRC_MASK;
AnnaBridge 181:57724642e740 356 }
AnnaBridge 181:57724642e740 357
AnnaBridge 181:57724642e740 358 /*!
AnnaBridge 181:57724642e740 359 * @brief Check if the software for ARM core is done.
AnnaBridge 181:57724642e740 360 *
AnnaBridge 181:57724642e740 361 * @param base SRC peripheral base address.
AnnaBridge 181:57724642e740 362 * @return If the reset is done.
AnnaBridge 181:57724642e740 363 */
AnnaBridge 181:57724642e740 364 static inline bool SRC_GetSoftwareResetARMCoreDone(SRC_Type *base)
AnnaBridge 181:57724642e740 365 {
AnnaBridge 181:57724642e740 366 return (0U == (base->SCR & SRC_SCR_SWRC_MASK));
AnnaBridge 181:57724642e740 367 }
AnnaBridge 181:57724642e740 368 #endif /* FSL_FEATURE_SRC_HAS_SCR_SWRC */
AnnaBridge 181:57724642e740 369
AnnaBridge 181:57724642e740 370 #if (defined(FSL_FEATURE_SRC_HAS_SCR_EIM_RST) && FSL_FEATURE_SRC_HAS_SCR_EIM_RST)
AnnaBridge 181:57724642e740 371 /*!
AnnaBridge 181:57724642e740 372 * @brief Assert the EIM reset.
AnnaBridge 181:57724642e740 373 *
AnnaBridge 181:57724642e740 374 * EIM reset is needed in order to reconfigure the EIM chip select.
AnnaBridge 181:57724642e740 375 * The software reset bit must de-asserted since this is not self-refresh.
AnnaBridge 181:57724642e740 376 *
AnnaBridge 181:57724642e740 377 * @param base SRC peripheral base address.
AnnaBridge 181:57724642e740 378 * @param enable Make the assertion or not.
AnnaBridge 181:57724642e740 379 */
AnnaBridge 181:57724642e740 380 static inline void SRC_AssertEIMReset(SRC_Type *base, bool enable)
AnnaBridge 181:57724642e740 381 {
AnnaBridge 181:57724642e740 382 if (enable)
AnnaBridge 181:57724642e740 383 {
AnnaBridge 181:57724642e740 384 base->SCR |= SRC_SCR_EIM_RST_MASK;
AnnaBridge 181:57724642e740 385 }
AnnaBridge 181:57724642e740 386 else
AnnaBridge 181:57724642e740 387 {
AnnaBridge 181:57724642e740 388 base->SCR &= ~SRC_SCR_EIM_RST_MASK;
AnnaBridge 181:57724642e740 389 }
AnnaBridge 181:57724642e740 390 }
AnnaBridge 181:57724642e740 391 #endif /* FSL_FEATURE_SRC_HAS_SCR_EIM_RST */
AnnaBridge 181:57724642e740 392
AnnaBridge 181:57724642e740 393 /*!
AnnaBridge 181:57724642e740 394 * @brief Enable the WDOG Reset in SRC.
AnnaBridge 181:57724642e740 395 *
AnnaBridge 181:57724642e740 396 * WDOG Reset is enabled in SRC by default. If the WDOG event to SRC is masked, it would not create
AnnaBridge 181:57724642e740 397 * a reset to the chip. During the time the WDOG event is masked, when the WDOG event flag is
AnnaBridge 181:57724642e740 398 * asserted, it would remain asserted regardless of servicing the WDOG module. The only way to clear
AnnaBridge 181:57724642e740 399 * that bit is the hardware reset.
AnnaBridge 181:57724642e740 400 *
AnnaBridge 181:57724642e740 401 * @param base SRC peripheral base address.
AnnaBridge 181:57724642e740 402 * @param enable Enable the reset or not.
AnnaBridge 181:57724642e740 403 */
AnnaBridge 181:57724642e740 404 static inline void SRC_EnableWDOGReset(SRC_Type *base, bool enable)
AnnaBridge 181:57724642e740 405 {
AnnaBridge 181:57724642e740 406 if (enable) /* WDOG Reset is not masked in SRC (default). */
AnnaBridge 181:57724642e740 407 {
AnnaBridge 181:57724642e740 408 base->SCR = (base->SCR & ~SRC_SCR_MWDR_MASK) | SRC_SCR_MWDR(0xA);
AnnaBridge 181:57724642e740 409 }
AnnaBridge 181:57724642e740 410 else /* WDOG Reset is masked in SRC. */
AnnaBridge 181:57724642e740 411 {
AnnaBridge 181:57724642e740 412 base->SCR = (base->SCR & ~SRC_SCR_MWDR_MASK) | SRC_SCR_MWDR(0x5);
AnnaBridge 181:57724642e740 413 }
AnnaBridge 181:57724642e740 414 }
AnnaBridge 181:57724642e740 415
AnnaBridge 181:57724642e740 416 #if !(defined(FSL_FEATURE_SRC_HAS_NO_SCR_WRBC) && FSL_FEATURE_SRC_HAS_NO_SCR_WRBC)
AnnaBridge 181:57724642e740 417 /*!
AnnaBridge 181:57724642e740 418 * @brief Set the delay count of waiting MMDC's acknowledge.
AnnaBridge 181:57724642e740 419 *
AnnaBridge 181:57724642e740 420 * This function would define the 32KHz clock cycles to count before bypassing the MMDC acknowledge
AnnaBridge 181:57724642e740 421 * for WARM reset. If the MMDC acknowledge is not asserted before this counter is elapsed, a COLD
AnnaBridge 181:57724642e740 422 * reset will be initiated.
AnnaBridge 181:57724642e740 423 *
AnnaBridge 181:57724642e740 424 * @param base SRC peripheral base address.
AnnaBridge 181:57724642e740 425 * @param option The option of setting mode, see to #src_warm_reset_bypass_count_t.
AnnaBridge 181:57724642e740 426 */
AnnaBridge 181:57724642e740 427 static inline void SRC_SetWarmResetBypassCount(SRC_Type *base, src_warm_reset_bypass_count_t option)
AnnaBridge 181:57724642e740 428 {
AnnaBridge 181:57724642e740 429 base->SCR = (base->SCR & ~SRC_SCR_WRBC_MASK) | SRC_SCR_WRBC(option);
AnnaBridge 181:57724642e740 430 }
AnnaBridge 181:57724642e740 431 #endif /* FSL_FEATURE_SRC_HAS_NO_SCR_WRBC */
AnnaBridge 181:57724642e740 432
AnnaBridge 181:57724642e740 433 #if (defined(FSL_FEATURE_SRC_HAS_SCR_LOCKUP_RST) && FSL_FEATURE_SRC_HAS_SCR_LOCKUP_RST)
AnnaBridge 181:57724642e740 434 /*!
AnnaBridge 181:57724642e740 435 * @brief Enable the lockup reset.
AnnaBridge 181:57724642e740 436 *
AnnaBridge 181:57724642e740 437 * @param base SRC peripheral base address.
AnnaBridge 181:57724642e740 438 * @param enable Enable the reset or not.
AnnaBridge 181:57724642e740 439 */
AnnaBridge 181:57724642e740 440 static inline void SRC_EnableLockupReset(SRC_Type *base, bool enable)
AnnaBridge 181:57724642e740 441 {
AnnaBridge 181:57724642e740 442 if (enable) /* Enable lockup reset. */
AnnaBridge 181:57724642e740 443 {
AnnaBridge 181:57724642e740 444 base->SCR |= SRC_SCR_LOCKUP_RST_MASK;
AnnaBridge 181:57724642e740 445 }
AnnaBridge 181:57724642e740 446 else /* Disable lockup reset. */
AnnaBridge 181:57724642e740 447 {
AnnaBridge 181:57724642e740 448 base->SCR &= ~SRC_SCR_LOCKUP_RST_MASK;
AnnaBridge 181:57724642e740 449 }
AnnaBridge 181:57724642e740 450 }
AnnaBridge 181:57724642e740 451 #endif /* FSL_FEATURE_SRC_HAS_SCR_LOCKUP_RST */
AnnaBridge 181:57724642e740 452
AnnaBridge 181:57724642e740 453 #if (defined(FSL_FEATURE_SRC_HAS_SCR_LUEN) && FSL_FEATURE_SRC_HAS_SCR_LUEN)
AnnaBridge 181:57724642e740 454 /*!
AnnaBridge 181:57724642e740 455 * @brief Enable the core lockup reset.
AnnaBridge 181:57724642e740 456 *
AnnaBridge 181:57724642e740 457 * When enable the core luckup reset, the system would be reset when core luckup event happens.
AnnaBridge 181:57724642e740 458 *
AnnaBridge 181:57724642e740 459 * @param base SRC peripheral base address.
AnnaBridge 181:57724642e740 460 * @param enable Enable the reset or not.
AnnaBridge 181:57724642e740 461 */
AnnaBridge 181:57724642e740 462 static inline void SRC_EnableCoreLockupReset(SRC_Type *base, bool enable)
AnnaBridge 181:57724642e740 463 {
AnnaBridge 181:57724642e740 464 if (enable) /* Core lockup will cause system reset. */
AnnaBridge 181:57724642e740 465 {
AnnaBridge 181:57724642e740 466 base->SCR |= SRC_SCR_LUEN_MASK;
AnnaBridge 181:57724642e740 467 }
AnnaBridge 181:57724642e740 468 else /* Core lockup will not cause system reset. */
AnnaBridge 181:57724642e740 469 {
AnnaBridge 181:57724642e740 470 base->SCR &= ~SRC_SCR_LUEN_MASK;
AnnaBridge 181:57724642e740 471 }
AnnaBridge 181:57724642e740 472 }
AnnaBridge 181:57724642e740 473 #endif /* FSL_FEATURE_SRC_HAS_SCR_LUEN */
AnnaBridge 181:57724642e740 474
AnnaBridge 181:57724642e740 475 #if !(defined(FSL_FEATURE_SRC_HAS_NO_SCR_WRE) && FSL_FEATURE_SRC_HAS_NO_SCR_WRE)
AnnaBridge 181:57724642e740 476 /*!
AnnaBridge 181:57724642e740 477 * @brief Enable the WARM reset.
AnnaBridge 181:57724642e740 478 *
AnnaBridge 181:57724642e740 479 * Only when the WARM reset is enabled, the WARM reset requests would be served by WARM reset.
AnnaBridge 181:57724642e740 480 * Otherwise, all the WARM reset sources would generate COLD reset.
AnnaBridge 181:57724642e740 481 *
AnnaBridge 181:57724642e740 482 * @param base SRC peripheral base address.
AnnaBridge 181:57724642e740 483 * @param enable Enable the WARM reset or not.
AnnaBridge 181:57724642e740 484 */
AnnaBridge 181:57724642e740 485 static inline void SRC_EnableWarmReset(SRC_Type *base, bool enable)
AnnaBridge 181:57724642e740 486 {
AnnaBridge 181:57724642e740 487 if (enable)
AnnaBridge 181:57724642e740 488 {
AnnaBridge 181:57724642e740 489 base->SCR |= SRC_SCR_WRE_MASK;
AnnaBridge 181:57724642e740 490 }
AnnaBridge 181:57724642e740 491 else
AnnaBridge 181:57724642e740 492 {
AnnaBridge 181:57724642e740 493 base->SCR &= ~SRC_SCR_WRE_MASK;
AnnaBridge 181:57724642e740 494 }
AnnaBridge 181:57724642e740 495 }
AnnaBridge 181:57724642e740 496 #endif /* FSL_FEATURE_SRC_HAS_NO_SCR_WRE */
AnnaBridge 181:57724642e740 497
AnnaBridge 181:57724642e740 498 #if (defined(FSL_FEATURE_SRC_HAS_SISR) && FSL_FEATURE_SRC_HAS_SISR)
AnnaBridge 181:57724642e740 499 /*!
AnnaBridge 181:57724642e740 500 * @brief Get interrupt status flags.
AnnaBridge 181:57724642e740 501 *
AnnaBridge 181:57724642e740 502 * @param base SRC peripheral base address.
AnnaBridge 181:57724642e740 503 * @return Mask value of status flags. See to $_src_status_flags.
AnnaBridge 181:57724642e740 504 */
AnnaBridge 181:57724642e740 505 static inline uint32_t SRC_GetStatusFlags(SRC_Type *base)
AnnaBridge 181:57724642e740 506 {
AnnaBridge 181:57724642e740 507 return base->SISR;
AnnaBridge 181:57724642e740 508 }
AnnaBridge 181:57724642e740 509 #endif /* FSL_FEATURE_SRC_HAS_SISR */
AnnaBridge 181:57724642e740 510
AnnaBridge 181:57724642e740 511 /*!
AnnaBridge 181:57724642e740 512 * @brief Get the boot mode register 1 value.
AnnaBridge 181:57724642e740 513 *
AnnaBridge 181:57724642e740 514 * The Boot Mode register contains bits that reflect the status of BOOT_CFGx pins of the chip.
AnnaBridge 181:57724642e740 515 * See to chip-specific document for detail information about value.
AnnaBridge 181:57724642e740 516 *
AnnaBridge 181:57724642e740 517 * @param base SRC peripheral base address.
AnnaBridge 181:57724642e740 518 * @return status of BOOT_CFGx pins of the chip.
AnnaBridge 181:57724642e740 519 */
AnnaBridge 181:57724642e740 520 static inline uint32_t SRC_GetBootModeWord1(SRC_Type *base)
AnnaBridge 181:57724642e740 521 {
AnnaBridge 181:57724642e740 522 return base->SBMR1;
AnnaBridge 181:57724642e740 523 }
AnnaBridge 181:57724642e740 524
AnnaBridge 181:57724642e740 525 /*!
AnnaBridge 181:57724642e740 526 * @brief Get the boot mode register 2 value.
AnnaBridge 181:57724642e740 527 *
AnnaBridge 181:57724642e740 528 * The Boot Mode register contains bits that reflect the status of BOOT_MODEx Pins and fuse values
AnnaBridge 181:57724642e740 529 * that controls boot of the chip. See to chip-specific document for detail information about value.
AnnaBridge 181:57724642e740 530 *
AnnaBridge 181:57724642e740 531 * @param base SRC peripheral base address.
AnnaBridge 181:57724642e740 532 * @return status of BOOT_MODEx Pins and fuse values that controls boot of the chip.
AnnaBridge 181:57724642e740 533 */
AnnaBridge 181:57724642e740 534 static inline uint32_t SRC_GetBootModeWord2(SRC_Type *base)
AnnaBridge 181:57724642e740 535 {
AnnaBridge 181:57724642e740 536 return base->SBMR2;
AnnaBridge 181:57724642e740 537 }
AnnaBridge 181:57724642e740 538
AnnaBridge 181:57724642e740 539 #if !(defined(FSL_FEATURE_SRC_HAS_NO_SRSR_WBI) && FSL_FEATURE_SRC_HAS_NO_SRSR_WBI)
AnnaBridge 181:57724642e740 540 /*!
AnnaBridge 181:57724642e740 541 * @brief Set the warm boot indication flag.
AnnaBridge 181:57724642e740 542 *
AnnaBridge 181:57724642e740 543 * WARM boot indication shows that WARM boot was initiated by software. This indicates to the
AnnaBridge 181:57724642e740 544 * software that it saved the needed information in the memory before initiating the WARM reset.
AnnaBridge 181:57724642e740 545 * In this case, software will set this bit to '1', before initiating the WARM reset. The warm_boot
AnnaBridge 181:57724642e740 546 * bit should be used as indication only after a warm_reset sequence. Software should clear this bit
AnnaBridge 181:57724642e740 547 * after warm_reset to indicate that the next warm_reset is not performed with warm_boot.
AnnaBridge 181:57724642e740 548 *
AnnaBridge 181:57724642e740 549 * @param base SRC peripheral base address.
AnnaBridge 181:57724642e740 550 * @param enable Assert the flag or not.
AnnaBridge 181:57724642e740 551 */
AnnaBridge 181:57724642e740 552 static inline void SRC_SetWarmBootIndication(SRC_Type *base, bool enable)
AnnaBridge 181:57724642e740 553 {
AnnaBridge 181:57724642e740 554 if (enable)
AnnaBridge 181:57724642e740 555 {
AnnaBridge 181:57724642e740 556 base->SRSR = (base->SRSR & ~SRC_SRSR_W1C_BITS_MASK) | SRC_SRSR_WBI_MASK;
AnnaBridge 181:57724642e740 557 }
AnnaBridge 181:57724642e740 558 else
AnnaBridge 181:57724642e740 559 {
AnnaBridge 181:57724642e740 560 base->SRSR = (base->SRSR & ~SRC_SRSR_W1C_BITS_MASK) & ~SRC_SRSR_WBI_MASK;
AnnaBridge 181:57724642e740 561 }
AnnaBridge 181:57724642e740 562 }
AnnaBridge 181:57724642e740 563 #endif /* FSL_FEATURE_SRC_HAS_NO_SRSR_WBI */
AnnaBridge 181:57724642e740 564
AnnaBridge 181:57724642e740 565 /*!
AnnaBridge 181:57724642e740 566 * @brief Get the status flags of SRC.
AnnaBridge 181:57724642e740 567 *
AnnaBridge 181:57724642e740 568 * @param base SRC peripheral base address.
AnnaBridge 181:57724642e740 569 * @return Mask value of status flags, see to #_src_reset_status_flags.
AnnaBridge 181:57724642e740 570 */
AnnaBridge 181:57724642e740 571 static inline uint32_t SRC_GetResetStatusFlags(SRC_Type *base)
AnnaBridge 181:57724642e740 572 {
AnnaBridge 181:57724642e740 573 return base->SRSR;
AnnaBridge 181:57724642e740 574 }
AnnaBridge 181:57724642e740 575
AnnaBridge 181:57724642e740 576 /*!
AnnaBridge 181:57724642e740 577 * @brief Clear the status flags of SRC.
AnnaBridge 181:57724642e740 578 *
AnnaBridge 181:57724642e740 579 * @param base SRC peripheral base address.
AnnaBridge 181:57724642e740 580 * @param Mask value of status flags to be cleared, see to #_src_reset_status_flags.
AnnaBridge 181:57724642e740 581 */
AnnaBridge 181:57724642e740 582 void SRC_ClearResetStatusFlags(SRC_Type *base, uint32_t flags);
AnnaBridge 181:57724642e740 583
AnnaBridge 181:57724642e740 584 /*!
AnnaBridge 181:57724642e740 585 * @brief Set value to general purpose registers.
AnnaBridge 181:57724642e740 586 *
AnnaBridge 181:57724642e740 587 * General purpose registers (GPRx) would hold the value during reset process. Wakeup function could
AnnaBridge 181:57724642e740 588 * be kept in these register. For example, the GPR1 holds the entry function for waking-up from
AnnaBridge 181:57724642e740 589 * Partial SLEEP mode while the GPR2 holds the argument. Other GPRx register would store the
AnnaBridge 181:57724642e740 590 * arbitray values.
AnnaBridge 181:57724642e740 591 *
AnnaBridge 181:57724642e740 592 * @param base SRC peripheral base address.
AnnaBridge 181:57724642e740 593 * @param index The index of GPRx register array. Note index 0 reponses the GPR1 register.
AnnaBridge 181:57724642e740 594 * @param value Setting value for GPRx register.
AnnaBridge 181:57724642e740 595 */
AnnaBridge 181:57724642e740 596 static inline void SRC_SetGeneralPurposeRegister(SRC_Type *base, uint32_t index, uint32_t value)
AnnaBridge 181:57724642e740 597 {
AnnaBridge 181:57724642e740 598 assert(index < SRC_GPR_COUNT);
AnnaBridge 181:57724642e740 599
AnnaBridge 181:57724642e740 600 base->GPR[index] = value;
AnnaBridge 181:57724642e740 601 }
AnnaBridge 181:57724642e740 602
AnnaBridge 181:57724642e740 603 /*!
AnnaBridge 181:57724642e740 604 * @brief Get the value from general purpose registers.
AnnaBridge 181:57724642e740 605 *
AnnaBridge 181:57724642e740 606 * @param base SRC peripheral base address.
AnnaBridge 181:57724642e740 607 * @param index The index of GPRx register array. Note index 0 reponses the GPR1 register.
AnnaBridge 181:57724642e740 608 * @return The setting value for GPRx register.
AnnaBridge 181:57724642e740 609 */
AnnaBridge 181:57724642e740 610 static inline uint32_t SRC_GetGeneralPurposeRegister(SRC_Type *base, uint32_t index)
AnnaBridge 181:57724642e740 611 {
AnnaBridge 181:57724642e740 612 assert(index < SRC_GPR_COUNT);
AnnaBridge 181:57724642e740 613
AnnaBridge 181:57724642e740 614 return base->GPR[index];
AnnaBridge 181:57724642e740 615 }
AnnaBridge 181:57724642e740 616
AnnaBridge 181:57724642e740 617 #if defined(__cplusplus)
AnnaBridge 181:57724642e740 618 }
AnnaBridge 181:57724642e740 619 #endif
AnnaBridge 181:57724642e740 620 /*!
AnnaBridge 181:57724642e740 621 * @}
AnnaBridge 181:57724642e740 622 */
AnnaBridge 181:57724642e740 623 #endif /* _FSL_SRC_H_ */