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targets/TARGET_NUVOTON/TARGET_M480/device/StdDriver/m480_spim.h@189:f392fc9709a3, 2019-02-20 (annotated)
- Committer:
- AnnaBridge
- Date:
- Wed Feb 20 22:31:08 2019 +0000
- Revision:
- 189:f392fc9709a3
- Parent:
- 172:7d866c31b3c5
mbed library release version 165
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| AnnaBridge | 172:7d866c31b3c5 | 1 | /**************************************************************************//** |
| AnnaBridge | 172:7d866c31b3c5 | 2 | * @file spim.h |
| AnnaBridge | 172:7d866c31b3c5 | 3 | * @version V1.00 |
| AnnaBridge | 172:7d866c31b3c5 | 4 | * @brief M480 series SPIM driver header file |
| AnnaBridge | 172:7d866c31b3c5 | 5 | * |
| AnnaBridge | 172:7d866c31b3c5 | 6 | * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved. |
| AnnaBridge | 172:7d866c31b3c5 | 7 | *****************************************************************************/ |
| AnnaBridge | 172:7d866c31b3c5 | 8 | #ifndef __SPIM_H__ |
| AnnaBridge | 172:7d866c31b3c5 | 9 | #define __SPIM_H__ |
| AnnaBridge | 172:7d866c31b3c5 | 10 | |
| AnnaBridge | 172:7d866c31b3c5 | 11 | /*---------------------------------------------------------------------------------------------------------*/ |
| AnnaBridge | 172:7d866c31b3c5 | 12 | /* Include related headers */ |
| AnnaBridge | 172:7d866c31b3c5 | 13 | /*---------------------------------------------------------------------------------------------------------*/ |
| AnnaBridge | 172:7d866c31b3c5 | 14 | |
| AnnaBridge | 172:7d866c31b3c5 | 15 | #ifdef __cplusplus |
| AnnaBridge | 172:7d866c31b3c5 | 16 | extern "C" |
| AnnaBridge | 172:7d866c31b3c5 | 17 | { |
| AnnaBridge | 172:7d866c31b3c5 | 18 | #endif |
| AnnaBridge | 172:7d866c31b3c5 | 19 | |
| AnnaBridge | 172:7d866c31b3c5 | 20 | |
| AnnaBridge | 172:7d866c31b3c5 | 21 | /** @addtogroup M480_Device_Driver M480 Device Driver |
| AnnaBridge | 172:7d866c31b3c5 | 22 | @{ |
| AnnaBridge | 172:7d866c31b3c5 | 23 | */ |
| AnnaBridge | 172:7d866c31b3c5 | 24 | |
| AnnaBridge | 172:7d866c31b3c5 | 25 | /** @addtogroup M480_SPIM_Driver SPIM Driver |
| AnnaBridge | 172:7d866c31b3c5 | 26 | @{ |
| AnnaBridge | 172:7d866c31b3c5 | 27 | */ |
| AnnaBridge | 172:7d866c31b3c5 | 28 | |
| AnnaBridge | 172:7d866c31b3c5 | 29 | |
| AnnaBridge | 172:7d866c31b3c5 | 30 | /** @addtogroup M480_SPIM_EXPORTED_CONSTANTS SPIM Exported Constants |
| AnnaBridge | 172:7d866c31b3c5 | 31 | @{ |
| AnnaBridge | 172:7d866c31b3c5 | 32 | */ |
| AnnaBridge | 172:7d866c31b3c5 | 33 | |
| AnnaBridge | 172:7d866c31b3c5 | 34 | #define SPIM_DMM_MAP_ADDR 0x8000000UL /*!< DMM mode memory map base address \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 35 | #define SPIM_DMM_SIZE 0x2000000UL /*!< DMM mode memory mapping size \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 36 | #define SPIM_CCM_ADDR 0x20020000UL /*!< CCM mode memory map base address \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 37 | #define SPIM_CCM_SIZE 0x8000UL /*!< CCM mode memory size \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 38 | |
| AnnaBridge | 172:7d866c31b3c5 | 39 | /*---------------------------------------------------------------------------------------------------------*/ |
| AnnaBridge | 172:7d866c31b3c5 | 40 | /* SPIM_CTL0 constant definitions */ |
| AnnaBridge | 172:7d866c31b3c5 | 41 | /*---------------------------------------------------------------------------------------------------------*/ |
| AnnaBridge | 172:7d866c31b3c5 | 42 | #define SPIM_CTL0_RW_IN(x) ((x) ? 0UL : (0x1UL << SPIM_CTL0_QDIODIR_Pos)) /*!< SPIM_CTL0: SPI Interface Direction Select \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 43 | #define SPIM_CTL0_BITMODE_SING (0UL << SPIM_CTL0_BITMODE_Pos) /*!< SPIM_CTL0: One bit mode (SPI Interface including DO, DI, HOLD, WP) \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 44 | #define SPIM_CTL0_BITMODE_DUAL (1UL << SPIM_CTL0_BITMODE_Pos) /*!< SPIM_CTL0: Two bits mode (SPI Interface including D0, D1, HOLD, WP) \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 45 | #define SPIM_CTL0_BITMODE_QUAD (2UL << SPIM_CTL0_BITMODE_Pos) /*!< SPIM_CTL0: Four bits mode (SPI Interface including D0, D1, D2, D3) \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 46 | #define SPIM_CTL0_OPMODE_IO (0UL << SPIM_CTL0_OPMODE_Pos) /*!< SPIM_CTL0: I/O Mode \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 47 | #define SPIM_CTL0_OPMODE_PAGEWRITE (1UL << SPIM_CTL0_OPMODE_Pos) /*!< SPIM_CTL0: Page Write Mode \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 48 | #define SPIM_CTL0_OPMODE_PAGEREAD (2UL << SPIM_CTL0_OPMODE_Pos) /*!< SPIM_CTL0: Page Read Mode \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 49 | #define SPIM_CTL0_OPMODE_DIRECTMAP (3UL << SPIM_CTL0_OPMODE_Pos) /*!< SPIM_CTL0: Direct Map Mode \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 50 | |
| AnnaBridge | 172:7d866c31b3c5 | 51 | #define CMD_NORMAL_PAGE_PROGRAM (0x02UL << SPIM_CTL0_CMDCODE_Pos) /*!< SPIM_CTL0: Page Program (Page Write Mode Use) \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 52 | #define CMD_NORMAL_PAGE_PROGRAM_4B (0x12UL << SPIM_CTL0_CMDCODE_Pos) /*!< SPIM_CTL0: Page Program (Page Write Mode Use) \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 53 | #define CMD_QUAD_PAGE_PROGRAM_WINBOND (0x32UL << SPIM_CTL0_CMDCODE_Pos) /*!< SPIM_CTL0: Quad Page program (for Winbond) (Page Write Mode Use) \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 54 | #define CMD_QUAD_PAGE_PROGRAM_MXIC (0x38UL << SPIM_CTL0_CMDCODE_Pos) /*!< SPIM_CTL0: Quad Page program (for MXIC) (Page Write Mode Use) \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 55 | #define CMD_QUAD_PAGE_PROGRAM_EON (0x40UL << SPIM_CTL0_CMDCODE_Pos) /*!< SPIM_CTL0: Quad Page Program (for EON) (Page Write Mode Use) \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 56 | |
| AnnaBridge | 172:7d866c31b3c5 | 57 | #define CMD_DMA_NORMAL_READ (0x03UL << SPIM_CTL0_CMDCODE_Pos) /*!< SPIM_CTL0: Read Data (Page Read Mode Use) \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 58 | #define CMD_DMA_FAST_READ (0x0BUL << SPIM_CTL0_CMDCODE_Pos) /*!< SPIM_CTL0: Fast Read (Page Read Mode Use) \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 59 | #define CMD_DMA_NORMAL_DUAL_READ (0x3BUL << SPIM_CTL0_CMDCODE_Pos) /*!< SPIM_CTL0: Fast Read Dual Output (Page Read Mode Use) \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 60 | #define CMD_DMA_FAST_READ_DUAL_OUTPUT (0x3BUL << SPIM_CTL0_CMDCODE_Pos) /*!< SPIM_CTL0: Fast Read Dual Output (Page Read Mode Use) \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 61 | #define CMD_DMA_FAST_READ_QUAD_OUTPUT (0x6BUL << SPIM_CTL0_CMDCODE_Pos) /*!< SPIM_CTL0: Fast Read Dual Output (Page Read Mode Use) \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 62 | #define CMD_DMA_FAST_DUAL_READ (0xBBUL << SPIM_CTL0_CMDCODE_Pos) /*!< SPIM_CTL0: Fast Read Dual Output (Page Read Mode Use) \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 63 | #define CMD_DMA_NORMAL_QUAD_READ (0xE7UL << SPIM_CTL0_CMDCODE_Pos) /*!< SPIM_CTL0: Fast Read Quad I/O (Page Read Mode Use) \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 64 | #define CMD_DMA_FAST_QUAD_READ (0xEBUL << SPIM_CTL0_CMDCODE_Pos) /*!< SPIM_CTL0: Fast Read Quad I/O (Page Read Mode Use) \hideinitializer */ |
| AnnaBridge | 172:7d866c31b3c5 | 65 | |
| AnnaBridge | 172:7d866c31b3c5 | 66 | /** @cond HIDDEN_SYMBOLS */ |
| AnnaBridge | 172:7d866c31b3c5 | 67 | |
| AnnaBridge | 172:7d866c31b3c5 | 68 | typedef enum { |
| AnnaBridge | 172:7d866c31b3c5 | 69 | MFGID_UNKNOW = 0x00U, |
| AnnaBridge | 172:7d866c31b3c5 | 70 | MFGID_SPANSION = 0x01U, |
| AnnaBridge | 172:7d866c31b3c5 | 71 | MFGID_EON = 0x1CU, |
| AnnaBridge | 172:7d866c31b3c5 | 72 | MFGID_ISSI = 0x7FU, |
| AnnaBridge | 172:7d866c31b3c5 | 73 | MFGID_MXIC = 0xC2U, |
| AnnaBridge | 172:7d866c31b3c5 | 74 | MFGID_WINBOND = 0xEFU |
| AnnaBridge | 172:7d866c31b3c5 | 75 | } |
| AnnaBridge | 172:7d866c31b3c5 | 76 | E_MFGID; |
| AnnaBridge | 172:7d866c31b3c5 | 77 | |
| AnnaBridge | 172:7d866c31b3c5 | 78 | /* Flash opcodes. */ |
| AnnaBridge | 172:7d866c31b3c5 | 79 | #define OPCODE_WREN 0x06U /* Write enable */ |
| AnnaBridge | 172:7d866c31b3c5 | 80 | #define OPCODE_RDSR 0x05U /* Read status register #1*/ |
| AnnaBridge | 172:7d866c31b3c5 | 81 | #define OPCODE_WRSR 0x01U /* Write status register #1 */ |
| AnnaBridge | 172:7d866c31b3c5 | 82 | #define OPCODE_RDSR2 0x35U /* Read status register #2*/ |
| AnnaBridge | 172:7d866c31b3c5 | 83 | #define OPCODE_WRSR2 0x31U /* Write status register #2 */ |
| AnnaBridge | 172:7d866c31b3c5 | 84 | #define OPCODE_RDSR3 0x15U /* Read status register #3*/ |
| AnnaBridge | 172:7d866c31b3c5 | 85 | #define OPCODE_WRSR3 0x11U /* Write status register #3 */ |
| AnnaBridge | 172:7d866c31b3c5 | 86 | #define OPCODE_PP 0x02U /* Page program (up to 256 bytes) */ |
| AnnaBridge | 172:7d866c31b3c5 | 87 | #define OPCODE_SE_4K 0x20U /* Erase 4KB sector */ |
| AnnaBridge | 172:7d866c31b3c5 | 88 | #define OPCODE_BE_32K 0x52U /* Erase 32KB block */ |
| AnnaBridge | 172:7d866c31b3c5 | 89 | #define OPCODE_CHIP_ERASE 0xc7U /* Erase whole flash chip */ |
| AnnaBridge | 172:7d866c31b3c5 | 90 | #define OPCODE_BE_64K 0xd8U /* Erase 64KB block */ |
| AnnaBridge | 172:7d866c31b3c5 | 91 | #define OPCODE_READ_ID 0x90U /* Read ID */ |
| AnnaBridge | 172:7d866c31b3c5 | 92 | #define OPCODE_RDID 0x9fU /* Read JEDEC ID */ |
| AnnaBridge | 172:7d866c31b3c5 | 93 | #define OPCODE_BRRD 0x16U /* SPANSION flash - Bank Register Read command */ |
| AnnaBridge | 172:7d866c31b3c5 | 94 | #define OPCODE_BRWR 0x17U /* SPANSION flash - Bank Register write command */ |
| AnnaBridge | 172:7d866c31b3c5 | 95 | #define OPCODE_NORM_READ 0x03U /* Read data bytes */ |
| AnnaBridge | 172:7d866c31b3c5 | 96 | #define OPCODE_FAST_READ 0x0bU /* Read data bytes */ |
| AnnaBridge | 172:7d866c31b3c5 | 97 | #define OPCODE_FAST_DUAL_READ 0x3bU /* Read data bytes */ |
| AnnaBridge | 172:7d866c31b3c5 | 98 | #define OPCODE_FAST_QUAD_READ 0x6bU /* Read data bytes */ |
| AnnaBridge | 172:7d866c31b3c5 | 99 | |
| AnnaBridge | 172:7d866c31b3c5 | 100 | /* Used for SST flashes only. */ |
| AnnaBridge | 172:7d866c31b3c5 | 101 | #define OPCODE_BP 0x02U /* Byte program */ |
| AnnaBridge | 172:7d866c31b3c5 | 102 | #define OPCODE_WRDI 0x04U /* Write disable */ |
| AnnaBridge | 172:7d866c31b3c5 | 103 | #define OPCODE_AAI_WP 0xadU /* Auto u32Address increment word program */ |
| AnnaBridge | 172:7d866c31b3c5 | 104 | |
| AnnaBridge | 172:7d866c31b3c5 | 105 | /* Used for Macronix flashes only. */ |
| AnnaBridge | 172:7d866c31b3c5 | 106 | #define OPCODE_EN4B 0xb7U /* Enter 4-byte mode */ |
| AnnaBridge | 172:7d866c31b3c5 | 107 | #define OPCODE_EX4B 0xe9U /* Exit 4-byte mode */ |
| AnnaBridge | 172:7d866c31b3c5 | 108 | |
| AnnaBridge | 172:7d866c31b3c5 | 109 | #define OPCODE_RDSCUR 0x2bU |
| AnnaBridge | 172:7d866c31b3c5 | 110 | #define OPCODE_WRSCUR 0x2fU |
| AnnaBridge | 172:7d866c31b3c5 | 111 | |
| AnnaBridge | 172:7d866c31b3c5 | 112 | #define OPCODE_RSTEN 0x66U |
| AnnaBridge | 172:7d866c31b3c5 | 113 | #define OPCODE_RST 0x99U |
| AnnaBridge | 172:7d866c31b3c5 | 114 | |
| AnnaBridge | 172:7d866c31b3c5 | 115 | #define OPCODE_ENQPI 0x38U |
| AnnaBridge | 172:7d866c31b3c5 | 116 | #define OPCODE_EXQPI 0xFFU |
| AnnaBridge | 172:7d866c31b3c5 | 117 | |
| AnnaBridge | 172:7d866c31b3c5 | 118 | /* Status Register bits. */ |
| AnnaBridge | 172:7d866c31b3c5 | 119 | #define SR_WIP 0x1U /* Write in progress */ |
| AnnaBridge | 172:7d866c31b3c5 | 120 | #define SR_WEL 0x2U /* Write enable latch */ |
| AnnaBridge | 172:7d866c31b3c5 | 121 | #define SR_QE 0x40U /* Quad Enable for MXIC */ |
| AnnaBridge | 172:7d866c31b3c5 | 122 | /* Status Register #2 bits. */ |
| AnnaBridge | 172:7d866c31b3c5 | 123 | #define SR2_QE 0x2U /* Quad Enable for Winbond */ |
| AnnaBridge | 172:7d866c31b3c5 | 124 | /* meaning of other SR_* bits may differ between vendors */ |
| AnnaBridge | 172:7d866c31b3c5 | 125 | #define SR_BP0 0x4U /* Block protect 0 */ |
| AnnaBridge | 172:7d866c31b3c5 | 126 | #define SR_BP1 0x8U /* Block protect 1 */ |
| AnnaBridge | 172:7d866c31b3c5 | 127 | #define SR_BP2 0x10U /* Block protect 2 */ |
| AnnaBridge | 172:7d866c31b3c5 | 128 | #define SR_SRWD 0x80U /* SR write protect */ |
| AnnaBridge | 172:7d866c31b3c5 | 129 | #define SR3_ADR 0x01U /* 4-byte u32Address mode */ |
| AnnaBridge | 172:7d866c31b3c5 | 130 | |
| AnnaBridge | 172:7d866c31b3c5 | 131 | #define SCUR_4BYTE 0x04U /* 4-byte u32Address mode */ |
| AnnaBridge | 172:7d866c31b3c5 | 132 | |
| AnnaBridge | 172:7d866c31b3c5 | 133 | /** @endcond HIDDEN_SYMBOLS */ |
| AnnaBridge | 172:7d866c31b3c5 | 134 | |
| AnnaBridge | 172:7d866c31b3c5 | 135 | /*@}*/ /* end of group M480_SPIM_EXPORTED_CONSTANTS */ |
| AnnaBridge | 172:7d866c31b3c5 | 136 | |
| AnnaBridge | 172:7d866c31b3c5 | 137 | |
| AnnaBridge | 172:7d866c31b3c5 | 138 | /** @addtogroup M480_SPIM_EXPORTED_FUNCTIONS SPIM Exported Functions |
| AnnaBridge | 172:7d866c31b3c5 | 139 | @{ |
| AnnaBridge | 172:7d866c31b3c5 | 140 | */ |
| AnnaBridge | 172:7d866c31b3c5 | 141 | |
| AnnaBridge | 172:7d866c31b3c5 | 142 | |
| AnnaBridge | 172:7d866c31b3c5 | 143 | /*---------------------------------------------------------------------------------------------------------*/ |
| AnnaBridge | 172:7d866c31b3c5 | 144 | /* Define Macros and functions */ |
| AnnaBridge | 172:7d866c31b3c5 | 145 | /*---------------------------------------------------------------------------------------------------------*/ |
| AnnaBridge | 172:7d866c31b3c5 | 146 | |
| AnnaBridge | 172:7d866c31b3c5 | 147 | /** |
| AnnaBridge | 172:7d866c31b3c5 | 148 | * @details Enable cipher. |
| AnnaBridge | 172:7d866c31b3c5 | 149 | * \hideinitializer |
| AnnaBridge | 172:7d866c31b3c5 | 150 | */ |
| AnnaBridge | 172:7d866c31b3c5 | 151 | #define SPIM_ENABLE_CIPHER() (SPIM->CTL0 &= ~SPIM_CTL0_CIPHOFF_Msk) |
| AnnaBridge | 172:7d866c31b3c5 | 152 | |
| AnnaBridge | 172:7d866c31b3c5 | 153 | /** |
| AnnaBridge | 172:7d866c31b3c5 | 154 | * @details Disable cipher. |
| AnnaBridge | 172:7d866c31b3c5 | 155 | * \hideinitializer |
| AnnaBridge | 172:7d866c31b3c5 | 156 | */ |
| AnnaBridge | 172:7d866c31b3c5 | 157 | #define SPIM_DISABLE_CIPHER() (SPIM->CTL0 |= SPIM_CTL0_CIPHOFF_Msk) |
| AnnaBridge | 172:7d866c31b3c5 | 158 | |
| AnnaBridge | 172:7d866c31b3c5 | 159 | /** |
| AnnaBridge | 172:7d866c31b3c5 | 160 | * @details Enable cipher balance |
| AnnaBridge | 172:7d866c31b3c5 | 161 | * \hideinitializer |
| AnnaBridge | 172:7d866c31b3c5 | 162 | */ |
| AnnaBridge | 172:7d866c31b3c5 | 163 | #define SPIM_ENABLE_BALEN() (SPIM->CTL0 |= SPIM_CTL0_BALEN_Msk) |
| AnnaBridge | 172:7d866c31b3c5 | 164 | |
| AnnaBridge | 172:7d866c31b3c5 | 165 | /** |
| AnnaBridge | 172:7d866c31b3c5 | 166 | * @details Disable cipher balance |
| AnnaBridge | 172:7d866c31b3c5 | 167 | * \hideinitializer |
| AnnaBridge | 172:7d866c31b3c5 | 168 | */ |
| AnnaBridge | 172:7d866c31b3c5 | 169 | #define SPIM_DISABLE_BALEN() (SPIM->CTL0 &= ~SPIM_CTL0_BALEN_Msk) |
| AnnaBridge | 172:7d866c31b3c5 | 170 | |
| AnnaBridge | 172:7d866c31b3c5 | 171 | /** |
| AnnaBridge | 172:7d866c31b3c5 | 172 | * @details Set 4-byte address to be enabled/disabled. |
| AnnaBridge | 172:7d866c31b3c5 | 173 | * \hideinitializer |
| AnnaBridge | 172:7d866c31b3c5 | 174 | */ |
| AnnaBridge | 172:7d866c31b3c5 | 175 | #define SPIM_SET_4BYTE_ADDR_EN(x) \ |
| AnnaBridge | 172:7d866c31b3c5 | 176 | do { \ |
| AnnaBridge | 172:7d866c31b3c5 | 177 | SPIM->CTL0 = (SPIM->CTL0 & (~SPIM_CTL0_B4ADDREN_Msk)) | (((x) ? 1UL : 0UL) << SPIM_CTL0_B4ADDREN_Pos); \ |
| AnnaBridge | 172:7d866c31b3c5 | 178 | } while (0) |
| AnnaBridge | 172:7d866c31b3c5 | 179 | |
| AnnaBridge | 172:7d866c31b3c5 | 180 | /** |
| AnnaBridge | 172:7d866c31b3c5 | 181 | * @details Enable SPIM interrupt |
| AnnaBridge | 172:7d866c31b3c5 | 182 | * \hideinitializer |
| AnnaBridge | 172:7d866c31b3c5 | 183 | */ |
| AnnaBridge | 172:7d866c31b3c5 | 184 | #define SPIM_ENABLE_INT() (SPIM->CTL0 |= SPIM_CTL0_IEN_Msk) |
| AnnaBridge | 172:7d866c31b3c5 | 185 | |
| AnnaBridge | 172:7d866c31b3c5 | 186 | /** |
| AnnaBridge | 172:7d866c31b3c5 | 187 | * @details Disable SPIM interrupt |
| AnnaBridge | 172:7d866c31b3c5 | 188 | * \hideinitializer |
| AnnaBridge | 172:7d866c31b3c5 | 189 | */ |
| AnnaBridge | 172:7d866c31b3c5 | 190 | #define SPIM_DISABLE_INT() (SPIM->CTL0 &= ~SPIM_CTL0_IEN_Msk) |
| AnnaBridge | 172:7d866c31b3c5 | 191 | |
| AnnaBridge | 172:7d866c31b3c5 | 192 | /** |
| AnnaBridge | 172:7d866c31b3c5 | 193 | * @details Is interrupt flag on. |
| AnnaBridge | 172:7d866c31b3c5 | 194 | * \hideinitializer |
| AnnaBridge | 172:7d866c31b3c5 | 195 | */ |
| AnnaBridge | 172:7d866c31b3c5 | 196 | #define SPIM_IS_IF_ON() ((SPIM->CTL0 & SPIM_CTL0_IF_Msk) != 0UL) |
| AnnaBridge | 172:7d866c31b3c5 | 197 | |
| AnnaBridge | 172:7d866c31b3c5 | 198 | /** |
| AnnaBridge | 172:7d866c31b3c5 | 199 | * @details Clear interrupt flag. |
| AnnaBridge | 172:7d866c31b3c5 | 200 | * \hideinitializer |
| AnnaBridge | 172:7d866c31b3c5 | 201 | */ |
| AnnaBridge | 172:7d866c31b3c5 | 202 | #define SPIM_CLR_INT() \ |
| AnnaBridge | 172:7d866c31b3c5 | 203 | do { \ |
| AnnaBridge | 172:7d866c31b3c5 | 204 | SPIM->CTL0 = (SPIM->CTL0 & (~SPIM_CTL0_IF_Msk)) | (1UL << SPIM_CTL0_IF_Pos); \ |
| AnnaBridge | 172:7d866c31b3c5 | 205 | } while (0) |
| AnnaBridge | 172:7d866c31b3c5 | 206 | |
| AnnaBridge | 172:7d866c31b3c5 | 207 | /** |
| AnnaBridge | 172:7d866c31b3c5 | 208 | * @details Set transmit/receive bit length |
| AnnaBridge | 172:7d866c31b3c5 | 209 | * \hideinitializer |
| AnnaBridge | 172:7d866c31b3c5 | 210 | */ |
| AnnaBridge | 172:7d866c31b3c5 | 211 | #define SPIM_SET_DATA_WIDTH(x) \ |
| AnnaBridge | 172:7d866c31b3c5 | 212 | do { \ |
| AnnaBridge | 172:7d866c31b3c5 | 213 | SPIM->CTL0 = (SPIM->CTL0 & (~SPIM_CTL0_DWIDTH_Msk)) | (((x) - 1U) << SPIM_CTL0_DWIDTH_Pos); \ |
| AnnaBridge | 172:7d866c31b3c5 | 214 | } while (0) |
| AnnaBridge | 172:7d866c31b3c5 | 215 | |
| AnnaBridge | 172:7d866c31b3c5 | 216 | /** |
| AnnaBridge | 172:7d866c31b3c5 | 217 | * @details Get data transmit/receive bit length setting |
| AnnaBridge | 172:7d866c31b3c5 | 218 | * \hideinitializer |
| AnnaBridge | 172:7d866c31b3c5 | 219 | */ |
| AnnaBridge | 172:7d866c31b3c5 | 220 | #define SPIM_GET_DATA_WIDTH() \ |
| AnnaBridge | 172:7d866c31b3c5 | 221 | (((SPIM->CTL0 & SPIM_CTL0_DWIDTH_Msk) >> SPIM_CTL0_DWIDTH_Pos)+1U) |
| AnnaBridge | 172:7d866c31b3c5 | 222 | |
| AnnaBridge | 172:7d866c31b3c5 | 223 | /** |
| AnnaBridge | 172:7d866c31b3c5 | 224 | * @details Set data transmit/receive burst number |
| AnnaBridge | 172:7d866c31b3c5 | 225 | * \hideinitializer |
| AnnaBridge | 172:7d866c31b3c5 | 226 | */ |
| AnnaBridge | 172:7d866c31b3c5 | 227 | #define SPIM_SET_DATA_NUM(x) \ |
| AnnaBridge | 172:7d866c31b3c5 | 228 | do { \ |
| AnnaBridge | 172:7d866c31b3c5 | 229 | SPIM->CTL0 = (SPIM->CTL0 & (~SPIM_CTL0_BURSTNUM_Msk)) | (((x) - 1U) << SPIM_CTL0_BURSTNUM_Pos); \ |
| AnnaBridge | 172:7d866c31b3c5 | 230 | } while (0) |
| AnnaBridge | 172:7d866c31b3c5 | 231 | |
| AnnaBridge | 172:7d866c31b3c5 | 232 | /** |
| AnnaBridge | 172:7d866c31b3c5 | 233 | * @details Get data transmit/receive burst number |
| AnnaBridge | 172:7d866c31b3c5 | 234 | * \hideinitializer |
| AnnaBridge | 172:7d866c31b3c5 | 235 | */ |
| AnnaBridge | 172:7d866c31b3c5 | 236 | #define SPIM_GET_DATA_NUM() \ |
| AnnaBridge | 172:7d866c31b3c5 | 237 | (((SPIM->CTL0 & SPIM_CTL0_BURSTNUM_Msk) >> SPIM_CTL0_BURSTNUM_Pos)+1U) |
| AnnaBridge | 172:7d866c31b3c5 | 238 | |
| AnnaBridge | 172:7d866c31b3c5 | 239 | /** |
| AnnaBridge | 172:7d866c31b3c5 | 240 | * @details Enable Single Input mode. |
| AnnaBridge | 172:7d866c31b3c5 | 241 | * \hideinitializer |
| AnnaBridge | 172:7d866c31b3c5 | 242 | */ |
| AnnaBridge | 172:7d866c31b3c5 | 243 | #define SPIM_ENABLE_SING_INPUT_MODE() \ |
| AnnaBridge | 172:7d866c31b3c5 | 244 | do { \ |
| AnnaBridge | 172:7d866c31b3c5 | 245 | SPIM->CTL0 = (SPIM->CTL0 & (~(SPIM_CTL0_BITMODE_Msk | SPIM_CTL0_QDIODIR_Msk))) | (SPIM_CTL0_BITMODE_SING | SPIM_CTL0_RW_IN(1)); \ |
| AnnaBridge | 172:7d866c31b3c5 | 246 | } while (0) |
| AnnaBridge | 172:7d866c31b3c5 | 247 | |
| AnnaBridge | 172:7d866c31b3c5 | 248 | /** |
| AnnaBridge | 172:7d866c31b3c5 | 249 | * @details Enable Single Output mode. |
| AnnaBridge | 172:7d866c31b3c5 | 250 | * \hideinitializer |
| AnnaBridge | 172:7d866c31b3c5 | 251 | */ |
| AnnaBridge | 172:7d866c31b3c5 | 252 | #define SPIM_ENABLE_SING_OUTPUT_MODE() \ |
| AnnaBridge | 172:7d866c31b3c5 | 253 | do { \ |
| AnnaBridge | 172:7d866c31b3c5 | 254 | SPIM->CTL0 = (SPIM->CTL0 & (~(SPIM_CTL0_BITMODE_Msk | SPIM_CTL0_QDIODIR_Msk))) | (SPIM_CTL0_BITMODE_SING | SPIM_CTL0_RW_IN(0)); \ |
| AnnaBridge | 172:7d866c31b3c5 | 255 | } while (0) |
| AnnaBridge | 172:7d866c31b3c5 | 256 | |
| AnnaBridge | 172:7d866c31b3c5 | 257 | /** |
| AnnaBridge | 172:7d866c31b3c5 | 258 | * @details Enable Dual Input mode. |
| AnnaBridge | 172:7d866c31b3c5 | 259 | * \hideinitializer |
| AnnaBridge | 172:7d866c31b3c5 | 260 | */ |
| AnnaBridge | 172:7d866c31b3c5 | 261 | #define SPIM_ENABLE_DUAL_INPUT_MODE() \ |
| AnnaBridge | 172:7d866c31b3c5 | 262 | do { \ |
| AnnaBridge | 172:7d866c31b3c5 | 263 | SPIM->CTL0 = (SPIM->CTL0 & (~(SPIM_CTL0_BITMODE_Msk | SPIM_CTL0_QDIODIR_Msk))) | (SPIM_CTL0_BITMODE_DUAL | SPIM_CTL0_RW_IN(1U)); \ |
| AnnaBridge | 172:7d866c31b3c5 | 264 | } while (0) |
| AnnaBridge | 172:7d866c31b3c5 | 265 | |
| AnnaBridge | 172:7d866c31b3c5 | 266 | /** |
| AnnaBridge | 172:7d866c31b3c5 | 267 | * @details Enable Dual Output mode. |
| AnnaBridge | 172:7d866c31b3c5 | 268 | * \hideinitializer |
| AnnaBridge | 172:7d866c31b3c5 | 269 | */ |
| AnnaBridge | 172:7d866c31b3c5 | 270 | #define SPIM_ENABLE_DUAL_OUTPUT_MODE() \ |
| AnnaBridge | 172:7d866c31b3c5 | 271 | do { \ |
| AnnaBridge | 172:7d866c31b3c5 | 272 | SPIM->CTL0 = (SPIM->CTL0 & (~(SPIM_CTL0_BITMODE_Msk | SPIM_CTL0_QDIODIR_Msk))) | (SPIM_CTL0_BITMODE_DUAL | SPIM_CTL0_RW_IN(0U)); \ |
| AnnaBridge | 172:7d866c31b3c5 | 273 | } while (0) |
| AnnaBridge | 172:7d866c31b3c5 | 274 | |
| AnnaBridge | 172:7d866c31b3c5 | 275 | /** |
| AnnaBridge | 172:7d866c31b3c5 | 276 | * @details Enable Quad Input mode. |
| AnnaBridge | 172:7d866c31b3c5 | 277 | * \hideinitializer |
| AnnaBridge | 172:7d866c31b3c5 | 278 | */ |
| AnnaBridge | 172:7d866c31b3c5 | 279 | #define SPIM_ENABLE_QUAD_INPUT_MODE() \ |
| AnnaBridge | 172:7d866c31b3c5 | 280 | do { \ |
| AnnaBridge | 172:7d866c31b3c5 | 281 | SPIM->CTL0 = (SPIM->CTL0 & (~(SPIM_CTL0_BITMODE_Msk | SPIM_CTL0_QDIODIR_Msk))) | (SPIM_CTL0_BITMODE_QUAD | SPIM_CTL0_RW_IN(1U)); \ |
| AnnaBridge | 172:7d866c31b3c5 | 282 | } while (0) |
| AnnaBridge | 172:7d866c31b3c5 | 283 | |
| AnnaBridge | 172:7d866c31b3c5 | 284 | /** |
| AnnaBridge | 172:7d866c31b3c5 | 285 | * @details Enable Quad Output mode. |
| AnnaBridge | 172:7d866c31b3c5 | 286 | * \hideinitializer |
| AnnaBridge | 172:7d866c31b3c5 | 287 | */ |
| AnnaBridge | 172:7d866c31b3c5 | 288 | #define SPIM_ENABLE_QUAD_OUTPUT_MODE() \ |
| AnnaBridge | 172:7d866c31b3c5 | 289 | do { \ |
| AnnaBridge | 172:7d866c31b3c5 | 290 | SPIM->CTL0 = (SPIM->CTL0 & (~(SPIM_CTL0_BITMODE_Msk | SPIM_CTL0_QDIODIR_Msk))) | (SPIM_CTL0_BITMODE_QUAD | SPIM_CTL0_RW_IN(0U)); \ |
| AnnaBridge | 172:7d866c31b3c5 | 291 | } while (0) |
| AnnaBridge | 172:7d866c31b3c5 | 292 | |
| AnnaBridge | 172:7d866c31b3c5 | 293 | /** |
| AnnaBridge | 172:7d866c31b3c5 | 294 | * @details Set suspend interval which ranges between 0 and 15. |
| AnnaBridge | 172:7d866c31b3c5 | 295 | * \hideinitializer |
| AnnaBridge | 172:7d866c31b3c5 | 296 | */ |
| AnnaBridge | 172:7d866c31b3c5 | 297 | #define SPIM_SET_SUSP_INTVL(x) \ |
| AnnaBridge | 172:7d866c31b3c5 | 298 | do { \ |
| AnnaBridge | 172:7d866c31b3c5 | 299 | SPIM->CTL0 = (SPIM->CTL0 & (~SPIM_CTL0_SUSPITV_Msk)) | ((x) << SPIM_CTL0_SUSPITV_Pos); \ |
| AnnaBridge | 172:7d866c31b3c5 | 300 | } while (0) |
| AnnaBridge | 172:7d866c31b3c5 | 301 | |
| AnnaBridge | 172:7d866c31b3c5 | 302 | /** |
| AnnaBridge | 172:7d866c31b3c5 | 303 | * @details Get suspend interval setting |
| AnnaBridge | 172:7d866c31b3c5 | 304 | * \hideinitializer |
| AnnaBridge | 172:7d866c31b3c5 | 305 | */ |
| AnnaBridge | 172:7d866c31b3c5 | 306 | #define SPIM_GET_SUSP_INTVL() \ |
| AnnaBridge | 172:7d866c31b3c5 | 307 | ((SPIM->CTL0 & SPIM_CTL0_SUSPITV_Msk) >> SPIM_CTL0_SUSPITV_Pos) |
| AnnaBridge | 172:7d866c31b3c5 | 308 | |
| AnnaBridge | 172:7d866c31b3c5 | 309 | /** |
| AnnaBridge | 172:7d866c31b3c5 | 310 | * @details Set operation mode. |
| AnnaBridge | 172:7d866c31b3c5 | 311 | * \hideinitializer |
| AnnaBridge | 172:7d866c31b3c5 | 312 | */ |
| AnnaBridge | 172:7d866c31b3c5 | 313 | #define SPIM_SET_OPMODE(x) \ |
| AnnaBridge | 172:7d866c31b3c5 | 314 | do { \ |
| AnnaBridge | 172:7d866c31b3c5 | 315 | SPIM->CTL0 = (SPIM->CTL0 & (~SPIM_CTL0_OPMODE_Msk)) | (x); \ |
| AnnaBridge | 172:7d866c31b3c5 | 316 | } while (0) |
| AnnaBridge | 172:7d866c31b3c5 | 317 | |
| AnnaBridge | 172:7d866c31b3c5 | 318 | /** |
| AnnaBridge | 172:7d866c31b3c5 | 319 | * @details Get operation mode. |
| AnnaBridge | 172:7d866c31b3c5 | 320 | * \hideinitializer |
| AnnaBridge | 172:7d866c31b3c5 | 321 | */ |
| AnnaBridge | 172:7d866c31b3c5 | 322 | #define SPIM_GET_OP_MODE() (SPIM->CTL0 & SPIM_CTL0_OPMODE_Msk) |
| AnnaBridge | 172:7d866c31b3c5 | 323 | |
| AnnaBridge | 172:7d866c31b3c5 | 324 | /** |
| AnnaBridge | 172:7d866c31b3c5 | 325 | * @details Set SPIM mode. |
| AnnaBridge | 172:7d866c31b3c5 | 326 | * \hideinitializer |
| AnnaBridge | 172:7d866c31b3c5 | 327 | */ |
| AnnaBridge | 172:7d866c31b3c5 | 328 | #define SPIM_SET_SPIM_MODE(x) \ |
| AnnaBridge | 172:7d866c31b3c5 | 329 | do { \ |
| AnnaBridge | 172:7d866c31b3c5 | 330 | SPIM->CTL0 = (SPIM->CTL0 & (~SPIM_CTL0_CMDCODE_Msk)) | (x); \ |
| AnnaBridge | 172:7d866c31b3c5 | 331 | } while (0) |
| AnnaBridge | 172:7d866c31b3c5 | 332 | |
| AnnaBridge | 172:7d866c31b3c5 | 333 | /** |
| AnnaBridge | 172:7d866c31b3c5 | 334 | * @details Get SPIM mode. |
| AnnaBridge | 172:7d866c31b3c5 | 335 | * \hideinitializer |
| AnnaBridge | 172:7d866c31b3c5 | 336 | */ |
| AnnaBridge | 172:7d866c31b3c5 | 337 | #define SPIM_GET_SPIM_MODE() (SPIM->CTL0 & SPIM_CTL0_CMDCODE_Msk) |
| AnnaBridge | 172:7d866c31b3c5 | 338 | |
| AnnaBridge | 172:7d866c31b3c5 | 339 | /** |
| AnnaBridge | 172:7d866c31b3c5 | 340 | * @details Start operation. |
| AnnaBridge | 172:7d866c31b3c5 | 341 | * \hideinitializer |
| AnnaBridge | 172:7d866c31b3c5 | 342 | */ |
| AnnaBridge | 172:7d866c31b3c5 | 343 | #define SPIM_SET_GO() (SPIM->CTL1 |= SPIM_CTL1_SPIMEN_Msk) |
| AnnaBridge | 172:7d866c31b3c5 | 344 | |
| AnnaBridge | 172:7d866c31b3c5 | 345 | /** |
| AnnaBridge | 172:7d866c31b3c5 | 346 | * @details Is engine busy. |
| AnnaBridge | 172:7d866c31b3c5 | 347 | * \hideinitializer |
| AnnaBridge | 172:7d866c31b3c5 | 348 | */ |
| AnnaBridge | 172:7d866c31b3c5 | 349 | #define SPIM_IS_BUSY() (SPIM->CTL1 & SPIM_CTL1_SPIMEN_Msk) |
| AnnaBridge | 172:7d866c31b3c5 | 350 | |
| AnnaBridge | 172:7d866c31b3c5 | 351 | /** |
| AnnaBridge | 172:7d866c31b3c5 | 352 | * @details Wait for free. |
| AnnaBridge | 172:7d866c31b3c5 | 353 | * \hideinitializer |
| AnnaBridge | 172:7d866c31b3c5 | 354 | */ |
| AnnaBridge | 172:7d866c31b3c5 | 355 | #define SPIM_WAIT_FREE() \ |
| AnnaBridge | 172:7d866c31b3c5 | 356 | do { \ |
| AnnaBridge | 172:7d866c31b3c5 | 357 | while (SPIM->CTL1 & SPIM_CTL1_SPIMEN_Msk) { } \ |
| AnnaBridge | 172:7d866c31b3c5 | 358 | } while (0) |
| AnnaBridge | 172:7d866c31b3c5 | 359 | |
| AnnaBridge | 172:7d866c31b3c5 | 360 | /** |
| AnnaBridge | 172:7d866c31b3c5 | 361 | * @details Enable cache. |
| AnnaBridge | 172:7d866c31b3c5 | 362 | * \hideinitializer |
| AnnaBridge | 172:7d866c31b3c5 | 363 | */ |
| AnnaBridge | 172:7d866c31b3c5 | 364 | #define SPIM_ENABLE_CACHE() (SPIM->CTL1 &= ~SPIM_CTL1_CACHEOFF_Msk) |
| AnnaBridge | 172:7d866c31b3c5 | 365 | |
| AnnaBridge | 172:7d866c31b3c5 | 366 | /** |
| AnnaBridge | 172:7d866c31b3c5 | 367 | * @details Disable cache. |
| AnnaBridge | 172:7d866c31b3c5 | 368 | * \hideinitializer |
| AnnaBridge | 172:7d866c31b3c5 | 369 | */ |
| AnnaBridge | 172:7d866c31b3c5 | 370 | #define SPIM_DISABLE_CACHE() (SPIM->CTL1 |= SPIM_CTL1_CACHEOFF_Msk) |
| AnnaBridge | 172:7d866c31b3c5 | 371 | |
| AnnaBridge | 172:7d866c31b3c5 | 372 | /** |
| AnnaBridge | 172:7d866c31b3c5 | 373 | * @details Is cache enabled. |
| AnnaBridge | 172:7d866c31b3c5 | 374 | * \hideinitializer |
| AnnaBridge | 172:7d866c31b3c5 | 375 | */ |
| AnnaBridge | 172:7d866c31b3c5 | 376 | #define SPIM_IS_CACHE_EN() ((SPIM->CTL1 & SPIM_CTL1_CACHEOFF_Msk) ? 0 : 1) |
| AnnaBridge | 172:7d866c31b3c5 | 377 | |
| AnnaBridge | 172:7d866c31b3c5 | 378 | /** |
| AnnaBridge | 172:7d866c31b3c5 | 379 | * @details Enable CCM |
| AnnaBridge | 172:7d866c31b3c5 | 380 | * \hideinitializer |
| AnnaBridge | 172:7d866c31b3c5 | 381 | */ |
| AnnaBridge | 172:7d866c31b3c5 | 382 | #define SPIM_ENABLE_CCM() (SPIM->CTL1 |= SPIM_CTL1_CCMEN_Msk) |
| AnnaBridge | 172:7d866c31b3c5 | 383 | |
| AnnaBridge | 172:7d866c31b3c5 | 384 | /** |
| AnnaBridge | 172:7d866c31b3c5 | 385 | * @details Disable CCM. |
| AnnaBridge | 172:7d866c31b3c5 | 386 | * \hideinitializer |
| AnnaBridge | 172:7d866c31b3c5 | 387 | */ |
| AnnaBridge | 172:7d866c31b3c5 | 388 | #define SPIM_DISABLE_CCM() (SPIM->CTL1 &= ~SPIM_CTL1_CCMEN_Msk) |
| AnnaBridge | 172:7d866c31b3c5 | 389 | |
| AnnaBridge | 172:7d866c31b3c5 | 390 | /** |
| AnnaBridge | 172:7d866c31b3c5 | 391 | * @details Is CCM enabled. |
| AnnaBridge | 172:7d866c31b3c5 | 392 | * \hideinitializer |
| AnnaBridge | 172:7d866c31b3c5 | 393 | */ |
| AnnaBridge | 172:7d866c31b3c5 | 394 | #define SPIM_IS_CCM_EN() ((SPIM->CTL1 & SPIM_CTL1_CCMEN_Msk) >> SPIM_CTL1_CCMEN_Pos) |
| AnnaBridge | 172:7d866c31b3c5 | 395 | |
| AnnaBridge | 172:7d866c31b3c5 | 396 | /** |
| AnnaBridge | 172:7d866c31b3c5 | 397 | * @details Invalidate cache. |
| AnnaBridge | 172:7d866c31b3c5 | 398 | * \hideinitializer |
| AnnaBridge | 172:7d866c31b3c5 | 399 | */ |
| AnnaBridge | 172:7d866c31b3c5 | 400 | #define SPIM_INVALID_CACHE() (SPIM->CTL1 |= SPIM_CTL1_CDINVAL_Msk) |
| AnnaBridge | 172:7d866c31b3c5 | 401 | |
| AnnaBridge | 172:7d866c31b3c5 | 402 | /** |
| AnnaBridge | 172:7d866c31b3c5 | 403 | * @details Set SS(Select Active) to active level. |
| AnnaBridge | 172:7d866c31b3c5 | 404 | * \hideinitializer |
| AnnaBridge | 172:7d866c31b3c5 | 405 | */ |
| AnnaBridge | 172:7d866c31b3c5 | 406 | #define SPIM_SET_SS_EN(x) \ |
| AnnaBridge | 172:7d866c31b3c5 | 407 | do { \ |
| AnnaBridge | 172:7d866c31b3c5 | 408 | (SPIM->CTL1 = (SPIM->CTL1 & (~SPIM_CTL1_SS_Msk)) | ((! (x) ? 1UL : 0UL) << SPIM_CTL1_SS_Pos)); \ |
| AnnaBridge | 172:7d866c31b3c5 | 409 | } while (0) |
| AnnaBridge | 172:7d866c31b3c5 | 410 | |
| AnnaBridge | 172:7d866c31b3c5 | 411 | /** |
| AnnaBridge | 172:7d866c31b3c5 | 412 | * @details Is SS(Select Active) in active level. |
| AnnaBridge | 172:7d866c31b3c5 | 413 | * \hideinitializer |
| AnnaBridge | 172:7d866c31b3c5 | 414 | */ |
| AnnaBridge | 172:7d866c31b3c5 | 415 | #define SPIM_GET_SS_EN() \ |
| AnnaBridge | 172:7d866c31b3c5 | 416 | (!(SPIM->CTL1 & SPIM_CTL1_SS_Msk)) |
| AnnaBridge | 172:7d866c31b3c5 | 417 | |
| AnnaBridge | 172:7d866c31b3c5 | 418 | /** |
| AnnaBridge | 172:7d866c31b3c5 | 419 | * @details Set active level of slave select to be high/low. |
| AnnaBridge | 172:7d866c31b3c5 | 420 | * \hideinitializer |
| AnnaBridge | 172:7d866c31b3c5 | 421 | */ |
| AnnaBridge | 172:7d866c31b3c5 | 422 | #define SPIM_SET_SS_ACTLVL(x) \ |
| AnnaBridge | 172:7d866c31b3c5 | 423 | do { \ |
| AnnaBridge | 172:7d866c31b3c5 | 424 | (SPIM->CTL1 = (SPIM->CTL1 & (~SPIM_CTL1_SSACTPOL_Msk)) | ((!! (x) ? 1UL : 0UL) << SPIM_CTL1_SSACTPOL_Pos)); \ |
| AnnaBridge | 172:7d866c31b3c5 | 425 | } while (0) |
| AnnaBridge | 172:7d866c31b3c5 | 426 | |
| AnnaBridge | 172:7d866c31b3c5 | 427 | /** |
| AnnaBridge | 172:7d866c31b3c5 | 428 | * @details Set idle time interval |
| AnnaBridge | 172:7d866c31b3c5 | 429 | * \hideinitializer |
| AnnaBridge | 172:7d866c31b3c5 | 430 | */ |
| AnnaBridge | 172:7d866c31b3c5 | 431 | #define SPIM_SET_IDL_INTVL(x) \ |
| AnnaBridge | 172:7d866c31b3c5 | 432 | do { \ |
| AnnaBridge | 172:7d866c31b3c5 | 433 | SPIM->CTL1 = (SPIM->CTL1 & (~SPIM_CTL1_IDLETIME_Msk)) | ((x) << SPIM_CTL1_IDLETIME_Pos); \ |
| AnnaBridge | 172:7d866c31b3c5 | 434 | } while (0) |
| AnnaBridge | 172:7d866c31b3c5 | 435 | |
| AnnaBridge | 172:7d866c31b3c5 | 436 | /** |
| AnnaBridge | 172:7d866c31b3c5 | 437 | * @details Get idle time interval setting |
| AnnaBridge | 172:7d866c31b3c5 | 438 | * \hideinitializer |
| AnnaBridge | 172:7d866c31b3c5 | 439 | */ |
| AnnaBridge | 172:7d866c31b3c5 | 440 | #define SPIM_GET_IDL_INTVL() \ |
| AnnaBridge | 172:7d866c31b3c5 | 441 | ((SPIM->CTL1 & SPIM_CTL1_IDLETIME_Msk) >> SPIM_CTL1_IDLETIME_Pos) |
| AnnaBridge | 172:7d866c31b3c5 | 442 | |
| AnnaBridge | 172:7d866c31b3c5 | 443 | /** |
| AnnaBridge | 172:7d866c31b3c5 | 444 | * @details Set SPIM clock divider |
| AnnaBridge | 172:7d866c31b3c5 | 445 | * \hideinitializer |
| AnnaBridge | 172:7d866c31b3c5 | 446 | */ |
| AnnaBridge | 172:7d866c31b3c5 | 447 | #define SPIM_SET_CLOCK_DIVIDER(x) \ |
| AnnaBridge | 172:7d866c31b3c5 | 448 | do { \ |
| AnnaBridge | 172:7d866c31b3c5 | 449 | SPIM->CTL1 = (SPIM->CTL1 & (~SPIM_CTL1_DIVIDER_Msk)) | ((x) << SPIM_CTL1_DIVIDER_Pos); \ |
| AnnaBridge | 172:7d866c31b3c5 | 450 | } while (0) |
| AnnaBridge | 172:7d866c31b3c5 | 451 | |
| AnnaBridge | 172:7d866c31b3c5 | 452 | /** |
| AnnaBridge | 172:7d866c31b3c5 | 453 | * @details Get SPIM current clock divider setting |
| AnnaBridge | 172:7d866c31b3c5 | 454 | * \hideinitializer |
| AnnaBridge | 172:7d866c31b3c5 | 455 | */ |
| AnnaBridge | 172:7d866c31b3c5 | 456 | #define SPIM_GET_CLOCK_DIVIDER() \ |
| AnnaBridge | 172:7d866c31b3c5 | 457 | ((SPIM->CTL1 & SPIM_CTL1_DIVIDER_Msk) >> SPIM_CTL1_DIVIDER_Pos) |
| AnnaBridge | 172:7d866c31b3c5 | 458 | |
| AnnaBridge | 172:7d866c31b3c5 | 459 | /** |
| AnnaBridge | 172:7d866c31b3c5 | 460 | * @details Set SPI flash deselect time interval of DMA write mode |
| AnnaBridge | 172:7d866c31b3c5 | 461 | * \hideinitializer |
| AnnaBridge | 172:7d866c31b3c5 | 462 | */ |
| AnnaBridge | 172:7d866c31b3c5 | 463 | #define SPIM_SET_RXCLKDLY_DWDELSEL(x) \ |
| AnnaBridge | 172:7d866c31b3c5 | 464 | do { \ |
| AnnaBridge | 172:7d866c31b3c5 | 465 | (SPIM->RXCLKDLY = (SPIM->RXCLKDLY & (~SPIM_RXCLKDLY_DWDELSEL_Msk)) | ((x) << SPIM_RXCLKDLY_DWDELSEL_Pos)); \ |
| AnnaBridge | 172:7d866c31b3c5 | 466 | } while (0) |
| AnnaBridge | 172:7d866c31b3c5 | 467 | |
| AnnaBridge | 172:7d866c31b3c5 | 468 | /** |
| AnnaBridge | 172:7d866c31b3c5 | 469 | * @details Get SPI flash deselect time interval of DMA write mode |
| AnnaBridge | 172:7d866c31b3c5 | 470 | * \hideinitializer |
| AnnaBridge | 172:7d866c31b3c5 | 471 | */ |
| AnnaBridge | 172:7d866c31b3c5 | 472 | #define SPIM_GET_RXCLKDLY_DWDELSEL() \ |
| AnnaBridge | 172:7d866c31b3c5 | 473 | ((SPIM->RXCLKDLY & SPIM_RXCLKDLY_DWDELSEL_Msk) >> SPIM_RXCLKDLY_DWDELSEL_Pos) |
| AnnaBridge | 172:7d866c31b3c5 | 474 | |
| AnnaBridge | 172:7d866c31b3c5 | 475 | /** |
| AnnaBridge | 172:7d866c31b3c5 | 476 | * @details Set sampling clock delay selection for received data |
| AnnaBridge | 172:7d866c31b3c5 | 477 | * \hideinitializer |
| AnnaBridge | 172:7d866c31b3c5 | 478 | */ |
| AnnaBridge | 172:7d866c31b3c5 | 479 | #define SPIM_SET_RXCLKDLY_RDDLYSEL(x) \ |
| AnnaBridge | 172:7d866c31b3c5 | 480 | do { \ |
| AnnaBridge | 172:7d866c31b3c5 | 481 | (SPIM->RXCLKDLY = (SPIM->RXCLKDLY & (~SPIM_RXCLKDLY_RDDLYSEL_Msk)) | ((x) << SPIM_RXCLKDLY_RDDLYSEL_Pos)); \ |
| AnnaBridge | 172:7d866c31b3c5 | 482 | } while (0) |
| AnnaBridge | 172:7d866c31b3c5 | 483 | |
| AnnaBridge | 172:7d866c31b3c5 | 484 | /** |
| AnnaBridge | 172:7d866c31b3c5 | 485 | * @details Get sampling clock delay selection for received data |
| AnnaBridge | 172:7d866c31b3c5 | 486 | * \hideinitializer |
| AnnaBridge | 172:7d866c31b3c5 | 487 | */ |
| AnnaBridge | 172:7d866c31b3c5 | 488 | #define SPIM_GET_RXCLKDLY_RDDLYSEL() \ |
| AnnaBridge | 172:7d866c31b3c5 | 489 | ((SPIM->RXCLKDLY & SPIM_RXCLKDLY_RDDLYSEL_Msk) >> SPIM_RXCLKDLY_RDDLYSEL_Pos) |
| AnnaBridge | 172:7d866c31b3c5 | 490 | |
| AnnaBridge | 172:7d866c31b3c5 | 491 | /** |
| AnnaBridge | 172:7d866c31b3c5 | 492 | * @details Set sampling clock edge selection for received data |
| AnnaBridge | 172:7d866c31b3c5 | 493 | * \hideinitializer |
| AnnaBridge | 172:7d866c31b3c5 | 494 | */ |
| AnnaBridge | 172:7d866c31b3c5 | 495 | #define SPIM_SET_RXCLKDLY_RDEDGE() \ |
| AnnaBridge | 172:7d866c31b3c5 | 496 | (SPIM->RXCLKDLY |= SPIM_RXCLKDLY_RDEDGE_Msk); \ |
| AnnaBridge | 172:7d866c31b3c5 | 497 | |
| AnnaBridge | 172:7d866c31b3c5 | 498 | /** |
| AnnaBridge | 172:7d866c31b3c5 | 499 | * @details Get sampling clock edge selection for received data |
| AnnaBridge | 172:7d866c31b3c5 | 500 | * \hideinitializer |
| AnnaBridge | 172:7d866c31b3c5 | 501 | */ |
| AnnaBridge | 172:7d866c31b3c5 | 502 | #define SPIM_CLR_RXCLKDLY_RDEDGE() \ |
| AnnaBridge | 172:7d866c31b3c5 | 503 | (SPIM->RXCLKDLY &= ~SPIM_RXCLKDLY_RDEDGE_Msk) |
| AnnaBridge | 172:7d866c31b3c5 | 504 | |
| AnnaBridge | 172:7d866c31b3c5 | 505 | /** |
| AnnaBridge | 172:7d866c31b3c5 | 506 | * @details Set mode bits data for continuous read mode |
| AnnaBridge | 172:7d866c31b3c5 | 507 | * \hideinitializer |
| AnnaBridge | 172:7d866c31b3c5 | 508 | */ |
| AnnaBridge | 172:7d866c31b3c5 | 509 | #define SPIM_SET_DMMCTL_CRMDAT(x) \ |
| AnnaBridge | 172:7d866c31b3c5 | 510 | do { \ |
| AnnaBridge | 172:7d866c31b3c5 | 511 | (SPIM->DMMCTL = (SPIM->DMMCTL & (~SPIM_DMMCTL_CRMDAT_Msk)) | ((x) << SPIM_DMMCTL_CRMDAT_Pos)) | SPIM_DMMCTL_CREN_Msk; \ |
| AnnaBridge | 172:7d866c31b3c5 | 512 | } while (0) |
| AnnaBridge | 172:7d866c31b3c5 | 513 | |
| AnnaBridge | 172:7d866c31b3c5 | 514 | /** |
| AnnaBridge | 172:7d866c31b3c5 | 515 | * @details Get mode bits data for continuous read mode |
| AnnaBridge | 172:7d866c31b3c5 | 516 | * \hideinitializer |
| AnnaBridge | 172:7d866c31b3c5 | 517 | */ |
| AnnaBridge | 172:7d866c31b3c5 | 518 | #define SPIM_GET_DMMCTL_CRMDAT() \ |
| AnnaBridge | 172:7d866c31b3c5 | 519 | ((SPIM->DMMCTL & SPIM_DMMCTL_CRMDAT_Msk) >> SPIM_DMMCTL_CRMDAT_Pos) |
| AnnaBridge | 172:7d866c31b3c5 | 520 | |
| AnnaBridge | 172:7d866c31b3c5 | 521 | /** |
| AnnaBridge | 172:7d866c31b3c5 | 522 | * @details Set DMM mode SPI flash deselect time |
| AnnaBridge | 172:7d866c31b3c5 | 523 | * \hideinitializer |
| AnnaBridge | 172:7d866c31b3c5 | 524 | */ |
| AnnaBridge | 172:7d866c31b3c5 | 525 | #define SPIM_DMM_SET_DESELTIM(x) \ |
| AnnaBridge | 172:7d866c31b3c5 | 526 | do { \ |
| AnnaBridge | 172:7d866c31b3c5 | 527 | SPIM->DMMCTL = (SPIM->DMMCTL & ~SPIM_DMMCTL_DESELTIM_Msk) | (((x) & 0x1FUL) << SPIM_DMMCTL_DESELTIM_Pos); \ |
| AnnaBridge | 172:7d866c31b3c5 | 528 | } while (0) |
| AnnaBridge | 172:7d866c31b3c5 | 529 | |
| AnnaBridge | 172:7d866c31b3c5 | 530 | /** |
| AnnaBridge | 172:7d866c31b3c5 | 531 | * @details Get current DMM mode SPI flash deselect time setting |
| AnnaBridge | 172:7d866c31b3c5 | 532 | * \hideinitializer |
| AnnaBridge | 172:7d866c31b3c5 | 533 | */ |
| AnnaBridge | 172:7d866c31b3c5 | 534 | #define SPIM_DMM_GET_DESELTIM() \ |
| AnnaBridge | 172:7d866c31b3c5 | 535 | ((SPIM->DMMCTL & SPIM_DMMCTL_DESELTIM_Msk) >> SPIM_DMMCTL_DESELTIM_Pos) |
| AnnaBridge | 172:7d866c31b3c5 | 536 | |
| AnnaBridge | 172:7d866c31b3c5 | 537 | /** |
| AnnaBridge | 172:7d866c31b3c5 | 538 | * @details Enable DMM mode burst wrap mode |
| AnnaBridge | 172:7d866c31b3c5 | 539 | * \hideinitializer |
| AnnaBridge | 172:7d866c31b3c5 | 540 | */ |
| AnnaBridge | 172:7d866c31b3c5 | 541 | #define SPIM_DMM_ENABLE_BWEN() (SPIM->DMMCTL |= SPIM_DMMCTL_BWEN_Msk) |
| AnnaBridge | 172:7d866c31b3c5 | 542 | |
| AnnaBridge | 172:7d866c31b3c5 | 543 | /** |
| AnnaBridge | 172:7d866c31b3c5 | 544 | * @details Disable DMM mode burst wrap mode |
| AnnaBridge | 172:7d866c31b3c5 | 545 | * \hideinitializer |
| AnnaBridge | 172:7d866c31b3c5 | 546 | */ |
| AnnaBridge | 172:7d866c31b3c5 | 547 | #define SPIM_DMM_DISABLE_BWEN() (SPIM->DMMCTL &= ~SPIM_DMMCTL_BWEN_Msk) |
| AnnaBridge | 172:7d866c31b3c5 | 548 | |
| AnnaBridge | 172:7d866c31b3c5 | 549 | /** |
| AnnaBridge | 172:7d866c31b3c5 | 550 | * @details Enable DMM mode continuous read mode |
| AnnaBridge | 172:7d866c31b3c5 | 551 | * \hideinitializer |
| AnnaBridge | 172:7d866c31b3c5 | 552 | */ |
| AnnaBridge | 172:7d866c31b3c5 | 553 | #define SPIM_DMM_ENABLE_CREN() (SPIM->DMMCTL |= SPIM_DMMCTL_CREN_Msk) |
| AnnaBridge | 172:7d866c31b3c5 | 554 | |
| AnnaBridge | 172:7d866c31b3c5 | 555 | /** |
| AnnaBridge | 172:7d866c31b3c5 | 556 | * @details Disable DMM mode continuous read mode |
| AnnaBridge | 172:7d866c31b3c5 | 557 | * \hideinitializer |
| AnnaBridge | 172:7d866c31b3c5 | 558 | */ |
| AnnaBridge | 172:7d866c31b3c5 | 559 | #define SPIM_DMM_DISABLE_CREN() (SPIM->DMMCTL &= ~SPIM_DMMCTL_CREN_Msk) |
| AnnaBridge | 172:7d866c31b3c5 | 560 | |
| AnnaBridge | 172:7d866c31b3c5 | 561 | /** |
| AnnaBridge | 172:7d866c31b3c5 | 562 | * @details Set DMM mode SPI flash active SCLK time |
| AnnaBridge | 172:7d866c31b3c5 | 563 | * \hideinitializer |
| AnnaBridge | 172:7d866c31b3c5 | 564 | */ |
| AnnaBridge | 172:7d866c31b3c5 | 565 | #define SPIM_DMM_SET_ACTSCLKT(x) \ |
| AnnaBridge | 172:7d866c31b3c5 | 566 | do { \ |
| AnnaBridge | 172:7d866c31b3c5 | 567 | SPIM->DMMCTL = (SPIM->DMMCTL & ~SPIM_DMMCTL_ACTSCLKT_Msk) | (((x) & 0xFUL) << SPIM_DMMCTL_ACTSCLKT_Pos) | SPIM_DMMCTL_UACTSCLK_Msk; \ |
| AnnaBridge | 172:7d866c31b3c5 | 568 | } while (0) |
| AnnaBridge | 172:7d866c31b3c5 | 569 | |
| AnnaBridge | 172:7d866c31b3c5 | 570 | /** |
| AnnaBridge | 172:7d866c31b3c5 | 571 | * @details Set SPI flash active SCLK time as SPIM default |
| AnnaBridge | 172:7d866c31b3c5 | 572 | * \hideinitializer |
| AnnaBridge | 172:7d866c31b3c5 | 573 | */ |
| AnnaBridge | 172:7d866c31b3c5 | 574 | #define SPIM_DMM_SET_DEFAULT_ACTSCLK() (SPIM->DMMCTL &= ~SPIM_DMMCTL_UACTSCLK_Msk) |
| AnnaBridge | 172:7d866c31b3c5 | 575 | |
| AnnaBridge | 172:7d866c31b3c5 | 576 | /** |
| AnnaBridge | 172:7d866c31b3c5 | 577 | * @details Set dummy cycle number (Only for DMM mode and DMA mode) |
| AnnaBridge | 172:7d866c31b3c5 | 578 | * \hideinitializer |
| AnnaBridge | 172:7d866c31b3c5 | 579 | */ |
| AnnaBridge | 172:7d866c31b3c5 | 580 | #define SPIM_SET_DCNUM(x) \ |
| AnnaBridge | 172:7d866c31b3c5 | 581 | do { \ |
| AnnaBridge | 172:7d866c31b3c5 | 582 | SPIM->CTL2 = (SPIM->CTL2 & ~SPIM_CTL2_DCNUM_Msk) | (((x) & 0x1FUL) << SPIM_CTL2_DCNUM_Pos) | SPIM_CTL2_USETEN_Msk; \ |
| AnnaBridge | 172:7d866c31b3c5 | 583 | } while (0) |
| AnnaBridge | 172:7d866c31b3c5 | 584 | |
| AnnaBridge | 172:7d866c31b3c5 | 585 | /** |
| AnnaBridge | 172:7d866c31b3c5 | 586 | * @details Set dummy cycle number (Only for DMM mode and DMA mode) as SPIM default |
| AnnaBridge | 172:7d866c31b3c5 | 587 | * \hideinitializer |
| AnnaBridge | 172:7d866c31b3c5 | 588 | */ |
| AnnaBridge | 172:7d866c31b3c5 | 589 | #define SPIM_SET_DEFAULT_DCNUM(x) (SPIM->CTL2 &= ~SPIM_CTL2_USETEN_Msk) |
| AnnaBridge | 172:7d866c31b3c5 | 590 | |
| AnnaBridge | 172:7d866c31b3c5 | 591 | |
| AnnaBridge | 172:7d866c31b3c5 | 592 | |
| AnnaBridge | 172:7d866c31b3c5 | 593 | /*---------------------------------------------------------------------------------------------------------*/ |
| AnnaBridge | 172:7d866c31b3c5 | 594 | /* Define Function Prototypes */ |
| AnnaBridge | 172:7d866c31b3c5 | 595 | /*---------------------------------------------------------------------------------------------------------*/ |
| AnnaBridge | 172:7d866c31b3c5 | 596 | |
| AnnaBridge | 172:7d866c31b3c5 | 597 | |
| AnnaBridge | 172:7d866c31b3c5 | 598 | int SPIM_InitFlash(int clrWP); |
| AnnaBridge | 172:7d866c31b3c5 | 599 | uint32_t SPIM_GetSClkFreq(void); |
| AnnaBridge | 172:7d866c31b3c5 | 600 | void SPIM_ReadJedecId(uint8_t idBuf[], uint32_t u32NRx, uint32_t u32NBit); |
| AnnaBridge | 172:7d866c31b3c5 | 601 | int SPIM_Enable_4Bytes_Mode(int isEn, uint32_t u32NBit); |
| AnnaBridge | 172:7d866c31b3c5 | 602 | int SPIM_Is4ByteModeEnable(uint32_t u32NBit); |
| AnnaBridge | 172:7d866c31b3c5 | 603 | |
| AnnaBridge | 172:7d866c31b3c5 | 604 | void SPIM_ChipErase(uint32_t u32NBit, int isSync); |
| AnnaBridge | 172:7d866c31b3c5 | 605 | void SPIM_EraseBlock(uint32_t u32Addr, int is4ByteAddr, uint8_t u8ErsCmd, uint32_t u32NBit, int isSync); |
| AnnaBridge | 172:7d866c31b3c5 | 606 | |
| AnnaBridge | 172:7d866c31b3c5 | 607 | void SPIM_IO_Write(uint32_t u32Addr, int is4ByteAddr, uint32_t u32NTx, uint8_t pu8TxBuf[], uint8_t wrCmd, uint32_t u32NBitCmd, uint32_t u32NBitAddr, uint32_t u32NBitDat); |
| AnnaBridge | 172:7d866c31b3c5 | 608 | void SPIM_IO_Read(uint32_t u32Addr, int is4ByteAddr, uint32_t u32NRx, uint8_t pu8RxBuf[], uint8_t rdCmd, uint32_t u32NBitCmd, uint32_t u32NBitAddr, uint32_t u32NBitDat, int u32NDummy); |
| AnnaBridge | 172:7d866c31b3c5 | 609 | |
| AnnaBridge | 172:7d866c31b3c5 | 610 | void SPIM_DMA_Write(uint32_t u32Addr, int is4ByteAddr, uint32_t u32NTx, uint8_t pu8TxBuf[], uint32_t wrCmd); |
| AnnaBridge | 172:7d866c31b3c5 | 611 | void SPIM_DMA_Read(uint32_t u32Addr, int is4ByteAddr, uint32_t u32NRx, uint8_t pu8RxBuf[], uint32_t u32RdCmd, int isSync); |
| AnnaBridge | 172:7d866c31b3c5 | 612 | |
| AnnaBridge | 172:7d866c31b3c5 | 613 | void SPIM_EnterDirectMapMode(int is4ByteAddr, uint32_t u32RdCmd, uint32_t u32IdleIntvl); |
| AnnaBridge | 172:7d866c31b3c5 | 614 | void SPIM_ExitDirectMapMode(void); |
| AnnaBridge | 172:7d866c31b3c5 | 615 | |
| AnnaBridge | 172:7d866c31b3c5 | 616 | void SPIM_SetQuadEnable(int isEn, uint32_t u32NBit); |
| AnnaBridge | 172:7d866c31b3c5 | 617 | |
| AnnaBridge | 172:7d866c31b3c5 | 618 | /*@}*/ /* end of group M480_SPIM_EXPORTED_FUNCTIONS */ |
| AnnaBridge | 172:7d866c31b3c5 | 619 | |
| AnnaBridge | 172:7d866c31b3c5 | 620 | /*@}*/ /* end of group M480_SPIM_Driver */ |
| AnnaBridge | 172:7d866c31b3c5 | 621 | |
| AnnaBridge | 172:7d866c31b3c5 | 622 | /*@}*/ /* end of group M480_Device_Driver */ |
| AnnaBridge | 172:7d866c31b3c5 | 623 | |
| AnnaBridge | 172:7d866c31b3c5 | 624 | #ifdef __cplusplus |
| AnnaBridge | 172:7d866c31b3c5 | 625 | } |
| AnnaBridge | 172:7d866c31b3c5 | 626 | #endif |
| AnnaBridge | 172:7d866c31b3c5 | 627 | |
| AnnaBridge | 172:7d866c31b3c5 | 628 | #endif /* __SPIM_H__ */ |
| AnnaBridge | 172:7d866c31b3c5 | 629 | |
| AnnaBridge | 172:7d866c31b3c5 | 630 | /*** (C) COPYRIGHT 2017 Nuvoton Technology Corp. ***/ |
