mbed official / mbed-dev

Important changes to repositories hosted on mbed.com

Mbed hosted mercurial repositories are deprecated and are due to be permanently deleted in July 2026.

To keep a copy of this software download the repository Zip archive or clone locally using Mercurial.

It is also possible to export all your personal repositories from the account settings page.

Dependents:   Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

cmsis/BUILD/mbed/TARGET_NUCLEO_F302R8/TOOLCHAIN_GCC_ARM/stm32f3xx_ll_dma.h@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 189:f392fc9709a3 1 /**
AnnaBridge 189:f392fc9709a3 2 ******************************************************************************
AnnaBridge 189:f392fc9709a3 3 * @file stm32f3xx_ll_dma.h
AnnaBridge 189:f392fc9709a3 4 * @author MCD Application Team
AnnaBridge 189:f392fc9709a3 5 * @brief Header file of DMA LL module.
AnnaBridge 189:f392fc9709a3 6 ******************************************************************************
AnnaBridge 189:f392fc9709a3 7 * @attention
AnnaBridge 189:f392fc9709a3 8 *
AnnaBridge 189:f392fc9709a3 9 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
AnnaBridge 189:f392fc9709a3 10 *
AnnaBridge 189:f392fc9709a3 11 * Redistribution and use in source and binary forms, with or without modification,
AnnaBridge 189:f392fc9709a3 12 * are permitted provided that the following conditions are met:
AnnaBridge 189:f392fc9709a3 13 * 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge 189:f392fc9709a3 14 * this list of conditions and the following disclaimer.
AnnaBridge 189:f392fc9709a3 15 * 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge 189:f392fc9709a3 16 * this list of conditions and the following disclaimer in the documentation
AnnaBridge 189:f392fc9709a3 17 * and/or other materials provided with the distribution.
AnnaBridge 189:f392fc9709a3 18 * 3. Neither the name of STMicroelectronics nor the names of its contributors
AnnaBridge 189:f392fc9709a3 19 * may be used to endorse or promote products derived from this software
AnnaBridge 189:f392fc9709a3 20 * without specific prior written permission.
AnnaBridge 189:f392fc9709a3 21 *
AnnaBridge 189:f392fc9709a3 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge 189:f392fc9709a3 23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge 189:f392fc9709a3 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge 189:f392fc9709a3 25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge 189:f392fc9709a3 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge 189:f392fc9709a3 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge 189:f392fc9709a3 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge 189:f392fc9709a3 29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge 189:f392fc9709a3 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge 189:f392fc9709a3 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge 189:f392fc9709a3 32 *
AnnaBridge 189:f392fc9709a3 33 ******************************************************************************
AnnaBridge 189:f392fc9709a3 34 */
AnnaBridge 189:f392fc9709a3 35
AnnaBridge 189:f392fc9709a3 36 /* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge 189:f392fc9709a3 37 #ifndef __STM32F3xx_LL_DMA_H
AnnaBridge 189:f392fc9709a3 38 #define __STM32F3xx_LL_DMA_H
AnnaBridge 189:f392fc9709a3 39
AnnaBridge 189:f392fc9709a3 40 #ifdef __cplusplus
AnnaBridge 189:f392fc9709a3 41 extern "C" {
AnnaBridge 189:f392fc9709a3 42 #endif
AnnaBridge 189:f392fc9709a3 43
AnnaBridge 189:f392fc9709a3 44 /* Includes ------------------------------------------------------------------*/
AnnaBridge 189:f392fc9709a3 45 #include "stm32f3xx.h"
AnnaBridge 189:f392fc9709a3 46
AnnaBridge 189:f392fc9709a3 47 /** @addtogroup STM32F3xx_LL_Driver
AnnaBridge 189:f392fc9709a3 48 * @{
AnnaBridge 189:f392fc9709a3 49 */
AnnaBridge 189:f392fc9709a3 50
AnnaBridge 189:f392fc9709a3 51 #if defined (DMA1) || defined (DMA2)
AnnaBridge 189:f392fc9709a3 52
AnnaBridge 189:f392fc9709a3 53 /** @defgroup DMA_LL DMA
AnnaBridge 189:f392fc9709a3 54 * @{
AnnaBridge 189:f392fc9709a3 55 */
AnnaBridge 189:f392fc9709a3 56
AnnaBridge 189:f392fc9709a3 57 /* Private types -------------------------------------------------------------*/
AnnaBridge 189:f392fc9709a3 58 /* Private variables ---------------------------------------------------------*/
AnnaBridge 189:f392fc9709a3 59 /** @defgroup DMA_LL_Private_Variables DMA Private Variables
AnnaBridge 189:f392fc9709a3 60 * @{
AnnaBridge 189:f392fc9709a3 61 */
AnnaBridge 189:f392fc9709a3 62 /* Array used to get the DMA channel register offset versus channel index LL_DMA_CHANNEL_x */
AnnaBridge 189:f392fc9709a3 63 static const uint8_t CHANNEL_OFFSET_TAB[] =
AnnaBridge 189:f392fc9709a3 64 {
AnnaBridge 189:f392fc9709a3 65 (uint8_t)(DMA1_Channel1_BASE - DMA1_BASE),
AnnaBridge 189:f392fc9709a3 66 (uint8_t)(DMA1_Channel2_BASE - DMA1_BASE),
AnnaBridge 189:f392fc9709a3 67 (uint8_t)(DMA1_Channel3_BASE - DMA1_BASE),
AnnaBridge 189:f392fc9709a3 68 (uint8_t)(DMA1_Channel4_BASE - DMA1_BASE),
AnnaBridge 189:f392fc9709a3 69 (uint8_t)(DMA1_Channel5_BASE - DMA1_BASE),
AnnaBridge 189:f392fc9709a3 70 (uint8_t)(DMA1_Channel6_BASE - DMA1_BASE),
AnnaBridge 189:f392fc9709a3 71 (uint8_t)(DMA1_Channel7_BASE - DMA1_BASE)
AnnaBridge 189:f392fc9709a3 72 };
AnnaBridge 189:f392fc9709a3 73 /**
AnnaBridge 189:f392fc9709a3 74 * @}
AnnaBridge 189:f392fc9709a3 75 */
AnnaBridge 189:f392fc9709a3 76
AnnaBridge 189:f392fc9709a3 77 /* Private constants ---------------------------------------------------------*/
AnnaBridge 189:f392fc9709a3 78 /* Private macros ------------------------------------------------------------*/
AnnaBridge 189:f392fc9709a3 79 #if defined(USE_FULL_LL_DRIVER)
AnnaBridge 189:f392fc9709a3 80 /** @defgroup DMA_LL_Private_Macros DMA Private Macros
AnnaBridge 189:f392fc9709a3 81 * @{
AnnaBridge 189:f392fc9709a3 82 */
AnnaBridge 189:f392fc9709a3 83 /**
AnnaBridge 189:f392fc9709a3 84 * @}
AnnaBridge 189:f392fc9709a3 85 */
AnnaBridge 189:f392fc9709a3 86 #endif /*USE_FULL_LL_DRIVER*/
AnnaBridge 189:f392fc9709a3 87
AnnaBridge 189:f392fc9709a3 88 /* Exported types ------------------------------------------------------------*/
AnnaBridge 189:f392fc9709a3 89 #if defined(USE_FULL_LL_DRIVER)
AnnaBridge 189:f392fc9709a3 90 /** @defgroup DMA_LL_ES_INIT DMA Exported Init structure
AnnaBridge 189:f392fc9709a3 91 * @{
AnnaBridge 189:f392fc9709a3 92 */
AnnaBridge 189:f392fc9709a3 93 typedef struct
AnnaBridge 189:f392fc9709a3 94 {
AnnaBridge 189:f392fc9709a3 95 uint32_t PeriphOrM2MSrcAddress; /*!< Specifies the peripheral base address for DMA transfer
AnnaBridge 189:f392fc9709a3 96 or as Source base address in case of memory to memory transfer direction.
AnnaBridge 189:f392fc9709a3 97
AnnaBridge 189:f392fc9709a3 98 This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
AnnaBridge 189:f392fc9709a3 99
AnnaBridge 189:f392fc9709a3 100 uint32_t MemoryOrM2MDstAddress; /*!< Specifies the memory base address for DMA transfer
AnnaBridge 189:f392fc9709a3 101 or as Destination base address in case of memory to memory transfer direction.
AnnaBridge 189:f392fc9709a3 102
AnnaBridge 189:f392fc9709a3 103 This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
AnnaBridge 189:f392fc9709a3 104
AnnaBridge 189:f392fc9709a3 105 uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
AnnaBridge 189:f392fc9709a3 106 from memory to memory or from peripheral to memory.
AnnaBridge 189:f392fc9709a3 107 This parameter can be a value of @ref DMA_LL_EC_DIRECTION
AnnaBridge 189:f392fc9709a3 108
AnnaBridge 189:f392fc9709a3 109 This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataTransferDirection(). */
AnnaBridge 189:f392fc9709a3 110
AnnaBridge 189:f392fc9709a3 111 uint32_t Mode; /*!< Specifies the normal or circular operation mode.
AnnaBridge 189:f392fc9709a3 112 This parameter can be a value of @ref DMA_LL_EC_MODE
AnnaBridge 189:f392fc9709a3 113 @note: The circular buffer mode cannot be used if the memory to memory
AnnaBridge 189:f392fc9709a3 114 data transfer direction is configured on the selected Channel
AnnaBridge 189:f392fc9709a3 115
AnnaBridge 189:f392fc9709a3 116 This feature can be modified afterwards using unitary function @ref LL_DMA_SetMode(). */
AnnaBridge 189:f392fc9709a3 117
AnnaBridge 189:f392fc9709a3 118 uint32_t PeriphOrM2MSrcIncMode; /*!< Specifies whether the Peripheral address or Source address in case of memory to memory transfer direction
AnnaBridge 189:f392fc9709a3 119 is incremented or not.
AnnaBridge 189:f392fc9709a3 120 This parameter can be a value of @ref DMA_LL_EC_PERIPH
AnnaBridge 189:f392fc9709a3 121
AnnaBridge 189:f392fc9709a3 122 This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphIncMode(). */
AnnaBridge 189:f392fc9709a3 123
AnnaBridge 189:f392fc9709a3 124 uint32_t MemoryOrM2MDstIncMode; /*!< Specifies whether the Memory address or Destination address in case of memory to memory transfer direction
AnnaBridge 189:f392fc9709a3 125 is incremented or not.
AnnaBridge 189:f392fc9709a3 126 This parameter can be a value of @ref DMA_LL_EC_MEMORY
AnnaBridge 189:f392fc9709a3 127
AnnaBridge 189:f392fc9709a3 128 This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryIncMode(). */
AnnaBridge 189:f392fc9709a3 129
AnnaBridge 189:f392fc9709a3 130 uint32_t PeriphOrM2MSrcDataSize; /*!< Specifies the Peripheral data size alignment or Source data size alignment (byte, half word, word)
AnnaBridge 189:f392fc9709a3 131 in case of memory to memory transfer direction.
AnnaBridge 189:f392fc9709a3 132 This parameter can be a value of @ref DMA_LL_EC_PDATAALIGN
AnnaBridge 189:f392fc9709a3 133
AnnaBridge 189:f392fc9709a3 134 This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphSize(). */
AnnaBridge 189:f392fc9709a3 135
AnnaBridge 189:f392fc9709a3 136 uint32_t MemoryOrM2MDstDataSize; /*!< Specifies the Memory data size alignment or Destination data size alignment (byte, half word, word)
AnnaBridge 189:f392fc9709a3 137 in case of memory to memory transfer direction.
AnnaBridge 189:f392fc9709a3 138 This parameter can be a value of @ref DMA_LL_EC_MDATAALIGN
AnnaBridge 189:f392fc9709a3 139
AnnaBridge 189:f392fc9709a3 140 This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemorySize(). */
AnnaBridge 189:f392fc9709a3 141
AnnaBridge 189:f392fc9709a3 142 uint32_t NbData; /*!< Specifies the number of data to transfer, in data unit.
AnnaBridge 189:f392fc9709a3 143 The data unit is equal to the source buffer configuration set in PeripheralSize
AnnaBridge 189:f392fc9709a3 144 or MemorySize parameters depending in the transfer direction.
AnnaBridge 189:f392fc9709a3 145 This parameter must be a value between Min_Data = 0 and Max_Data = 0x0000FFFF
AnnaBridge 189:f392fc9709a3 146
AnnaBridge 189:f392fc9709a3 147 This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataLength(). */
AnnaBridge 189:f392fc9709a3 148
AnnaBridge 189:f392fc9709a3 149 uint32_t Priority; /*!< Specifies the channel priority level.
AnnaBridge 189:f392fc9709a3 150 This parameter can be a value of @ref DMA_LL_EC_PRIORITY
AnnaBridge 189:f392fc9709a3 151
AnnaBridge 189:f392fc9709a3 152 This feature can be modified afterwards using unitary function @ref LL_DMA_SetChannelPriorityLevel(). */
AnnaBridge 189:f392fc9709a3 153
AnnaBridge 189:f392fc9709a3 154 } LL_DMA_InitTypeDef;
AnnaBridge 189:f392fc9709a3 155 /**
AnnaBridge 189:f392fc9709a3 156 * @}
AnnaBridge 189:f392fc9709a3 157 */
AnnaBridge 189:f392fc9709a3 158 #endif /*USE_FULL_LL_DRIVER*/
AnnaBridge 189:f392fc9709a3 159
AnnaBridge 189:f392fc9709a3 160 /* Exported constants --------------------------------------------------------*/
AnnaBridge 189:f392fc9709a3 161 /** @defgroup DMA_LL_Exported_Constants DMA Exported Constants
AnnaBridge 189:f392fc9709a3 162 * @{
AnnaBridge 189:f392fc9709a3 163 */
AnnaBridge 189:f392fc9709a3 164 /** @defgroup DMA_LL_EC_CLEAR_FLAG Clear Flags Defines
AnnaBridge 189:f392fc9709a3 165 * @brief Flags defines which can be used with LL_DMA_WriteReg function
AnnaBridge 189:f392fc9709a3 166 * @{
AnnaBridge 189:f392fc9709a3 167 */
AnnaBridge 189:f392fc9709a3 168 #define LL_DMA_IFCR_CGIF1 DMA_IFCR_CGIF1 /*!< Channel 1 global flag */
AnnaBridge 189:f392fc9709a3 169 #define LL_DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1 /*!< Channel 1 transfer complete flag */
AnnaBridge 189:f392fc9709a3 170 #define LL_DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1 /*!< Channel 1 half transfer flag */
AnnaBridge 189:f392fc9709a3 171 #define LL_DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1 /*!< Channel 1 transfer error flag */
AnnaBridge 189:f392fc9709a3 172 #define LL_DMA_IFCR_CGIF2 DMA_IFCR_CGIF2 /*!< Channel 2 global flag */
AnnaBridge 189:f392fc9709a3 173 #define LL_DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2 /*!< Channel 2 transfer complete flag */
AnnaBridge 189:f392fc9709a3 174 #define LL_DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2 /*!< Channel 2 half transfer flag */
AnnaBridge 189:f392fc9709a3 175 #define LL_DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2 /*!< Channel 2 transfer error flag */
AnnaBridge 189:f392fc9709a3 176 #define LL_DMA_IFCR_CGIF3 DMA_IFCR_CGIF3 /*!< Channel 3 global flag */
AnnaBridge 189:f392fc9709a3 177 #define LL_DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3 /*!< Channel 3 transfer complete flag */
AnnaBridge 189:f392fc9709a3 178 #define LL_DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3 /*!< Channel 3 half transfer flag */
AnnaBridge 189:f392fc9709a3 179 #define LL_DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3 /*!< Channel 3 transfer error flag */
AnnaBridge 189:f392fc9709a3 180 #define LL_DMA_IFCR_CGIF4 DMA_IFCR_CGIF4 /*!< Channel 4 global flag */
AnnaBridge 189:f392fc9709a3 181 #define LL_DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4 /*!< Channel 4 transfer complete flag */
AnnaBridge 189:f392fc9709a3 182 #define LL_DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4 /*!< Channel 4 half transfer flag */
AnnaBridge 189:f392fc9709a3 183 #define LL_DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4 /*!< Channel 4 transfer error flag */
AnnaBridge 189:f392fc9709a3 184 #define LL_DMA_IFCR_CGIF5 DMA_IFCR_CGIF5 /*!< Channel 5 global flag */
AnnaBridge 189:f392fc9709a3 185 #define LL_DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5 /*!< Channel 5 transfer complete flag */
AnnaBridge 189:f392fc9709a3 186 #define LL_DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5 /*!< Channel 5 half transfer flag */
AnnaBridge 189:f392fc9709a3 187 #define LL_DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5 /*!< Channel 5 transfer error flag */
AnnaBridge 189:f392fc9709a3 188 #define LL_DMA_IFCR_CGIF6 DMA_IFCR_CGIF6 /*!< Channel 6 global flag */
AnnaBridge 189:f392fc9709a3 189 #define LL_DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6 /*!< Channel 6 transfer complete flag */
AnnaBridge 189:f392fc9709a3 190 #define LL_DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6 /*!< Channel 6 half transfer flag */
AnnaBridge 189:f392fc9709a3 191 #define LL_DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6 /*!< Channel 6 transfer error flag */
AnnaBridge 189:f392fc9709a3 192 #define LL_DMA_IFCR_CGIF7 DMA_IFCR_CGIF7 /*!< Channel 7 global flag */
AnnaBridge 189:f392fc9709a3 193 #define LL_DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7 /*!< Channel 7 transfer complete flag */
AnnaBridge 189:f392fc9709a3 194 #define LL_DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7 /*!< Channel 7 half transfer flag */
AnnaBridge 189:f392fc9709a3 195 #define LL_DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7 /*!< Channel 7 transfer error flag */
AnnaBridge 189:f392fc9709a3 196 /**
AnnaBridge 189:f392fc9709a3 197 * @}
AnnaBridge 189:f392fc9709a3 198 */
AnnaBridge 189:f392fc9709a3 199
AnnaBridge 189:f392fc9709a3 200 /** @defgroup DMA_LL_EC_GET_FLAG Get Flags Defines
AnnaBridge 189:f392fc9709a3 201 * @brief Flags defines which can be used with LL_DMA_ReadReg function
AnnaBridge 189:f392fc9709a3 202 * @{
AnnaBridge 189:f392fc9709a3 203 */
AnnaBridge 189:f392fc9709a3 204 #define LL_DMA_ISR_GIF1 DMA_ISR_GIF1 /*!< Channel 1 global flag */
AnnaBridge 189:f392fc9709a3 205 #define LL_DMA_ISR_TCIF1 DMA_ISR_TCIF1 /*!< Channel 1 transfer complete flag */
AnnaBridge 189:f392fc9709a3 206 #define LL_DMA_ISR_HTIF1 DMA_ISR_HTIF1 /*!< Channel 1 half transfer flag */
AnnaBridge 189:f392fc9709a3 207 #define LL_DMA_ISR_TEIF1 DMA_ISR_TEIF1 /*!< Channel 1 transfer error flag */
AnnaBridge 189:f392fc9709a3 208 #define LL_DMA_ISR_GIF2 DMA_ISR_GIF2 /*!< Channel 2 global flag */
AnnaBridge 189:f392fc9709a3 209 #define LL_DMA_ISR_TCIF2 DMA_ISR_TCIF2 /*!< Channel 2 transfer complete flag */
AnnaBridge 189:f392fc9709a3 210 #define LL_DMA_ISR_HTIF2 DMA_ISR_HTIF2 /*!< Channel 2 half transfer flag */
AnnaBridge 189:f392fc9709a3 211 #define LL_DMA_ISR_TEIF2 DMA_ISR_TEIF2 /*!< Channel 2 transfer error flag */
AnnaBridge 189:f392fc9709a3 212 #define LL_DMA_ISR_GIF3 DMA_ISR_GIF3 /*!< Channel 3 global flag */
AnnaBridge 189:f392fc9709a3 213 #define LL_DMA_ISR_TCIF3 DMA_ISR_TCIF3 /*!< Channel 3 transfer complete flag */
AnnaBridge 189:f392fc9709a3 214 #define LL_DMA_ISR_HTIF3 DMA_ISR_HTIF3 /*!< Channel 3 half transfer flag */
AnnaBridge 189:f392fc9709a3 215 #define LL_DMA_ISR_TEIF3 DMA_ISR_TEIF3 /*!< Channel 3 transfer error flag */
AnnaBridge 189:f392fc9709a3 216 #define LL_DMA_ISR_GIF4 DMA_ISR_GIF4 /*!< Channel 4 global flag */
AnnaBridge 189:f392fc9709a3 217 #define LL_DMA_ISR_TCIF4 DMA_ISR_TCIF4 /*!< Channel 4 transfer complete flag */
AnnaBridge 189:f392fc9709a3 218 #define LL_DMA_ISR_HTIF4 DMA_ISR_HTIF4 /*!< Channel 4 half transfer flag */
AnnaBridge 189:f392fc9709a3 219 #define LL_DMA_ISR_TEIF4 DMA_ISR_TEIF4 /*!< Channel 4 transfer error flag */
AnnaBridge 189:f392fc9709a3 220 #define LL_DMA_ISR_GIF5 DMA_ISR_GIF5 /*!< Channel 5 global flag */
AnnaBridge 189:f392fc9709a3 221 #define LL_DMA_ISR_TCIF5 DMA_ISR_TCIF5 /*!< Channel 5 transfer complete flag */
AnnaBridge 189:f392fc9709a3 222 #define LL_DMA_ISR_HTIF5 DMA_ISR_HTIF5 /*!< Channel 5 half transfer flag */
AnnaBridge 189:f392fc9709a3 223 #define LL_DMA_ISR_TEIF5 DMA_ISR_TEIF5 /*!< Channel 5 transfer error flag */
AnnaBridge 189:f392fc9709a3 224 #define LL_DMA_ISR_GIF6 DMA_ISR_GIF6 /*!< Channel 6 global flag */
AnnaBridge 189:f392fc9709a3 225 #define LL_DMA_ISR_TCIF6 DMA_ISR_TCIF6 /*!< Channel 6 transfer complete flag */
AnnaBridge 189:f392fc9709a3 226 #define LL_DMA_ISR_HTIF6 DMA_ISR_HTIF6 /*!< Channel 6 half transfer flag */
AnnaBridge 189:f392fc9709a3 227 #define LL_DMA_ISR_TEIF6 DMA_ISR_TEIF6 /*!< Channel 6 transfer error flag */
AnnaBridge 189:f392fc9709a3 228 #define LL_DMA_ISR_GIF7 DMA_ISR_GIF7 /*!< Channel 7 global flag */
AnnaBridge 189:f392fc9709a3 229 #define LL_DMA_ISR_TCIF7 DMA_ISR_TCIF7 /*!< Channel 7 transfer complete flag */
AnnaBridge 189:f392fc9709a3 230 #define LL_DMA_ISR_HTIF7 DMA_ISR_HTIF7 /*!< Channel 7 half transfer flag */
AnnaBridge 189:f392fc9709a3 231 #define LL_DMA_ISR_TEIF7 DMA_ISR_TEIF7 /*!< Channel 7 transfer error flag */
AnnaBridge 189:f392fc9709a3 232 /**
AnnaBridge 189:f392fc9709a3 233 * @}
AnnaBridge 189:f392fc9709a3 234 */
AnnaBridge 189:f392fc9709a3 235
AnnaBridge 189:f392fc9709a3 236 /** @defgroup DMA_LL_EC_IT IT Defines
AnnaBridge 189:f392fc9709a3 237 * @brief IT defines which can be used with LL_DMA_ReadReg and LL_DMA_WriteReg functions
AnnaBridge 189:f392fc9709a3 238 * @{
AnnaBridge 189:f392fc9709a3 239 */
AnnaBridge 189:f392fc9709a3 240 #define LL_DMA_CCR_TCIE DMA_CCR_TCIE /*!< Transfer complete interrupt */
AnnaBridge 189:f392fc9709a3 241 #define LL_DMA_CCR_HTIE DMA_CCR_HTIE /*!< Half Transfer interrupt */
AnnaBridge 189:f392fc9709a3 242 #define LL_DMA_CCR_TEIE DMA_CCR_TEIE /*!< Transfer error interrupt */
AnnaBridge 189:f392fc9709a3 243 /**
AnnaBridge 189:f392fc9709a3 244 * @}
AnnaBridge 189:f392fc9709a3 245 */
AnnaBridge 189:f392fc9709a3 246
AnnaBridge 189:f392fc9709a3 247 /** @defgroup DMA_LL_EC_CHANNEL CHANNEL
AnnaBridge 189:f392fc9709a3 248 * @{
AnnaBridge 189:f392fc9709a3 249 */
AnnaBridge 189:f392fc9709a3 250 #define LL_DMA_CHANNEL_1 0x00000001U /*!< DMA Channel 1 */
AnnaBridge 189:f392fc9709a3 251 #define LL_DMA_CHANNEL_2 0x00000002U /*!< DMA Channel 2 */
AnnaBridge 189:f392fc9709a3 252 #define LL_DMA_CHANNEL_3 0x00000003U /*!< DMA Channel 3 */
AnnaBridge 189:f392fc9709a3 253 #define LL_DMA_CHANNEL_4 0x00000004U /*!< DMA Channel 4 */
AnnaBridge 189:f392fc9709a3 254 #define LL_DMA_CHANNEL_5 0x00000005U /*!< DMA Channel 5 */
AnnaBridge 189:f392fc9709a3 255 #define LL_DMA_CHANNEL_6 0x00000006U /*!< DMA Channel 6 */
AnnaBridge 189:f392fc9709a3 256 #define LL_DMA_CHANNEL_7 0x00000007U /*!< DMA Channel 7 */
AnnaBridge 189:f392fc9709a3 257 #if defined(USE_FULL_LL_DRIVER)
AnnaBridge 189:f392fc9709a3 258 #define LL_DMA_CHANNEL_ALL 0xFFFF0000U /*!< DMA Channel all (used only for function @ref LL_DMA_DeInit(). */
AnnaBridge 189:f392fc9709a3 259 #endif /*USE_FULL_LL_DRIVER*/
AnnaBridge 189:f392fc9709a3 260 /**
AnnaBridge 189:f392fc9709a3 261 * @}
AnnaBridge 189:f392fc9709a3 262 */
AnnaBridge 189:f392fc9709a3 263
AnnaBridge 189:f392fc9709a3 264 /** @defgroup DMA_LL_EC_DIRECTION Transfer Direction
AnnaBridge 189:f392fc9709a3 265 * @{
AnnaBridge 189:f392fc9709a3 266 */
AnnaBridge 189:f392fc9709a3 267 #define LL_DMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */
AnnaBridge 189:f392fc9709a3 268 #define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_CCR_DIR /*!< Memory to peripheral direction */
AnnaBridge 189:f392fc9709a3 269 #define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_CCR_MEM2MEM /*!< Memory to memory direction */
AnnaBridge 189:f392fc9709a3 270 /**
AnnaBridge 189:f392fc9709a3 271 * @}
AnnaBridge 189:f392fc9709a3 272 */
AnnaBridge 189:f392fc9709a3 273
AnnaBridge 189:f392fc9709a3 274 /** @defgroup DMA_LL_EC_MODE Transfer mode
AnnaBridge 189:f392fc9709a3 275 * @{
AnnaBridge 189:f392fc9709a3 276 */
AnnaBridge 189:f392fc9709a3 277 #define LL_DMA_MODE_NORMAL 0x00000000U /*!< Normal Mode */
AnnaBridge 189:f392fc9709a3 278 #define LL_DMA_MODE_CIRCULAR DMA_CCR_CIRC /*!< Circular Mode */
AnnaBridge 189:f392fc9709a3 279 /**
AnnaBridge 189:f392fc9709a3 280 * @}
AnnaBridge 189:f392fc9709a3 281 */
AnnaBridge 189:f392fc9709a3 282
AnnaBridge 189:f392fc9709a3 283 /** @defgroup DMA_LL_EC_PERIPH Peripheral increment mode
AnnaBridge 189:f392fc9709a3 284 * @{
AnnaBridge 189:f392fc9709a3 285 */
AnnaBridge 189:f392fc9709a3 286 #define LL_DMA_PERIPH_INCREMENT DMA_CCR_PINC /*!< Peripheral increment mode Enable */
AnnaBridge 189:f392fc9709a3 287 #define LL_DMA_PERIPH_NOINCREMENT 0x00000000U /*!< Peripheral increment mode Disable */
AnnaBridge 189:f392fc9709a3 288 /**
AnnaBridge 189:f392fc9709a3 289 * @}
AnnaBridge 189:f392fc9709a3 290 */
AnnaBridge 189:f392fc9709a3 291
AnnaBridge 189:f392fc9709a3 292 /** @defgroup DMA_LL_EC_MEMORY Memory increment mode
AnnaBridge 189:f392fc9709a3 293 * @{
AnnaBridge 189:f392fc9709a3 294 */
AnnaBridge 189:f392fc9709a3 295 #define LL_DMA_MEMORY_INCREMENT DMA_CCR_MINC /*!< Memory increment mode Enable */
AnnaBridge 189:f392fc9709a3 296 #define LL_DMA_MEMORY_NOINCREMENT 0x00000000U /*!< Memory increment mode Disable */
AnnaBridge 189:f392fc9709a3 297 /**
AnnaBridge 189:f392fc9709a3 298 * @}
AnnaBridge 189:f392fc9709a3 299 */
AnnaBridge 189:f392fc9709a3 300
AnnaBridge 189:f392fc9709a3 301 /** @defgroup DMA_LL_EC_PDATAALIGN Peripheral data alignment
AnnaBridge 189:f392fc9709a3 302 * @{
AnnaBridge 189:f392fc9709a3 303 */
AnnaBridge 189:f392fc9709a3 304 #define LL_DMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment : Byte */
AnnaBridge 189:f392fc9709a3 305 #define LL_DMA_PDATAALIGN_HALFWORD DMA_CCR_PSIZE_0 /*!< Peripheral data alignment : HalfWord */
AnnaBridge 189:f392fc9709a3 306 #define LL_DMA_PDATAALIGN_WORD DMA_CCR_PSIZE_1 /*!< Peripheral data alignment : Word */
AnnaBridge 189:f392fc9709a3 307 /**
AnnaBridge 189:f392fc9709a3 308 * @}
AnnaBridge 189:f392fc9709a3 309 */
AnnaBridge 189:f392fc9709a3 310
AnnaBridge 189:f392fc9709a3 311 /** @defgroup DMA_LL_EC_MDATAALIGN Memory data alignment
AnnaBridge 189:f392fc9709a3 312 * @{
AnnaBridge 189:f392fc9709a3 313 */
AnnaBridge 189:f392fc9709a3 314 #define LL_DMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment : Byte */
AnnaBridge 189:f392fc9709a3 315 #define LL_DMA_MDATAALIGN_HALFWORD DMA_CCR_MSIZE_0 /*!< Memory data alignment : HalfWord */
AnnaBridge 189:f392fc9709a3 316 #define LL_DMA_MDATAALIGN_WORD DMA_CCR_MSIZE_1 /*!< Memory data alignment : Word */
AnnaBridge 189:f392fc9709a3 317 /**
AnnaBridge 189:f392fc9709a3 318 * @}
AnnaBridge 189:f392fc9709a3 319 */
AnnaBridge 189:f392fc9709a3 320
AnnaBridge 189:f392fc9709a3 321 /** @defgroup DMA_LL_EC_PRIORITY Transfer Priority level
AnnaBridge 189:f392fc9709a3 322 * @{
AnnaBridge 189:f392fc9709a3 323 */
AnnaBridge 189:f392fc9709a3 324 #define LL_DMA_PRIORITY_LOW 0x00000000U /*!< Priority level : Low */
AnnaBridge 189:f392fc9709a3 325 #define LL_DMA_PRIORITY_MEDIUM DMA_CCR_PL_0 /*!< Priority level : Medium */
AnnaBridge 189:f392fc9709a3 326 #define LL_DMA_PRIORITY_HIGH DMA_CCR_PL_1 /*!< Priority level : High */
AnnaBridge 189:f392fc9709a3 327 #define LL_DMA_PRIORITY_VERYHIGH DMA_CCR_PL /*!< Priority level : Very_High */
AnnaBridge 189:f392fc9709a3 328 /**
AnnaBridge 189:f392fc9709a3 329 * @}
AnnaBridge 189:f392fc9709a3 330 */
AnnaBridge 189:f392fc9709a3 331
AnnaBridge 189:f392fc9709a3 332
AnnaBridge 189:f392fc9709a3 333 /**
AnnaBridge 189:f392fc9709a3 334 * @}
AnnaBridge 189:f392fc9709a3 335 */
AnnaBridge 189:f392fc9709a3 336
AnnaBridge 189:f392fc9709a3 337 /* Exported macro ------------------------------------------------------------*/
AnnaBridge 189:f392fc9709a3 338 /** @defgroup DMA_LL_Exported_Macros DMA Exported Macros
AnnaBridge 189:f392fc9709a3 339 * @{
AnnaBridge 189:f392fc9709a3 340 */
AnnaBridge 189:f392fc9709a3 341
AnnaBridge 189:f392fc9709a3 342 /** @defgroup DMA_LL_EM_WRITE_READ Common Write and read registers macros
AnnaBridge 189:f392fc9709a3 343 * @{
AnnaBridge 189:f392fc9709a3 344 */
AnnaBridge 189:f392fc9709a3 345 /**
AnnaBridge 189:f392fc9709a3 346 * @brief Write a value in DMA register
AnnaBridge 189:f392fc9709a3 347 * @param __INSTANCE__ DMA Instance
AnnaBridge 189:f392fc9709a3 348 * @param __REG__ Register to be written
AnnaBridge 189:f392fc9709a3 349 * @param __VALUE__ Value to be written in the register
AnnaBridge 189:f392fc9709a3 350 * @retval None
AnnaBridge 189:f392fc9709a3 351 */
AnnaBridge 189:f392fc9709a3 352 #define LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
AnnaBridge 189:f392fc9709a3 353
AnnaBridge 189:f392fc9709a3 354 /**
AnnaBridge 189:f392fc9709a3 355 * @brief Read a value in DMA register
AnnaBridge 189:f392fc9709a3 356 * @param __INSTANCE__ DMA Instance
AnnaBridge 189:f392fc9709a3 357 * @param __REG__ Register to be read
AnnaBridge 189:f392fc9709a3 358 * @retval Register value
AnnaBridge 189:f392fc9709a3 359 */
AnnaBridge 189:f392fc9709a3 360 #define LL_DMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
AnnaBridge 189:f392fc9709a3 361 /**
AnnaBridge 189:f392fc9709a3 362 * @}
AnnaBridge 189:f392fc9709a3 363 */
AnnaBridge 189:f392fc9709a3 364
AnnaBridge 189:f392fc9709a3 365 /** @defgroup DMA_LL_EM_CONVERT_DMAxCHANNELy Convert DMAxChannely
AnnaBridge 189:f392fc9709a3 366 * @{
AnnaBridge 189:f392fc9709a3 367 */
AnnaBridge 189:f392fc9709a3 368 /**
AnnaBridge 189:f392fc9709a3 369 * @brief Convert DMAx_Channely into DMAx
AnnaBridge 189:f392fc9709a3 370 * @param __CHANNEL_INSTANCE__ DMAx_Channely
AnnaBridge 189:f392fc9709a3 371 * @retval DMAx
AnnaBridge 189:f392fc9709a3 372 */
AnnaBridge 189:f392fc9709a3 373 #if defined(DMA2)
AnnaBridge 189:f392fc9709a3 374 #define __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__) \
AnnaBridge 189:f392fc9709a3 375 (((uint32_t)(__CHANNEL_INSTANCE__) > ((uint32_t)DMA1_Channel7)) ? DMA2 : DMA1)
AnnaBridge 189:f392fc9709a3 376 #else
AnnaBridge 189:f392fc9709a3 377 #define __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__) (DMA1)
AnnaBridge 189:f392fc9709a3 378 #endif
AnnaBridge 189:f392fc9709a3 379
AnnaBridge 189:f392fc9709a3 380 /**
AnnaBridge 189:f392fc9709a3 381 * @brief Convert DMAx_Channely into LL_DMA_CHANNEL_y
AnnaBridge 189:f392fc9709a3 382 * @param __CHANNEL_INSTANCE__ DMAx_Channely
AnnaBridge 189:f392fc9709a3 383 * @retval LL_DMA_CHANNEL_y
AnnaBridge 189:f392fc9709a3 384 */
AnnaBridge 189:f392fc9709a3 385 #if defined (DMA2)
AnnaBridge 189:f392fc9709a3 386 #if defined (DMA2_Channel6) && defined (DMA2_Channel7)
AnnaBridge 189:f392fc9709a3 387 #define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \
AnnaBridge 189:f392fc9709a3 388 (((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
AnnaBridge 189:f392fc9709a3 389 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel1)) ? LL_DMA_CHANNEL_1 : \
AnnaBridge 189:f392fc9709a3 390 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
AnnaBridge 189:f392fc9709a3 391 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel2)) ? LL_DMA_CHANNEL_2 : \
AnnaBridge 189:f392fc9709a3 392 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
AnnaBridge 189:f392fc9709a3 393 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel3)) ? LL_DMA_CHANNEL_3 : \
AnnaBridge 189:f392fc9709a3 394 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
AnnaBridge 189:f392fc9709a3 395 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel4)) ? LL_DMA_CHANNEL_4 : \
AnnaBridge 189:f392fc9709a3 396 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \
AnnaBridge 189:f392fc9709a3 397 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel5)) ? LL_DMA_CHANNEL_5 : \
AnnaBridge 189:f392fc9709a3 398 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \
AnnaBridge 189:f392fc9709a3 399 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel6)) ? LL_DMA_CHANNEL_6 : \
AnnaBridge 189:f392fc9709a3 400 LL_DMA_CHANNEL_7)
AnnaBridge 189:f392fc9709a3 401 #else
AnnaBridge 189:f392fc9709a3 402 #define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \
AnnaBridge 189:f392fc9709a3 403 (((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
AnnaBridge 189:f392fc9709a3 404 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel1)) ? LL_DMA_CHANNEL_1 : \
AnnaBridge 189:f392fc9709a3 405 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
AnnaBridge 189:f392fc9709a3 406 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel2)) ? LL_DMA_CHANNEL_2 : \
AnnaBridge 189:f392fc9709a3 407 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
AnnaBridge 189:f392fc9709a3 408 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel3)) ? LL_DMA_CHANNEL_3 : \
AnnaBridge 189:f392fc9709a3 409 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
AnnaBridge 189:f392fc9709a3 410 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel4)) ? LL_DMA_CHANNEL_4 : \
AnnaBridge 189:f392fc9709a3 411 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \
AnnaBridge 189:f392fc9709a3 412 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel5)) ? LL_DMA_CHANNEL_5 : \
AnnaBridge 189:f392fc9709a3 413 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \
AnnaBridge 189:f392fc9709a3 414 LL_DMA_CHANNEL_7)
AnnaBridge 189:f392fc9709a3 415 #endif
AnnaBridge 189:f392fc9709a3 416 #else
AnnaBridge 189:f392fc9709a3 417 #define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \
AnnaBridge 189:f392fc9709a3 418 (((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
AnnaBridge 189:f392fc9709a3 419 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
AnnaBridge 189:f392fc9709a3 420 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
AnnaBridge 189:f392fc9709a3 421 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
AnnaBridge 189:f392fc9709a3 422 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \
AnnaBridge 189:f392fc9709a3 423 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \
AnnaBridge 189:f392fc9709a3 424 LL_DMA_CHANNEL_7)
AnnaBridge 189:f392fc9709a3 425 #endif
AnnaBridge 189:f392fc9709a3 426
AnnaBridge 189:f392fc9709a3 427 /**
AnnaBridge 189:f392fc9709a3 428 * @brief Convert DMA Instance DMAx and LL_DMA_CHANNEL_y into DMAx_Channely
AnnaBridge 189:f392fc9709a3 429 * @param __DMA_INSTANCE__ DMAx
AnnaBridge 189:f392fc9709a3 430 * @param __CHANNEL__ LL_DMA_CHANNEL_y
AnnaBridge 189:f392fc9709a3 431 * @retval DMAx_Channely
AnnaBridge 189:f392fc9709a3 432 */
AnnaBridge 189:f392fc9709a3 433 #if defined (DMA2)
AnnaBridge 189:f392fc9709a3 434 #if defined (DMA2_Channel6) && defined (DMA2_Channel7)
AnnaBridge 189:f392fc9709a3 435 #define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \
AnnaBridge 189:f392fc9709a3 436 ((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
AnnaBridge 189:f392fc9709a3 437 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA2_Channel1 : \
AnnaBridge 189:f392fc9709a3 438 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
AnnaBridge 189:f392fc9709a3 439 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA2_Channel2 : \
AnnaBridge 189:f392fc9709a3 440 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \
AnnaBridge 189:f392fc9709a3 441 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA2_Channel3 : \
AnnaBridge 189:f392fc9709a3 442 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \
AnnaBridge 189:f392fc9709a3 443 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA2_Channel4 : \
AnnaBridge 189:f392fc9709a3 444 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \
AnnaBridge 189:f392fc9709a3 445 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA2_Channel5 : \
AnnaBridge 189:f392fc9709a3 446 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \
AnnaBridge 189:f392fc9709a3 447 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA2_Channel6 : \
AnnaBridge 189:f392fc9709a3 448 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_7))) ? DMA1_Channel7 : \
AnnaBridge 189:f392fc9709a3 449 DMA2_Channel7)
AnnaBridge 189:f392fc9709a3 450 #else
AnnaBridge 189:f392fc9709a3 451 #define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \
AnnaBridge 189:f392fc9709a3 452 ((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
AnnaBridge 189:f392fc9709a3 453 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA2_Channel1 : \
AnnaBridge 189:f392fc9709a3 454 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
AnnaBridge 189:f392fc9709a3 455 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA2_Channel2 : \
AnnaBridge 189:f392fc9709a3 456 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \
AnnaBridge 189:f392fc9709a3 457 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA2_Channel3 : \
AnnaBridge 189:f392fc9709a3 458 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \
AnnaBridge 189:f392fc9709a3 459 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA2_Channel4 : \
AnnaBridge 189:f392fc9709a3 460 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \
AnnaBridge 189:f392fc9709a3 461 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA2_Channel5 : \
AnnaBridge 189:f392fc9709a3 462 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \
AnnaBridge 189:f392fc9709a3 463 DMA1_Channel7)
AnnaBridge 189:f392fc9709a3 464 #endif
AnnaBridge 189:f392fc9709a3 465 #else
AnnaBridge 189:f392fc9709a3 466 #define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \
AnnaBridge 189:f392fc9709a3 467 ((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
AnnaBridge 189:f392fc9709a3 468 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
AnnaBridge 189:f392fc9709a3 469 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \
AnnaBridge 189:f392fc9709a3 470 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \
AnnaBridge 189:f392fc9709a3 471 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \
AnnaBridge 189:f392fc9709a3 472 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \
AnnaBridge 189:f392fc9709a3 473 DMA1_Channel7)
AnnaBridge 189:f392fc9709a3 474 #endif
AnnaBridge 189:f392fc9709a3 475
AnnaBridge 189:f392fc9709a3 476 /**
AnnaBridge 189:f392fc9709a3 477 * @}
AnnaBridge 189:f392fc9709a3 478 */
AnnaBridge 189:f392fc9709a3 479
AnnaBridge 189:f392fc9709a3 480 /**
AnnaBridge 189:f392fc9709a3 481 * @}
AnnaBridge 189:f392fc9709a3 482 */
AnnaBridge 189:f392fc9709a3 483
AnnaBridge 189:f392fc9709a3 484 /* Exported functions --------------------------------------------------------*/
AnnaBridge 189:f392fc9709a3 485 /** @defgroup DMA_LL_Exported_Functions DMA Exported Functions
AnnaBridge 189:f392fc9709a3 486 * @{
AnnaBridge 189:f392fc9709a3 487 */
AnnaBridge 189:f392fc9709a3 488
AnnaBridge 189:f392fc9709a3 489 /** @defgroup DMA_LL_EF_Configuration Configuration
AnnaBridge 189:f392fc9709a3 490 * @{
AnnaBridge 189:f392fc9709a3 491 */
AnnaBridge 189:f392fc9709a3 492 /**
AnnaBridge 189:f392fc9709a3 493 * @brief Enable DMA channel.
AnnaBridge 189:f392fc9709a3 494 * @rmtoll CCR EN LL_DMA_EnableChannel
AnnaBridge 189:f392fc9709a3 495 * @param DMAx DMAx Instance
AnnaBridge 189:f392fc9709a3 496 * @param Channel This parameter can be one of the following values:
AnnaBridge 189:f392fc9709a3 497 * @arg @ref LL_DMA_CHANNEL_1
AnnaBridge 189:f392fc9709a3 498 * @arg @ref LL_DMA_CHANNEL_2
AnnaBridge 189:f392fc9709a3 499 * @arg @ref LL_DMA_CHANNEL_3
AnnaBridge 189:f392fc9709a3 500 * @arg @ref LL_DMA_CHANNEL_4
AnnaBridge 189:f392fc9709a3 501 * @arg @ref LL_DMA_CHANNEL_5
AnnaBridge 189:f392fc9709a3 502 * @arg @ref LL_DMA_CHANNEL_6
AnnaBridge 189:f392fc9709a3 503 * @arg @ref LL_DMA_CHANNEL_7
AnnaBridge 189:f392fc9709a3 504 * @retval None
AnnaBridge 189:f392fc9709a3 505 */
AnnaBridge 189:f392fc9709a3 506 __STATIC_INLINE void LL_DMA_EnableChannel(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge 189:f392fc9709a3 507 {
AnnaBridge 189:f392fc9709a3 508 SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_EN);
AnnaBridge 189:f392fc9709a3 509 }
AnnaBridge 189:f392fc9709a3 510
AnnaBridge 189:f392fc9709a3 511 /**
AnnaBridge 189:f392fc9709a3 512 * @brief Disable DMA channel.
AnnaBridge 189:f392fc9709a3 513 * @rmtoll CCR EN LL_DMA_DisableChannel
AnnaBridge 189:f392fc9709a3 514 * @param DMAx DMAx Instance
AnnaBridge 189:f392fc9709a3 515 * @param Channel This parameter can be one of the following values:
AnnaBridge 189:f392fc9709a3 516 * @arg @ref LL_DMA_CHANNEL_1
AnnaBridge 189:f392fc9709a3 517 * @arg @ref LL_DMA_CHANNEL_2
AnnaBridge 189:f392fc9709a3 518 * @arg @ref LL_DMA_CHANNEL_3
AnnaBridge 189:f392fc9709a3 519 * @arg @ref LL_DMA_CHANNEL_4
AnnaBridge 189:f392fc9709a3 520 * @arg @ref LL_DMA_CHANNEL_5
AnnaBridge 189:f392fc9709a3 521 * @arg @ref LL_DMA_CHANNEL_6
AnnaBridge 189:f392fc9709a3 522 * @arg @ref LL_DMA_CHANNEL_7
AnnaBridge 189:f392fc9709a3 523 * @retval None
AnnaBridge 189:f392fc9709a3 524 */
AnnaBridge 189:f392fc9709a3 525 __STATIC_INLINE void LL_DMA_DisableChannel(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge 189:f392fc9709a3 526 {
AnnaBridge 189:f392fc9709a3 527 CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_EN);
AnnaBridge 189:f392fc9709a3 528 }
AnnaBridge 189:f392fc9709a3 529
AnnaBridge 189:f392fc9709a3 530 /**
AnnaBridge 189:f392fc9709a3 531 * @brief Check if DMA channel is enabled or disabled.
AnnaBridge 189:f392fc9709a3 532 * @rmtoll CCR EN LL_DMA_IsEnabledChannel
AnnaBridge 189:f392fc9709a3 533 * @param DMAx DMAx Instance
AnnaBridge 189:f392fc9709a3 534 * @param Channel This parameter can be one of the following values:
AnnaBridge 189:f392fc9709a3 535 * @arg @ref LL_DMA_CHANNEL_1
AnnaBridge 189:f392fc9709a3 536 * @arg @ref LL_DMA_CHANNEL_2
AnnaBridge 189:f392fc9709a3 537 * @arg @ref LL_DMA_CHANNEL_3
AnnaBridge 189:f392fc9709a3 538 * @arg @ref LL_DMA_CHANNEL_4
AnnaBridge 189:f392fc9709a3 539 * @arg @ref LL_DMA_CHANNEL_5
AnnaBridge 189:f392fc9709a3 540 * @arg @ref LL_DMA_CHANNEL_6
AnnaBridge 189:f392fc9709a3 541 * @arg @ref LL_DMA_CHANNEL_7
AnnaBridge 189:f392fc9709a3 542 * @retval State of bit (1 or 0).
AnnaBridge 189:f392fc9709a3 543 */
AnnaBridge 189:f392fc9709a3 544 __STATIC_INLINE uint32_t LL_DMA_IsEnabledChannel(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge 189:f392fc9709a3 545 {
AnnaBridge 189:f392fc9709a3 546 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
AnnaBridge 189:f392fc9709a3 547 DMA_CCR_EN) == (DMA_CCR_EN));
AnnaBridge 189:f392fc9709a3 548 }
AnnaBridge 189:f392fc9709a3 549
AnnaBridge 189:f392fc9709a3 550 /**
AnnaBridge 189:f392fc9709a3 551 * @brief Configure all parameters link to DMA transfer.
AnnaBridge 189:f392fc9709a3 552 * @rmtoll CCR DIR LL_DMA_ConfigTransfer\n
AnnaBridge 189:f392fc9709a3 553 * CCR MEM2MEM LL_DMA_ConfigTransfer\n
AnnaBridge 189:f392fc9709a3 554 * CCR CIRC LL_DMA_ConfigTransfer\n
AnnaBridge 189:f392fc9709a3 555 * CCR PINC LL_DMA_ConfigTransfer\n
AnnaBridge 189:f392fc9709a3 556 * CCR MINC LL_DMA_ConfigTransfer\n
AnnaBridge 189:f392fc9709a3 557 * CCR PSIZE LL_DMA_ConfigTransfer\n
AnnaBridge 189:f392fc9709a3 558 * CCR MSIZE LL_DMA_ConfigTransfer\n
AnnaBridge 189:f392fc9709a3 559 * CCR PL LL_DMA_ConfigTransfer
AnnaBridge 189:f392fc9709a3 560 * @param DMAx DMAx Instance
AnnaBridge 189:f392fc9709a3 561 * @param Channel This parameter can be one of the following values:
AnnaBridge 189:f392fc9709a3 562 * @arg @ref LL_DMA_CHANNEL_1
AnnaBridge 189:f392fc9709a3 563 * @arg @ref LL_DMA_CHANNEL_2
AnnaBridge 189:f392fc9709a3 564 * @arg @ref LL_DMA_CHANNEL_3
AnnaBridge 189:f392fc9709a3 565 * @arg @ref LL_DMA_CHANNEL_4
AnnaBridge 189:f392fc9709a3 566 * @arg @ref LL_DMA_CHANNEL_5
AnnaBridge 189:f392fc9709a3 567 * @arg @ref LL_DMA_CHANNEL_6
AnnaBridge 189:f392fc9709a3 568 * @arg @ref LL_DMA_CHANNEL_7
AnnaBridge 189:f392fc9709a3 569 * @param Configuration This parameter must be a combination of all the following values:
AnnaBridge 189:f392fc9709a3 570 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY or @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH or @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
AnnaBridge 189:f392fc9709a3 571 * @arg @ref LL_DMA_MODE_NORMAL or @ref LL_DMA_MODE_CIRCULAR
AnnaBridge 189:f392fc9709a3 572 * @arg @ref LL_DMA_PERIPH_INCREMENT or @ref LL_DMA_PERIPH_NOINCREMENT
AnnaBridge 189:f392fc9709a3 573 * @arg @ref LL_DMA_MEMORY_INCREMENT or @ref LL_DMA_MEMORY_NOINCREMENT
AnnaBridge 189:f392fc9709a3 574 * @arg @ref LL_DMA_PDATAALIGN_BYTE or @ref LL_DMA_PDATAALIGN_HALFWORD or @ref LL_DMA_PDATAALIGN_WORD
AnnaBridge 189:f392fc9709a3 575 * @arg @ref LL_DMA_MDATAALIGN_BYTE or @ref LL_DMA_MDATAALIGN_HALFWORD or @ref LL_DMA_MDATAALIGN_WORD
AnnaBridge 189:f392fc9709a3 576 * @arg @ref LL_DMA_PRIORITY_LOW or @ref LL_DMA_PRIORITY_MEDIUM or @ref LL_DMA_PRIORITY_HIGH or @ref LL_DMA_PRIORITY_VERYHIGH
AnnaBridge 189:f392fc9709a3 577 * @retval None
AnnaBridge 189:f392fc9709a3 578 */
AnnaBridge 189:f392fc9709a3 579 __STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration)
AnnaBridge 189:f392fc9709a3 580 {
AnnaBridge 189:f392fc9709a3 581 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
AnnaBridge 189:f392fc9709a3 582 DMA_CCR_DIR | DMA_CCR_MEM2MEM | DMA_CCR_CIRC | DMA_CCR_PINC | DMA_CCR_MINC | DMA_CCR_PSIZE | DMA_CCR_MSIZE | DMA_CCR_PL,
AnnaBridge 189:f392fc9709a3 583 Configuration);
AnnaBridge 189:f392fc9709a3 584 }
AnnaBridge 189:f392fc9709a3 585
AnnaBridge 189:f392fc9709a3 586 /**
AnnaBridge 189:f392fc9709a3 587 * @brief Set Data transfer direction (read from peripheral or from memory).
AnnaBridge 189:f392fc9709a3 588 * @rmtoll CCR DIR LL_DMA_SetDataTransferDirection\n
AnnaBridge 189:f392fc9709a3 589 * CCR MEM2MEM LL_DMA_SetDataTransferDirection
AnnaBridge 189:f392fc9709a3 590 * @param DMAx DMAx Instance
AnnaBridge 189:f392fc9709a3 591 * @param Channel This parameter can be one of the following values:
AnnaBridge 189:f392fc9709a3 592 * @arg @ref LL_DMA_CHANNEL_1
AnnaBridge 189:f392fc9709a3 593 * @arg @ref LL_DMA_CHANNEL_2
AnnaBridge 189:f392fc9709a3 594 * @arg @ref LL_DMA_CHANNEL_3
AnnaBridge 189:f392fc9709a3 595 * @arg @ref LL_DMA_CHANNEL_4
AnnaBridge 189:f392fc9709a3 596 * @arg @ref LL_DMA_CHANNEL_5
AnnaBridge 189:f392fc9709a3 597 * @arg @ref LL_DMA_CHANNEL_6
AnnaBridge 189:f392fc9709a3 598 * @arg @ref LL_DMA_CHANNEL_7
AnnaBridge 189:f392fc9709a3 599 * @param Direction This parameter can be one of the following values:
AnnaBridge 189:f392fc9709a3 600 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
AnnaBridge 189:f392fc9709a3 601 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
AnnaBridge 189:f392fc9709a3 602 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
AnnaBridge 189:f392fc9709a3 603 * @retval None
AnnaBridge 189:f392fc9709a3 604 */
AnnaBridge 189:f392fc9709a3 605 __STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Direction)
AnnaBridge 189:f392fc9709a3 606 {
AnnaBridge 189:f392fc9709a3 607 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
AnnaBridge 189:f392fc9709a3 608 DMA_CCR_DIR | DMA_CCR_MEM2MEM, Direction);
AnnaBridge 189:f392fc9709a3 609 }
AnnaBridge 189:f392fc9709a3 610
AnnaBridge 189:f392fc9709a3 611 /**
AnnaBridge 189:f392fc9709a3 612 * @brief Get Data transfer direction (read from peripheral or from memory).
AnnaBridge 189:f392fc9709a3 613 * @rmtoll CCR DIR LL_DMA_GetDataTransferDirection\n
AnnaBridge 189:f392fc9709a3 614 * CCR MEM2MEM LL_DMA_GetDataTransferDirection
AnnaBridge 189:f392fc9709a3 615 * @param DMAx DMAx Instance
AnnaBridge 189:f392fc9709a3 616 * @param Channel This parameter can be one of the following values:
AnnaBridge 189:f392fc9709a3 617 * @arg @ref LL_DMA_CHANNEL_1
AnnaBridge 189:f392fc9709a3 618 * @arg @ref LL_DMA_CHANNEL_2
AnnaBridge 189:f392fc9709a3 619 * @arg @ref LL_DMA_CHANNEL_3
AnnaBridge 189:f392fc9709a3 620 * @arg @ref LL_DMA_CHANNEL_4
AnnaBridge 189:f392fc9709a3 621 * @arg @ref LL_DMA_CHANNEL_5
AnnaBridge 189:f392fc9709a3 622 * @arg @ref LL_DMA_CHANNEL_6
AnnaBridge 189:f392fc9709a3 623 * @arg @ref LL_DMA_CHANNEL_7
AnnaBridge 189:f392fc9709a3 624 * @retval Returned value can be one of the following values:
AnnaBridge 189:f392fc9709a3 625 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
AnnaBridge 189:f392fc9709a3 626 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
AnnaBridge 189:f392fc9709a3 627 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
AnnaBridge 189:f392fc9709a3 628 */
AnnaBridge 189:f392fc9709a3 629 __STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge 189:f392fc9709a3 630 {
AnnaBridge 189:f392fc9709a3 631 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
AnnaBridge 189:f392fc9709a3 632 DMA_CCR_DIR | DMA_CCR_MEM2MEM));
AnnaBridge 189:f392fc9709a3 633 }
AnnaBridge 189:f392fc9709a3 634
AnnaBridge 189:f392fc9709a3 635 /**
AnnaBridge 189:f392fc9709a3 636 * @brief Set DMA mode circular or normal.
AnnaBridge 189:f392fc9709a3 637 * @note The circular buffer mode cannot be used if the memory-to-memory
AnnaBridge 189:f392fc9709a3 638 * data transfer is configured on the selected Channel.
AnnaBridge 189:f392fc9709a3 639 * @rmtoll CCR CIRC LL_DMA_SetMode
AnnaBridge 189:f392fc9709a3 640 * @param DMAx DMAx Instance
AnnaBridge 189:f392fc9709a3 641 * @param Channel This parameter can be one of the following values:
AnnaBridge 189:f392fc9709a3 642 * @arg @ref LL_DMA_CHANNEL_1
AnnaBridge 189:f392fc9709a3 643 * @arg @ref LL_DMA_CHANNEL_2
AnnaBridge 189:f392fc9709a3 644 * @arg @ref LL_DMA_CHANNEL_3
AnnaBridge 189:f392fc9709a3 645 * @arg @ref LL_DMA_CHANNEL_4
AnnaBridge 189:f392fc9709a3 646 * @arg @ref LL_DMA_CHANNEL_5
AnnaBridge 189:f392fc9709a3 647 * @arg @ref LL_DMA_CHANNEL_6
AnnaBridge 189:f392fc9709a3 648 * @arg @ref LL_DMA_CHANNEL_7
AnnaBridge 189:f392fc9709a3 649 * @param Mode This parameter can be one of the following values:
AnnaBridge 189:f392fc9709a3 650 * @arg @ref LL_DMA_MODE_NORMAL
AnnaBridge 189:f392fc9709a3 651 * @arg @ref LL_DMA_MODE_CIRCULAR
AnnaBridge 189:f392fc9709a3 652 * @retval None
AnnaBridge 189:f392fc9709a3 653 */
AnnaBridge 189:f392fc9709a3 654 __STATIC_INLINE void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Mode)
AnnaBridge 189:f392fc9709a3 655 {
AnnaBridge 189:f392fc9709a3 656 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_CIRC,
AnnaBridge 189:f392fc9709a3 657 Mode);
AnnaBridge 189:f392fc9709a3 658 }
AnnaBridge 189:f392fc9709a3 659
AnnaBridge 189:f392fc9709a3 660 /**
AnnaBridge 189:f392fc9709a3 661 * @brief Get DMA mode circular or normal.
AnnaBridge 189:f392fc9709a3 662 * @rmtoll CCR CIRC LL_DMA_GetMode
AnnaBridge 189:f392fc9709a3 663 * @param DMAx DMAx Instance
AnnaBridge 189:f392fc9709a3 664 * @param Channel This parameter can be one of the following values:
AnnaBridge 189:f392fc9709a3 665 * @arg @ref LL_DMA_CHANNEL_1
AnnaBridge 189:f392fc9709a3 666 * @arg @ref LL_DMA_CHANNEL_2
AnnaBridge 189:f392fc9709a3 667 * @arg @ref LL_DMA_CHANNEL_3
AnnaBridge 189:f392fc9709a3 668 * @arg @ref LL_DMA_CHANNEL_4
AnnaBridge 189:f392fc9709a3 669 * @arg @ref LL_DMA_CHANNEL_5
AnnaBridge 189:f392fc9709a3 670 * @arg @ref LL_DMA_CHANNEL_6
AnnaBridge 189:f392fc9709a3 671 * @arg @ref LL_DMA_CHANNEL_7
AnnaBridge 189:f392fc9709a3 672 * @retval Returned value can be one of the following values:
AnnaBridge 189:f392fc9709a3 673 * @arg @ref LL_DMA_MODE_NORMAL
AnnaBridge 189:f392fc9709a3 674 * @arg @ref LL_DMA_MODE_CIRCULAR
AnnaBridge 189:f392fc9709a3 675 */
AnnaBridge 189:f392fc9709a3 676 __STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge 189:f392fc9709a3 677 {
AnnaBridge 189:f392fc9709a3 678 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
AnnaBridge 189:f392fc9709a3 679 DMA_CCR_CIRC));
AnnaBridge 189:f392fc9709a3 680 }
AnnaBridge 189:f392fc9709a3 681
AnnaBridge 189:f392fc9709a3 682 /**
AnnaBridge 189:f392fc9709a3 683 * @brief Set Peripheral increment mode.
AnnaBridge 189:f392fc9709a3 684 * @rmtoll CCR PINC LL_DMA_SetPeriphIncMode
AnnaBridge 189:f392fc9709a3 685 * @param DMAx DMAx Instance
AnnaBridge 189:f392fc9709a3 686 * @param Channel This parameter can be one of the following values:
AnnaBridge 189:f392fc9709a3 687 * @arg @ref LL_DMA_CHANNEL_1
AnnaBridge 189:f392fc9709a3 688 * @arg @ref LL_DMA_CHANNEL_2
AnnaBridge 189:f392fc9709a3 689 * @arg @ref LL_DMA_CHANNEL_3
AnnaBridge 189:f392fc9709a3 690 * @arg @ref LL_DMA_CHANNEL_4
AnnaBridge 189:f392fc9709a3 691 * @arg @ref LL_DMA_CHANNEL_5
AnnaBridge 189:f392fc9709a3 692 * @arg @ref LL_DMA_CHANNEL_6
AnnaBridge 189:f392fc9709a3 693 * @arg @ref LL_DMA_CHANNEL_7
AnnaBridge 189:f392fc9709a3 694 * @param PeriphOrM2MSrcIncMode This parameter can be one of the following values:
AnnaBridge 189:f392fc9709a3 695 * @arg @ref LL_DMA_PERIPH_INCREMENT
AnnaBridge 189:f392fc9709a3 696 * @arg @ref LL_DMA_PERIPH_NOINCREMENT
AnnaBridge 189:f392fc9709a3 697 * @retval None
AnnaBridge 189:f392fc9709a3 698 */
AnnaBridge 189:f392fc9709a3 699 __STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcIncMode)
AnnaBridge 189:f392fc9709a3 700 {
AnnaBridge 189:f392fc9709a3 701 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PINC,
AnnaBridge 189:f392fc9709a3 702 PeriphOrM2MSrcIncMode);
AnnaBridge 189:f392fc9709a3 703 }
AnnaBridge 189:f392fc9709a3 704
AnnaBridge 189:f392fc9709a3 705 /**
AnnaBridge 189:f392fc9709a3 706 * @brief Get Peripheral increment mode.
AnnaBridge 189:f392fc9709a3 707 * @rmtoll CCR PINC LL_DMA_GetPeriphIncMode
AnnaBridge 189:f392fc9709a3 708 * @param DMAx DMAx Instance
AnnaBridge 189:f392fc9709a3 709 * @param Channel This parameter can be one of the following values:
AnnaBridge 189:f392fc9709a3 710 * @arg @ref LL_DMA_CHANNEL_1
AnnaBridge 189:f392fc9709a3 711 * @arg @ref LL_DMA_CHANNEL_2
AnnaBridge 189:f392fc9709a3 712 * @arg @ref LL_DMA_CHANNEL_3
AnnaBridge 189:f392fc9709a3 713 * @arg @ref LL_DMA_CHANNEL_4
AnnaBridge 189:f392fc9709a3 714 * @arg @ref LL_DMA_CHANNEL_5
AnnaBridge 189:f392fc9709a3 715 * @arg @ref LL_DMA_CHANNEL_6
AnnaBridge 189:f392fc9709a3 716 * @arg @ref LL_DMA_CHANNEL_7
AnnaBridge 189:f392fc9709a3 717 * @retval Returned value can be one of the following values:
AnnaBridge 189:f392fc9709a3 718 * @arg @ref LL_DMA_PERIPH_INCREMENT
AnnaBridge 189:f392fc9709a3 719 * @arg @ref LL_DMA_PERIPH_NOINCREMENT
AnnaBridge 189:f392fc9709a3 720 */
AnnaBridge 189:f392fc9709a3 721 __STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge 189:f392fc9709a3 722 {
AnnaBridge 189:f392fc9709a3 723 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
AnnaBridge 189:f392fc9709a3 724 DMA_CCR_PINC));
AnnaBridge 189:f392fc9709a3 725 }
AnnaBridge 189:f392fc9709a3 726
AnnaBridge 189:f392fc9709a3 727 /**
AnnaBridge 189:f392fc9709a3 728 * @brief Set Memory increment mode.
AnnaBridge 189:f392fc9709a3 729 * @rmtoll CCR MINC LL_DMA_SetMemoryIncMode
AnnaBridge 189:f392fc9709a3 730 * @param DMAx DMAx Instance
AnnaBridge 189:f392fc9709a3 731 * @param Channel This parameter can be one of the following values:
AnnaBridge 189:f392fc9709a3 732 * @arg @ref LL_DMA_CHANNEL_1
AnnaBridge 189:f392fc9709a3 733 * @arg @ref LL_DMA_CHANNEL_2
AnnaBridge 189:f392fc9709a3 734 * @arg @ref LL_DMA_CHANNEL_3
AnnaBridge 189:f392fc9709a3 735 * @arg @ref LL_DMA_CHANNEL_4
AnnaBridge 189:f392fc9709a3 736 * @arg @ref LL_DMA_CHANNEL_5
AnnaBridge 189:f392fc9709a3 737 * @arg @ref LL_DMA_CHANNEL_6
AnnaBridge 189:f392fc9709a3 738 * @arg @ref LL_DMA_CHANNEL_7
AnnaBridge 189:f392fc9709a3 739 * @param MemoryOrM2MDstIncMode This parameter can be one of the following values:
AnnaBridge 189:f392fc9709a3 740 * @arg @ref LL_DMA_MEMORY_INCREMENT
AnnaBridge 189:f392fc9709a3 741 * @arg @ref LL_DMA_MEMORY_NOINCREMENT
AnnaBridge 189:f392fc9709a3 742 * @retval None
AnnaBridge 189:f392fc9709a3 743 */
AnnaBridge 189:f392fc9709a3 744 __STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstIncMode)
AnnaBridge 189:f392fc9709a3 745 {
AnnaBridge 189:f392fc9709a3 746 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_MINC,
AnnaBridge 189:f392fc9709a3 747 MemoryOrM2MDstIncMode);
AnnaBridge 189:f392fc9709a3 748 }
AnnaBridge 189:f392fc9709a3 749
AnnaBridge 189:f392fc9709a3 750 /**
AnnaBridge 189:f392fc9709a3 751 * @brief Get Memory increment mode.
AnnaBridge 189:f392fc9709a3 752 * @rmtoll CCR MINC LL_DMA_GetMemoryIncMode
AnnaBridge 189:f392fc9709a3 753 * @param DMAx DMAx Instance
AnnaBridge 189:f392fc9709a3 754 * @param Channel This parameter can be one of the following values:
AnnaBridge 189:f392fc9709a3 755 * @arg @ref LL_DMA_CHANNEL_1
AnnaBridge 189:f392fc9709a3 756 * @arg @ref LL_DMA_CHANNEL_2
AnnaBridge 189:f392fc9709a3 757 * @arg @ref LL_DMA_CHANNEL_3
AnnaBridge 189:f392fc9709a3 758 * @arg @ref LL_DMA_CHANNEL_4
AnnaBridge 189:f392fc9709a3 759 * @arg @ref LL_DMA_CHANNEL_5
AnnaBridge 189:f392fc9709a3 760 * @arg @ref LL_DMA_CHANNEL_6
AnnaBridge 189:f392fc9709a3 761 * @arg @ref LL_DMA_CHANNEL_7
AnnaBridge 189:f392fc9709a3 762 * @retval Returned value can be one of the following values:
AnnaBridge 189:f392fc9709a3 763 * @arg @ref LL_DMA_MEMORY_INCREMENT
AnnaBridge 189:f392fc9709a3 764 * @arg @ref LL_DMA_MEMORY_NOINCREMENT
AnnaBridge 189:f392fc9709a3 765 */
AnnaBridge 189:f392fc9709a3 766 __STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge 189:f392fc9709a3 767 {
AnnaBridge 189:f392fc9709a3 768 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
AnnaBridge 189:f392fc9709a3 769 DMA_CCR_MINC));
AnnaBridge 189:f392fc9709a3 770 }
AnnaBridge 189:f392fc9709a3 771
AnnaBridge 189:f392fc9709a3 772 /**
AnnaBridge 189:f392fc9709a3 773 * @brief Set Peripheral size.
AnnaBridge 189:f392fc9709a3 774 * @rmtoll CCR PSIZE LL_DMA_SetPeriphSize
AnnaBridge 189:f392fc9709a3 775 * @param DMAx DMAx Instance
AnnaBridge 189:f392fc9709a3 776 * @param Channel This parameter can be one of the following values:
AnnaBridge 189:f392fc9709a3 777 * @arg @ref LL_DMA_CHANNEL_1
AnnaBridge 189:f392fc9709a3 778 * @arg @ref LL_DMA_CHANNEL_2
AnnaBridge 189:f392fc9709a3 779 * @arg @ref LL_DMA_CHANNEL_3
AnnaBridge 189:f392fc9709a3 780 * @arg @ref LL_DMA_CHANNEL_4
AnnaBridge 189:f392fc9709a3 781 * @arg @ref LL_DMA_CHANNEL_5
AnnaBridge 189:f392fc9709a3 782 * @arg @ref LL_DMA_CHANNEL_6
AnnaBridge 189:f392fc9709a3 783 * @arg @ref LL_DMA_CHANNEL_7
AnnaBridge 189:f392fc9709a3 784 * @param PeriphOrM2MSrcDataSize This parameter can be one of the following values:
AnnaBridge 189:f392fc9709a3 785 * @arg @ref LL_DMA_PDATAALIGN_BYTE
AnnaBridge 189:f392fc9709a3 786 * @arg @ref LL_DMA_PDATAALIGN_HALFWORD
AnnaBridge 189:f392fc9709a3 787 * @arg @ref LL_DMA_PDATAALIGN_WORD
AnnaBridge 189:f392fc9709a3 788 * @retval None
AnnaBridge 189:f392fc9709a3 789 */
AnnaBridge 189:f392fc9709a3 790 __STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcDataSize)
AnnaBridge 189:f392fc9709a3 791 {
AnnaBridge 189:f392fc9709a3 792 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PSIZE,
AnnaBridge 189:f392fc9709a3 793 PeriphOrM2MSrcDataSize);
AnnaBridge 189:f392fc9709a3 794 }
AnnaBridge 189:f392fc9709a3 795
AnnaBridge 189:f392fc9709a3 796 /**
AnnaBridge 189:f392fc9709a3 797 * @brief Get Peripheral size.
AnnaBridge 189:f392fc9709a3 798 * @rmtoll CCR PSIZE LL_DMA_GetPeriphSize
AnnaBridge 189:f392fc9709a3 799 * @param DMAx DMAx Instance
AnnaBridge 189:f392fc9709a3 800 * @param Channel This parameter can be one of the following values:
AnnaBridge 189:f392fc9709a3 801 * @arg @ref LL_DMA_CHANNEL_1
AnnaBridge 189:f392fc9709a3 802 * @arg @ref LL_DMA_CHANNEL_2
AnnaBridge 189:f392fc9709a3 803 * @arg @ref LL_DMA_CHANNEL_3
AnnaBridge 189:f392fc9709a3 804 * @arg @ref LL_DMA_CHANNEL_4
AnnaBridge 189:f392fc9709a3 805 * @arg @ref LL_DMA_CHANNEL_5
AnnaBridge 189:f392fc9709a3 806 * @arg @ref LL_DMA_CHANNEL_6
AnnaBridge 189:f392fc9709a3 807 * @arg @ref LL_DMA_CHANNEL_7
AnnaBridge 189:f392fc9709a3 808 * @retval Returned value can be one of the following values:
AnnaBridge 189:f392fc9709a3 809 * @arg @ref LL_DMA_PDATAALIGN_BYTE
AnnaBridge 189:f392fc9709a3 810 * @arg @ref LL_DMA_PDATAALIGN_HALFWORD
AnnaBridge 189:f392fc9709a3 811 * @arg @ref LL_DMA_PDATAALIGN_WORD
AnnaBridge 189:f392fc9709a3 812 */
AnnaBridge 189:f392fc9709a3 813 __STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge 189:f392fc9709a3 814 {
AnnaBridge 189:f392fc9709a3 815 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
AnnaBridge 189:f392fc9709a3 816 DMA_CCR_PSIZE));
AnnaBridge 189:f392fc9709a3 817 }
AnnaBridge 189:f392fc9709a3 818
AnnaBridge 189:f392fc9709a3 819 /**
AnnaBridge 189:f392fc9709a3 820 * @brief Set Memory size.
AnnaBridge 189:f392fc9709a3 821 * @rmtoll CCR MSIZE LL_DMA_SetMemorySize
AnnaBridge 189:f392fc9709a3 822 * @param DMAx DMAx Instance
AnnaBridge 189:f392fc9709a3 823 * @param Channel This parameter can be one of the following values:
AnnaBridge 189:f392fc9709a3 824 * @arg @ref LL_DMA_CHANNEL_1
AnnaBridge 189:f392fc9709a3 825 * @arg @ref LL_DMA_CHANNEL_2
AnnaBridge 189:f392fc9709a3 826 * @arg @ref LL_DMA_CHANNEL_3
AnnaBridge 189:f392fc9709a3 827 * @arg @ref LL_DMA_CHANNEL_4
AnnaBridge 189:f392fc9709a3 828 * @arg @ref LL_DMA_CHANNEL_5
AnnaBridge 189:f392fc9709a3 829 * @arg @ref LL_DMA_CHANNEL_6
AnnaBridge 189:f392fc9709a3 830 * @arg @ref LL_DMA_CHANNEL_7
AnnaBridge 189:f392fc9709a3 831 * @param MemoryOrM2MDstDataSize This parameter can be one of the following values:
AnnaBridge 189:f392fc9709a3 832 * @arg @ref LL_DMA_MDATAALIGN_BYTE
AnnaBridge 189:f392fc9709a3 833 * @arg @ref LL_DMA_MDATAALIGN_HALFWORD
AnnaBridge 189:f392fc9709a3 834 * @arg @ref LL_DMA_MDATAALIGN_WORD
AnnaBridge 189:f392fc9709a3 835 * @retval None
AnnaBridge 189:f392fc9709a3 836 */
AnnaBridge 189:f392fc9709a3 837 __STATIC_INLINE void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstDataSize)
AnnaBridge 189:f392fc9709a3 838 {
AnnaBridge 189:f392fc9709a3 839 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_MSIZE,
AnnaBridge 189:f392fc9709a3 840 MemoryOrM2MDstDataSize);
AnnaBridge 189:f392fc9709a3 841 }
AnnaBridge 189:f392fc9709a3 842
AnnaBridge 189:f392fc9709a3 843 /**
AnnaBridge 189:f392fc9709a3 844 * @brief Get Memory size.
AnnaBridge 189:f392fc9709a3 845 * @rmtoll CCR MSIZE LL_DMA_GetMemorySize
AnnaBridge 189:f392fc9709a3 846 * @param DMAx DMAx Instance
AnnaBridge 189:f392fc9709a3 847 * @param Channel This parameter can be one of the following values:
AnnaBridge 189:f392fc9709a3 848 * @arg @ref LL_DMA_CHANNEL_1
AnnaBridge 189:f392fc9709a3 849 * @arg @ref LL_DMA_CHANNEL_2
AnnaBridge 189:f392fc9709a3 850 * @arg @ref LL_DMA_CHANNEL_3
AnnaBridge 189:f392fc9709a3 851 * @arg @ref LL_DMA_CHANNEL_4
AnnaBridge 189:f392fc9709a3 852 * @arg @ref LL_DMA_CHANNEL_5
AnnaBridge 189:f392fc9709a3 853 * @arg @ref LL_DMA_CHANNEL_6
AnnaBridge 189:f392fc9709a3 854 * @arg @ref LL_DMA_CHANNEL_7
AnnaBridge 189:f392fc9709a3 855 * @retval Returned value can be one of the following values:
AnnaBridge 189:f392fc9709a3 856 * @arg @ref LL_DMA_MDATAALIGN_BYTE
AnnaBridge 189:f392fc9709a3 857 * @arg @ref LL_DMA_MDATAALIGN_HALFWORD
AnnaBridge 189:f392fc9709a3 858 * @arg @ref LL_DMA_MDATAALIGN_WORD
AnnaBridge 189:f392fc9709a3 859 */
AnnaBridge 189:f392fc9709a3 860 __STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge 189:f392fc9709a3 861 {
AnnaBridge 189:f392fc9709a3 862 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
AnnaBridge 189:f392fc9709a3 863 DMA_CCR_MSIZE));
AnnaBridge 189:f392fc9709a3 864 }
AnnaBridge 189:f392fc9709a3 865
AnnaBridge 189:f392fc9709a3 866 /**
AnnaBridge 189:f392fc9709a3 867 * @brief Set Channel priority level.
AnnaBridge 189:f392fc9709a3 868 * @rmtoll CCR PL LL_DMA_SetChannelPriorityLevel
AnnaBridge 189:f392fc9709a3 869 * @param DMAx DMAx Instance
AnnaBridge 189:f392fc9709a3 870 * @param Channel This parameter can be one of the following values:
AnnaBridge 189:f392fc9709a3 871 * @arg @ref LL_DMA_CHANNEL_1
AnnaBridge 189:f392fc9709a3 872 * @arg @ref LL_DMA_CHANNEL_2
AnnaBridge 189:f392fc9709a3 873 * @arg @ref LL_DMA_CHANNEL_3
AnnaBridge 189:f392fc9709a3 874 * @arg @ref LL_DMA_CHANNEL_4
AnnaBridge 189:f392fc9709a3 875 * @arg @ref LL_DMA_CHANNEL_5
AnnaBridge 189:f392fc9709a3 876 * @arg @ref LL_DMA_CHANNEL_6
AnnaBridge 189:f392fc9709a3 877 * @arg @ref LL_DMA_CHANNEL_7
AnnaBridge 189:f392fc9709a3 878 * @param Priority This parameter can be one of the following values:
AnnaBridge 189:f392fc9709a3 879 * @arg @ref LL_DMA_PRIORITY_LOW
AnnaBridge 189:f392fc9709a3 880 * @arg @ref LL_DMA_PRIORITY_MEDIUM
AnnaBridge 189:f392fc9709a3 881 * @arg @ref LL_DMA_PRIORITY_HIGH
AnnaBridge 189:f392fc9709a3 882 * @arg @ref LL_DMA_PRIORITY_VERYHIGH
AnnaBridge 189:f392fc9709a3 883 * @retval None
AnnaBridge 189:f392fc9709a3 884 */
AnnaBridge 189:f392fc9709a3 885 __STATIC_INLINE void LL_DMA_SetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Priority)
AnnaBridge 189:f392fc9709a3 886 {
AnnaBridge 189:f392fc9709a3 887 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PL,
AnnaBridge 189:f392fc9709a3 888 Priority);
AnnaBridge 189:f392fc9709a3 889 }
AnnaBridge 189:f392fc9709a3 890
AnnaBridge 189:f392fc9709a3 891 /**
AnnaBridge 189:f392fc9709a3 892 * @brief Get Channel priority level.
AnnaBridge 189:f392fc9709a3 893 * @rmtoll CCR PL LL_DMA_GetChannelPriorityLevel
AnnaBridge 189:f392fc9709a3 894 * @param DMAx DMAx Instance
AnnaBridge 189:f392fc9709a3 895 * @param Channel This parameter can be one of the following values:
AnnaBridge 189:f392fc9709a3 896 * @arg @ref LL_DMA_CHANNEL_1
AnnaBridge 189:f392fc9709a3 897 * @arg @ref LL_DMA_CHANNEL_2
AnnaBridge 189:f392fc9709a3 898 * @arg @ref LL_DMA_CHANNEL_3
AnnaBridge 189:f392fc9709a3 899 * @arg @ref LL_DMA_CHANNEL_4
AnnaBridge 189:f392fc9709a3 900 * @arg @ref LL_DMA_CHANNEL_5
AnnaBridge 189:f392fc9709a3 901 * @arg @ref LL_DMA_CHANNEL_6
AnnaBridge 189:f392fc9709a3 902 * @arg @ref LL_DMA_CHANNEL_7
AnnaBridge 189:f392fc9709a3 903 * @retval Returned value can be one of the following values:
AnnaBridge 189:f392fc9709a3 904 * @arg @ref LL_DMA_PRIORITY_LOW
AnnaBridge 189:f392fc9709a3 905 * @arg @ref LL_DMA_PRIORITY_MEDIUM
AnnaBridge 189:f392fc9709a3 906 * @arg @ref LL_DMA_PRIORITY_HIGH
AnnaBridge 189:f392fc9709a3 907 * @arg @ref LL_DMA_PRIORITY_VERYHIGH
AnnaBridge 189:f392fc9709a3 908 */
AnnaBridge 189:f392fc9709a3 909 __STATIC_INLINE uint32_t LL_DMA_GetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge 189:f392fc9709a3 910 {
AnnaBridge 189:f392fc9709a3 911 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
AnnaBridge 189:f392fc9709a3 912 DMA_CCR_PL));
AnnaBridge 189:f392fc9709a3 913 }
AnnaBridge 189:f392fc9709a3 914
AnnaBridge 189:f392fc9709a3 915 /**
AnnaBridge 189:f392fc9709a3 916 * @brief Set Number of data to transfer.
AnnaBridge 189:f392fc9709a3 917 * @note This action has no effect if
AnnaBridge 189:f392fc9709a3 918 * channel is enabled.
AnnaBridge 189:f392fc9709a3 919 * @rmtoll CNDTR NDT LL_DMA_SetDataLength
AnnaBridge 189:f392fc9709a3 920 * @param DMAx DMAx Instance
AnnaBridge 189:f392fc9709a3 921 * @param Channel This parameter can be one of the following values:
AnnaBridge 189:f392fc9709a3 922 * @arg @ref LL_DMA_CHANNEL_1
AnnaBridge 189:f392fc9709a3 923 * @arg @ref LL_DMA_CHANNEL_2
AnnaBridge 189:f392fc9709a3 924 * @arg @ref LL_DMA_CHANNEL_3
AnnaBridge 189:f392fc9709a3 925 * @arg @ref LL_DMA_CHANNEL_4
AnnaBridge 189:f392fc9709a3 926 * @arg @ref LL_DMA_CHANNEL_5
AnnaBridge 189:f392fc9709a3 927 * @arg @ref LL_DMA_CHANNEL_6
AnnaBridge 189:f392fc9709a3 928 * @arg @ref LL_DMA_CHANNEL_7
AnnaBridge 189:f392fc9709a3 929 * @param NbData Between Min_Data = 0 and Max_Data = 0x0000FFFF
AnnaBridge 189:f392fc9709a3 930 * @retval None
AnnaBridge 189:f392fc9709a3 931 */
AnnaBridge 189:f392fc9709a3 932 __STATIC_INLINE void LL_DMA_SetDataLength(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t NbData)
AnnaBridge 189:f392fc9709a3 933 {
AnnaBridge 189:f392fc9709a3 934 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CNDTR,
AnnaBridge 189:f392fc9709a3 935 DMA_CNDTR_NDT, NbData);
AnnaBridge 189:f392fc9709a3 936 }
AnnaBridge 189:f392fc9709a3 937
AnnaBridge 189:f392fc9709a3 938 /**
AnnaBridge 189:f392fc9709a3 939 * @brief Get Number of data to transfer.
AnnaBridge 189:f392fc9709a3 940 * @note Once the channel is enabled, the return value indicate the
AnnaBridge 189:f392fc9709a3 941 * remaining bytes to be transmitted.
AnnaBridge 189:f392fc9709a3 942 * @rmtoll CNDTR NDT LL_DMA_GetDataLength
AnnaBridge 189:f392fc9709a3 943 * @param DMAx DMAx Instance
AnnaBridge 189:f392fc9709a3 944 * @param Channel This parameter can be one of the following values:
AnnaBridge 189:f392fc9709a3 945 * @arg @ref LL_DMA_CHANNEL_1
AnnaBridge 189:f392fc9709a3 946 * @arg @ref LL_DMA_CHANNEL_2
AnnaBridge 189:f392fc9709a3 947 * @arg @ref LL_DMA_CHANNEL_3
AnnaBridge 189:f392fc9709a3 948 * @arg @ref LL_DMA_CHANNEL_4
AnnaBridge 189:f392fc9709a3 949 * @arg @ref LL_DMA_CHANNEL_5
AnnaBridge 189:f392fc9709a3 950 * @arg @ref LL_DMA_CHANNEL_6
AnnaBridge 189:f392fc9709a3 951 * @arg @ref LL_DMA_CHANNEL_7
AnnaBridge 189:f392fc9709a3 952 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
AnnaBridge 189:f392fc9709a3 953 */
AnnaBridge 189:f392fc9709a3 954 __STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge 189:f392fc9709a3 955 {
AnnaBridge 189:f392fc9709a3 956 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CNDTR,
AnnaBridge 189:f392fc9709a3 957 DMA_CNDTR_NDT));
AnnaBridge 189:f392fc9709a3 958 }
AnnaBridge 189:f392fc9709a3 959
AnnaBridge 189:f392fc9709a3 960 /**
AnnaBridge 189:f392fc9709a3 961 * @brief Configure the Source and Destination addresses.
AnnaBridge 189:f392fc9709a3 962 * @note This API must not be called when the DMA channel is enabled.
AnnaBridge 189:f392fc9709a3 963 * @note Each IP using DMA provides an API to get directly the register adress (LL_PPP_DMA_GetRegAddr).
AnnaBridge 189:f392fc9709a3 964 * @rmtoll CPAR PA LL_DMA_ConfigAddresses\n
AnnaBridge 189:f392fc9709a3 965 * CMAR MA LL_DMA_ConfigAddresses
AnnaBridge 189:f392fc9709a3 966 * @param DMAx DMAx Instance
AnnaBridge 189:f392fc9709a3 967 * @param Channel This parameter can be one of the following values:
AnnaBridge 189:f392fc9709a3 968 * @arg @ref LL_DMA_CHANNEL_1
AnnaBridge 189:f392fc9709a3 969 * @arg @ref LL_DMA_CHANNEL_2
AnnaBridge 189:f392fc9709a3 970 * @arg @ref LL_DMA_CHANNEL_3
AnnaBridge 189:f392fc9709a3 971 * @arg @ref LL_DMA_CHANNEL_4
AnnaBridge 189:f392fc9709a3 972 * @arg @ref LL_DMA_CHANNEL_5
AnnaBridge 189:f392fc9709a3 973 * @arg @ref LL_DMA_CHANNEL_6
AnnaBridge 189:f392fc9709a3 974 * @arg @ref LL_DMA_CHANNEL_7
AnnaBridge 189:f392fc9709a3 975 * @param SrcAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
AnnaBridge 189:f392fc9709a3 976 * @param DstAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
AnnaBridge 189:f392fc9709a3 977 * @param Direction This parameter can be one of the following values:
AnnaBridge 189:f392fc9709a3 978 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
AnnaBridge 189:f392fc9709a3 979 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
AnnaBridge 189:f392fc9709a3 980 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
AnnaBridge 189:f392fc9709a3 981 * @retval None
AnnaBridge 189:f392fc9709a3 982 */
AnnaBridge 189:f392fc9709a3 983 __STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddress,
AnnaBridge 189:f392fc9709a3 984 uint32_t DstAddress, uint32_t Direction)
AnnaBridge 189:f392fc9709a3 985 {
AnnaBridge 189:f392fc9709a3 986 /* Direction Memory to Periph */
AnnaBridge 189:f392fc9709a3 987 if (Direction == LL_DMA_DIRECTION_MEMORY_TO_PERIPH)
AnnaBridge 189:f392fc9709a3 988 {
AnnaBridge 189:f392fc9709a3 989 WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, SrcAddress);
AnnaBridge 189:f392fc9709a3 990 WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, DstAddress);
AnnaBridge 189:f392fc9709a3 991 }
AnnaBridge 189:f392fc9709a3 992 /* Direction Periph to Memory and Memory to Memory */
AnnaBridge 189:f392fc9709a3 993 else
AnnaBridge 189:f392fc9709a3 994 {
AnnaBridge 189:f392fc9709a3 995 WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, SrcAddress);
AnnaBridge 189:f392fc9709a3 996 WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, DstAddress);
AnnaBridge 189:f392fc9709a3 997 }
AnnaBridge 189:f392fc9709a3 998 }
AnnaBridge 189:f392fc9709a3 999
AnnaBridge 189:f392fc9709a3 1000 /**
AnnaBridge 189:f392fc9709a3 1001 * @brief Set the Memory address.
AnnaBridge 189:f392fc9709a3 1002 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
AnnaBridge 189:f392fc9709a3 1003 * @note This API must not be called when the DMA channel is enabled.
AnnaBridge 189:f392fc9709a3 1004 * @rmtoll CMAR MA LL_DMA_SetMemoryAddress
AnnaBridge 189:f392fc9709a3 1005 * @param DMAx DMAx Instance
AnnaBridge 189:f392fc9709a3 1006 * @param Channel This parameter can be one of the following values:
AnnaBridge 189:f392fc9709a3 1007 * @arg @ref LL_DMA_CHANNEL_1
AnnaBridge 189:f392fc9709a3 1008 * @arg @ref LL_DMA_CHANNEL_2
AnnaBridge 189:f392fc9709a3 1009 * @arg @ref LL_DMA_CHANNEL_3
AnnaBridge 189:f392fc9709a3 1010 * @arg @ref LL_DMA_CHANNEL_4
AnnaBridge 189:f392fc9709a3 1011 * @arg @ref LL_DMA_CHANNEL_5
AnnaBridge 189:f392fc9709a3 1012 * @arg @ref LL_DMA_CHANNEL_6
AnnaBridge 189:f392fc9709a3 1013 * @arg @ref LL_DMA_CHANNEL_7
AnnaBridge 189:f392fc9709a3 1014 * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
AnnaBridge 189:f392fc9709a3 1015 * @retval None
AnnaBridge 189:f392fc9709a3 1016 */
AnnaBridge 189:f392fc9709a3 1017 __STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
AnnaBridge 189:f392fc9709a3 1018 {
AnnaBridge 189:f392fc9709a3 1019 WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, MemoryAddress);
AnnaBridge 189:f392fc9709a3 1020 }
AnnaBridge 189:f392fc9709a3 1021
AnnaBridge 189:f392fc9709a3 1022 /**
AnnaBridge 189:f392fc9709a3 1023 * @brief Set the Peripheral address.
AnnaBridge 189:f392fc9709a3 1024 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
AnnaBridge 189:f392fc9709a3 1025 * @note This API must not be called when the DMA channel is enabled.
AnnaBridge 189:f392fc9709a3 1026 * @rmtoll CPAR PA LL_DMA_SetPeriphAddress
AnnaBridge 189:f392fc9709a3 1027 * @param DMAx DMAx Instance
AnnaBridge 189:f392fc9709a3 1028 * @param Channel This parameter can be one of the following values:
AnnaBridge 189:f392fc9709a3 1029 * @arg @ref LL_DMA_CHANNEL_1
AnnaBridge 189:f392fc9709a3 1030 * @arg @ref LL_DMA_CHANNEL_2
AnnaBridge 189:f392fc9709a3 1031 * @arg @ref LL_DMA_CHANNEL_3
AnnaBridge 189:f392fc9709a3 1032 * @arg @ref LL_DMA_CHANNEL_4
AnnaBridge 189:f392fc9709a3 1033 * @arg @ref LL_DMA_CHANNEL_5
AnnaBridge 189:f392fc9709a3 1034 * @arg @ref LL_DMA_CHANNEL_6
AnnaBridge 189:f392fc9709a3 1035 * @arg @ref LL_DMA_CHANNEL_7
AnnaBridge 189:f392fc9709a3 1036 * @param PeriphAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
AnnaBridge 189:f392fc9709a3 1037 * @retval None
AnnaBridge 189:f392fc9709a3 1038 */
AnnaBridge 189:f392fc9709a3 1039 __STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphAddress)
AnnaBridge 189:f392fc9709a3 1040 {
AnnaBridge 189:f392fc9709a3 1041 WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, PeriphAddress);
AnnaBridge 189:f392fc9709a3 1042 }
AnnaBridge 189:f392fc9709a3 1043
AnnaBridge 189:f392fc9709a3 1044 /**
AnnaBridge 189:f392fc9709a3 1045 * @brief Get Memory address.
AnnaBridge 189:f392fc9709a3 1046 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
AnnaBridge 189:f392fc9709a3 1047 * @rmtoll CMAR MA LL_DMA_GetMemoryAddress
AnnaBridge 189:f392fc9709a3 1048 * @param DMAx DMAx Instance
AnnaBridge 189:f392fc9709a3 1049 * @param Channel This parameter can be one of the following values:
AnnaBridge 189:f392fc9709a3 1050 * @arg @ref LL_DMA_CHANNEL_1
AnnaBridge 189:f392fc9709a3 1051 * @arg @ref LL_DMA_CHANNEL_2
AnnaBridge 189:f392fc9709a3 1052 * @arg @ref LL_DMA_CHANNEL_3
AnnaBridge 189:f392fc9709a3 1053 * @arg @ref LL_DMA_CHANNEL_4
AnnaBridge 189:f392fc9709a3 1054 * @arg @ref LL_DMA_CHANNEL_5
AnnaBridge 189:f392fc9709a3 1055 * @arg @ref LL_DMA_CHANNEL_6
AnnaBridge 189:f392fc9709a3 1056 * @arg @ref LL_DMA_CHANNEL_7
AnnaBridge 189:f392fc9709a3 1057 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
AnnaBridge 189:f392fc9709a3 1058 */
AnnaBridge 189:f392fc9709a3 1059 __STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge 189:f392fc9709a3 1060 {
AnnaBridge 189:f392fc9709a3 1061 return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR));
AnnaBridge 189:f392fc9709a3 1062 }
AnnaBridge 189:f392fc9709a3 1063
AnnaBridge 189:f392fc9709a3 1064 /**
AnnaBridge 189:f392fc9709a3 1065 * @brief Get Peripheral address.
AnnaBridge 189:f392fc9709a3 1066 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
AnnaBridge 189:f392fc9709a3 1067 * @rmtoll CPAR PA LL_DMA_GetPeriphAddress
AnnaBridge 189:f392fc9709a3 1068 * @param DMAx DMAx Instance
AnnaBridge 189:f392fc9709a3 1069 * @param Channel This parameter can be one of the following values:
AnnaBridge 189:f392fc9709a3 1070 * @arg @ref LL_DMA_CHANNEL_1
AnnaBridge 189:f392fc9709a3 1071 * @arg @ref LL_DMA_CHANNEL_2
AnnaBridge 189:f392fc9709a3 1072 * @arg @ref LL_DMA_CHANNEL_3
AnnaBridge 189:f392fc9709a3 1073 * @arg @ref LL_DMA_CHANNEL_4
AnnaBridge 189:f392fc9709a3 1074 * @arg @ref LL_DMA_CHANNEL_5
AnnaBridge 189:f392fc9709a3 1075 * @arg @ref LL_DMA_CHANNEL_6
AnnaBridge 189:f392fc9709a3 1076 * @arg @ref LL_DMA_CHANNEL_7
AnnaBridge 189:f392fc9709a3 1077 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
AnnaBridge 189:f392fc9709a3 1078 */
AnnaBridge 189:f392fc9709a3 1079 __STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge 189:f392fc9709a3 1080 {
AnnaBridge 189:f392fc9709a3 1081 return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR));
AnnaBridge 189:f392fc9709a3 1082 }
AnnaBridge 189:f392fc9709a3 1083
AnnaBridge 189:f392fc9709a3 1084 /**
AnnaBridge 189:f392fc9709a3 1085 * @brief Set the Memory to Memory Source address.
AnnaBridge 189:f392fc9709a3 1086 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
AnnaBridge 189:f392fc9709a3 1087 * @note This API must not be called when the DMA channel is enabled.
AnnaBridge 189:f392fc9709a3 1088 * @rmtoll CPAR PA LL_DMA_SetM2MSrcAddress
AnnaBridge 189:f392fc9709a3 1089 * @param DMAx DMAx Instance
AnnaBridge 189:f392fc9709a3 1090 * @param Channel This parameter can be one of the following values:
AnnaBridge 189:f392fc9709a3 1091 * @arg @ref LL_DMA_CHANNEL_1
AnnaBridge 189:f392fc9709a3 1092 * @arg @ref LL_DMA_CHANNEL_2
AnnaBridge 189:f392fc9709a3 1093 * @arg @ref LL_DMA_CHANNEL_3
AnnaBridge 189:f392fc9709a3 1094 * @arg @ref LL_DMA_CHANNEL_4
AnnaBridge 189:f392fc9709a3 1095 * @arg @ref LL_DMA_CHANNEL_5
AnnaBridge 189:f392fc9709a3 1096 * @arg @ref LL_DMA_CHANNEL_6
AnnaBridge 189:f392fc9709a3 1097 * @arg @ref LL_DMA_CHANNEL_7
AnnaBridge 189:f392fc9709a3 1098 * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
AnnaBridge 189:f392fc9709a3 1099 * @retval None
AnnaBridge 189:f392fc9709a3 1100 */
AnnaBridge 189:f392fc9709a3 1101 __STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
AnnaBridge 189:f392fc9709a3 1102 {
AnnaBridge 189:f392fc9709a3 1103 WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, MemoryAddress);
AnnaBridge 189:f392fc9709a3 1104 }
AnnaBridge 189:f392fc9709a3 1105
AnnaBridge 189:f392fc9709a3 1106 /**
AnnaBridge 189:f392fc9709a3 1107 * @brief Set the Memory to Memory Destination address.
AnnaBridge 189:f392fc9709a3 1108 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
AnnaBridge 189:f392fc9709a3 1109 * @note This API must not be called when the DMA channel is enabled.
AnnaBridge 189:f392fc9709a3 1110 * @rmtoll CMAR MA LL_DMA_SetM2MDstAddress
AnnaBridge 189:f392fc9709a3 1111 * @param DMAx DMAx Instance
AnnaBridge 189:f392fc9709a3 1112 * @param Channel This parameter can be one of the following values:
AnnaBridge 189:f392fc9709a3 1113 * @arg @ref LL_DMA_CHANNEL_1
AnnaBridge 189:f392fc9709a3 1114 * @arg @ref LL_DMA_CHANNEL_2
AnnaBridge 189:f392fc9709a3 1115 * @arg @ref LL_DMA_CHANNEL_3
AnnaBridge 189:f392fc9709a3 1116 * @arg @ref LL_DMA_CHANNEL_4
AnnaBridge 189:f392fc9709a3 1117 * @arg @ref LL_DMA_CHANNEL_5
AnnaBridge 189:f392fc9709a3 1118 * @arg @ref LL_DMA_CHANNEL_6
AnnaBridge 189:f392fc9709a3 1119 * @arg @ref LL_DMA_CHANNEL_7
AnnaBridge 189:f392fc9709a3 1120 * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
AnnaBridge 189:f392fc9709a3 1121 * @retval None
AnnaBridge 189:f392fc9709a3 1122 */
AnnaBridge 189:f392fc9709a3 1123 __STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
AnnaBridge 189:f392fc9709a3 1124 {
AnnaBridge 189:f392fc9709a3 1125 WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, MemoryAddress);
AnnaBridge 189:f392fc9709a3 1126 }
AnnaBridge 189:f392fc9709a3 1127
AnnaBridge 189:f392fc9709a3 1128 /**
AnnaBridge 189:f392fc9709a3 1129 * @brief Get the Memory to Memory Source address.
AnnaBridge 189:f392fc9709a3 1130 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
AnnaBridge 189:f392fc9709a3 1131 * @rmtoll CPAR PA LL_DMA_GetM2MSrcAddress
AnnaBridge 189:f392fc9709a3 1132 * @param DMAx DMAx Instance
AnnaBridge 189:f392fc9709a3 1133 * @param Channel This parameter can be one of the following values:
AnnaBridge 189:f392fc9709a3 1134 * @arg @ref LL_DMA_CHANNEL_1
AnnaBridge 189:f392fc9709a3 1135 * @arg @ref LL_DMA_CHANNEL_2
AnnaBridge 189:f392fc9709a3 1136 * @arg @ref LL_DMA_CHANNEL_3
AnnaBridge 189:f392fc9709a3 1137 * @arg @ref LL_DMA_CHANNEL_4
AnnaBridge 189:f392fc9709a3 1138 * @arg @ref LL_DMA_CHANNEL_5
AnnaBridge 189:f392fc9709a3 1139 * @arg @ref LL_DMA_CHANNEL_6
AnnaBridge 189:f392fc9709a3 1140 * @arg @ref LL_DMA_CHANNEL_7
AnnaBridge 189:f392fc9709a3 1141 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
AnnaBridge 189:f392fc9709a3 1142 */
AnnaBridge 189:f392fc9709a3 1143 __STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge 189:f392fc9709a3 1144 {
AnnaBridge 189:f392fc9709a3 1145 return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR));
AnnaBridge 189:f392fc9709a3 1146 }
AnnaBridge 189:f392fc9709a3 1147
AnnaBridge 189:f392fc9709a3 1148 /**
AnnaBridge 189:f392fc9709a3 1149 * @brief Get the Memory to Memory Destination address.
AnnaBridge 189:f392fc9709a3 1150 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
AnnaBridge 189:f392fc9709a3 1151 * @rmtoll CMAR MA LL_DMA_GetM2MDstAddress
AnnaBridge 189:f392fc9709a3 1152 * @param DMAx DMAx Instance
AnnaBridge 189:f392fc9709a3 1153 * @param Channel This parameter can be one of the following values:
AnnaBridge 189:f392fc9709a3 1154 * @arg @ref LL_DMA_CHANNEL_1
AnnaBridge 189:f392fc9709a3 1155 * @arg @ref LL_DMA_CHANNEL_2
AnnaBridge 189:f392fc9709a3 1156 * @arg @ref LL_DMA_CHANNEL_3
AnnaBridge 189:f392fc9709a3 1157 * @arg @ref LL_DMA_CHANNEL_4
AnnaBridge 189:f392fc9709a3 1158 * @arg @ref LL_DMA_CHANNEL_5
AnnaBridge 189:f392fc9709a3 1159 * @arg @ref LL_DMA_CHANNEL_6
AnnaBridge 189:f392fc9709a3 1160 * @arg @ref LL_DMA_CHANNEL_7
AnnaBridge 189:f392fc9709a3 1161 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
AnnaBridge 189:f392fc9709a3 1162 */
AnnaBridge 189:f392fc9709a3 1163 __STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge 189:f392fc9709a3 1164 {
AnnaBridge 189:f392fc9709a3 1165 return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR));
AnnaBridge 189:f392fc9709a3 1166 }
AnnaBridge 189:f392fc9709a3 1167
AnnaBridge 189:f392fc9709a3 1168
AnnaBridge 189:f392fc9709a3 1169 /**
AnnaBridge 189:f392fc9709a3 1170 * @}
AnnaBridge 189:f392fc9709a3 1171 */
AnnaBridge 189:f392fc9709a3 1172
AnnaBridge 189:f392fc9709a3 1173 /** @defgroup DMA_LL_EF_FLAG_Management FLAG_Management
AnnaBridge 189:f392fc9709a3 1174 * @{
AnnaBridge 189:f392fc9709a3 1175 */
AnnaBridge 189:f392fc9709a3 1176
AnnaBridge 189:f392fc9709a3 1177 /**
AnnaBridge 189:f392fc9709a3 1178 * @brief Get Channel 1 global interrupt flag.
AnnaBridge 189:f392fc9709a3 1179 * @rmtoll ISR GIF1 LL_DMA_IsActiveFlag_GI1
AnnaBridge 189:f392fc9709a3 1180 * @param DMAx DMAx Instance
AnnaBridge 189:f392fc9709a3 1181 * @retval State of bit (1 or 0).
AnnaBridge 189:f392fc9709a3 1182 */
AnnaBridge 189:f392fc9709a3 1183 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI1(DMA_TypeDef *DMAx)
AnnaBridge 189:f392fc9709a3 1184 {
AnnaBridge 189:f392fc9709a3 1185 return (READ_BIT(DMAx->ISR, DMA_ISR_GIF1) == (DMA_ISR_GIF1));
AnnaBridge 189:f392fc9709a3 1186 }
AnnaBridge 189:f392fc9709a3 1187
AnnaBridge 189:f392fc9709a3 1188 /**
AnnaBridge 189:f392fc9709a3 1189 * @brief Get Channel 2 global interrupt flag.
AnnaBridge 189:f392fc9709a3 1190 * @rmtoll ISR GIF2 LL_DMA_IsActiveFlag_GI2
AnnaBridge 189:f392fc9709a3 1191 * @param DMAx DMAx Instance
AnnaBridge 189:f392fc9709a3 1192 * @retval State of bit (1 or 0).
AnnaBridge 189:f392fc9709a3 1193 */
AnnaBridge 189:f392fc9709a3 1194 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI2(DMA_TypeDef *DMAx)
AnnaBridge 189:f392fc9709a3 1195 {
AnnaBridge 189:f392fc9709a3 1196 return (READ_BIT(DMAx->ISR, DMA_ISR_GIF2) == (DMA_ISR_GIF2));
AnnaBridge 189:f392fc9709a3 1197 }
AnnaBridge 189:f392fc9709a3 1198
AnnaBridge 189:f392fc9709a3 1199 /**
AnnaBridge 189:f392fc9709a3 1200 * @brief Get Channel 3 global interrupt flag.
AnnaBridge 189:f392fc9709a3 1201 * @rmtoll ISR GIF3 LL_DMA_IsActiveFlag_GI3
AnnaBridge 189:f392fc9709a3 1202 * @param DMAx DMAx Instance
AnnaBridge 189:f392fc9709a3 1203 * @retval State of bit (1 or 0).
AnnaBridge 189:f392fc9709a3 1204 */
AnnaBridge 189:f392fc9709a3 1205 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI3(DMA_TypeDef *DMAx)
AnnaBridge 189:f392fc9709a3 1206 {
AnnaBridge 189:f392fc9709a3 1207 return (READ_BIT(DMAx->ISR, DMA_ISR_GIF3) == (DMA_ISR_GIF3));
AnnaBridge 189:f392fc9709a3 1208 }
AnnaBridge 189:f392fc9709a3 1209
AnnaBridge 189:f392fc9709a3 1210 /**
AnnaBridge 189:f392fc9709a3 1211 * @brief Get Channel 4 global interrupt flag.
AnnaBridge 189:f392fc9709a3 1212 * @rmtoll ISR GIF4 LL_DMA_IsActiveFlag_GI4
AnnaBridge 189:f392fc9709a3 1213 * @param DMAx DMAx Instance
AnnaBridge 189:f392fc9709a3 1214 * @retval State of bit (1 or 0).
AnnaBridge 189:f392fc9709a3 1215 */
AnnaBridge 189:f392fc9709a3 1216 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI4(DMA_TypeDef *DMAx)
AnnaBridge 189:f392fc9709a3 1217 {
AnnaBridge 189:f392fc9709a3 1218 return (READ_BIT(DMAx->ISR, DMA_ISR_GIF4) == (DMA_ISR_GIF4));
AnnaBridge 189:f392fc9709a3 1219 }
AnnaBridge 189:f392fc9709a3 1220
AnnaBridge 189:f392fc9709a3 1221 /**
AnnaBridge 189:f392fc9709a3 1222 * @brief Get Channel 5 global interrupt flag.
AnnaBridge 189:f392fc9709a3 1223 * @rmtoll ISR GIF5 LL_DMA_IsActiveFlag_GI5
AnnaBridge 189:f392fc9709a3 1224 * @param DMAx DMAx Instance
AnnaBridge 189:f392fc9709a3 1225 * @retval State of bit (1 or 0).
AnnaBridge 189:f392fc9709a3 1226 */
AnnaBridge 189:f392fc9709a3 1227 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI5(DMA_TypeDef *DMAx)
AnnaBridge 189:f392fc9709a3 1228 {
AnnaBridge 189:f392fc9709a3 1229 return (READ_BIT(DMAx->ISR, DMA_ISR_GIF5) == (DMA_ISR_GIF5));
AnnaBridge 189:f392fc9709a3 1230 }
AnnaBridge 189:f392fc9709a3 1231
AnnaBridge 189:f392fc9709a3 1232 /**
AnnaBridge 189:f392fc9709a3 1233 * @brief Get Channel 6 global interrupt flag.
AnnaBridge 189:f392fc9709a3 1234 * @rmtoll ISR GIF6 LL_DMA_IsActiveFlag_GI6
AnnaBridge 189:f392fc9709a3 1235 * @param DMAx DMAx Instance
AnnaBridge 189:f392fc9709a3 1236 * @retval State of bit (1 or 0).
AnnaBridge 189:f392fc9709a3 1237 */
AnnaBridge 189:f392fc9709a3 1238 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI6(DMA_TypeDef *DMAx)
AnnaBridge 189:f392fc9709a3 1239 {
AnnaBridge 189:f392fc9709a3 1240 return (READ_BIT(DMAx->ISR, DMA_ISR_GIF6) == (DMA_ISR_GIF6));
AnnaBridge 189:f392fc9709a3 1241 }
AnnaBridge 189:f392fc9709a3 1242
AnnaBridge 189:f392fc9709a3 1243 /**
AnnaBridge 189:f392fc9709a3 1244 * @brief Get Channel 7 global interrupt flag.
AnnaBridge 189:f392fc9709a3 1245 * @rmtoll ISR GIF7 LL_DMA_IsActiveFlag_GI7
AnnaBridge 189:f392fc9709a3 1246 * @param DMAx DMAx Instance
AnnaBridge 189:f392fc9709a3 1247 * @retval State of bit (1 or 0).
AnnaBridge 189:f392fc9709a3 1248 */
AnnaBridge 189:f392fc9709a3 1249 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI7(DMA_TypeDef *DMAx)
AnnaBridge 189:f392fc9709a3 1250 {
AnnaBridge 189:f392fc9709a3 1251 return (READ_BIT(DMAx->ISR, DMA_ISR_GIF7) == (DMA_ISR_GIF7));
AnnaBridge 189:f392fc9709a3 1252 }
AnnaBridge 189:f392fc9709a3 1253
AnnaBridge 189:f392fc9709a3 1254 /**
AnnaBridge 189:f392fc9709a3 1255 * @brief Get Channel 1 transfer complete flag.
AnnaBridge 189:f392fc9709a3 1256 * @rmtoll ISR TCIF1 LL_DMA_IsActiveFlag_TC1
AnnaBridge 189:f392fc9709a3 1257 * @param DMAx DMAx Instance
AnnaBridge 189:f392fc9709a3 1258 * @retval State of bit (1 or 0).
AnnaBridge 189:f392fc9709a3 1259 */
AnnaBridge 189:f392fc9709a3 1260 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1(DMA_TypeDef *DMAx)
AnnaBridge 189:f392fc9709a3 1261 {
AnnaBridge 189:f392fc9709a3 1262 return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF1) == (DMA_ISR_TCIF1));
AnnaBridge 189:f392fc9709a3 1263 }
AnnaBridge 189:f392fc9709a3 1264
AnnaBridge 189:f392fc9709a3 1265 /**
AnnaBridge 189:f392fc9709a3 1266 * @brief Get Channel 2 transfer complete flag.
AnnaBridge 189:f392fc9709a3 1267 * @rmtoll ISR TCIF2 LL_DMA_IsActiveFlag_TC2
AnnaBridge 189:f392fc9709a3 1268 * @param DMAx DMAx Instance
AnnaBridge 189:f392fc9709a3 1269 * @retval State of bit (1 or 0).
AnnaBridge 189:f392fc9709a3 1270 */
AnnaBridge 189:f392fc9709a3 1271 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2(DMA_TypeDef *DMAx)
AnnaBridge 189:f392fc9709a3 1272 {
AnnaBridge 189:f392fc9709a3 1273 return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF2) == (DMA_ISR_TCIF2));
AnnaBridge 189:f392fc9709a3 1274 }
AnnaBridge 189:f392fc9709a3 1275
AnnaBridge 189:f392fc9709a3 1276 /**
AnnaBridge 189:f392fc9709a3 1277 * @brief Get Channel 3 transfer complete flag.
AnnaBridge 189:f392fc9709a3 1278 * @rmtoll ISR TCIF3 LL_DMA_IsActiveFlag_TC3
AnnaBridge 189:f392fc9709a3 1279 * @param DMAx DMAx Instance
AnnaBridge 189:f392fc9709a3 1280 * @retval State of bit (1 or 0).
AnnaBridge 189:f392fc9709a3 1281 */
AnnaBridge 189:f392fc9709a3 1282 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3(DMA_TypeDef *DMAx)
AnnaBridge 189:f392fc9709a3 1283 {
AnnaBridge 189:f392fc9709a3 1284 return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF3) == (DMA_ISR_TCIF3));
AnnaBridge 189:f392fc9709a3 1285 }
AnnaBridge 189:f392fc9709a3 1286
AnnaBridge 189:f392fc9709a3 1287 /**
AnnaBridge 189:f392fc9709a3 1288 * @brief Get Channel 4 transfer complete flag.
AnnaBridge 189:f392fc9709a3 1289 * @rmtoll ISR TCIF4 LL_DMA_IsActiveFlag_TC4
AnnaBridge 189:f392fc9709a3 1290 * @param DMAx DMAx Instance
AnnaBridge 189:f392fc9709a3 1291 * @retval State of bit (1 or 0).
AnnaBridge 189:f392fc9709a3 1292 */
AnnaBridge 189:f392fc9709a3 1293 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4(DMA_TypeDef *DMAx)
AnnaBridge 189:f392fc9709a3 1294 {
AnnaBridge 189:f392fc9709a3 1295 return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF4) == (DMA_ISR_TCIF4));
AnnaBridge 189:f392fc9709a3 1296 }
AnnaBridge 189:f392fc9709a3 1297
AnnaBridge 189:f392fc9709a3 1298 /**
AnnaBridge 189:f392fc9709a3 1299 * @brief Get Channel 5 transfer complete flag.
AnnaBridge 189:f392fc9709a3 1300 * @rmtoll ISR TCIF5 LL_DMA_IsActiveFlag_TC5
AnnaBridge 189:f392fc9709a3 1301 * @param DMAx DMAx Instance
AnnaBridge 189:f392fc9709a3 1302 * @retval State of bit (1 or 0).
AnnaBridge 189:f392fc9709a3 1303 */
AnnaBridge 189:f392fc9709a3 1304 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5(DMA_TypeDef *DMAx)
AnnaBridge 189:f392fc9709a3 1305 {
AnnaBridge 189:f392fc9709a3 1306 return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF5) == (DMA_ISR_TCIF5));
AnnaBridge 189:f392fc9709a3 1307 }
AnnaBridge 189:f392fc9709a3 1308
AnnaBridge 189:f392fc9709a3 1309 /**
AnnaBridge 189:f392fc9709a3 1310 * @brief Get Channel 6 transfer complete flag.
AnnaBridge 189:f392fc9709a3 1311 * @rmtoll ISR TCIF6 LL_DMA_IsActiveFlag_TC6
AnnaBridge 189:f392fc9709a3 1312 * @param DMAx DMAx Instance
AnnaBridge 189:f392fc9709a3 1313 * @retval State of bit (1 or 0).
AnnaBridge 189:f392fc9709a3 1314 */
AnnaBridge 189:f392fc9709a3 1315 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6(DMA_TypeDef *DMAx)
AnnaBridge 189:f392fc9709a3 1316 {
AnnaBridge 189:f392fc9709a3 1317 return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF6) == (DMA_ISR_TCIF6));
AnnaBridge 189:f392fc9709a3 1318 }
AnnaBridge 189:f392fc9709a3 1319
AnnaBridge 189:f392fc9709a3 1320 /**
AnnaBridge 189:f392fc9709a3 1321 * @brief Get Channel 7 transfer complete flag.
AnnaBridge 189:f392fc9709a3 1322 * @rmtoll ISR TCIF7 LL_DMA_IsActiveFlag_TC7
AnnaBridge 189:f392fc9709a3 1323 * @param DMAx DMAx Instance
AnnaBridge 189:f392fc9709a3 1324 * @retval State of bit (1 or 0).
AnnaBridge 189:f392fc9709a3 1325 */
AnnaBridge 189:f392fc9709a3 1326 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7(DMA_TypeDef *DMAx)
AnnaBridge 189:f392fc9709a3 1327 {
AnnaBridge 189:f392fc9709a3 1328 return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF7) == (DMA_ISR_TCIF7));
AnnaBridge 189:f392fc9709a3 1329 }
AnnaBridge 189:f392fc9709a3 1330
AnnaBridge 189:f392fc9709a3 1331 /**
AnnaBridge 189:f392fc9709a3 1332 * @brief Get Channel 1 half transfer flag.
AnnaBridge 189:f392fc9709a3 1333 * @rmtoll ISR HTIF1 LL_DMA_IsActiveFlag_HT1
AnnaBridge 189:f392fc9709a3 1334 * @param DMAx DMAx Instance
AnnaBridge 189:f392fc9709a3 1335 * @retval State of bit (1 or 0).
AnnaBridge 189:f392fc9709a3 1336 */
AnnaBridge 189:f392fc9709a3 1337 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1(DMA_TypeDef *DMAx)
AnnaBridge 189:f392fc9709a3 1338 {
AnnaBridge 189:f392fc9709a3 1339 return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF1) == (DMA_ISR_HTIF1));
AnnaBridge 189:f392fc9709a3 1340 }
AnnaBridge 189:f392fc9709a3 1341
AnnaBridge 189:f392fc9709a3 1342 /**
AnnaBridge 189:f392fc9709a3 1343 * @brief Get Channel 2 half transfer flag.
AnnaBridge 189:f392fc9709a3 1344 * @rmtoll ISR HTIF2 LL_DMA_IsActiveFlag_HT2
AnnaBridge 189:f392fc9709a3 1345 * @param DMAx DMAx Instance
AnnaBridge 189:f392fc9709a3 1346 * @retval State of bit (1 or 0).
AnnaBridge 189:f392fc9709a3 1347 */
AnnaBridge 189:f392fc9709a3 1348 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2(DMA_TypeDef *DMAx)
AnnaBridge 189:f392fc9709a3 1349 {
AnnaBridge 189:f392fc9709a3 1350 return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF2) == (DMA_ISR_HTIF2));
AnnaBridge 189:f392fc9709a3 1351 }
AnnaBridge 189:f392fc9709a3 1352
AnnaBridge 189:f392fc9709a3 1353 /**
AnnaBridge 189:f392fc9709a3 1354 * @brief Get Channel 3 half transfer flag.
AnnaBridge 189:f392fc9709a3 1355 * @rmtoll ISR HTIF3 LL_DMA_IsActiveFlag_HT3
AnnaBridge 189:f392fc9709a3 1356 * @param DMAx DMAx Instance
AnnaBridge 189:f392fc9709a3 1357 * @retval State of bit (1 or 0).
AnnaBridge 189:f392fc9709a3 1358 */
AnnaBridge 189:f392fc9709a3 1359 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3(DMA_TypeDef *DMAx)
AnnaBridge 189:f392fc9709a3 1360 {
AnnaBridge 189:f392fc9709a3 1361 return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF3) == (DMA_ISR_HTIF3));
AnnaBridge 189:f392fc9709a3 1362 }
AnnaBridge 189:f392fc9709a3 1363
AnnaBridge 189:f392fc9709a3 1364 /**
AnnaBridge 189:f392fc9709a3 1365 * @brief Get Channel 4 half transfer flag.
AnnaBridge 189:f392fc9709a3 1366 * @rmtoll ISR HTIF4 LL_DMA_IsActiveFlag_HT4
AnnaBridge 189:f392fc9709a3 1367 * @param DMAx DMAx Instance
AnnaBridge 189:f392fc9709a3 1368 * @retval State of bit (1 or 0).
AnnaBridge 189:f392fc9709a3 1369 */
AnnaBridge 189:f392fc9709a3 1370 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4(DMA_TypeDef *DMAx)
AnnaBridge 189:f392fc9709a3 1371 {
AnnaBridge 189:f392fc9709a3 1372 return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF4) == (DMA_ISR_HTIF4));
AnnaBridge 189:f392fc9709a3 1373 }
AnnaBridge 189:f392fc9709a3 1374
AnnaBridge 189:f392fc9709a3 1375 /**
AnnaBridge 189:f392fc9709a3 1376 * @brief Get Channel 5 half transfer flag.
AnnaBridge 189:f392fc9709a3 1377 * @rmtoll ISR HTIF5 LL_DMA_IsActiveFlag_HT5
AnnaBridge 189:f392fc9709a3 1378 * @param DMAx DMAx Instance
AnnaBridge 189:f392fc9709a3 1379 * @retval State of bit (1 or 0).
AnnaBridge 189:f392fc9709a3 1380 */
AnnaBridge 189:f392fc9709a3 1381 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5(DMA_TypeDef *DMAx)
AnnaBridge 189:f392fc9709a3 1382 {
AnnaBridge 189:f392fc9709a3 1383 return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF5) == (DMA_ISR_HTIF5));
AnnaBridge 189:f392fc9709a3 1384 }
AnnaBridge 189:f392fc9709a3 1385
AnnaBridge 189:f392fc9709a3 1386 /**
AnnaBridge 189:f392fc9709a3 1387 * @brief Get Channel 6 half transfer flag.
AnnaBridge 189:f392fc9709a3 1388 * @rmtoll ISR HTIF6 LL_DMA_IsActiveFlag_HT6
AnnaBridge 189:f392fc9709a3 1389 * @param DMAx DMAx Instance
AnnaBridge 189:f392fc9709a3 1390 * @retval State of bit (1 or 0).
AnnaBridge 189:f392fc9709a3 1391 */
AnnaBridge 189:f392fc9709a3 1392 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6(DMA_TypeDef *DMAx)
AnnaBridge 189:f392fc9709a3 1393 {
AnnaBridge 189:f392fc9709a3 1394 return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF6) == (DMA_ISR_HTIF6));
AnnaBridge 189:f392fc9709a3 1395 }
AnnaBridge 189:f392fc9709a3 1396
AnnaBridge 189:f392fc9709a3 1397 /**
AnnaBridge 189:f392fc9709a3 1398 * @brief Get Channel 7 half transfer flag.
AnnaBridge 189:f392fc9709a3 1399 * @rmtoll ISR HTIF7 LL_DMA_IsActiveFlag_HT7
AnnaBridge 189:f392fc9709a3 1400 * @param DMAx DMAx Instance
AnnaBridge 189:f392fc9709a3 1401 * @retval State of bit (1 or 0).
AnnaBridge 189:f392fc9709a3 1402 */
AnnaBridge 189:f392fc9709a3 1403 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7(DMA_TypeDef *DMAx)
AnnaBridge 189:f392fc9709a3 1404 {
AnnaBridge 189:f392fc9709a3 1405 return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF7) == (DMA_ISR_HTIF7));
AnnaBridge 189:f392fc9709a3 1406 }
AnnaBridge 189:f392fc9709a3 1407
AnnaBridge 189:f392fc9709a3 1408 /**
AnnaBridge 189:f392fc9709a3 1409 * @brief Get Channel 1 transfer error flag.
AnnaBridge 189:f392fc9709a3 1410 * @rmtoll ISR TEIF1 LL_DMA_IsActiveFlag_TE1
AnnaBridge 189:f392fc9709a3 1411 * @param DMAx DMAx Instance
AnnaBridge 189:f392fc9709a3 1412 * @retval State of bit (1 or 0).
AnnaBridge 189:f392fc9709a3 1413 */
AnnaBridge 189:f392fc9709a3 1414 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1(DMA_TypeDef *DMAx)
AnnaBridge 189:f392fc9709a3 1415 {
AnnaBridge 189:f392fc9709a3 1416 return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF1) == (DMA_ISR_TEIF1));
AnnaBridge 189:f392fc9709a3 1417 }
AnnaBridge 189:f392fc9709a3 1418
AnnaBridge 189:f392fc9709a3 1419 /**
AnnaBridge 189:f392fc9709a3 1420 * @brief Get Channel 2 transfer error flag.
AnnaBridge 189:f392fc9709a3 1421 * @rmtoll ISR TEIF2 LL_DMA_IsActiveFlag_TE2
AnnaBridge 189:f392fc9709a3 1422 * @param DMAx DMAx Instance
AnnaBridge 189:f392fc9709a3 1423 * @retval State of bit (1 or 0).
AnnaBridge 189:f392fc9709a3 1424 */
AnnaBridge 189:f392fc9709a3 1425 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2(DMA_TypeDef *DMAx)
AnnaBridge 189:f392fc9709a3 1426 {
AnnaBridge 189:f392fc9709a3 1427 return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF2) == (DMA_ISR_TEIF2));
AnnaBridge 189:f392fc9709a3 1428 }
AnnaBridge 189:f392fc9709a3 1429
AnnaBridge 189:f392fc9709a3 1430 /**
AnnaBridge 189:f392fc9709a3 1431 * @brief Get Channel 3 transfer error flag.
AnnaBridge 189:f392fc9709a3 1432 * @rmtoll ISR TEIF3 LL_DMA_IsActiveFlag_TE3
AnnaBridge 189:f392fc9709a3 1433 * @param DMAx DMAx Instance
AnnaBridge 189:f392fc9709a3 1434 * @retval State of bit (1 or 0).
AnnaBridge 189:f392fc9709a3 1435 */
AnnaBridge 189:f392fc9709a3 1436 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3(DMA_TypeDef *DMAx)
AnnaBridge 189:f392fc9709a3 1437 {
AnnaBridge 189:f392fc9709a3 1438 return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF3) == (DMA_ISR_TEIF3));
AnnaBridge 189:f392fc9709a3 1439 }
AnnaBridge 189:f392fc9709a3 1440
AnnaBridge 189:f392fc9709a3 1441 /**
AnnaBridge 189:f392fc9709a3 1442 * @brief Get Channel 4 transfer error flag.
AnnaBridge 189:f392fc9709a3 1443 * @rmtoll ISR TEIF4 LL_DMA_IsActiveFlag_TE4
AnnaBridge 189:f392fc9709a3 1444 * @param DMAx DMAx Instance
AnnaBridge 189:f392fc9709a3 1445 * @retval State of bit (1 or 0).
AnnaBridge 189:f392fc9709a3 1446 */
AnnaBridge 189:f392fc9709a3 1447 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4(DMA_TypeDef *DMAx)
AnnaBridge 189:f392fc9709a3 1448 {
AnnaBridge 189:f392fc9709a3 1449 return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF4) == (DMA_ISR_TEIF4));
AnnaBridge 189:f392fc9709a3 1450 }
AnnaBridge 189:f392fc9709a3 1451
AnnaBridge 189:f392fc9709a3 1452 /**
AnnaBridge 189:f392fc9709a3 1453 * @brief Get Channel 5 transfer error flag.
AnnaBridge 189:f392fc9709a3 1454 * @rmtoll ISR TEIF5 LL_DMA_IsActiveFlag_TE5
AnnaBridge 189:f392fc9709a3 1455 * @param DMAx DMAx Instance
AnnaBridge 189:f392fc9709a3 1456 * @retval State of bit (1 or 0).
AnnaBridge 189:f392fc9709a3 1457 */
AnnaBridge 189:f392fc9709a3 1458 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5(DMA_TypeDef *DMAx)
AnnaBridge 189:f392fc9709a3 1459 {
AnnaBridge 189:f392fc9709a3 1460 return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF5) == (DMA_ISR_TEIF5));
AnnaBridge 189:f392fc9709a3 1461 }
AnnaBridge 189:f392fc9709a3 1462
AnnaBridge 189:f392fc9709a3 1463 /**
AnnaBridge 189:f392fc9709a3 1464 * @brief Get Channel 6 transfer error flag.
AnnaBridge 189:f392fc9709a3 1465 * @rmtoll ISR TEIF6 LL_DMA_IsActiveFlag_TE6
AnnaBridge 189:f392fc9709a3 1466 * @param DMAx DMAx Instance
AnnaBridge 189:f392fc9709a3 1467 * @retval State of bit (1 or 0).
AnnaBridge 189:f392fc9709a3 1468 */
AnnaBridge 189:f392fc9709a3 1469 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6(DMA_TypeDef *DMAx)
AnnaBridge 189:f392fc9709a3 1470 {
AnnaBridge 189:f392fc9709a3 1471 return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF6) == (DMA_ISR_TEIF6));
AnnaBridge 189:f392fc9709a3 1472 }
AnnaBridge 189:f392fc9709a3 1473
AnnaBridge 189:f392fc9709a3 1474 /**
AnnaBridge 189:f392fc9709a3 1475 * @brief Get Channel 7 transfer error flag.
AnnaBridge 189:f392fc9709a3 1476 * @rmtoll ISR TEIF7 LL_DMA_IsActiveFlag_TE7
AnnaBridge 189:f392fc9709a3 1477 * @param DMAx DMAx Instance
AnnaBridge 189:f392fc9709a3 1478 * @retval State of bit (1 or 0).
AnnaBridge 189:f392fc9709a3 1479 */
AnnaBridge 189:f392fc9709a3 1480 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE7(DMA_TypeDef *DMAx)
AnnaBridge 189:f392fc9709a3 1481 {
AnnaBridge 189:f392fc9709a3 1482 return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF7) == (DMA_ISR_TEIF7));
AnnaBridge 189:f392fc9709a3 1483 }
AnnaBridge 189:f392fc9709a3 1484
AnnaBridge 189:f392fc9709a3 1485 /**
AnnaBridge 189:f392fc9709a3 1486 * @brief Clear Channel 1 global interrupt flag.
AnnaBridge 189:f392fc9709a3 1487 * @rmtoll IFCR CGIF1 LL_DMA_ClearFlag_GI1
AnnaBridge 189:f392fc9709a3 1488 * @param DMAx DMAx Instance
AnnaBridge 189:f392fc9709a3 1489 * @retval None
AnnaBridge 189:f392fc9709a3 1490 */
AnnaBridge 189:f392fc9709a3 1491 __STATIC_INLINE void LL_DMA_ClearFlag_GI1(DMA_TypeDef *DMAx)
AnnaBridge 189:f392fc9709a3 1492 {
AnnaBridge 189:f392fc9709a3 1493 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF1);
AnnaBridge 189:f392fc9709a3 1494 }
AnnaBridge 189:f392fc9709a3 1495
AnnaBridge 189:f392fc9709a3 1496 /**
AnnaBridge 189:f392fc9709a3 1497 * @brief Clear Channel 2 global interrupt flag.
AnnaBridge 189:f392fc9709a3 1498 * @rmtoll IFCR CGIF2 LL_DMA_ClearFlag_GI2
AnnaBridge 189:f392fc9709a3 1499 * @param DMAx DMAx Instance
AnnaBridge 189:f392fc9709a3 1500 * @retval None
AnnaBridge 189:f392fc9709a3 1501 */
AnnaBridge 189:f392fc9709a3 1502 __STATIC_INLINE void LL_DMA_ClearFlag_GI2(DMA_TypeDef *DMAx)
AnnaBridge 189:f392fc9709a3 1503 {
AnnaBridge 189:f392fc9709a3 1504 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF2);
AnnaBridge 189:f392fc9709a3 1505 }
AnnaBridge 189:f392fc9709a3 1506
AnnaBridge 189:f392fc9709a3 1507 /**
AnnaBridge 189:f392fc9709a3 1508 * @brief Clear Channel 3 global interrupt flag.
AnnaBridge 189:f392fc9709a3 1509 * @rmtoll IFCR CGIF3 LL_DMA_ClearFlag_GI3
AnnaBridge 189:f392fc9709a3 1510 * @param DMAx DMAx Instance
AnnaBridge 189:f392fc9709a3 1511 * @retval None
AnnaBridge 189:f392fc9709a3 1512 */
AnnaBridge 189:f392fc9709a3 1513 __STATIC_INLINE void LL_DMA_ClearFlag_GI3(DMA_TypeDef *DMAx)
AnnaBridge 189:f392fc9709a3 1514 {
AnnaBridge 189:f392fc9709a3 1515 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF3);
AnnaBridge 189:f392fc9709a3 1516 }
AnnaBridge 189:f392fc9709a3 1517
AnnaBridge 189:f392fc9709a3 1518 /**
AnnaBridge 189:f392fc9709a3 1519 * @brief Clear Channel 4 global interrupt flag.
AnnaBridge 189:f392fc9709a3 1520 * @rmtoll IFCR CGIF4 LL_DMA_ClearFlag_GI4
AnnaBridge 189:f392fc9709a3 1521 * @param DMAx DMAx Instance
AnnaBridge 189:f392fc9709a3 1522 * @retval None
AnnaBridge 189:f392fc9709a3 1523 */
AnnaBridge 189:f392fc9709a3 1524 __STATIC_INLINE void LL_DMA_ClearFlag_GI4(DMA_TypeDef *DMAx)
AnnaBridge 189:f392fc9709a3 1525 {
AnnaBridge 189:f392fc9709a3 1526 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF4);
AnnaBridge 189:f392fc9709a3 1527 }
AnnaBridge 189:f392fc9709a3 1528
AnnaBridge 189:f392fc9709a3 1529 /**
AnnaBridge 189:f392fc9709a3 1530 * @brief Clear Channel 5 global interrupt flag.
AnnaBridge 189:f392fc9709a3 1531 * @rmtoll IFCR CGIF5 LL_DMA_ClearFlag_GI5
AnnaBridge 189:f392fc9709a3 1532 * @param DMAx DMAx Instance
AnnaBridge 189:f392fc9709a3 1533 * @retval None
AnnaBridge 189:f392fc9709a3 1534 */
AnnaBridge 189:f392fc9709a3 1535 __STATIC_INLINE void LL_DMA_ClearFlag_GI5(DMA_TypeDef *DMAx)
AnnaBridge 189:f392fc9709a3 1536 {
AnnaBridge 189:f392fc9709a3 1537 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF5);
AnnaBridge 189:f392fc9709a3 1538 }
AnnaBridge 189:f392fc9709a3 1539
AnnaBridge 189:f392fc9709a3 1540 /**
AnnaBridge 189:f392fc9709a3 1541 * @brief Clear Channel 6 global interrupt flag.
AnnaBridge 189:f392fc9709a3 1542 * @rmtoll IFCR CGIF6 LL_DMA_ClearFlag_GI6
AnnaBridge 189:f392fc9709a3 1543 * @param DMAx DMAx Instance
AnnaBridge 189:f392fc9709a3 1544 * @retval None
AnnaBridge 189:f392fc9709a3 1545 */
AnnaBridge 189:f392fc9709a3 1546 __STATIC_INLINE void LL_DMA_ClearFlag_GI6(DMA_TypeDef *DMAx)
AnnaBridge 189:f392fc9709a3 1547 {
AnnaBridge 189:f392fc9709a3 1548 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF6);
AnnaBridge 189:f392fc9709a3 1549 }
AnnaBridge 189:f392fc9709a3 1550
AnnaBridge 189:f392fc9709a3 1551 /**
AnnaBridge 189:f392fc9709a3 1552 * @brief Clear Channel 7 global interrupt flag.
AnnaBridge 189:f392fc9709a3 1553 * @rmtoll IFCR CGIF7 LL_DMA_ClearFlag_GI7
AnnaBridge 189:f392fc9709a3 1554 * @param DMAx DMAx Instance
AnnaBridge 189:f392fc9709a3 1555 * @retval None
AnnaBridge 189:f392fc9709a3 1556 */
AnnaBridge 189:f392fc9709a3 1557 __STATIC_INLINE void LL_DMA_ClearFlag_GI7(DMA_TypeDef *DMAx)
AnnaBridge 189:f392fc9709a3 1558 {
AnnaBridge 189:f392fc9709a3 1559 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF7);
AnnaBridge 189:f392fc9709a3 1560 }
AnnaBridge 189:f392fc9709a3 1561
AnnaBridge 189:f392fc9709a3 1562 /**
AnnaBridge 189:f392fc9709a3 1563 * @brief Clear Channel 1 transfer complete flag.
AnnaBridge 189:f392fc9709a3 1564 * @rmtoll IFCR CTCIF1 LL_DMA_ClearFlag_TC1
AnnaBridge 189:f392fc9709a3 1565 * @param DMAx DMAx Instance
AnnaBridge 189:f392fc9709a3 1566 * @retval None
AnnaBridge 189:f392fc9709a3 1567 */
AnnaBridge 189:f392fc9709a3 1568 __STATIC_INLINE void LL_DMA_ClearFlag_TC1(DMA_TypeDef *DMAx)
AnnaBridge 189:f392fc9709a3 1569 {
AnnaBridge 189:f392fc9709a3 1570 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF1);
AnnaBridge 189:f392fc9709a3 1571 }
AnnaBridge 189:f392fc9709a3 1572
AnnaBridge 189:f392fc9709a3 1573 /**
AnnaBridge 189:f392fc9709a3 1574 * @brief Clear Channel 2 transfer complete flag.
AnnaBridge 189:f392fc9709a3 1575 * @rmtoll IFCR CTCIF2 LL_DMA_ClearFlag_TC2
AnnaBridge 189:f392fc9709a3 1576 * @param DMAx DMAx Instance
AnnaBridge 189:f392fc9709a3 1577 * @retval None
AnnaBridge 189:f392fc9709a3 1578 */
AnnaBridge 189:f392fc9709a3 1579 __STATIC_INLINE void LL_DMA_ClearFlag_TC2(DMA_TypeDef *DMAx)
AnnaBridge 189:f392fc9709a3 1580 {
AnnaBridge 189:f392fc9709a3 1581 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF2);
AnnaBridge 189:f392fc9709a3 1582 }
AnnaBridge 189:f392fc9709a3 1583
AnnaBridge 189:f392fc9709a3 1584 /**
AnnaBridge 189:f392fc9709a3 1585 * @brief Clear Channel 3 transfer complete flag.
AnnaBridge 189:f392fc9709a3 1586 * @rmtoll IFCR CTCIF3 LL_DMA_ClearFlag_TC3
AnnaBridge 189:f392fc9709a3 1587 * @param DMAx DMAx Instance
AnnaBridge 189:f392fc9709a3 1588 * @retval None
AnnaBridge 189:f392fc9709a3 1589 */
AnnaBridge 189:f392fc9709a3 1590 __STATIC_INLINE void LL_DMA_ClearFlag_TC3(DMA_TypeDef *DMAx)
AnnaBridge 189:f392fc9709a3 1591 {
AnnaBridge 189:f392fc9709a3 1592 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF3);
AnnaBridge 189:f392fc9709a3 1593 }
AnnaBridge 189:f392fc9709a3 1594
AnnaBridge 189:f392fc9709a3 1595 /**
AnnaBridge 189:f392fc9709a3 1596 * @brief Clear Channel 4 transfer complete flag.
AnnaBridge 189:f392fc9709a3 1597 * @rmtoll IFCR CTCIF4 LL_DMA_ClearFlag_TC4
AnnaBridge 189:f392fc9709a3 1598 * @param DMAx DMAx Instance
AnnaBridge 189:f392fc9709a3 1599 * @retval None
AnnaBridge 189:f392fc9709a3 1600 */
AnnaBridge 189:f392fc9709a3 1601 __STATIC_INLINE void LL_DMA_ClearFlag_TC4(DMA_TypeDef *DMAx)
AnnaBridge 189:f392fc9709a3 1602 {
AnnaBridge 189:f392fc9709a3 1603 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF4);
AnnaBridge 189:f392fc9709a3 1604 }
AnnaBridge 189:f392fc9709a3 1605
AnnaBridge 189:f392fc9709a3 1606 /**
AnnaBridge 189:f392fc9709a3 1607 * @brief Clear Channel 5 transfer complete flag.
AnnaBridge 189:f392fc9709a3 1608 * @rmtoll IFCR CTCIF5 LL_DMA_ClearFlag_TC5
AnnaBridge 189:f392fc9709a3 1609 * @param DMAx DMAx Instance
AnnaBridge 189:f392fc9709a3 1610 * @retval None
AnnaBridge 189:f392fc9709a3 1611 */
AnnaBridge 189:f392fc9709a3 1612 __STATIC_INLINE void LL_DMA_ClearFlag_TC5(DMA_TypeDef *DMAx)
AnnaBridge 189:f392fc9709a3 1613 {
AnnaBridge 189:f392fc9709a3 1614 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF5);
AnnaBridge 189:f392fc9709a3 1615 }
AnnaBridge 189:f392fc9709a3 1616
AnnaBridge 189:f392fc9709a3 1617 /**
AnnaBridge 189:f392fc9709a3 1618 * @brief Clear Channel 6 transfer complete flag.
AnnaBridge 189:f392fc9709a3 1619 * @rmtoll IFCR CTCIF6 LL_DMA_ClearFlag_TC6
AnnaBridge 189:f392fc9709a3 1620 * @param DMAx DMAx Instance
AnnaBridge 189:f392fc9709a3 1621 * @retval None
AnnaBridge 189:f392fc9709a3 1622 */
AnnaBridge 189:f392fc9709a3 1623 __STATIC_INLINE void LL_DMA_ClearFlag_TC6(DMA_TypeDef *DMAx)
AnnaBridge 189:f392fc9709a3 1624 {
AnnaBridge 189:f392fc9709a3 1625 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF6);
AnnaBridge 189:f392fc9709a3 1626 }
AnnaBridge 189:f392fc9709a3 1627
AnnaBridge 189:f392fc9709a3 1628 /**
AnnaBridge 189:f392fc9709a3 1629 * @brief Clear Channel 7 transfer complete flag.
AnnaBridge 189:f392fc9709a3 1630 * @rmtoll IFCR CTCIF7 LL_DMA_ClearFlag_TC7
AnnaBridge 189:f392fc9709a3 1631 * @param DMAx DMAx Instance
AnnaBridge 189:f392fc9709a3 1632 * @retval None
AnnaBridge 189:f392fc9709a3 1633 */
AnnaBridge 189:f392fc9709a3 1634 __STATIC_INLINE void LL_DMA_ClearFlag_TC7(DMA_TypeDef *DMAx)
AnnaBridge 189:f392fc9709a3 1635 {
AnnaBridge 189:f392fc9709a3 1636 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF7);
AnnaBridge 189:f392fc9709a3 1637 }
AnnaBridge 189:f392fc9709a3 1638
AnnaBridge 189:f392fc9709a3 1639 /**
AnnaBridge 189:f392fc9709a3 1640 * @brief Clear Channel 1 half transfer flag.
AnnaBridge 189:f392fc9709a3 1641 * @rmtoll IFCR CHTIF1 LL_DMA_ClearFlag_HT1
AnnaBridge 189:f392fc9709a3 1642 * @param DMAx DMAx Instance
AnnaBridge 189:f392fc9709a3 1643 * @retval None
AnnaBridge 189:f392fc9709a3 1644 */
AnnaBridge 189:f392fc9709a3 1645 __STATIC_INLINE void LL_DMA_ClearFlag_HT1(DMA_TypeDef *DMAx)
AnnaBridge 189:f392fc9709a3 1646 {
AnnaBridge 189:f392fc9709a3 1647 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF1);
AnnaBridge 189:f392fc9709a3 1648 }
AnnaBridge 189:f392fc9709a3 1649
AnnaBridge 189:f392fc9709a3 1650 /**
AnnaBridge 189:f392fc9709a3 1651 * @brief Clear Channel 2 half transfer flag.
AnnaBridge 189:f392fc9709a3 1652 * @rmtoll IFCR CHTIF2 LL_DMA_ClearFlag_HT2
AnnaBridge 189:f392fc9709a3 1653 * @param DMAx DMAx Instance
AnnaBridge 189:f392fc9709a3 1654 * @retval None
AnnaBridge 189:f392fc9709a3 1655 */
AnnaBridge 189:f392fc9709a3 1656 __STATIC_INLINE void LL_DMA_ClearFlag_HT2(DMA_TypeDef *DMAx)
AnnaBridge 189:f392fc9709a3 1657 {
AnnaBridge 189:f392fc9709a3 1658 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF2);
AnnaBridge 189:f392fc9709a3 1659 }
AnnaBridge 189:f392fc9709a3 1660
AnnaBridge 189:f392fc9709a3 1661 /**
AnnaBridge 189:f392fc9709a3 1662 * @brief Clear Channel 3 half transfer flag.
AnnaBridge 189:f392fc9709a3 1663 * @rmtoll IFCR CHTIF3 LL_DMA_ClearFlag_HT3
AnnaBridge 189:f392fc9709a3 1664 * @param DMAx DMAx Instance
AnnaBridge 189:f392fc9709a3 1665 * @retval None
AnnaBridge 189:f392fc9709a3 1666 */
AnnaBridge 189:f392fc9709a3 1667 __STATIC_INLINE void LL_DMA_ClearFlag_HT3(DMA_TypeDef *DMAx)
AnnaBridge 189:f392fc9709a3 1668 {
AnnaBridge 189:f392fc9709a3 1669 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF3);
AnnaBridge 189:f392fc9709a3 1670 }
AnnaBridge 189:f392fc9709a3 1671
AnnaBridge 189:f392fc9709a3 1672 /**
AnnaBridge 189:f392fc9709a3 1673 * @brief Clear Channel 4 half transfer flag.
AnnaBridge 189:f392fc9709a3 1674 * @rmtoll IFCR CHTIF4 LL_DMA_ClearFlag_HT4
AnnaBridge 189:f392fc9709a3 1675 * @param DMAx DMAx Instance
AnnaBridge 189:f392fc9709a3 1676 * @retval None
AnnaBridge 189:f392fc9709a3 1677 */
AnnaBridge 189:f392fc9709a3 1678 __STATIC_INLINE void LL_DMA_ClearFlag_HT4(DMA_TypeDef *DMAx)
AnnaBridge 189:f392fc9709a3 1679 {
AnnaBridge 189:f392fc9709a3 1680 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF4);
AnnaBridge 189:f392fc9709a3 1681 }
AnnaBridge 189:f392fc9709a3 1682
AnnaBridge 189:f392fc9709a3 1683 /**
AnnaBridge 189:f392fc9709a3 1684 * @brief Clear Channel 5 half transfer flag.
AnnaBridge 189:f392fc9709a3 1685 * @rmtoll IFCR CHTIF5 LL_DMA_ClearFlag_HT5
AnnaBridge 189:f392fc9709a3 1686 * @param DMAx DMAx Instance
AnnaBridge 189:f392fc9709a3 1687 * @retval None
AnnaBridge 189:f392fc9709a3 1688 */
AnnaBridge 189:f392fc9709a3 1689 __STATIC_INLINE void LL_DMA_ClearFlag_HT5(DMA_TypeDef *DMAx)
AnnaBridge 189:f392fc9709a3 1690 {
AnnaBridge 189:f392fc9709a3 1691 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF5);
AnnaBridge 189:f392fc9709a3 1692 }
AnnaBridge 189:f392fc9709a3 1693
AnnaBridge 189:f392fc9709a3 1694 /**
AnnaBridge 189:f392fc9709a3 1695 * @brief Clear Channel 6 half transfer flag.
AnnaBridge 189:f392fc9709a3 1696 * @rmtoll IFCR CHTIF6 LL_DMA_ClearFlag_HT6
AnnaBridge 189:f392fc9709a3 1697 * @param DMAx DMAx Instance
AnnaBridge 189:f392fc9709a3 1698 * @retval None
AnnaBridge 189:f392fc9709a3 1699 */
AnnaBridge 189:f392fc9709a3 1700 __STATIC_INLINE void LL_DMA_ClearFlag_HT6(DMA_TypeDef *DMAx)
AnnaBridge 189:f392fc9709a3 1701 {
AnnaBridge 189:f392fc9709a3 1702 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF6);
AnnaBridge 189:f392fc9709a3 1703 }
AnnaBridge 189:f392fc9709a3 1704
AnnaBridge 189:f392fc9709a3 1705 /**
AnnaBridge 189:f392fc9709a3 1706 * @brief Clear Channel 7 half transfer flag.
AnnaBridge 189:f392fc9709a3 1707 * @rmtoll IFCR CHTIF7 LL_DMA_ClearFlag_HT7
AnnaBridge 189:f392fc9709a3 1708 * @param DMAx DMAx Instance
AnnaBridge 189:f392fc9709a3 1709 * @retval None
AnnaBridge 189:f392fc9709a3 1710 */
AnnaBridge 189:f392fc9709a3 1711 __STATIC_INLINE void LL_DMA_ClearFlag_HT7(DMA_TypeDef *DMAx)
AnnaBridge 189:f392fc9709a3 1712 {
AnnaBridge 189:f392fc9709a3 1713 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF7);
AnnaBridge 189:f392fc9709a3 1714 }
AnnaBridge 189:f392fc9709a3 1715
AnnaBridge 189:f392fc9709a3 1716 /**
AnnaBridge 189:f392fc9709a3 1717 * @brief Clear Channel 1 transfer error flag.
AnnaBridge 189:f392fc9709a3 1718 * @rmtoll IFCR CTEIF1 LL_DMA_ClearFlag_TE1
AnnaBridge 189:f392fc9709a3 1719 * @param DMAx DMAx Instance
AnnaBridge 189:f392fc9709a3 1720 * @retval None
AnnaBridge 189:f392fc9709a3 1721 */
AnnaBridge 189:f392fc9709a3 1722 __STATIC_INLINE void LL_DMA_ClearFlag_TE1(DMA_TypeDef *DMAx)
AnnaBridge 189:f392fc9709a3 1723 {
AnnaBridge 189:f392fc9709a3 1724 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF1);
AnnaBridge 189:f392fc9709a3 1725 }
AnnaBridge 189:f392fc9709a3 1726
AnnaBridge 189:f392fc9709a3 1727 /**
AnnaBridge 189:f392fc9709a3 1728 * @brief Clear Channel 2 transfer error flag.
AnnaBridge 189:f392fc9709a3 1729 * @rmtoll IFCR CTEIF2 LL_DMA_ClearFlag_TE2
AnnaBridge 189:f392fc9709a3 1730 * @param DMAx DMAx Instance
AnnaBridge 189:f392fc9709a3 1731 * @retval None
AnnaBridge 189:f392fc9709a3 1732 */
AnnaBridge 189:f392fc9709a3 1733 __STATIC_INLINE void LL_DMA_ClearFlag_TE2(DMA_TypeDef *DMAx)
AnnaBridge 189:f392fc9709a3 1734 {
AnnaBridge 189:f392fc9709a3 1735 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF2);
AnnaBridge 189:f392fc9709a3 1736 }
AnnaBridge 189:f392fc9709a3 1737
AnnaBridge 189:f392fc9709a3 1738 /**
AnnaBridge 189:f392fc9709a3 1739 * @brief Clear Channel 3 transfer error flag.
AnnaBridge 189:f392fc9709a3 1740 * @rmtoll IFCR CTEIF3 LL_DMA_ClearFlag_TE3
AnnaBridge 189:f392fc9709a3 1741 * @param DMAx DMAx Instance
AnnaBridge 189:f392fc9709a3 1742 * @retval None
AnnaBridge 189:f392fc9709a3 1743 */
AnnaBridge 189:f392fc9709a3 1744 __STATIC_INLINE void LL_DMA_ClearFlag_TE3(DMA_TypeDef *DMAx)
AnnaBridge 189:f392fc9709a3 1745 {
AnnaBridge 189:f392fc9709a3 1746 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF3);
AnnaBridge 189:f392fc9709a3 1747 }
AnnaBridge 189:f392fc9709a3 1748
AnnaBridge 189:f392fc9709a3 1749 /**
AnnaBridge 189:f392fc9709a3 1750 * @brief Clear Channel 4 transfer error flag.
AnnaBridge 189:f392fc9709a3 1751 * @rmtoll IFCR CTEIF4 LL_DMA_ClearFlag_TE4
AnnaBridge 189:f392fc9709a3 1752 * @param DMAx DMAx Instance
AnnaBridge 189:f392fc9709a3 1753 * @retval None
AnnaBridge 189:f392fc9709a3 1754 */
AnnaBridge 189:f392fc9709a3 1755 __STATIC_INLINE void LL_DMA_ClearFlag_TE4(DMA_TypeDef *DMAx)
AnnaBridge 189:f392fc9709a3 1756 {
AnnaBridge 189:f392fc9709a3 1757 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF4);
AnnaBridge 189:f392fc9709a3 1758 }
AnnaBridge 189:f392fc9709a3 1759
AnnaBridge 189:f392fc9709a3 1760 /**
AnnaBridge 189:f392fc9709a3 1761 * @brief Clear Channel 5 transfer error flag.
AnnaBridge 189:f392fc9709a3 1762 * @rmtoll IFCR CTEIF5 LL_DMA_ClearFlag_TE5
AnnaBridge 189:f392fc9709a3 1763 * @param DMAx DMAx Instance
AnnaBridge 189:f392fc9709a3 1764 * @retval None
AnnaBridge 189:f392fc9709a3 1765 */
AnnaBridge 189:f392fc9709a3 1766 __STATIC_INLINE void LL_DMA_ClearFlag_TE5(DMA_TypeDef *DMAx)
AnnaBridge 189:f392fc9709a3 1767 {
AnnaBridge 189:f392fc9709a3 1768 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF5);
AnnaBridge 189:f392fc9709a3 1769 }
AnnaBridge 189:f392fc9709a3 1770
AnnaBridge 189:f392fc9709a3 1771 /**
AnnaBridge 189:f392fc9709a3 1772 * @brief Clear Channel 6 transfer error flag.
AnnaBridge 189:f392fc9709a3 1773 * @rmtoll IFCR CTEIF6 LL_DMA_ClearFlag_TE6
AnnaBridge 189:f392fc9709a3 1774 * @param DMAx DMAx Instance
AnnaBridge 189:f392fc9709a3 1775 * @retval None
AnnaBridge 189:f392fc9709a3 1776 */
AnnaBridge 189:f392fc9709a3 1777 __STATIC_INLINE void LL_DMA_ClearFlag_TE6(DMA_TypeDef *DMAx)
AnnaBridge 189:f392fc9709a3 1778 {
AnnaBridge 189:f392fc9709a3 1779 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF6);
AnnaBridge 189:f392fc9709a3 1780 }
AnnaBridge 189:f392fc9709a3 1781
AnnaBridge 189:f392fc9709a3 1782 /**
AnnaBridge 189:f392fc9709a3 1783 * @brief Clear Channel 7 transfer error flag.
AnnaBridge 189:f392fc9709a3 1784 * @rmtoll IFCR CTEIF7 LL_DMA_ClearFlag_TE7
AnnaBridge 189:f392fc9709a3 1785 * @param DMAx DMAx Instance
AnnaBridge 189:f392fc9709a3 1786 * @retval None
AnnaBridge 189:f392fc9709a3 1787 */
AnnaBridge 189:f392fc9709a3 1788 __STATIC_INLINE void LL_DMA_ClearFlag_TE7(DMA_TypeDef *DMAx)
AnnaBridge 189:f392fc9709a3 1789 {
AnnaBridge 189:f392fc9709a3 1790 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF7);
AnnaBridge 189:f392fc9709a3 1791 }
AnnaBridge 189:f392fc9709a3 1792
AnnaBridge 189:f392fc9709a3 1793 /**
AnnaBridge 189:f392fc9709a3 1794 * @}
AnnaBridge 189:f392fc9709a3 1795 */
AnnaBridge 189:f392fc9709a3 1796
AnnaBridge 189:f392fc9709a3 1797 /** @defgroup DMA_LL_EF_IT_Management IT_Management
AnnaBridge 189:f392fc9709a3 1798 * @{
AnnaBridge 189:f392fc9709a3 1799 */
AnnaBridge 189:f392fc9709a3 1800 /**
AnnaBridge 189:f392fc9709a3 1801 * @brief Enable Transfer complete interrupt.
AnnaBridge 189:f392fc9709a3 1802 * @rmtoll CCR TCIE LL_DMA_EnableIT_TC
AnnaBridge 189:f392fc9709a3 1803 * @param DMAx DMAx Instance
AnnaBridge 189:f392fc9709a3 1804 * @param Channel This parameter can be one of the following values:
AnnaBridge 189:f392fc9709a3 1805 * @arg @ref LL_DMA_CHANNEL_1
AnnaBridge 189:f392fc9709a3 1806 * @arg @ref LL_DMA_CHANNEL_2
AnnaBridge 189:f392fc9709a3 1807 * @arg @ref LL_DMA_CHANNEL_3
AnnaBridge 189:f392fc9709a3 1808 * @arg @ref LL_DMA_CHANNEL_4
AnnaBridge 189:f392fc9709a3 1809 * @arg @ref LL_DMA_CHANNEL_5
AnnaBridge 189:f392fc9709a3 1810 * @arg @ref LL_DMA_CHANNEL_6
AnnaBridge 189:f392fc9709a3 1811 * @arg @ref LL_DMA_CHANNEL_7
AnnaBridge 189:f392fc9709a3 1812 * @retval None
AnnaBridge 189:f392fc9709a3 1813 */
AnnaBridge 189:f392fc9709a3 1814 __STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge 189:f392fc9709a3 1815 {
AnnaBridge 189:f392fc9709a3 1816 SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TCIE);
AnnaBridge 189:f392fc9709a3 1817 }
AnnaBridge 189:f392fc9709a3 1818
AnnaBridge 189:f392fc9709a3 1819 /**
AnnaBridge 189:f392fc9709a3 1820 * @brief Enable Half transfer interrupt.
AnnaBridge 189:f392fc9709a3 1821 * @rmtoll CCR HTIE LL_DMA_EnableIT_HT
AnnaBridge 189:f392fc9709a3 1822 * @param DMAx DMAx Instance
AnnaBridge 189:f392fc9709a3 1823 * @param Channel This parameter can be one of the following values:
AnnaBridge 189:f392fc9709a3 1824 * @arg @ref LL_DMA_CHANNEL_1
AnnaBridge 189:f392fc9709a3 1825 * @arg @ref LL_DMA_CHANNEL_2
AnnaBridge 189:f392fc9709a3 1826 * @arg @ref LL_DMA_CHANNEL_3
AnnaBridge 189:f392fc9709a3 1827 * @arg @ref LL_DMA_CHANNEL_4
AnnaBridge 189:f392fc9709a3 1828 * @arg @ref LL_DMA_CHANNEL_5
AnnaBridge 189:f392fc9709a3 1829 * @arg @ref LL_DMA_CHANNEL_6
AnnaBridge 189:f392fc9709a3 1830 * @arg @ref LL_DMA_CHANNEL_7
AnnaBridge 189:f392fc9709a3 1831 * @retval None
AnnaBridge 189:f392fc9709a3 1832 */
AnnaBridge 189:f392fc9709a3 1833 __STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge 189:f392fc9709a3 1834 {
AnnaBridge 189:f392fc9709a3 1835 SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_HTIE);
AnnaBridge 189:f392fc9709a3 1836 }
AnnaBridge 189:f392fc9709a3 1837
AnnaBridge 189:f392fc9709a3 1838 /**
AnnaBridge 189:f392fc9709a3 1839 * @brief Enable Transfer error interrupt.
AnnaBridge 189:f392fc9709a3 1840 * @rmtoll CCR TEIE LL_DMA_EnableIT_TE
AnnaBridge 189:f392fc9709a3 1841 * @param DMAx DMAx Instance
AnnaBridge 189:f392fc9709a3 1842 * @param Channel This parameter can be one of the following values:
AnnaBridge 189:f392fc9709a3 1843 * @arg @ref LL_DMA_CHANNEL_1
AnnaBridge 189:f392fc9709a3 1844 * @arg @ref LL_DMA_CHANNEL_2
AnnaBridge 189:f392fc9709a3 1845 * @arg @ref LL_DMA_CHANNEL_3
AnnaBridge 189:f392fc9709a3 1846 * @arg @ref LL_DMA_CHANNEL_4
AnnaBridge 189:f392fc9709a3 1847 * @arg @ref LL_DMA_CHANNEL_5
AnnaBridge 189:f392fc9709a3 1848 * @arg @ref LL_DMA_CHANNEL_6
AnnaBridge 189:f392fc9709a3 1849 * @arg @ref LL_DMA_CHANNEL_7
AnnaBridge 189:f392fc9709a3 1850 * @retval None
AnnaBridge 189:f392fc9709a3 1851 */
AnnaBridge 189:f392fc9709a3 1852 __STATIC_INLINE void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge 189:f392fc9709a3 1853 {
AnnaBridge 189:f392fc9709a3 1854 SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TEIE);
AnnaBridge 189:f392fc9709a3 1855 }
AnnaBridge 189:f392fc9709a3 1856
AnnaBridge 189:f392fc9709a3 1857 /**
AnnaBridge 189:f392fc9709a3 1858 * @brief Disable Transfer complete interrupt.
AnnaBridge 189:f392fc9709a3 1859 * @rmtoll CCR TCIE LL_DMA_DisableIT_TC
AnnaBridge 189:f392fc9709a3 1860 * @param DMAx DMAx Instance
AnnaBridge 189:f392fc9709a3 1861 * @param Channel This parameter can be one of the following values:
AnnaBridge 189:f392fc9709a3 1862 * @arg @ref LL_DMA_CHANNEL_1
AnnaBridge 189:f392fc9709a3 1863 * @arg @ref LL_DMA_CHANNEL_2
AnnaBridge 189:f392fc9709a3 1864 * @arg @ref LL_DMA_CHANNEL_3
AnnaBridge 189:f392fc9709a3 1865 * @arg @ref LL_DMA_CHANNEL_4
AnnaBridge 189:f392fc9709a3 1866 * @arg @ref LL_DMA_CHANNEL_5
AnnaBridge 189:f392fc9709a3 1867 * @arg @ref LL_DMA_CHANNEL_6
AnnaBridge 189:f392fc9709a3 1868 * @arg @ref LL_DMA_CHANNEL_7
AnnaBridge 189:f392fc9709a3 1869 * @retval None
AnnaBridge 189:f392fc9709a3 1870 */
AnnaBridge 189:f392fc9709a3 1871 __STATIC_INLINE void LL_DMA_DisableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge 189:f392fc9709a3 1872 {
AnnaBridge 189:f392fc9709a3 1873 CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TCIE);
AnnaBridge 189:f392fc9709a3 1874 }
AnnaBridge 189:f392fc9709a3 1875
AnnaBridge 189:f392fc9709a3 1876 /**
AnnaBridge 189:f392fc9709a3 1877 * @brief Disable Half transfer interrupt.
AnnaBridge 189:f392fc9709a3 1878 * @rmtoll CCR HTIE LL_DMA_DisableIT_HT
AnnaBridge 189:f392fc9709a3 1879 * @param DMAx DMAx Instance
AnnaBridge 189:f392fc9709a3 1880 * @param Channel This parameter can be one of the following values:
AnnaBridge 189:f392fc9709a3 1881 * @arg @ref LL_DMA_CHANNEL_1
AnnaBridge 189:f392fc9709a3 1882 * @arg @ref LL_DMA_CHANNEL_2
AnnaBridge 189:f392fc9709a3 1883 * @arg @ref LL_DMA_CHANNEL_3
AnnaBridge 189:f392fc9709a3 1884 * @arg @ref LL_DMA_CHANNEL_4
AnnaBridge 189:f392fc9709a3 1885 * @arg @ref LL_DMA_CHANNEL_5
AnnaBridge 189:f392fc9709a3 1886 * @arg @ref LL_DMA_CHANNEL_6
AnnaBridge 189:f392fc9709a3 1887 * @arg @ref LL_DMA_CHANNEL_7
AnnaBridge 189:f392fc9709a3 1888 * @retval None
AnnaBridge 189:f392fc9709a3 1889 */
AnnaBridge 189:f392fc9709a3 1890 __STATIC_INLINE void LL_DMA_DisableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge 189:f392fc9709a3 1891 {
AnnaBridge 189:f392fc9709a3 1892 CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_HTIE);
AnnaBridge 189:f392fc9709a3 1893 }
AnnaBridge 189:f392fc9709a3 1894
AnnaBridge 189:f392fc9709a3 1895 /**
AnnaBridge 189:f392fc9709a3 1896 * @brief Disable Transfer error interrupt.
AnnaBridge 189:f392fc9709a3 1897 * @rmtoll CCR TEIE LL_DMA_DisableIT_TE
AnnaBridge 189:f392fc9709a3 1898 * @param DMAx DMAx Instance
AnnaBridge 189:f392fc9709a3 1899 * @param Channel This parameter can be one of the following values:
AnnaBridge 189:f392fc9709a3 1900 * @arg @ref LL_DMA_CHANNEL_1
AnnaBridge 189:f392fc9709a3 1901 * @arg @ref LL_DMA_CHANNEL_2
AnnaBridge 189:f392fc9709a3 1902 * @arg @ref LL_DMA_CHANNEL_3
AnnaBridge 189:f392fc9709a3 1903 * @arg @ref LL_DMA_CHANNEL_4
AnnaBridge 189:f392fc9709a3 1904 * @arg @ref LL_DMA_CHANNEL_5
AnnaBridge 189:f392fc9709a3 1905 * @arg @ref LL_DMA_CHANNEL_6
AnnaBridge 189:f392fc9709a3 1906 * @arg @ref LL_DMA_CHANNEL_7
AnnaBridge 189:f392fc9709a3 1907 * @retval None
AnnaBridge 189:f392fc9709a3 1908 */
AnnaBridge 189:f392fc9709a3 1909 __STATIC_INLINE void LL_DMA_DisableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge 189:f392fc9709a3 1910 {
AnnaBridge 189:f392fc9709a3 1911 CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TEIE);
AnnaBridge 189:f392fc9709a3 1912 }
AnnaBridge 189:f392fc9709a3 1913
AnnaBridge 189:f392fc9709a3 1914 /**
AnnaBridge 189:f392fc9709a3 1915 * @brief Check if Transfer complete Interrupt is enabled.
AnnaBridge 189:f392fc9709a3 1916 * @rmtoll CCR TCIE LL_DMA_IsEnabledIT_TC
AnnaBridge 189:f392fc9709a3 1917 * @param DMAx DMAx Instance
AnnaBridge 189:f392fc9709a3 1918 * @param Channel This parameter can be one of the following values:
AnnaBridge 189:f392fc9709a3 1919 * @arg @ref LL_DMA_CHANNEL_1
AnnaBridge 189:f392fc9709a3 1920 * @arg @ref LL_DMA_CHANNEL_2
AnnaBridge 189:f392fc9709a3 1921 * @arg @ref LL_DMA_CHANNEL_3
AnnaBridge 189:f392fc9709a3 1922 * @arg @ref LL_DMA_CHANNEL_4
AnnaBridge 189:f392fc9709a3 1923 * @arg @ref LL_DMA_CHANNEL_5
AnnaBridge 189:f392fc9709a3 1924 * @arg @ref LL_DMA_CHANNEL_6
AnnaBridge 189:f392fc9709a3 1925 * @arg @ref LL_DMA_CHANNEL_7
AnnaBridge 189:f392fc9709a3 1926 * @retval State of bit (1 or 0).
AnnaBridge 189:f392fc9709a3 1927 */
AnnaBridge 189:f392fc9709a3 1928 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge 189:f392fc9709a3 1929 {
AnnaBridge 189:f392fc9709a3 1930 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
AnnaBridge 189:f392fc9709a3 1931 DMA_CCR_TCIE) == (DMA_CCR_TCIE));
AnnaBridge 189:f392fc9709a3 1932 }
AnnaBridge 189:f392fc9709a3 1933
AnnaBridge 189:f392fc9709a3 1934 /**
AnnaBridge 189:f392fc9709a3 1935 * @brief Check if Half transfer Interrupt is enabled.
AnnaBridge 189:f392fc9709a3 1936 * @rmtoll CCR HTIE LL_DMA_IsEnabledIT_HT
AnnaBridge 189:f392fc9709a3 1937 * @param DMAx DMAx Instance
AnnaBridge 189:f392fc9709a3 1938 * @param Channel This parameter can be one of the following values:
AnnaBridge 189:f392fc9709a3 1939 * @arg @ref LL_DMA_CHANNEL_1
AnnaBridge 189:f392fc9709a3 1940 * @arg @ref LL_DMA_CHANNEL_2
AnnaBridge 189:f392fc9709a3 1941 * @arg @ref LL_DMA_CHANNEL_3
AnnaBridge 189:f392fc9709a3 1942 * @arg @ref LL_DMA_CHANNEL_4
AnnaBridge 189:f392fc9709a3 1943 * @arg @ref LL_DMA_CHANNEL_5
AnnaBridge 189:f392fc9709a3 1944 * @arg @ref LL_DMA_CHANNEL_6
AnnaBridge 189:f392fc9709a3 1945 * @arg @ref LL_DMA_CHANNEL_7
AnnaBridge 189:f392fc9709a3 1946 * @retval State of bit (1 or 0).
AnnaBridge 189:f392fc9709a3 1947 */
AnnaBridge 189:f392fc9709a3 1948 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge 189:f392fc9709a3 1949 {
AnnaBridge 189:f392fc9709a3 1950 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
AnnaBridge 189:f392fc9709a3 1951 DMA_CCR_HTIE) == (DMA_CCR_HTIE));
AnnaBridge 189:f392fc9709a3 1952 }
AnnaBridge 189:f392fc9709a3 1953
AnnaBridge 189:f392fc9709a3 1954 /**
AnnaBridge 189:f392fc9709a3 1955 * @brief Check if Transfer error Interrupt is enabled.
AnnaBridge 189:f392fc9709a3 1956 * @rmtoll CCR TEIE LL_DMA_IsEnabledIT_TE
AnnaBridge 189:f392fc9709a3 1957 * @param DMAx DMAx Instance
AnnaBridge 189:f392fc9709a3 1958 * @param Channel This parameter can be one of the following values:
AnnaBridge 189:f392fc9709a3 1959 * @arg @ref LL_DMA_CHANNEL_1
AnnaBridge 189:f392fc9709a3 1960 * @arg @ref LL_DMA_CHANNEL_2
AnnaBridge 189:f392fc9709a3 1961 * @arg @ref LL_DMA_CHANNEL_3
AnnaBridge 189:f392fc9709a3 1962 * @arg @ref LL_DMA_CHANNEL_4
AnnaBridge 189:f392fc9709a3 1963 * @arg @ref LL_DMA_CHANNEL_5
AnnaBridge 189:f392fc9709a3 1964 * @arg @ref LL_DMA_CHANNEL_6
AnnaBridge 189:f392fc9709a3 1965 * @arg @ref LL_DMA_CHANNEL_7
AnnaBridge 189:f392fc9709a3 1966 * @retval State of bit (1 or 0).
AnnaBridge 189:f392fc9709a3 1967 */
AnnaBridge 189:f392fc9709a3 1968 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge 189:f392fc9709a3 1969 {
AnnaBridge 189:f392fc9709a3 1970 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
AnnaBridge 189:f392fc9709a3 1971 DMA_CCR_TEIE) == (DMA_CCR_TEIE));
AnnaBridge 189:f392fc9709a3 1972 }
AnnaBridge 189:f392fc9709a3 1973
AnnaBridge 189:f392fc9709a3 1974 /**
AnnaBridge 189:f392fc9709a3 1975 * @}
AnnaBridge 189:f392fc9709a3 1976 */
AnnaBridge 189:f392fc9709a3 1977
AnnaBridge 189:f392fc9709a3 1978 #if defined(USE_FULL_LL_DRIVER)
AnnaBridge 189:f392fc9709a3 1979 /** @defgroup DMA_LL_EF_Init Initialization and de-initialization functions
AnnaBridge 189:f392fc9709a3 1980 * @{
AnnaBridge 189:f392fc9709a3 1981 */
AnnaBridge 189:f392fc9709a3 1982
AnnaBridge 189:f392fc9709a3 1983 uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DMA_InitStruct);
AnnaBridge 189:f392fc9709a3 1984 uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel);
AnnaBridge 189:f392fc9709a3 1985 void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct);
AnnaBridge 189:f392fc9709a3 1986
AnnaBridge 189:f392fc9709a3 1987 /**
AnnaBridge 189:f392fc9709a3 1988 * @}
AnnaBridge 189:f392fc9709a3 1989 */
AnnaBridge 189:f392fc9709a3 1990 #endif /* USE_FULL_LL_DRIVER */
AnnaBridge 189:f392fc9709a3 1991
AnnaBridge 189:f392fc9709a3 1992 /**
AnnaBridge 189:f392fc9709a3 1993 * @}
AnnaBridge 189:f392fc9709a3 1994 */
AnnaBridge 189:f392fc9709a3 1995
AnnaBridge 189:f392fc9709a3 1996 /**
AnnaBridge 189:f392fc9709a3 1997 * @}
AnnaBridge 189:f392fc9709a3 1998 */
AnnaBridge 189:f392fc9709a3 1999
AnnaBridge 189:f392fc9709a3 2000 #endif /* DMA1 || DMA2 */
AnnaBridge 189:f392fc9709a3 2001
AnnaBridge 189:f392fc9709a3 2002 /**
AnnaBridge 189:f392fc9709a3 2003 * @}
AnnaBridge 189:f392fc9709a3 2004 */
AnnaBridge 189:f392fc9709a3 2005
AnnaBridge 189:f392fc9709a3 2006 #ifdef __cplusplus
AnnaBridge 189:f392fc9709a3 2007 }
AnnaBridge 189:f392fc9709a3 2008 #endif
AnnaBridge 189:f392fc9709a3 2009
AnnaBridge 189:f392fc9709a3 2010 #endif /* __STM32F3xx_LL_DMA_H */
AnnaBridge 189:f392fc9709a3 2011
AnnaBridge 189:f392fc9709a3 2012 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/