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targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/efm32lg_vcmp.h@144:ef7eb2e8f9f7, 2016-09-02 (annotated)

Committer:
<>
Date:
Fri Sep 02 15:07:44 2016 +0100
Revision:
144:ef7eb2e8f9f7
Parent:
50:a417edff4437 
This updates the lib to the mbed lib v125

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**************************************************************************//**
<> 144:ef7eb2e8f9f7 2 * @file efm32lg_vcmp.h
<> 144:ef7eb2e8f9f7 3 * @brief EFM32LG_VCMP register and bit field definitions
<> 144:ef7eb2e8f9f7 4 * @version 4.2.0
<> 144:ef7eb2e8f9f7 5 ******************************************************************************
<> 144:ef7eb2e8f9f7 6 * @section License
<> 144:ef7eb2e8f9f7 7 * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
<> 144:ef7eb2e8f9f7 8 ******************************************************************************
<> 144:ef7eb2e8f9f7 9 *
<> 144:ef7eb2e8f9f7 10 * Permission is granted to anyone to use this software for any purpose,
<> 144:ef7eb2e8f9f7 11 * including commercial applications, and to alter it and redistribute it
<> 144:ef7eb2e8f9f7 12 * freely, subject to the following restrictions:
<> 144:ef7eb2e8f9f7 13 *
<> 144:ef7eb2e8f9f7 14 * 1. The origin of this software must not be misrepresented; you must not
<> 144:ef7eb2e8f9f7 15 * claim that you wrote the original software.@n
<> 144:ef7eb2e8f9f7 16 * 2. Altered source versions must be plainly marked as such, and must not be
<> 144:ef7eb2e8f9f7 17 * misrepresented as being the original software.@n
<> 144:ef7eb2e8f9f7 18 * 3. This notice may not be removed or altered from any source distribution.
<> 144:ef7eb2e8f9f7 19 *
<> 144:ef7eb2e8f9f7 20 * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
<> 144:ef7eb2e8f9f7 21 * has no obligation to support this Software. Silicon Laboratories, Inc. is
<> 144:ef7eb2e8f9f7 22 * providing the Software "AS IS", with no express or implied warranties of any
<> 144:ef7eb2e8f9f7 23 * kind, including, but not limited to, any implied warranties of
<> 144:ef7eb2e8f9f7 24 * merchantability or fitness for any particular purpose or warranties against
<> 144:ef7eb2e8f9f7 25 * infringement of any proprietary rights of a third party.
<> 144:ef7eb2e8f9f7 26 *
<> 144:ef7eb2e8f9f7 27 * Silicon Laboratories, Inc. will not be liable for any consequential,
<> 144:ef7eb2e8f9f7 28 * incidental, or special damages, or any other relief, or for any claim by
<> 144:ef7eb2e8f9f7 29 * any third party, arising from your use of this Software.
<> 144:ef7eb2e8f9f7 30 *
<> 144:ef7eb2e8f9f7 31 *****************************************************************************/
<> 144:ef7eb2e8f9f7 32 /**************************************************************************//**
<> 144:ef7eb2e8f9f7 33 * @addtogroup Parts
<> 144:ef7eb2e8f9f7 34 * @{
<> 144:ef7eb2e8f9f7 35 ******************************************************************************/
<> 144:ef7eb2e8f9f7 36 /**************************************************************************//**
<> 144:ef7eb2e8f9f7 37 * @defgroup EFM32LG_VCMP
<> 144:ef7eb2e8f9f7 38 * @{
<> 144:ef7eb2e8f9f7 39 * @brief EFM32LG_VCMP Register Declaration
<> 144:ef7eb2e8f9f7 40 *****************************************************************************/
<> 144:ef7eb2e8f9f7 41 typedef struct
<> 144:ef7eb2e8f9f7 42 {
<> 144:ef7eb2e8f9f7 43 __IO uint32_t CTRL; /**< Control Register */
<> 144:ef7eb2e8f9f7 44 __IO uint32_t INPUTSEL; /**< Input Selection Register */
<> 144:ef7eb2e8f9f7 45 __I uint32_t STATUS; /**< Status Register */
<> 144:ef7eb2e8f9f7 46 __IO uint32_t IEN; /**< Interrupt Enable Register */
<> 144:ef7eb2e8f9f7 47 __I uint32_t IF; /**< Interrupt Flag Register */
<> 144:ef7eb2e8f9f7 48 __IO uint32_t IFS; /**< Interrupt Flag Set Register */
<> 144:ef7eb2e8f9f7 49 __IO uint32_t IFC; /**< Interrupt Flag Clear Register */
<> 144:ef7eb2e8f9f7 50 } VCMP_TypeDef; /** @} */
<> 144:ef7eb2e8f9f7 51
<> 144:ef7eb2e8f9f7 52 /**************************************************************************//**
<> 144:ef7eb2e8f9f7 53 * @defgroup EFM32LG_VCMP_BitFields
<> 144:ef7eb2e8f9f7 54 * @{
<> 144:ef7eb2e8f9f7 55 *****************************************************************************/
<> 144:ef7eb2e8f9f7 56
<> 144:ef7eb2e8f9f7 57 /* Bit fields for VCMP CTRL */
<> 144:ef7eb2e8f9f7 58 #define _VCMP_CTRL_RESETVALUE 0x47000000UL /**< Default value for VCMP_CTRL */
<> 144:ef7eb2e8f9f7 59 #define _VCMP_CTRL_MASK 0x4F030715UL /**< Mask for VCMP_CTRL */
<> 144:ef7eb2e8f9f7 60 #define VCMP_CTRL_EN (0x1UL << 0) /**< Voltage Supply Comparator Enable */
<> 144:ef7eb2e8f9f7 61 #define _VCMP_CTRL_EN_SHIFT 0 /**< Shift value for VCMP_EN */
<> 144:ef7eb2e8f9f7 62 #define _VCMP_CTRL_EN_MASK 0x1UL /**< Bit mask for VCMP_EN */
<> 144:ef7eb2e8f9f7 63 #define _VCMP_CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for VCMP_CTRL */
<> 144:ef7eb2e8f9f7 64 #define VCMP_CTRL_EN_DEFAULT (_VCMP_CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for VCMP_CTRL */
<> 144:ef7eb2e8f9f7 65 #define VCMP_CTRL_INACTVAL (0x1UL << 2) /**< Inactive Value */
<> 144:ef7eb2e8f9f7 66 #define _VCMP_CTRL_INACTVAL_SHIFT 2 /**< Shift value for VCMP_INACTVAL */
<> 144:ef7eb2e8f9f7 67 #define _VCMP_CTRL_INACTVAL_MASK 0x4UL /**< Bit mask for VCMP_INACTVAL */
<> 144:ef7eb2e8f9f7 68 #define _VCMP_CTRL_INACTVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for VCMP_CTRL */
<> 144:ef7eb2e8f9f7 69 #define VCMP_CTRL_INACTVAL_DEFAULT (_VCMP_CTRL_INACTVAL_DEFAULT << 2) /**< Shifted mode DEFAULT for VCMP_CTRL */
<> 144:ef7eb2e8f9f7 70 #define VCMP_CTRL_HYSTEN (0x1UL << 4) /**< Hysteresis Enable */
<> 144:ef7eb2e8f9f7 71 #define _VCMP_CTRL_HYSTEN_SHIFT 4 /**< Shift value for VCMP_HYSTEN */
<> 144:ef7eb2e8f9f7 72 #define _VCMP_CTRL_HYSTEN_MASK 0x10UL /**< Bit mask for VCMP_HYSTEN */
<> 144:ef7eb2e8f9f7 73 #define _VCMP_CTRL_HYSTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for VCMP_CTRL */
<> 144:ef7eb2e8f9f7 74 #define VCMP_CTRL_HYSTEN_DEFAULT (_VCMP_CTRL_HYSTEN_DEFAULT << 4) /**< Shifted mode DEFAULT for VCMP_CTRL */
<> 144:ef7eb2e8f9f7 75 #define _VCMP_CTRL_WARMTIME_SHIFT 8 /**< Shift value for VCMP_WARMTIME */
<> 144:ef7eb2e8f9f7 76 #define _VCMP_CTRL_WARMTIME_MASK 0x700UL /**< Bit mask for VCMP_WARMTIME */
<> 144:ef7eb2e8f9f7 77 #define _VCMP_CTRL_WARMTIME_DEFAULT 0x00000000UL /**< Mode DEFAULT for VCMP_CTRL */
<> 144:ef7eb2e8f9f7 78 #define _VCMP_CTRL_WARMTIME_4CYCLES 0x00000000UL /**< Mode 4CYCLES for VCMP_CTRL */
<> 144:ef7eb2e8f9f7 79 #define _VCMP_CTRL_WARMTIME_8CYCLES 0x00000001UL /**< Mode 8CYCLES for VCMP_CTRL */
<> 144:ef7eb2e8f9f7 80 #define _VCMP_CTRL_WARMTIME_16CYCLES 0x00000002UL /**< Mode 16CYCLES for VCMP_CTRL */
<> 144:ef7eb2e8f9f7 81 #define _VCMP_CTRL_WARMTIME_32CYCLES 0x00000003UL /**< Mode 32CYCLES for VCMP_CTRL */
<> 144:ef7eb2e8f9f7 82 #define _VCMP_CTRL_WARMTIME_64CYCLES 0x00000004UL /**< Mode 64CYCLES for VCMP_CTRL */
<> 144:ef7eb2e8f9f7 83 #define _VCMP_CTRL_WARMTIME_128CYCLES 0x00000005UL /**< Mode 128CYCLES for VCMP_CTRL */
<> 144:ef7eb2e8f9f7 84 #define _VCMP_CTRL_WARMTIME_256CYCLES 0x00000006UL /**< Mode 256CYCLES for VCMP_CTRL */
<> 144:ef7eb2e8f9f7 85 #define _VCMP_CTRL_WARMTIME_512CYCLES 0x00000007UL /**< Mode 512CYCLES for VCMP_CTRL */
<> 144:ef7eb2e8f9f7 86 #define VCMP_CTRL_WARMTIME_DEFAULT (_VCMP_CTRL_WARMTIME_DEFAULT << 8) /**< Shifted mode DEFAULT for VCMP_CTRL */
<> 144:ef7eb2e8f9f7 87 #define VCMP_CTRL_WARMTIME_4CYCLES (_VCMP_CTRL_WARMTIME_4CYCLES << 8) /**< Shifted mode 4CYCLES for VCMP_CTRL */
<> 144:ef7eb2e8f9f7 88 #define VCMP_CTRL_WARMTIME_8CYCLES (_VCMP_CTRL_WARMTIME_8CYCLES << 8) /**< Shifted mode 8CYCLES for VCMP_CTRL */
<> 144:ef7eb2e8f9f7 89 #define VCMP_CTRL_WARMTIME_16CYCLES (_VCMP_CTRL_WARMTIME_16CYCLES << 8) /**< Shifted mode 16CYCLES for VCMP_CTRL */
<> 144:ef7eb2e8f9f7 90 #define VCMP_CTRL_WARMTIME_32CYCLES (_VCMP_CTRL_WARMTIME_32CYCLES << 8) /**< Shifted mode 32CYCLES for VCMP_CTRL */
<> 144:ef7eb2e8f9f7 91 #define VCMP_CTRL_WARMTIME_64CYCLES (_VCMP_CTRL_WARMTIME_64CYCLES << 8) /**< Shifted mode 64CYCLES for VCMP_CTRL */
<> 144:ef7eb2e8f9f7 92 #define VCMP_CTRL_WARMTIME_128CYCLES (_VCMP_CTRL_WARMTIME_128CYCLES << 8) /**< Shifted mode 128CYCLES for VCMP_CTRL */
<> 144:ef7eb2e8f9f7 93 #define VCMP_CTRL_WARMTIME_256CYCLES (_VCMP_CTRL_WARMTIME_256CYCLES << 8) /**< Shifted mode 256CYCLES for VCMP_CTRL */
<> 144:ef7eb2e8f9f7 94 #define VCMP_CTRL_WARMTIME_512CYCLES (_VCMP_CTRL_WARMTIME_512CYCLES << 8) /**< Shifted mode 512CYCLES for VCMP_CTRL */
<> 144:ef7eb2e8f9f7 95 #define VCMP_CTRL_IRISE (0x1UL << 16) /**< Rising Edge Interrupt Sense */
<> 144:ef7eb2e8f9f7 96 #define _VCMP_CTRL_IRISE_SHIFT 16 /**< Shift value for VCMP_IRISE */
<> 144:ef7eb2e8f9f7 97 #define _VCMP_CTRL_IRISE_MASK 0x10000UL /**< Bit mask for VCMP_IRISE */
<> 144:ef7eb2e8f9f7 98 #define _VCMP_CTRL_IRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VCMP_CTRL */
<> 144:ef7eb2e8f9f7 99 #define VCMP_CTRL_IRISE_DEFAULT (_VCMP_CTRL_IRISE_DEFAULT << 16) /**< Shifted mode DEFAULT for VCMP_CTRL */
<> 144:ef7eb2e8f9f7 100 #define VCMP_CTRL_IFALL (0x1UL << 17) /**< Falling Edge Interrupt Sense */
<> 144:ef7eb2e8f9f7 101 #define _VCMP_CTRL_IFALL_SHIFT 17 /**< Shift value for VCMP_IFALL */
<> 144:ef7eb2e8f9f7 102 #define _VCMP_CTRL_IFALL_MASK 0x20000UL /**< Bit mask for VCMP_IFALL */
<> 144:ef7eb2e8f9f7 103 #define _VCMP_CTRL_IFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for VCMP_CTRL */
<> 144:ef7eb2e8f9f7 104 #define VCMP_CTRL_IFALL_DEFAULT (_VCMP_CTRL_IFALL_DEFAULT << 17) /**< Shifted mode DEFAULT for VCMP_CTRL */
<> 144:ef7eb2e8f9f7 105 #define _VCMP_CTRL_BIASPROG_SHIFT 24 /**< Shift value for VCMP_BIASPROG */
<> 144:ef7eb2e8f9f7 106 #define _VCMP_CTRL_BIASPROG_MASK 0xF000000UL /**< Bit mask for VCMP_BIASPROG */
<> 144:ef7eb2e8f9f7 107 #define _VCMP_CTRL_BIASPROG_DEFAULT 0x00000007UL /**< Mode DEFAULT for VCMP_CTRL */
<> 144:ef7eb2e8f9f7 108 #define VCMP_CTRL_BIASPROG_DEFAULT (_VCMP_CTRL_BIASPROG_DEFAULT << 24) /**< Shifted mode DEFAULT for VCMP_CTRL */
<> 144:ef7eb2e8f9f7 109 #define VCMP_CTRL_HALFBIAS (0x1UL << 30) /**< Half Bias Current */
<> 144:ef7eb2e8f9f7 110 #define _VCMP_CTRL_HALFBIAS_SHIFT 30 /**< Shift value for VCMP_HALFBIAS */
<> 144:ef7eb2e8f9f7 111 #define _VCMP_CTRL_HALFBIAS_MASK 0x40000000UL /**< Bit mask for VCMP_HALFBIAS */
<> 144:ef7eb2e8f9f7 112 #define _VCMP_CTRL_HALFBIAS_DEFAULT 0x00000001UL /**< Mode DEFAULT for VCMP_CTRL */
<> 144:ef7eb2e8f9f7 113 #define VCMP_CTRL_HALFBIAS_DEFAULT (_VCMP_CTRL_HALFBIAS_DEFAULT << 30) /**< Shifted mode DEFAULT for VCMP_CTRL */
<> 144:ef7eb2e8f9f7 114
<> 144:ef7eb2e8f9f7 115 /* Bit fields for VCMP INPUTSEL */
<> 144:ef7eb2e8f9f7 116 #define _VCMP_INPUTSEL_RESETVALUE 0x00000000UL /**< Default value for VCMP_INPUTSEL */
<> 144:ef7eb2e8f9f7 117 #define _VCMP_INPUTSEL_MASK 0x0000013FUL /**< Mask for VCMP_INPUTSEL */
<> 144:ef7eb2e8f9f7 118 #define _VCMP_INPUTSEL_TRIGLEVEL_SHIFT 0 /**< Shift value for VCMP_TRIGLEVEL */
<> 144:ef7eb2e8f9f7 119 #define _VCMP_INPUTSEL_TRIGLEVEL_MASK 0x3FUL /**< Bit mask for VCMP_TRIGLEVEL */
<> 144:ef7eb2e8f9f7 120 #define _VCMP_INPUTSEL_TRIGLEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for VCMP_INPUTSEL */
<> 144:ef7eb2e8f9f7 121 #define VCMP_INPUTSEL_TRIGLEVEL_DEFAULT (_VCMP_INPUTSEL_TRIGLEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for VCMP_INPUTSEL */
<> 144:ef7eb2e8f9f7 122 #define VCMP_INPUTSEL_LPREF (0x1UL << 8) /**< Low Power Reference */
<> 144:ef7eb2e8f9f7 123 #define _VCMP_INPUTSEL_LPREF_SHIFT 8 /**< Shift value for VCMP_LPREF */
<> 144:ef7eb2e8f9f7 124 #define _VCMP_INPUTSEL_LPREF_MASK 0x100UL /**< Bit mask for VCMP_LPREF */
<> 144:ef7eb2e8f9f7 125 #define _VCMP_INPUTSEL_LPREF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VCMP_INPUTSEL */
<> 144:ef7eb2e8f9f7 126 #define VCMP_INPUTSEL_LPREF_DEFAULT (_VCMP_INPUTSEL_LPREF_DEFAULT << 8) /**< Shifted mode DEFAULT for VCMP_INPUTSEL */
<> 144:ef7eb2e8f9f7 127
<> 144:ef7eb2e8f9f7 128 /* Bit fields for VCMP STATUS */
<> 144:ef7eb2e8f9f7 129 #define _VCMP_STATUS_RESETVALUE 0x00000000UL /**< Default value for VCMP_STATUS */
<> 144:ef7eb2e8f9f7 130 #define _VCMP_STATUS_MASK 0x00000003UL /**< Mask for VCMP_STATUS */
<> 144:ef7eb2e8f9f7 131 #define VCMP_STATUS_VCMPACT (0x1UL << 0) /**< Voltage Supply Comparator Active */
<> 144:ef7eb2e8f9f7 132 #define _VCMP_STATUS_VCMPACT_SHIFT 0 /**< Shift value for VCMP_VCMPACT */
<> 144:ef7eb2e8f9f7 133 #define _VCMP_STATUS_VCMPACT_MASK 0x1UL /**< Bit mask for VCMP_VCMPACT */
<> 144:ef7eb2e8f9f7 134 #define _VCMP_STATUS_VCMPACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VCMP_STATUS */
<> 144:ef7eb2e8f9f7 135 #define VCMP_STATUS_VCMPACT_DEFAULT (_VCMP_STATUS_VCMPACT_DEFAULT << 0) /**< Shifted mode DEFAULT for VCMP_STATUS */
<> 144:ef7eb2e8f9f7 136 #define VCMP_STATUS_VCMPOUT (0x1UL << 1) /**< Voltage Supply Comparator Output */
<> 144:ef7eb2e8f9f7 137 #define _VCMP_STATUS_VCMPOUT_SHIFT 1 /**< Shift value for VCMP_VCMPOUT */
<> 144:ef7eb2e8f9f7 138 #define _VCMP_STATUS_VCMPOUT_MASK 0x2UL /**< Bit mask for VCMP_VCMPOUT */
<> 144:ef7eb2e8f9f7 139 #define _VCMP_STATUS_VCMPOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VCMP_STATUS */
<> 144:ef7eb2e8f9f7 140 #define VCMP_STATUS_VCMPOUT_DEFAULT (_VCMP_STATUS_VCMPOUT_DEFAULT << 1) /**< Shifted mode DEFAULT for VCMP_STATUS */
<> 144:ef7eb2e8f9f7 141
<> 144:ef7eb2e8f9f7 142 /* Bit fields for VCMP IEN */
<> 144:ef7eb2e8f9f7 143 #define _VCMP_IEN_RESETVALUE 0x00000000UL /**< Default value for VCMP_IEN */
<> 144:ef7eb2e8f9f7 144 #define _VCMP_IEN_MASK 0x00000003UL /**< Mask for VCMP_IEN */
<> 144:ef7eb2e8f9f7 145 #define VCMP_IEN_EDGE (0x1UL << 0) /**< Edge Trigger Interrupt Enable */
<> 144:ef7eb2e8f9f7 146 #define _VCMP_IEN_EDGE_SHIFT 0 /**< Shift value for VCMP_EDGE */
<> 144:ef7eb2e8f9f7 147 #define _VCMP_IEN_EDGE_MASK 0x1UL /**< Bit mask for VCMP_EDGE */
<> 144:ef7eb2e8f9f7 148 #define _VCMP_IEN_EDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VCMP_IEN */
<> 144:ef7eb2e8f9f7 149 #define VCMP_IEN_EDGE_DEFAULT (_VCMP_IEN_EDGE_DEFAULT << 0) /**< Shifted mode DEFAULT for VCMP_IEN */
<> 144:ef7eb2e8f9f7 150 #define VCMP_IEN_WARMUP (0x1UL << 1) /**< Warm-up Interrupt Enable */
<> 144:ef7eb2e8f9f7 151 #define _VCMP_IEN_WARMUP_SHIFT 1 /**< Shift value for VCMP_WARMUP */
<> 144:ef7eb2e8f9f7 152 #define _VCMP_IEN_WARMUP_MASK 0x2UL /**< Bit mask for VCMP_WARMUP */
<> 144:ef7eb2e8f9f7 153 #define _VCMP_IEN_WARMUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for VCMP_IEN */
<> 144:ef7eb2e8f9f7 154 #define VCMP_IEN_WARMUP_DEFAULT (_VCMP_IEN_WARMUP_DEFAULT << 1) /**< Shifted mode DEFAULT for VCMP_IEN */
<> 144:ef7eb2e8f9f7 155
<> 144:ef7eb2e8f9f7 156 /* Bit fields for VCMP IF */
<> 144:ef7eb2e8f9f7 157 #define _VCMP_IF_RESETVALUE 0x00000000UL /**< Default value for VCMP_IF */
<> 144:ef7eb2e8f9f7 158 #define _VCMP_IF_MASK 0x00000003UL /**< Mask for VCMP_IF */
<> 144:ef7eb2e8f9f7 159 #define VCMP_IF_EDGE (0x1UL << 0) /**< Edge Triggered Interrupt Flag */
<> 144:ef7eb2e8f9f7 160 #define _VCMP_IF_EDGE_SHIFT 0 /**< Shift value for VCMP_EDGE */
<> 144:ef7eb2e8f9f7 161 #define _VCMP_IF_EDGE_MASK 0x1UL /**< Bit mask for VCMP_EDGE */
<> 144:ef7eb2e8f9f7 162 #define _VCMP_IF_EDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VCMP_IF */
<> 144:ef7eb2e8f9f7 163 #define VCMP_IF_EDGE_DEFAULT (_VCMP_IF_EDGE_DEFAULT << 0) /**< Shifted mode DEFAULT for VCMP_IF */
<> 144:ef7eb2e8f9f7 164 #define VCMP_IF_WARMUP (0x1UL << 1) /**< Warm-up Interrupt Flag */
<> 144:ef7eb2e8f9f7 165 #define _VCMP_IF_WARMUP_SHIFT 1 /**< Shift value for VCMP_WARMUP */
<> 144:ef7eb2e8f9f7 166 #define _VCMP_IF_WARMUP_MASK 0x2UL /**< Bit mask for VCMP_WARMUP */
<> 144:ef7eb2e8f9f7 167 #define _VCMP_IF_WARMUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for VCMP_IF */
<> 144:ef7eb2e8f9f7 168 #define VCMP_IF_WARMUP_DEFAULT (_VCMP_IF_WARMUP_DEFAULT << 1) /**< Shifted mode DEFAULT for VCMP_IF */
<> 144:ef7eb2e8f9f7 169
<> 144:ef7eb2e8f9f7 170 /* Bit fields for VCMP IFS */
<> 144:ef7eb2e8f9f7 171 #define _VCMP_IFS_RESETVALUE 0x00000000UL /**< Default value for VCMP_IFS */
<> 144:ef7eb2e8f9f7 172 #define _VCMP_IFS_MASK 0x00000003UL /**< Mask for VCMP_IFS */
<> 144:ef7eb2e8f9f7 173 #define VCMP_IFS_EDGE (0x1UL << 0) /**< Edge Triggered Interrupt Flag Set */
<> 144:ef7eb2e8f9f7 174 #define _VCMP_IFS_EDGE_SHIFT 0 /**< Shift value for VCMP_EDGE */
<> 144:ef7eb2e8f9f7 175 #define _VCMP_IFS_EDGE_MASK 0x1UL /**< Bit mask for VCMP_EDGE */
<> 144:ef7eb2e8f9f7 176 #define _VCMP_IFS_EDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VCMP_IFS */
<> 144:ef7eb2e8f9f7 177 #define VCMP_IFS_EDGE_DEFAULT (_VCMP_IFS_EDGE_DEFAULT << 0) /**< Shifted mode DEFAULT for VCMP_IFS */
<> 144:ef7eb2e8f9f7 178 #define VCMP_IFS_WARMUP (0x1UL << 1) /**< Warm-up Interrupt Flag Set */
<> 144:ef7eb2e8f9f7 179 #define _VCMP_IFS_WARMUP_SHIFT 1 /**< Shift value for VCMP_WARMUP */
<> 144:ef7eb2e8f9f7 180 #define _VCMP_IFS_WARMUP_MASK 0x2UL /**< Bit mask for VCMP_WARMUP */
<> 144:ef7eb2e8f9f7 181 #define _VCMP_IFS_WARMUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for VCMP_IFS */
<> 144:ef7eb2e8f9f7 182 #define VCMP_IFS_WARMUP_DEFAULT (_VCMP_IFS_WARMUP_DEFAULT << 1) /**< Shifted mode DEFAULT for VCMP_IFS */
<> 144:ef7eb2e8f9f7 183
<> 144:ef7eb2e8f9f7 184 /* Bit fields for VCMP IFC */
<> 144:ef7eb2e8f9f7 185 #define _VCMP_IFC_RESETVALUE 0x00000000UL /**< Default value for VCMP_IFC */
<> 144:ef7eb2e8f9f7 186 #define _VCMP_IFC_MASK 0x00000003UL /**< Mask for VCMP_IFC */
<> 144:ef7eb2e8f9f7 187 #define VCMP_IFC_EDGE (0x1UL << 0) /**< Edge Triggered Interrupt Flag Clear */
<> 144:ef7eb2e8f9f7 188 #define _VCMP_IFC_EDGE_SHIFT 0 /**< Shift value for VCMP_EDGE */
<> 144:ef7eb2e8f9f7 189 #define _VCMP_IFC_EDGE_MASK 0x1UL /**< Bit mask for VCMP_EDGE */
<> 144:ef7eb2e8f9f7 190 #define _VCMP_IFC_EDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VCMP_IFC */
<> 144:ef7eb2e8f9f7 191 #define VCMP_IFC_EDGE_DEFAULT (_VCMP_IFC_EDGE_DEFAULT << 0) /**< Shifted mode DEFAULT for VCMP_IFC */
<> 144:ef7eb2e8f9f7 192 #define VCMP_IFC_WARMUP (0x1UL << 1) /**< Warm-up Interrupt Flag Clear */
<> 144:ef7eb2e8f9f7 193 #define _VCMP_IFC_WARMUP_SHIFT 1 /**< Shift value for VCMP_WARMUP */
<> 144:ef7eb2e8f9f7 194 #define _VCMP_IFC_WARMUP_MASK 0x2UL /**< Bit mask for VCMP_WARMUP */
<> 144:ef7eb2e8f9f7 195 #define _VCMP_IFC_WARMUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for VCMP_IFC */
<> 144:ef7eb2e8f9f7 196 #define VCMP_IFC_WARMUP_DEFAULT (_VCMP_IFC_WARMUP_DEFAULT << 1) /**< Shifted mode DEFAULT for VCMP_IFC */
<> 144:ef7eb2e8f9f7 197
<> 144:ef7eb2e8f9f7 198 /** @} End of group EFM32LG_VCMP */
<> 144:ef7eb2e8f9f7 199 /** @} End of group Parts */
<> 144:ef7eb2e8f9f7 200