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targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_qspi.h@167:e84263d55307, 2017-06-21 (annotated)

Committer:
AnnaBridge
Date:
Wed Jun 21 17:46:44 2017 +0100
Revision:
167:e84263d55307
Parent:
149:156823d33999
Child:
182:a56a73fd2a6f
This updates the lib to the mbed lib v 145

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f4xx_hal_qspi.h
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
AnnaBridge 167:e84263d55307 5 * @version V1.7.1
AnnaBridge 167:e84263d55307 6 * @date 14-April-2017
<> 144:ef7eb2e8f9f7 7 * @brief Header file of QSPI HAL module.
<> 144:ef7eb2e8f9f7 8 ******************************************************************************
<> 144:ef7eb2e8f9f7 9 * @attention
<> 144:ef7eb2e8f9f7 10 *
AnnaBridge 167:e84263d55307 11 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 12 *
<> 144:ef7eb2e8f9f7 13 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 14 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 15 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 16 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 18 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 19 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 21 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 22 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 23 *
<> 144:ef7eb2e8f9f7 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 34 *
<> 144:ef7eb2e8f9f7 35 ******************************************************************************
<> 144:ef7eb2e8f9f7 36 */
<> 144:ef7eb2e8f9f7 37
<> 144:ef7eb2e8f9f7 38 /* Define to prevent recursive inclusion -------------------------------------*/
<> 144:ef7eb2e8f9f7 39 #ifndef __STM32F4xx_HAL_QSPI_H
<> 144:ef7eb2e8f9f7 40 #define __STM32F4xx_HAL_QSPI_H
<> 144:ef7eb2e8f9f7 41
<> 144:ef7eb2e8f9f7 42 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 43 extern "C" {
<> 144:ef7eb2e8f9f7 44 #endif
<> 144:ef7eb2e8f9f7 45
<> 144:ef7eb2e8f9f7 46 #if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
AnnaBridge 167:e84263d55307 47 defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx)
<> 144:ef7eb2e8f9f7 48 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 49 #include "stm32f4xx_hal_def.h"
<> 144:ef7eb2e8f9f7 50
<> 144:ef7eb2e8f9f7 51 /** @addtogroup STM32F4xx_HAL_Driver
<> 144:ef7eb2e8f9f7 52 * @{
<> 144:ef7eb2e8f9f7 53 */
<> 144:ef7eb2e8f9f7 54
<> 144:ef7eb2e8f9f7 55 /** @addtogroup QSPI
<> 144:ef7eb2e8f9f7 56 * @{
<> 144:ef7eb2e8f9f7 57 */
<> 144:ef7eb2e8f9f7 58
<> 144:ef7eb2e8f9f7 59 /* Exported types ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 60 /** @defgroup QSPI_Exported_Types QSPI Exported Types
<> 144:ef7eb2e8f9f7 61 * @{
<> 144:ef7eb2e8f9f7 62 */
<> 144:ef7eb2e8f9f7 63
<> 144:ef7eb2e8f9f7 64 /**
<> 144:ef7eb2e8f9f7 65 * @brief QSPI Init structure definition
<> 144:ef7eb2e8f9f7 66 */
<> 144:ef7eb2e8f9f7 67
<> 144:ef7eb2e8f9f7 68 typedef struct
<> 144:ef7eb2e8f9f7 69 {
<> 144:ef7eb2e8f9f7 70 uint32_t ClockPrescaler; /* Specifies the prescaler factor for generating clock based on the AHB clock.
<> 144:ef7eb2e8f9f7 71 This parameter can be a number between 0 and 255 */
<> 144:ef7eb2e8f9f7 72
<> 144:ef7eb2e8f9f7 73 uint32_t FifoThreshold; /* Specifies the threshold number of bytes in the FIFO (used only in indirect mode)
<> 144:ef7eb2e8f9f7 74 This parameter can be a value between 1 and 32 */
<> 144:ef7eb2e8f9f7 75
<> 144:ef7eb2e8f9f7 76 uint32_t SampleShifting; /* Specifies the Sample Shift. The data is sampled 1/2 clock cycle delay later to
<> 144:ef7eb2e8f9f7 77 take in account external signal delays. (It should be QSPI_SAMPLE_SHIFTING_NONE in DDR mode)
<> 144:ef7eb2e8f9f7 78 This parameter can be a value of @ref QSPI_SampleShifting */
<> 144:ef7eb2e8f9f7 79
<> 144:ef7eb2e8f9f7 80 uint32_t FlashSize; /* Specifies the Flash Size. FlashSize+1 is effectively the number of address bits
<> 144:ef7eb2e8f9f7 81 required to address the flash memory. The flash capacity can be up to 4GB
<> 144:ef7eb2e8f9f7 82 (addressed using 32 bits) in indirect mode, but the addressable space in
<> 144:ef7eb2e8f9f7 83 memory-mapped mode is limited to 256MB
<> 144:ef7eb2e8f9f7 84 This parameter can be a number between 0 and 31 */
<> 144:ef7eb2e8f9f7 85
<> 144:ef7eb2e8f9f7 86 uint32_t ChipSelectHighTime; /* Specifies the Chip Select High Time. ChipSelectHighTime+1 defines the minimum number
<> 144:ef7eb2e8f9f7 87 of clock cycles which the chip select must remain high between commands.
<> 144:ef7eb2e8f9f7 88 This parameter can be a value of @ref QSPI_ChipSelectHighTime */
<> 144:ef7eb2e8f9f7 89
<> 144:ef7eb2e8f9f7 90 uint32_t ClockMode; /* Specifies the Clock Mode. It indicates the level that clock takes between commands.
<> 144:ef7eb2e8f9f7 91 This parameter can be a value of @ref QSPI_ClockMode */
<> 144:ef7eb2e8f9f7 92
<> 144:ef7eb2e8f9f7 93 uint32_t FlashID; /* Specifies the Flash which will be used,
<> 144:ef7eb2e8f9f7 94 This parameter can be a value of @ref QSPI_Flash_Select */
<> 144:ef7eb2e8f9f7 95
<> 144:ef7eb2e8f9f7 96 uint32_t DualFlash; /* Specifies the Dual Flash Mode State
<> 144:ef7eb2e8f9f7 97 This parameter can be a value of @ref QSPI_DualFlash_Mode */
<> 144:ef7eb2e8f9f7 98 }QSPI_InitTypeDef;
<> 144:ef7eb2e8f9f7 99
<> 144:ef7eb2e8f9f7 100 /**
<> 144:ef7eb2e8f9f7 101 * @brief HAL QSPI State structures definition
<> 144:ef7eb2e8f9f7 102 */
<> 144:ef7eb2e8f9f7 103 typedef enum
<> 144:ef7eb2e8f9f7 104 {
<> 144:ef7eb2e8f9f7 105 HAL_QSPI_STATE_RESET = 0x00U, /*!< Peripheral not initialized */
<> 144:ef7eb2e8f9f7 106 HAL_QSPI_STATE_READY = 0x01U, /*!< Peripheral initialized and ready for use */
<> 144:ef7eb2e8f9f7 107 HAL_QSPI_STATE_BUSY = 0x02U, /*!< Peripheral in indirect mode and busy */
<> 144:ef7eb2e8f9f7 108 HAL_QSPI_STATE_BUSY_INDIRECT_TX = 0x12U, /*!< Peripheral in indirect mode with transmission ongoing */
<> 144:ef7eb2e8f9f7 109 HAL_QSPI_STATE_BUSY_INDIRECT_RX = 0x22U, /*!< Peripheral in indirect mode with reception ongoing */
<> 144:ef7eb2e8f9f7 110 HAL_QSPI_STATE_BUSY_AUTO_POLLING = 0x42U, /*!< Peripheral in auto polling mode ongoing */
<> 144:ef7eb2e8f9f7 111 HAL_QSPI_STATE_BUSY_MEM_MAPPED = 0x82U, /*!< Peripheral in memory mapped mode ongoing */
<> 144:ef7eb2e8f9f7 112 HAL_QSPI_STATE_ABORT = 0x08U, /*!< Peripheral with abort request ongoing */
<> 144:ef7eb2e8f9f7 113 HAL_QSPI_STATE_ERROR = 0x04U /*!< Peripheral in error */
<> 144:ef7eb2e8f9f7 114 }HAL_QSPI_StateTypeDef;
<> 144:ef7eb2e8f9f7 115
<> 144:ef7eb2e8f9f7 116 /**
<> 144:ef7eb2e8f9f7 117 * @brief QSPI Handle Structure definition
<> 144:ef7eb2e8f9f7 118 */
<> 144:ef7eb2e8f9f7 119 typedef struct
<> 144:ef7eb2e8f9f7 120 {
<> 144:ef7eb2e8f9f7 121 QUADSPI_TypeDef *Instance; /* QSPI registers base address */
<> 144:ef7eb2e8f9f7 122 QSPI_InitTypeDef Init; /* QSPI communication parameters */
<> 144:ef7eb2e8f9f7 123 uint8_t *pTxBuffPtr; /* Pointer to QSPI Tx transfer Buffer */
AnnaBridge 167:e84263d55307 124 __IO uint32_t TxXferSize; /* QSPI Tx Transfer size */
AnnaBridge 167:e84263d55307 125 __IO uint32_t TxXferCount; /* QSPI Tx Transfer Counter */
<> 144:ef7eb2e8f9f7 126 uint8_t *pRxBuffPtr; /* Pointer to QSPI Rx transfer Buffer */
AnnaBridge 167:e84263d55307 127 __IO uint32_t RxXferSize; /* QSPI Rx Transfer size */
AnnaBridge 167:e84263d55307 128 __IO uint32_t RxXferCount; /* QSPI Rx Transfer Counter */
<> 144:ef7eb2e8f9f7 129 DMA_HandleTypeDef *hdma; /* QSPI Rx/Tx DMA Handle parameters */
<> 144:ef7eb2e8f9f7 130 __IO HAL_LockTypeDef Lock; /* Locking object */
<> 144:ef7eb2e8f9f7 131 __IO HAL_QSPI_StateTypeDef State; /* QSPI communication state */
<> 144:ef7eb2e8f9f7 132 __IO uint32_t ErrorCode; /* QSPI Error code */
<> 144:ef7eb2e8f9f7 133 uint32_t Timeout; /* Timeout for the QSPI memory access */
<> 144:ef7eb2e8f9f7 134 }QSPI_HandleTypeDef;
<> 144:ef7eb2e8f9f7 135
<> 144:ef7eb2e8f9f7 136 /**
<> 144:ef7eb2e8f9f7 137 * @brief QSPI Command structure definition
<> 144:ef7eb2e8f9f7 138 */
<> 144:ef7eb2e8f9f7 139 typedef struct
<> 144:ef7eb2e8f9f7 140 {
<> 144:ef7eb2e8f9f7 141 uint32_t Instruction; /* Specifies the Instruction to be sent
<> 144:ef7eb2e8f9f7 142 This parameter can be a value (8-bit) between 0x00 and 0xFF */
<> 144:ef7eb2e8f9f7 143 uint32_t Address; /* Specifies the Address to be sent (Size from 1 to 4 bytes according AddressSize)
<> 144:ef7eb2e8f9f7 144 This parameter can be a value (32-bits) between 0x0 and 0xFFFFFFFFU */
<> 144:ef7eb2e8f9f7 145 uint32_t AlternateBytes; /* Specifies the Alternate Bytes to be sent (Size from 1 to 4 bytes according AlternateBytesSize)
<> 144:ef7eb2e8f9f7 146 This parameter can be a value (32-bits) between 0x0 and 0xFFFFFFFFU */
<> 144:ef7eb2e8f9f7 147 uint32_t AddressSize; /* Specifies the Address Size
<> 144:ef7eb2e8f9f7 148 This parameter can be a value of @ref QSPI_AddressSize */
<> 144:ef7eb2e8f9f7 149 uint32_t AlternateBytesSize; /* Specifies the Alternate Bytes Size
<> 144:ef7eb2e8f9f7 150 This parameter can be a value of @ref QSPI_AlternateBytesSize */
<> 144:ef7eb2e8f9f7 151 uint32_t DummyCycles; /* Specifies the Number of Dummy Cycles.
<> 144:ef7eb2e8f9f7 152 This parameter can be a number between 0 and 31 */
<> 144:ef7eb2e8f9f7 153 uint32_t InstructionMode; /* Specifies the Instruction Mode
<> 144:ef7eb2e8f9f7 154 This parameter can be a value of @ref QSPI_InstructionMode */
<> 144:ef7eb2e8f9f7 155 uint32_t AddressMode; /* Specifies the Address Mode
<> 144:ef7eb2e8f9f7 156 This parameter can be a value of @ref QSPI_AddressMode */
<> 144:ef7eb2e8f9f7 157 uint32_t AlternateByteMode; /* Specifies the Alternate Bytes Mode
<> 144:ef7eb2e8f9f7 158 This parameter can be a value of @ref QSPI_AlternateBytesMode */
<> 144:ef7eb2e8f9f7 159 uint32_t DataMode; /* Specifies the Data Mode (used for dummy cycles and data phases)
<> 144:ef7eb2e8f9f7 160 This parameter can be a value of @ref QSPI_DataMode */
<> 144:ef7eb2e8f9f7 161 uint32_t NbData; /* Specifies the number of data to transfer.
<> 144:ef7eb2e8f9f7 162 This parameter can be any value between 0 and 0xFFFFFFFFU (0 means undefined length
<> 144:ef7eb2e8f9f7 163 until end of memory)*/
<> 144:ef7eb2e8f9f7 164 uint32_t DdrMode; /* Specifies the double data rate mode for address, alternate byte and data phase
<> 144:ef7eb2e8f9f7 165 This parameter can be a value of @ref QSPI_DdrMode */
<> 144:ef7eb2e8f9f7 166 uint32_t DdrHoldHalfCycle; /* Specifies the DDR hold half cycle. It delays the data output by one half of
<> 144:ef7eb2e8f9f7 167 system clock in DDR mode.
<> 144:ef7eb2e8f9f7 168 This parameter can be a value of @ref QSPI_DdrHoldHalfCycle */
<> 144:ef7eb2e8f9f7 169 uint32_t SIOOMode; /* Specifies the send instruction only once mode
<> 144:ef7eb2e8f9f7 170 This parameter can be a value of @ref QSPI_SIOOMode */
<> 144:ef7eb2e8f9f7 171 }QSPI_CommandTypeDef;
<> 144:ef7eb2e8f9f7 172
<> 144:ef7eb2e8f9f7 173 /**
<> 144:ef7eb2e8f9f7 174 * @brief QSPI Auto Polling mode configuration structure definition
<> 144:ef7eb2e8f9f7 175 */
<> 144:ef7eb2e8f9f7 176 typedef struct
<> 144:ef7eb2e8f9f7 177 {
<> 144:ef7eb2e8f9f7 178 uint32_t Match; /* Specifies the value to be compared with the masked status register to get a match.
<> 144:ef7eb2e8f9f7 179 This parameter can be any value between 0 and 0xFFFFFFFFU */
<> 144:ef7eb2e8f9f7 180 uint32_t Mask; /* Specifies the mask to be applied to the status bytes received.
<> 144:ef7eb2e8f9f7 181 This parameter can be any value between 0 and 0xFFFFFFFFU */
<> 144:ef7eb2e8f9f7 182 uint32_t Interval; /* Specifies the number of clock cycles between two read during automatic polling phases.
<> 144:ef7eb2e8f9f7 183 This parameter can be any value between 0 and 0xFFFFU */
<> 144:ef7eb2e8f9f7 184 uint32_t StatusBytesSize; /* Specifies the size of the status bytes received.
<> 144:ef7eb2e8f9f7 185 This parameter can be any value between 1 and 4 */
<> 144:ef7eb2e8f9f7 186 uint32_t MatchMode; /* Specifies the method used for determining a match.
<> 144:ef7eb2e8f9f7 187 This parameter can be a value of @ref QSPI_MatchMode */
<> 144:ef7eb2e8f9f7 188 uint32_t AutomaticStop; /* Specifies if automatic polling is stopped after a match.
<> 144:ef7eb2e8f9f7 189 This parameter can be a value of @ref QSPI_AutomaticStop */
<> 144:ef7eb2e8f9f7 190 }QSPI_AutoPollingTypeDef;
<> 144:ef7eb2e8f9f7 191
<> 144:ef7eb2e8f9f7 192 /**
<> 144:ef7eb2e8f9f7 193 * @brief QSPI Memory Mapped mode configuration structure definition
<> 144:ef7eb2e8f9f7 194 */
<> 144:ef7eb2e8f9f7 195 typedef struct
<> 144:ef7eb2e8f9f7 196 {
<> 144:ef7eb2e8f9f7 197 uint32_t TimeOutPeriod; /* Specifies the number of clock to wait when the FIFO is full before to release the chip select.
<> 144:ef7eb2e8f9f7 198 This parameter can be any value between 0 and 0xFFFFU */
<> 144:ef7eb2e8f9f7 199 uint32_t TimeOutActivation; /* Specifies if the time out counter is enabled to release the chip select.
<> 144:ef7eb2e8f9f7 200 This parameter can be a value of @ref QSPI_TimeOutActivation */
<> 144:ef7eb2e8f9f7 201 }QSPI_MemoryMappedTypeDef;
<> 144:ef7eb2e8f9f7 202 /**
<> 144:ef7eb2e8f9f7 203 * @}
<> 144:ef7eb2e8f9f7 204 */
<> 144:ef7eb2e8f9f7 205
<> 144:ef7eb2e8f9f7 206 /* Exported constants --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 207 /** @defgroup QSPI_Exported_Constants QSPI Exported Constants
<> 144:ef7eb2e8f9f7 208 * @{
<> 144:ef7eb2e8f9f7 209 */
<> 144:ef7eb2e8f9f7 210 /** @defgroup QSPI_ErrorCode QSPI Error Code
<> 144:ef7eb2e8f9f7 211 * @{
<> 144:ef7eb2e8f9f7 212 */
AnnaBridge 167:e84263d55307 213 #define HAL_QSPI_ERROR_NONE 0x00000000U /*!< No error */
AnnaBridge 167:e84263d55307 214 #define HAL_QSPI_ERROR_TIMEOUT 0x00000001U /*!< Timeout error */
AnnaBridge 167:e84263d55307 215 #define HAL_QSPI_ERROR_TRANSFER 0x00000002U /*!< Transfer error */
AnnaBridge 167:e84263d55307 216 #define HAL_QSPI_ERROR_DMA 0x00000004U /*!< DMA transfer error */
AnnaBridge 167:e84263d55307 217 #define HAL_QSPI_ERROR_INVALID_PARAM 0x00000008U /*!< Invalid parameters error */
<> 144:ef7eb2e8f9f7 218 /**
<> 144:ef7eb2e8f9f7 219 * @}
<> 144:ef7eb2e8f9f7 220 */
<> 144:ef7eb2e8f9f7 221
<> 144:ef7eb2e8f9f7 222 /** @defgroup QSPI_SampleShifting QSPI Sample Shifting
<> 144:ef7eb2e8f9f7 223 * @{
<> 144:ef7eb2e8f9f7 224 */
AnnaBridge 167:e84263d55307 225 #define QSPI_SAMPLE_SHIFTING_NONE 0x00000000U /*!<No clock cycle shift to sample data*/
<> 144:ef7eb2e8f9f7 226 #define QSPI_SAMPLE_SHIFTING_HALFCYCLE ((uint32_t)QUADSPI_CR_SSHIFT) /*!<1/2 clock cycle shift to sample data*/
<> 144:ef7eb2e8f9f7 227 /**
<> 144:ef7eb2e8f9f7 228 * @}
<> 144:ef7eb2e8f9f7 229 */
<> 144:ef7eb2e8f9f7 230
<> 144:ef7eb2e8f9f7 231 /** @defgroup QSPI_ChipSelectHighTime QSPI Chip Select High Time
<> 144:ef7eb2e8f9f7 232 * @{
<> 144:ef7eb2e8f9f7 233 */
AnnaBridge 167:e84263d55307 234 #define QSPI_CS_HIGH_TIME_1_CYCLE 0x00000000U /*!<nCS stay high for at least 1 clock cycle between commands*/
<> 144:ef7eb2e8f9f7 235 #define QSPI_CS_HIGH_TIME_2_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_0) /*!<nCS stay high for at least 2 clock cycles between commands*/
<> 144:ef7eb2e8f9f7 236 #define QSPI_CS_HIGH_TIME_3_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_1) /*!<nCS stay high for at least 3 clock cycles between commands*/
<> 144:ef7eb2e8f9f7 237 #define QSPI_CS_HIGH_TIME_4_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_0 | QUADSPI_DCR_CSHT_1) /*!<nCS stay high for at least 4 clock cycles between commands*/
<> 144:ef7eb2e8f9f7 238 #define QSPI_CS_HIGH_TIME_5_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2) /*!<nCS stay high for at least 5 clock cycles between commands*/
<> 144:ef7eb2e8f9f7 239 #define QSPI_CS_HIGH_TIME_6_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2 | QUADSPI_DCR_CSHT_0) /*!<nCS stay high for at least 6 clock cycles between commands*/
<> 144:ef7eb2e8f9f7 240 #define QSPI_CS_HIGH_TIME_7_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2 | QUADSPI_DCR_CSHT_1) /*!<nCS stay high for at least 7 clock cycles between commands*/
<> 144:ef7eb2e8f9f7 241 #define QSPI_CS_HIGH_TIME_8_CYCLE ((uint32_t)QUADSPI_DCR_CSHT) /*!<nCS stay high for at least 8 clock cycles between commands*/
<> 144:ef7eb2e8f9f7 242 /**
<> 144:ef7eb2e8f9f7 243 * @}
<> 144:ef7eb2e8f9f7 244 */
<> 144:ef7eb2e8f9f7 245
<> 144:ef7eb2e8f9f7 246 /** @defgroup QSPI_ClockMode QSPI Clock Mode
<> 144:ef7eb2e8f9f7 247 * @{
<> 144:ef7eb2e8f9f7 248 */
AnnaBridge 167:e84263d55307 249 #define QSPI_CLOCK_MODE_0 0x00000000U /*!<Clk stays low while nCS is released*/
<> 144:ef7eb2e8f9f7 250 #define QSPI_CLOCK_MODE_3 ((uint32_t)QUADSPI_DCR_CKMODE) /*!<Clk goes high while nCS is released*/
<> 144:ef7eb2e8f9f7 251 /**
<> 144:ef7eb2e8f9f7 252 * @}
<> 144:ef7eb2e8f9f7 253 */
<> 144:ef7eb2e8f9f7 254
<> 144:ef7eb2e8f9f7 255 /** @defgroup QSPI_Flash_Select QSPI Flash Select
<> 144:ef7eb2e8f9f7 256 * @{
<> 144:ef7eb2e8f9f7 257 */
AnnaBridge 167:e84263d55307 258 #define QSPI_FLASH_ID_1 0x00000000U
<> 144:ef7eb2e8f9f7 259 #define QSPI_FLASH_ID_2 ((uint32_t)QUADSPI_CR_FSEL)
<> 144:ef7eb2e8f9f7 260 /**
<> 144:ef7eb2e8f9f7 261 * @}
<> 144:ef7eb2e8f9f7 262 */
<> 144:ef7eb2e8f9f7 263
<> 144:ef7eb2e8f9f7 264 /** @defgroup QSPI_DualFlash_Mode QSPI Dual Flash Mode
<> 144:ef7eb2e8f9f7 265 * @{
<> 144:ef7eb2e8f9f7 266 */
<> 144:ef7eb2e8f9f7 267 #define QSPI_DUALFLASH_ENABLE ((uint32_t)QUADSPI_CR_DFM)
AnnaBridge 167:e84263d55307 268 #define QSPI_DUALFLASH_DISABLE 0x00000000U
<> 144:ef7eb2e8f9f7 269 /**
<> 144:ef7eb2e8f9f7 270 * @}
<> 144:ef7eb2e8f9f7 271 */
<> 144:ef7eb2e8f9f7 272
<> 144:ef7eb2e8f9f7 273 /** @defgroup QSPI_AddressSize QSPI Address Size
<> 144:ef7eb2e8f9f7 274 * @{
<> 144:ef7eb2e8f9f7 275 */
AnnaBridge 167:e84263d55307 276 #define QSPI_ADDRESS_8_BITS 0x00000000U /*!<8-bit address*/
<> 144:ef7eb2e8f9f7 277 #define QSPI_ADDRESS_16_BITS ((uint32_t)QUADSPI_CCR_ADSIZE_0) /*!<16-bit address*/
<> 144:ef7eb2e8f9f7 278 #define QSPI_ADDRESS_24_BITS ((uint32_t)QUADSPI_CCR_ADSIZE_1) /*!<24-bit address*/
<> 144:ef7eb2e8f9f7 279 #define QSPI_ADDRESS_32_BITS ((uint32_t)QUADSPI_CCR_ADSIZE) /*!<32-bit address*/
<> 144:ef7eb2e8f9f7 280 /**
<> 144:ef7eb2e8f9f7 281 * @}
<> 144:ef7eb2e8f9f7 282 */
<> 144:ef7eb2e8f9f7 283
<> 144:ef7eb2e8f9f7 284 /** @defgroup QSPI_AlternateBytesSize QSPI Alternate Bytes Size
<> 144:ef7eb2e8f9f7 285 * @{
<> 144:ef7eb2e8f9f7 286 */
AnnaBridge 167:e84263d55307 287 #define QSPI_ALTERNATE_BYTES_8_BITS 0x00000000U /*!<8-bit alternate bytes*/
<> 144:ef7eb2e8f9f7 288 #define QSPI_ALTERNATE_BYTES_16_BITS ((uint32_t)QUADSPI_CCR_ABSIZE_0) /*!<16-bit alternate bytes*/
<> 144:ef7eb2e8f9f7 289 #define QSPI_ALTERNATE_BYTES_24_BITS ((uint32_t)QUADSPI_CCR_ABSIZE_1) /*!<24-bit alternate bytes*/
<> 144:ef7eb2e8f9f7 290 #define QSPI_ALTERNATE_BYTES_32_BITS ((uint32_t)QUADSPI_CCR_ABSIZE) /*!<32-bit alternate bytes*/
<> 144:ef7eb2e8f9f7 291 /**
<> 144:ef7eb2e8f9f7 292 * @}
<> 144:ef7eb2e8f9f7 293 */
<> 144:ef7eb2e8f9f7 294
<> 144:ef7eb2e8f9f7 295 /** @defgroup QSPI_InstructionMode QSPI Instruction Mode
<> 144:ef7eb2e8f9f7 296 * @{
<> 144:ef7eb2e8f9f7 297 */
AnnaBridge 167:e84263d55307 298 #define QSPI_INSTRUCTION_NONE 0x00000000U /*!<No instruction*/
<> 144:ef7eb2e8f9f7 299 #define QSPI_INSTRUCTION_1_LINE ((uint32_t)QUADSPI_CCR_IMODE_0) /*!<Instruction on a single line*/
<> 144:ef7eb2e8f9f7 300 #define QSPI_INSTRUCTION_2_LINES ((uint32_t)QUADSPI_CCR_IMODE_1) /*!<Instruction on two lines*/
<> 144:ef7eb2e8f9f7 301 #define QSPI_INSTRUCTION_4_LINES ((uint32_t)QUADSPI_CCR_IMODE) /*!<Instruction on four lines*/
<> 144:ef7eb2e8f9f7 302 /**
<> 144:ef7eb2e8f9f7 303 * @}
<> 144:ef7eb2e8f9f7 304 */
<> 144:ef7eb2e8f9f7 305
<> 144:ef7eb2e8f9f7 306 /** @defgroup QSPI_AddressMode QSPI Address Mode
<> 144:ef7eb2e8f9f7 307 * @{
<> 144:ef7eb2e8f9f7 308 */
AnnaBridge 167:e84263d55307 309 #define QSPI_ADDRESS_NONE 0x00000000U /*!<No address*/
<> 144:ef7eb2e8f9f7 310 #define QSPI_ADDRESS_1_LINE ((uint32_t)QUADSPI_CCR_ADMODE_0) /*!<Address on a single line*/
<> 144:ef7eb2e8f9f7 311 #define QSPI_ADDRESS_2_LINES ((uint32_t)QUADSPI_CCR_ADMODE_1) /*!<Address on two lines*/
<> 144:ef7eb2e8f9f7 312 #define QSPI_ADDRESS_4_LINES ((uint32_t)QUADSPI_CCR_ADMODE) /*!<Address on four lines*/
<> 144:ef7eb2e8f9f7 313 /**
<> 144:ef7eb2e8f9f7 314 * @}
<> 144:ef7eb2e8f9f7 315 */
<> 144:ef7eb2e8f9f7 316
<> 144:ef7eb2e8f9f7 317 /** @defgroup QSPI_AlternateBytesMode QSPI Alternate Bytes Mode
<> 144:ef7eb2e8f9f7 318 * @{
<> 144:ef7eb2e8f9f7 319 */
AnnaBridge 167:e84263d55307 320 #define QSPI_ALTERNATE_BYTES_NONE 0x00000000U /*!<No alternate bytes*/
<> 144:ef7eb2e8f9f7 321 #define QSPI_ALTERNATE_BYTES_1_LINE ((uint32_t)QUADSPI_CCR_ABMODE_0) /*!<Alternate bytes on a single line*/
<> 144:ef7eb2e8f9f7 322 #define QSPI_ALTERNATE_BYTES_2_LINES ((uint32_t)QUADSPI_CCR_ABMODE_1) /*!<Alternate bytes on two lines*/
<> 144:ef7eb2e8f9f7 323 #define QSPI_ALTERNATE_BYTES_4_LINES ((uint32_t)QUADSPI_CCR_ABMODE) /*!<Alternate bytes on four lines*/
<> 144:ef7eb2e8f9f7 324 /**
<> 144:ef7eb2e8f9f7 325 * @}
<> 144:ef7eb2e8f9f7 326 */
<> 144:ef7eb2e8f9f7 327
<> 144:ef7eb2e8f9f7 328 /** @defgroup QSPI_DataMode QSPI Data Mode
<> 144:ef7eb2e8f9f7 329 * @{
<> 144:ef7eb2e8f9f7 330 */
AnnaBridge 167:e84263d55307 331 #define QSPI_DATA_NONE 0x00000000U /*!<No data*/
<> 144:ef7eb2e8f9f7 332 #define QSPI_DATA_1_LINE ((uint32_t)QUADSPI_CCR_DMODE_0) /*!<Data on a single line*/
<> 144:ef7eb2e8f9f7 333 #define QSPI_DATA_2_LINES ((uint32_t)QUADSPI_CCR_DMODE_1) /*!<Data on two lines*/
<> 144:ef7eb2e8f9f7 334 #define QSPI_DATA_4_LINES ((uint32_t)QUADSPI_CCR_DMODE) /*!<Data on four lines*/
<> 144:ef7eb2e8f9f7 335 /**
<> 144:ef7eb2e8f9f7 336 * @}
<> 144:ef7eb2e8f9f7 337 */
<> 144:ef7eb2e8f9f7 338
<> 144:ef7eb2e8f9f7 339 /** @defgroup QSPI_DdrMode QSPI Ddr Mode
<> 144:ef7eb2e8f9f7 340 * @{
<> 144:ef7eb2e8f9f7 341 */
AnnaBridge 167:e84263d55307 342 #define QSPI_DDR_MODE_DISABLE 0x00000000U /*!<Double data rate mode disabled*/
<> 144:ef7eb2e8f9f7 343 #define QSPI_DDR_MODE_ENABLE ((uint32_t)QUADSPI_CCR_DDRM) /*!<Double data rate mode enabled*/
<> 144:ef7eb2e8f9f7 344 /**
<> 144:ef7eb2e8f9f7 345 * @}
<> 144:ef7eb2e8f9f7 346 */
<> 144:ef7eb2e8f9f7 347
<> 144:ef7eb2e8f9f7 348 /** @defgroup QSPI_DdrHoldHalfCycle QSPI Ddr HoldHalfCycle
<> 144:ef7eb2e8f9f7 349 * @{
<> 144:ef7eb2e8f9f7 350 */
AnnaBridge 167:e84263d55307 351 #define QSPI_DDR_HHC_ANALOG_DELAY 0x00000000U /*!<Delay the data output using analog delay in DDR mode*/
<> 144:ef7eb2e8f9f7 352 #define QSPI_DDR_HHC_HALF_CLK_DELAY ((uint32_t)QUADSPI_CCR_DHHC) /*!<Delay the data output by 1/2 clock cycle in DDR mode*/
<> 144:ef7eb2e8f9f7 353 /**
<> 144:ef7eb2e8f9f7 354 * @}
<> 144:ef7eb2e8f9f7 355 */
<> 144:ef7eb2e8f9f7 356
<> 144:ef7eb2e8f9f7 357 /** @defgroup QSPI_SIOOMode QSPI SIOO Mode
<> 144:ef7eb2e8f9f7 358 * @{
<> 144:ef7eb2e8f9f7 359 */
AnnaBridge 167:e84263d55307 360 #define QSPI_SIOO_INST_EVERY_CMD 0x00000000U /*!<Send instruction on every transaction*/
<> 144:ef7eb2e8f9f7 361 #define QSPI_SIOO_INST_ONLY_FIRST_CMD ((uint32_t)QUADSPI_CCR_SIOO) /*!<Send instruction only for the first command*/
<> 144:ef7eb2e8f9f7 362 /**
<> 144:ef7eb2e8f9f7 363 * @}
<> 144:ef7eb2e8f9f7 364 */
<> 144:ef7eb2e8f9f7 365
<> 144:ef7eb2e8f9f7 366 /** @defgroup QSPI_MatchMode QSPI Match Mode
<> 144:ef7eb2e8f9f7 367 * @{
<> 144:ef7eb2e8f9f7 368 */
AnnaBridge 167:e84263d55307 369 #define QSPI_MATCH_MODE_AND 0x00000000U /*!<AND match mode between unmasked bits*/
<> 144:ef7eb2e8f9f7 370 #define QSPI_MATCH_MODE_OR ((uint32_t)QUADSPI_CR_PMM) /*!<OR match mode between unmasked bits*/
<> 144:ef7eb2e8f9f7 371 /**
<> 144:ef7eb2e8f9f7 372 * @}
<> 144:ef7eb2e8f9f7 373 */
<> 144:ef7eb2e8f9f7 374
<> 144:ef7eb2e8f9f7 375 /** @defgroup QSPI_AutomaticStop QSPI Automatic Stop
<> 144:ef7eb2e8f9f7 376 * @{
<> 144:ef7eb2e8f9f7 377 */
AnnaBridge 167:e84263d55307 378 #define QSPI_AUTOMATIC_STOP_DISABLE 0x00000000U /*!<AutoPolling stops only with abort or QSPI disabling*/
<> 144:ef7eb2e8f9f7 379 #define QSPI_AUTOMATIC_STOP_ENABLE ((uint32_t)QUADSPI_CR_APMS) /*!<AutoPolling stops as soon as there is a match*/
<> 144:ef7eb2e8f9f7 380 /**
<> 144:ef7eb2e8f9f7 381 * @}
<> 144:ef7eb2e8f9f7 382 */
<> 144:ef7eb2e8f9f7 383
<> 144:ef7eb2e8f9f7 384 /** @defgroup QSPI_TimeOutActivation QSPI TimeOut Activation
<> 144:ef7eb2e8f9f7 385 * @{
<> 144:ef7eb2e8f9f7 386 */
AnnaBridge 167:e84263d55307 387 #define QSPI_TIMEOUT_COUNTER_DISABLE 0x00000000U /*!<Timeout counter disabled, nCS remains active*/
<> 144:ef7eb2e8f9f7 388 #define QSPI_TIMEOUT_COUNTER_ENABLE ((uint32_t)QUADSPI_CR_TCEN) /*!<Timeout counter enabled, nCS released when timeout expires*/
<> 144:ef7eb2e8f9f7 389 /**
<> 144:ef7eb2e8f9f7 390 * @}
<> 144:ef7eb2e8f9f7 391 */
<> 144:ef7eb2e8f9f7 392
<> 144:ef7eb2e8f9f7 393 /** @defgroup QSPI_Flags QSPI Flags
<> 144:ef7eb2e8f9f7 394 * @{
<> 144:ef7eb2e8f9f7 395 */
<> 144:ef7eb2e8f9f7 396 #define QSPI_FLAG_BUSY QUADSPI_SR_BUSY /*!<Busy flag: operation is ongoing*/
<> 144:ef7eb2e8f9f7 397 #define QSPI_FLAG_TO QUADSPI_SR_TOF /*!<Timeout flag: timeout occurs in memory-mapped mode*/
<> 144:ef7eb2e8f9f7 398 #define QSPI_FLAG_SM QUADSPI_SR_SMF /*!<Status match flag: received data matches in autopolling mode*/
<> 144:ef7eb2e8f9f7 399 #define QSPI_FLAG_FT QUADSPI_SR_FTF /*!<Fifo threshold flag: Fifo threshold reached or data left after read from memory is complete*/
<> 144:ef7eb2e8f9f7 400 #define QSPI_FLAG_TC QUADSPI_SR_TCF /*!<Transfer complete flag: programmed number of data have been transferred or the transfer has been aborted*/
<> 144:ef7eb2e8f9f7 401 #define QSPI_FLAG_TE QUADSPI_SR_TEF /*!<Transfer error flag: invalid address is being accessed*/
<> 144:ef7eb2e8f9f7 402 /**
<> 144:ef7eb2e8f9f7 403 * @}
<> 144:ef7eb2e8f9f7 404 */
<> 144:ef7eb2e8f9f7 405
<> 144:ef7eb2e8f9f7 406 /** @defgroup QSPI_Interrupts QSPI Interrupts
<> 144:ef7eb2e8f9f7 407 * @{
<> 144:ef7eb2e8f9f7 408 */
<> 144:ef7eb2e8f9f7 409 #define QSPI_IT_TO QUADSPI_CR_TOIE /*!<Interrupt on the timeout flag*/
<> 144:ef7eb2e8f9f7 410 #define QSPI_IT_SM QUADSPI_CR_SMIE /*!<Interrupt on the status match flag*/
<> 144:ef7eb2e8f9f7 411 #define QSPI_IT_FT QUADSPI_CR_FTIE /*!<Interrupt on the fifo threshold flag*/
<> 144:ef7eb2e8f9f7 412 #define QSPI_IT_TC QUADSPI_CR_TCIE /*!<Interrupt on the transfer complete flag*/
<> 144:ef7eb2e8f9f7 413 #define QSPI_IT_TE QUADSPI_CR_TEIE /*!<Interrupt on the transfer error flag*/
<> 144:ef7eb2e8f9f7 414 /**
<> 144:ef7eb2e8f9f7 415 * @}
<> 144:ef7eb2e8f9f7 416 */
<> 144:ef7eb2e8f9f7 417
<> 144:ef7eb2e8f9f7 418 /** @defgroup QSPI_Timeout_definition QSPI Timeout definition
<> 144:ef7eb2e8f9f7 419 * @{
<> 144:ef7eb2e8f9f7 420 */
AnnaBridge 167:e84263d55307 421 #define HAL_QPSI_TIMEOUT_DEFAULT_VALUE 5000U /* 5 s */
<> 144:ef7eb2e8f9f7 422 /**
<> 144:ef7eb2e8f9f7 423 * @}
<> 144:ef7eb2e8f9f7 424 */
<> 144:ef7eb2e8f9f7 425
<> 144:ef7eb2e8f9f7 426 /**
<> 144:ef7eb2e8f9f7 427 * @}
<> 144:ef7eb2e8f9f7 428 */
<> 144:ef7eb2e8f9f7 429
<> 144:ef7eb2e8f9f7 430 /* Exported macros -----------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 431 /** @defgroup QSPI_Exported_Macros QSPI Exported Macros
<> 144:ef7eb2e8f9f7 432 * @{
<> 144:ef7eb2e8f9f7 433 */
<> 144:ef7eb2e8f9f7 434
<> 144:ef7eb2e8f9f7 435 /** @brief Reset QSPI handle state
<> 144:ef7eb2e8f9f7 436 * @param __HANDLE__: QSPI handle.
<> 144:ef7eb2e8f9f7 437 * @retval None
<> 144:ef7eb2e8f9f7 438 */
<> 144:ef7eb2e8f9f7 439 #define __HAL_QSPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_QSPI_STATE_RESET)
<> 144:ef7eb2e8f9f7 440
<> 144:ef7eb2e8f9f7 441 /** @brief Enable QSPI
<> 144:ef7eb2e8f9f7 442 * @param __HANDLE__: specifies the QSPI Handle.
<> 144:ef7eb2e8f9f7 443 * @retval None
<> 144:ef7eb2e8f9f7 444 */
<> 144:ef7eb2e8f9f7 445 #define __HAL_QSPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN)
<> 144:ef7eb2e8f9f7 446
<> 144:ef7eb2e8f9f7 447 /** @brief Disable QSPI
<> 144:ef7eb2e8f9f7 448 * @param __HANDLE__: specifies the QSPI Handle.
<> 144:ef7eb2e8f9f7 449 * @retval None
<> 144:ef7eb2e8f9f7 450 */
<> 144:ef7eb2e8f9f7 451 #define __HAL_QSPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN)
<> 144:ef7eb2e8f9f7 452
<> 144:ef7eb2e8f9f7 453 /** @brief Enables the specified QSPI interrupt.
<> 144:ef7eb2e8f9f7 454 * @param __HANDLE__: specifies the QSPI Handle.
<> 144:ef7eb2e8f9f7 455 * @param __INTERRUPT__: specifies the QSPI interrupt source to enable.
<> 144:ef7eb2e8f9f7 456 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 457 * @arg QSPI_IT_TO: QSPI Time out interrupt
<> 144:ef7eb2e8f9f7 458 * @arg QSPI_IT_SM: QSPI Status match interrupt
<> 144:ef7eb2e8f9f7 459 * @arg QSPI_IT_FT: QSPI FIFO threshold interrupt
<> 144:ef7eb2e8f9f7 460 * @arg QSPI_IT_TC: QSPI Transfer complete interrupt
<> 144:ef7eb2e8f9f7 461 * @arg QSPI_IT_TE: QSPI Transfer error interrupt
<> 144:ef7eb2e8f9f7 462 * @retval None
<> 144:ef7eb2e8f9f7 463 */
<> 144:ef7eb2e8f9f7 464 #define __HAL_QSPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))
<> 144:ef7eb2e8f9f7 465
<> 144:ef7eb2e8f9f7 466
<> 144:ef7eb2e8f9f7 467 /** @brief Disables the specified QSPI interrupt.
<> 144:ef7eb2e8f9f7 468 * @param __HANDLE__: specifies the QSPI Handle.
<> 144:ef7eb2e8f9f7 469 * @param __INTERRUPT__: specifies the QSPI interrupt source to disable.
<> 144:ef7eb2e8f9f7 470 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 471 * @arg QSPI_IT_TO: QSPI Timeout interrupt
<> 144:ef7eb2e8f9f7 472 * @arg QSPI_IT_SM: QSPI Status match interrupt
<> 144:ef7eb2e8f9f7 473 * @arg QSPI_IT_FT: QSPI FIFO threshold interrupt
<> 144:ef7eb2e8f9f7 474 * @arg QSPI_IT_TC: QSPI Transfer complete interrupt
<> 144:ef7eb2e8f9f7 475 * @arg QSPI_IT_TE: QSPI Transfer error interrupt
<> 144:ef7eb2e8f9f7 476 * @retval None
<> 144:ef7eb2e8f9f7 477 */
<> 144:ef7eb2e8f9f7 478 #define __HAL_QSPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))
<> 144:ef7eb2e8f9f7 479
<> 144:ef7eb2e8f9f7 480 /** @brief Checks whether the specified QSPI interrupt source is enabled.
<> 144:ef7eb2e8f9f7 481 * @param __HANDLE__: specifies the QSPI Handle.
<> 144:ef7eb2e8f9f7 482 * @param __INTERRUPT__: specifies the QSPI interrupt source to check.
<> 144:ef7eb2e8f9f7 483 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 484 * @arg QSPI_IT_TO: QSPI Time out interrupt
<> 144:ef7eb2e8f9f7 485 * @arg QSPI_IT_SM: QSPI Status match interrupt
<> 144:ef7eb2e8f9f7 486 * @arg QSPI_IT_FT: QSPI FIFO threshold interrupt
<> 144:ef7eb2e8f9f7 487 * @arg QSPI_IT_TC: QSPI Transfer complete interrupt
<> 144:ef7eb2e8f9f7 488 * @arg QSPI_IT_TE: QSPI Transfer error interrupt
<> 144:ef7eb2e8f9f7 489 * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
<> 144:ef7eb2e8f9f7 490 */
<> 144:ef7eb2e8f9f7 491 #define __HAL_QSPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (READ_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) == (__INTERRUPT__))
<> 144:ef7eb2e8f9f7 492
<> 144:ef7eb2e8f9f7 493 /**
<> 144:ef7eb2e8f9f7 494 * @brief Get the selected QSPI's flag status.
<> 144:ef7eb2e8f9f7 495 * @param __HANDLE__: specifies the QSPI Handle.
<> 144:ef7eb2e8f9f7 496 * @param __FLAG__: specifies the QSPI flag to check.
<> 144:ef7eb2e8f9f7 497 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 498 * @arg QSPI_FLAG_BUSY: QSPI Busy flag
<> 144:ef7eb2e8f9f7 499 * @arg QSPI_FLAG_TO: QSPI Time out flag
<> 144:ef7eb2e8f9f7 500 * @arg QSPI_FLAG_SM: QSPI Status match flag
<> 144:ef7eb2e8f9f7 501 * @arg QSPI_FLAG_FT: QSPI FIFO threshold flag
<> 144:ef7eb2e8f9f7 502 * @arg QSPI_FLAG_TC: QSPI Transfer complete flag
<> 144:ef7eb2e8f9f7 503 * @arg QSPI_FLAG_TE: QSPI Transfer error flag
<> 144:ef7eb2e8f9f7 504 * @retval None
<> 144:ef7eb2e8f9f7 505 */
<> 144:ef7eb2e8f9f7 506 #define __HAL_QSPI_GET_FLAG(__HANDLE__, __FLAG__) (READ_BIT((__HANDLE__)->Instance->SR, (__FLAG__)) != 0U)
<> 144:ef7eb2e8f9f7 507
<> 144:ef7eb2e8f9f7 508 /** @brief Clears the specified QSPI's flag status.
<> 144:ef7eb2e8f9f7 509 * @param __HANDLE__: specifies the QSPI Handle.
<> 144:ef7eb2e8f9f7 510 * @param __FLAG__: specifies the QSPI clear register flag that needs to be set
<> 144:ef7eb2e8f9f7 511 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 512 * @arg QSPI_FLAG_TO: QSPI Time out flag
<> 144:ef7eb2e8f9f7 513 * @arg QSPI_FLAG_SM: QSPI Status match flag
<> 144:ef7eb2e8f9f7 514 * @arg QSPI_FLAG_TC: QSPI Transfer complete flag
<> 144:ef7eb2e8f9f7 515 * @arg QSPI_FLAG_TE: QSPI Transfer error flag
<> 144:ef7eb2e8f9f7 516 * @retval None
<> 144:ef7eb2e8f9f7 517 */
<> 144:ef7eb2e8f9f7 518 #define __HAL_QSPI_CLEAR_FLAG(__HANDLE__, __FLAG__) WRITE_REG((__HANDLE__)->Instance->FCR, (__FLAG__))
<> 144:ef7eb2e8f9f7 519 /**
<> 144:ef7eb2e8f9f7 520 * @}
<> 144:ef7eb2e8f9f7 521 */
<> 144:ef7eb2e8f9f7 522
<> 144:ef7eb2e8f9f7 523 /* Exported functions --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 524 /** @addtogroup QSPI_Exported_Functions
<> 144:ef7eb2e8f9f7 525 * @{
<> 144:ef7eb2e8f9f7 526 */
<> 144:ef7eb2e8f9f7 527
<> 144:ef7eb2e8f9f7 528 /** @addtogroup QSPI_Exported_Functions_Group1
<> 144:ef7eb2e8f9f7 529 * @{
<> 144:ef7eb2e8f9f7 530 */
<> 144:ef7eb2e8f9f7 531 /* Initialization/de-initialization functions ********************************/
<> 144:ef7eb2e8f9f7 532 HAL_StatusTypeDef HAL_QSPI_Init (QSPI_HandleTypeDef *hqspi);
<> 144:ef7eb2e8f9f7 533 HAL_StatusTypeDef HAL_QSPI_DeInit (QSPI_HandleTypeDef *hqspi);
<> 144:ef7eb2e8f9f7 534 void HAL_QSPI_MspInit (QSPI_HandleTypeDef *hqspi);
<> 144:ef7eb2e8f9f7 535 void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi);
<> 144:ef7eb2e8f9f7 536 /**
<> 144:ef7eb2e8f9f7 537 * @}
<> 144:ef7eb2e8f9f7 538 */
<> 144:ef7eb2e8f9f7 539
<> 144:ef7eb2e8f9f7 540 /** @addtogroup QSPI_Exported_Functions_Group2
<> 144:ef7eb2e8f9f7 541 * @{
<> 144:ef7eb2e8f9f7 542 */
<> 144:ef7eb2e8f9f7 543 /* IO operation functions *****************************************************/
<> 144:ef7eb2e8f9f7 544 /* QSPI IRQ handler method */
<> 144:ef7eb2e8f9f7 545 void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi);
<> 144:ef7eb2e8f9f7 546
<> 144:ef7eb2e8f9f7 547 /* QSPI indirect mode */
<> 144:ef7eb2e8f9f7 548 HAL_StatusTypeDef HAL_QSPI_Command (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t Timeout);
<> 144:ef7eb2e8f9f7 549 HAL_StatusTypeDef HAL_QSPI_Transmit (QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout);
<> 144:ef7eb2e8f9f7 550 HAL_StatusTypeDef HAL_QSPI_Receive (QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout);
<> 144:ef7eb2e8f9f7 551 HAL_StatusTypeDef HAL_QSPI_Command_IT (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd);
<> 144:ef7eb2e8f9f7 552 HAL_StatusTypeDef HAL_QSPI_Transmit_IT (QSPI_HandleTypeDef *hqspi, uint8_t *pData);
<> 144:ef7eb2e8f9f7 553 HAL_StatusTypeDef HAL_QSPI_Receive_IT (QSPI_HandleTypeDef *hqspi, uint8_t *pData);
<> 144:ef7eb2e8f9f7 554 HAL_StatusTypeDef HAL_QSPI_Transmit_DMA (QSPI_HandleTypeDef *hqspi, uint8_t *pData);
<> 144:ef7eb2e8f9f7 555 HAL_StatusTypeDef HAL_QSPI_Receive_DMA (QSPI_HandleTypeDef *hqspi, uint8_t *pData);
<> 144:ef7eb2e8f9f7 556
<> 144:ef7eb2e8f9f7 557 /* QSPI status flag polling mode */
<> 144:ef7eb2e8f9f7 558 HAL_StatusTypeDef HAL_QSPI_AutoPolling (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg, uint32_t Timeout);
<> 144:ef7eb2e8f9f7 559 HAL_StatusTypeDef HAL_QSPI_AutoPolling_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg);
<> 144:ef7eb2e8f9f7 560
<> 144:ef7eb2e8f9f7 561 /* QSPI memory-mapped mode */
<> 144:ef7eb2e8f9f7 562 HAL_StatusTypeDef HAL_QSPI_MemoryMapped(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_MemoryMappedTypeDef *cfg);
<> 144:ef7eb2e8f9f7 563 /**
<> 144:ef7eb2e8f9f7 564 * @}
<> 144:ef7eb2e8f9f7 565 */
<> 144:ef7eb2e8f9f7 566
<> 144:ef7eb2e8f9f7 567 /** @addtogroup QSPI_Exported_Functions_Group3
<> 144:ef7eb2e8f9f7 568 * @{
<> 144:ef7eb2e8f9f7 569 */
<> 144:ef7eb2e8f9f7 570 /* Callback functions in non-blocking modes ***********************************/
<> 144:ef7eb2e8f9f7 571 void HAL_QSPI_ErrorCallback (QSPI_HandleTypeDef *hqspi);
<> 144:ef7eb2e8f9f7 572 void HAL_QSPI_AbortCpltCallback (QSPI_HandleTypeDef *hqspi);
<> 144:ef7eb2e8f9f7 573 void HAL_QSPI_FifoThresholdCallback(QSPI_HandleTypeDef *hqspi);
<> 144:ef7eb2e8f9f7 574
<> 144:ef7eb2e8f9f7 575 /* QSPI indirect mode */
<> 144:ef7eb2e8f9f7 576 void HAL_QSPI_CmdCpltCallback (QSPI_HandleTypeDef *hqspi);
<> 144:ef7eb2e8f9f7 577 void HAL_QSPI_RxCpltCallback (QSPI_HandleTypeDef *hqspi);
<> 144:ef7eb2e8f9f7 578 void HAL_QSPI_TxCpltCallback (QSPI_HandleTypeDef *hqspi);
<> 144:ef7eb2e8f9f7 579 void HAL_QSPI_RxHalfCpltCallback (QSPI_HandleTypeDef *hqspi);
<> 144:ef7eb2e8f9f7 580 void HAL_QSPI_TxHalfCpltCallback (QSPI_HandleTypeDef *hqspi);
<> 144:ef7eb2e8f9f7 581
<> 144:ef7eb2e8f9f7 582 /* QSPI status flag polling mode */
<> 144:ef7eb2e8f9f7 583 void HAL_QSPI_StatusMatchCallback (QSPI_HandleTypeDef *hqspi);
<> 144:ef7eb2e8f9f7 584
<> 144:ef7eb2e8f9f7 585 /* QSPI memory-mapped mode */
<> 144:ef7eb2e8f9f7 586 void HAL_QSPI_TimeOutCallback (QSPI_HandleTypeDef *hqspi);
<> 144:ef7eb2e8f9f7 587 /**
<> 144:ef7eb2e8f9f7 588 * @}
<> 144:ef7eb2e8f9f7 589 */
<> 144:ef7eb2e8f9f7 590
<> 144:ef7eb2e8f9f7 591 /** @addtogroup QSPI_Exported_Functions_Group4
<> 144:ef7eb2e8f9f7 592 * @{
<> 144:ef7eb2e8f9f7 593 */
<> 144:ef7eb2e8f9f7 594 /* Peripheral Control and State functions ************************************/
<> 144:ef7eb2e8f9f7 595 HAL_QSPI_StateTypeDef HAL_QSPI_GetState (QSPI_HandleTypeDef *hqspi);
<> 144:ef7eb2e8f9f7 596 uint32_t HAL_QSPI_GetError (QSPI_HandleTypeDef *hqspi);
<> 144:ef7eb2e8f9f7 597 HAL_StatusTypeDef HAL_QSPI_Abort (QSPI_HandleTypeDef *hqspi);
<> 144:ef7eb2e8f9f7 598 HAL_StatusTypeDef HAL_QSPI_Abort_IT (QSPI_HandleTypeDef *hqspi);
<> 144:ef7eb2e8f9f7 599 void HAL_QSPI_SetTimeout (QSPI_HandleTypeDef *hqspi, uint32_t Timeout);
<> 144:ef7eb2e8f9f7 600 HAL_StatusTypeDef HAL_QSPI_SetFifoThreshold(QSPI_HandleTypeDef *hqspi, uint32_t Threshold);
<> 144:ef7eb2e8f9f7 601 uint32_t HAL_QSPI_GetFifoThreshold(QSPI_HandleTypeDef *hqspi);
<> 144:ef7eb2e8f9f7 602 /**
<> 144:ef7eb2e8f9f7 603 * @}
<> 144:ef7eb2e8f9f7 604 */
<> 144:ef7eb2e8f9f7 605
<> 144:ef7eb2e8f9f7 606 /* Private macros ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 607 /** @defgroup QSPI_Private_Macros QSPI Private Macros
<> 144:ef7eb2e8f9f7 608 * @{
<> 144:ef7eb2e8f9f7 609 */
<> 144:ef7eb2e8f9f7 610 /** @defgroup QSPI_ClockPrescaler QSPI Clock Prescaler
<> 144:ef7eb2e8f9f7 611 * @{
<> 144:ef7eb2e8f9f7 612 */
<> 144:ef7eb2e8f9f7 613 #define IS_QSPI_CLOCK_PRESCALER(PRESCALER) ((PRESCALER) <= 0xFFU)
<> 144:ef7eb2e8f9f7 614 /**
<> 144:ef7eb2e8f9f7 615 * @}
<> 144:ef7eb2e8f9f7 616 */
<> 144:ef7eb2e8f9f7 617
<> 144:ef7eb2e8f9f7 618 /** @defgroup QSPI_FifoThreshold QSPI Fifo Threshold
<> 144:ef7eb2e8f9f7 619 * @{
<> 144:ef7eb2e8f9f7 620 */
<> 144:ef7eb2e8f9f7 621 #define IS_QSPI_FIFO_THRESHOLD(THR) (((THR) > 0U) && ((THR) <= 32U))
<> 144:ef7eb2e8f9f7 622 /**
<> 144:ef7eb2e8f9f7 623 * @}
<> 144:ef7eb2e8f9f7 624 */
<> 144:ef7eb2e8f9f7 625
<> 144:ef7eb2e8f9f7 626 #define IS_QSPI_SSHIFT(SSHIFT) (((SSHIFT) == QSPI_SAMPLE_SHIFTING_NONE) || \
<> 144:ef7eb2e8f9f7 627 ((SSHIFT) == QSPI_SAMPLE_SHIFTING_HALFCYCLE))
<> 144:ef7eb2e8f9f7 628
<> 144:ef7eb2e8f9f7 629 /** @defgroup QSPI_FlashSize QSPI Flash Size
<> 144:ef7eb2e8f9f7 630 * @{
<> 144:ef7eb2e8f9f7 631 */
<> 144:ef7eb2e8f9f7 632 #define IS_QSPI_FLASH_SIZE(FSIZE) (((FSIZE) <= 31U))
<> 144:ef7eb2e8f9f7 633 /**
<> 144:ef7eb2e8f9f7 634 * @}
<> 144:ef7eb2e8f9f7 635 */
<> 144:ef7eb2e8f9f7 636
<> 144:ef7eb2e8f9f7 637 #define IS_QSPI_CS_HIGH_TIME(CSHTIME) (((CSHTIME) == QSPI_CS_HIGH_TIME_1_CYCLE) || \
<> 144:ef7eb2e8f9f7 638 ((CSHTIME) == QSPI_CS_HIGH_TIME_2_CYCLE) || \
<> 144:ef7eb2e8f9f7 639 ((CSHTIME) == QSPI_CS_HIGH_TIME_3_CYCLE) || \
<> 144:ef7eb2e8f9f7 640 ((CSHTIME) == QSPI_CS_HIGH_TIME_4_CYCLE) || \
<> 144:ef7eb2e8f9f7 641 ((CSHTIME) == QSPI_CS_HIGH_TIME_5_CYCLE) || \
<> 144:ef7eb2e8f9f7 642 ((CSHTIME) == QSPI_CS_HIGH_TIME_6_CYCLE) || \
<> 144:ef7eb2e8f9f7 643 ((CSHTIME) == QSPI_CS_HIGH_TIME_7_CYCLE) || \
<> 144:ef7eb2e8f9f7 644 ((CSHTIME) == QSPI_CS_HIGH_TIME_8_CYCLE))
<> 144:ef7eb2e8f9f7 645
<> 144:ef7eb2e8f9f7 646 #define IS_QSPI_CLOCK_MODE(CLKMODE) (((CLKMODE) == QSPI_CLOCK_MODE_0) || \
<> 144:ef7eb2e8f9f7 647 ((CLKMODE) == QSPI_CLOCK_MODE_3))
<> 144:ef7eb2e8f9f7 648
<> 144:ef7eb2e8f9f7 649 #define IS_QSPI_FLASH_ID(FLA) (((FLA) == QSPI_FLASH_ID_1) || \
<> 144:ef7eb2e8f9f7 650 ((FLA) == QSPI_FLASH_ID_2))
<> 144:ef7eb2e8f9f7 651
<> 144:ef7eb2e8f9f7 652 #define IS_QSPI_DUAL_FLASH_MODE(MODE) (((MODE) == QSPI_DUALFLASH_ENABLE) || \
<> 144:ef7eb2e8f9f7 653 ((MODE) == QSPI_DUALFLASH_DISABLE))
<> 144:ef7eb2e8f9f7 654
<> 144:ef7eb2e8f9f7 655
<> 144:ef7eb2e8f9f7 656 /** @defgroup QSPI_Instruction QSPI Instruction
<> 144:ef7eb2e8f9f7 657 * @{
<> 144:ef7eb2e8f9f7 658 */
<> 144:ef7eb2e8f9f7 659 #define IS_QSPI_INSTRUCTION(INSTRUCTION) ((INSTRUCTION) <= 0xFFU)
<> 144:ef7eb2e8f9f7 660 /**
<> 144:ef7eb2e8f9f7 661 * @}
<> 144:ef7eb2e8f9f7 662 */
<> 144:ef7eb2e8f9f7 663
<> 144:ef7eb2e8f9f7 664 #define IS_QSPI_ADDRESS_SIZE(ADDR_SIZE) (((ADDR_SIZE) == QSPI_ADDRESS_8_BITS) || \
<> 144:ef7eb2e8f9f7 665 ((ADDR_SIZE) == QSPI_ADDRESS_16_BITS) || \
<> 144:ef7eb2e8f9f7 666 ((ADDR_SIZE) == QSPI_ADDRESS_24_BITS) || \
<> 144:ef7eb2e8f9f7 667 ((ADDR_SIZE) == QSPI_ADDRESS_32_BITS))
<> 144:ef7eb2e8f9f7 668
<> 144:ef7eb2e8f9f7 669 #define IS_QSPI_ALTERNATE_BYTES_SIZE(SIZE) (((SIZE) == QSPI_ALTERNATE_BYTES_8_BITS) || \
<> 144:ef7eb2e8f9f7 670 ((SIZE) == QSPI_ALTERNATE_BYTES_16_BITS) || \
<> 144:ef7eb2e8f9f7 671 ((SIZE) == QSPI_ALTERNATE_BYTES_24_BITS) || \
<> 144:ef7eb2e8f9f7 672 ((SIZE) == QSPI_ALTERNATE_BYTES_32_BITS))
<> 144:ef7eb2e8f9f7 673
<> 144:ef7eb2e8f9f7 674
<> 144:ef7eb2e8f9f7 675 /** @defgroup QSPI_DummyCycles QSPI Dummy Cycles
<> 144:ef7eb2e8f9f7 676 * @{
<> 144:ef7eb2e8f9f7 677 */
<> 144:ef7eb2e8f9f7 678 #define IS_QSPI_DUMMY_CYCLES(DCY) ((DCY) <= 31U)
<> 144:ef7eb2e8f9f7 679 /**
<> 144:ef7eb2e8f9f7 680 * @}
<> 144:ef7eb2e8f9f7 681 */
<> 144:ef7eb2e8f9f7 682
<> 144:ef7eb2e8f9f7 683 #define IS_QSPI_INSTRUCTION_MODE(MODE) (((MODE) == QSPI_INSTRUCTION_NONE) || \
<> 144:ef7eb2e8f9f7 684 ((MODE) == QSPI_INSTRUCTION_1_LINE) || \
<> 144:ef7eb2e8f9f7 685 ((MODE) == QSPI_INSTRUCTION_2_LINES) || \
<> 144:ef7eb2e8f9f7 686 ((MODE) == QSPI_INSTRUCTION_4_LINES))
<> 144:ef7eb2e8f9f7 687
<> 144:ef7eb2e8f9f7 688 #define IS_QSPI_ADDRESS_MODE(MODE) (((MODE) == QSPI_ADDRESS_NONE) || \
<> 144:ef7eb2e8f9f7 689 ((MODE) == QSPI_ADDRESS_1_LINE) || \
<> 144:ef7eb2e8f9f7 690 ((MODE) == QSPI_ADDRESS_2_LINES) || \
<> 144:ef7eb2e8f9f7 691 ((MODE) == QSPI_ADDRESS_4_LINES))
<> 144:ef7eb2e8f9f7 692
<> 144:ef7eb2e8f9f7 693 #define IS_QSPI_ALTERNATE_BYTES_MODE(MODE) (((MODE) == QSPI_ALTERNATE_BYTES_NONE) || \
<> 144:ef7eb2e8f9f7 694 ((MODE) == QSPI_ALTERNATE_BYTES_1_LINE) || \
<> 144:ef7eb2e8f9f7 695 ((MODE) == QSPI_ALTERNATE_BYTES_2_LINES) || \
<> 144:ef7eb2e8f9f7 696 ((MODE) == QSPI_ALTERNATE_BYTES_4_LINES))
<> 144:ef7eb2e8f9f7 697
<> 144:ef7eb2e8f9f7 698 #define IS_QSPI_DATA_MODE(MODE) (((MODE) == QSPI_DATA_NONE) || \
<> 144:ef7eb2e8f9f7 699 ((MODE) == QSPI_DATA_1_LINE) || \
<> 144:ef7eb2e8f9f7 700 ((MODE) == QSPI_DATA_2_LINES) || \
<> 144:ef7eb2e8f9f7 701 ((MODE) == QSPI_DATA_4_LINES))
<> 144:ef7eb2e8f9f7 702
<> 144:ef7eb2e8f9f7 703 #define IS_QSPI_DDR_MODE(DDR_MODE) (((DDR_MODE) == QSPI_DDR_MODE_DISABLE) || \
<> 144:ef7eb2e8f9f7 704 ((DDR_MODE) == QSPI_DDR_MODE_ENABLE))
<> 144:ef7eb2e8f9f7 705
<> 144:ef7eb2e8f9f7 706 #define IS_QSPI_DDR_HHC(DDR_HHC) (((DDR_HHC) == QSPI_DDR_HHC_ANALOG_DELAY) || \
<> 144:ef7eb2e8f9f7 707 ((DDR_HHC) == QSPI_DDR_HHC_HALF_CLK_DELAY))
<> 144:ef7eb2e8f9f7 708
<> 144:ef7eb2e8f9f7 709 #define IS_QSPI_SIOO_MODE(SIOO_MODE) (((SIOO_MODE) == QSPI_SIOO_INST_EVERY_CMD) || \
<> 144:ef7eb2e8f9f7 710 ((SIOO_MODE) == QSPI_SIOO_INST_ONLY_FIRST_CMD))
<> 144:ef7eb2e8f9f7 711
<> 144:ef7eb2e8f9f7 712 /** @defgroup QSPI_Interval QSPI Interval
<> 144:ef7eb2e8f9f7 713 * @{
<> 144:ef7eb2e8f9f7 714 */
<> 144:ef7eb2e8f9f7 715 #define IS_QSPI_INTERVAL(INTERVAL) ((INTERVAL) <= QUADSPI_PIR_INTERVAL)
<> 144:ef7eb2e8f9f7 716 /**
<> 144:ef7eb2e8f9f7 717 * @}
<> 144:ef7eb2e8f9f7 718 */
<> 144:ef7eb2e8f9f7 719
<> 144:ef7eb2e8f9f7 720 /** @defgroup QSPI_StatusBytesSize QSPI Status Bytes Size
<> 144:ef7eb2e8f9f7 721 * @{
<> 144:ef7eb2e8f9f7 722 */
<> 144:ef7eb2e8f9f7 723 #define IS_QSPI_STATUS_BYTES_SIZE(SIZE) (((SIZE) >= 1U) && ((SIZE) <= 4U))
<> 144:ef7eb2e8f9f7 724 /**
<> 144:ef7eb2e8f9f7 725 * @}
<> 144:ef7eb2e8f9f7 726 */
<> 144:ef7eb2e8f9f7 727 #define IS_QSPI_MATCH_MODE(MODE) (((MODE) == QSPI_MATCH_MODE_AND) || \
<> 144:ef7eb2e8f9f7 728 ((MODE) == QSPI_MATCH_MODE_OR))
<> 144:ef7eb2e8f9f7 729
<> 144:ef7eb2e8f9f7 730 #define IS_QSPI_AUTOMATIC_STOP(APMS) (((APMS) == QSPI_AUTOMATIC_STOP_DISABLE) || \
<> 144:ef7eb2e8f9f7 731 ((APMS) == QSPI_AUTOMATIC_STOP_ENABLE))
<> 144:ef7eb2e8f9f7 732
<> 144:ef7eb2e8f9f7 733 #define IS_QSPI_TIMEOUT_ACTIVATION(TCEN) (((TCEN) == QSPI_TIMEOUT_COUNTER_DISABLE) || \
<> 144:ef7eb2e8f9f7 734 ((TCEN) == QSPI_TIMEOUT_COUNTER_ENABLE))
<> 144:ef7eb2e8f9f7 735
<> 144:ef7eb2e8f9f7 736 /** @defgroup QSPI_TimeOutPeriod QSPI TimeOut Period
<> 144:ef7eb2e8f9f7 737 * @{
<> 144:ef7eb2e8f9f7 738 */
<> 144:ef7eb2e8f9f7 739 #define IS_QSPI_TIMEOUT_PERIOD(PERIOD) ((PERIOD) <= 0xFFFFU)
<> 144:ef7eb2e8f9f7 740 /**
<> 144:ef7eb2e8f9f7 741 * @}
<> 144:ef7eb2e8f9f7 742 */
<> 144:ef7eb2e8f9f7 743
<> 144:ef7eb2e8f9f7 744 #define IS_QSPI_GET_FLAG(FLAG) (((FLAG) == QSPI_FLAG_BUSY) || \
<> 144:ef7eb2e8f9f7 745 ((FLAG) == QSPI_FLAG_TO) || \
<> 144:ef7eb2e8f9f7 746 ((FLAG) == QSPI_FLAG_SM) || \
<> 144:ef7eb2e8f9f7 747 ((FLAG) == QSPI_FLAG_FT) || \
<> 144:ef7eb2e8f9f7 748 ((FLAG) == QSPI_FLAG_TC) || \
<> 144:ef7eb2e8f9f7 749 ((FLAG) == QSPI_FLAG_TE))
<> 144:ef7eb2e8f9f7 750
AnnaBridge 167:e84263d55307 751 #define IS_QSPI_IT(IT) ((((IT) & 0xFFE0FFFFU) == 0x00000000U) && ((IT) != 0x00000000U))
<> 144:ef7eb2e8f9f7 752 /**
<> 144:ef7eb2e8f9f7 753 * @}
<> 144:ef7eb2e8f9f7 754 */
<> 144:ef7eb2e8f9f7 755
<> 144:ef7eb2e8f9f7 756 /* Private functions ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 757 /** @defgroup QSPI_Private_Functions QSPI Private Functions
<> 144:ef7eb2e8f9f7 758 * @{
<> 144:ef7eb2e8f9f7 759 */
<> 144:ef7eb2e8f9f7 760
<> 144:ef7eb2e8f9f7 761 /**
<> 144:ef7eb2e8f9f7 762 * @}
<> 144:ef7eb2e8f9f7 763 */
<> 144:ef7eb2e8f9f7 764
<> 144:ef7eb2e8f9f7 765 /**
<> 144:ef7eb2e8f9f7 766 * @}
<> 144:ef7eb2e8f9f7 767 */
<> 144:ef7eb2e8f9f7 768
<> 144:ef7eb2e8f9f7 769 /**
<> 144:ef7eb2e8f9f7 770 * @}
<> 144:ef7eb2e8f9f7 771 */
<> 144:ef7eb2e8f9f7 772
<> 144:ef7eb2e8f9f7 773 /**
<> 144:ef7eb2e8f9f7 774 * @}
<> 144:ef7eb2e8f9f7 775 */
AnnaBridge 167:e84263d55307 776 #endif /* STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || STM32F412Rx ||
AnnaBridge 167:e84263d55307 777 STM32F413xx || STM32F423xx */
<> 144:ef7eb2e8f9f7 778
<> 144:ef7eb2e8f9f7 779 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 780 }
<> 144:ef7eb2e8f9f7 781 #endif
<> 144:ef7eb2e8f9f7 782
<> 144:ef7eb2e8f9f7 783 #endif /* __STM32F4xx_HAL_QSPI_H */
<> 144:ef7eb2e8f9f7 784
<> 144:ef7eb2e8f9f7 785 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/