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targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/spi_api.c@167:e84263d55307, 2017-06-21 (annotated)

Committer:
AnnaBridge
Date:
Wed Jun 21 17:46:44 2017 +0100
Revision:
167:e84263d55307
Parent:
154:37f96f9d4de2
Child:
170:19eb464bc2be
This updates the lib to the mbed lib v 145

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 154:37f96f9d4de2 1 /* mbed Microcontroller Library
<> 154:37f96f9d4de2 2 * Copyright (c) 2013 ARM Limited
<> 154:37f96f9d4de2 3 *
<> 154:37f96f9d4de2 4 * Licensed under the Apache License, Version 2.0 (the "License");
<> 154:37f96f9d4de2 5 * you may not use this file except in compliance with the License.
<> 154:37f96f9d4de2 6 * You may obtain a copy of the License at
<> 154:37f96f9d4de2 7 *
<> 154:37f96f9d4de2 8 * http://www.apache.org/licenses/LICENSE-2.0
<> 154:37f96f9d4de2 9 *
<> 154:37f96f9d4de2 10 * Unless required by applicable law or agreed to in writing, software
<> 154:37f96f9d4de2 11 * distributed under the License is distributed on an "AS IS" BASIS,
<> 154:37f96f9d4de2 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
<> 154:37f96f9d4de2 13 * See the License for the specific language governing permissions and
<> 154:37f96f9d4de2 14 * limitations under the License.
<> 154:37f96f9d4de2 15 */
<> 154:37f96f9d4de2 16 #include <math.h>
<> 154:37f96f9d4de2 17 #include "mbed_assert.h"
<> 154:37f96f9d4de2 18
<> 154:37f96f9d4de2 19 #include "spi_api.h"
<> 154:37f96f9d4de2 20
<> 154:37f96f9d4de2 21 #if DEVICE_SPI
<> 154:37f96f9d4de2 22
<> 154:37f96f9d4de2 23 #include "cmsis.h"
<> 154:37f96f9d4de2 24 #include "pinmap.h"
<> 154:37f96f9d4de2 25 #include "mbed_error.h"
<> 154:37f96f9d4de2 26 #include "fsl_dspi.h"
<> 154:37f96f9d4de2 27 #include "peripheral_clock_defines.h"
<> 154:37f96f9d4de2 28 #include "PeripheralPins.h"
<> 154:37f96f9d4de2 29
<> 154:37f96f9d4de2 30 /* Array of SPI peripheral base address. */
<> 154:37f96f9d4de2 31 static SPI_Type *const spi_address[] = SPI_BASE_PTRS;
<> 154:37f96f9d4de2 32 /* Array of SPI bus clock frequencies */
<> 154:37f96f9d4de2 33 static clock_name_t const spi_clocks[] = SPI_CLOCK_FREQS;
<> 154:37f96f9d4de2 34
<> 154:37f96f9d4de2 35 void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel)
<> 154:37f96f9d4de2 36 {
<> 154:37f96f9d4de2 37 // determine the SPI to use
<> 154:37f96f9d4de2 38 uint32_t spi_mosi = pinmap_peripheral(mosi, PinMap_SPI_MOSI);
<> 154:37f96f9d4de2 39 uint32_t spi_miso = pinmap_peripheral(miso, PinMap_SPI_MISO);
<> 154:37f96f9d4de2 40 uint32_t spi_sclk = pinmap_peripheral(sclk, PinMap_SPI_SCLK);
<> 154:37f96f9d4de2 41 uint32_t spi_ssel = pinmap_peripheral(ssel, PinMap_SPI_SSEL);
<> 154:37f96f9d4de2 42 uint32_t spi_data = pinmap_merge(spi_mosi, spi_miso);
<> 154:37f96f9d4de2 43 uint32_t spi_cntl = pinmap_merge(spi_sclk, spi_ssel);
<> 154:37f96f9d4de2 44
<> 154:37f96f9d4de2 45 obj->instance = pinmap_merge(spi_data, spi_cntl);
<> 154:37f96f9d4de2 46 MBED_ASSERT((int)obj->instance != NC);
<> 154:37f96f9d4de2 47
<> 154:37f96f9d4de2 48 // pin out the spi pins
<> 154:37f96f9d4de2 49 pinmap_pinout(mosi, PinMap_SPI_MOSI);
<> 154:37f96f9d4de2 50 pinmap_pinout(miso, PinMap_SPI_MISO);
<> 154:37f96f9d4de2 51 pinmap_pinout(sclk, PinMap_SPI_SCLK);
<> 154:37f96f9d4de2 52 if (ssel != NC) {
<> 154:37f96f9d4de2 53 pinmap_pinout(ssel, PinMap_SPI_SSEL);
<> 154:37f96f9d4de2 54 }
<> 154:37f96f9d4de2 55 }
<> 154:37f96f9d4de2 56
<> 154:37f96f9d4de2 57 void spi_free(spi_t *obj)
<> 154:37f96f9d4de2 58 {
<> 154:37f96f9d4de2 59 DSPI_Deinit(spi_address[obj->instance]);
<> 154:37f96f9d4de2 60 }
<> 154:37f96f9d4de2 61
<> 154:37f96f9d4de2 62 void spi_format(spi_t *obj, int bits, int mode, int slave)
<> 154:37f96f9d4de2 63 {
<> 154:37f96f9d4de2 64
<> 154:37f96f9d4de2 65 dspi_master_config_t master_config;
<> 154:37f96f9d4de2 66 dspi_slave_config_t slave_config;
<> 154:37f96f9d4de2 67
<> 154:37f96f9d4de2 68 if (slave) {
<> 154:37f96f9d4de2 69 /* Slave config */
<> 154:37f96f9d4de2 70 DSPI_SlaveGetDefaultConfig(&slave_config);
<> 154:37f96f9d4de2 71 slave_config.whichCtar = kDSPI_Ctar0;
<> 154:37f96f9d4de2 72 slave_config.ctarConfig.bitsPerFrame = (uint32_t)bits;;
<> 154:37f96f9d4de2 73 slave_config.ctarConfig.cpol = (mode & 0x2) ? kDSPI_ClockPolarityActiveLow : kDSPI_ClockPolarityActiveHigh;
<> 154:37f96f9d4de2 74 slave_config.ctarConfig.cpha = (mode & 0x1) ? kDSPI_ClockPhaseSecondEdge : kDSPI_ClockPhaseFirstEdge;
<> 154:37f96f9d4de2 75
<> 154:37f96f9d4de2 76 DSPI_SlaveInit(spi_address[obj->instance], &slave_config);
<> 154:37f96f9d4de2 77 } else {
<> 154:37f96f9d4de2 78 /* Master config */
<> 154:37f96f9d4de2 79 DSPI_MasterGetDefaultConfig(&master_config);
<> 154:37f96f9d4de2 80 master_config.ctarConfig.bitsPerFrame = (uint32_t)bits;;
<> 154:37f96f9d4de2 81 master_config.ctarConfig.cpol = (mode & 0x2) ? kDSPI_ClockPolarityActiveLow : kDSPI_ClockPolarityActiveHigh;
<> 154:37f96f9d4de2 82 master_config.ctarConfig.cpha = (mode & 0x1) ? kDSPI_ClockPhaseSecondEdge : kDSPI_ClockPhaseFirstEdge;
<> 154:37f96f9d4de2 83 master_config.ctarConfig.direction = kDSPI_MsbFirst;
<> 154:37f96f9d4de2 84 master_config.ctarConfig.pcsToSckDelayInNanoSec = 0;
<> 154:37f96f9d4de2 85
<> 154:37f96f9d4de2 86 DSPI_MasterInit(spi_address[obj->instance], &master_config, CLOCK_GetFreq(spi_clocks[obj->instance]));
<> 154:37f96f9d4de2 87 }
<> 154:37f96f9d4de2 88 }
<> 154:37f96f9d4de2 89
<> 154:37f96f9d4de2 90 void spi_frequency(spi_t *obj, int hz)
<> 154:37f96f9d4de2 91 {
<> 154:37f96f9d4de2 92 uint32_t busClock = CLOCK_GetFreq(spi_clocks[obj->instance]);
<> 154:37f96f9d4de2 93 DSPI_MasterSetBaudRate(spi_address[obj->instance], kDSPI_Ctar0, (uint32_t)hz, busClock);
<> 154:37f96f9d4de2 94 //Half clock period delay after SPI transfer
<> 154:37f96f9d4de2 95 DSPI_MasterSetDelayTimes(spi_address[obj->instance], kDSPI_Ctar0, kDSPI_LastSckToPcs, busClock, 500000000 / hz);
<> 154:37f96f9d4de2 96 }
<> 154:37f96f9d4de2 97
<> 154:37f96f9d4de2 98 static inline int spi_readable(spi_t * obj)
<> 154:37f96f9d4de2 99 {
<> 154:37f96f9d4de2 100 return (DSPI_GetStatusFlags(spi_address[obj->instance]) & kDSPI_RxFifoDrainRequestFlag);
<> 154:37f96f9d4de2 101 }
<> 154:37f96f9d4de2 102
<> 154:37f96f9d4de2 103 int spi_master_write(spi_t *obj, int value)
<> 154:37f96f9d4de2 104 {
<> 154:37f96f9d4de2 105 dspi_command_data_config_t command;
<> 154:37f96f9d4de2 106 uint32_t rx_data;
<> 154:37f96f9d4de2 107 DSPI_GetDefaultDataCommandConfig(&command);
<> 154:37f96f9d4de2 108 command.isEndOfQueue = true;
<> 154:37f96f9d4de2 109
<> 154:37f96f9d4de2 110 DSPI_MasterWriteDataBlocking(spi_address[obj->instance], &command, (uint16_t)value);
<> 154:37f96f9d4de2 111
<> 154:37f96f9d4de2 112 DSPI_ClearStatusFlags(spi_address[obj->instance], kDSPI_TxFifoFillRequestFlag);
<> 154:37f96f9d4de2 113
<> 154:37f96f9d4de2 114 // wait rx buffer full
<> 154:37f96f9d4de2 115 while (!spi_readable(obj));
<> 154:37f96f9d4de2 116 rx_data = DSPI_ReadData(spi_address[obj->instance]);
<> 154:37f96f9d4de2 117 DSPI_ClearStatusFlags(spi_address[obj->instance], kDSPI_RxFifoDrainRequestFlag | kDSPI_EndOfQueueFlag);
<> 154:37f96f9d4de2 118 return rx_data & 0xffff;
<> 154:37f96f9d4de2 119 }
<> 154:37f96f9d4de2 120
AnnaBridge 167:e84263d55307 121 int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length, char *rx_buffer, int rx_length) {
AnnaBridge 167:e84263d55307 122 int total = (tx_length > rx_length) ? tx_length : rx_length;
AnnaBridge 167:e84263d55307 123
AnnaBridge 167:e84263d55307 124 for (int i = 0; i < total; i++) {
AnnaBridge 167:e84263d55307 125 char out = (i < tx_length) ? tx_buffer[i] : 0xff;
AnnaBridge 167:e84263d55307 126 char in = spi_master_write(obj, out);
AnnaBridge 167:e84263d55307 127 if (i < rx_length) {
AnnaBridge 167:e84263d55307 128 rx_buffer[i] = in;
AnnaBridge 167:e84263d55307 129 }
AnnaBridge 167:e84263d55307 130 }
AnnaBridge 167:e84263d55307 131
AnnaBridge 167:e84263d55307 132 return total;
AnnaBridge 167:e84263d55307 133 }
AnnaBridge 167:e84263d55307 134
<> 154:37f96f9d4de2 135 int spi_slave_receive(spi_t *obj)
<> 154:37f96f9d4de2 136 {
<> 154:37f96f9d4de2 137 return spi_readable(obj);
<> 154:37f96f9d4de2 138 }
<> 154:37f96f9d4de2 139
<> 154:37f96f9d4de2 140 int spi_slave_read(spi_t *obj)
<> 154:37f96f9d4de2 141 {
<> 154:37f96f9d4de2 142 uint32_t rx_data;
<> 154:37f96f9d4de2 143
<> 154:37f96f9d4de2 144 while (!spi_readable(obj));
<> 154:37f96f9d4de2 145 rx_data = DSPI_ReadData(spi_address[obj->instance]);
<> 154:37f96f9d4de2 146 DSPI_ClearStatusFlags(spi_address[obj->instance], kDSPI_RxFifoDrainRequestFlag);
<> 154:37f96f9d4de2 147 return rx_data & 0xffff;
<> 154:37f96f9d4de2 148 }
<> 154:37f96f9d4de2 149
<> 154:37f96f9d4de2 150 void spi_slave_write(spi_t *obj, int value)
<> 154:37f96f9d4de2 151 {
<> 154:37f96f9d4de2 152 DSPI_SlaveWriteDataBlocking(spi_address[obj->instance], (uint32_t)value);
<> 154:37f96f9d4de2 153 }
<> 154:37f96f9d4de2 154
<> 154:37f96f9d4de2 155 #endif