mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

Dependents:   Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.c@173:e131a1973e81, 2017-09-15 (annotated)

Committer:
AnnaBridge
Date:
Fri Sep 15 14:59:18 2017 +0100
Revision:
173:e131a1973e81
Parent:
167:e84263d55307
Child:
181:57724642e740
This updates the lib to the mbed lib v 151

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32l4xx_hal_spi.c
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
AnnaBridge 167:e84263d55307 5 * @version V1.7.1
AnnaBridge 167:e84263d55307 6 * @date 21-April-2017
<> 144:ef7eb2e8f9f7 7 * @brief SPI HAL module driver.
<> 144:ef7eb2e8f9f7 8 * This file provides firmware functions to manage the following
<> 144:ef7eb2e8f9f7 9 * functionalities of the Serial Peripheral Interface (SPI) peripheral:
<> 144:ef7eb2e8f9f7 10 * + Initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 11 * + IO operation functions
<> 144:ef7eb2e8f9f7 12 * + Peripheral Control functions
<> 144:ef7eb2e8f9f7 13 * + Peripheral State functions
<> 144:ef7eb2e8f9f7 14 *
<> 144:ef7eb2e8f9f7 15 @verbatim
<> 144:ef7eb2e8f9f7 16 ==============================================================================
<> 144:ef7eb2e8f9f7 17 ##### How to use this driver #####
<> 144:ef7eb2e8f9f7 18 ==============================================================================
<> 144:ef7eb2e8f9f7 19 [..]
<> 144:ef7eb2e8f9f7 20 The SPI HAL driver can be used as follows:
<> 144:ef7eb2e8f9f7 21
<> 144:ef7eb2e8f9f7 22 (#) Declare a SPI_HandleTypeDef handle structure, for example:
<> 144:ef7eb2e8f9f7 23 SPI_HandleTypeDef hspi;
<> 144:ef7eb2e8f9f7 24
<> 144:ef7eb2e8f9f7 25 (#)Initialize the SPI low level resources by implementing the HAL_SPI_MspInit() API:
<> 144:ef7eb2e8f9f7 26 (##) Enable the SPIx interface clock
<> 144:ef7eb2e8f9f7 27 (##) SPI pins configuration
<> 144:ef7eb2e8f9f7 28 (+++) Enable the clock for the SPI GPIOs
<> 144:ef7eb2e8f9f7 29 (+++) Configure these SPI pins as alternate function push-pull
<> 144:ef7eb2e8f9f7 30 (##) NVIC configuration if you need to use interrupt process
<> 144:ef7eb2e8f9f7 31 (+++) Configure the SPIx interrupt priority
<> 144:ef7eb2e8f9f7 32 (+++) Enable the NVIC SPI IRQ handle
<> 144:ef7eb2e8f9f7 33 (##) DMA Configuration if you need to use DMA process
AnnaBridge 167:e84263d55307 34 (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive Stream/Channel
<> 144:ef7eb2e8f9f7 35 (+++) Enable the DMAx clock
<> 144:ef7eb2e8f9f7 36 (+++) Configure the DMA handle parameters
AnnaBridge 167:e84263d55307 37 (+++) Configure the DMA Tx or Rx Stream/Channel
<> 144:ef7eb2e8f9f7 38 (+++) Associate the initialized hdma_tx handle to the hspi DMA Tx or Rx handle
AnnaBridge 167:e84263d55307 39 (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx Stream/Channel
<> 144:ef7eb2e8f9f7 40
<> 144:ef7eb2e8f9f7 41 (#) Program the Mode, BidirectionalMode , Data size, Baudrate Prescaler, NSS
<> 144:ef7eb2e8f9f7 42 management, Clock polarity and phase, FirstBit and CRC configuration in the hspi Init structure.
<> 144:ef7eb2e8f9f7 43
<> 144:ef7eb2e8f9f7 44 (#) Initialize the SPI registers by calling the HAL_SPI_Init() API:
<> 144:ef7eb2e8f9f7 45 (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
<> 144:ef7eb2e8f9f7 46 by calling the customized HAL_SPI_MspInit() API.
<> 144:ef7eb2e8f9f7 47 [..]
<> 144:ef7eb2e8f9f7 48 Circular mode restriction:
<> 144:ef7eb2e8f9f7 49 (#) The DMA circular mode cannot be used when the SPI is configured in these modes:
<> 144:ef7eb2e8f9f7 50 (##) Master 2Lines RxOnly
<> 144:ef7eb2e8f9f7 51 (##) Master 1Line Rx
<> 144:ef7eb2e8f9f7 52 (#) The CRC feature is not managed when the DMA circular mode is enabled
<> 144:ef7eb2e8f9f7 53 (#) When the SPI DMA Pause/Stop features are used, we must use the following APIs
<> 144:ef7eb2e8f9f7 54 the HAL_SPI_DMAPause()/ HAL_SPI_DMAStop() only under the SPI callbacks
AnnaBridge 167:e84263d55307 55 [..]
AnnaBridge 167:e84263d55307 56 Master Receive mode restriction:
AnnaBridge 167:e84263d55307 57 (#) In Master unidirectional receive-only mode (MSTR =1, BIDIMODE=0, RXONLY=0) or
AnnaBridge 167:e84263d55307 58 bidirectional receive mode (MSTR=1, BIDIMODE=1, BIDIOE=0), to ensure that the SPI
AnnaBridge 167:e84263d55307 59 does not initiate a new transfer the following procedure has to be respected:
AnnaBridge 167:e84263d55307 60 (##) HAL_SPI_DeInit()
AnnaBridge 167:e84263d55307 61 (##) HAL_SPI_Init()
AnnaBridge 167:e84263d55307 62 [..]
AnnaBridge 167:e84263d55307 63 The HAL drivers do not allow reaching all supported SPI frequencies in the different SPI
AnnaBridge 167:e84263d55307 64 modes. Refer to the source code (stm32xxxx_hal_spi.c header) to get a summary of the
AnnaBridge 167:e84263d55307 65 maximum SPI frequency that can be reached with a data size of 8 or 16 bits, depending on
AnnaBridge 167:e84263d55307 66 the APBx peripheral clock frequency (fPCLK) used by the SPI instance.
AnnaBridge 167:e84263d55307 67
<> 144:ef7eb2e8f9f7 68
<> 144:ef7eb2e8f9f7 69 @endverbatim
AnnaBridge 167:e84263d55307 70
AnnaBridge 167:e84263d55307 71 Additional table :
AnnaBridge 167:e84263d55307 72
AnnaBridge 167:e84263d55307 73 DataSize = SPI_DATASIZE_8BIT:
AnnaBridge 167:e84263d55307 74 +----------------------------------------------------------------------------------------------+
AnnaBridge 167:e84263d55307 75 | | | 2Lines Fullduplex | 2Lines RxOnly | 1Line |
AnnaBridge 167:e84263d55307 76 | Process | Tranfert mode |---------------------|----------------------|----------------------|
AnnaBridge 167:e84263d55307 77 | | | Master | Slave | Master | Slave | Master | Slave |
AnnaBridge 167:e84263d55307 78 |==============================================================================================|
AnnaBridge 167:e84263d55307 79 | T | Polling | Fpclk/4 | Fpclk/8 | NA | NA | NA | NA |
AnnaBridge 167:e84263d55307 80 | X |----------------|----------|----------|-----------|----------|-----------|----------|
AnnaBridge 167:e84263d55307 81 | / | Interrupt | Fpclk/4 | Fpclk/16 | NA | NA | NA | NA |
AnnaBridge 167:e84263d55307 82 | R |----------------|----------|----------|-----------|----------|-----------|----------|
AnnaBridge 167:e84263d55307 83 | X | DMA | Fpclk/2 | Fpclk/2 | NA | NA | NA | NA |
AnnaBridge 167:e84263d55307 84 |=========|================|==========|==========|===========|==========|===========|==========|
AnnaBridge 167:e84263d55307 85 | | Polling | Fpclk/4 | Fpclk/8 | Fpclk/16 | Fpclk/8 | Fpclk/8 | Fpclk/8 |
AnnaBridge 167:e84263d55307 86 | |----------------|----------|----------|-----------|----------|-----------|----------|
AnnaBridge 167:e84263d55307 87 | R | Interrupt | Fpclk/8 | Fpclk/16 | Fpclk/8 | Fpclk/8 | Fpclk/8 | Fpclk/4 |
AnnaBridge 167:e84263d55307 88 | X |----------------|----------|----------|-----------|----------|-----------|----------|
AnnaBridge 167:e84263d55307 89 | | DMA | Fpclk/4 | Fpclk/2 | Fpclk/2 | Fpclk/16 | Fpclk/2 | Fpclk/16 |
AnnaBridge 167:e84263d55307 90 |=========|================|==========|==========|===========|==========|===========|==========|
AnnaBridge 167:e84263d55307 91 | | Polling | Fpclk/8 | Fpclk/2 | NA | NA | Fpclk/8 | Fpclk/8 |
AnnaBridge 167:e84263d55307 92 | |----------------|----------|----------|-----------|----------|-----------|----------|
AnnaBridge 167:e84263d55307 93 | T | Interrupt | Fpclk/2 | Fpclk/4 | NA | NA | Fpclk/16 | Fpclk/8 |
AnnaBridge 167:e84263d55307 94 | X |----------------|----------|----------|-----------|----------|-----------|----------|
AnnaBridge 167:e84263d55307 95 | | DMA | Fpclk/2 | Fpclk/2 | NA | NA | Fpclk/8 | Fpclk/16 |
AnnaBridge 167:e84263d55307 96 +----------------------------------------------------------------------------------------------+
AnnaBridge 167:e84263d55307 97
AnnaBridge 167:e84263d55307 98 DataSize = SPI_DATASIZE_16BIT:
AnnaBridge 167:e84263d55307 99 +----------------------------------------------------------------------------------------------+
AnnaBridge 167:e84263d55307 100 | | | 2Lines Fullduplex | 2Lines RxOnly | 1Line |
AnnaBridge 167:e84263d55307 101 | Process | Tranfert mode |---------------------|----------------------|----------------------|
AnnaBridge 167:e84263d55307 102 | | | Master | Slave | Master | Slave | Master | Slave |
AnnaBridge 167:e84263d55307 103 |==============================================================================================|
AnnaBridge 167:e84263d55307 104 | T | Polling | Fpclk/4 | Fpclk/8 | NA | NA | NA | NA |
AnnaBridge 167:e84263d55307 105 | X |----------------|----------|----------|-----------|----------|-----------|----------|
AnnaBridge 167:e84263d55307 106 | / | Interrupt | Fpclk/4 | Fpclk/16 | NA | NA | NA | NA |
AnnaBridge 167:e84263d55307 107 | R |----------------|----------|----------|-----------|----------|-----------|----------|
AnnaBridge 167:e84263d55307 108 | X | DMA | Fpclk/2 | Fpclk/2 | NA | NA | NA | NA |
AnnaBridge 167:e84263d55307 109 |=========|================|==========|==========|===========|==========|===========|==========|
AnnaBridge 167:e84263d55307 110 | | Polling | Fpclk/4 | Fpclk/8 | Fpclk/16 | Fpclk/8 | Fpclk/8 | Fpclk/8 |
AnnaBridge 167:e84263d55307 111 | |----------------|----------|----------|-----------|----------|-----------|----------|
AnnaBridge 167:e84263d55307 112 | R | Interrupt | Fpclk/8 | Fpclk/16 | Fpclk/8 | Fpclk/8 | Fpclk/8 | Fpclk/4 |
AnnaBridge 167:e84263d55307 113 | X |----------------|----------|----------|-----------|----------|-----------|----------|
AnnaBridge 167:e84263d55307 114 | | DMA | Fpclk/4 | Fpclk/2 | Fpclk/2 | Fpclk/16 | Fpclk/2 | Fpclk/16 |
AnnaBridge 167:e84263d55307 115 |=========|================|==========|==========|===========|==========|===========|==========|
AnnaBridge 167:e84263d55307 116 | | Polling | Fpclk/8 | Fpclk/2 | NA | NA | Fpclk/8 | Fpclk/8 |
AnnaBridge 167:e84263d55307 117 | |----------------|----------|----------|-----------|----------|-----------|----------|
AnnaBridge 167:e84263d55307 118 | T | Interrupt | Fpclk/2 | Fpclk/4 | NA | NA | Fpclk/16 | Fpclk/8 |
AnnaBridge 167:e84263d55307 119 | X |----------------|----------|----------|-----------|----------|-----------|----------|
AnnaBridge 167:e84263d55307 120 | | DMA | Fpclk/2 | Fpclk/2 | NA | NA | Fpclk/8 | Fpclk/16 |
AnnaBridge 167:e84263d55307 121 +----------------------------------------------------------------------------------------------+
AnnaBridge 167:e84263d55307 122 @note The max SPI frequency depend on SPI data size (4bits, 5bits,..., 8bits,...15bits, 16bits),
AnnaBridge 167:e84263d55307 123 SPI mode(2 Lines fullduplex, 2 lines RxOnly, 1 line TX/RX) and Process mode (Polling, IT, DMA).
AnnaBridge 167:e84263d55307 124 @note
AnnaBridge 167:e84263d55307 125 (#) TX/RX processes are HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_IT() and HAL_SPI_TransmitReceive_DMA()
AnnaBridge 167:e84263d55307 126 (#) RX processes are HAL_SPI_Receive(), HAL_SPI_Receive_IT() and HAL_SPI_Receive_DMA()
AnnaBridge 167:e84263d55307 127 (#) TX processes are HAL_SPI_Transmit(), HAL_SPI_Transmit_IT() and HAL_SPI_Transmit_DMA()
AnnaBridge 167:e84263d55307 128
<> 144:ef7eb2e8f9f7 129 ******************************************************************************
<> 144:ef7eb2e8f9f7 130 * @attention
<> 144:ef7eb2e8f9f7 131 *
AnnaBridge 167:e84263d55307 132 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 133 *
<> 144:ef7eb2e8f9f7 134 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 135 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 136 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 137 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 138 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 139 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 140 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 141 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 142 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 143 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 144 *
<> 144:ef7eb2e8f9f7 145 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 146 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 147 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 148 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 149 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 150 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 151 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 152 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 153 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 154 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 155 *
<> 144:ef7eb2e8f9f7 156 ******************************************************************************
<> 144:ef7eb2e8f9f7 157 */
<> 144:ef7eb2e8f9f7 158
<> 144:ef7eb2e8f9f7 159 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 160 #include "stm32l4xx_hal.h"
<> 144:ef7eb2e8f9f7 161
<> 144:ef7eb2e8f9f7 162 /** @addtogroup STM32L4xx_HAL_Driver
<> 144:ef7eb2e8f9f7 163 * @{
<> 144:ef7eb2e8f9f7 164 */
<> 144:ef7eb2e8f9f7 165
<> 144:ef7eb2e8f9f7 166 /** @defgroup SPI SPI
<> 144:ef7eb2e8f9f7 167 * @brief SPI HAL module driver
<> 144:ef7eb2e8f9f7 168 * @{
<> 144:ef7eb2e8f9f7 169 */
<> 144:ef7eb2e8f9f7 170 #ifdef HAL_SPI_MODULE_ENABLED
<> 144:ef7eb2e8f9f7 171
<> 144:ef7eb2e8f9f7 172 /* Private typedef -----------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 173 /* Private defines -----------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 174 /** @defgroup SPI_Private_Constants SPI Private Constants
<> 144:ef7eb2e8f9f7 175 * @{
<> 144:ef7eb2e8f9f7 176 */
AnnaBridge 167:e84263d55307 177 #define SPI_DEFAULT_TIMEOUT 100U
<> 144:ef7eb2e8f9f7 178 /**
<> 144:ef7eb2e8f9f7 179 * @}
<> 144:ef7eb2e8f9f7 180 */
<> 144:ef7eb2e8f9f7 181
<> 144:ef7eb2e8f9f7 182 /* Private macros ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 183 /* Private variables ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 184 /* Private function prototypes -----------------------------------------------*/
<> 144:ef7eb2e8f9f7 185 /** @defgroup SPI_Private_Functions SPI Private Functions
<> 144:ef7eb2e8f9f7 186 * @{
<> 144:ef7eb2e8f9f7 187 */
<> 144:ef7eb2e8f9f7 188 static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 189 static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 190 static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 191 static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 192 static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 193 static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 194 static void SPI_DMAError(DMA_HandleTypeDef *hdma);
AnnaBridge 167:e84263d55307 195 static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma);
AnnaBridge 167:e84263d55307 196 static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
AnnaBridge 167:e84263d55307 197 static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
AnnaBridge 167:e84263d55307 198 static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, uint32_t State,
AnnaBridge 167:e84263d55307 199 uint32_t Timeout, uint32_t Tickstart);
AnnaBridge 167:e84263d55307 200 static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State,
AnnaBridge 167:e84263d55307 201 uint32_t Timeout, uint32_t Tickstart);
<> 144:ef7eb2e8f9f7 202 static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
<> 144:ef7eb2e8f9f7 203 static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
<> 144:ef7eb2e8f9f7 204 static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
<> 144:ef7eb2e8f9f7 205 static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
<> 144:ef7eb2e8f9f7 206 static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
<> 144:ef7eb2e8f9f7 207 static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
<> 144:ef7eb2e8f9f7 208 static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
<> 144:ef7eb2e8f9f7 209 static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
AnnaBridge 167:e84263d55307 210 #if (USE_SPI_CRC != 0U)
AnnaBridge 167:e84263d55307 211 static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi);
AnnaBridge 167:e84263d55307 212 static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi);
AnnaBridge 167:e84263d55307 213 static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi);
<> 144:ef7eb2e8f9f7 214 static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi);
AnnaBridge 167:e84263d55307 215 #endif /* USE_SPI_CRC */
AnnaBridge 167:e84263d55307 216 static void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi);
AnnaBridge 167:e84263d55307 217 static void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi);
<> 144:ef7eb2e8f9f7 218 static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi);
<> 144:ef7eb2e8f9f7 219 static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi);
<> 144:ef7eb2e8f9f7 220 static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi);
AnnaBridge 167:e84263d55307 221 static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart);
AnnaBridge 167:e84263d55307 222 static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart);
<> 144:ef7eb2e8f9f7 223 /**
<> 144:ef7eb2e8f9f7 224 * @}
<> 144:ef7eb2e8f9f7 225 */
<> 144:ef7eb2e8f9f7 226
AnnaBridge 167:e84263d55307 227 /* Exported functions --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 228 /** @defgroup SPI_Exported_Functions SPI Exported Functions
<> 144:ef7eb2e8f9f7 229 * @{
<> 144:ef7eb2e8f9f7 230 */
<> 144:ef7eb2e8f9f7 231
<> 144:ef7eb2e8f9f7 232 /** @defgroup SPI_Exported_Functions_Group1 Initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 233 * @brief Initialization and Configuration functions
<> 144:ef7eb2e8f9f7 234 *
<> 144:ef7eb2e8f9f7 235 @verbatim
<> 144:ef7eb2e8f9f7 236 ===============================================================================
<> 144:ef7eb2e8f9f7 237 ##### Initialization and de-initialization functions #####
<> 144:ef7eb2e8f9f7 238 ===============================================================================
<> 144:ef7eb2e8f9f7 239 [..] This subsection provides a set of functions allowing to initialize and
<> 144:ef7eb2e8f9f7 240 de-initialize the SPIx peripheral:
<> 144:ef7eb2e8f9f7 241
<> 144:ef7eb2e8f9f7 242 (+) User must implement HAL_SPI_MspInit() function in which he configures
<> 144:ef7eb2e8f9f7 243 all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
<> 144:ef7eb2e8f9f7 244
<> 144:ef7eb2e8f9f7 245 (+) Call the function HAL_SPI_Init() to configure the selected device with
<> 144:ef7eb2e8f9f7 246 the selected configuration:
<> 144:ef7eb2e8f9f7 247 (++) Mode
<> 144:ef7eb2e8f9f7 248 (++) Direction
<> 144:ef7eb2e8f9f7 249 (++) Data Size
<> 144:ef7eb2e8f9f7 250 (++) Clock Polarity and Phase
<> 144:ef7eb2e8f9f7 251 (++) NSS Management
<> 144:ef7eb2e8f9f7 252 (++) BaudRate Prescaler
<> 144:ef7eb2e8f9f7 253 (++) FirstBit
<> 144:ef7eb2e8f9f7 254 (++) TIMode
<> 144:ef7eb2e8f9f7 255 (++) CRC Calculation
<> 144:ef7eb2e8f9f7 256 (++) CRC Polynomial if CRC enabled
<> 144:ef7eb2e8f9f7 257 (++) CRC Length, used only with Data8 and Data16
<> 144:ef7eb2e8f9f7 258 (++) FIFO reception threshold
<> 144:ef7eb2e8f9f7 259
<> 144:ef7eb2e8f9f7 260 (+) Call the function HAL_SPI_DeInit() to restore the default configuration
<> 144:ef7eb2e8f9f7 261 of the selected SPIx peripheral.
<> 144:ef7eb2e8f9f7 262
<> 144:ef7eb2e8f9f7 263 @endverbatim
<> 144:ef7eb2e8f9f7 264 * @{
<> 144:ef7eb2e8f9f7 265 */
<> 144:ef7eb2e8f9f7 266
<> 144:ef7eb2e8f9f7 267 /**
<> 144:ef7eb2e8f9f7 268 * @brief Initialize the SPI according to the specified parameters
<> 144:ef7eb2e8f9f7 269 * in the SPI_InitTypeDef and initialize the associated handle.
<> 144:ef7eb2e8f9f7 270 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 271 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 272 * @retval HAL status
<> 144:ef7eb2e8f9f7 273 */
<> 144:ef7eb2e8f9f7 274 HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 275 {
<> 144:ef7eb2e8f9f7 276 uint32_t frxth;
<> 144:ef7eb2e8f9f7 277
<> 144:ef7eb2e8f9f7 278 /* Check the SPI handle allocation */
AnnaBridge 167:e84263d55307 279 if (hspi == NULL)
<> 144:ef7eb2e8f9f7 280 {
<> 144:ef7eb2e8f9f7 281 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 282 }
<> 144:ef7eb2e8f9f7 283
<> 144:ef7eb2e8f9f7 284 /* Check the parameters */
<> 144:ef7eb2e8f9f7 285 assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));
<> 144:ef7eb2e8f9f7 286 assert_param(IS_SPI_MODE(hspi->Init.Mode));
<> 144:ef7eb2e8f9f7 287 assert_param(IS_SPI_DIRECTION(hspi->Init.Direction));
<> 144:ef7eb2e8f9f7 288 assert_param(IS_SPI_DATASIZE(hspi->Init.DataSize));
<> 144:ef7eb2e8f9f7 289 assert_param(IS_SPI_NSS(hspi->Init.NSS));
<> 144:ef7eb2e8f9f7 290 assert_param(IS_SPI_NSSP(hspi->Init.NSSPMode));
<> 144:ef7eb2e8f9f7 291 assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
<> 144:ef7eb2e8f9f7 292 assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit));
<> 144:ef7eb2e8f9f7 293 assert_param(IS_SPI_TIMODE(hspi->Init.TIMode));
AnnaBridge 167:e84263d55307 294 if (hspi->Init.TIMode == SPI_TIMODE_DISABLE)
AnnaBridge 167:e84263d55307 295 {
AnnaBridge 167:e84263d55307 296 assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity));
AnnaBridge 167:e84263d55307 297 assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase));
AnnaBridge 167:e84263d55307 298 }
AnnaBridge 167:e84263d55307 299 #if (USE_SPI_CRC != 0U)
<> 144:ef7eb2e8f9f7 300 assert_param(IS_SPI_CRC_CALCULATION(hspi->Init.CRCCalculation));
AnnaBridge 167:e84263d55307 301 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
AnnaBridge 167:e84263d55307 302 {
AnnaBridge 167:e84263d55307 303 assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial));
AnnaBridge 167:e84263d55307 304 assert_param(IS_SPI_CRC_LENGTH(hspi->Init.CRCLength));
AnnaBridge 167:e84263d55307 305 }
AnnaBridge 167:e84263d55307 306 #else
AnnaBridge 167:e84263d55307 307 hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
AnnaBridge 167:e84263d55307 308 #endif /* USE_SPI_CRC */
AnnaBridge 167:e84263d55307 309
AnnaBridge 167:e84263d55307 310 if (hspi->State == HAL_SPI_STATE_RESET)
<> 144:ef7eb2e8f9f7 311 {
<> 144:ef7eb2e8f9f7 312 /* Allocate lock resource and initialize it */
<> 144:ef7eb2e8f9f7 313 hspi->Lock = HAL_UNLOCKED;
<> 144:ef7eb2e8f9f7 314
<> 144:ef7eb2e8f9f7 315 /* Init the low level hardware : GPIO, CLOCK, NVIC... */
<> 144:ef7eb2e8f9f7 316 HAL_SPI_MspInit(hspi);
<> 144:ef7eb2e8f9f7 317 }
<> 144:ef7eb2e8f9f7 318
<> 144:ef7eb2e8f9f7 319 hspi->State = HAL_SPI_STATE_BUSY;
<> 144:ef7eb2e8f9f7 320
<> 144:ef7eb2e8f9f7 321 /* Disable the selected SPI peripheral */
<> 144:ef7eb2e8f9f7 322 __HAL_SPI_DISABLE(hspi);
<> 144:ef7eb2e8f9f7 323
<> 144:ef7eb2e8f9f7 324 /* Align by default the rs fifo threshold on the data size */
AnnaBridge 167:e84263d55307 325 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
<> 144:ef7eb2e8f9f7 326 {
<> 144:ef7eb2e8f9f7 327 frxth = SPI_RXFIFO_THRESHOLD_HF;
<> 144:ef7eb2e8f9f7 328 }
<> 144:ef7eb2e8f9f7 329 else
<> 144:ef7eb2e8f9f7 330 {
<> 144:ef7eb2e8f9f7 331 frxth = SPI_RXFIFO_THRESHOLD_QF;
<> 144:ef7eb2e8f9f7 332 }
<> 144:ef7eb2e8f9f7 333
<> 144:ef7eb2e8f9f7 334 /* CRC calculation is valid only for 16Bit and 8 Bit */
AnnaBridge 167:e84263d55307 335 if ((hspi->Init.DataSize != SPI_DATASIZE_16BIT) && (hspi->Init.DataSize != SPI_DATASIZE_8BIT))
<> 144:ef7eb2e8f9f7 336 {
<> 144:ef7eb2e8f9f7 337 /* CRC must be disabled */
<> 144:ef7eb2e8f9f7 338 hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
<> 144:ef7eb2e8f9f7 339 }
<> 144:ef7eb2e8f9f7 340
<> 144:ef7eb2e8f9f7 341 /* Align the CRC Length on the data size */
AnnaBridge 167:e84263d55307 342 if (hspi->Init.CRCLength == SPI_CRC_LENGTH_DATASIZE)
<> 144:ef7eb2e8f9f7 343 {
<> 144:ef7eb2e8f9f7 344 /* CRC Length aligned on the data size : value set by default */
AnnaBridge 167:e84263d55307 345 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
<> 144:ef7eb2e8f9f7 346 {
<> 144:ef7eb2e8f9f7 347 hspi->Init.CRCLength = SPI_CRC_LENGTH_16BIT;
<> 144:ef7eb2e8f9f7 348 }
<> 144:ef7eb2e8f9f7 349 else
<> 144:ef7eb2e8f9f7 350 {
<> 144:ef7eb2e8f9f7 351 hspi->Init.CRCLength = SPI_CRC_LENGTH_8BIT;
<> 144:ef7eb2e8f9f7 352 }
<> 144:ef7eb2e8f9f7 353 }
<> 144:ef7eb2e8f9f7 354
AnnaBridge 167:e84263d55307 355 /*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/
<> 144:ef7eb2e8f9f7 356 /* Configure : SPI Mode, Communication Mode, Clock polarity and phase, NSS management,
AnnaBridge 167:e84263d55307 357 Communication speed, First bit and CRC calculation state */
AnnaBridge 167:e84263d55307 358 WRITE_REG(hspi->Instance->CR1, (hspi->Init.Mode | hspi->Init.Direction |
AnnaBridge 167:e84263d55307 359 hspi->Init.CLKPolarity | hspi->Init.CLKPhase | (hspi->Init.NSS & SPI_CR1_SSM) |
AnnaBridge 167:e84263d55307 360 hspi->Init.BaudRatePrescaler | hspi->Init.FirstBit | hspi->Init.CRCCalculation));
AnnaBridge 167:e84263d55307 361 #if (USE_SPI_CRC != 0U)
AnnaBridge 167:e84263d55307 362 /* Configure : CRC Length */
AnnaBridge 167:e84263d55307 363 if (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)
<> 144:ef7eb2e8f9f7 364 {
AnnaBridge 167:e84263d55307 365 hspi->Instance->CR1 |= SPI_CR1_CRCL;
<> 144:ef7eb2e8f9f7 366 }
AnnaBridge 167:e84263d55307 367 #endif /* USE_SPI_CRC */
AnnaBridge 167:e84263d55307 368
AnnaBridge 167:e84263d55307 369 /* Configure : NSS management, TI Mode, NSS Pulse, Data size and Rx Fifo Threshold */
AnnaBridge 167:e84263d55307 370 WRITE_REG(hspi->Instance->CR2, (((hspi->Init.NSS >> 16U) & SPI_CR2_SSOE) | hspi->Init.TIMode |
AnnaBridge 167:e84263d55307 371 hspi->Init.NSSPMode | hspi->Init.DataSize) | frxth);
AnnaBridge 167:e84263d55307 372
AnnaBridge 167:e84263d55307 373 #if (USE_SPI_CRC != 0U)
AnnaBridge 167:e84263d55307 374 /*---------------------------- SPIx CRCPOLY Configuration ------------------*/
<> 144:ef7eb2e8f9f7 375 /* Configure : CRC Polynomial */
AnnaBridge 167:e84263d55307 376 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
AnnaBridge 167:e84263d55307 377 {
AnnaBridge 167:e84263d55307 378 WRITE_REG(hspi->Instance->CRCPR, hspi->Init.CRCPolynomial);
AnnaBridge 167:e84263d55307 379 }
AnnaBridge 167:e84263d55307 380 #endif /* USE_SPI_CRC */
AnnaBridge 167:e84263d55307 381
AnnaBridge 167:e84263d55307 382 #if defined(SPI_I2SCFGR_I2SMOD)
AnnaBridge 167:e84263d55307 383 /* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */
AnnaBridge 167:e84263d55307 384 CLEAR_BIT(hspi->Instance->I2SCFGR, SPI_I2SCFGR_I2SMOD);
AnnaBridge 167:e84263d55307 385 #endif /* SPI_I2SCFGR_I2SMOD */
<> 144:ef7eb2e8f9f7 386
<> 144:ef7eb2e8f9f7 387 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
AnnaBridge 167:e84263d55307 388 hspi->State = HAL_SPI_STATE_READY;
<> 144:ef7eb2e8f9f7 389
<> 144:ef7eb2e8f9f7 390 return HAL_OK;
<> 144:ef7eb2e8f9f7 391 }
<> 144:ef7eb2e8f9f7 392
<> 144:ef7eb2e8f9f7 393 /**
AnnaBridge 167:e84263d55307 394 * @brief De-Initialize the SPI peripheral.
<> 144:ef7eb2e8f9f7 395 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 396 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 397 * @retval HAL status
<> 144:ef7eb2e8f9f7 398 */
<> 144:ef7eb2e8f9f7 399 HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 400 {
<> 144:ef7eb2e8f9f7 401 /* Check the SPI handle allocation */
AnnaBridge 167:e84263d55307 402 if (hspi == NULL)
<> 144:ef7eb2e8f9f7 403 {
<> 144:ef7eb2e8f9f7 404 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 405 }
<> 144:ef7eb2e8f9f7 406
AnnaBridge 167:e84263d55307 407 /* Check SPI Instance parameter */
<> 144:ef7eb2e8f9f7 408 assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));
AnnaBridge 167:e84263d55307 409
<> 144:ef7eb2e8f9f7 410 hspi->State = HAL_SPI_STATE_BUSY;
<> 144:ef7eb2e8f9f7 411
<> 144:ef7eb2e8f9f7 412 /* Disable the SPI Peripheral Clock */
<> 144:ef7eb2e8f9f7 413 __HAL_SPI_DISABLE(hspi);
<> 144:ef7eb2e8f9f7 414
<> 144:ef7eb2e8f9f7 415 /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
<> 144:ef7eb2e8f9f7 416 HAL_SPI_MspDeInit(hspi);
<> 144:ef7eb2e8f9f7 417
<> 144:ef7eb2e8f9f7 418 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
<> 144:ef7eb2e8f9f7 419 hspi->State = HAL_SPI_STATE_RESET;
<> 144:ef7eb2e8f9f7 420
AnnaBridge 167:e84263d55307 421 /* Release Lock */
<> 144:ef7eb2e8f9f7 422 __HAL_UNLOCK(hspi);
<> 144:ef7eb2e8f9f7 423
<> 144:ef7eb2e8f9f7 424 return HAL_OK;
<> 144:ef7eb2e8f9f7 425 }
<> 144:ef7eb2e8f9f7 426
<> 144:ef7eb2e8f9f7 427 /**
AnnaBridge 167:e84263d55307 428 * @brief Initialize the SPI MSP.
<> 144:ef7eb2e8f9f7 429 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 430 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 431 * @retval None
<> 144:ef7eb2e8f9f7 432 */
<> 144:ef7eb2e8f9f7 433 __weak void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 434 {
<> 144:ef7eb2e8f9f7 435 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 436 UNUSED(hspi);
<> 144:ef7eb2e8f9f7 437
<> 144:ef7eb2e8f9f7 438 /* NOTE : This function should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 439 the HAL_SPI_MspInit should be implemented in the user file
<> 144:ef7eb2e8f9f7 440 */
<> 144:ef7eb2e8f9f7 441 }
<> 144:ef7eb2e8f9f7 442
<> 144:ef7eb2e8f9f7 443 /**
AnnaBridge 167:e84263d55307 444 * @brief De-Initialize the SPI MSP.
<> 144:ef7eb2e8f9f7 445 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 446 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 447 * @retval None
<> 144:ef7eb2e8f9f7 448 */
<> 144:ef7eb2e8f9f7 449 __weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 450 {
<> 144:ef7eb2e8f9f7 451 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 452 UNUSED(hspi);
<> 144:ef7eb2e8f9f7 453
<> 144:ef7eb2e8f9f7 454 /* NOTE : This function should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 455 the HAL_SPI_MspDeInit should be implemented in the user file
<> 144:ef7eb2e8f9f7 456 */
<> 144:ef7eb2e8f9f7 457 }
<> 144:ef7eb2e8f9f7 458
<> 144:ef7eb2e8f9f7 459 /**
<> 144:ef7eb2e8f9f7 460 * @}
<> 144:ef7eb2e8f9f7 461 */
<> 144:ef7eb2e8f9f7 462
<> 144:ef7eb2e8f9f7 463 /** @defgroup SPI_Exported_Functions_Group2 IO operation functions
<> 144:ef7eb2e8f9f7 464 * @brief Data transfers functions
<> 144:ef7eb2e8f9f7 465 *
<> 144:ef7eb2e8f9f7 466 @verbatim
<> 144:ef7eb2e8f9f7 467 ==============================================================================
<> 144:ef7eb2e8f9f7 468 ##### IO operation functions #####
<> 144:ef7eb2e8f9f7 469 ===============================================================================
<> 144:ef7eb2e8f9f7 470 [..]
<> 144:ef7eb2e8f9f7 471 This subsection provides a set of functions allowing to manage the SPI
<> 144:ef7eb2e8f9f7 472 data transfers.
<> 144:ef7eb2e8f9f7 473
<> 144:ef7eb2e8f9f7 474 [..] The SPI supports master and slave mode :
<> 144:ef7eb2e8f9f7 475
<> 144:ef7eb2e8f9f7 476 (#) There are two modes of transfer:
<> 144:ef7eb2e8f9f7 477 (++) Blocking mode: The communication is performed in polling mode.
<> 144:ef7eb2e8f9f7 478 The HAL status of all data processing is returned by the same function
<> 144:ef7eb2e8f9f7 479 after finishing transfer.
<> 144:ef7eb2e8f9f7 480 (++) No-Blocking mode: The communication is performed using Interrupts
AnnaBridge 167:e84263d55307 481 or DMA, These APIs return the HAL status.
AnnaBridge 167:e84263d55307 482 The end of the data processing will be indicated through the
AnnaBridge 167:e84263d55307 483 dedicated SPI IRQ when using Interrupt mode or the DMA IRQ when
AnnaBridge 167:e84263d55307 484 using DMA mode.
AnnaBridge 167:e84263d55307 485 The HAL_SPI_TxCpltCallback(), HAL_SPI_RxCpltCallback() and HAL_SPI_TxRxCpltCallback() user callbacks
AnnaBridge 167:e84263d55307 486 will be executed respectively at the end of the transmit or Receive process
AnnaBridge 167:e84263d55307 487 The HAL_SPI_ErrorCallback()user callback will be executed when a communication error is detected
<> 144:ef7eb2e8f9f7 488
<> 144:ef7eb2e8f9f7 489 (#) APIs provided for these 2 transfer modes (Blocking mode or Non blocking mode using either Interrupt or DMA)
<> 144:ef7eb2e8f9f7 490 exist for 1Line (simplex) and 2Lines (full duplex) modes.
<> 144:ef7eb2e8f9f7 491
<> 144:ef7eb2e8f9f7 492 @endverbatim
<> 144:ef7eb2e8f9f7 493 * @{
<> 144:ef7eb2e8f9f7 494 */
<> 144:ef7eb2e8f9f7 495
<> 144:ef7eb2e8f9f7 496 /**
<> 144:ef7eb2e8f9f7 497 * @brief Transmit an amount of data in blocking mode.
<> 144:ef7eb2e8f9f7 498 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 499 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 500 * @param pData: pointer to data buffer
<> 144:ef7eb2e8f9f7 501 * @param Size: amount of data to be sent
<> 144:ef7eb2e8f9f7 502 * @param Timeout: Timeout duration
<> 144:ef7eb2e8f9f7 503 * @retval HAL status
<> 144:ef7eb2e8f9f7 504 */
<> 144:ef7eb2e8f9f7 505 HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
<> 144:ef7eb2e8f9f7 506 {
AnnaBridge 167:e84263d55307 507 uint32_t tickstart = 0U;
<> 144:ef7eb2e8f9f7 508 HAL_StatusTypeDef errorcode = HAL_OK;
<> 144:ef7eb2e8f9f7 509
AnnaBridge 167:e84263d55307 510
AnnaBridge 167:e84263d55307 511 /* Check Direction parameter */
<> 144:ef7eb2e8f9f7 512 assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
<> 144:ef7eb2e8f9f7 513
<> 144:ef7eb2e8f9f7 514 /* Process Locked */
<> 144:ef7eb2e8f9f7 515 __HAL_LOCK(hspi);
<> 144:ef7eb2e8f9f7 516
AnnaBridge 167:e84263d55307 517 /* Init tickstart for timeout management*/
AnnaBridge 167:e84263d55307 518 tickstart = HAL_GetTick();
AnnaBridge 167:e84263d55307 519
AnnaBridge 167:e84263d55307 520 if (hspi->State != HAL_SPI_STATE_READY)
<> 144:ef7eb2e8f9f7 521 {
<> 144:ef7eb2e8f9f7 522 errorcode = HAL_BUSY;
<> 144:ef7eb2e8f9f7 523 goto error;
<> 144:ef7eb2e8f9f7 524 }
<> 144:ef7eb2e8f9f7 525
AnnaBridge 167:e84263d55307 526 if ((pData == NULL) || (Size == 0U))
<> 144:ef7eb2e8f9f7 527 {
<> 144:ef7eb2e8f9f7 528 errorcode = HAL_ERROR;
<> 144:ef7eb2e8f9f7 529 goto error;
<> 144:ef7eb2e8f9f7 530 }
<> 144:ef7eb2e8f9f7 531
<> 144:ef7eb2e8f9f7 532 /* Set the transaction information */
<> 144:ef7eb2e8f9f7 533 hspi->State = HAL_SPI_STATE_BUSY_TX;
<> 144:ef7eb2e8f9f7 534 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
AnnaBridge 167:e84263d55307 535 hspi->pTxBuffPtr = (uint8_t *)pData;
<> 144:ef7eb2e8f9f7 536 hspi->TxXferSize = Size;
<> 144:ef7eb2e8f9f7 537 hspi->TxXferCount = Size;
AnnaBridge 167:e84263d55307 538
AnnaBridge 167:e84263d55307 539 /*Init field not used in handle to zero */
<> 144:ef7eb2e8f9f7 540 hspi->pRxBuffPtr = (uint8_t *)NULL;
AnnaBridge 167:e84263d55307 541 hspi->RxXferSize = 0U;
AnnaBridge 167:e84263d55307 542 hspi->RxXferCount = 0U;
AnnaBridge 167:e84263d55307 543 hspi->TxISR = NULL;
AnnaBridge 167:e84263d55307 544 hspi->RxISR = NULL;
<> 144:ef7eb2e8f9f7 545
<> 144:ef7eb2e8f9f7 546 /* Configure communication direction : 1Line */
AnnaBridge 167:e84263d55307 547 if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
<> 144:ef7eb2e8f9f7 548 {
<> 144:ef7eb2e8f9f7 549 SPI_1LINE_TX(hspi);
<> 144:ef7eb2e8f9f7 550 }
<> 144:ef7eb2e8f9f7 551
AnnaBridge 167:e84263d55307 552 #if (USE_SPI_CRC != 0U)
<> 144:ef7eb2e8f9f7 553 /* Reset CRC Calculation */
AnnaBridge 167:e84263d55307 554 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<> 144:ef7eb2e8f9f7 555 {
<> 144:ef7eb2e8f9f7 556 SPI_RESET_CRC(hspi);
<> 144:ef7eb2e8f9f7 557 }
AnnaBridge 167:e84263d55307 558 #endif /* USE_SPI_CRC */
<> 144:ef7eb2e8f9f7 559
<> 144:ef7eb2e8f9f7 560 /* Check if the SPI is already enabled */
AnnaBridge 167:e84263d55307 561 if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
<> 144:ef7eb2e8f9f7 562 {
<> 144:ef7eb2e8f9f7 563 /* Enable SPI peripheral */
<> 144:ef7eb2e8f9f7 564 __HAL_SPI_ENABLE(hspi);
<> 144:ef7eb2e8f9f7 565 }
<> 144:ef7eb2e8f9f7 566
<> 144:ef7eb2e8f9f7 567 /* Transmit data in 16 Bit mode */
AnnaBridge 167:e84263d55307 568 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
<> 144:ef7eb2e8f9f7 569 {
AnnaBridge 167:e84263d55307 570 if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (hspi->TxXferCount == 0x01U))
AnnaBridge 167:e84263d55307 571 {
AnnaBridge 167:e84263d55307 572 hspi->Instance->DR = *((uint16_t *)pData);
AnnaBridge 167:e84263d55307 573 pData += sizeof(uint16_t);
AnnaBridge 167:e84263d55307 574 hspi->TxXferCount--;
AnnaBridge 167:e84263d55307 575 }
<> 144:ef7eb2e8f9f7 576 /* Transmit data in 16 Bit mode */
AnnaBridge 167:e84263d55307 577 while (hspi->TxXferCount > 0U)
<> 144:ef7eb2e8f9f7 578 {
<> 144:ef7eb2e8f9f7 579 /* Wait until TXE flag is set to send data */
AnnaBridge 167:e84263d55307 580 if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE))
<> 144:ef7eb2e8f9f7 581 {
AnnaBridge 167:e84263d55307 582 hspi->Instance->DR = *((uint16_t *)pData);
AnnaBridge 167:e84263d55307 583 pData += sizeof(uint16_t);
AnnaBridge 167:e84263d55307 584 hspi->TxXferCount--;
<> 144:ef7eb2e8f9f7 585 }
<> 144:ef7eb2e8f9f7 586 else
<> 144:ef7eb2e8f9f7 587 {
<> 144:ef7eb2e8f9f7 588 /* Timeout management */
AnnaBridge 167:e84263d55307 589 if ((Timeout == 0U) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick() - tickstart) >= Timeout)))
<> 144:ef7eb2e8f9f7 590 {
<> 144:ef7eb2e8f9f7 591 errorcode = HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 592 goto error;
<> 144:ef7eb2e8f9f7 593 }
<> 144:ef7eb2e8f9f7 594 }
<> 144:ef7eb2e8f9f7 595 }
<> 144:ef7eb2e8f9f7 596 }
<> 144:ef7eb2e8f9f7 597 /* Transmit data in 8 Bit mode */
<> 144:ef7eb2e8f9f7 598 else
<> 144:ef7eb2e8f9f7 599 {
AnnaBridge 167:e84263d55307 600 if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (hspi->TxXferCount == 0x01U))
AnnaBridge 167:e84263d55307 601 {
AnnaBridge 167:e84263d55307 602 if (hspi->TxXferCount > 1U)
AnnaBridge 167:e84263d55307 603 {
AnnaBridge 167:e84263d55307 604 /* write on the data register in packing mode */
AnnaBridge 167:e84263d55307 605 hspi->Instance->DR = *((uint16_t *)pData);
AnnaBridge 167:e84263d55307 606 pData += sizeof(uint16_t);
AnnaBridge 167:e84263d55307 607 hspi->TxXferCount -= 2U;
AnnaBridge 167:e84263d55307 608 }
AnnaBridge 167:e84263d55307 609 else
AnnaBridge 167:e84263d55307 610 {
AnnaBridge 167:e84263d55307 611 *((__IO uint8_t *)&hspi->Instance->DR) = (*pData++);
AnnaBridge 167:e84263d55307 612 hspi->TxXferCount--;
AnnaBridge 167:e84263d55307 613 }
AnnaBridge 167:e84263d55307 614 }
AnnaBridge 167:e84263d55307 615 while (hspi->TxXferCount > 0U)
<> 144:ef7eb2e8f9f7 616 {
<> 144:ef7eb2e8f9f7 617 /* Wait until TXE flag is set to send data */
AnnaBridge 167:e84263d55307 618 if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE))
<> 144:ef7eb2e8f9f7 619 {
AnnaBridge 167:e84263d55307 620 if (hspi->TxXferCount > 1U)
<> 144:ef7eb2e8f9f7 621 {
<> 144:ef7eb2e8f9f7 622 /* write on the data register in packing mode */
AnnaBridge 167:e84263d55307 623 hspi->Instance->DR = *((uint16_t *)pData);
AnnaBridge 167:e84263d55307 624 pData += sizeof(uint16_t);
AnnaBridge 167:e84263d55307 625 hspi->TxXferCount -= 2U;
<> 144:ef7eb2e8f9f7 626 }
<> 144:ef7eb2e8f9f7 627 else
<> 144:ef7eb2e8f9f7 628 {
AnnaBridge 167:e84263d55307 629 *((__IO uint8_t *)&hspi->Instance->DR) = (*pData++);
<> 144:ef7eb2e8f9f7 630 hspi->TxXferCount--;
<> 144:ef7eb2e8f9f7 631 }
<> 144:ef7eb2e8f9f7 632 }
<> 144:ef7eb2e8f9f7 633 else
<> 144:ef7eb2e8f9f7 634 {
<> 144:ef7eb2e8f9f7 635 /* Timeout management */
AnnaBridge 167:e84263d55307 636 if ((Timeout == 0U) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick() - tickstart) >= Timeout)))
<> 144:ef7eb2e8f9f7 637 {
<> 144:ef7eb2e8f9f7 638 errorcode = HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 639 goto error;
<> 144:ef7eb2e8f9f7 640 }
<> 144:ef7eb2e8f9f7 641 }
<> 144:ef7eb2e8f9f7 642 }
<> 144:ef7eb2e8f9f7 643 }
AnnaBridge 167:e84263d55307 644 #if (USE_SPI_CRC != 0U)
<> 144:ef7eb2e8f9f7 645 /* Enable CRC Transmission */
AnnaBridge 167:e84263d55307 646 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<> 144:ef7eb2e8f9f7 647 {
AnnaBridge 167:e84263d55307 648 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
<> 144:ef7eb2e8f9f7 649 }
AnnaBridge 167:e84263d55307 650 #endif /* USE_SPI_CRC */
<> 144:ef7eb2e8f9f7 651
<> 144:ef7eb2e8f9f7 652 /* Check the end of the transaction */
AnnaBridge 167:e84263d55307 653 if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK)
<> 144:ef7eb2e8f9f7 654 {
<> 144:ef7eb2e8f9f7 655 hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
<> 144:ef7eb2e8f9f7 656 }
AnnaBridge 167:e84263d55307 657
AnnaBridge 173:e131a1973e81 658 if (hspi->Init.Direction == SPI_DIRECTION_1LINE) {
AnnaBridge 173:e131a1973e81 659 __HAL_SPI_DISABLE(hspi);
AnnaBridge 173:e131a1973e81 660 }
AnnaBridge 173:e131a1973e81 661
<> 144:ef7eb2e8f9f7 662 /* Clear overrun flag in 2 Lines communication mode because received is not read */
AnnaBridge 167:e84263d55307 663 if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
<> 144:ef7eb2e8f9f7 664 {
<> 144:ef7eb2e8f9f7 665 __HAL_SPI_CLEAR_OVRFLAG(hspi);
<> 144:ef7eb2e8f9f7 666 }
<> 144:ef7eb2e8f9f7 667
AnnaBridge 167:e84263d55307 668 if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
<> 144:ef7eb2e8f9f7 669 {
<> 144:ef7eb2e8f9f7 670 errorcode = HAL_ERROR;
<> 144:ef7eb2e8f9f7 671 }
<> 144:ef7eb2e8f9f7 672
<> 144:ef7eb2e8f9f7 673 error:
<> 144:ef7eb2e8f9f7 674 hspi->State = HAL_SPI_STATE_READY;
<> 144:ef7eb2e8f9f7 675 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 676 __HAL_UNLOCK(hspi);
<> 144:ef7eb2e8f9f7 677 return errorcode;
<> 144:ef7eb2e8f9f7 678 }
<> 144:ef7eb2e8f9f7 679
<> 144:ef7eb2e8f9f7 680 /**
<> 144:ef7eb2e8f9f7 681 * @brief Receive an amount of data in blocking mode.
<> 144:ef7eb2e8f9f7 682 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 683 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 684 * @param pData: pointer to data buffer
<> 144:ef7eb2e8f9f7 685 * @param Size: amount of data to be received
<> 144:ef7eb2e8f9f7 686 * @param Timeout: Timeout duration
<> 144:ef7eb2e8f9f7 687 * @retval HAL status
<> 144:ef7eb2e8f9f7 688 */
<> 144:ef7eb2e8f9f7 689 HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
<> 144:ef7eb2e8f9f7 690 {
AnnaBridge 167:e84263d55307 691 #if (USE_SPI_CRC != 0U)
AnnaBridge 167:e84263d55307 692 __IO uint16_t tmpreg = 0U;
AnnaBridge 167:e84263d55307 693 #endif /* USE_SPI_CRC */
AnnaBridge 167:e84263d55307 694 uint32_t tickstart = 0U;
<> 144:ef7eb2e8f9f7 695 HAL_StatusTypeDef errorcode = HAL_OK;
AnnaBridge 167:e84263d55307 696
AnnaBridge 167:e84263d55307 697
AnnaBridge 167:e84263d55307 698 if ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))
<> 144:ef7eb2e8f9f7 699 {
AnnaBridge 167:e84263d55307 700 hspi->State = HAL_SPI_STATE_BUSY_RX;
AnnaBridge 167:e84263d55307 701 /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
AnnaBridge 167:e84263d55307 702 return HAL_SPI_TransmitReceive(hspi, pData, pData, Size, Timeout);
<> 144:ef7eb2e8f9f7 703 }
<> 144:ef7eb2e8f9f7 704
<> 144:ef7eb2e8f9f7 705 /* Process Locked */
<> 144:ef7eb2e8f9f7 706 __HAL_LOCK(hspi);
<> 144:ef7eb2e8f9f7 707
AnnaBridge 167:e84263d55307 708 /* Init tickstart for timeout management*/
AnnaBridge 167:e84263d55307 709 tickstart = HAL_GetTick();
AnnaBridge 167:e84263d55307 710
AnnaBridge 167:e84263d55307 711 if (hspi->State != HAL_SPI_STATE_READY)
<> 144:ef7eb2e8f9f7 712 {
<> 144:ef7eb2e8f9f7 713 errorcode = HAL_BUSY;
<> 144:ef7eb2e8f9f7 714 goto error;
<> 144:ef7eb2e8f9f7 715 }
<> 144:ef7eb2e8f9f7 716
AnnaBridge 167:e84263d55307 717 if ((pData == NULL) || (Size == 0U))
<> 144:ef7eb2e8f9f7 718 {
<> 144:ef7eb2e8f9f7 719 errorcode = HAL_ERROR;
<> 144:ef7eb2e8f9f7 720 goto error;
<> 144:ef7eb2e8f9f7 721 }
<> 144:ef7eb2e8f9f7 722
AnnaBridge 167:e84263d55307 723 /* Set the transaction information */
<> 144:ef7eb2e8f9f7 724 hspi->State = HAL_SPI_STATE_BUSY_RX;
<> 144:ef7eb2e8f9f7 725 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
AnnaBridge 167:e84263d55307 726 hspi->pRxBuffPtr = (uint8_t *)pData;
<> 144:ef7eb2e8f9f7 727 hspi->RxXferSize = Size;
<> 144:ef7eb2e8f9f7 728 hspi->RxXferCount = Size;
AnnaBridge 167:e84263d55307 729
AnnaBridge 167:e84263d55307 730 /*Init field not used in handle to zero */
<> 144:ef7eb2e8f9f7 731 hspi->pTxBuffPtr = (uint8_t *)NULL;
AnnaBridge 167:e84263d55307 732 hspi->TxXferSize = 0U;
AnnaBridge 167:e84263d55307 733 hspi->TxXferCount = 0U;
AnnaBridge 167:e84263d55307 734 hspi->RxISR = NULL;
AnnaBridge 167:e84263d55307 735 hspi->TxISR = NULL;
AnnaBridge 167:e84263d55307 736
AnnaBridge 167:e84263d55307 737 #if (USE_SPI_CRC != 0U)
<> 144:ef7eb2e8f9f7 738 /* Reset CRC Calculation */
AnnaBridge 167:e84263d55307 739 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<> 144:ef7eb2e8f9f7 740 {
<> 144:ef7eb2e8f9f7 741 SPI_RESET_CRC(hspi);
<> 144:ef7eb2e8f9f7 742 /* this is done to handle the CRCNEXT before the latest data */
<> 144:ef7eb2e8f9f7 743 hspi->RxXferCount--;
<> 144:ef7eb2e8f9f7 744 }
AnnaBridge 167:e84263d55307 745 #endif /* USE_SPI_CRC */
AnnaBridge 167:e84263d55307 746
AnnaBridge 167:e84263d55307 747 /* Set the Rx Fifo threshold */
AnnaBridge 167:e84263d55307 748 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
<> 144:ef7eb2e8f9f7 749 {
<> 144:ef7eb2e8f9f7 750 /* set fiforxthresold according the reception data length: 16bit */
<> 144:ef7eb2e8f9f7 751 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
<> 144:ef7eb2e8f9f7 752 }
<> 144:ef7eb2e8f9f7 753 else
<> 144:ef7eb2e8f9f7 754 {
<> 144:ef7eb2e8f9f7 755 /* set fiforxthresold according the reception data length: 8bit */
<> 144:ef7eb2e8f9f7 756 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
<> 144:ef7eb2e8f9f7 757 }
<> 144:ef7eb2e8f9f7 758
AnnaBridge 167:e84263d55307 759 /* Configure communication direction: 1Line */
AnnaBridge 167:e84263d55307 760 if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
<> 144:ef7eb2e8f9f7 761 {
<> 144:ef7eb2e8f9f7 762 SPI_1LINE_RX(hspi);
<> 144:ef7eb2e8f9f7 763 }
<> 144:ef7eb2e8f9f7 764
<> 144:ef7eb2e8f9f7 765 /* Check if the SPI is already enabled */
AnnaBridge 167:e84263d55307 766 if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
<> 144:ef7eb2e8f9f7 767 {
<> 144:ef7eb2e8f9f7 768 /* Enable SPI peripheral */
<> 144:ef7eb2e8f9f7 769 __HAL_SPI_ENABLE(hspi);
<> 144:ef7eb2e8f9f7 770 }
<> 144:ef7eb2e8f9f7 771
AnnaBridge 167:e84263d55307 772 /* Receive data in 8 Bit mode */
AnnaBridge 167:e84263d55307 773 if (hspi->Init.DataSize <= SPI_DATASIZE_8BIT)
<> 144:ef7eb2e8f9f7 774 {
<> 144:ef7eb2e8f9f7 775 /* Transfer loop */
AnnaBridge 167:e84263d55307 776 while (hspi->RxXferCount > 0U)
<> 144:ef7eb2e8f9f7 777 {
<> 144:ef7eb2e8f9f7 778 /* Check the RXNE flag */
AnnaBridge 167:e84263d55307 779 if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE))
<> 144:ef7eb2e8f9f7 780 {
<> 144:ef7eb2e8f9f7 781 /* read the received data */
AnnaBridge 167:e84263d55307 782 (* (uint8_t *)pData) = *(__IO uint8_t *)&hspi->Instance->DR;
AnnaBridge 167:e84263d55307 783 pData += sizeof(uint8_t);
<> 144:ef7eb2e8f9f7 784 hspi->RxXferCount--;
<> 144:ef7eb2e8f9f7 785 }
<> 144:ef7eb2e8f9f7 786 else
<> 144:ef7eb2e8f9f7 787 {
<> 144:ef7eb2e8f9f7 788 /* Timeout management */
AnnaBridge 167:e84263d55307 789 if ((Timeout == 0U) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick() - tickstart) >= Timeout)))
<> 144:ef7eb2e8f9f7 790 {
<> 144:ef7eb2e8f9f7 791 errorcode = HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 792 goto error;
<> 144:ef7eb2e8f9f7 793 }
<> 144:ef7eb2e8f9f7 794 }
<> 144:ef7eb2e8f9f7 795 }
<> 144:ef7eb2e8f9f7 796 }
<> 144:ef7eb2e8f9f7 797 else
<> 144:ef7eb2e8f9f7 798 {
<> 144:ef7eb2e8f9f7 799 /* Transfer loop */
AnnaBridge 167:e84263d55307 800 while (hspi->RxXferCount > 0U)
<> 144:ef7eb2e8f9f7 801 {
<> 144:ef7eb2e8f9f7 802 /* Check the RXNE flag */
AnnaBridge 167:e84263d55307 803 if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE))
<> 144:ef7eb2e8f9f7 804 {
AnnaBridge 167:e84263d55307 805 *((uint16_t *)pData) = hspi->Instance->DR;
AnnaBridge 167:e84263d55307 806 pData += sizeof(uint16_t);
<> 144:ef7eb2e8f9f7 807 hspi->RxXferCount--;
<> 144:ef7eb2e8f9f7 808 }
<> 144:ef7eb2e8f9f7 809 else
<> 144:ef7eb2e8f9f7 810 {
<> 144:ef7eb2e8f9f7 811 /* Timeout management */
AnnaBridge 167:e84263d55307 812 if ((Timeout == 0U) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick() - tickstart) >= Timeout)))
<> 144:ef7eb2e8f9f7 813 {
<> 144:ef7eb2e8f9f7 814 errorcode = HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 815 goto error;
<> 144:ef7eb2e8f9f7 816 }
<> 144:ef7eb2e8f9f7 817 }
<> 144:ef7eb2e8f9f7 818 }
<> 144:ef7eb2e8f9f7 819 }
<> 144:ef7eb2e8f9f7 820
AnnaBridge 167:e84263d55307 821 #if (USE_SPI_CRC != 0U)
<> 144:ef7eb2e8f9f7 822 /* Handle the CRC Transmission */
AnnaBridge 167:e84263d55307 823 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<> 144:ef7eb2e8f9f7 824 {
<> 144:ef7eb2e8f9f7 825 /* freeze the CRC before the latest data */
AnnaBridge 167:e84263d55307 826 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
<> 144:ef7eb2e8f9f7 827
<> 144:ef7eb2e8f9f7 828 /* Read the latest data */
AnnaBridge 167:e84263d55307 829 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
<> 144:ef7eb2e8f9f7 830 {
<> 144:ef7eb2e8f9f7 831 /* the latest data has not been received */
<> 144:ef7eb2e8f9f7 832 errorcode = HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 833 goto error;
<> 144:ef7eb2e8f9f7 834 }
<> 144:ef7eb2e8f9f7 835
<> 144:ef7eb2e8f9f7 836 /* Receive last data in 16 Bit mode */
AnnaBridge 167:e84263d55307 837 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
<> 144:ef7eb2e8f9f7 838 {
AnnaBridge 167:e84263d55307 839 *((uint16_t *)pData) = hspi->Instance->DR;
<> 144:ef7eb2e8f9f7 840 }
<> 144:ef7eb2e8f9f7 841 /* Receive last data in 8 Bit mode */
<> 144:ef7eb2e8f9f7 842 else
<> 144:ef7eb2e8f9f7 843 {
AnnaBridge 167:e84263d55307 844 (*(uint8_t *)pData) = *(__IO uint8_t *)&hspi->Instance->DR;
<> 144:ef7eb2e8f9f7 845 }
<> 144:ef7eb2e8f9f7 846
AnnaBridge 167:e84263d55307 847 /* Wait the CRC data */
AnnaBridge 167:e84263d55307 848 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
<> 144:ef7eb2e8f9f7 849 {
AnnaBridge 167:e84263d55307 850 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
<> 144:ef7eb2e8f9f7 851 errorcode = HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 852 goto error;
<> 144:ef7eb2e8f9f7 853 }
<> 144:ef7eb2e8f9f7 854
AnnaBridge 167:e84263d55307 855 /* Read CRC to Flush DR and RXNE flag */
AnnaBridge 167:e84263d55307 856 if (hspi->Init.DataSize == SPI_DATASIZE_16BIT)
<> 144:ef7eb2e8f9f7 857 {
<> 144:ef7eb2e8f9f7 858 tmpreg = hspi->Instance->DR;
AnnaBridge 167:e84263d55307 859 /* To avoid GCC warning */
AnnaBridge 167:e84263d55307 860 UNUSED(tmpreg);
<> 144:ef7eb2e8f9f7 861 }
<> 144:ef7eb2e8f9f7 862 else
<> 144:ef7eb2e8f9f7 863 {
<> 144:ef7eb2e8f9f7 864 tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
AnnaBridge 167:e84263d55307 865 /* To avoid GCC warning */
AnnaBridge 167:e84263d55307 866 UNUSED(tmpreg);
AnnaBridge 167:e84263d55307 867
AnnaBridge 167:e84263d55307 868 if ((hspi->Init.DataSize == SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))
<> 144:ef7eb2e8f9f7 869 {
AnnaBridge 167:e84263d55307 870 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout, tickstart) != HAL_OK)
<> 144:ef7eb2e8f9f7 871 {
<> 144:ef7eb2e8f9f7 872 /* Error on the CRC reception */
AnnaBridge 167:e84263d55307 873 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
<> 144:ef7eb2e8f9f7 874 errorcode = HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 875 goto error;
<> 144:ef7eb2e8f9f7 876 }
<> 144:ef7eb2e8f9f7 877 tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
AnnaBridge 167:e84263d55307 878 /* To avoid GCC warning */
AnnaBridge 167:e84263d55307 879 UNUSED(tmpreg);
<> 144:ef7eb2e8f9f7 880 }
<> 144:ef7eb2e8f9f7 881 }
<> 144:ef7eb2e8f9f7 882 }
AnnaBridge 167:e84263d55307 883 #endif /* USE_SPI_CRC */
AnnaBridge 167:e84263d55307 884
<> 144:ef7eb2e8f9f7 885 /* Check the end of the transaction */
AnnaBridge 167:e84263d55307 886 if (SPI_EndRxTransaction(hspi, Timeout, tickstart) != HAL_OK)
<> 144:ef7eb2e8f9f7 887 {
<> 144:ef7eb2e8f9f7 888 hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
<> 144:ef7eb2e8f9f7 889 }
<> 144:ef7eb2e8f9f7 890
AnnaBridge 167:e84263d55307 891 #if (USE_SPI_CRC != 0U)
<> 144:ef7eb2e8f9f7 892 /* Check if CRC error occurred */
AnnaBridge 167:e84263d55307 893 if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))
<> 144:ef7eb2e8f9f7 894 {
AnnaBridge 167:e84263d55307 895 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
<> 144:ef7eb2e8f9f7 896 __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
<> 144:ef7eb2e8f9f7 897 }
AnnaBridge 167:e84263d55307 898 #endif /* USE_SPI_CRC */
AnnaBridge 167:e84263d55307 899
AnnaBridge 167:e84263d55307 900 if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
<> 144:ef7eb2e8f9f7 901 {
<> 144:ef7eb2e8f9f7 902 errorcode = HAL_ERROR;
<> 144:ef7eb2e8f9f7 903 }
<> 144:ef7eb2e8f9f7 904
<> 144:ef7eb2e8f9f7 905 error :
<> 144:ef7eb2e8f9f7 906 hspi->State = HAL_SPI_STATE_READY;
<> 144:ef7eb2e8f9f7 907 __HAL_UNLOCK(hspi);
<> 144:ef7eb2e8f9f7 908 return errorcode;
<> 144:ef7eb2e8f9f7 909 }
<> 144:ef7eb2e8f9f7 910
<> 144:ef7eb2e8f9f7 911 /**
<> 144:ef7eb2e8f9f7 912 * @brief Transmit and Receive an amount of data in blocking mode.
<> 144:ef7eb2e8f9f7 913 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 914 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 915 * @param pTxData: pointer to transmission data buffer
<> 144:ef7eb2e8f9f7 916 * @param pRxData: pointer to reception data buffer
<> 144:ef7eb2e8f9f7 917 * @param Size: amount of data to be sent and received
<> 144:ef7eb2e8f9f7 918 * @param Timeout: Timeout duration
<> 144:ef7eb2e8f9f7 919 * @retval HAL status
<> 144:ef7eb2e8f9f7 920 */
AnnaBridge 167:e84263d55307 921 HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size,
AnnaBridge 167:e84263d55307 922 uint32_t Timeout)
<> 144:ef7eb2e8f9f7 923 {
AnnaBridge 167:e84263d55307 924 uint32_t tmp = 0U, tmp1 = 0U;
AnnaBridge 167:e84263d55307 925 #if (USE_SPI_CRC != 0U)
AnnaBridge 167:e84263d55307 926 __IO uint16_t tmpreg = 0U;
AnnaBridge 167:e84263d55307 927 #endif /* USE_SPI_CRC */
AnnaBridge 167:e84263d55307 928 uint32_t tickstart = 0U;
AnnaBridge 167:e84263d55307 929 /* Variable used to alternate Rx and Tx during transfer */
AnnaBridge 167:e84263d55307 930 uint32_t txallowed = 1U;
<> 144:ef7eb2e8f9f7 931 HAL_StatusTypeDef errorcode = HAL_OK;
AnnaBridge 167:e84263d55307 932
AnnaBridge 167:e84263d55307 933
AnnaBridge 167:e84263d55307 934 /* Check Direction parameter */
<> 144:ef7eb2e8f9f7 935 assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
<> 144:ef7eb2e8f9f7 936
<> 144:ef7eb2e8f9f7 937 /* Process Locked */
<> 144:ef7eb2e8f9f7 938 __HAL_LOCK(hspi);
<> 144:ef7eb2e8f9f7 939
AnnaBridge 167:e84263d55307 940 /* Init tickstart for timeout management*/
AnnaBridge 167:e84263d55307 941 tickstart = HAL_GetTick();
AnnaBridge 167:e84263d55307 942
AnnaBridge 167:e84263d55307 943 tmp = hspi->State;
AnnaBridge 167:e84263d55307 944 tmp1 = hspi->Init.Mode;
AnnaBridge 167:e84263d55307 945
AnnaBridge 167:e84263d55307 946 if (!((tmp == HAL_SPI_STATE_READY) || \
AnnaBridge 167:e84263d55307 947 ((tmp1 == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp == HAL_SPI_STATE_BUSY_RX))))
<> 144:ef7eb2e8f9f7 948 {
<> 144:ef7eb2e8f9f7 949 errorcode = HAL_BUSY;
<> 144:ef7eb2e8f9f7 950 goto error;
<> 144:ef7eb2e8f9f7 951 }
<> 144:ef7eb2e8f9f7 952
AnnaBridge 167:e84263d55307 953 if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
<> 144:ef7eb2e8f9f7 954 {
<> 144:ef7eb2e8f9f7 955 errorcode = HAL_ERROR;
<> 144:ef7eb2e8f9f7 956 goto error;
<> 144:ef7eb2e8f9f7 957 }
<> 144:ef7eb2e8f9f7 958
AnnaBridge 167:e84263d55307 959 /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
AnnaBridge 167:e84263d55307 960 if (hspi->State != HAL_SPI_STATE_BUSY_RX)
AnnaBridge 167:e84263d55307 961 {
AnnaBridge 167:e84263d55307 962 hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
AnnaBridge 167:e84263d55307 963 }
AnnaBridge 167:e84263d55307 964
AnnaBridge 167:e84263d55307 965 /* Set the transaction information */
<> 144:ef7eb2e8f9f7 966 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
AnnaBridge 167:e84263d55307 967 hspi->pRxBuffPtr = (uint8_t *)pRxData;
<> 144:ef7eb2e8f9f7 968 hspi->RxXferCount = Size;
<> 144:ef7eb2e8f9f7 969 hspi->RxXferSize = Size;
AnnaBridge 167:e84263d55307 970 hspi->pTxBuffPtr = (uint8_t *)pTxData;
<> 144:ef7eb2e8f9f7 971 hspi->TxXferCount = Size;
<> 144:ef7eb2e8f9f7 972 hspi->TxXferSize = Size;
<> 144:ef7eb2e8f9f7 973
AnnaBridge 167:e84263d55307 974 /*Init field not used in handle to zero */
AnnaBridge 167:e84263d55307 975 hspi->RxISR = NULL;
AnnaBridge 167:e84263d55307 976 hspi->TxISR = NULL;
AnnaBridge 167:e84263d55307 977
AnnaBridge 167:e84263d55307 978 #if (USE_SPI_CRC != 0U)
<> 144:ef7eb2e8f9f7 979 /* Reset CRC Calculation */
AnnaBridge 167:e84263d55307 980 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<> 144:ef7eb2e8f9f7 981 {
<> 144:ef7eb2e8f9f7 982 SPI_RESET_CRC(hspi);
<> 144:ef7eb2e8f9f7 983 }
AnnaBridge 167:e84263d55307 984 #endif /* USE_SPI_CRC */
AnnaBridge 167:e84263d55307 985
AnnaBridge 167:e84263d55307 986 /* Set the Rx Fifo threshold */
AnnaBridge 167:e84263d55307 987 if ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (hspi->RxXferCount > 1U))
<> 144:ef7eb2e8f9f7 988 {
<> 144:ef7eb2e8f9f7 989 /* set fiforxthreshold according the reception data length: 16bit */
<> 144:ef7eb2e8f9f7 990 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
<> 144:ef7eb2e8f9f7 991 }
<> 144:ef7eb2e8f9f7 992 else
<> 144:ef7eb2e8f9f7 993 {
<> 144:ef7eb2e8f9f7 994 /* set fiforxthreshold according the reception data length: 8bit */
<> 144:ef7eb2e8f9f7 995 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
<> 144:ef7eb2e8f9f7 996 }
<> 144:ef7eb2e8f9f7 997
<> 144:ef7eb2e8f9f7 998 /* Check if the SPI is already enabled */
AnnaBridge 167:e84263d55307 999 if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
<> 144:ef7eb2e8f9f7 1000 {
<> 144:ef7eb2e8f9f7 1001 /* Enable SPI peripheral */
<> 144:ef7eb2e8f9f7 1002 __HAL_SPI_ENABLE(hspi);
<> 144:ef7eb2e8f9f7 1003 }
<> 144:ef7eb2e8f9f7 1004
<> 144:ef7eb2e8f9f7 1005 /* Transmit and Receive data in 16 Bit mode */
AnnaBridge 167:e84263d55307 1006 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
<> 144:ef7eb2e8f9f7 1007 {
AnnaBridge 167:e84263d55307 1008 if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (hspi->TxXferCount == 0x01U))
AnnaBridge 167:e84263d55307 1009 {
AnnaBridge 167:e84263d55307 1010 hspi->Instance->DR = *((uint16_t *)pTxData);
AnnaBridge 167:e84263d55307 1011 pTxData += sizeof(uint16_t);
AnnaBridge 167:e84263d55307 1012 hspi->TxXferCount--;
AnnaBridge 167:e84263d55307 1013 }
AnnaBridge 167:e84263d55307 1014 while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U))
<> 144:ef7eb2e8f9f7 1015 {
<> 144:ef7eb2e8f9f7 1016 /* Check TXE flag */
AnnaBridge 167:e84263d55307 1017 if (txallowed && (hspi->TxXferCount > 0U) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)))
<> 144:ef7eb2e8f9f7 1018 {
AnnaBridge 167:e84263d55307 1019 hspi->Instance->DR = *((uint16_t *)pTxData);
AnnaBridge 167:e84263d55307 1020 pTxData += sizeof(uint16_t);
<> 144:ef7eb2e8f9f7 1021 hspi->TxXferCount--;
AnnaBridge 167:e84263d55307 1022 /* Next Data is a reception (Rx). Tx not allowed */
AnnaBridge 167:e84263d55307 1023 txallowed = 0U;
AnnaBridge 167:e84263d55307 1024
AnnaBridge 167:e84263d55307 1025 #if (USE_SPI_CRC != 0U)
<> 144:ef7eb2e8f9f7 1026 /* Enable CRC Transmission */
AnnaBridge 167:e84263d55307 1027 if ((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
<> 144:ef7eb2e8f9f7 1028 {
AnnaBridge 167:e84263d55307 1029 /* Set NSS Soft to received correctly the CRC on slave mode with NSS pulse activated */
AnnaBridge 167:e84263d55307 1030 if (((hspi->Instance->CR1 & SPI_CR1_MSTR) == 0U) && ((hspi->Instance->CR2 & SPI_CR2_NSSP) == SPI_CR2_NSSP))
AnnaBridge 167:e84263d55307 1031 {
AnnaBridge 167:e84263d55307 1032 SET_BIT(hspi->Instance->CR1, SPI_CR1_SSM);
AnnaBridge 167:e84263d55307 1033 }
AnnaBridge 167:e84263d55307 1034 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
<> 144:ef7eb2e8f9f7 1035 }
AnnaBridge 167:e84263d55307 1036 #endif /* USE_SPI_CRC */
<> 144:ef7eb2e8f9f7 1037 }
<> 144:ef7eb2e8f9f7 1038
<> 144:ef7eb2e8f9f7 1039 /* Check RXNE flag */
AnnaBridge 167:e84263d55307 1040 if ((hspi->RxXferCount > 0U) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)))
<> 144:ef7eb2e8f9f7 1041 {
AnnaBridge 167:e84263d55307 1042 *((uint16_t *)pRxData) = hspi->Instance->DR;
AnnaBridge 167:e84263d55307 1043 pRxData += sizeof(uint16_t);
<> 144:ef7eb2e8f9f7 1044 hspi->RxXferCount--;
AnnaBridge 167:e84263d55307 1045 /* Next Data is a Transmission (Tx). Tx is allowed */
AnnaBridge 167:e84263d55307 1046 txallowed = 1U;
<> 144:ef7eb2e8f9f7 1047 }
AnnaBridge 167:e84263d55307 1048 if ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick() - tickstart) >= Timeout))
<> 144:ef7eb2e8f9f7 1049 {
<> 144:ef7eb2e8f9f7 1050 errorcode = HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 1051 goto error;
<> 144:ef7eb2e8f9f7 1052 }
<> 144:ef7eb2e8f9f7 1053 }
<> 144:ef7eb2e8f9f7 1054 }
<> 144:ef7eb2e8f9f7 1055 /* Transmit and Receive data in 8 Bit mode */
<> 144:ef7eb2e8f9f7 1056 else
<> 144:ef7eb2e8f9f7 1057 {
AnnaBridge 167:e84263d55307 1058 if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (hspi->TxXferCount == 0x01U))
AnnaBridge 167:e84263d55307 1059 {
AnnaBridge 167:e84263d55307 1060 if (hspi->TxXferCount > 1U)
AnnaBridge 167:e84263d55307 1061 {
AnnaBridge 167:e84263d55307 1062 hspi->Instance->DR = *((uint16_t *)pTxData);
AnnaBridge 167:e84263d55307 1063 pTxData += sizeof(uint16_t);
AnnaBridge 167:e84263d55307 1064 hspi->TxXferCount -= 2U;
AnnaBridge 167:e84263d55307 1065 }
AnnaBridge 167:e84263d55307 1066 else
AnnaBridge 167:e84263d55307 1067 {
AnnaBridge 167:e84263d55307 1068 *(__IO uint8_t *)&hspi->Instance->DR = (*pTxData++);
AnnaBridge 167:e84263d55307 1069 hspi->TxXferCount--;
AnnaBridge 167:e84263d55307 1070 }
AnnaBridge 167:e84263d55307 1071 }
AnnaBridge 167:e84263d55307 1072 while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U))
<> 144:ef7eb2e8f9f7 1073 {
<> 144:ef7eb2e8f9f7 1074 /* check TXE flag */
AnnaBridge 167:e84263d55307 1075 if (txallowed && (hspi->TxXferCount > 0U) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)))
<> 144:ef7eb2e8f9f7 1076 {
AnnaBridge 167:e84263d55307 1077 if (hspi->TxXferCount > 1U)
<> 144:ef7eb2e8f9f7 1078 {
AnnaBridge 167:e84263d55307 1079 hspi->Instance->DR = *((uint16_t *)pTxData);
AnnaBridge 167:e84263d55307 1080 pTxData += sizeof(uint16_t);
AnnaBridge 167:e84263d55307 1081 hspi->TxXferCount -= 2U;
<> 144:ef7eb2e8f9f7 1082 }
<> 144:ef7eb2e8f9f7 1083 else
<> 144:ef7eb2e8f9f7 1084 {
AnnaBridge 167:e84263d55307 1085 *(__IO uint8_t *)&hspi->Instance->DR = (*pTxData++);
<> 144:ef7eb2e8f9f7 1086 hspi->TxXferCount--;
<> 144:ef7eb2e8f9f7 1087 }
AnnaBridge 167:e84263d55307 1088 /* Next Data is a reception (Rx). Tx not allowed */
AnnaBridge 167:e84263d55307 1089 txallowed = 0U;
AnnaBridge 167:e84263d55307 1090
AnnaBridge 167:e84263d55307 1091 #if (USE_SPI_CRC != 0U)
<> 144:ef7eb2e8f9f7 1092 /* Enable CRC Transmission */
AnnaBridge 167:e84263d55307 1093 if ((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
<> 144:ef7eb2e8f9f7 1094 {
AnnaBridge 167:e84263d55307 1095 /* Set NSS Soft to received correctly the CRC on slave mode with NSS pulse activated */
AnnaBridge 167:e84263d55307 1096 if (((hspi->Instance->CR1 & SPI_CR1_MSTR) == 0U) && ((hspi->Instance->CR2 & SPI_CR2_NSSP) == SPI_CR2_NSSP))
AnnaBridge 167:e84263d55307 1097 {
AnnaBridge 167:e84263d55307 1098 SET_BIT(hspi->Instance->CR1, SPI_CR1_SSM);
AnnaBridge 167:e84263d55307 1099 }
AnnaBridge 167:e84263d55307 1100 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
<> 144:ef7eb2e8f9f7 1101 }
AnnaBridge 167:e84263d55307 1102 #endif /* USE_SPI_CRC */
<> 144:ef7eb2e8f9f7 1103 }
<> 144:ef7eb2e8f9f7 1104
<> 144:ef7eb2e8f9f7 1105 /* Wait until RXNE flag is reset */
AnnaBridge 167:e84263d55307 1106 if ((hspi->RxXferCount > 0U) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)))
<> 144:ef7eb2e8f9f7 1107 {
AnnaBridge 167:e84263d55307 1108 if (hspi->RxXferCount > 1U)
<> 144:ef7eb2e8f9f7 1109 {
AnnaBridge 167:e84263d55307 1110 *((uint16_t *)pRxData) = hspi->Instance->DR;
AnnaBridge 167:e84263d55307 1111 pRxData += sizeof(uint16_t);
AnnaBridge 167:e84263d55307 1112 hspi->RxXferCount -= 2U;
AnnaBridge 167:e84263d55307 1113 if (hspi->RxXferCount <= 1U)
<> 144:ef7eb2e8f9f7 1114 {
<> 144:ef7eb2e8f9f7 1115 /* set fiforxthresold before to switch on 8 bit data size */
<> 144:ef7eb2e8f9f7 1116 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
<> 144:ef7eb2e8f9f7 1117 }
<> 144:ef7eb2e8f9f7 1118 }
<> 144:ef7eb2e8f9f7 1119 else
<> 144:ef7eb2e8f9f7 1120 {
AnnaBridge 167:e84263d55307 1121 (*(uint8_t *)pRxData++) = *(__IO uint8_t *)&hspi->Instance->DR;
<> 144:ef7eb2e8f9f7 1122 hspi->RxXferCount--;
<> 144:ef7eb2e8f9f7 1123 }
AnnaBridge 167:e84263d55307 1124 /* Next Data is a Transmission (Tx). Tx is allowed */
AnnaBridge 167:e84263d55307 1125 txallowed = 1U;
<> 144:ef7eb2e8f9f7 1126 }
AnnaBridge 167:e84263d55307 1127 if ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick() - tickstart) >= Timeout))
<> 144:ef7eb2e8f9f7 1128 {
<> 144:ef7eb2e8f9f7 1129 errorcode = HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 1130 goto error;
<> 144:ef7eb2e8f9f7 1131 }
<> 144:ef7eb2e8f9f7 1132 }
<> 144:ef7eb2e8f9f7 1133 }
<> 144:ef7eb2e8f9f7 1134
AnnaBridge 167:e84263d55307 1135 #if (USE_SPI_CRC != 0U)
<> 144:ef7eb2e8f9f7 1136 /* Read CRC from DR to close CRC calculation process */
AnnaBridge 167:e84263d55307 1137 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<> 144:ef7eb2e8f9f7 1138 {
<> 144:ef7eb2e8f9f7 1139 /* Wait until TXE flag */
AnnaBridge 167:e84263d55307 1140 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
<> 144:ef7eb2e8f9f7 1141 {
<> 144:ef7eb2e8f9f7 1142 /* Error on the CRC reception */
AnnaBridge 167:e84263d55307 1143 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
<> 144:ef7eb2e8f9f7 1144 errorcode = HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 1145 goto error;
<> 144:ef7eb2e8f9f7 1146 }
AnnaBridge 167:e84263d55307 1147 /* Read CRC */
AnnaBridge 167:e84263d55307 1148 if (hspi->Init.DataSize == SPI_DATASIZE_16BIT)
<> 144:ef7eb2e8f9f7 1149 {
<> 144:ef7eb2e8f9f7 1150 tmpreg = hspi->Instance->DR;
AnnaBridge 167:e84263d55307 1151 /* To avoid GCC warning */
AnnaBridge 167:e84263d55307 1152 UNUSED(tmpreg);
<> 144:ef7eb2e8f9f7 1153 }
<> 144:ef7eb2e8f9f7 1154 else
<> 144:ef7eb2e8f9f7 1155 {
<> 144:ef7eb2e8f9f7 1156 tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
AnnaBridge 167:e84263d55307 1157 /* To avoid GCC warning */
AnnaBridge 167:e84263d55307 1158 UNUSED(tmpreg);
AnnaBridge 167:e84263d55307 1159
AnnaBridge 167:e84263d55307 1160 if (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)
<> 144:ef7eb2e8f9f7 1161 {
AnnaBridge 167:e84263d55307 1162 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
<> 144:ef7eb2e8f9f7 1163 {
<> 144:ef7eb2e8f9f7 1164 /* Error on the CRC reception */
AnnaBridge 167:e84263d55307 1165 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
<> 144:ef7eb2e8f9f7 1166 errorcode = HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 1167 goto error;
<> 144:ef7eb2e8f9f7 1168 }
<> 144:ef7eb2e8f9f7 1169 tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
AnnaBridge 167:e84263d55307 1170 /* To avoid GCC warning */
AnnaBridge 167:e84263d55307 1171 UNUSED(tmpreg);
<> 144:ef7eb2e8f9f7 1172 }
<> 144:ef7eb2e8f9f7 1173 }
<> 144:ef7eb2e8f9f7 1174 }
<> 144:ef7eb2e8f9f7 1175
<> 144:ef7eb2e8f9f7 1176 /* Check if CRC error occurred */
AnnaBridge 167:e84263d55307 1177 if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))
<> 144:ef7eb2e8f9f7 1178 {
AnnaBridge 167:e84263d55307 1179 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
<> 144:ef7eb2e8f9f7 1180 /* Clear CRC Flag */
<> 144:ef7eb2e8f9f7 1181 __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
<> 144:ef7eb2e8f9f7 1182
<> 144:ef7eb2e8f9f7 1183 errorcode = HAL_ERROR;
<> 144:ef7eb2e8f9f7 1184 }
AnnaBridge 167:e84263d55307 1185 #endif /* USE_SPI_CRC */
<> 144:ef7eb2e8f9f7 1186
<> 144:ef7eb2e8f9f7 1187 /* Check the end of the transaction */
AnnaBridge 167:e84263d55307 1188 if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK)
<> 144:ef7eb2e8f9f7 1189 {
<> 144:ef7eb2e8f9f7 1190 hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
<> 144:ef7eb2e8f9f7 1191 }
<> 144:ef7eb2e8f9f7 1192
AnnaBridge 167:e84263d55307 1193 if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
<> 144:ef7eb2e8f9f7 1194 {
<> 144:ef7eb2e8f9f7 1195 errorcode = HAL_ERROR;
<> 144:ef7eb2e8f9f7 1196 }
<> 144:ef7eb2e8f9f7 1197
<> 144:ef7eb2e8f9f7 1198 error :
<> 144:ef7eb2e8f9f7 1199 hspi->State = HAL_SPI_STATE_READY;
<> 144:ef7eb2e8f9f7 1200 __HAL_UNLOCK(hspi);
<> 144:ef7eb2e8f9f7 1201 return errorcode;
<> 144:ef7eb2e8f9f7 1202 }
<> 144:ef7eb2e8f9f7 1203
<> 144:ef7eb2e8f9f7 1204 /**
<> 144:ef7eb2e8f9f7 1205 * @brief Transmit an amount of data in non-blocking mode with Interrupt.
<> 144:ef7eb2e8f9f7 1206 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1207 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 1208 * @param pData: pointer to data buffer
<> 144:ef7eb2e8f9f7 1209 * @param Size: amount of data to be sent
<> 144:ef7eb2e8f9f7 1210 * @retval HAL status
<> 144:ef7eb2e8f9f7 1211 */
<> 144:ef7eb2e8f9f7 1212 HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
<> 144:ef7eb2e8f9f7 1213 {
<> 144:ef7eb2e8f9f7 1214 HAL_StatusTypeDef errorcode = HAL_OK;
AnnaBridge 167:e84263d55307 1215
AnnaBridge 167:e84263d55307 1216
AnnaBridge 167:e84263d55307 1217 /* Check Direction parameter */
<> 144:ef7eb2e8f9f7 1218 assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
<> 144:ef7eb2e8f9f7 1219
<> 144:ef7eb2e8f9f7 1220 /* Process Locked */
<> 144:ef7eb2e8f9f7 1221 __HAL_LOCK(hspi);
<> 144:ef7eb2e8f9f7 1222
AnnaBridge 167:e84263d55307 1223 if ((pData == NULL) || (Size == 0U))
<> 144:ef7eb2e8f9f7 1224 {
<> 144:ef7eb2e8f9f7 1225 errorcode = HAL_ERROR;
<> 144:ef7eb2e8f9f7 1226 goto error;
<> 144:ef7eb2e8f9f7 1227 }
<> 144:ef7eb2e8f9f7 1228
AnnaBridge 167:e84263d55307 1229 if (hspi->State != HAL_SPI_STATE_READY)
<> 144:ef7eb2e8f9f7 1230 {
<> 144:ef7eb2e8f9f7 1231 errorcode = HAL_BUSY;
<> 144:ef7eb2e8f9f7 1232 goto error;
<> 144:ef7eb2e8f9f7 1233 }
<> 144:ef7eb2e8f9f7 1234
AnnaBridge 167:e84263d55307 1235 /* Set the transaction information */
<> 144:ef7eb2e8f9f7 1236 hspi->State = HAL_SPI_STATE_BUSY_TX;
<> 144:ef7eb2e8f9f7 1237 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
AnnaBridge 167:e84263d55307 1238 hspi->pTxBuffPtr = (uint8_t *)pData;
<> 144:ef7eb2e8f9f7 1239 hspi->TxXferSize = Size;
<> 144:ef7eb2e8f9f7 1240 hspi->TxXferCount = Size;
AnnaBridge 167:e84263d55307 1241
AnnaBridge 167:e84263d55307 1242 /* Init field not used in handle to zero */
<> 144:ef7eb2e8f9f7 1243 hspi->pRxBuffPtr = (uint8_t *)NULL;
AnnaBridge 167:e84263d55307 1244 hspi->RxXferSize = 0U;
AnnaBridge 167:e84263d55307 1245 hspi->RxXferCount = 0U;
AnnaBridge 167:e84263d55307 1246 hspi->RxISR = NULL;
<> 144:ef7eb2e8f9f7 1247
<> 144:ef7eb2e8f9f7 1248 /* Set the function for IT treatment */
AnnaBridge 167:e84263d55307 1249 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
<> 144:ef7eb2e8f9f7 1250 {
<> 144:ef7eb2e8f9f7 1251 hspi->TxISR = SPI_TxISR_16BIT;
<> 144:ef7eb2e8f9f7 1252 }
<> 144:ef7eb2e8f9f7 1253 else
<> 144:ef7eb2e8f9f7 1254 {
<> 144:ef7eb2e8f9f7 1255 hspi->TxISR = SPI_TxISR_8BIT;
<> 144:ef7eb2e8f9f7 1256 }
<> 144:ef7eb2e8f9f7 1257
<> 144:ef7eb2e8f9f7 1258 /* Configure communication direction : 1Line */
AnnaBridge 167:e84263d55307 1259 if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
<> 144:ef7eb2e8f9f7 1260 {
<> 144:ef7eb2e8f9f7 1261 SPI_1LINE_TX(hspi);
<> 144:ef7eb2e8f9f7 1262 }
<> 144:ef7eb2e8f9f7 1263
AnnaBridge 167:e84263d55307 1264 #if (USE_SPI_CRC != 0U)
<> 144:ef7eb2e8f9f7 1265 /* Reset CRC Calculation */
AnnaBridge 167:e84263d55307 1266 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<> 144:ef7eb2e8f9f7 1267 {
<> 144:ef7eb2e8f9f7 1268 SPI_RESET_CRC(hspi);
<> 144:ef7eb2e8f9f7 1269 }
AnnaBridge 167:e84263d55307 1270 #endif /* USE_SPI_CRC */
<> 144:ef7eb2e8f9f7 1271
<> 144:ef7eb2e8f9f7 1272 /* Enable TXE and ERR interrupt */
AnnaBridge 167:e84263d55307 1273 __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR));
<> 144:ef7eb2e8f9f7 1274
<> 144:ef7eb2e8f9f7 1275
<> 144:ef7eb2e8f9f7 1276 /* Check if the SPI is already enabled */
AnnaBridge 167:e84263d55307 1277 if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
<> 144:ef7eb2e8f9f7 1278 {
<> 144:ef7eb2e8f9f7 1279 /* Enable SPI peripheral */
<> 144:ef7eb2e8f9f7 1280 __HAL_SPI_ENABLE(hspi);
<> 144:ef7eb2e8f9f7 1281 }
<> 144:ef7eb2e8f9f7 1282
<> 144:ef7eb2e8f9f7 1283 error :
<> 144:ef7eb2e8f9f7 1284 __HAL_UNLOCK(hspi);
<> 144:ef7eb2e8f9f7 1285 return errorcode;
<> 144:ef7eb2e8f9f7 1286 }
<> 144:ef7eb2e8f9f7 1287
<> 144:ef7eb2e8f9f7 1288 /**
<> 144:ef7eb2e8f9f7 1289 * @brief Receive an amount of data in non-blocking mode with Interrupt.
<> 144:ef7eb2e8f9f7 1290 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1291 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 1292 * @param pData: pointer to data buffer
<> 144:ef7eb2e8f9f7 1293 * @param Size: amount of data to be sent
<> 144:ef7eb2e8f9f7 1294 * @retval HAL status
<> 144:ef7eb2e8f9f7 1295 */
<> 144:ef7eb2e8f9f7 1296 HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
<> 144:ef7eb2e8f9f7 1297 {
<> 144:ef7eb2e8f9f7 1298 HAL_StatusTypeDef errorcode = HAL_OK;
AnnaBridge 167:e84263d55307 1299
AnnaBridge 167:e84263d55307 1300
AnnaBridge 167:e84263d55307 1301 if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
AnnaBridge 167:e84263d55307 1302 {
AnnaBridge 167:e84263d55307 1303 hspi->State = HAL_SPI_STATE_BUSY_RX;
AnnaBridge 167:e84263d55307 1304 /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
AnnaBridge 167:e84263d55307 1305 return HAL_SPI_TransmitReceive_IT(hspi, pData, pData, Size);
AnnaBridge 167:e84263d55307 1306 }
<> 144:ef7eb2e8f9f7 1307
<> 144:ef7eb2e8f9f7 1308 /* Process Locked */
<> 144:ef7eb2e8f9f7 1309 __HAL_LOCK(hspi);
<> 144:ef7eb2e8f9f7 1310
AnnaBridge 167:e84263d55307 1311 if (hspi->State != HAL_SPI_STATE_READY)
<> 144:ef7eb2e8f9f7 1312 {
<> 144:ef7eb2e8f9f7 1313 errorcode = HAL_BUSY;
<> 144:ef7eb2e8f9f7 1314 goto error;
<> 144:ef7eb2e8f9f7 1315 }
AnnaBridge 167:e84263d55307 1316
AnnaBridge 167:e84263d55307 1317 if ((pData == NULL) || (Size == 0U))
<> 144:ef7eb2e8f9f7 1318 {
<> 144:ef7eb2e8f9f7 1319 errorcode = HAL_ERROR;
<> 144:ef7eb2e8f9f7 1320 goto error;
<> 144:ef7eb2e8f9f7 1321 }
<> 144:ef7eb2e8f9f7 1322
AnnaBridge 167:e84263d55307 1323 /* Set the transaction information */
<> 144:ef7eb2e8f9f7 1324 hspi->State = HAL_SPI_STATE_BUSY_RX;
<> 144:ef7eb2e8f9f7 1325 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
AnnaBridge 167:e84263d55307 1326 hspi->pRxBuffPtr = (uint8_t *)pData;
<> 144:ef7eb2e8f9f7 1327 hspi->RxXferSize = Size;
<> 144:ef7eb2e8f9f7 1328 hspi->RxXferCount = Size;
AnnaBridge 167:e84263d55307 1329
AnnaBridge 167:e84263d55307 1330 /* Init field not used in handle to zero */
<> 144:ef7eb2e8f9f7 1331 hspi->pTxBuffPtr = (uint8_t *)NULL;
AnnaBridge 167:e84263d55307 1332 hspi->TxXferSize = 0U;
AnnaBridge 167:e84263d55307 1333 hspi->TxXferCount = 0U;
AnnaBridge 167:e84263d55307 1334 hspi->TxISR = NULL;
AnnaBridge 167:e84263d55307 1335
AnnaBridge 167:e84263d55307 1336 /* Check the data size to adapt Rx threshold and the set the function for IT treatment */
AnnaBridge 167:e84263d55307 1337 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
<> 144:ef7eb2e8f9f7 1338 {
AnnaBridge 167:e84263d55307 1339 /* Set fiforxthresold according the reception data length: 16 bit */
<> 144:ef7eb2e8f9f7 1340 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
<> 144:ef7eb2e8f9f7 1341 hspi->RxISR = SPI_RxISR_16BIT;
<> 144:ef7eb2e8f9f7 1342 }
<> 144:ef7eb2e8f9f7 1343 else
<> 144:ef7eb2e8f9f7 1344 {
AnnaBridge 167:e84263d55307 1345 /* Set fiforxthresold according the reception data length: 8 bit */
<> 144:ef7eb2e8f9f7 1346 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
<> 144:ef7eb2e8f9f7 1347 hspi->RxISR = SPI_RxISR_8BIT;
<> 144:ef7eb2e8f9f7 1348 }
<> 144:ef7eb2e8f9f7 1349
<> 144:ef7eb2e8f9f7 1350 /* Configure communication direction : 1Line */
AnnaBridge 167:e84263d55307 1351 if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
<> 144:ef7eb2e8f9f7 1352 {
<> 144:ef7eb2e8f9f7 1353 SPI_1LINE_RX(hspi);
<> 144:ef7eb2e8f9f7 1354 }
<> 144:ef7eb2e8f9f7 1355
AnnaBridge 167:e84263d55307 1356 #if (USE_SPI_CRC != 0U)
<> 144:ef7eb2e8f9f7 1357 /* Reset CRC Calculation */
AnnaBridge 167:e84263d55307 1358 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<> 144:ef7eb2e8f9f7 1359 {
AnnaBridge 167:e84263d55307 1360 hspi->CRCSize = 1U;
AnnaBridge 167:e84263d55307 1361 if ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))
AnnaBridge 167:e84263d55307 1362 {
AnnaBridge 167:e84263d55307 1363 hspi->CRCSize = 2U;
AnnaBridge 167:e84263d55307 1364 }
<> 144:ef7eb2e8f9f7 1365 SPI_RESET_CRC(hspi);
<> 144:ef7eb2e8f9f7 1366 }
AnnaBridge 167:e84263d55307 1367 else
AnnaBridge 167:e84263d55307 1368 {
AnnaBridge 167:e84263d55307 1369 hspi->CRCSize = 0U;
AnnaBridge 167:e84263d55307 1370 }
AnnaBridge 167:e84263d55307 1371 #endif /* USE_SPI_CRC */
<> 144:ef7eb2e8f9f7 1372
<> 144:ef7eb2e8f9f7 1373 /* Enable TXE and ERR interrupt */
<> 144:ef7eb2e8f9f7 1374 __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
<> 144:ef7eb2e8f9f7 1375
AnnaBridge 167:e84263d55307 1376 /* Note : The SPI must be enabled after unlocking current process
AnnaBridge 167:e84263d55307 1377 to avoid the risk of SPI interrupt handle execution before current
AnnaBridge 167:e84263d55307 1378 process unlock */
AnnaBridge 167:e84263d55307 1379
<> 144:ef7eb2e8f9f7 1380 /* Check if the SPI is already enabled */
AnnaBridge 167:e84263d55307 1381 if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
<> 144:ef7eb2e8f9f7 1382 {
<> 144:ef7eb2e8f9f7 1383 /* Enable SPI peripheral */
<> 144:ef7eb2e8f9f7 1384 __HAL_SPI_ENABLE(hspi);
<> 144:ef7eb2e8f9f7 1385 }
<> 144:ef7eb2e8f9f7 1386
<> 144:ef7eb2e8f9f7 1387 error :
<> 144:ef7eb2e8f9f7 1388 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1389 __HAL_UNLOCK(hspi);
<> 144:ef7eb2e8f9f7 1390 return errorcode;
<> 144:ef7eb2e8f9f7 1391 }
<> 144:ef7eb2e8f9f7 1392
<> 144:ef7eb2e8f9f7 1393 /**
<> 144:ef7eb2e8f9f7 1394 * @brief Transmit and Receive an amount of data in non-blocking mode with Interrupt.
<> 144:ef7eb2e8f9f7 1395 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1396 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 1397 * @param pTxData: pointer to transmission data buffer
<> 144:ef7eb2e8f9f7 1398 * @param pRxData: pointer to reception data buffer
<> 144:ef7eb2e8f9f7 1399 * @param Size: amount of data to be sent and received
<> 144:ef7eb2e8f9f7 1400 * @retval HAL status
<> 144:ef7eb2e8f9f7 1401 */
<> 144:ef7eb2e8f9f7 1402 HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
<> 144:ef7eb2e8f9f7 1403 {
AnnaBridge 167:e84263d55307 1404 uint32_t tmp = 0U, tmp1 = 0U;
<> 144:ef7eb2e8f9f7 1405 HAL_StatusTypeDef errorcode = HAL_OK;
AnnaBridge 167:e84263d55307 1406
AnnaBridge 167:e84263d55307 1407
AnnaBridge 167:e84263d55307 1408 /* Check Direction parameter */
<> 144:ef7eb2e8f9f7 1409 assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
<> 144:ef7eb2e8f9f7 1410
<> 144:ef7eb2e8f9f7 1411 /* Process locked */
<> 144:ef7eb2e8f9f7 1412 __HAL_LOCK(hspi);
<> 144:ef7eb2e8f9f7 1413
AnnaBridge 167:e84263d55307 1414 tmp = hspi->State;
AnnaBridge 167:e84263d55307 1415 tmp1 = hspi->Init.Mode;
AnnaBridge 167:e84263d55307 1416
AnnaBridge 167:e84263d55307 1417 if (!((tmp == HAL_SPI_STATE_READY) || \
AnnaBridge 167:e84263d55307 1418 ((tmp1 == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp == HAL_SPI_STATE_BUSY_RX))))
<> 144:ef7eb2e8f9f7 1419 {
<> 144:ef7eb2e8f9f7 1420 errorcode = HAL_BUSY;
<> 144:ef7eb2e8f9f7 1421 goto error;
<> 144:ef7eb2e8f9f7 1422 }
<> 144:ef7eb2e8f9f7 1423
AnnaBridge 167:e84263d55307 1424 if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
<> 144:ef7eb2e8f9f7 1425 {
<> 144:ef7eb2e8f9f7 1426 errorcode = HAL_ERROR;
<> 144:ef7eb2e8f9f7 1427 goto error;
<> 144:ef7eb2e8f9f7 1428 }
<> 144:ef7eb2e8f9f7 1429
AnnaBridge 167:e84263d55307 1430 /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
AnnaBridge 167:e84263d55307 1431 if (hspi->State != HAL_SPI_STATE_BUSY_RX)
<> 144:ef7eb2e8f9f7 1432 {
<> 144:ef7eb2e8f9f7 1433 hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
<> 144:ef7eb2e8f9f7 1434 }
<> 144:ef7eb2e8f9f7 1435
AnnaBridge 167:e84263d55307 1436 /* Set the transaction information */
<> 144:ef7eb2e8f9f7 1437 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
AnnaBridge 167:e84263d55307 1438 hspi->pTxBuffPtr = (uint8_t *)pTxData;
<> 144:ef7eb2e8f9f7 1439 hspi->TxXferSize = Size;
<> 144:ef7eb2e8f9f7 1440 hspi->TxXferCount = Size;
AnnaBridge 167:e84263d55307 1441 hspi->pRxBuffPtr = (uint8_t *)pRxData;
<> 144:ef7eb2e8f9f7 1442 hspi->RxXferSize = Size;
<> 144:ef7eb2e8f9f7 1443 hspi->RxXferCount = Size;
<> 144:ef7eb2e8f9f7 1444
<> 144:ef7eb2e8f9f7 1445 /* Set the function for IT treatment */
AnnaBridge 167:e84263d55307 1446 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
<> 144:ef7eb2e8f9f7 1447 {
AnnaBridge 167:e84263d55307 1448 hspi->RxISR = SPI_2linesRxISR_16BIT;
AnnaBridge 167:e84263d55307 1449 hspi->TxISR = SPI_2linesTxISR_16BIT;
<> 144:ef7eb2e8f9f7 1450 }
<> 144:ef7eb2e8f9f7 1451 else
<> 144:ef7eb2e8f9f7 1452 {
AnnaBridge 167:e84263d55307 1453 hspi->RxISR = SPI_2linesRxISR_8BIT;
AnnaBridge 167:e84263d55307 1454 hspi->TxISR = SPI_2linesTxISR_8BIT;
<> 144:ef7eb2e8f9f7 1455 }
<> 144:ef7eb2e8f9f7 1456
AnnaBridge 167:e84263d55307 1457 #if (USE_SPI_CRC != 0U)
<> 144:ef7eb2e8f9f7 1458 /* Reset CRC Calculation */
AnnaBridge 167:e84263d55307 1459 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<> 144:ef7eb2e8f9f7 1460 {
AnnaBridge 167:e84263d55307 1461 hspi->CRCSize = 1U;
AnnaBridge 167:e84263d55307 1462 if ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))
AnnaBridge 167:e84263d55307 1463 {
AnnaBridge 167:e84263d55307 1464 hspi->CRCSize = 2U;
AnnaBridge 167:e84263d55307 1465 }
<> 144:ef7eb2e8f9f7 1466 SPI_RESET_CRC(hspi);
<> 144:ef7eb2e8f9f7 1467 }
AnnaBridge 167:e84263d55307 1468 else
<> 144:ef7eb2e8f9f7 1469 {
AnnaBridge 167:e84263d55307 1470 hspi->CRCSize = 0U;
AnnaBridge 167:e84263d55307 1471 }
AnnaBridge 167:e84263d55307 1472 #endif /* USE_SPI_CRC */
AnnaBridge 167:e84263d55307 1473
AnnaBridge 167:e84263d55307 1474 /* Check if packing mode is enabled and if there is more than 2 data to receive */
AnnaBridge 167:e84263d55307 1475 if ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (hspi->RxXferCount >= 2U))
AnnaBridge 167:e84263d55307 1476 {
AnnaBridge 167:e84263d55307 1477 /* Set fiforxthresold according the reception data length: 16 bit */
<> 144:ef7eb2e8f9f7 1478 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
<> 144:ef7eb2e8f9f7 1479 }
<> 144:ef7eb2e8f9f7 1480 else
<> 144:ef7eb2e8f9f7 1481 {
AnnaBridge 167:e84263d55307 1482 /* Set fiforxthresold according the reception data length: 8 bit */
<> 144:ef7eb2e8f9f7 1483 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
<> 144:ef7eb2e8f9f7 1484 }
<> 144:ef7eb2e8f9f7 1485
<> 144:ef7eb2e8f9f7 1486 /* Enable TXE, RXNE and ERR interrupt */
<> 144:ef7eb2e8f9f7 1487 __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
<> 144:ef7eb2e8f9f7 1488
<> 144:ef7eb2e8f9f7 1489 /* Check if the SPI is already enabled */
AnnaBridge 167:e84263d55307 1490 if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
<> 144:ef7eb2e8f9f7 1491 {
<> 144:ef7eb2e8f9f7 1492 /* Enable SPI peripheral */
<> 144:ef7eb2e8f9f7 1493 __HAL_SPI_ENABLE(hspi);
<> 144:ef7eb2e8f9f7 1494 }
<> 144:ef7eb2e8f9f7 1495
<> 144:ef7eb2e8f9f7 1496 error :
<> 144:ef7eb2e8f9f7 1497 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1498 __HAL_UNLOCK(hspi);
<> 144:ef7eb2e8f9f7 1499 return errorcode;
<> 144:ef7eb2e8f9f7 1500 }
<> 144:ef7eb2e8f9f7 1501
<> 144:ef7eb2e8f9f7 1502 /**
<> 144:ef7eb2e8f9f7 1503 * @brief Transmit an amount of data in non-blocking mode with DMA.
<> 144:ef7eb2e8f9f7 1504 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1505 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 1506 * @param pData: pointer to data buffer
<> 144:ef7eb2e8f9f7 1507 * @param Size: amount of data to be sent
<> 144:ef7eb2e8f9f7 1508 * @retval HAL status
<> 144:ef7eb2e8f9f7 1509 */
<> 144:ef7eb2e8f9f7 1510 HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
<> 144:ef7eb2e8f9f7 1511 {
<> 144:ef7eb2e8f9f7 1512 HAL_StatusTypeDef errorcode = HAL_OK;
AnnaBridge 167:e84263d55307 1513
AnnaBridge 167:e84263d55307 1514 /* check tx dma handle */
AnnaBridge 167:e84263d55307 1515 assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx));
AnnaBridge 167:e84263d55307 1516
AnnaBridge 167:e84263d55307 1517 /* Check Direction parameter */
<> 144:ef7eb2e8f9f7 1518 assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
<> 144:ef7eb2e8f9f7 1519
<> 144:ef7eb2e8f9f7 1520 /* Process Locked */
<> 144:ef7eb2e8f9f7 1521 __HAL_LOCK(hspi);
<> 144:ef7eb2e8f9f7 1522
AnnaBridge 167:e84263d55307 1523 if (hspi->State != HAL_SPI_STATE_READY)
<> 144:ef7eb2e8f9f7 1524 {
<> 144:ef7eb2e8f9f7 1525 errorcode = HAL_BUSY;
<> 144:ef7eb2e8f9f7 1526 goto error;
<> 144:ef7eb2e8f9f7 1527 }
<> 144:ef7eb2e8f9f7 1528
AnnaBridge 167:e84263d55307 1529 if ((pData == NULL) || (Size == 0U))
<> 144:ef7eb2e8f9f7 1530 {
<> 144:ef7eb2e8f9f7 1531 errorcode = HAL_ERROR;
<> 144:ef7eb2e8f9f7 1532 goto error;
<> 144:ef7eb2e8f9f7 1533 }
<> 144:ef7eb2e8f9f7 1534
AnnaBridge 167:e84263d55307 1535 /* Set the transaction information */
<> 144:ef7eb2e8f9f7 1536 hspi->State = HAL_SPI_STATE_BUSY_TX;
<> 144:ef7eb2e8f9f7 1537 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
AnnaBridge 167:e84263d55307 1538 hspi->pTxBuffPtr = (uint8_t *)pData;
<> 144:ef7eb2e8f9f7 1539 hspi->TxXferSize = Size;
<> 144:ef7eb2e8f9f7 1540 hspi->TxXferCount = Size;
AnnaBridge 167:e84263d55307 1541
AnnaBridge 167:e84263d55307 1542 /* Init field not used in handle to zero */
<> 144:ef7eb2e8f9f7 1543 hspi->pRxBuffPtr = (uint8_t *)NULL;
AnnaBridge 167:e84263d55307 1544 hspi->TxISR = NULL;
AnnaBridge 167:e84263d55307 1545 hspi->RxISR = NULL;
AnnaBridge 167:e84263d55307 1546 hspi->RxXferSize = 0U;
AnnaBridge 167:e84263d55307 1547 hspi->RxXferCount = 0U;
<> 144:ef7eb2e8f9f7 1548
<> 144:ef7eb2e8f9f7 1549 /* Configure communication direction : 1Line */
AnnaBridge 167:e84263d55307 1550 if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
<> 144:ef7eb2e8f9f7 1551 {
<> 144:ef7eb2e8f9f7 1552 SPI_1LINE_TX(hspi);
<> 144:ef7eb2e8f9f7 1553 }
<> 144:ef7eb2e8f9f7 1554
AnnaBridge 167:e84263d55307 1555 #if (USE_SPI_CRC != 0U)
<> 144:ef7eb2e8f9f7 1556 /* Reset CRC Calculation */
AnnaBridge 167:e84263d55307 1557 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<> 144:ef7eb2e8f9f7 1558 {
<> 144:ef7eb2e8f9f7 1559 SPI_RESET_CRC(hspi);
<> 144:ef7eb2e8f9f7 1560 }
AnnaBridge 167:e84263d55307 1561 #endif /* USE_SPI_CRC */
<> 144:ef7eb2e8f9f7 1562
<> 144:ef7eb2e8f9f7 1563 /* Set the SPI TxDMA Half transfer complete callback */
<> 144:ef7eb2e8f9f7 1564 hspi->hdmatx->XferHalfCpltCallback = SPI_DMAHalfTransmitCplt;
<> 144:ef7eb2e8f9f7 1565
<> 144:ef7eb2e8f9f7 1566 /* Set the SPI TxDMA transfer complete callback */
<> 144:ef7eb2e8f9f7 1567 hspi->hdmatx->XferCpltCallback = SPI_DMATransmitCplt;
<> 144:ef7eb2e8f9f7 1568
<> 144:ef7eb2e8f9f7 1569 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 1570 hspi->hdmatx->XferErrorCallback = SPI_DMAError;
<> 144:ef7eb2e8f9f7 1571
AnnaBridge 167:e84263d55307 1572 /* Set the DMA AbortCpltCallback */
AnnaBridge 167:e84263d55307 1573 hspi->hdmatx->XferAbortCallback = NULL;
AnnaBridge 167:e84263d55307 1574
<> 144:ef7eb2e8f9f7 1575 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
AnnaBridge 167:e84263d55307 1576 /* Packing mode is enabled only if the DMA setting is HALWORD */
AnnaBridge 167:e84263d55307 1577 if ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD))
<> 144:ef7eb2e8f9f7 1578 {
<> 144:ef7eb2e8f9f7 1579 /* Check the even/odd of the data size + crc if enabled */
AnnaBridge 167:e84263d55307 1580 if ((hspi->TxXferCount & 0x1U) == 0U)
<> 144:ef7eb2e8f9f7 1581 {
<> 144:ef7eb2e8f9f7 1582 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
AnnaBridge 167:e84263d55307 1583 hspi->TxXferCount = (hspi->TxXferCount >> 1U);
<> 144:ef7eb2e8f9f7 1584 }
<> 144:ef7eb2e8f9f7 1585 else
<> 144:ef7eb2e8f9f7 1586 {
<> 144:ef7eb2e8f9f7 1587 SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
AnnaBridge 167:e84263d55307 1588 hspi->TxXferCount = (hspi->TxXferCount >> 1U) + 1U;
<> 144:ef7eb2e8f9f7 1589 }
<> 144:ef7eb2e8f9f7 1590 }
<> 144:ef7eb2e8f9f7 1591
AnnaBridge 167:e84263d55307 1592 /* Enable the Tx DMA Stream/Channel */
<> 144:ef7eb2e8f9f7 1593 HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount);
<> 144:ef7eb2e8f9f7 1594
<> 144:ef7eb2e8f9f7 1595 /* Check if the SPI is already enabled */
AnnaBridge 167:e84263d55307 1596 if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
<> 144:ef7eb2e8f9f7 1597 {
<> 144:ef7eb2e8f9f7 1598 /* Enable SPI peripheral */
<> 144:ef7eb2e8f9f7 1599 __HAL_SPI_ENABLE(hspi);
<> 144:ef7eb2e8f9f7 1600 }
<> 144:ef7eb2e8f9f7 1601
AnnaBridge 167:e84263d55307 1602 /* Enable the SPI Error Interrupt Bit */
AnnaBridge 167:e84263d55307 1603 __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR));
AnnaBridge 167:e84263d55307 1604
<> 144:ef7eb2e8f9f7 1605 /* Enable Tx DMA Request */
<> 144:ef7eb2e8f9f7 1606 SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
<> 144:ef7eb2e8f9f7 1607
<> 144:ef7eb2e8f9f7 1608 error :
<> 144:ef7eb2e8f9f7 1609 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1610 __HAL_UNLOCK(hspi);
<> 144:ef7eb2e8f9f7 1611 return errorcode;
<> 144:ef7eb2e8f9f7 1612 }
<> 144:ef7eb2e8f9f7 1613
<> 144:ef7eb2e8f9f7 1614 /**
<> 144:ef7eb2e8f9f7 1615 * @brief Receive an amount of data in non-blocking mode with DMA.
AnnaBridge 167:e84263d55307 1616 * @note In case of MASTER mode and SPI_DIRECTION_2LINES direction, hdmatx shall be defined.
<> 144:ef7eb2e8f9f7 1617 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1618 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 1619 * @param pData: pointer to data buffer
AnnaBridge 167:e84263d55307 1620 * @note When the CRC feature is enabled the pData Length must be Size + 1.
<> 144:ef7eb2e8f9f7 1621 * @param Size: amount of data to be sent
<> 144:ef7eb2e8f9f7 1622 * @retval HAL status
<> 144:ef7eb2e8f9f7 1623 */
<> 144:ef7eb2e8f9f7 1624 HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
<> 144:ef7eb2e8f9f7 1625 {
<> 144:ef7eb2e8f9f7 1626 HAL_StatusTypeDef errorcode = HAL_OK;
AnnaBridge 167:e84263d55307 1627
AnnaBridge 167:e84263d55307 1628 /* check rx dma handle */
AnnaBridge 167:e84263d55307 1629 assert_param(IS_SPI_DMA_HANDLE(hspi->hdmarx));
AnnaBridge 167:e84263d55307 1630
AnnaBridge 167:e84263d55307 1631 if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
AnnaBridge 167:e84263d55307 1632 {
AnnaBridge 167:e84263d55307 1633 hspi->State = HAL_SPI_STATE_BUSY_RX;
AnnaBridge 167:e84263d55307 1634
AnnaBridge 167:e84263d55307 1635 /* check tx dma handle */
AnnaBridge 167:e84263d55307 1636 assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx));
AnnaBridge 167:e84263d55307 1637
AnnaBridge 167:e84263d55307 1638 /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
AnnaBridge 167:e84263d55307 1639 return HAL_SPI_TransmitReceive_DMA(hspi, pData, pData, Size);
AnnaBridge 167:e84263d55307 1640 }
<> 144:ef7eb2e8f9f7 1641
<> 144:ef7eb2e8f9f7 1642 /* Process Locked */
<> 144:ef7eb2e8f9f7 1643 __HAL_LOCK(hspi);
<> 144:ef7eb2e8f9f7 1644
AnnaBridge 167:e84263d55307 1645 if (hspi->State != HAL_SPI_STATE_READY)
<> 144:ef7eb2e8f9f7 1646 {
<> 144:ef7eb2e8f9f7 1647 errorcode = HAL_BUSY;
<> 144:ef7eb2e8f9f7 1648 goto error;
<> 144:ef7eb2e8f9f7 1649 }
<> 144:ef7eb2e8f9f7 1650
AnnaBridge 167:e84263d55307 1651 if ((pData == NULL) || (Size == 0U))
<> 144:ef7eb2e8f9f7 1652 {
<> 144:ef7eb2e8f9f7 1653 errorcode = HAL_ERROR;
<> 144:ef7eb2e8f9f7 1654 goto error;
<> 144:ef7eb2e8f9f7 1655 }
<> 144:ef7eb2e8f9f7 1656
AnnaBridge 167:e84263d55307 1657 /* Set the transaction information */
<> 144:ef7eb2e8f9f7 1658 hspi->State = HAL_SPI_STATE_BUSY_RX;
<> 144:ef7eb2e8f9f7 1659 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
AnnaBridge 167:e84263d55307 1660 hspi->pRxBuffPtr = (uint8_t *)pData;
<> 144:ef7eb2e8f9f7 1661 hspi->RxXferSize = Size;
<> 144:ef7eb2e8f9f7 1662 hspi->RxXferCount = Size;
AnnaBridge 167:e84263d55307 1663
AnnaBridge 167:e84263d55307 1664 /*Init field not used in handle to zero */
AnnaBridge 167:e84263d55307 1665 hspi->RxISR = NULL;
AnnaBridge 167:e84263d55307 1666 hspi->TxISR = NULL;
AnnaBridge 167:e84263d55307 1667 hspi->TxXferSize = 0U;
AnnaBridge 167:e84263d55307 1668 hspi->TxXferCount = 0U;
<> 144:ef7eb2e8f9f7 1669
<> 144:ef7eb2e8f9f7 1670 /* Configure communication direction : 1Line */
AnnaBridge 167:e84263d55307 1671 if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
<> 144:ef7eb2e8f9f7 1672 {
<> 144:ef7eb2e8f9f7 1673 SPI_1LINE_RX(hspi);
<> 144:ef7eb2e8f9f7 1674 }
<> 144:ef7eb2e8f9f7 1675
AnnaBridge 167:e84263d55307 1676 #if (USE_SPI_CRC != 0U)
<> 144:ef7eb2e8f9f7 1677 /* Reset CRC Calculation */
AnnaBridge 167:e84263d55307 1678 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<> 144:ef7eb2e8f9f7 1679 {
<> 144:ef7eb2e8f9f7 1680 SPI_RESET_CRC(hspi);
<> 144:ef7eb2e8f9f7 1681 }
AnnaBridge 167:e84263d55307 1682 #endif /* USE_SPI_CRC */
AnnaBridge 167:e84263d55307 1683
<> 144:ef7eb2e8f9f7 1684
<> 144:ef7eb2e8f9f7 1685 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
AnnaBridge 167:e84263d55307 1686 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
<> 144:ef7eb2e8f9f7 1687 {
AnnaBridge 167:e84263d55307 1688 /* Set fiforxthresold according the reception data length: 16bit */
<> 144:ef7eb2e8f9f7 1689 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
<> 144:ef7eb2e8f9f7 1690 }
<> 144:ef7eb2e8f9f7 1691 else
<> 144:ef7eb2e8f9f7 1692 {
AnnaBridge 167:e84263d55307 1693 /* Set fiforxthresold according the reception data length: 8bit */
<> 144:ef7eb2e8f9f7 1694 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
AnnaBridge 167:e84263d55307 1695
AnnaBridge 167:e84263d55307 1696 if (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
AnnaBridge 167:e84263d55307 1697 {
AnnaBridge 167:e84263d55307 1698 /* set fiforxthresold according the reception data length: 16bit */
AnnaBridge 167:e84263d55307 1699 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
AnnaBridge 167:e84263d55307 1700
AnnaBridge 167:e84263d55307 1701 if ((hspi->RxXferCount & 0x1U) == 0x0U)
AnnaBridge 167:e84263d55307 1702 {
AnnaBridge 167:e84263d55307 1703 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
AnnaBridge 167:e84263d55307 1704 hspi->RxXferCount = hspi->RxXferCount >> 1U;
AnnaBridge 167:e84263d55307 1705 }
AnnaBridge 167:e84263d55307 1706 else
AnnaBridge 167:e84263d55307 1707 {
AnnaBridge 167:e84263d55307 1708 SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
AnnaBridge 167:e84263d55307 1709 hspi->RxXferCount = (hspi->RxXferCount >> 1U) + 1U;
AnnaBridge 167:e84263d55307 1710 }
AnnaBridge 167:e84263d55307 1711 }
<> 144:ef7eb2e8f9f7 1712 }
<> 144:ef7eb2e8f9f7 1713
<> 144:ef7eb2e8f9f7 1714 /* Set the SPI RxDMA Half transfer complete callback */
<> 144:ef7eb2e8f9f7 1715 hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
<> 144:ef7eb2e8f9f7 1716
<> 144:ef7eb2e8f9f7 1717 /* Set the SPI Rx DMA transfer complete callback */
<> 144:ef7eb2e8f9f7 1718 hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
<> 144:ef7eb2e8f9f7 1719
<> 144:ef7eb2e8f9f7 1720 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 1721 hspi->hdmarx->XferErrorCallback = SPI_DMAError;
<> 144:ef7eb2e8f9f7 1722
AnnaBridge 167:e84263d55307 1723 /* Set the DMA AbortCpltCallback */
AnnaBridge 167:e84263d55307 1724 hspi->hdmarx->XferAbortCallback = NULL;
AnnaBridge 167:e84263d55307 1725
AnnaBridge 167:e84263d55307 1726 /* Enable the Rx DMA Stream/Channel */
<> 144:ef7eb2e8f9f7 1727 HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount);
<> 144:ef7eb2e8f9f7 1728
<> 144:ef7eb2e8f9f7 1729 /* Check if the SPI is already enabled */
AnnaBridge 167:e84263d55307 1730 if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
<> 144:ef7eb2e8f9f7 1731 {
<> 144:ef7eb2e8f9f7 1732 /* Enable SPI peripheral */
<> 144:ef7eb2e8f9f7 1733 __HAL_SPI_ENABLE(hspi);
<> 144:ef7eb2e8f9f7 1734 }
<> 144:ef7eb2e8f9f7 1735
AnnaBridge 167:e84263d55307 1736 /* Enable the SPI Error Interrupt Bit */
AnnaBridge 167:e84263d55307 1737 __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR));
AnnaBridge 167:e84263d55307 1738
AnnaBridge 167:e84263d55307 1739 /* Enable Rx DMA Request */
AnnaBridge 167:e84263d55307 1740 SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
AnnaBridge 167:e84263d55307 1741
<> 144:ef7eb2e8f9f7 1742 error:
<> 144:ef7eb2e8f9f7 1743 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1744 __HAL_UNLOCK(hspi);
<> 144:ef7eb2e8f9f7 1745 return errorcode;
<> 144:ef7eb2e8f9f7 1746 }
<> 144:ef7eb2e8f9f7 1747
<> 144:ef7eb2e8f9f7 1748 /**
<> 144:ef7eb2e8f9f7 1749 * @brief Transmit and Receive an amount of data in non-blocking mode with DMA.
<> 144:ef7eb2e8f9f7 1750 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1751 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 1752 * @param pTxData: pointer to transmission data buffer
<> 144:ef7eb2e8f9f7 1753 * @param pRxData: pointer to reception data buffer
AnnaBridge 167:e84263d55307 1754 * @note When the CRC feature is enabled the pRxData Length must be Size + 1
<> 144:ef7eb2e8f9f7 1755 * @param Size: amount of data to be sent
<> 144:ef7eb2e8f9f7 1756 * @retval HAL status
<> 144:ef7eb2e8f9f7 1757 */
AnnaBridge 167:e84263d55307 1758 HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData,
AnnaBridge 167:e84263d55307 1759 uint16_t Size)
<> 144:ef7eb2e8f9f7 1760 {
AnnaBridge 167:e84263d55307 1761 uint32_t tmp = 0U, tmp1 = 0U;
<> 144:ef7eb2e8f9f7 1762 HAL_StatusTypeDef errorcode = HAL_OK;
AnnaBridge 167:e84263d55307 1763
AnnaBridge 167:e84263d55307 1764 /* check rx & tx dma handles */
AnnaBridge 167:e84263d55307 1765 assert_param(IS_SPI_DMA_HANDLE(hspi->hdmarx));
AnnaBridge 167:e84263d55307 1766 assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx));
AnnaBridge 167:e84263d55307 1767
AnnaBridge 167:e84263d55307 1768 /* Check Direction parameter */
<> 144:ef7eb2e8f9f7 1769 assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
<> 144:ef7eb2e8f9f7 1770
<> 144:ef7eb2e8f9f7 1771 /* Process locked */
<> 144:ef7eb2e8f9f7 1772 __HAL_LOCK(hspi);
<> 144:ef7eb2e8f9f7 1773
AnnaBridge 167:e84263d55307 1774 tmp = hspi->State;
AnnaBridge 167:e84263d55307 1775 tmp1 = hspi->Init.Mode;
AnnaBridge 167:e84263d55307 1776 if (!((tmp == HAL_SPI_STATE_READY) ||
AnnaBridge 167:e84263d55307 1777 ((tmp1 == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp == HAL_SPI_STATE_BUSY_RX))))
<> 144:ef7eb2e8f9f7 1778 {
<> 144:ef7eb2e8f9f7 1779 errorcode = HAL_BUSY;
<> 144:ef7eb2e8f9f7 1780 goto error;
<> 144:ef7eb2e8f9f7 1781 }
<> 144:ef7eb2e8f9f7 1782
AnnaBridge 167:e84263d55307 1783 if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
<> 144:ef7eb2e8f9f7 1784 {
<> 144:ef7eb2e8f9f7 1785 errorcode = HAL_ERROR;
<> 144:ef7eb2e8f9f7 1786 goto error;
<> 144:ef7eb2e8f9f7 1787 }
<> 144:ef7eb2e8f9f7 1788
AnnaBridge 167:e84263d55307 1789 /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
AnnaBridge 167:e84263d55307 1790 if (hspi->State != HAL_SPI_STATE_BUSY_RX)
<> 144:ef7eb2e8f9f7 1791 {
<> 144:ef7eb2e8f9f7 1792 hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
<> 144:ef7eb2e8f9f7 1793 }
<> 144:ef7eb2e8f9f7 1794
AnnaBridge 167:e84263d55307 1795 /* Set the transaction information */
<> 144:ef7eb2e8f9f7 1796 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
<> 144:ef7eb2e8f9f7 1797 hspi->pTxBuffPtr = (uint8_t *)pTxData;
<> 144:ef7eb2e8f9f7 1798 hspi->TxXferSize = Size;
<> 144:ef7eb2e8f9f7 1799 hspi->TxXferCount = Size;
<> 144:ef7eb2e8f9f7 1800 hspi->pRxBuffPtr = (uint8_t *)pRxData;
<> 144:ef7eb2e8f9f7 1801 hspi->RxXferSize = Size;
<> 144:ef7eb2e8f9f7 1802 hspi->RxXferCount = Size;
<> 144:ef7eb2e8f9f7 1803
AnnaBridge 167:e84263d55307 1804 /* Init field not used in handle to zero */
AnnaBridge 167:e84263d55307 1805 hspi->RxISR = NULL;
AnnaBridge 167:e84263d55307 1806 hspi->TxISR = NULL;
AnnaBridge 167:e84263d55307 1807
AnnaBridge 167:e84263d55307 1808 #if (USE_SPI_CRC != 0U)
AnnaBridge 167:e84263d55307 1809 /* Reset CRC Calculation */
AnnaBridge 167:e84263d55307 1810 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<> 144:ef7eb2e8f9f7 1811 {
<> 144:ef7eb2e8f9f7 1812 SPI_RESET_CRC(hspi);
<> 144:ef7eb2e8f9f7 1813 }
AnnaBridge 167:e84263d55307 1814 #endif /* USE_SPI_CRC */
AnnaBridge 167:e84263d55307 1815
AnnaBridge 167:e84263d55307 1816
<> 144:ef7eb2e8f9f7 1817
<> 144:ef7eb2e8f9f7 1818 /* Reset the threshold bit */
<> 144:ef7eb2e8f9f7 1819 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX | SPI_CR2_LDMARX);
<> 144:ef7eb2e8f9f7 1820
AnnaBridge 167:e84263d55307 1821 /* The packing mode management is enabled by the DMA settings according the spi data size */
AnnaBridge 167:e84263d55307 1822 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
<> 144:ef7eb2e8f9f7 1823 {
AnnaBridge 167:e84263d55307 1824 /* Set fiforxthreshold according the reception data length: 16bit */
<> 144:ef7eb2e8f9f7 1825 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
<> 144:ef7eb2e8f9f7 1826 }
<> 144:ef7eb2e8f9f7 1827 else
<> 144:ef7eb2e8f9f7 1828 {
AnnaBridge 167:e84263d55307 1829 /* Set fiforxthresold according the reception data length: 8bit */
<> 144:ef7eb2e8f9f7 1830 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
<> 144:ef7eb2e8f9f7 1831
AnnaBridge 167:e84263d55307 1832 if (hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
<> 144:ef7eb2e8f9f7 1833 {
AnnaBridge 167:e84263d55307 1834 if ((hspi->TxXferSize & 0x1U) == 0x0U)
<> 144:ef7eb2e8f9f7 1835 {
<> 144:ef7eb2e8f9f7 1836 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
AnnaBridge 167:e84263d55307 1837 hspi->TxXferCount = hspi->TxXferCount >> 1U;
<> 144:ef7eb2e8f9f7 1838 }
<> 144:ef7eb2e8f9f7 1839 else
<> 144:ef7eb2e8f9f7 1840 {
<> 144:ef7eb2e8f9f7 1841 SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
AnnaBridge 167:e84263d55307 1842 hspi->TxXferCount = (hspi->TxXferCount >> 1U) + 1U;
<> 144:ef7eb2e8f9f7 1843 }
<> 144:ef7eb2e8f9f7 1844 }
<> 144:ef7eb2e8f9f7 1845
AnnaBridge 167:e84263d55307 1846 if (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
<> 144:ef7eb2e8f9f7 1847 {
AnnaBridge 167:e84263d55307 1848 /* Set fiforxthresold according the reception data length: 16bit */
<> 144:ef7eb2e8f9f7 1849 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
<> 144:ef7eb2e8f9f7 1850
AnnaBridge 167:e84263d55307 1851 if ((hspi->RxXferCount & 0x1U) == 0x0U)
<> 144:ef7eb2e8f9f7 1852 {
<> 144:ef7eb2e8f9f7 1853 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
AnnaBridge 167:e84263d55307 1854 hspi->RxXferCount = hspi->RxXferCount >> 1U;
<> 144:ef7eb2e8f9f7 1855 }
<> 144:ef7eb2e8f9f7 1856 else
<> 144:ef7eb2e8f9f7 1857 {
<> 144:ef7eb2e8f9f7 1858 SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
AnnaBridge 167:e84263d55307 1859 hspi->RxXferCount = (hspi->RxXferCount >> 1U) + 1U;
<> 144:ef7eb2e8f9f7 1860 }
<> 144:ef7eb2e8f9f7 1861 }
<> 144:ef7eb2e8f9f7 1862 }
<> 144:ef7eb2e8f9f7 1863
AnnaBridge 167:e84263d55307 1864 /* Check if we are in Rx only or in Rx/Tx Mode and configure the DMA transfer complete callback */
AnnaBridge 167:e84263d55307 1865 if (hspi->State == HAL_SPI_STATE_BUSY_RX)
<> 144:ef7eb2e8f9f7 1866 {
<> 144:ef7eb2e8f9f7 1867 /* Set the SPI Rx DMA Half transfer complete callback */
<> 144:ef7eb2e8f9f7 1868 hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
AnnaBridge 167:e84263d55307 1869 hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
<> 144:ef7eb2e8f9f7 1870 }
<> 144:ef7eb2e8f9f7 1871 else
<> 144:ef7eb2e8f9f7 1872 {
AnnaBridge 167:e84263d55307 1873 /* Set the SPI Tx/Rx DMA Half transfer complete callback */
<> 144:ef7eb2e8f9f7 1874 hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfTransmitReceiveCplt;
AnnaBridge 167:e84263d55307 1875 hspi->hdmarx->XferCpltCallback = SPI_DMATransmitReceiveCplt;
<> 144:ef7eb2e8f9f7 1876 }
<> 144:ef7eb2e8f9f7 1877
<> 144:ef7eb2e8f9f7 1878 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 1879 hspi->hdmarx->XferErrorCallback = SPI_DMAError;
<> 144:ef7eb2e8f9f7 1880
AnnaBridge 167:e84263d55307 1881 /* Set the DMA AbortCpltCallback */
AnnaBridge 167:e84263d55307 1882 hspi->hdmarx->XferAbortCallback = NULL;
AnnaBridge 167:e84263d55307 1883
AnnaBridge 167:e84263d55307 1884 /* Enable the Rx DMA Stream/Channel */
AnnaBridge 167:e84263d55307 1885 HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount);
AnnaBridge 167:e84263d55307 1886
<> 144:ef7eb2e8f9f7 1887 /* Enable Rx DMA Request */
<> 144:ef7eb2e8f9f7 1888 SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
<> 144:ef7eb2e8f9f7 1889
AnnaBridge 167:e84263d55307 1890 /* Set the SPI Tx DMA transfer complete callback as NULL because the communication closing
AnnaBridge 167:e84263d55307 1891 is performed in DMA reception complete callback */
<> 144:ef7eb2e8f9f7 1892 hspi->hdmatx->XferHalfCpltCallback = NULL;
<> 144:ef7eb2e8f9f7 1893 hspi->hdmatx->XferCpltCallback = NULL;
<> 144:ef7eb2e8f9f7 1894 hspi->hdmatx->XferErrorCallback = NULL;
AnnaBridge 167:e84263d55307 1895 hspi->hdmatx->XferAbortCallback = NULL;
AnnaBridge 167:e84263d55307 1896
AnnaBridge 167:e84263d55307 1897 /* Enable the Tx DMA Stream/Channel */
<> 144:ef7eb2e8f9f7 1898 HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount);
<> 144:ef7eb2e8f9f7 1899
<> 144:ef7eb2e8f9f7 1900 /* Check if the SPI is already enabled */
AnnaBridge 167:e84263d55307 1901 if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
<> 144:ef7eb2e8f9f7 1902 {
<> 144:ef7eb2e8f9f7 1903 /* Enable SPI peripheral */
<> 144:ef7eb2e8f9f7 1904 __HAL_SPI_ENABLE(hspi);
<> 144:ef7eb2e8f9f7 1905 }
AnnaBridge 167:e84263d55307 1906 /* Enable the SPI Error Interrupt Bit */
AnnaBridge 167:e84263d55307 1907 __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR));
<> 144:ef7eb2e8f9f7 1908
<> 144:ef7eb2e8f9f7 1909 /* Enable Tx DMA Request */
<> 144:ef7eb2e8f9f7 1910 SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
<> 144:ef7eb2e8f9f7 1911
<> 144:ef7eb2e8f9f7 1912 error :
<> 144:ef7eb2e8f9f7 1913 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1914 __HAL_UNLOCK(hspi);
<> 144:ef7eb2e8f9f7 1915 return errorcode;
<> 144:ef7eb2e8f9f7 1916 }
<> 144:ef7eb2e8f9f7 1917
<> 144:ef7eb2e8f9f7 1918 /**
AnnaBridge 167:e84263d55307 1919 * @brief Abort ongoing transfer (blocking mode).
AnnaBridge 167:e84263d55307 1920 * @param hspi SPI handle.
AnnaBridge 167:e84263d55307 1921 * @note This procedure could be used for aborting any ongoing transfer (Tx and Rx),
AnnaBridge 167:e84263d55307 1922 * started in Interrupt or DMA mode.
AnnaBridge 167:e84263d55307 1923 * This procedure performs following operations :
AnnaBridge 167:e84263d55307 1924 * - Disable SPI Interrupts (depending of transfer direction)
AnnaBridge 167:e84263d55307 1925 * - Disable the DMA transfer in the peripheral register (if enabled)
AnnaBridge 167:e84263d55307 1926 * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
AnnaBridge 167:e84263d55307 1927 * - Set handle State to READY
AnnaBridge 167:e84263d55307 1928 * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
AnnaBridge 167:e84263d55307 1929 * @retval HAL status
AnnaBridge 167:e84263d55307 1930 */
AnnaBridge 167:e84263d55307 1931 HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi)
AnnaBridge 167:e84263d55307 1932 {
AnnaBridge 167:e84263d55307 1933 HAL_StatusTypeDef errorcode;
AnnaBridge 167:e84263d55307 1934 __IO uint32_t count, resetcount;
AnnaBridge 167:e84263d55307 1935
AnnaBridge 167:e84263d55307 1936 /* Initialized local variable */
AnnaBridge 167:e84263d55307 1937 errorcode = HAL_OK;
AnnaBridge 167:e84263d55307 1938 resetcount = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
AnnaBridge 167:e84263d55307 1939 count = resetcount;
AnnaBridge 167:e84263d55307 1940
AnnaBridge 167:e84263d55307 1941 /* Disable TXEIE, RXNEIE and ERRIE(mode fault event, overrun error, TI frame error) interrupts */
AnnaBridge 167:e84263d55307 1942 if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE))
AnnaBridge 167:e84263d55307 1943 {
AnnaBridge 167:e84263d55307 1944 hspi->TxISR = SPI_AbortTx_ISR;
AnnaBridge 167:e84263d55307 1945 /* Wait HAL_SPI_STATE_ABORT state */
AnnaBridge 167:e84263d55307 1946 do
AnnaBridge 167:e84263d55307 1947 {
AnnaBridge 167:e84263d55307 1948 if (count-- == 0U)
AnnaBridge 167:e84263d55307 1949 {
AnnaBridge 167:e84263d55307 1950 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
AnnaBridge 167:e84263d55307 1951 break;
AnnaBridge 167:e84263d55307 1952 }
AnnaBridge 167:e84263d55307 1953 }
AnnaBridge 167:e84263d55307 1954 while (hspi->State != HAL_SPI_STATE_ABORT);
AnnaBridge 167:e84263d55307 1955 /* Reset Timeout Counter */
AnnaBridge 167:e84263d55307 1956 count = resetcount;
AnnaBridge 167:e84263d55307 1957 }
AnnaBridge 167:e84263d55307 1958
AnnaBridge 167:e84263d55307 1959 if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE))
AnnaBridge 167:e84263d55307 1960 {
AnnaBridge 167:e84263d55307 1961 hspi->RxISR = SPI_AbortRx_ISR;
AnnaBridge 167:e84263d55307 1962 /* Wait HAL_SPI_STATE_ABORT state */
AnnaBridge 167:e84263d55307 1963 do
AnnaBridge 167:e84263d55307 1964 {
AnnaBridge 167:e84263d55307 1965 if (count-- == 0U)
AnnaBridge 167:e84263d55307 1966 {
AnnaBridge 167:e84263d55307 1967 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
AnnaBridge 167:e84263d55307 1968 break;
AnnaBridge 167:e84263d55307 1969 }
AnnaBridge 167:e84263d55307 1970 }
AnnaBridge 167:e84263d55307 1971 while (hspi->State != HAL_SPI_STATE_ABORT);
AnnaBridge 167:e84263d55307 1972 /* Reset Timeout Counter */
AnnaBridge 167:e84263d55307 1973 count = resetcount;
AnnaBridge 167:e84263d55307 1974 }
AnnaBridge 167:e84263d55307 1975
AnnaBridge 167:e84263d55307 1976 /* Clear ERRIE interrupts in case of DMA Mode */
AnnaBridge 167:e84263d55307 1977 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE);
AnnaBridge 167:e84263d55307 1978
AnnaBridge 167:e84263d55307 1979 /* Disable the SPI DMA Tx or SPI DMA Rx request if enabled */
AnnaBridge 167:e84263d55307 1980 if ((HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN)) || (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN)))
AnnaBridge 167:e84263d55307 1981 {
AnnaBridge 167:e84263d55307 1982 /* Abort the SPI DMA Tx Stream/Channel : use blocking DMA Abort API (no callback) */
AnnaBridge 167:e84263d55307 1983 if (hspi->hdmatx != NULL)
AnnaBridge 167:e84263d55307 1984 {
AnnaBridge 167:e84263d55307 1985 /* Set the SPI DMA Abort callback :
AnnaBridge 167:e84263d55307 1986 will lead to call HAL_SPI_AbortCpltCallback() at end of DMA abort procedure */
AnnaBridge 167:e84263d55307 1987 hspi->hdmatx->XferAbortCallback = NULL;
AnnaBridge 167:e84263d55307 1988
AnnaBridge 167:e84263d55307 1989 /* Abort DMA Tx Handle linked to SPI Peripheral */
AnnaBridge 167:e84263d55307 1990 if (HAL_DMA_Abort(hspi->hdmatx) != HAL_OK)
AnnaBridge 167:e84263d55307 1991 {
AnnaBridge 167:e84263d55307 1992 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
AnnaBridge 167:e84263d55307 1993 }
AnnaBridge 167:e84263d55307 1994
AnnaBridge 167:e84263d55307 1995 /* Disable Tx DMA Request */
AnnaBridge 167:e84263d55307 1996 CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXDMAEN));
AnnaBridge 167:e84263d55307 1997
AnnaBridge 167:e84263d55307 1998 if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
AnnaBridge 167:e84263d55307 1999 {
AnnaBridge 167:e84263d55307 2000 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
AnnaBridge 167:e84263d55307 2001 }
AnnaBridge 167:e84263d55307 2002
AnnaBridge 167:e84263d55307 2003 /* Disable SPI Peripheral */
AnnaBridge 167:e84263d55307 2004 __HAL_SPI_DISABLE(hspi);
AnnaBridge 167:e84263d55307 2005
AnnaBridge 167:e84263d55307 2006 /* Empty the FRLVL fifo */
AnnaBridge 167:e84263d55307 2007 if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
AnnaBridge 167:e84263d55307 2008 {
AnnaBridge 167:e84263d55307 2009 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
AnnaBridge 167:e84263d55307 2010 }
AnnaBridge 167:e84263d55307 2011 }
AnnaBridge 167:e84263d55307 2012 /* Abort the SPI DMA Rx Stream/Channel : use blocking DMA Abort API (no callback) */
AnnaBridge 167:e84263d55307 2013 if (hspi->hdmarx != NULL)
AnnaBridge 167:e84263d55307 2014 {
AnnaBridge 167:e84263d55307 2015 /* Set the SPI DMA Abort callback :
AnnaBridge 167:e84263d55307 2016 will lead to call HAL_SPI_AbortCpltCallback() at end of DMA abort procedure */
AnnaBridge 167:e84263d55307 2017 hspi->hdmarx->XferAbortCallback = NULL;
AnnaBridge 167:e84263d55307 2018
AnnaBridge 167:e84263d55307 2019 /* Abort DMA Rx Handle linked to SPI Peripheral */
AnnaBridge 167:e84263d55307 2020 if (HAL_DMA_Abort(hspi->hdmarx) != HAL_OK)
AnnaBridge 167:e84263d55307 2021 {
AnnaBridge 167:e84263d55307 2022 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
AnnaBridge 167:e84263d55307 2023 }
AnnaBridge 167:e84263d55307 2024
AnnaBridge 167:e84263d55307 2025 /* Disable peripheral */
AnnaBridge 167:e84263d55307 2026 __HAL_SPI_DISABLE(hspi);
AnnaBridge 167:e84263d55307 2027
AnnaBridge 167:e84263d55307 2028 /* Control the BSY flag */
AnnaBridge 167:e84263d55307 2029 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
AnnaBridge 167:e84263d55307 2030 {
AnnaBridge 167:e84263d55307 2031 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
AnnaBridge 167:e84263d55307 2032 }
AnnaBridge 167:e84263d55307 2033
AnnaBridge 167:e84263d55307 2034 /* Empty the FRLVL fifo */
AnnaBridge 167:e84263d55307 2035 if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
AnnaBridge 167:e84263d55307 2036 {
AnnaBridge 167:e84263d55307 2037 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
AnnaBridge 167:e84263d55307 2038 }
AnnaBridge 167:e84263d55307 2039
AnnaBridge 167:e84263d55307 2040 /* Disable Rx DMA Request */
AnnaBridge 167:e84263d55307 2041 CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_RXDMAEN));
AnnaBridge 167:e84263d55307 2042 }
AnnaBridge 167:e84263d55307 2043 }
AnnaBridge 167:e84263d55307 2044 /* Reset Tx and Rx transfer counters */
AnnaBridge 167:e84263d55307 2045 hspi->RxXferCount = 0U;
AnnaBridge 167:e84263d55307 2046 hspi->TxXferCount = 0U;
AnnaBridge 167:e84263d55307 2047
AnnaBridge 167:e84263d55307 2048 /* Check error during Abort procedure */
AnnaBridge 167:e84263d55307 2049 if (hspi->ErrorCode == HAL_SPI_ERROR_ABORT)
AnnaBridge 167:e84263d55307 2050 {
AnnaBridge 167:e84263d55307 2051 /* return HAL_Error in case of error during Abort procedure */
AnnaBridge 167:e84263d55307 2052 errorcode = HAL_ERROR;
AnnaBridge 167:e84263d55307 2053 }
AnnaBridge 167:e84263d55307 2054 else
AnnaBridge 167:e84263d55307 2055 {
AnnaBridge 167:e84263d55307 2056 /* Reset errorCode */
AnnaBridge 167:e84263d55307 2057 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
AnnaBridge 167:e84263d55307 2058 }
AnnaBridge 167:e84263d55307 2059
AnnaBridge 167:e84263d55307 2060 /* Clear the Error flags in the SR register */
AnnaBridge 167:e84263d55307 2061 __HAL_SPI_CLEAR_OVRFLAG(hspi);
AnnaBridge 167:e84263d55307 2062 __HAL_SPI_CLEAR_FREFLAG(hspi);
AnnaBridge 167:e84263d55307 2063
AnnaBridge 167:e84263d55307 2064 /* Restore hspi->state to ready */
AnnaBridge 167:e84263d55307 2065 hspi->State = HAL_SPI_STATE_READY;
AnnaBridge 167:e84263d55307 2066
AnnaBridge 167:e84263d55307 2067 return errorcode;
AnnaBridge 167:e84263d55307 2068 }
AnnaBridge 167:e84263d55307 2069
AnnaBridge 167:e84263d55307 2070 /**
AnnaBridge 167:e84263d55307 2071 * @brief Abort ongoing transfer (Interrupt mode).
AnnaBridge 167:e84263d55307 2072 * @param hspi SPI handle.
AnnaBridge 167:e84263d55307 2073 * @note This procedure could be used for aborting any ongoing transfer (Tx and Rx),
AnnaBridge 167:e84263d55307 2074 * started in Interrupt or DMA mode.
AnnaBridge 167:e84263d55307 2075 * This procedure performs following operations :
AnnaBridge 167:e84263d55307 2076 * - Disable SPI Interrupts (depending of transfer direction)
AnnaBridge 167:e84263d55307 2077 * - Disable the DMA transfer in the peripheral register (if enabled)
AnnaBridge 167:e84263d55307 2078 * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
AnnaBridge 167:e84263d55307 2079 * - Set handle State to READY
AnnaBridge 167:e84263d55307 2080 * - At abort completion, call user abort complete callback
AnnaBridge 167:e84263d55307 2081 * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
AnnaBridge 167:e84263d55307 2082 * considered as completed only when user abort complete callback is executed (not when exiting function).
AnnaBridge 167:e84263d55307 2083 * @retval HAL status
AnnaBridge 167:e84263d55307 2084 */
AnnaBridge 167:e84263d55307 2085 HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi)
AnnaBridge 167:e84263d55307 2086 {
AnnaBridge 167:e84263d55307 2087 HAL_StatusTypeDef errorcode;
AnnaBridge 167:e84263d55307 2088 uint32_t abortcplt ;
AnnaBridge 167:e84263d55307 2089 __IO uint32_t count, resetcount;
AnnaBridge 167:e84263d55307 2090
AnnaBridge 167:e84263d55307 2091 /* Initialized local variable */
AnnaBridge 167:e84263d55307 2092 errorcode = HAL_OK;
AnnaBridge 167:e84263d55307 2093 abortcplt = 1U;
AnnaBridge 167:e84263d55307 2094 resetcount = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
AnnaBridge 167:e84263d55307 2095 count = resetcount;
AnnaBridge 167:e84263d55307 2096
AnnaBridge 167:e84263d55307 2097 /* Change Rx and Tx Irq Handler to Disable TXEIE, RXNEIE and ERRIE interrupts */
AnnaBridge 167:e84263d55307 2098 if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE))
AnnaBridge 167:e84263d55307 2099 {
AnnaBridge 167:e84263d55307 2100 hspi->TxISR = SPI_AbortTx_ISR;
AnnaBridge 167:e84263d55307 2101 /* Wait HAL_SPI_STATE_ABORT state */
AnnaBridge 167:e84263d55307 2102 do
AnnaBridge 167:e84263d55307 2103 {
AnnaBridge 167:e84263d55307 2104 if (count-- == 0U)
AnnaBridge 167:e84263d55307 2105 {
AnnaBridge 167:e84263d55307 2106 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
AnnaBridge 167:e84263d55307 2107 break;
AnnaBridge 167:e84263d55307 2108 }
AnnaBridge 167:e84263d55307 2109 }
AnnaBridge 167:e84263d55307 2110 while (hspi->State != HAL_SPI_STATE_ABORT);
AnnaBridge 167:e84263d55307 2111 /* Reset Timeout Counter */
AnnaBridge 167:e84263d55307 2112 count = resetcount;
AnnaBridge 167:e84263d55307 2113 }
AnnaBridge 167:e84263d55307 2114
AnnaBridge 167:e84263d55307 2115 if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE))
AnnaBridge 167:e84263d55307 2116 {
AnnaBridge 167:e84263d55307 2117 hspi->RxISR = SPI_AbortRx_ISR;
AnnaBridge 167:e84263d55307 2118 /* Wait HAL_SPI_STATE_ABORT state */
AnnaBridge 167:e84263d55307 2119 do
AnnaBridge 167:e84263d55307 2120 {
AnnaBridge 167:e84263d55307 2121 if (count-- == 0U)
AnnaBridge 167:e84263d55307 2122 {
AnnaBridge 167:e84263d55307 2123 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
AnnaBridge 167:e84263d55307 2124 break;
AnnaBridge 167:e84263d55307 2125 }
AnnaBridge 167:e84263d55307 2126 }
AnnaBridge 167:e84263d55307 2127 while (hspi->State != HAL_SPI_STATE_ABORT);
AnnaBridge 167:e84263d55307 2128 /* Reset Timeout Counter */
AnnaBridge 167:e84263d55307 2129 count = resetcount;
AnnaBridge 167:e84263d55307 2130 }
AnnaBridge 167:e84263d55307 2131
AnnaBridge 167:e84263d55307 2132 /* Clear ERRIE interrupts in case of DMA Mode */
AnnaBridge 167:e84263d55307 2133 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE);
AnnaBridge 167:e84263d55307 2134
AnnaBridge 167:e84263d55307 2135 /* If DMA Tx and/or DMA Rx Handles are associated to SPI Handle, DMA Abort complete callbacks should be initialised
AnnaBridge 167:e84263d55307 2136 before any call to DMA Abort functions */
AnnaBridge 167:e84263d55307 2137 /* DMA Tx Handle is valid */
AnnaBridge 167:e84263d55307 2138 if (hspi->hdmatx != NULL)
AnnaBridge 167:e84263d55307 2139 {
AnnaBridge 167:e84263d55307 2140 /* Set DMA Abort Complete callback if UART DMA Tx request if enabled.
AnnaBridge 167:e84263d55307 2141 Otherwise, set it to NULL */
AnnaBridge 167:e84263d55307 2142 if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN))
AnnaBridge 167:e84263d55307 2143 {
AnnaBridge 167:e84263d55307 2144 hspi->hdmatx->XferAbortCallback = SPI_DMATxAbortCallback;
AnnaBridge 167:e84263d55307 2145 }
AnnaBridge 167:e84263d55307 2146 else
AnnaBridge 167:e84263d55307 2147 {
AnnaBridge 167:e84263d55307 2148 hspi->hdmatx->XferAbortCallback = NULL;
AnnaBridge 167:e84263d55307 2149 }
AnnaBridge 167:e84263d55307 2150 }
AnnaBridge 167:e84263d55307 2151 /* DMA Rx Handle is valid */
AnnaBridge 167:e84263d55307 2152 if (hspi->hdmarx != NULL)
AnnaBridge 167:e84263d55307 2153 {
AnnaBridge 167:e84263d55307 2154 /* Set DMA Abort Complete callback if UART DMA Rx request if enabled.
AnnaBridge 167:e84263d55307 2155 Otherwise, set it to NULL */
AnnaBridge 167:e84263d55307 2156 if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN))
AnnaBridge 167:e84263d55307 2157 {
AnnaBridge 167:e84263d55307 2158 hspi->hdmarx->XferAbortCallback = SPI_DMARxAbortCallback;
AnnaBridge 167:e84263d55307 2159 }
AnnaBridge 167:e84263d55307 2160 else
AnnaBridge 167:e84263d55307 2161 {
AnnaBridge 167:e84263d55307 2162 hspi->hdmarx->XferAbortCallback = NULL;
AnnaBridge 167:e84263d55307 2163 }
AnnaBridge 167:e84263d55307 2164 }
AnnaBridge 167:e84263d55307 2165
AnnaBridge 167:e84263d55307 2166 /* Disable the SPI DMA Tx or the SPI Rx request if enabled */
AnnaBridge 167:e84263d55307 2167 if ((HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN)) && (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN)))
AnnaBridge 167:e84263d55307 2168 {
AnnaBridge 167:e84263d55307 2169 /* Abort the SPI DMA Tx Stream/Channel */
AnnaBridge 167:e84263d55307 2170 if (hspi->hdmatx != NULL)
AnnaBridge 167:e84263d55307 2171 {
AnnaBridge 167:e84263d55307 2172 /* Abort DMA Tx Handle linked to SPI Peripheral */
AnnaBridge 167:e84263d55307 2173 if (HAL_DMA_Abort_IT(hspi->hdmatx) != HAL_OK)
AnnaBridge 167:e84263d55307 2174 {
AnnaBridge 167:e84263d55307 2175 hspi->hdmatx->XferAbortCallback = NULL;
AnnaBridge 167:e84263d55307 2176 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
AnnaBridge 167:e84263d55307 2177 }
AnnaBridge 167:e84263d55307 2178 else
AnnaBridge 167:e84263d55307 2179 {
AnnaBridge 167:e84263d55307 2180 abortcplt = 0U;
AnnaBridge 167:e84263d55307 2181 }
AnnaBridge 167:e84263d55307 2182 }
AnnaBridge 167:e84263d55307 2183 /* Abort the SPI DMA Rx Stream/Channel */
AnnaBridge 167:e84263d55307 2184 if (hspi->hdmarx != NULL)
AnnaBridge 167:e84263d55307 2185 {
AnnaBridge 167:e84263d55307 2186 /* Abort DMA Rx Handle linked to SPI Peripheral */
AnnaBridge 167:e84263d55307 2187 if (HAL_DMA_Abort_IT(hspi->hdmarx) != HAL_OK)
AnnaBridge 167:e84263d55307 2188 {
AnnaBridge 167:e84263d55307 2189 hspi->hdmarx->XferAbortCallback = NULL;
AnnaBridge 167:e84263d55307 2190 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
AnnaBridge 167:e84263d55307 2191 abortcplt = 1U;
AnnaBridge 167:e84263d55307 2192 }
AnnaBridge 167:e84263d55307 2193 else
AnnaBridge 167:e84263d55307 2194 {
AnnaBridge 167:e84263d55307 2195 abortcplt = 0U;
AnnaBridge 167:e84263d55307 2196 }
AnnaBridge 167:e84263d55307 2197 }
AnnaBridge 167:e84263d55307 2198 }
AnnaBridge 167:e84263d55307 2199
AnnaBridge 167:e84263d55307 2200 /* Disable the SPI DMA Tx or the SPI Rx request if enabled */
AnnaBridge 167:e84263d55307 2201 if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN))
AnnaBridge 167:e84263d55307 2202 {
AnnaBridge 167:e84263d55307 2203 /* Abort the SPI DMA Tx Stream/Channel */
AnnaBridge 167:e84263d55307 2204 if (hspi->hdmatx != NULL)
AnnaBridge 167:e84263d55307 2205 {
AnnaBridge 167:e84263d55307 2206 /* Abort DMA Tx Handle linked to SPI Peripheral */
AnnaBridge 167:e84263d55307 2207 if (HAL_DMA_Abort_IT(hspi->hdmatx) != HAL_OK)
AnnaBridge 167:e84263d55307 2208 {
AnnaBridge 167:e84263d55307 2209 hspi->hdmatx->XferAbortCallback = NULL;
AnnaBridge 167:e84263d55307 2210 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
AnnaBridge 167:e84263d55307 2211 }
AnnaBridge 167:e84263d55307 2212 else
AnnaBridge 167:e84263d55307 2213 {
AnnaBridge 167:e84263d55307 2214 abortcplt = 0U;
AnnaBridge 167:e84263d55307 2215 }
AnnaBridge 167:e84263d55307 2216 }
AnnaBridge 167:e84263d55307 2217 }
AnnaBridge 167:e84263d55307 2218 /* Disable the SPI DMA Tx or the SPI Rx request if enabled */
AnnaBridge 167:e84263d55307 2219 if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN))
AnnaBridge 167:e84263d55307 2220 {
AnnaBridge 167:e84263d55307 2221 /* Abort the SPI DMA Rx Stream/Channel */
AnnaBridge 167:e84263d55307 2222 if (hspi->hdmarx != NULL)
AnnaBridge 167:e84263d55307 2223 {
AnnaBridge 167:e84263d55307 2224 /* Abort DMA Rx Handle linked to SPI Peripheral */
AnnaBridge 167:e84263d55307 2225 if (HAL_DMA_Abort_IT(hspi->hdmarx) != HAL_OK)
AnnaBridge 167:e84263d55307 2226 {
AnnaBridge 167:e84263d55307 2227 hspi->hdmarx->XferAbortCallback = NULL;
AnnaBridge 167:e84263d55307 2228 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
AnnaBridge 167:e84263d55307 2229 }
AnnaBridge 167:e84263d55307 2230 else
AnnaBridge 167:e84263d55307 2231 {
AnnaBridge 167:e84263d55307 2232 abortcplt = 0U;
AnnaBridge 167:e84263d55307 2233 }
AnnaBridge 167:e84263d55307 2234 }
AnnaBridge 167:e84263d55307 2235 }
AnnaBridge 167:e84263d55307 2236
AnnaBridge 167:e84263d55307 2237 if (abortcplt == 1U)
AnnaBridge 167:e84263d55307 2238 {
AnnaBridge 167:e84263d55307 2239 /* Reset Tx and Rx transfer counters */
AnnaBridge 167:e84263d55307 2240 hspi->RxXferCount = 0U;
AnnaBridge 167:e84263d55307 2241 hspi->TxXferCount = 0U;
AnnaBridge 167:e84263d55307 2242
AnnaBridge 167:e84263d55307 2243 /* Check error during Abort procedure */
AnnaBridge 167:e84263d55307 2244 if (hspi->ErrorCode == HAL_SPI_ERROR_ABORT)
AnnaBridge 167:e84263d55307 2245 {
AnnaBridge 167:e84263d55307 2246 /* return HAL_Error in case of error during Abort procedure */
AnnaBridge 167:e84263d55307 2247 errorcode = HAL_ERROR;
AnnaBridge 167:e84263d55307 2248 }
AnnaBridge 167:e84263d55307 2249 else
AnnaBridge 167:e84263d55307 2250 {
AnnaBridge 167:e84263d55307 2251 /* Reset errorCode */
AnnaBridge 167:e84263d55307 2252 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
AnnaBridge 167:e84263d55307 2253 }
AnnaBridge 167:e84263d55307 2254
AnnaBridge 167:e84263d55307 2255 /* Clear the Error flags in the SR register */
AnnaBridge 167:e84263d55307 2256 __HAL_SPI_CLEAR_OVRFLAG(hspi);
AnnaBridge 167:e84263d55307 2257 __HAL_SPI_CLEAR_FREFLAG(hspi);
AnnaBridge 167:e84263d55307 2258
AnnaBridge 167:e84263d55307 2259 /* Restore hspi->State to Ready */
AnnaBridge 167:e84263d55307 2260 hspi->State = HAL_SPI_STATE_READY;
AnnaBridge 167:e84263d55307 2261
AnnaBridge 167:e84263d55307 2262 /* As no DMA to be aborted, call directly user Abort complete callback */
AnnaBridge 167:e84263d55307 2263 HAL_SPI_AbortCpltCallback(hspi);
AnnaBridge 167:e84263d55307 2264 }
AnnaBridge 167:e84263d55307 2265
AnnaBridge 167:e84263d55307 2266 return errorcode;
AnnaBridge 167:e84263d55307 2267 }
AnnaBridge 167:e84263d55307 2268
AnnaBridge 167:e84263d55307 2269 /**
AnnaBridge 167:e84263d55307 2270 * @brief Pause the DMA Transfer.
<> 144:ef7eb2e8f9f7 2271 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 2272 * the configuration information for the specified SPI module.
<> 144:ef7eb2e8f9f7 2273 * @retval HAL status
<> 144:ef7eb2e8f9f7 2274 */
<> 144:ef7eb2e8f9f7 2275 HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 2276 {
<> 144:ef7eb2e8f9f7 2277 /* Process Locked */
<> 144:ef7eb2e8f9f7 2278 __HAL_LOCK(hspi);
<> 144:ef7eb2e8f9f7 2279
<> 144:ef7eb2e8f9f7 2280 /* Disable the SPI DMA Tx & Rx requests */
<> 144:ef7eb2e8f9f7 2281 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
<> 144:ef7eb2e8f9f7 2282
<> 144:ef7eb2e8f9f7 2283 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 2284 __HAL_UNLOCK(hspi);
<> 144:ef7eb2e8f9f7 2285
<> 144:ef7eb2e8f9f7 2286 return HAL_OK;
<> 144:ef7eb2e8f9f7 2287 }
<> 144:ef7eb2e8f9f7 2288
<> 144:ef7eb2e8f9f7 2289 /**
AnnaBridge 167:e84263d55307 2290 * @brief Resume the DMA Transfer.
<> 144:ef7eb2e8f9f7 2291 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 2292 * the configuration information for the specified SPI module.
<> 144:ef7eb2e8f9f7 2293 * @retval HAL status
<> 144:ef7eb2e8f9f7 2294 */
<> 144:ef7eb2e8f9f7 2295 HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 2296 {
<> 144:ef7eb2e8f9f7 2297 /* Process Locked */
<> 144:ef7eb2e8f9f7 2298 __HAL_LOCK(hspi);
<> 144:ef7eb2e8f9f7 2299
<> 144:ef7eb2e8f9f7 2300 /* Enable the SPI DMA Tx & Rx requests */
<> 144:ef7eb2e8f9f7 2301 SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
<> 144:ef7eb2e8f9f7 2302
<> 144:ef7eb2e8f9f7 2303 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 2304 __HAL_UNLOCK(hspi);
<> 144:ef7eb2e8f9f7 2305
<> 144:ef7eb2e8f9f7 2306 return HAL_OK;
<> 144:ef7eb2e8f9f7 2307 }
<> 144:ef7eb2e8f9f7 2308
<> 144:ef7eb2e8f9f7 2309 /**
<> 144:ef7eb2e8f9f7 2310 * @brief Stop the DMA Transfer.
<> 144:ef7eb2e8f9f7 2311 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 2312 * the configuration information for the specified SPI module.
<> 144:ef7eb2e8f9f7 2313 * @retval HAL status
<> 144:ef7eb2e8f9f7 2314 */
<> 144:ef7eb2e8f9f7 2315 HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 2316 {
<> 144:ef7eb2e8f9f7 2317 /* The Lock is not implemented on this API to allow the user application
<> 144:ef7eb2e8f9f7 2318 to call the HAL SPI API under callbacks HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback():
<> 144:ef7eb2e8f9f7 2319 when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated
<> 144:ef7eb2e8f9f7 2320 and the correspond call back is executed HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback()
<> 144:ef7eb2e8f9f7 2321 */
<> 144:ef7eb2e8f9f7 2322
AnnaBridge 167:e84263d55307 2323 /* Abort the SPI DMA tx Stream/Channel */
AnnaBridge 167:e84263d55307 2324 if (hspi->hdmatx != NULL)
<> 144:ef7eb2e8f9f7 2325 {
<> 144:ef7eb2e8f9f7 2326 HAL_DMA_Abort(hspi->hdmatx);
<> 144:ef7eb2e8f9f7 2327 }
AnnaBridge 167:e84263d55307 2328 /* Abort the SPI DMA rx Stream/Channel */
AnnaBridge 167:e84263d55307 2329 if (hspi->hdmarx != NULL)
<> 144:ef7eb2e8f9f7 2330 {
<> 144:ef7eb2e8f9f7 2331 HAL_DMA_Abort(hspi->hdmarx);
<> 144:ef7eb2e8f9f7 2332 }
<> 144:ef7eb2e8f9f7 2333
<> 144:ef7eb2e8f9f7 2334 /* Disable the SPI DMA Tx & Rx requests */
<> 144:ef7eb2e8f9f7 2335 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
<> 144:ef7eb2e8f9f7 2336 hspi->State = HAL_SPI_STATE_READY;
<> 144:ef7eb2e8f9f7 2337 return HAL_OK;
<> 144:ef7eb2e8f9f7 2338 }
<> 144:ef7eb2e8f9f7 2339
<> 144:ef7eb2e8f9f7 2340 /**
<> 144:ef7eb2e8f9f7 2341 * @brief Handle SPI interrupt request.
<> 144:ef7eb2e8f9f7 2342 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 2343 * the configuration information for the specified SPI module.
<> 144:ef7eb2e8f9f7 2344 * @retval None
<> 144:ef7eb2e8f9f7 2345 */
<> 144:ef7eb2e8f9f7 2346 void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 2347 {
<> 144:ef7eb2e8f9f7 2348 uint32_t itsource = hspi->Instance->CR2;
<> 144:ef7eb2e8f9f7 2349 uint32_t itflag = hspi->Instance->SR;
<> 144:ef7eb2e8f9f7 2350
<> 144:ef7eb2e8f9f7 2351 /* SPI in mode Receiver ----------------------------------------------------*/
AnnaBridge 167:e84263d55307 2352 if (((itflag & SPI_FLAG_OVR) == RESET) &&
AnnaBridge 167:e84263d55307 2353 ((itflag & SPI_FLAG_RXNE) != RESET) && ((itsource & SPI_IT_RXNE) != RESET))
<> 144:ef7eb2e8f9f7 2354 {
<> 144:ef7eb2e8f9f7 2355 hspi->RxISR(hspi);
<> 144:ef7eb2e8f9f7 2356 return;
<> 144:ef7eb2e8f9f7 2357 }
<> 144:ef7eb2e8f9f7 2358
AnnaBridge 167:e84263d55307 2359 /* SPI in mode Transmitter -------------------------------------------------*/
AnnaBridge 167:e84263d55307 2360 if (((itflag & SPI_FLAG_TXE) != RESET) && ((itsource & SPI_IT_TXE) != RESET))
<> 144:ef7eb2e8f9f7 2361 {
<> 144:ef7eb2e8f9f7 2362 hspi->TxISR(hspi);
<> 144:ef7eb2e8f9f7 2363 return;
<> 144:ef7eb2e8f9f7 2364 }
<> 144:ef7eb2e8f9f7 2365
AnnaBridge 167:e84263d55307 2366 /* SPI in Error Treatment --------------------------------------------------*/
AnnaBridge 167:e84263d55307 2367 if (((itflag & (SPI_FLAG_MODF | SPI_FLAG_OVR | SPI_FLAG_FRE)) != RESET) && ((itsource & SPI_IT_ERR) != RESET))
<> 144:ef7eb2e8f9f7 2368 {
AnnaBridge 167:e84263d55307 2369 /* SPI Overrun error interrupt occurred ----------------------------------*/
AnnaBridge 167:e84263d55307 2370 if ((itflag & SPI_FLAG_OVR) != RESET)
<> 144:ef7eb2e8f9f7 2371 {
AnnaBridge 167:e84263d55307 2372 if (hspi->State != HAL_SPI_STATE_BUSY_TX)
<> 144:ef7eb2e8f9f7 2373 {
AnnaBridge 167:e84263d55307 2374 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_OVR);
<> 144:ef7eb2e8f9f7 2375 __HAL_SPI_CLEAR_OVRFLAG(hspi);
<> 144:ef7eb2e8f9f7 2376 }
<> 144:ef7eb2e8f9f7 2377 else
<> 144:ef7eb2e8f9f7 2378 {
AnnaBridge 167:e84263d55307 2379 __HAL_SPI_CLEAR_OVRFLAG(hspi);
<> 144:ef7eb2e8f9f7 2380 return;
<> 144:ef7eb2e8f9f7 2381 }
<> 144:ef7eb2e8f9f7 2382 }
<> 144:ef7eb2e8f9f7 2383
AnnaBridge 167:e84263d55307 2384 /* SPI Mode Fault error interrupt occurred -------------------------------*/
AnnaBridge 167:e84263d55307 2385 if ((itflag & SPI_FLAG_MODF) != RESET)
<> 144:ef7eb2e8f9f7 2386 {
AnnaBridge 167:e84263d55307 2387 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_MODF);
<> 144:ef7eb2e8f9f7 2388 __HAL_SPI_CLEAR_MODFFLAG(hspi);
<> 144:ef7eb2e8f9f7 2389 }
<> 144:ef7eb2e8f9f7 2390
AnnaBridge 167:e84263d55307 2391 /* SPI Frame error interrupt occurred ------------------------------------*/
AnnaBridge 167:e84263d55307 2392 if ((itflag & SPI_FLAG_FRE) != RESET)
<> 144:ef7eb2e8f9f7 2393 {
AnnaBridge 167:e84263d55307 2394 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FRE);
<> 144:ef7eb2e8f9f7 2395 __HAL_SPI_CLEAR_FREFLAG(hspi);
<> 144:ef7eb2e8f9f7 2396 }
<> 144:ef7eb2e8f9f7 2397
AnnaBridge 167:e84263d55307 2398 if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
AnnaBridge 167:e84263d55307 2399 {
AnnaBridge 167:e84263d55307 2400 /* Disable all interrupts */
AnnaBridge 167:e84263d55307 2401 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE | SPI_IT_TXE | SPI_IT_ERR);
AnnaBridge 167:e84263d55307 2402
AnnaBridge 167:e84263d55307 2403 hspi->State = HAL_SPI_STATE_READY;
AnnaBridge 167:e84263d55307 2404 /* Disable the SPI DMA requests if enabled */
AnnaBridge 167:e84263d55307 2405 if ((HAL_IS_BIT_SET(itsource, SPI_CR2_TXDMAEN)) || (HAL_IS_BIT_SET(itsource, SPI_CR2_RXDMAEN)))
AnnaBridge 167:e84263d55307 2406 {
AnnaBridge 167:e84263d55307 2407 CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN));
AnnaBridge 167:e84263d55307 2408
AnnaBridge 167:e84263d55307 2409 /* Abort the SPI DMA Rx channel */
AnnaBridge 167:e84263d55307 2410 if (hspi->hdmarx != NULL)
AnnaBridge 167:e84263d55307 2411 {
AnnaBridge 167:e84263d55307 2412 /* Set the SPI DMA Abort callback :
AnnaBridge 167:e84263d55307 2413 will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */
AnnaBridge 167:e84263d55307 2414 hspi->hdmarx->XferAbortCallback = SPI_DMAAbortOnError;
AnnaBridge 167:e84263d55307 2415 HAL_DMA_Abort_IT(hspi->hdmarx);
AnnaBridge 167:e84263d55307 2416 }
AnnaBridge 167:e84263d55307 2417 /* Abort the SPI DMA Tx channel */
AnnaBridge 167:e84263d55307 2418 if (hspi->hdmatx != NULL)
AnnaBridge 167:e84263d55307 2419 {
AnnaBridge 167:e84263d55307 2420 /* Set the SPI DMA Abort callback :
AnnaBridge 167:e84263d55307 2421 will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */
AnnaBridge 167:e84263d55307 2422 hspi->hdmatx->XferAbortCallback = SPI_DMAAbortOnError;
AnnaBridge 167:e84263d55307 2423 HAL_DMA_Abort_IT(hspi->hdmatx);
AnnaBridge 167:e84263d55307 2424 }
AnnaBridge 167:e84263d55307 2425 }
AnnaBridge 167:e84263d55307 2426 else
AnnaBridge 167:e84263d55307 2427 {
AnnaBridge 167:e84263d55307 2428 /* Call user error callback */
AnnaBridge 167:e84263d55307 2429 HAL_SPI_ErrorCallback(hspi);
AnnaBridge 167:e84263d55307 2430 }
AnnaBridge 167:e84263d55307 2431 }
<> 144:ef7eb2e8f9f7 2432 return;
<> 144:ef7eb2e8f9f7 2433 }
<> 144:ef7eb2e8f9f7 2434 }
<> 144:ef7eb2e8f9f7 2435
<> 144:ef7eb2e8f9f7 2436 /**
<> 144:ef7eb2e8f9f7 2437 * @brief Tx Transfer completed callback.
<> 144:ef7eb2e8f9f7 2438 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 2439 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 2440 * @retval None
<> 144:ef7eb2e8f9f7 2441 */
<> 144:ef7eb2e8f9f7 2442 __weak void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 2443 {
<> 144:ef7eb2e8f9f7 2444 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 2445 UNUSED(hspi);
<> 144:ef7eb2e8f9f7 2446
<> 144:ef7eb2e8f9f7 2447 /* NOTE : This function should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 2448 the HAL_SPI_TxCpltCallback should be implemented in the user file
<> 144:ef7eb2e8f9f7 2449 */
<> 144:ef7eb2e8f9f7 2450 }
<> 144:ef7eb2e8f9f7 2451
<> 144:ef7eb2e8f9f7 2452 /**
<> 144:ef7eb2e8f9f7 2453 * @brief Rx Transfer completed callback.
<> 144:ef7eb2e8f9f7 2454 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 2455 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 2456 * @retval None
<> 144:ef7eb2e8f9f7 2457 */
<> 144:ef7eb2e8f9f7 2458 __weak void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 2459 {
<> 144:ef7eb2e8f9f7 2460 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 2461 UNUSED(hspi);
<> 144:ef7eb2e8f9f7 2462
<> 144:ef7eb2e8f9f7 2463 /* NOTE : This function should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 2464 the HAL_SPI_RxCpltCallback should be implemented in the user file
<> 144:ef7eb2e8f9f7 2465 */
<> 144:ef7eb2e8f9f7 2466 }
<> 144:ef7eb2e8f9f7 2467
<> 144:ef7eb2e8f9f7 2468 /**
<> 144:ef7eb2e8f9f7 2469 * @brief Tx and Rx Transfer completed callback.
<> 144:ef7eb2e8f9f7 2470 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 2471 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 2472 * @retval None
<> 144:ef7eb2e8f9f7 2473 */
<> 144:ef7eb2e8f9f7 2474 __weak void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 2475 {
<> 144:ef7eb2e8f9f7 2476 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 2477 UNUSED(hspi);
<> 144:ef7eb2e8f9f7 2478
<> 144:ef7eb2e8f9f7 2479 /* NOTE : This function should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 2480 the HAL_SPI_TxRxCpltCallback should be implemented in the user file
<> 144:ef7eb2e8f9f7 2481 */
<> 144:ef7eb2e8f9f7 2482 }
<> 144:ef7eb2e8f9f7 2483
<> 144:ef7eb2e8f9f7 2484 /**
<> 144:ef7eb2e8f9f7 2485 * @brief Tx Half Transfer completed callback.
<> 144:ef7eb2e8f9f7 2486 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 2487 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 2488 * @retval None
<> 144:ef7eb2e8f9f7 2489 */
<> 144:ef7eb2e8f9f7 2490 __weak void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 2491 {
<> 144:ef7eb2e8f9f7 2492 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 2493 UNUSED(hspi);
<> 144:ef7eb2e8f9f7 2494
<> 144:ef7eb2e8f9f7 2495 /* NOTE : This function should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 2496 the HAL_SPI_TxHalfCpltCallback should be implemented in the user file
<> 144:ef7eb2e8f9f7 2497 */
<> 144:ef7eb2e8f9f7 2498 }
<> 144:ef7eb2e8f9f7 2499
<> 144:ef7eb2e8f9f7 2500 /**
<> 144:ef7eb2e8f9f7 2501 * @brief Rx Half Transfer completed callback.
<> 144:ef7eb2e8f9f7 2502 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 2503 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 2504 * @retval None
<> 144:ef7eb2e8f9f7 2505 */
<> 144:ef7eb2e8f9f7 2506 __weak void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 2507 {
<> 144:ef7eb2e8f9f7 2508 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 2509 UNUSED(hspi);
<> 144:ef7eb2e8f9f7 2510
<> 144:ef7eb2e8f9f7 2511 /* NOTE : This function should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 2512 the HAL_SPI_RxHalfCpltCallback() should be implemented in the user file
<> 144:ef7eb2e8f9f7 2513 */
<> 144:ef7eb2e8f9f7 2514 }
<> 144:ef7eb2e8f9f7 2515
<> 144:ef7eb2e8f9f7 2516 /**
<> 144:ef7eb2e8f9f7 2517 * @brief Tx and Rx Half Transfer callback.
<> 144:ef7eb2e8f9f7 2518 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 2519 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 2520 * @retval None
<> 144:ef7eb2e8f9f7 2521 */
<> 144:ef7eb2e8f9f7 2522 __weak void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 2523 {
<> 144:ef7eb2e8f9f7 2524 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 2525 UNUSED(hspi);
<> 144:ef7eb2e8f9f7 2526
<> 144:ef7eb2e8f9f7 2527 /* NOTE : This function should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 2528 the HAL_SPI_TxRxHalfCpltCallback() should be implemented in the user file
<> 144:ef7eb2e8f9f7 2529 */
<> 144:ef7eb2e8f9f7 2530 }
<> 144:ef7eb2e8f9f7 2531
<> 144:ef7eb2e8f9f7 2532 /**
<> 144:ef7eb2e8f9f7 2533 * @brief SPI error callback.
<> 144:ef7eb2e8f9f7 2534 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 2535 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 2536 * @retval None
<> 144:ef7eb2e8f9f7 2537 */
<> 144:ef7eb2e8f9f7 2538 __weak void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 2539 {
<> 144:ef7eb2e8f9f7 2540 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 2541 UNUSED(hspi);
<> 144:ef7eb2e8f9f7 2542
<> 144:ef7eb2e8f9f7 2543 /* NOTE : This function should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 2544 the HAL_SPI_ErrorCallback should be implemented in the user file
<> 144:ef7eb2e8f9f7 2545 */
<> 144:ef7eb2e8f9f7 2546 /* NOTE : The ErrorCode parameter in the hspi handle is updated by the SPI processes
<> 144:ef7eb2e8f9f7 2547 and user can use HAL_SPI_GetError() API to check the latest error occurred
<> 144:ef7eb2e8f9f7 2548 */
<> 144:ef7eb2e8f9f7 2549 }
<> 144:ef7eb2e8f9f7 2550
<> 144:ef7eb2e8f9f7 2551 /**
AnnaBridge 167:e84263d55307 2552 * @brief SPI Abort Complete callback.
AnnaBridge 167:e84263d55307 2553 * @param hspi SPI handle.
AnnaBridge 167:e84263d55307 2554 * @retval None
AnnaBridge 167:e84263d55307 2555 */
AnnaBridge 167:e84263d55307 2556 __weak void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi)
AnnaBridge 167:e84263d55307 2557 {
AnnaBridge 167:e84263d55307 2558 /* Prevent unused argument(s) compilation warning */
AnnaBridge 167:e84263d55307 2559 UNUSED(hspi);
AnnaBridge 167:e84263d55307 2560
AnnaBridge 167:e84263d55307 2561 /* NOTE : This function should not be modified, when the callback is needed,
AnnaBridge 167:e84263d55307 2562 the HAL_SPI_AbortCpltCallback can be implemented in the user file.
AnnaBridge 167:e84263d55307 2563 */
AnnaBridge 167:e84263d55307 2564 }
AnnaBridge 167:e84263d55307 2565
AnnaBridge 167:e84263d55307 2566 /**
<> 144:ef7eb2e8f9f7 2567 * @}
<> 144:ef7eb2e8f9f7 2568 */
<> 144:ef7eb2e8f9f7 2569
<> 144:ef7eb2e8f9f7 2570 /** @defgroup SPI_Exported_Functions_Group3 Peripheral State and Errors functions
AnnaBridge 167:e84263d55307 2571 * @brief SPI control functions
<> 144:ef7eb2e8f9f7 2572 *
<> 144:ef7eb2e8f9f7 2573 @verbatim
<> 144:ef7eb2e8f9f7 2574 ===============================================================================
<> 144:ef7eb2e8f9f7 2575 ##### Peripheral State and Errors functions #####
<> 144:ef7eb2e8f9f7 2576 ===============================================================================
<> 144:ef7eb2e8f9f7 2577 [..]
<> 144:ef7eb2e8f9f7 2578 This subsection provides a set of functions allowing to control the SPI.
<> 144:ef7eb2e8f9f7 2579 (+) HAL_SPI_GetState() API can be helpful to check in run-time the state of the SPI peripheral
<> 144:ef7eb2e8f9f7 2580 (+) HAL_SPI_GetError() check in run-time Errors occurring during communication
<> 144:ef7eb2e8f9f7 2581 @endverbatim
<> 144:ef7eb2e8f9f7 2582 * @{
<> 144:ef7eb2e8f9f7 2583 */
<> 144:ef7eb2e8f9f7 2584
<> 144:ef7eb2e8f9f7 2585 /**
<> 144:ef7eb2e8f9f7 2586 * @brief Return the SPI handle state.
<> 144:ef7eb2e8f9f7 2587 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 2588 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 2589 * @retval SPI state
<> 144:ef7eb2e8f9f7 2590 */
<> 144:ef7eb2e8f9f7 2591 HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 2592 {
<> 144:ef7eb2e8f9f7 2593 /* Return SPI handle state */
<> 144:ef7eb2e8f9f7 2594 return hspi->State;
<> 144:ef7eb2e8f9f7 2595 }
<> 144:ef7eb2e8f9f7 2596
<> 144:ef7eb2e8f9f7 2597 /**
<> 144:ef7eb2e8f9f7 2598 * @brief Return the SPI error code.
<> 144:ef7eb2e8f9f7 2599 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 2600 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 2601 * @retval SPI error code in bitmap format
<> 144:ef7eb2e8f9f7 2602 */
<> 144:ef7eb2e8f9f7 2603 uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 2604 {
AnnaBridge 167:e84263d55307 2605 /* Return SPI ErrorCode */
<> 144:ef7eb2e8f9f7 2606 return hspi->ErrorCode;
<> 144:ef7eb2e8f9f7 2607 }
<> 144:ef7eb2e8f9f7 2608
<> 144:ef7eb2e8f9f7 2609 /**
<> 144:ef7eb2e8f9f7 2610 * @}
<> 144:ef7eb2e8f9f7 2611 */
<> 144:ef7eb2e8f9f7 2612
<> 144:ef7eb2e8f9f7 2613 /**
<> 144:ef7eb2e8f9f7 2614 * @}
<> 144:ef7eb2e8f9f7 2615 */
<> 144:ef7eb2e8f9f7 2616
<> 144:ef7eb2e8f9f7 2617 /** @addtogroup SPI_Private_Functions
AnnaBridge 167:e84263d55307 2618 * @brief Private functions
<> 144:ef7eb2e8f9f7 2619 * @{
<> 144:ef7eb2e8f9f7 2620 */
<> 144:ef7eb2e8f9f7 2621
<> 144:ef7eb2e8f9f7 2622 /**
<> 144:ef7eb2e8f9f7 2623 * @brief DMA SPI transmit process complete callback.
<> 144:ef7eb2e8f9f7 2624 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 2625 * the configuration information for the specified DMA module.
<> 144:ef7eb2e8f9f7 2626 * @retval None
<> 144:ef7eb2e8f9f7 2627 */
<> 144:ef7eb2e8f9f7 2628 static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 2629 {
AnnaBridge 167:e84263d55307 2630 SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
AnnaBridge 167:e84263d55307 2631 uint32_t tickstart = 0U;
AnnaBridge 167:e84263d55307 2632
AnnaBridge 167:e84263d55307 2633 /* Init tickstart for timeout managment*/
AnnaBridge 167:e84263d55307 2634 tickstart = HAL_GetTick();
AnnaBridge 167:e84263d55307 2635
AnnaBridge 167:e84263d55307 2636 /* DMA Normal Mode */
AnnaBridge 167:e84263d55307 2637 if ((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC)
<> 144:ef7eb2e8f9f7 2638 {
AnnaBridge 167:e84263d55307 2639 /* Disable ERR interrupt */
AnnaBridge 167:e84263d55307 2640 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
AnnaBridge 167:e84263d55307 2641
<> 144:ef7eb2e8f9f7 2642 /* Disable Tx DMA Request */
<> 144:ef7eb2e8f9f7 2643 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
<> 144:ef7eb2e8f9f7 2644
<> 144:ef7eb2e8f9f7 2645 /* Check the end of the transaction */
AnnaBridge 167:e84263d55307 2646 if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
<> 144:ef7eb2e8f9f7 2647 {
AnnaBridge 167:e84263d55307 2648 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
<> 144:ef7eb2e8f9f7 2649 }
<> 144:ef7eb2e8f9f7 2650
<> 144:ef7eb2e8f9f7 2651 /* Clear overrun flag in 2 Lines communication mode because received data is not read */
AnnaBridge 167:e84263d55307 2652 if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
<> 144:ef7eb2e8f9f7 2653 {
<> 144:ef7eb2e8f9f7 2654 __HAL_SPI_CLEAR_OVRFLAG(hspi);
<> 144:ef7eb2e8f9f7 2655 }
<> 144:ef7eb2e8f9f7 2656
AnnaBridge 167:e84263d55307 2657 hspi->TxXferCount = 0U;
<> 144:ef7eb2e8f9f7 2658 hspi->State = HAL_SPI_STATE_READY;
<> 144:ef7eb2e8f9f7 2659
AnnaBridge 167:e84263d55307 2660 if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
<> 144:ef7eb2e8f9f7 2661 {
<> 144:ef7eb2e8f9f7 2662 HAL_SPI_ErrorCallback(hspi);
<> 144:ef7eb2e8f9f7 2663 return;
<> 144:ef7eb2e8f9f7 2664 }
<> 144:ef7eb2e8f9f7 2665 }
<> 144:ef7eb2e8f9f7 2666 HAL_SPI_TxCpltCallback(hspi);
<> 144:ef7eb2e8f9f7 2667 }
<> 144:ef7eb2e8f9f7 2668
<> 144:ef7eb2e8f9f7 2669 /**
<> 144:ef7eb2e8f9f7 2670 * @brief DMA SPI receive process complete callback.
<> 144:ef7eb2e8f9f7 2671 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 2672 * the configuration information for the specified DMA module.
<> 144:ef7eb2e8f9f7 2673 * @retval None
<> 144:ef7eb2e8f9f7 2674 */
<> 144:ef7eb2e8f9f7 2675 static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 2676 {
AnnaBridge 167:e84263d55307 2677 SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
AnnaBridge 167:e84263d55307 2678 uint32_t tickstart = 0U;
AnnaBridge 167:e84263d55307 2679 #if (USE_SPI_CRC != 0U)
AnnaBridge 167:e84263d55307 2680 __IO uint16_t tmpreg = 0U;
AnnaBridge 167:e84263d55307 2681 #endif /* USE_SPI_CRC */
AnnaBridge 167:e84263d55307 2682
AnnaBridge 167:e84263d55307 2683 /* Init tickstart for timeout management*/
AnnaBridge 167:e84263d55307 2684 tickstart = HAL_GetTick();
AnnaBridge 167:e84263d55307 2685
AnnaBridge 167:e84263d55307 2686 /* DMA Normal Mode */
AnnaBridge 167:e84263d55307 2687 if ((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC)
<> 144:ef7eb2e8f9f7 2688 {
AnnaBridge 167:e84263d55307 2689 /* Disable ERR interrupt */
AnnaBridge 167:e84263d55307 2690 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
AnnaBridge 167:e84263d55307 2691
AnnaBridge 167:e84263d55307 2692 #if (USE_SPI_CRC != 0U)
<> 144:ef7eb2e8f9f7 2693 /* CRC handling */
AnnaBridge 167:e84263d55307 2694 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<> 144:ef7eb2e8f9f7 2695 {
AnnaBridge 167:e84263d55307 2696 /* Wait until RXNE flag */
AnnaBridge 167:e84263d55307 2697 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
<> 144:ef7eb2e8f9f7 2698 {
<> 144:ef7eb2e8f9f7 2699 /* Error on the CRC reception */
AnnaBridge 167:e84263d55307 2700 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
<> 144:ef7eb2e8f9f7 2701 }
AnnaBridge 167:e84263d55307 2702 /* Read CRC */
AnnaBridge 167:e84263d55307 2703 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
<> 144:ef7eb2e8f9f7 2704 {
<> 144:ef7eb2e8f9f7 2705 tmpreg = hspi->Instance->DR;
AnnaBridge 167:e84263d55307 2706 /* To avoid GCC warning */
AnnaBridge 167:e84263d55307 2707 UNUSED(tmpreg);
<> 144:ef7eb2e8f9f7 2708 }
<> 144:ef7eb2e8f9f7 2709 else
<> 144:ef7eb2e8f9f7 2710 {
<> 144:ef7eb2e8f9f7 2711 tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
AnnaBridge 167:e84263d55307 2712 /* To avoid GCC warning */
AnnaBridge 167:e84263d55307 2713 UNUSED(tmpreg);
AnnaBridge 167:e84263d55307 2714
AnnaBridge 167:e84263d55307 2715 if (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)
<> 144:ef7eb2e8f9f7 2716 {
AnnaBridge 167:e84263d55307 2717 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
<> 144:ef7eb2e8f9f7 2718 {
<> 144:ef7eb2e8f9f7 2719 /* Error on the CRC reception */
AnnaBridge 167:e84263d55307 2720 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
<> 144:ef7eb2e8f9f7 2721 }
<> 144:ef7eb2e8f9f7 2722 tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
AnnaBridge 167:e84263d55307 2723 /* To avoid GCC warning */
AnnaBridge 167:e84263d55307 2724 UNUSED(tmpreg);
<> 144:ef7eb2e8f9f7 2725 }
<> 144:ef7eb2e8f9f7 2726 }
<> 144:ef7eb2e8f9f7 2727 }
AnnaBridge 167:e84263d55307 2728 #endif /* USE_SPI_CRC */
<> 144:ef7eb2e8f9f7 2729
<> 144:ef7eb2e8f9f7 2730 /* Disable Rx/Tx DMA Request (done by default to handle the case master rx direction 2 lines) */
<> 144:ef7eb2e8f9f7 2731 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
<> 144:ef7eb2e8f9f7 2732
<> 144:ef7eb2e8f9f7 2733 /* Check the end of the transaction */
AnnaBridge 167:e84263d55307 2734 if (SPI_EndRxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
<> 144:ef7eb2e8f9f7 2735 {
AnnaBridge 167:e84263d55307 2736 hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
<> 144:ef7eb2e8f9f7 2737 }
<> 144:ef7eb2e8f9f7 2738
AnnaBridge 167:e84263d55307 2739 hspi->RxXferCount = 0U;
<> 144:ef7eb2e8f9f7 2740 hspi->State = HAL_SPI_STATE_READY;
<> 144:ef7eb2e8f9f7 2741
AnnaBridge 167:e84263d55307 2742 #if (USE_SPI_CRC != 0U)
<> 144:ef7eb2e8f9f7 2743 /* Check if CRC error occurred */
AnnaBridge 167:e84263d55307 2744 if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))
<> 144:ef7eb2e8f9f7 2745 {
AnnaBridge 167:e84263d55307 2746 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
<> 144:ef7eb2e8f9f7 2747 __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
<> 144:ef7eb2e8f9f7 2748 }
AnnaBridge 167:e84263d55307 2749 #endif /* USE_SPI_CRC */
AnnaBridge 167:e84263d55307 2750
AnnaBridge 167:e84263d55307 2751 if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
<> 144:ef7eb2e8f9f7 2752 {
<> 144:ef7eb2e8f9f7 2753 HAL_SPI_ErrorCallback(hspi);
<> 144:ef7eb2e8f9f7 2754 return;
<> 144:ef7eb2e8f9f7 2755 }
<> 144:ef7eb2e8f9f7 2756 }
<> 144:ef7eb2e8f9f7 2757 HAL_SPI_RxCpltCallback(hspi);
<> 144:ef7eb2e8f9f7 2758 }
<> 144:ef7eb2e8f9f7 2759
<> 144:ef7eb2e8f9f7 2760 /**
AnnaBridge 167:e84263d55307 2761 * @brief DMA SPI transmit receive process complete callback.
AnnaBridge 167:e84263d55307 2762 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 2763 * the configuration information for the specified DMA module.
<> 144:ef7eb2e8f9f7 2764 * @retval None
<> 144:ef7eb2e8f9f7 2765 */
<> 144:ef7eb2e8f9f7 2766 static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 2767 {
AnnaBridge 167:e84263d55307 2768 SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
AnnaBridge 167:e84263d55307 2769 uint32_t tickstart = 0U;
AnnaBridge 167:e84263d55307 2770 #if (USE_SPI_CRC != 0U)
AnnaBridge 167:e84263d55307 2771 __IO int16_t tmpreg = 0U;
AnnaBridge 167:e84263d55307 2772 #endif /* USE_SPI_CRC */
AnnaBridge 167:e84263d55307 2773 /* Init tickstart for timeout management*/
AnnaBridge 167:e84263d55307 2774 tickstart = HAL_GetTick();
AnnaBridge 167:e84263d55307 2775
AnnaBridge 167:e84263d55307 2776 /* DMA Normal Mode */
AnnaBridge 167:e84263d55307 2777 if ((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC)
<> 144:ef7eb2e8f9f7 2778 {
AnnaBridge 167:e84263d55307 2779 /* Disable ERR interrupt */
AnnaBridge 167:e84263d55307 2780 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
AnnaBridge 167:e84263d55307 2781
AnnaBridge 167:e84263d55307 2782 #if (USE_SPI_CRC != 0U)
<> 144:ef7eb2e8f9f7 2783 /* CRC handling */
AnnaBridge 167:e84263d55307 2784 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<> 144:ef7eb2e8f9f7 2785 {
AnnaBridge 167:e84263d55307 2786 if ((hspi->Init.DataSize == SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_8BIT))
<> 144:ef7eb2e8f9f7 2787 {
AnnaBridge 167:e84263d55307 2788 if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_QUARTER_FULL, SPI_DEFAULT_TIMEOUT,
AnnaBridge 167:e84263d55307 2789 tickstart) != HAL_OK)
<> 144:ef7eb2e8f9f7 2790 {
<> 144:ef7eb2e8f9f7 2791 /* Error on the CRC reception */
AnnaBridge 167:e84263d55307 2792 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
<> 144:ef7eb2e8f9f7 2793 }
AnnaBridge 167:e84263d55307 2794 /* Read CRC to Flush DR and RXNE flag */
<> 144:ef7eb2e8f9f7 2795 tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
AnnaBridge 167:e84263d55307 2796 /* To avoid GCC warning */
AnnaBridge 167:e84263d55307 2797 UNUSED(tmpreg);
<> 144:ef7eb2e8f9f7 2798 }
<> 144:ef7eb2e8f9f7 2799 else
<> 144:ef7eb2e8f9f7 2800 {
AnnaBridge 167:e84263d55307 2801 if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_HALF_FULL, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
<> 144:ef7eb2e8f9f7 2802 {
<> 144:ef7eb2e8f9f7 2803 /* Error on the CRC reception */
AnnaBridge 167:e84263d55307 2804 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
<> 144:ef7eb2e8f9f7 2805 }
AnnaBridge 167:e84263d55307 2806 /* Read CRC to Flush DR and RXNE flag */
<> 144:ef7eb2e8f9f7 2807 tmpreg = hspi->Instance->DR;
AnnaBridge 167:e84263d55307 2808 /* To avoid GCC warning */
AnnaBridge 167:e84263d55307 2809 UNUSED(tmpreg);
<> 144:ef7eb2e8f9f7 2810 }
<> 144:ef7eb2e8f9f7 2811 }
AnnaBridge 167:e84263d55307 2812 #endif /* USE_SPI_CRC */
<> 144:ef7eb2e8f9f7 2813
<> 144:ef7eb2e8f9f7 2814 /* Check the end of the transaction */
AnnaBridge 167:e84263d55307 2815 if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
<> 144:ef7eb2e8f9f7 2816 {
AnnaBridge 167:e84263d55307 2817 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
<> 144:ef7eb2e8f9f7 2818 }
AnnaBridge 167:e84263d55307 2819
<> 144:ef7eb2e8f9f7 2820 /* Disable Rx/Tx DMA Request */
<> 144:ef7eb2e8f9f7 2821 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
<> 144:ef7eb2e8f9f7 2822
AnnaBridge 167:e84263d55307 2823 hspi->TxXferCount = 0U;
AnnaBridge 167:e84263d55307 2824 hspi->RxXferCount = 0U;
<> 144:ef7eb2e8f9f7 2825 hspi->State = HAL_SPI_STATE_READY;
<> 144:ef7eb2e8f9f7 2826
AnnaBridge 167:e84263d55307 2827 #if (USE_SPI_CRC != 0U)
<> 144:ef7eb2e8f9f7 2828 /* Check if CRC error occurred */
AnnaBridge 167:e84263d55307 2829 if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))
<> 144:ef7eb2e8f9f7 2830 {
AnnaBridge 167:e84263d55307 2831 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
<> 144:ef7eb2e8f9f7 2832 __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
<> 144:ef7eb2e8f9f7 2833 }
AnnaBridge 167:e84263d55307 2834 #endif /* USE_SPI_CRC */
AnnaBridge 167:e84263d55307 2835
AnnaBridge 167:e84263d55307 2836 if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
<> 144:ef7eb2e8f9f7 2837 {
<> 144:ef7eb2e8f9f7 2838 HAL_SPI_ErrorCallback(hspi);
<> 144:ef7eb2e8f9f7 2839 return;
<> 144:ef7eb2e8f9f7 2840 }
<> 144:ef7eb2e8f9f7 2841 }
<> 144:ef7eb2e8f9f7 2842 HAL_SPI_TxRxCpltCallback(hspi);
<> 144:ef7eb2e8f9f7 2843 }
<> 144:ef7eb2e8f9f7 2844
<> 144:ef7eb2e8f9f7 2845 /**
AnnaBridge 167:e84263d55307 2846 * @brief DMA SPI half transmit process complete callback.
AnnaBridge 167:e84263d55307 2847 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 2848 * the configuration information for the specified DMA module.
<> 144:ef7eb2e8f9f7 2849 * @retval None
<> 144:ef7eb2e8f9f7 2850 */
<> 144:ef7eb2e8f9f7 2851 static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 2852 {
AnnaBridge 167:e84263d55307 2853 SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
<> 144:ef7eb2e8f9f7 2854
<> 144:ef7eb2e8f9f7 2855 HAL_SPI_TxHalfCpltCallback(hspi);
<> 144:ef7eb2e8f9f7 2856 }
<> 144:ef7eb2e8f9f7 2857
<> 144:ef7eb2e8f9f7 2858 /**
AnnaBridge 167:e84263d55307 2859 * @brief DMA SPI half receive process complete callback
<> 144:ef7eb2e8f9f7 2860 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 2861 * the configuration information for the specified DMA module.
<> 144:ef7eb2e8f9f7 2862 * @retval None
<> 144:ef7eb2e8f9f7 2863 */
<> 144:ef7eb2e8f9f7 2864 static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 2865 {
AnnaBridge 167:e84263d55307 2866 SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
<> 144:ef7eb2e8f9f7 2867
<> 144:ef7eb2e8f9f7 2868 HAL_SPI_RxHalfCpltCallback(hspi);
<> 144:ef7eb2e8f9f7 2869 }
<> 144:ef7eb2e8f9f7 2870
<> 144:ef7eb2e8f9f7 2871 /**
AnnaBridge 167:e84263d55307 2872 * @brief DMA SPI half transmit receive process complete callback.
AnnaBridge 167:e84263d55307 2873 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 2874 * the configuration information for the specified DMA module.
<> 144:ef7eb2e8f9f7 2875 * @retval None
<> 144:ef7eb2e8f9f7 2876 */
<> 144:ef7eb2e8f9f7 2877 static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 2878 {
AnnaBridge 167:e84263d55307 2879 SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
<> 144:ef7eb2e8f9f7 2880
<> 144:ef7eb2e8f9f7 2881 HAL_SPI_TxRxHalfCpltCallback(hspi);
<> 144:ef7eb2e8f9f7 2882 }
<> 144:ef7eb2e8f9f7 2883
<> 144:ef7eb2e8f9f7 2884 /**
AnnaBridge 167:e84263d55307 2885 * @brief DMA SPI communication error callback.
AnnaBridge 167:e84263d55307 2886 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 2887 * the configuration information for the specified DMA module.
<> 144:ef7eb2e8f9f7 2888 * @retval None
<> 144:ef7eb2e8f9f7 2889 */
<> 144:ef7eb2e8f9f7 2890 static void SPI_DMAError(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 2891 {
AnnaBridge 167:e84263d55307 2892 SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
<> 144:ef7eb2e8f9f7 2893
<> 144:ef7eb2e8f9f7 2894 /* Stop the disable DMA transfer on SPI side */
<> 144:ef7eb2e8f9f7 2895 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
<> 144:ef7eb2e8f9f7 2896
AnnaBridge 167:e84263d55307 2897 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
<> 144:ef7eb2e8f9f7 2898 hspi->State = HAL_SPI_STATE_READY;
<> 144:ef7eb2e8f9f7 2899 HAL_SPI_ErrorCallback(hspi);
<> 144:ef7eb2e8f9f7 2900 }
<> 144:ef7eb2e8f9f7 2901
<> 144:ef7eb2e8f9f7 2902 /**
AnnaBridge 167:e84263d55307 2903 * @brief DMA SPI communication abort callback, when initiated by HAL services on Error
AnnaBridge 167:e84263d55307 2904 * (To be called at end of DMA Abort procedure following error occurrence).
AnnaBridge 167:e84263d55307 2905 * @param hdma DMA handle.
AnnaBridge 167:e84263d55307 2906 * @retval None
AnnaBridge 167:e84263d55307 2907 */
AnnaBridge 167:e84263d55307 2908 static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma)
AnnaBridge 167:e84263d55307 2909 {
AnnaBridge 167:e84263d55307 2910 SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
AnnaBridge 167:e84263d55307 2911 hspi->RxXferCount = 0U;
AnnaBridge 167:e84263d55307 2912 hspi->TxXferCount = 0U;
AnnaBridge 167:e84263d55307 2913
AnnaBridge 167:e84263d55307 2914 HAL_SPI_ErrorCallback(hspi);
AnnaBridge 167:e84263d55307 2915 }
AnnaBridge 167:e84263d55307 2916
AnnaBridge 167:e84263d55307 2917 /**
AnnaBridge 167:e84263d55307 2918 * @brief DMA SPI Tx communication abort callback, when initiated by user
AnnaBridge 167:e84263d55307 2919 * (To be called at end of DMA Tx Abort procedure following user abort request).
AnnaBridge 167:e84263d55307 2920 * @note When this callback is executed, User Abort complete call back is called only if no
AnnaBridge 167:e84263d55307 2921 * Abort still ongoing for Rx DMA Handle.
AnnaBridge 167:e84263d55307 2922 * @param hdma DMA handle.
AnnaBridge 167:e84263d55307 2923 * @retval None
AnnaBridge 167:e84263d55307 2924 */
AnnaBridge 167:e84263d55307 2925 static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
AnnaBridge 167:e84263d55307 2926 {
AnnaBridge 167:e84263d55307 2927 SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
AnnaBridge 167:e84263d55307 2928
AnnaBridge 167:e84263d55307 2929 hspi->hdmatx->XferAbortCallback = NULL;
AnnaBridge 167:e84263d55307 2930
AnnaBridge 167:e84263d55307 2931 /* Disable Tx DMA Request */
AnnaBridge 167:e84263d55307 2932 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
AnnaBridge 167:e84263d55307 2933
AnnaBridge 167:e84263d55307 2934 if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
AnnaBridge 167:e84263d55307 2935 {
AnnaBridge 167:e84263d55307 2936 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
AnnaBridge 167:e84263d55307 2937 }
AnnaBridge 167:e84263d55307 2938
AnnaBridge 167:e84263d55307 2939 /* Disable SPI Peripheral */
AnnaBridge 167:e84263d55307 2940 __HAL_SPI_DISABLE(hspi);
AnnaBridge 167:e84263d55307 2941
AnnaBridge 167:e84263d55307 2942 /* Empty the FRLVL fifo */
AnnaBridge 167:e84263d55307 2943 if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
AnnaBridge 167:e84263d55307 2944 {
AnnaBridge 167:e84263d55307 2945 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
AnnaBridge 167:e84263d55307 2946 }
AnnaBridge 167:e84263d55307 2947
AnnaBridge 167:e84263d55307 2948 /* Check if an Abort process is still ongoing */
AnnaBridge 167:e84263d55307 2949 if (hspi->hdmarx != NULL)
AnnaBridge 167:e84263d55307 2950 {
AnnaBridge 167:e84263d55307 2951 if (hspi->hdmarx->XferAbortCallback != NULL)
AnnaBridge 167:e84263d55307 2952 {
AnnaBridge 167:e84263d55307 2953 return;
AnnaBridge 167:e84263d55307 2954 }
AnnaBridge 167:e84263d55307 2955 }
AnnaBridge 167:e84263d55307 2956
AnnaBridge 167:e84263d55307 2957 /* No Abort process still ongoing : All DMA Stream/Channel are aborted, call user Abort Complete callback */
AnnaBridge 167:e84263d55307 2958 hspi->RxXferCount = 0U;
AnnaBridge 167:e84263d55307 2959 hspi->TxXferCount = 0U;
AnnaBridge 167:e84263d55307 2960
AnnaBridge 167:e84263d55307 2961 /* Check no error during Abort procedure */
AnnaBridge 167:e84263d55307 2962 if (hspi->ErrorCode != HAL_SPI_ERROR_ABORT)
AnnaBridge 167:e84263d55307 2963 {
AnnaBridge 167:e84263d55307 2964 /* Reset errorCode */
AnnaBridge 167:e84263d55307 2965 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
AnnaBridge 167:e84263d55307 2966 }
AnnaBridge 167:e84263d55307 2967
AnnaBridge 167:e84263d55307 2968 /* Clear the Error flags in the SR register */
AnnaBridge 167:e84263d55307 2969 __HAL_SPI_CLEAR_OVRFLAG(hspi);
AnnaBridge 167:e84263d55307 2970 __HAL_SPI_CLEAR_FREFLAG(hspi);
AnnaBridge 167:e84263d55307 2971
AnnaBridge 167:e84263d55307 2972 /* Restore hspi->State to Ready */
AnnaBridge 167:e84263d55307 2973 hspi->State = HAL_SPI_STATE_READY;
AnnaBridge 167:e84263d55307 2974
AnnaBridge 167:e84263d55307 2975 /* Call user Abort complete callback */
AnnaBridge 167:e84263d55307 2976 HAL_SPI_AbortCpltCallback(hspi);
AnnaBridge 167:e84263d55307 2977 }
AnnaBridge 167:e84263d55307 2978
AnnaBridge 167:e84263d55307 2979 /**
AnnaBridge 167:e84263d55307 2980 * @brief DMA SPI Rx communication abort callback, when initiated by user
AnnaBridge 167:e84263d55307 2981 * (To be called at end of DMA Rx Abort procedure following user abort request).
AnnaBridge 167:e84263d55307 2982 * @note When this callback is executed, User Abort complete call back is called only if no
AnnaBridge 167:e84263d55307 2983 * Abort still ongoing for Tx DMA Handle.
AnnaBridge 167:e84263d55307 2984 * @param hdma DMA handle.
AnnaBridge 167:e84263d55307 2985 * @retval None
AnnaBridge 167:e84263d55307 2986 */
AnnaBridge 167:e84263d55307 2987 static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
AnnaBridge 167:e84263d55307 2988 {
AnnaBridge 167:e84263d55307 2989 SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
AnnaBridge 167:e84263d55307 2990
AnnaBridge 167:e84263d55307 2991 /* Disable SPI Peripheral */
AnnaBridge 167:e84263d55307 2992 __HAL_SPI_DISABLE(hspi);
AnnaBridge 167:e84263d55307 2993
AnnaBridge 167:e84263d55307 2994 hspi->hdmarx->XferAbortCallback = NULL;
AnnaBridge 167:e84263d55307 2995
AnnaBridge 167:e84263d55307 2996 /* Disable Rx DMA Request */
AnnaBridge 167:e84263d55307 2997 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
AnnaBridge 167:e84263d55307 2998
AnnaBridge 167:e84263d55307 2999 /* Control the BSY flag */
AnnaBridge 167:e84263d55307 3000 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
AnnaBridge 167:e84263d55307 3001 {
AnnaBridge 167:e84263d55307 3002 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
AnnaBridge 167:e84263d55307 3003 }
AnnaBridge 167:e84263d55307 3004
AnnaBridge 167:e84263d55307 3005 /* Empty the FRLVL fifo */
AnnaBridge 167:e84263d55307 3006 if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
AnnaBridge 167:e84263d55307 3007 {
AnnaBridge 167:e84263d55307 3008 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
AnnaBridge 167:e84263d55307 3009 }
AnnaBridge 167:e84263d55307 3010
AnnaBridge 167:e84263d55307 3011 /* Check if an Abort process is still ongoing */
AnnaBridge 167:e84263d55307 3012 if (hspi->hdmatx != NULL)
AnnaBridge 167:e84263d55307 3013 {
AnnaBridge 167:e84263d55307 3014 if (hspi->hdmatx->XferAbortCallback != NULL)
AnnaBridge 167:e84263d55307 3015 {
AnnaBridge 167:e84263d55307 3016 return;
AnnaBridge 167:e84263d55307 3017 }
AnnaBridge 167:e84263d55307 3018 }
AnnaBridge 167:e84263d55307 3019
AnnaBridge 167:e84263d55307 3020 /* No Abort process still ongoing : All DMA Stream/Channel are aborted, call user Abort Complete callback */
AnnaBridge 167:e84263d55307 3021 hspi->RxXferCount = 0U;
AnnaBridge 167:e84263d55307 3022 hspi->TxXferCount = 0U;
AnnaBridge 167:e84263d55307 3023
AnnaBridge 167:e84263d55307 3024 /* Check no error during Abort procedure */
AnnaBridge 167:e84263d55307 3025 if (hspi->ErrorCode != HAL_SPI_ERROR_ABORT)
AnnaBridge 167:e84263d55307 3026 {
AnnaBridge 167:e84263d55307 3027 /* Reset errorCode */
AnnaBridge 167:e84263d55307 3028 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
AnnaBridge 167:e84263d55307 3029 }
AnnaBridge 167:e84263d55307 3030
AnnaBridge 167:e84263d55307 3031 /* Clear the Error flags in the SR register */
AnnaBridge 167:e84263d55307 3032 __HAL_SPI_CLEAR_OVRFLAG(hspi);
AnnaBridge 167:e84263d55307 3033 __HAL_SPI_CLEAR_FREFLAG(hspi);
AnnaBridge 167:e84263d55307 3034
AnnaBridge 167:e84263d55307 3035 /* Restore hspi->State to Ready */
AnnaBridge 167:e84263d55307 3036 hspi->State = HAL_SPI_STATE_READY;
AnnaBridge 167:e84263d55307 3037
AnnaBridge 167:e84263d55307 3038 /* Call user Abort complete callback */
AnnaBridge 167:e84263d55307 3039 HAL_SPI_AbortCpltCallback(hspi);
AnnaBridge 167:e84263d55307 3040 }
AnnaBridge 167:e84263d55307 3041
AnnaBridge 167:e84263d55307 3042 /**
<> 144:ef7eb2e8f9f7 3043 * @brief Rx 8-bit handler for Transmit and Receive in Interrupt mode.
<> 144:ef7eb2e8f9f7 3044 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 3045 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 3046 * @retval None
<> 144:ef7eb2e8f9f7 3047 */
<> 144:ef7eb2e8f9f7 3048 static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 3049 {
<> 144:ef7eb2e8f9f7 3050 /* Receive data in packing mode */
AnnaBridge 167:e84263d55307 3051 if (hspi->RxXferCount > 1U)
<> 144:ef7eb2e8f9f7 3052 {
AnnaBridge 167:e84263d55307 3053 *((uint16_t *)hspi->pRxBuffPtr) = hspi->Instance->DR;
<> 144:ef7eb2e8f9f7 3054 hspi->pRxBuffPtr += sizeof(uint16_t);
AnnaBridge 167:e84263d55307 3055 hspi->RxXferCount -= 2U;
AnnaBridge 167:e84263d55307 3056 if (hspi->RxXferCount == 1U)
<> 144:ef7eb2e8f9f7 3057 {
<> 144:ef7eb2e8f9f7 3058 /* set fiforxthresold according the reception data length: 8bit */
<> 144:ef7eb2e8f9f7 3059 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
<> 144:ef7eb2e8f9f7 3060 }
<> 144:ef7eb2e8f9f7 3061 }
<> 144:ef7eb2e8f9f7 3062 /* Receive data in 8 Bit mode */
<> 144:ef7eb2e8f9f7 3063 else
<> 144:ef7eb2e8f9f7 3064 {
<> 144:ef7eb2e8f9f7 3065 *hspi->pRxBuffPtr++ = *((__IO uint8_t *)&hspi->Instance->DR);
<> 144:ef7eb2e8f9f7 3066 hspi->RxXferCount--;
<> 144:ef7eb2e8f9f7 3067 }
<> 144:ef7eb2e8f9f7 3068
<> 144:ef7eb2e8f9f7 3069 /* check end of the reception */
AnnaBridge 167:e84263d55307 3070 if (hspi->RxXferCount == 0U)
<> 144:ef7eb2e8f9f7 3071 {
AnnaBridge 167:e84263d55307 3072 #if (USE_SPI_CRC != 0U)
AnnaBridge 167:e84263d55307 3073 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<> 144:ef7eb2e8f9f7 3074 {
<> 144:ef7eb2e8f9f7 3075 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
<> 144:ef7eb2e8f9f7 3076 hspi->RxISR = SPI_2linesRxISR_8BITCRC;
<> 144:ef7eb2e8f9f7 3077 return;
<> 144:ef7eb2e8f9f7 3078 }
AnnaBridge 167:e84263d55307 3079 #endif /* USE_SPI_CRC */
AnnaBridge 167:e84263d55307 3080
AnnaBridge 167:e84263d55307 3081 /* Disable RXNE and ERR interrupt */
AnnaBridge 167:e84263d55307 3082 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
AnnaBridge 167:e84263d55307 3083
AnnaBridge 167:e84263d55307 3084 if (hspi->TxXferCount == 0U)
<> 144:ef7eb2e8f9f7 3085 {
<> 144:ef7eb2e8f9f7 3086 SPI_CloseRxTx_ISR(hspi);
<> 144:ef7eb2e8f9f7 3087 }
<> 144:ef7eb2e8f9f7 3088 }
<> 144:ef7eb2e8f9f7 3089 }
<> 144:ef7eb2e8f9f7 3090
AnnaBridge 167:e84263d55307 3091 #if (USE_SPI_CRC != 0U)
<> 144:ef7eb2e8f9f7 3092 /**
<> 144:ef7eb2e8f9f7 3093 * @brief Rx 8-bit handler for Transmit and Receive in Interrupt mode.
<> 144:ef7eb2e8f9f7 3094 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 3095 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 3096 * @retval None
<> 144:ef7eb2e8f9f7 3097 */
<> 144:ef7eb2e8f9f7 3098 static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 3099 {
AnnaBridge 167:e84263d55307 3100 __IO uint8_t tmpreg = 0U;
AnnaBridge 167:e84263d55307 3101
AnnaBridge 167:e84263d55307 3102 /* Read data register to flush CRC */
AnnaBridge 167:e84263d55307 3103 tmpreg = *((__IO uint8_t *)&hspi->Instance->DR);
AnnaBridge 167:e84263d55307 3104
AnnaBridge 167:e84263d55307 3105 /* To avoid GCC warning */
AnnaBridge 167:e84263d55307 3106 UNUSED(tmpreg);
<> 144:ef7eb2e8f9f7 3107
<> 144:ef7eb2e8f9f7 3108 hspi->CRCSize--;
<> 144:ef7eb2e8f9f7 3109
<> 144:ef7eb2e8f9f7 3110 /* check end of the reception */
AnnaBridge 167:e84263d55307 3111 if (hspi->CRCSize == 0U)
<> 144:ef7eb2e8f9f7 3112 {
AnnaBridge 167:e84263d55307 3113 /* Disable RXNE and ERR interrupt */
AnnaBridge 167:e84263d55307 3114 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
AnnaBridge 167:e84263d55307 3115
AnnaBridge 167:e84263d55307 3116 if (hspi->TxXferCount == 0U)
<> 144:ef7eb2e8f9f7 3117 {
<> 144:ef7eb2e8f9f7 3118 SPI_CloseRxTx_ISR(hspi);
<> 144:ef7eb2e8f9f7 3119 }
<> 144:ef7eb2e8f9f7 3120 }
<> 144:ef7eb2e8f9f7 3121 }
AnnaBridge 167:e84263d55307 3122 #endif /* USE_SPI_CRC */
<> 144:ef7eb2e8f9f7 3123
<> 144:ef7eb2e8f9f7 3124 /**
<> 144:ef7eb2e8f9f7 3125 * @brief Tx 8-bit handler for Transmit and Receive in Interrupt mode.
<> 144:ef7eb2e8f9f7 3126 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 3127 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 3128 * @retval None
<> 144:ef7eb2e8f9f7 3129 */
<> 144:ef7eb2e8f9f7 3130 static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 3131 {
<> 144:ef7eb2e8f9f7 3132 /* Transmit data in packing Bit mode */
AnnaBridge 167:e84263d55307 3133 if (hspi->TxXferCount >= 2U)
<> 144:ef7eb2e8f9f7 3134 {
<> 144:ef7eb2e8f9f7 3135 hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
<> 144:ef7eb2e8f9f7 3136 hspi->pTxBuffPtr += sizeof(uint16_t);
AnnaBridge 167:e84263d55307 3137 hspi->TxXferCount -= 2U;
<> 144:ef7eb2e8f9f7 3138 }
<> 144:ef7eb2e8f9f7 3139 /* Transmit data in 8 Bit mode */
<> 144:ef7eb2e8f9f7 3140 else
<> 144:ef7eb2e8f9f7 3141 {
<> 144:ef7eb2e8f9f7 3142 *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr++);
<> 144:ef7eb2e8f9f7 3143 hspi->TxXferCount--;
<> 144:ef7eb2e8f9f7 3144 }
<> 144:ef7eb2e8f9f7 3145
<> 144:ef7eb2e8f9f7 3146 /* check the end of the transmission */
AnnaBridge 167:e84263d55307 3147 if (hspi->TxXferCount == 0U)
<> 144:ef7eb2e8f9f7 3148 {
AnnaBridge 167:e84263d55307 3149 #if (USE_SPI_CRC != 0U)
AnnaBridge 167:e84263d55307 3150 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<> 144:ef7eb2e8f9f7 3151 {
AnnaBridge 167:e84263d55307 3152 /* Set CRC Next Bit to send CRC */
AnnaBridge 167:e84263d55307 3153 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
AnnaBridge 167:e84263d55307 3154 /* Disable TXE interrupt */
AnnaBridge 167:e84263d55307 3155 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
AnnaBridge 167:e84263d55307 3156 return;
<> 144:ef7eb2e8f9f7 3157 }
AnnaBridge 167:e84263d55307 3158 #endif /* USE_SPI_CRC */
AnnaBridge 167:e84263d55307 3159
<> 144:ef7eb2e8f9f7 3160 /* Disable TXE interrupt */
<> 144:ef7eb2e8f9f7 3161 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
<> 144:ef7eb2e8f9f7 3162
AnnaBridge 167:e84263d55307 3163 if (hspi->RxXferCount == 0U)
<> 144:ef7eb2e8f9f7 3164 {
<> 144:ef7eb2e8f9f7 3165 SPI_CloseRxTx_ISR(hspi);
<> 144:ef7eb2e8f9f7 3166 }
<> 144:ef7eb2e8f9f7 3167 }
<> 144:ef7eb2e8f9f7 3168 }
<> 144:ef7eb2e8f9f7 3169
<> 144:ef7eb2e8f9f7 3170 /**
<> 144:ef7eb2e8f9f7 3171 * @brief Rx 16-bit handler for Transmit and Receive in Interrupt mode.
<> 144:ef7eb2e8f9f7 3172 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 3173 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 3174 * @retval None
<> 144:ef7eb2e8f9f7 3175 */
<> 144:ef7eb2e8f9f7 3176 static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 3177 {
<> 144:ef7eb2e8f9f7 3178 /* Receive data in 16 Bit mode */
AnnaBridge 167:e84263d55307 3179 *((uint16_t *)hspi->pRxBuffPtr) = hspi->Instance->DR;
<> 144:ef7eb2e8f9f7 3180 hspi->pRxBuffPtr += sizeof(uint16_t);
<> 144:ef7eb2e8f9f7 3181 hspi->RxXferCount--;
<> 144:ef7eb2e8f9f7 3182
AnnaBridge 167:e84263d55307 3183 if (hspi->RxXferCount == 0U)
<> 144:ef7eb2e8f9f7 3184 {
AnnaBridge 167:e84263d55307 3185 #if (USE_SPI_CRC != 0U)
AnnaBridge 167:e84263d55307 3186 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<> 144:ef7eb2e8f9f7 3187 {
<> 144:ef7eb2e8f9f7 3188 hspi->RxISR = SPI_2linesRxISR_16BITCRC;
<> 144:ef7eb2e8f9f7 3189 return;
<> 144:ef7eb2e8f9f7 3190 }
AnnaBridge 167:e84263d55307 3191 #endif /* USE_SPI_CRC */
<> 144:ef7eb2e8f9f7 3192
<> 144:ef7eb2e8f9f7 3193 /* Disable RXNE interrupt */
<> 144:ef7eb2e8f9f7 3194 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
<> 144:ef7eb2e8f9f7 3195
AnnaBridge 167:e84263d55307 3196 if (hspi->TxXferCount == 0U)
<> 144:ef7eb2e8f9f7 3197 {
<> 144:ef7eb2e8f9f7 3198 SPI_CloseRxTx_ISR(hspi);
<> 144:ef7eb2e8f9f7 3199 }
<> 144:ef7eb2e8f9f7 3200 }
<> 144:ef7eb2e8f9f7 3201 }
<> 144:ef7eb2e8f9f7 3202
AnnaBridge 167:e84263d55307 3203 #if (USE_SPI_CRC != 0U)
<> 144:ef7eb2e8f9f7 3204 /**
<> 144:ef7eb2e8f9f7 3205 * @brief Manage the CRC 16-bit receive for Transmit and Receive in Interrupt mode.
<> 144:ef7eb2e8f9f7 3206 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 3207 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 3208 * @retval None
<> 144:ef7eb2e8f9f7 3209 */
<> 144:ef7eb2e8f9f7 3210 static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 3211 {
<> 144:ef7eb2e8f9f7 3212 /* Receive data in 16 Bit mode */
AnnaBridge 167:e84263d55307 3213 __IO uint16_t tmpreg = 0U;
AnnaBridge 167:e84263d55307 3214
AnnaBridge 167:e84263d55307 3215 /* Read data register to flush CRC */
AnnaBridge 167:e84263d55307 3216 tmpreg = hspi->Instance->DR;
AnnaBridge 167:e84263d55307 3217
AnnaBridge 167:e84263d55307 3218 /* To avoid GCC warning */
AnnaBridge 167:e84263d55307 3219 UNUSED(tmpreg);
<> 144:ef7eb2e8f9f7 3220
<> 144:ef7eb2e8f9f7 3221 /* Disable RXNE interrupt */
<> 144:ef7eb2e8f9f7 3222 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
<> 144:ef7eb2e8f9f7 3223
<> 144:ef7eb2e8f9f7 3224 SPI_CloseRxTx_ISR(hspi);
<> 144:ef7eb2e8f9f7 3225 }
AnnaBridge 167:e84263d55307 3226 #endif /* USE_SPI_CRC */
<> 144:ef7eb2e8f9f7 3227
<> 144:ef7eb2e8f9f7 3228 /**
<> 144:ef7eb2e8f9f7 3229 * @brief Tx 16-bit handler for Transmit and Receive in Interrupt mode.
<> 144:ef7eb2e8f9f7 3230 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 3231 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 3232 * @retval None
<> 144:ef7eb2e8f9f7 3233 */
<> 144:ef7eb2e8f9f7 3234 static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 3235 {
<> 144:ef7eb2e8f9f7 3236 /* Transmit data in 16 Bit mode */
<> 144:ef7eb2e8f9f7 3237 hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
<> 144:ef7eb2e8f9f7 3238 hspi->pTxBuffPtr += sizeof(uint16_t);
<> 144:ef7eb2e8f9f7 3239 hspi->TxXferCount--;
<> 144:ef7eb2e8f9f7 3240
<> 144:ef7eb2e8f9f7 3241 /* Enable CRC Transmission */
AnnaBridge 167:e84263d55307 3242 if (hspi->TxXferCount == 0U)
<> 144:ef7eb2e8f9f7 3243 {
AnnaBridge 167:e84263d55307 3244 #if (USE_SPI_CRC != 0U)
AnnaBridge 167:e84263d55307 3245 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<> 144:ef7eb2e8f9f7 3246 {
AnnaBridge 167:e84263d55307 3247 /* Set CRC Next Bit to send CRC */
AnnaBridge 167:e84263d55307 3248 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
AnnaBridge 167:e84263d55307 3249 /* Disable TXE interrupt */
AnnaBridge 167:e84263d55307 3250 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
AnnaBridge 167:e84263d55307 3251 return;
<> 144:ef7eb2e8f9f7 3252 }
AnnaBridge 167:e84263d55307 3253 #endif /* USE_SPI_CRC */
AnnaBridge 167:e84263d55307 3254
<> 144:ef7eb2e8f9f7 3255 /* Disable TXE interrupt */
<> 144:ef7eb2e8f9f7 3256 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
<> 144:ef7eb2e8f9f7 3257
AnnaBridge 167:e84263d55307 3258 if (hspi->RxXferCount == 0U)
<> 144:ef7eb2e8f9f7 3259 {
<> 144:ef7eb2e8f9f7 3260 SPI_CloseRxTx_ISR(hspi);
<> 144:ef7eb2e8f9f7 3261 }
<> 144:ef7eb2e8f9f7 3262 }
<> 144:ef7eb2e8f9f7 3263 }
<> 144:ef7eb2e8f9f7 3264
AnnaBridge 167:e84263d55307 3265 #if (USE_SPI_CRC != 0U)
<> 144:ef7eb2e8f9f7 3266 /**
<> 144:ef7eb2e8f9f7 3267 * @brief Manage the CRC 8-bit receive in Interrupt context.
<> 144:ef7eb2e8f9f7 3268 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 3269 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 3270 * @retval None
<> 144:ef7eb2e8f9f7 3271 */
<> 144:ef7eb2e8f9f7 3272 static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 3273 {
AnnaBridge 167:e84263d55307 3274 __IO uint8_t tmpreg = 0U;
AnnaBridge 167:e84263d55307 3275
AnnaBridge 167:e84263d55307 3276 /* Read data register to flush CRC */
AnnaBridge 167:e84263d55307 3277 tmpreg = *((__IO uint8_t *)&hspi->Instance->DR);
AnnaBridge 167:e84263d55307 3278
AnnaBridge 167:e84263d55307 3279 /* To avoid GCC warning */
AnnaBridge 167:e84263d55307 3280 UNUSED(tmpreg);
<> 144:ef7eb2e8f9f7 3281
<> 144:ef7eb2e8f9f7 3282 hspi->CRCSize--;
<> 144:ef7eb2e8f9f7 3283
AnnaBridge 167:e84263d55307 3284 if (hspi->CRCSize == 0U)
<> 144:ef7eb2e8f9f7 3285 {
<> 144:ef7eb2e8f9f7 3286 SPI_CloseRx_ISR(hspi);
<> 144:ef7eb2e8f9f7 3287 }
<> 144:ef7eb2e8f9f7 3288 }
AnnaBridge 167:e84263d55307 3289 #endif /* USE_SPI_CRC */
<> 144:ef7eb2e8f9f7 3290
<> 144:ef7eb2e8f9f7 3291 /**
<> 144:ef7eb2e8f9f7 3292 * @brief Manage the receive 8-bit in Interrupt context.
<> 144:ef7eb2e8f9f7 3293 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 3294 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 3295 * @retval None
<> 144:ef7eb2e8f9f7 3296 */
<> 144:ef7eb2e8f9f7 3297 static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 3298 {
<> 144:ef7eb2e8f9f7 3299 *hspi->pRxBuffPtr++ = (*(__IO uint8_t *)&hspi->Instance->DR);
<> 144:ef7eb2e8f9f7 3300 hspi->RxXferCount--;
<> 144:ef7eb2e8f9f7 3301
AnnaBridge 167:e84263d55307 3302 #if (USE_SPI_CRC != 0U)
<> 144:ef7eb2e8f9f7 3303 /* Enable CRC Transmission */
AnnaBridge 167:e84263d55307 3304 if ((hspi->RxXferCount == 1U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
<> 144:ef7eb2e8f9f7 3305 {
AnnaBridge 167:e84263d55307 3306 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
<> 144:ef7eb2e8f9f7 3307 }
AnnaBridge 167:e84263d55307 3308 #endif /* USE_SPI_CRC */
AnnaBridge 167:e84263d55307 3309
AnnaBridge 167:e84263d55307 3310 if (hspi->RxXferCount == 0U)
<> 144:ef7eb2e8f9f7 3311 {
AnnaBridge 167:e84263d55307 3312 #if (USE_SPI_CRC != 0U)
AnnaBridge 167:e84263d55307 3313 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<> 144:ef7eb2e8f9f7 3314 {
<> 144:ef7eb2e8f9f7 3315 hspi->RxISR = SPI_RxISR_8BITCRC;
<> 144:ef7eb2e8f9f7 3316 return;
<> 144:ef7eb2e8f9f7 3317 }
AnnaBridge 167:e84263d55307 3318 #endif /* USE_SPI_CRC */
<> 144:ef7eb2e8f9f7 3319 SPI_CloseRx_ISR(hspi);
<> 144:ef7eb2e8f9f7 3320 }
<> 144:ef7eb2e8f9f7 3321 }
<> 144:ef7eb2e8f9f7 3322
AnnaBridge 167:e84263d55307 3323 #if (USE_SPI_CRC != 0U)
<> 144:ef7eb2e8f9f7 3324 /**
<> 144:ef7eb2e8f9f7 3325 * @brief Manage the CRC 16-bit receive in Interrupt context.
<> 144:ef7eb2e8f9f7 3326 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 3327 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 3328 * @retval None
<> 144:ef7eb2e8f9f7 3329 */
<> 144:ef7eb2e8f9f7 3330 static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 3331 {
AnnaBridge 167:e84263d55307 3332 __IO uint16_t tmpreg = 0U;
AnnaBridge 167:e84263d55307 3333
AnnaBridge 167:e84263d55307 3334 /* Read data register to flush CRC */
<> 144:ef7eb2e8f9f7 3335 tmpreg = hspi->Instance->DR;
AnnaBridge 167:e84263d55307 3336
AnnaBridge 167:e84263d55307 3337 /* To avoid GCC warning */
AnnaBridge 167:e84263d55307 3338 UNUSED(tmpreg);
<> 144:ef7eb2e8f9f7 3339
<> 144:ef7eb2e8f9f7 3340 /* Disable RXNE and ERR interrupt */
<> 144:ef7eb2e8f9f7 3341 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
<> 144:ef7eb2e8f9f7 3342
<> 144:ef7eb2e8f9f7 3343 SPI_CloseRx_ISR(hspi);
<> 144:ef7eb2e8f9f7 3344 }
AnnaBridge 167:e84263d55307 3345 #endif /* USE_SPI_CRC */
<> 144:ef7eb2e8f9f7 3346
<> 144:ef7eb2e8f9f7 3347 /**
<> 144:ef7eb2e8f9f7 3348 * @brief Manage the 16-bit receive in Interrupt context.
<> 144:ef7eb2e8f9f7 3349 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 3350 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 3351 * @retval None
<> 144:ef7eb2e8f9f7 3352 */
<> 144:ef7eb2e8f9f7 3353 static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 3354 {
<> 144:ef7eb2e8f9f7 3355 *((uint16_t *)hspi->pRxBuffPtr) = hspi->Instance->DR;
<> 144:ef7eb2e8f9f7 3356 hspi->pRxBuffPtr += sizeof(uint16_t);
<> 144:ef7eb2e8f9f7 3357 hspi->RxXferCount--;
<> 144:ef7eb2e8f9f7 3358
AnnaBridge 167:e84263d55307 3359 #if (USE_SPI_CRC != 0U)
<> 144:ef7eb2e8f9f7 3360 /* Enable CRC Transmission */
AnnaBridge 167:e84263d55307 3361 if ((hspi->RxXferCount == 1U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
<> 144:ef7eb2e8f9f7 3362 {
AnnaBridge 167:e84263d55307 3363 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
<> 144:ef7eb2e8f9f7 3364 }
AnnaBridge 167:e84263d55307 3365 #endif /* USE_SPI_CRC */
AnnaBridge 167:e84263d55307 3366
AnnaBridge 167:e84263d55307 3367 if (hspi->RxXferCount == 0U)
<> 144:ef7eb2e8f9f7 3368 {
AnnaBridge 167:e84263d55307 3369 #if (USE_SPI_CRC != 0U)
AnnaBridge 167:e84263d55307 3370 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<> 144:ef7eb2e8f9f7 3371 {
<> 144:ef7eb2e8f9f7 3372 hspi->RxISR = SPI_RxISR_16BITCRC;
<> 144:ef7eb2e8f9f7 3373 return;
<> 144:ef7eb2e8f9f7 3374 }
AnnaBridge 167:e84263d55307 3375 #endif /* USE_SPI_CRC */
<> 144:ef7eb2e8f9f7 3376 SPI_CloseRx_ISR(hspi);
<> 144:ef7eb2e8f9f7 3377 }
<> 144:ef7eb2e8f9f7 3378 }
<> 144:ef7eb2e8f9f7 3379
<> 144:ef7eb2e8f9f7 3380 /**
<> 144:ef7eb2e8f9f7 3381 * @brief Handle the data 8-bit transmit in Interrupt mode.
<> 144:ef7eb2e8f9f7 3382 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 3383 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 3384 * @retval None
<> 144:ef7eb2e8f9f7 3385 */
<> 144:ef7eb2e8f9f7 3386 static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 3387 {
<> 144:ef7eb2e8f9f7 3388 *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr++);
<> 144:ef7eb2e8f9f7 3389 hspi->TxXferCount--;
<> 144:ef7eb2e8f9f7 3390
AnnaBridge 167:e84263d55307 3391 if (hspi->TxXferCount == 0U)
<> 144:ef7eb2e8f9f7 3392 {
AnnaBridge 167:e84263d55307 3393 #if (USE_SPI_CRC != 0U)
AnnaBridge 167:e84263d55307 3394 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<> 144:ef7eb2e8f9f7 3395 {
<> 144:ef7eb2e8f9f7 3396 /* Enable CRC Transmission */
AnnaBridge 167:e84263d55307 3397 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
<> 144:ef7eb2e8f9f7 3398 }
AnnaBridge 167:e84263d55307 3399 #endif /* USE_SPI_CRC */
<> 144:ef7eb2e8f9f7 3400 SPI_CloseTx_ISR(hspi);
<> 144:ef7eb2e8f9f7 3401 }
<> 144:ef7eb2e8f9f7 3402 }
<> 144:ef7eb2e8f9f7 3403
<> 144:ef7eb2e8f9f7 3404 /**
<> 144:ef7eb2e8f9f7 3405 * @brief Handle the data 16-bit transmit in Interrupt mode.
<> 144:ef7eb2e8f9f7 3406 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 3407 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 3408 * @retval None
<> 144:ef7eb2e8f9f7 3409 */
<> 144:ef7eb2e8f9f7 3410 static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 3411 {
<> 144:ef7eb2e8f9f7 3412 /* Transmit data in 16 Bit mode */
<> 144:ef7eb2e8f9f7 3413 hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
<> 144:ef7eb2e8f9f7 3414 hspi->pTxBuffPtr += sizeof(uint16_t);
<> 144:ef7eb2e8f9f7 3415 hspi->TxXferCount--;
<> 144:ef7eb2e8f9f7 3416
AnnaBridge 167:e84263d55307 3417 if (hspi->TxXferCount == 0U)
<> 144:ef7eb2e8f9f7 3418 {
AnnaBridge 167:e84263d55307 3419 #if (USE_SPI_CRC != 0U)
AnnaBridge 167:e84263d55307 3420 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<> 144:ef7eb2e8f9f7 3421 {
<> 144:ef7eb2e8f9f7 3422 /* Enable CRC Transmission */
AnnaBridge 167:e84263d55307 3423 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
<> 144:ef7eb2e8f9f7 3424 }
AnnaBridge 167:e84263d55307 3425 #endif /* USE_SPI_CRC */
<> 144:ef7eb2e8f9f7 3426 SPI_CloseTx_ISR(hspi);
<> 144:ef7eb2e8f9f7 3427 }
<> 144:ef7eb2e8f9f7 3428 }
<> 144:ef7eb2e8f9f7 3429
<> 144:ef7eb2e8f9f7 3430 /**
<> 144:ef7eb2e8f9f7 3431 * @brief Handle SPI Communication Timeout.
AnnaBridge 167:e84263d55307 3432 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
AnnaBridge 167:e84263d55307 3433 * the configuration information for SPI module.
AnnaBridge 167:e84263d55307 3434 * @param Flag: SPI flag to check
AnnaBridge 167:e84263d55307 3435 * @param State: flag state to check
AnnaBridge 167:e84263d55307 3436 * @param Timeout: Timeout duration
AnnaBridge 167:e84263d55307 3437 * @param Tickstart: tick start value
<> 144:ef7eb2e8f9f7 3438 * @retval HAL status
<> 144:ef7eb2e8f9f7 3439 */
AnnaBridge 167:e84263d55307 3440 static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, uint32_t State,
AnnaBridge 167:e84263d55307 3441 uint32_t Timeout, uint32_t Tickstart)
<> 144:ef7eb2e8f9f7 3442 {
AnnaBridge 167:e84263d55307 3443 while ((__HAL_SPI_GET_FLAG(hspi, Flag) ? SET : RESET) != State)
<> 144:ef7eb2e8f9f7 3444 {
AnnaBridge 167:e84263d55307 3445 if (Timeout != HAL_MAX_DELAY)
<> 144:ef7eb2e8f9f7 3446 {
AnnaBridge 167:e84263d55307 3447 if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) >= Timeout))
<> 144:ef7eb2e8f9f7 3448 {
<> 144:ef7eb2e8f9f7 3449 /* Disable the SPI and reset the CRC: the CRC value should be cleared
<> 144:ef7eb2e8f9f7 3450 on both master and slave sides in order to resynchronize the master
<> 144:ef7eb2e8f9f7 3451 and slave for their respective CRC calculation */
<> 144:ef7eb2e8f9f7 3452
<> 144:ef7eb2e8f9f7 3453 /* Disable TXE, RXNE and ERR interrupts for the interrupt process */
<> 144:ef7eb2e8f9f7 3454 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
<> 144:ef7eb2e8f9f7 3455
AnnaBridge 167:e84263d55307 3456 if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
AnnaBridge 167:e84263d55307 3457 || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
<> 144:ef7eb2e8f9f7 3458 {
<> 144:ef7eb2e8f9f7 3459 /* Disable SPI peripheral */
<> 144:ef7eb2e8f9f7 3460 __HAL_SPI_DISABLE(hspi);
<> 144:ef7eb2e8f9f7 3461 }
<> 144:ef7eb2e8f9f7 3462
<> 144:ef7eb2e8f9f7 3463 /* Reset CRC Calculation */
AnnaBridge 167:e84263d55307 3464 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<> 144:ef7eb2e8f9f7 3465 {
<> 144:ef7eb2e8f9f7 3466 SPI_RESET_CRC(hspi);
<> 144:ef7eb2e8f9f7 3467 }
<> 144:ef7eb2e8f9f7 3468
<> 144:ef7eb2e8f9f7 3469 hspi->State = HAL_SPI_STATE_READY;
<> 144:ef7eb2e8f9f7 3470
<> 144:ef7eb2e8f9f7 3471 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 3472 __HAL_UNLOCK(hspi);
<> 144:ef7eb2e8f9f7 3473
<> 144:ef7eb2e8f9f7 3474 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 3475 }
<> 144:ef7eb2e8f9f7 3476 }
<> 144:ef7eb2e8f9f7 3477 }
<> 144:ef7eb2e8f9f7 3478
<> 144:ef7eb2e8f9f7 3479 return HAL_OK;
<> 144:ef7eb2e8f9f7 3480 }
<> 144:ef7eb2e8f9f7 3481
<> 144:ef7eb2e8f9f7 3482 /**
AnnaBridge 167:e84263d55307 3483 * @brief Handle SPI FIFO Communication Timeout.
AnnaBridge 167:e84263d55307 3484 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
AnnaBridge 167:e84263d55307 3485 * the configuration information for SPI module.
AnnaBridge 167:e84263d55307 3486 * @param Fifo: Fifo to check
AnnaBridge 167:e84263d55307 3487 * @param State: Fifo state to check
AnnaBridge 167:e84263d55307 3488 * @param Timeout: Timeout duration
AnnaBridge 167:e84263d55307 3489 * @param Tickstart: tick start value
AnnaBridge 167:e84263d55307 3490 * @retval HAL status
AnnaBridge 167:e84263d55307 3491 */
AnnaBridge 167:e84263d55307 3492 static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State,
AnnaBridge 167:e84263d55307 3493 uint32_t Timeout, uint32_t Tickstart)
AnnaBridge 167:e84263d55307 3494 {
AnnaBridge 167:e84263d55307 3495 __IO uint8_t tmpreg;
AnnaBridge 167:e84263d55307 3496
AnnaBridge 167:e84263d55307 3497 while ((hspi->Instance->SR & Fifo) != State)
AnnaBridge 167:e84263d55307 3498 {
AnnaBridge 167:e84263d55307 3499 if ((Fifo == SPI_SR_FRLVL) && (State == SPI_FRLVL_EMPTY))
AnnaBridge 167:e84263d55307 3500 {
AnnaBridge 167:e84263d55307 3501 tmpreg = *((__IO uint8_t *)&hspi->Instance->DR);
AnnaBridge 167:e84263d55307 3502 /* To avoid GCC warning */
AnnaBridge 167:e84263d55307 3503 UNUSED(tmpreg);
AnnaBridge 167:e84263d55307 3504 }
AnnaBridge 167:e84263d55307 3505
AnnaBridge 167:e84263d55307 3506 if (Timeout != HAL_MAX_DELAY)
AnnaBridge 167:e84263d55307 3507 {
AnnaBridge 167:e84263d55307 3508 if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) >= Timeout))
AnnaBridge 167:e84263d55307 3509 {
AnnaBridge 167:e84263d55307 3510 /* Disable the SPI and reset the CRC: the CRC value should be cleared
AnnaBridge 167:e84263d55307 3511 on both master and slave sides in order to resynchronize the master
AnnaBridge 167:e84263d55307 3512 and slave for their respective CRC calculation */
AnnaBridge 167:e84263d55307 3513
AnnaBridge 167:e84263d55307 3514 /* Disable TXE, RXNE and ERR interrupts for the interrupt process */
AnnaBridge 167:e84263d55307 3515 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
AnnaBridge 167:e84263d55307 3516
AnnaBridge 167:e84263d55307 3517 if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
AnnaBridge 167:e84263d55307 3518 || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
AnnaBridge 167:e84263d55307 3519 {
AnnaBridge 167:e84263d55307 3520 /* Disable SPI peripheral */
AnnaBridge 167:e84263d55307 3521 __HAL_SPI_DISABLE(hspi);
AnnaBridge 167:e84263d55307 3522 }
AnnaBridge 167:e84263d55307 3523
AnnaBridge 167:e84263d55307 3524 /* Reset CRC Calculation */
AnnaBridge 167:e84263d55307 3525 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
AnnaBridge 167:e84263d55307 3526 {
AnnaBridge 167:e84263d55307 3527 SPI_RESET_CRC(hspi);
AnnaBridge 167:e84263d55307 3528 }
AnnaBridge 167:e84263d55307 3529
AnnaBridge 167:e84263d55307 3530 hspi->State = HAL_SPI_STATE_READY;
AnnaBridge 167:e84263d55307 3531
AnnaBridge 167:e84263d55307 3532 /* Process Unlocked */
AnnaBridge 167:e84263d55307 3533 __HAL_UNLOCK(hspi);
AnnaBridge 167:e84263d55307 3534
AnnaBridge 167:e84263d55307 3535 return HAL_TIMEOUT;
AnnaBridge 167:e84263d55307 3536 }
AnnaBridge 167:e84263d55307 3537 }
AnnaBridge 167:e84263d55307 3538 }
AnnaBridge 167:e84263d55307 3539
AnnaBridge 167:e84263d55307 3540 return HAL_OK;
AnnaBridge 167:e84263d55307 3541 }
AnnaBridge 167:e84263d55307 3542
AnnaBridge 167:e84263d55307 3543 /**
AnnaBridge 167:e84263d55307 3544 * @brief Handle the check of the RX transaction complete.
<> 144:ef7eb2e8f9f7 3545 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 3546 * the configuration information for SPI module.
AnnaBridge 167:e84263d55307 3547 * @param Timeout: Timeout duration
AnnaBridge 167:e84263d55307 3548 * @param Tickstart: tick start value
AnnaBridge 167:e84263d55307 3549 * @retval HAL status
<> 144:ef7eb2e8f9f7 3550 */
AnnaBridge 167:e84263d55307 3551 static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart)
<> 144:ef7eb2e8f9f7 3552 {
AnnaBridge 167:e84263d55307 3553 if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
AnnaBridge 167:e84263d55307 3554 || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
<> 144:ef7eb2e8f9f7 3555 {
<> 144:ef7eb2e8f9f7 3556 /* Disable SPI peripheral */
<> 144:ef7eb2e8f9f7 3557 __HAL_SPI_DISABLE(hspi);
<> 144:ef7eb2e8f9f7 3558 }
AnnaBridge 167:e84263d55307 3559
<> 144:ef7eb2e8f9f7 3560 /* Control the BSY flag */
AnnaBridge 167:e84263d55307 3561 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK)
<> 144:ef7eb2e8f9f7 3562 {
AnnaBridge 167:e84263d55307 3563 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
<> 144:ef7eb2e8f9f7 3564 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 3565 }
<> 144:ef7eb2e8f9f7 3566
AnnaBridge 167:e84263d55307 3567 if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
AnnaBridge 167:e84263d55307 3568 || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
<> 144:ef7eb2e8f9f7 3569 {
<> 144:ef7eb2e8f9f7 3570 /* Empty the FRLVL fifo */
AnnaBridge 167:e84263d55307 3571 if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, Timeout, Tickstart) != HAL_OK)
<> 144:ef7eb2e8f9f7 3572 {
AnnaBridge 167:e84263d55307 3573 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
<> 144:ef7eb2e8f9f7 3574 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 3575 }
<> 144:ef7eb2e8f9f7 3576 }
<> 144:ef7eb2e8f9f7 3577 return HAL_OK;
<> 144:ef7eb2e8f9f7 3578 }
<> 144:ef7eb2e8f9f7 3579
<> 144:ef7eb2e8f9f7 3580 /**
AnnaBridge 167:e84263d55307 3581 * @brief Handle the check of the RXTX or TX transaction complete.
AnnaBridge 167:e84263d55307 3582 * @param hspi: SPI handle
AnnaBridge 167:e84263d55307 3583 * @param Timeout: Timeout duration
AnnaBridge 167:e84263d55307 3584 * @param Tickstart: tick start value
AnnaBridge 167:e84263d55307 3585 * @retval HAL status
<> 144:ef7eb2e8f9f7 3586 */
AnnaBridge 167:e84263d55307 3587 static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart)
<> 144:ef7eb2e8f9f7 3588 {
<> 144:ef7eb2e8f9f7 3589 /* Control if the TX fifo is empty */
AnnaBridge 167:e84263d55307 3590 if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FTLVL, SPI_FTLVL_EMPTY, Timeout, Tickstart) != HAL_OK)
<> 144:ef7eb2e8f9f7 3591 {
AnnaBridge 167:e84263d55307 3592 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
<> 144:ef7eb2e8f9f7 3593 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 3594 }
<> 144:ef7eb2e8f9f7 3595 /* Control the BSY flag */
AnnaBridge 167:e84263d55307 3596 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK)
<> 144:ef7eb2e8f9f7 3597 {
AnnaBridge 167:e84263d55307 3598 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
AnnaBridge 167:e84263d55307 3599 return HAL_TIMEOUT;
AnnaBridge 167:e84263d55307 3600 }
AnnaBridge 167:e84263d55307 3601
AnnaBridge 167:e84263d55307 3602 /* Control if the RX fifo is empty */
AnnaBridge 167:e84263d55307 3603 if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, Timeout, Tickstart) != HAL_OK)
AnnaBridge 167:e84263d55307 3604 {
AnnaBridge 167:e84263d55307 3605 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
<> 144:ef7eb2e8f9f7 3606 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 3607 }
<> 144:ef7eb2e8f9f7 3608 return HAL_OK;
<> 144:ef7eb2e8f9f7 3609 }
<> 144:ef7eb2e8f9f7 3610
<> 144:ef7eb2e8f9f7 3611 /**
AnnaBridge 167:e84263d55307 3612 * @brief Handle the end of the RXTX transaction.
<> 144:ef7eb2e8f9f7 3613 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 3614 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 3615 * @retval None
<> 144:ef7eb2e8f9f7 3616 */
<> 144:ef7eb2e8f9f7 3617 static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 3618 {
AnnaBridge 167:e84263d55307 3619 uint32_t tickstart = 0U;
AnnaBridge 167:e84263d55307 3620
AnnaBridge 167:e84263d55307 3621 /* Init tickstart for timeout managment*/
AnnaBridge 167:e84263d55307 3622 tickstart = HAL_GetTick();
AnnaBridge 167:e84263d55307 3623
<> 144:ef7eb2e8f9f7 3624 /* Disable ERR interrupt */
<> 144:ef7eb2e8f9f7 3625 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
<> 144:ef7eb2e8f9f7 3626
<> 144:ef7eb2e8f9f7 3627 /* Check the end of the transaction */
AnnaBridge 167:e84263d55307 3628 if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
<> 144:ef7eb2e8f9f7 3629 {
AnnaBridge 167:e84263d55307 3630 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
<> 144:ef7eb2e8f9f7 3631 }
<> 144:ef7eb2e8f9f7 3632
AnnaBridge 167:e84263d55307 3633 #if (USE_SPI_CRC != 0U)
<> 144:ef7eb2e8f9f7 3634 /* Check if CRC error occurred */
AnnaBridge 167:e84263d55307 3635 if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
<> 144:ef7eb2e8f9f7 3636 {
<> 144:ef7eb2e8f9f7 3637 hspi->State = HAL_SPI_STATE_READY;
AnnaBridge 167:e84263d55307 3638 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
<> 144:ef7eb2e8f9f7 3639 __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
<> 144:ef7eb2e8f9f7 3640 HAL_SPI_ErrorCallback(hspi);
<> 144:ef7eb2e8f9f7 3641 }
<> 144:ef7eb2e8f9f7 3642 else
<> 144:ef7eb2e8f9f7 3643 {
AnnaBridge 167:e84263d55307 3644 #endif /* USE_SPI_CRC */
AnnaBridge 167:e84263d55307 3645 if (hspi->ErrorCode == HAL_SPI_ERROR_NONE)
<> 144:ef7eb2e8f9f7 3646 {
AnnaBridge 167:e84263d55307 3647 if (hspi->State == HAL_SPI_STATE_BUSY_RX)
<> 144:ef7eb2e8f9f7 3648 {
AnnaBridge 167:e84263d55307 3649 hspi->State = HAL_SPI_STATE_READY;
<> 144:ef7eb2e8f9f7 3650 HAL_SPI_RxCpltCallback(hspi);
<> 144:ef7eb2e8f9f7 3651 }
<> 144:ef7eb2e8f9f7 3652 else
<> 144:ef7eb2e8f9f7 3653 {
AnnaBridge 167:e84263d55307 3654 hspi->State = HAL_SPI_STATE_READY;
<> 144:ef7eb2e8f9f7 3655 HAL_SPI_TxRxCpltCallback(hspi);
<> 144:ef7eb2e8f9f7 3656 }
<> 144:ef7eb2e8f9f7 3657 }
<> 144:ef7eb2e8f9f7 3658 else
<> 144:ef7eb2e8f9f7 3659 {
<> 144:ef7eb2e8f9f7 3660 hspi->State = HAL_SPI_STATE_READY;
<> 144:ef7eb2e8f9f7 3661 HAL_SPI_ErrorCallback(hspi);
<> 144:ef7eb2e8f9f7 3662 }
AnnaBridge 167:e84263d55307 3663 #if (USE_SPI_CRC != 0U)
<> 144:ef7eb2e8f9f7 3664 }
AnnaBridge 167:e84263d55307 3665 #endif /* USE_SPI_CRC */
<> 144:ef7eb2e8f9f7 3666 }
<> 144:ef7eb2e8f9f7 3667
<> 144:ef7eb2e8f9f7 3668 /**
AnnaBridge 167:e84263d55307 3669 * @brief Handle the end of the RX transaction.
<> 144:ef7eb2e8f9f7 3670 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 3671 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 3672 * @retval None
<> 144:ef7eb2e8f9f7 3673 */
<> 144:ef7eb2e8f9f7 3674 static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 3675 {
AnnaBridge 167:e84263d55307 3676 /* Disable RXNE and ERR interrupt */
AnnaBridge 167:e84263d55307 3677 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
AnnaBridge 167:e84263d55307 3678
AnnaBridge 167:e84263d55307 3679 /* Check the end of the transaction */
AnnaBridge 167:e84263d55307 3680 if (SPI_EndRxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
AnnaBridge 167:e84263d55307 3681 {
AnnaBridge 167:e84263d55307 3682 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
AnnaBridge 167:e84263d55307 3683 }
AnnaBridge 167:e84263d55307 3684 hspi->State = HAL_SPI_STATE_READY;
AnnaBridge 167:e84263d55307 3685
AnnaBridge 167:e84263d55307 3686 #if (USE_SPI_CRC != 0U)
AnnaBridge 167:e84263d55307 3687 /* Check if CRC error occurred */
AnnaBridge 167:e84263d55307 3688 if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
AnnaBridge 167:e84263d55307 3689 {
AnnaBridge 167:e84263d55307 3690 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
AnnaBridge 167:e84263d55307 3691 __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
AnnaBridge 167:e84263d55307 3692 HAL_SPI_ErrorCallback(hspi);
AnnaBridge 167:e84263d55307 3693 }
AnnaBridge 167:e84263d55307 3694 else
AnnaBridge 167:e84263d55307 3695 {
AnnaBridge 167:e84263d55307 3696 #endif /* USE_SPI_CRC */
AnnaBridge 167:e84263d55307 3697 if (hspi->ErrorCode == HAL_SPI_ERROR_NONE)
<> 144:ef7eb2e8f9f7 3698 {
AnnaBridge 167:e84263d55307 3699 HAL_SPI_RxCpltCallback(hspi);
<> 144:ef7eb2e8f9f7 3700 }
<> 144:ef7eb2e8f9f7 3701 else
<> 144:ef7eb2e8f9f7 3702 {
AnnaBridge 167:e84263d55307 3703 HAL_SPI_ErrorCallback(hspi);
<> 144:ef7eb2e8f9f7 3704 }
AnnaBridge 167:e84263d55307 3705 #if (USE_SPI_CRC != 0U)
AnnaBridge 167:e84263d55307 3706 }
AnnaBridge 167:e84263d55307 3707 #endif /* USE_SPI_CRC */
<> 144:ef7eb2e8f9f7 3708 }
<> 144:ef7eb2e8f9f7 3709
<> 144:ef7eb2e8f9f7 3710 /**
AnnaBridge 167:e84263d55307 3711 * @brief Handle the end of the TX transaction.
<> 144:ef7eb2e8f9f7 3712 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 3713 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 3714 * @retval None
<> 144:ef7eb2e8f9f7 3715 */
<> 144:ef7eb2e8f9f7 3716 static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 3717 {
AnnaBridge 167:e84263d55307 3718 uint32_t tickstart = 0U;
AnnaBridge 167:e84263d55307 3719
AnnaBridge 167:e84263d55307 3720 /* Init tickstart for timeout management*/
AnnaBridge 167:e84263d55307 3721 tickstart = HAL_GetTick();
AnnaBridge 167:e84263d55307 3722
<> 144:ef7eb2e8f9f7 3723 /* Disable TXE and ERR interrupt */
<> 144:ef7eb2e8f9f7 3724 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR));
<> 144:ef7eb2e8f9f7 3725
<> 144:ef7eb2e8f9f7 3726 /* Check the end of the transaction */
AnnaBridge 167:e84263d55307 3727 if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
<> 144:ef7eb2e8f9f7 3728 {
AnnaBridge 167:e84263d55307 3729 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
<> 144:ef7eb2e8f9f7 3730 }
<> 144:ef7eb2e8f9f7 3731
<> 144:ef7eb2e8f9f7 3732 /* Clear overrun flag in 2 Lines communication mode because received is not read */
AnnaBridge 167:e84263d55307 3733 if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
<> 144:ef7eb2e8f9f7 3734 {
<> 144:ef7eb2e8f9f7 3735 __HAL_SPI_CLEAR_OVRFLAG(hspi);
<> 144:ef7eb2e8f9f7 3736 }
<> 144:ef7eb2e8f9f7 3737
<> 144:ef7eb2e8f9f7 3738 hspi->State = HAL_SPI_STATE_READY;
AnnaBridge 167:e84263d55307 3739 if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
<> 144:ef7eb2e8f9f7 3740 {
<> 144:ef7eb2e8f9f7 3741 HAL_SPI_ErrorCallback(hspi);
<> 144:ef7eb2e8f9f7 3742 }
<> 144:ef7eb2e8f9f7 3743 else
<> 144:ef7eb2e8f9f7 3744 {
<> 144:ef7eb2e8f9f7 3745 HAL_SPI_TxCpltCallback(hspi);
<> 144:ef7eb2e8f9f7 3746 }
<> 144:ef7eb2e8f9f7 3747 }
<> 144:ef7eb2e8f9f7 3748
<> 144:ef7eb2e8f9f7 3749 /**
AnnaBridge 167:e84263d55307 3750 * @brief Handle abort a Rx transaction.
AnnaBridge 167:e84263d55307 3751 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
AnnaBridge 167:e84263d55307 3752 * the configuration information for SPI module.
AnnaBridge 167:e84263d55307 3753 * @retval None
AnnaBridge 167:e84263d55307 3754 */
AnnaBridge 167:e84263d55307 3755 static void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi)
AnnaBridge 167:e84263d55307 3756 {
AnnaBridge 167:e84263d55307 3757 __IO uint32_t count;
AnnaBridge 167:e84263d55307 3758
AnnaBridge 167:e84263d55307 3759 /* Disable SPI Peripheral */
AnnaBridge 167:e84263d55307 3760 __HAL_SPI_DISABLE(hspi);
AnnaBridge 167:e84263d55307 3761
AnnaBridge 167:e84263d55307 3762 count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
AnnaBridge 167:e84263d55307 3763
AnnaBridge 167:e84263d55307 3764 /* Disable TXEIE, RXNEIE and ERRIE(mode fault event, overrun error, TI frame error) interrupts */
AnnaBridge 167:e84263d55307 3765 CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXEIE | SPI_CR2_RXNEIE | SPI_CR2_ERRIE));
AnnaBridge 167:e84263d55307 3766
AnnaBridge 167:e84263d55307 3767 /* Check RXNEIE is disabled */
AnnaBridge 167:e84263d55307 3768 do
AnnaBridge 167:e84263d55307 3769 {
AnnaBridge 167:e84263d55307 3770 if (count-- == 0U)
AnnaBridge 167:e84263d55307 3771 {
AnnaBridge 167:e84263d55307 3772 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
AnnaBridge 167:e84263d55307 3773 break;
AnnaBridge 167:e84263d55307 3774 }
AnnaBridge 167:e84263d55307 3775 }
AnnaBridge 167:e84263d55307 3776 while (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE));
AnnaBridge 167:e84263d55307 3777
AnnaBridge 167:e84263d55307 3778 /* Control the BSY flag */
AnnaBridge 167:e84263d55307 3779 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
AnnaBridge 167:e84263d55307 3780 {
AnnaBridge 167:e84263d55307 3781 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
AnnaBridge 167:e84263d55307 3782 }
AnnaBridge 167:e84263d55307 3783
AnnaBridge 167:e84263d55307 3784 /* Empty the FRLVL fifo */
AnnaBridge 167:e84263d55307 3785 if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
AnnaBridge 167:e84263d55307 3786 {
AnnaBridge 167:e84263d55307 3787 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
AnnaBridge 167:e84263d55307 3788 }
AnnaBridge 167:e84263d55307 3789
AnnaBridge 167:e84263d55307 3790 hspi->State = HAL_SPI_STATE_ABORT;
AnnaBridge 167:e84263d55307 3791 }
AnnaBridge 167:e84263d55307 3792
AnnaBridge 167:e84263d55307 3793 /**
AnnaBridge 167:e84263d55307 3794 * @brief Handle abort a Tx or Rx/Tx transaction.
AnnaBridge 167:e84263d55307 3795 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
AnnaBridge 167:e84263d55307 3796 * the configuration information for SPI module.
AnnaBridge 167:e84263d55307 3797 * @retval None
AnnaBridge 167:e84263d55307 3798 */
AnnaBridge 167:e84263d55307 3799 static void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi)
AnnaBridge 167:e84263d55307 3800 {
AnnaBridge 167:e84263d55307 3801 __IO uint32_t count;
AnnaBridge 167:e84263d55307 3802
AnnaBridge 167:e84263d55307 3803 count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
AnnaBridge 167:e84263d55307 3804
AnnaBridge 167:e84263d55307 3805 /* Disable TXEIE, RXNEIE and ERRIE(mode fault event, overrun error, TI frame error) interrupts */
AnnaBridge 167:e84263d55307 3806 CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXEIE | SPI_CR2_RXNEIE | SPI_CR2_ERRIE));
AnnaBridge 167:e84263d55307 3807
AnnaBridge 167:e84263d55307 3808 /* Check TXEIE is disabled */
AnnaBridge 167:e84263d55307 3809 do
AnnaBridge 167:e84263d55307 3810 {
AnnaBridge 167:e84263d55307 3811 if (count-- == 0U)
AnnaBridge 167:e84263d55307 3812 {
AnnaBridge 167:e84263d55307 3813 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
AnnaBridge 167:e84263d55307 3814 break;
AnnaBridge 167:e84263d55307 3815 }
AnnaBridge 167:e84263d55307 3816 }
AnnaBridge 167:e84263d55307 3817 while (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE));
AnnaBridge 167:e84263d55307 3818
AnnaBridge 167:e84263d55307 3819 if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
AnnaBridge 167:e84263d55307 3820 {
AnnaBridge 167:e84263d55307 3821 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
AnnaBridge 167:e84263d55307 3822 }
AnnaBridge 167:e84263d55307 3823
AnnaBridge 167:e84263d55307 3824 /* Disable SPI Peripheral */
AnnaBridge 167:e84263d55307 3825 __HAL_SPI_DISABLE(hspi);
AnnaBridge 167:e84263d55307 3826
AnnaBridge 167:e84263d55307 3827 /* Empty the FRLVL fifo */
AnnaBridge 167:e84263d55307 3828 if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
AnnaBridge 167:e84263d55307 3829 {
AnnaBridge 167:e84263d55307 3830 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
AnnaBridge 167:e84263d55307 3831 }
AnnaBridge 167:e84263d55307 3832
AnnaBridge 167:e84263d55307 3833 hspi->State = HAL_SPI_STATE_ABORT;
AnnaBridge 167:e84263d55307 3834 }
AnnaBridge 167:e84263d55307 3835
AnnaBridge 167:e84263d55307 3836 /**
<> 144:ef7eb2e8f9f7 3837 * @}
<> 144:ef7eb2e8f9f7 3838 */
<> 144:ef7eb2e8f9f7 3839
<> 144:ef7eb2e8f9f7 3840 #endif /* HAL_SPI_MODULE_ENABLED */
<> 144:ef7eb2e8f9f7 3841
<> 144:ef7eb2e8f9f7 3842 /**
<> 144:ef7eb2e8f9f7 3843 * @}
<> 144:ef7eb2e8f9f7 3844 */
<> 144:ef7eb2e8f9f7 3845
<> 144:ef7eb2e8f9f7 3846 /**
<> 144:ef7eb2e8f9f7 3847 * @}
<> 144:ef7eb2e8f9f7 3848 */
<> 144:ef7eb2e8f9f7 3849
<> 144:ef7eb2e8f9f7 3850 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/