mbed-dev - mbed library sources. Supersedes mbed-src.

Users » mbed_official » Code » mbed-dev

mbed library sources. Supersedes mbed-src.

Dependents: Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.c@181:57724642e740, 2018-02-16 (annotated)

Committer:: AnnaBridge
Date:: Fri Feb 16 16:09:33 2018 +0000
Revision:: 181:57724642e740
Parent:: 173:e131a1973e81

mbed-dev library. Release version 159.

Who changed what in which revision?

User	Revision	Line number	New contents of line
<>	144:ef7eb2e8f9f7	1	/**
<>	144:ef7eb2e8f9f7	2	******************************************************************************
<>	144:ef7eb2e8f9f7	3	* @file stm32l4xx_hal_spi.c
<>	144:ef7eb2e8f9f7	4	* @author MCD Application Team
<>	144:ef7eb2e8f9f7	5	* @brief SPI HAL module driver.
<>	144:ef7eb2e8f9f7	6	* This file provides firmware functions to manage the following
<>	144:ef7eb2e8f9f7	7	* functionalities of the Serial Peripheral Interface (SPI) peripheral:
<>	144:ef7eb2e8f9f7	8	* + Initialization and de-initialization functions
<>	144:ef7eb2e8f9f7	9	* + IO operation functions
<>	144:ef7eb2e8f9f7	10	* + Peripheral Control functions
<>	144:ef7eb2e8f9f7	11	* + Peripheral State functions
<>	144:ef7eb2e8f9f7	12	*
<>	144:ef7eb2e8f9f7	13	@verbatim
<>	144:ef7eb2e8f9f7	14	==============================================================================
<>	144:ef7eb2e8f9f7	15	##### How to use this driver #####
<>	144:ef7eb2e8f9f7	16	==============================================================================
<>	144:ef7eb2e8f9f7	17	[..]
<>	144:ef7eb2e8f9f7	18	The SPI HAL driver can be used as follows:
<>	144:ef7eb2e8f9f7	19
<>	144:ef7eb2e8f9f7	20	(#) Declare a SPI_HandleTypeDef handle structure, for example:
<>	144:ef7eb2e8f9f7	21	SPI_HandleTypeDef hspi;
<>	144:ef7eb2e8f9f7	22
<>	144:ef7eb2e8f9f7	23	(#)Initialize the SPI low level resources by implementing the HAL_SPI_MspInit() API:
<>	144:ef7eb2e8f9f7	24	(##) Enable the SPIx interface clock
<>	144:ef7eb2e8f9f7	25	(##) SPI pins configuration
<>	144:ef7eb2e8f9f7	26	(+++) Enable the clock for the SPI GPIOs
<>	144:ef7eb2e8f9f7	27	(+++) Configure these SPI pins as alternate function push-pull
<>	144:ef7eb2e8f9f7	28	(##) NVIC configuration if you need to use interrupt process
<>	144:ef7eb2e8f9f7	29	(+++) Configure the SPIx interrupt priority
<>	144:ef7eb2e8f9f7	30	(+++) Enable the NVIC SPI IRQ handle
<>	144:ef7eb2e8f9f7	31	(##) DMA Configuration if you need to use DMA process
AnnaBridge	167:e84263d55307	32	(+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive Stream/Channel
<>	144:ef7eb2e8f9f7	33	(+++) Enable the DMAx clock
<>	144:ef7eb2e8f9f7	34	(+++) Configure the DMA handle parameters
AnnaBridge	167:e84263d55307	35	(+++) Configure the DMA Tx or Rx Stream/Channel
AnnaBridge	181:57724642e740	36	(+++) Associate the initialized hdma_tx(or _rx) handle to the hspi DMA Tx or Rx handle
AnnaBridge	167:e84263d55307	37	(+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx Stream/Channel
<>	144:ef7eb2e8f9f7	38
<>	144:ef7eb2e8f9f7	39	(#) Program the Mode, BidirectionalMode , Data size, Baudrate Prescaler, NSS
<>	144:ef7eb2e8f9f7	40	management, Clock polarity and phase, FirstBit and CRC configuration in the hspi Init structure.
<>	144:ef7eb2e8f9f7	41
<>	144:ef7eb2e8f9f7	42	(#) Initialize the SPI registers by calling the HAL_SPI_Init() API:
<>	144:ef7eb2e8f9f7	43	(++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
<>	144:ef7eb2e8f9f7	44	by calling the customized HAL_SPI_MspInit() API.
<>	144:ef7eb2e8f9f7	45	[..]
<>	144:ef7eb2e8f9f7	46	Circular mode restriction:
<>	144:ef7eb2e8f9f7	47	(#) The DMA circular mode cannot be used when the SPI is configured in these modes:
<>	144:ef7eb2e8f9f7	48	(##) Master 2Lines RxOnly
<>	144:ef7eb2e8f9f7	49	(##) Master 1Line Rx
<>	144:ef7eb2e8f9f7	50	(#) The CRC feature is not managed when the DMA circular mode is enabled
<>	144:ef7eb2e8f9f7	51	(#) When the SPI DMA Pause/Stop features are used, we must use the following APIs
<>	144:ef7eb2e8f9f7	52	the HAL_SPI_DMAPause()/ HAL_SPI_DMAStop() only under the SPI callbacks
AnnaBridge	167:e84263d55307	53	[..]
AnnaBridge	167:e84263d55307	54	Master Receive mode restriction:
AnnaBridge	181:57724642e740	55	(#) In Master unidirectional receive-only mode (MSTR =1, BIDIMODE=0, RXONLY=1) or
AnnaBridge	167:e84263d55307	56	bidirectional receive mode (MSTR=1, BIDIMODE=1, BIDIOE=0), to ensure that the SPI
AnnaBridge	167:e84263d55307	57	does not initiate a new transfer the following procedure has to be respected:
AnnaBridge	167:e84263d55307	58	(##) HAL_SPI_DeInit()
AnnaBridge	167:e84263d55307	59	(##) HAL_SPI_Init()
AnnaBridge	167:e84263d55307	60	[..]
AnnaBridge	181:57724642e740	61	Using the HAL it is not possible to reach all supported SPI frequency with the differents SPI Modes,
AnnaBridge	181:57724642e740	62	the following table resume the max SPI frequency reached with data size 8bits/16bits,
AnnaBridge	181:57724642e740	63	according to frequency of the APBx Peripheral Clock (fPCLK) used by the SPI instance.
<>	144:ef7eb2e8f9f7	64
<>	144:ef7eb2e8f9f7	65	@endverbatim
AnnaBridge	167:e84263d55307	66
AnnaBridge	167:e84263d55307	67	Additional table :
AnnaBridge	167:e84263d55307	68
AnnaBridge	167:e84263d55307	69	DataSize = SPI_DATASIZE_8BIT:
AnnaBridge	167:e84263d55307	70	+----------------------------------------------------------------------------------------------+
AnnaBridge	167:e84263d55307	71	\| \| \| 2Lines Fullduplex \| 2Lines RxOnly \| 1Line \|
AnnaBridge	167:e84263d55307	72	\| Process \| Tranfert mode \|---------------------\|----------------------\|----------------------\|
AnnaBridge	167:e84263d55307	73	\| \| \| Master \| Slave \| Master \| Slave \| Master \| Slave \|
AnnaBridge	167:e84263d55307	74	\|==============================================================================================\|
AnnaBridge	167:e84263d55307	75	\| T \| Polling \| Fpclk/4 \| Fpclk/8 \| NA \| NA \| NA \| NA \|
AnnaBridge	167:e84263d55307	76	\| X \|----------------\|----------\|----------\|-----------\|----------\|-----------\|----------\|
AnnaBridge	167:e84263d55307	77	\| / \| Interrupt \| Fpclk/4 \| Fpclk/16 \| NA \| NA \| NA \| NA \|
AnnaBridge	167:e84263d55307	78	\| R \|----------------\|----------\|----------\|-----------\|----------\|-----------\|----------\|
AnnaBridge	167:e84263d55307	79	\| X \| DMA \| Fpclk/2 \| Fpclk/2 \| NA \| NA \| NA \| NA \|
AnnaBridge	167:e84263d55307	80	\|=========\|================\|==========\|==========\|===========\|==========\|===========\|==========\|
AnnaBridge	167:e84263d55307	81	\| \| Polling \| Fpclk/4 \| Fpclk/8 \| Fpclk/16 \| Fpclk/8 \| Fpclk/8 \| Fpclk/8 \|
AnnaBridge	167:e84263d55307	82	\| \|----------------\|----------\|----------\|-----------\|----------\|-----------\|----------\|
AnnaBridge	167:e84263d55307	83	\| R \| Interrupt \| Fpclk/8 \| Fpclk/16 \| Fpclk/8 \| Fpclk/8 \| Fpclk/8 \| Fpclk/4 \|
AnnaBridge	167:e84263d55307	84	\| X \|----------------\|----------\|----------\|-----------\|----------\|-----------\|----------\|
AnnaBridge	167:e84263d55307	85	\| \| DMA \| Fpclk/4 \| Fpclk/2 \| Fpclk/2 \| Fpclk/16 \| Fpclk/2 \| Fpclk/16 \|
AnnaBridge	167:e84263d55307	86	\|=========\|================\|==========\|==========\|===========\|==========\|===========\|==========\|
AnnaBridge	167:e84263d55307	87	\| \| Polling \| Fpclk/8 \| Fpclk/2 \| NA \| NA \| Fpclk/8 \| Fpclk/8 \|
AnnaBridge	167:e84263d55307	88	\| \|----------------\|----------\|----------\|-----------\|----------\|-----------\|----------\|
AnnaBridge	167:e84263d55307	89	\| T \| Interrupt \| Fpclk/2 \| Fpclk/4 \| NA \| NA \| Fpclk/16 \| Fpclk/8 \|
AnnaBridge	167:e84263d55307	90	\| X \|----------------\|----------\|----------\|-----------\|----------\|-----------\|----------\|
AnnaBridge	167:e84263d55307	91	\| \| DMA \| Fpclk/2 \| Fpclk/2 \| NA \| NA \| Fpclk/8 \| Fpclk/16 \|
AnnaBridge	167:e84263d55307	92	+----------------------------------------------------------------------------------------------+
AnnaBridge	167:e84263d55307	93
AnnaBridge	167:e84263d55307	94	DataSize = SPI_DATASIZE_16BIT:
AnnaBridge	167:e84263d55307	95	+----------------------------------------------------------------------------------------------+
AnnaBridge	167:e84263d55307	96	\| \| \| 2Lines Fullduplex \| 2Lines RxOnly \| 1Line \|
AnnaBridge	167:e84263d55307	97	\| Process \| Tranfert mode \|---------------------\|----------------------\|----------------------\|
AnnaBridge	167:e84263d55307	98	\| \| \| Master \| Slave \| Master \| Slave \| Master \| Slave \|
AnnaBridge	167:e84263d55307	99	\|==============================================================================================\|
AnnaBridge	167:e84263d55307	100	\| T \| Polling \| Fpclk/4 \| Fpclk/8 \| NA \| NA \| NA \| NA \|
AnnaBridge	167:e84263d55307	101	\| X \|----------------\|----------\|----------\|-----------\|----------\|-----------\|----------\|
AnnaBridge	167:e84263d55307	102	\| / \| Interrupt \| Fpclk/4 \| Fpclk/16 \| NA \| NA \| NA \| NA \|
AnnaBridge	167:e84263d55307	103	\| R \|----------------\|----------\|----------\|-----------\|----------\|-----------\|----------\|
AnnaBridge	167:e84263d55307	104	\| X \| DMA \| Fpclk/2 \| Fpclk/2 \| NA \| NA \| NA \| NA \|
AnnaBridge	167:e84263d55307	105	\|=========\|================\|==========\|==========\|===========\|==========\|===========\|==========\|
AnnaBridge	167:e84263d55307	106	\| \| Polling \| Fpclk/4 \| Fpclk/8 \| Fpclk/16 \| Fpclk/8 \| Fpclk/8 \| Fpclk/8 \|
AnnaBridge	167:e84263d55307	107	\| \|----------------\|----------\|----------\|-----------\|----------\|-----------\|----------\|
AnnaBridge	167:e84263d55307	108	\| R \| Interrupt \| Fpclk/8 \| Fpclk/16 \| Fpclk/8 \| Fpclk/8 \| Fpclk/8 \| Fpclk/4 \|
AnnaBridge	167:e84263d55307	109	\| X \|----------------\|----------\|----------\|-----------\|----------\|-----------\|----------\|
AnnaBridge	167:e84263d55307	110	\| \| DMA \| Fpclk/4 \| Fpclk/2 \| Fpclk/2 \| Fpclk/16 \| Fpclk/2 \| Fpclk/16 \|
AnnaBridge	167:e84263d55307	111	\|=========\|================\|==========\|==========\|===========\|==========\|===========\|==========\|
AnnaBridge	167:e84263d55307	112	\| \| Polling \| Fpclk/8 \| Fpclk/2 \| NA \| NA \| Fpclk/8 \| Fpclk/8 \|
AnnaBridge	167:e84263d55307	113	\| \|----------------\|----------\|----------\|-----------\|----------\|-----------\|----------\|
AnnaBridge	167:e84263d55307	114	\| T \| Interrupt \| Fpclk/2 \| Fpclk/4 \| NA \| NA \| Fpclk/16 \| Fpclk/8 \|
AnnaBridge	167:e84263d55307	115	\| X \|----------------\|----------\|----------\|-----------\|----------\|-----------\|----------\|
AnnaBridge	167:e84263d55307	116	\| \| DMA \| Fpclk/2 \| Fpclk/2 \| NA \| NA \| Fpclk/8 \| Fpclk/16 \|
AnnaBridge	167:e84263d55307	117	+----------------------------------------------------------------------------------------------+
AnnaBridge	167:e84263d55307	118	@note The max SPI frequency depend on SPI data size (4bits, 5bits,..., 8bits,...15bits, 16bits),
AnnaBridge	167:e84263d55307	119	SPI mode(2 Lines fullduplex, 2 lines RxOnly, 1 line TX/RX) and Process mode (Polling, IT, DMA).
AnnaBridge	167:e84263d55307	120	@note
AnnaBridge	167:e84263d55307	121	(#) TX/RX processes are HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_IT() and HAL_SPI_TransmitReceive_DMA()
AnnaBridge	167:e84263d55307	122	(#) RX processes are HAL_SPI_Receive(), HAL_SPI_Receive_IT() and HAL_SPI_Receive_DMA()
AnnaBridge	167:e84263d55307	123	(#) TX processes are HAL_SPI_Transmit(), HAL_SPI_Transmit_IT() and HAL_SPI_Transmit_DMA()
AnnaBridge	167:e84263d55307	124
<>	144:ef7eb2e8f9f7	125	******************************************************************************
<>	144:ef7eb2e8f9f7	126	* @attention
<>	144:ef7eb2e8f9f7	127	*
AnnaBridge	167:e84263d55307	128	* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
<>	144:ef7eb2e8f9f7	129	*
<>	144:ef7eb2e8f9f7	130	* Redistribution and use in source and binary forms, with or without modification,
<>	144:ef7eb2e8f9f7	131	* are permitted provided that the following conditions are met:
<>	144:ef7eb2e8f9f7	132	* 1. Redistributions of source code must retain the above copyright notice,
<>	144:ef7eb2e8f9f7	133	* this list of conditions and the following disclaimer.
<>	144:ef7eb2e8f9f7	134	* 2. Redistributions in binary form must reproduce the above copyright notice,
<>	144:ef7eb2e8f9f7	135	* this list of conditions and the following disclaimer in the documentation
<>	144:ef7eb2e8f9f7	136	* and/or other materials provided with the distribution.
<>	144:ef7eb2e8f9f7	137	* 3. Neither the name of STMicroelectronics nor the names of its contributors
<>	144:ef7eb2e8f9f7	138	* may be used to endorse or promote products derived from this software
<>	144:ef7eb2e8f9f7	139	* without specific prior written permission.
<>	144:ef7eb2e8f9f7	140	*
<>	144:ef7eb2e8f9f7	141	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<>	144:ef7eb2e8f9f7	142	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<>	144:ef7eb2e8f9f7	143	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<>	144:ef7eb2e8f9f7	144	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<>	144:ef7eb2e8f9f7	145	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<>	144:ef7eb2e8f9f7	146	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<>	144:ef7eb2e8f9f7	147	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<>	144:ef7eb2e8f9f7	148	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<>	144:ef7eb2e8f9f7	149	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<>	144:ef7eb2e8f9f7	150	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<>	144:ef7eb2e8f9f7	151	*
<>	144:ef7eb2e8f9f7	152	******************************************************************************
<>	144:ef7eb2e8f9f7	153	*/
<>	144:ef7eb2e8f9f7	154
<>	144:ef7eb2e8f9f7	155	/* Includes ------------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	156	#include "stm32l4xx_hal.h"
<>	144:ef7eb2e8f9f7	157
<>	144:ef7eb2e8f9f7	158	/** @addtogroup STM32L4xx_HAL_Driver
<>	144:ef7eb2e8f9f7	159	* @{
<>	144:ef7eb2e8f9f7	160	*/
<>	144:ef7eb2e8f9f7	161
<>	144:ef7eb2e8f9f7	162	/** @defgroup SPI SPI
<>	144:ef7eb2e8f9f7	163	* @brief SPI HAL module driver
<>	144:ef7eb2e8f9f7	164	* @{
<>	144:ef7eb2e8f9f7	165	*/
<>	144:ef7eb2e8f9f7	166	#ifdef HAL_SPI_MODULE_ENABLED
<>	144:ef7eb2e8f9f7	167
<>	144:ef7eb2e8f9f7	168	/* Private typedef -----------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	169	/* Private defines -----------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	170	/** @defgroup SPI_Private_Constants SPI Private Constants
<>	144:ef7eb2e8f9f7	171	* @{
<>	144:ef7eb2e8f9f7	172	*/
AnnaBridge	167:e84263d55307	173	#define SPI_DEFAULT_TIMEOUT 100U
<>	144:ef7eb2e8f9f7	174	/**
<>	144:ef7eb2e8f9f7	175	* @}
<>	144:ef7eb2e8f9f7	176	*/
<>	144:ef7eb2e8f9f7	177
<>	144:ef7eb2e8f9f7	178	/* Private macros ------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	179	/* Private variables ---------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	180	/* Private function prototypes -----------------------------------------------*/
<>	144:ef7eb2e8f9f7	181	/** @defgroup SPI_Private_Functions SPI Private Functions
<>	144:ef7eb2e8f9f7	182	* @{
<>	144:ef7eb2e8f9f7	183	*/
<>	144:ef7eb2e8f9f7	184	static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma);
<>	144:ef7eb2e8f9f7	185	static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
<>	144:ef7eb2e8f9f7	186	static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma);
<>	144:ef7eb2e8f9f7	187	static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma);
<>	144:ef7eb2e8f9f7	188	static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma);
<>	144:ef7eb2e8f9f7	189	static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma);
<>	144:ef7eb2e8f9f7	190	static void SPI_DMAError(DMA_HandleTypeDef *hdma);
AnnaBridge	167:e84263d55307	191	static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma);
AnnaBridge	167:e84263d55307	192	static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
AnnaBridge	167:e84263d55307	193	static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
AnnaBridge	167:e84263d55307	194	static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, uint32_t State,
AnnaBridge	167:e84263d55307	195	uint32_t Timeout, uint32_t Tickstart);
AnnaBridge	167:e84263d55307	196	static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State,
AnnaBridge	167:e84263d55307	197	uint32_t Timeout, uint32_t Tickstart);
<>	144:ef7eb2e8f9f7	198	static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
<>	144:ef7eb2e8f9f7	199	static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
<>	144:ef7eb2e8f9f7	200	static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
<>	144:ef7eb2e8f9f7	201	static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
<>	144:ef7eb2e8f9f7	202	static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
<>	144:ef7eb2e8f9f7	203	static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
<>	144:ef7eb2e8f9f7	204	static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
<>	144:ef7eb2e8f9f7	205	static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
AnnaBridge	167:e84263d55307	206	#if (USE_SPI_CRC != 0U)
AnnaBridge	167:e84263d55307	207	static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi);
AnnaBridge	167:e84263d55307	208	static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi);
AnnaBridge	167:e84263d55307	209	static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi);
<>	144:ef7eb2e8f9f7	210	static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi);
AnnaBridge	167:e84263d55307	211	#endif /* USE_SPI_CRC */
AnnaBridge	167:e84263d55307	212	static void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi);
AnnaBridge	167:e84263d55307	213	static void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi);
<>	144:ef7eb2e8f9f7	214	static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi);
<>	144:ef7eb2e8f9f7	215	static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi);
<>	144:ef7eb2e8f9f7	216	static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi);
AnnaBridge	167:e84263d55307	217	static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart);
AnnaBridge	167:e84263d55307	218	static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart);
<>	144:ef7eb2e8f9f7	219	/**
<>	144:ef7eb2e8f9f7	220	* @}
<>	144:ef7eb2e8f9f7	221	*/
<>	144:ef7eb2e8f9f7	222
AnnaBridge	167:e84263d55307	223	/* Exported functions --------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	224	/** @defgroup SPI_Exported_Functions SPI Exported Functions
<>	144:ef7eb2e8f9f7	225	* @{
<>	144:ef7eb2e8f9f7	226	*/
<>	144:ef7eb2e8f9f7	227
<>	144:ef7eb2e8f9f7	228	/** @defgroup SPI_Exported_Functions_Group1 Initialization and de-initialization functions
<>	144:ef7eb2e8f9f7	229	* @brief Initialization and Configuration functions
<>	144:ef7eb2e8f9f7	230	*
<>	144:ef7eb2e8f9f7	231	@verbatim
<>	144:ef7eb2e8f9f7	232	===============================================================================
<>	144:ef7eb2e8f9f7	233	##### Initialization and de-initialization functions #####
<>	144:ef7eb2e8f9f7	234	===============================================================================
<>	144:ef7eb2e8f9f7	235	[..] This subsection provides a set of functions allowing to initialize and
<>	144:ef7eb2e8f9f7	236	de-initialize the SPIx peripheral:
<>	144:ef7eb2e8f9f7	237
<>	144:ef7eb2e8f9f7	238	(+) User must implement HAL_SPI_MspInit() function in which he configures
<>	144:ef7eb2e8f9f7	239	all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
<>	144:ef7eb2e8f9f7	240
<>	144:ef7eb2e8f9f7	241	(+) Call the function HAL_SPI_Init() to configure the selected device with
<>	144:ef7eb2e8f9f7	242	the selected configuration:
<>	144:ef7eb2e8f9f7	243	(++) Mode
<>	144:ef7eb2e8f9f7	244	(++) Direction
<>	144:ef7eb2e8f9f7	245	(++) Data Size
<>	144:ef7eb2e8f9f7	246	(++) Clock Polarity and Phase
<>	144:ef7eb2e8f9f7	247	(++) NSS Management
<>	144:ef7eb2e8f9f7	248	(++) BaudRate Prescaler
<>	144:ef7eb2e8f9f7	249	(++) FirstBit
<>	144:ef7eb2e8f9f7	250	(++) TIMode
<>	144:ef7eb2e8f9f7	251	(++) CRC Calculation
<>	144:ef7eb2e8f9f7	252	(++) CRC Polynomial if CRC enabled
<>	144:ef7eb2e8f9f7	253	(++) CRC Length, used only with Data8 and Data16
<>	144:ef7eb2e8f9f7	254	(++) FIFO reception threshold
<>	144:ef7eb2e8f9f7	255
<>	144:ef7eb2e8f9f7	256	(+) Call the function HAL_SPI_DeInit() to restore the default configuration
<>	144:ef7eb2e8f9f7	257	of the selected SPIx peripheral.
<>	144:ef7eb2e8f9f7	258
<>	144:ef7eb2e8f9f7	259	@endverbatim
<>	144:ef7eb2e8f9f7	260	* @{
<>	144:ef7eb2e8f9f7	261	*/
<>	144:ef7eb2e8f9f7	262
<>	144:ef7eb2e8f9f7	263	/**
<>	144:ef7eb2e8f9f7	264	* @brief Initialize the SPI according to the specified parameters
<>	144:ef7eb2e8f9f7	265	* in the SPI_InitTypeDef and initialize the associated handle.
AnnaBridge	181:57724642e740	266	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	267	* the configuration information for SPI module.
<>	144:ef7eb2e8f9f7	268	* @retval HAL status
<>	144:ef7eb2e8f9f7	269	*/
<>	144:ef7eb2e8f9f7	270	HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
<>	144:ef7eb2e8f9f7	271	{
<>	144:ef7eb2e8f9f7	272	uint32_t frxth;
<>	144:ef7eb2e8f9f7	273
<>	144:ef7eb2e8f9f7	274	/* Check the SPI handle allocation */
AnnaBridge	167:e84263d55307	275	if (hspi == NULL)
<>	144:ef7eb2e8f9f7	276	{
<>	144:ef7eb2e8f9f7	277	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	278	}
<>	144:ef7eb2e8f9f7	279
<>	144:ef7eb2e8f9f7	280	/* Check the parameters */
<>	144:ef7eb2e8f9f7	281	assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));
<>	144:ef7eb2e8f9f7	282	assert_param(IS_SPI_MODE(hspi->Init.Mode));
<>	144:ef7eb2e8f9f7	283	assert_param(IS_SPI_DIRECTION(hspi->Init.Direction));
<>	144:ef7eb2e8f9f7	284	assert_param(IS_SPI_DATASIZE(hspi->Init.DataSize));
<>	144:ef7eb2e8f9f7	285	assert_param(IS_SPI_NSS(hspi->Init.NSS));
<>	144:ef7eb2e8f9f7	286	assert_param(IS_SPI_NSSP(hspi->Init.NSSPMode));
<>	144:ef7eb2e8f9f7	287	assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
<>	144:ef7eb2e8f9f7	288	assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit));
<>	144:ef7eb2e8f9f7	289	assert_param(IS_SPI_TIMODE(hspi->Init.TIMode));
AnnaBridge	167:e84263d55307	290	if (hspi->Init.TIMode == SPI_TIMODE_DISABLE)
AnnaBridge	167:e84263d55307	291	{
AnnaBridge	167:e84263d55307	292	assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity));
AnnaBridge	167:e84263d55307	293	assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase));
AnnaBridge	167:e84263d55307	294	}
AnnaBridge	167:e84263d55307	295	#if (USE_SPI_CRC != 0U)
<>	144:ef7eb2e8f9f7	296	assert_param(IS_SPI_CRC_CALCULATION(hspi->Init.CRCCalculation));
AnnaBridge	167:e84263d55307	297	if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
AnnaBridge	167:e84263d55307	298	{
AnnaBridge	167:e84263d55307	299	assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial));
AnnaBridge	167:e84263d55307	300	assert_param(IS_SPI_CRC_LENGTH(hspi->Init.CRCLength));
AnnaBridge	167:e84263d55307	301	}
AnnaBridge	167:e84263d55307	302	#else
AnnaBridge	167:e84263d55307	303	hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
AnnaBridge	167:e84263d55307	304	#endif /* USE_SPI_CRC */
AnnaBridge	167:e84263d55307	305
AnnaBridge	167:e84263d55307	306	if (hspi->State == HAL_SPI_STATE_RESET)
<>	144:ef7eb2e8f9f7	307	{
<>	144:ef7eb2e8f9f7	308	/* Allocate lock resource and initialize it */
<>	144:ef7eb2e8f9f7	309	hspi->Lock = HAL_UNLOCKED;
<>	144:ef7eb2e8f9f7	310
<>	144:ef7eb2e8f9f7	311	/* Init the low level hardware : GPIO, CLOCK, NVIC... */
<>	144:ef7eb2e8f9f7	312	HAL_SPI_MspInit(hspi);
<>	144:ef7eb2e8f9f7	313	}
<>	144:ef7eb2e8f9f7	314
<>	144:ef7eb2e8f9f7	315	hspi->State = HAL_SPI_STATE_BUSY;
<>	144:ef7eb2e8f9f7	316
<>	144:ef7eb2e8f9f7	317	/* Disable the selected SPI peripheral */
<>	144:ef7eb2e8f9f7	318	__HAL_SPI_DISABLE(hspi);
<>	144:ef7eb2e8f9f7	319
<>	144:ef7eb2e8f9f7	320	/* Align by default the rs fifo threshold on the data size */
AnnaBridge	167:e84263d55307	321	if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
<>	144:ef7eb2e8f9f7	322	{
<>	144:ef7eb2e8f9f7	323	frxth = SPI_RXFIFO_THRESHOLD_HF;
<>	144:ef7eb2e8f9f7	324	}
<>	144:ef7eb2e8f9f7	325	else
<>	144:ef7eb2e8f9f7	326	{
<>	144:ef7eb2e8f9f7	327	frxth = SPI_RXFIFO_THRESHOLD_QF;
<>	144:ef7eb2e8f9f7	328	}
<>	144:ef7eb2e8f9f7	329
<>	144:ef7eb2e8f9f7	330	/* CRC calculation is valid only for 16Bit and 8 Bit */
AnnaBridge	167:e84263d55307	331	if ((hspi->Init.DataSize != SPI_DATASIZE_16BIT) && (hspi->Init.DataSize != SPI_DATASIZE_8BIT))
<>	144:ef7eb2e8f9f7	332	{
<>	144:ef7eb2e8f9f7	333	/* CRC must be disabled */
<>	144:ef7eb2e8f9f7	334	hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
<>	144:ef7eb2e8f9f7	335	}
<>	144:ef7eb2e8f9f7	336
<>	144:ef7eb2e8f9f7	337	/* Align the CRC Length on the data size */
AnnaBridge	167:e84263d55307	338	if (hspi->Init.CRCLength == SPI_CRC_LENGTH_DATASIZE)
<>	144:ef7eb2e8f9f7	339	{
<>	144:ef7eb2e8f9f7	340	/* CRC Length aligned on the data size : value set by default */
AnnaBridge	167:e84263d55307	341	if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
<>	144:ef7eb2e8f9f7	342	{
<>	144:ef7eb2e8f9f7	343	hspi->Init.CRCLength = SPI_CRC_LENGTH_16BIT;
<>	144:ef7eb2e8f9f7	344	}
<>	144:ef7eb2e8f9f7	345	else
<>	144:ef7eb2e8f9f7	346	{
<>	144:ef7eb2e8f9f7	347	hspi->Init.CRCLength = SPI_CRC_LENGTH_8BIT;
<>	144:ef7eb2e8f9f7	348	}
<>	144:ef7eb2e8f9f7	349	}
<>	144:ef7eb2e8f9f7	350
AnnaBridge	167:e84263d55307	351	/----------------------- SPIx CR1 & CR2 Configuration ---------------------/
<>	144:ef7eb2e8f9f7	352	/* Configure : SPI Mode, Communication Mode, Clock polarity and phase, NSS management,
AnnaBridge	167:e84263d55307	353	Communication speed, First bit and CRC calculation state */
AnnaBridge	167:e84263d55307	354	WRITE_REG(hspi->Instance->CR1, (hspi->Init.Mode \| hspi->Init.Direction \|
AnnaBridge	167:e84263d55307	355	hspi->Init.CLKPolarity \| hspi->Init.CLKPhase \| (hspi->Init.NSS & SPI_CR1_SSM) \|
AnnaBridge	167:e84263d55307	356	hspi->Init.BaudRatePrescaler \| hspi->Init.FirstBit \| hspi->Init.CRCCalculation));
AnnaBridge	167:e84263d55307	357	#if (USE_SPI_CRC != 0U)
AnnaBridge	167:e84263d55307	358	/* Configure : CRC Length */
AnnaBridge	167:e84263d55307	359	if (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)
<>	144:ef7eb2e8f9f7	360	{
AnnaBridge	167:e84263d55307	361	hspi->Instance->CR1 \|= SPI_CR1_CRCL;
<>	144:ef7eb2e8f9f7	362	}
AnnaBridge	167:e84263d55307	363	#endif /* USE_SPI_CRC */
AnnaBridge	167:e84263d55307	364
AnnaBridge	181:57724642e740	365	/* Configure : NSS management, TI Mode, NSS Pulse, Data size and Rx Fifo threshold */
AnnaBridge	167:e84263d55307	366	WRITE_REG(hspi->Instance->CR2, (((hspi->Init.NSS >> 16U) & SPI_CR2_SSOE) \| hspi->Init.TIMode \|
AnnaBridge	167:e84263d55307	367	hspi->Init.NSSPMode \| hspi->Init.DataSize) \| frxth);
AnnaBridge	167:e84263d55307	368
AnnaBridge	167:e84263d55307	369	#if (USE_SPI_CRC != 0U)
AnnaBridge	167:e84263d55307	370	/---------------------------- SPIx CRCPOLY Configuration ------------------/
<>	144:ef7eb2e8f9f7	371	/* Configure : CRC Polynomial */
AnnaBridge	167:e84263d55307	372	if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
AnnaBridge	167:e84263d55307	373	{
AnnaBridge	167:e84263d55307	374	WRITE_REG(hspi->Instance->CRCPR, hspi->Init.CRCPolynomial);
AnnaBridge	167:e84263d55307	375	}
AnnaBridge	167:e84263d55307	376	#endif /* USE_SPI_CRC */
AnnaBridge	167:e84263d55307	377
AnnaBridge	167:e84263d55307	378	#if defined(SPI_I2SCFGR_I2SMOD)
AnnaBridge	167:e84263d55307	379	/* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */
AnnaBridge	167:e84263d55307	380	CLEAR_BIT(hspi->Instance->I2SCFGR, SPI_I2SCFGR_I2SMOD);
AnnaBridge	167:e84263d55307	381	#endif /* SPI_I2SCFGR_I2SMOD */
<>	144:ef7eb2e8f9f7	382
<>	144:ef7eb2e8f9f7	383	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
AnnaBridge	167:e84263d55307	384	hspi->State = HAL_SPI_STATE_READY;
<>	144:ef7eb2e8f9f7	385
<>	144:ef7eb2e8f9f7	386	return HAL_OK;
<>	144:ef7eb2e8f9f7	387	}
<>	144:ef7eb2e8f9f7	388
<>	144:ef7eb2e8f9f7	389	/**
AnnaBridge	167:e84263d55307	390	* @brief De-Initialize the SPI peripheral.
AnnaBridge	181:57724642e740	391	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	392	* the configuration information for SPI module.
<>	144:ef7eb2e8f9f7	393	* @retval HAL status
<>	144:ef7eb2e8f9f7	394	*/
<>	144:ef7eb2e8f9f7	395	HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi)
<>	144:ef7eb2e8f9f7	396	{
<>	144:ef7eb2e8f9f7	397	/* Check the SPI handle allocation */
AnnaBridge	167:e84263d55307	398	if (hspi == NULL)
<>	144:ef7eb2e8f9f7	399	{
<>	144:ef7eb2e8f9f7	400	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	401	}
<>	144:ef7eb2e8f9f7	402
AnnaBridge	167:e84263d55307	403	/* Check SPI Instance parameter */
<>	144:ef7eb2e8f9f7	404	assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));
AnnaBridge	167:e84263d55307	405
<>	144:ef7eb2e8f9f7	406	hspi->State = HAL_SPI_STATE_BUSY;
<>	144:ef7eb2e8f9f7	407
<>	144:ef7eb2e8f9f7	408	/* Disable the SPI Peripheral Clock */
<>	144:ef7eb2e8f9f7	409	__HAL_SPI_DISABLE(hspi);
<>	144:ef7eb2e8f9f7	410
<>	144:ef7eb2e8f9f7	411	/* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
<>	144:ef7eb2e8f9f7	412	HAL_SPI_MspDeInit(hspi);
<>	144:ef7eb2e8f9f7	413
<>	144:ef7eb2e8f9f7	414	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
<>	144:ef7eb2e8f9f7	415	hspi->State = HAL_SPI_STATE_RESET;
<>	144:ef7eb2e8f9f7	416
AnnaBridge	167:e84263d55307	417	/* Release Lock */
<>	144:ef7eb2e8f9f7	418	__HAL_UNLOCK(hspi);
<>	144:ef7eb2e8f9f7	419
<>	144:ef7eb2e8f9f7	420	return HAL_OK;
<>	144:ef7eb2e8f9f7	421	}
<>	144:ef7eb2e8f9f7	422
<>	144:ef7eb2e8f9f7	423	/**
AnnaBridge	167:e84263d55307	424	* @brief Initialize the SPI MSP.
AnnaBridge	181:57724642e740	425	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	426	* the configuration information for SPI module.
<>	144:ef7eb2e8f9f7	427	* @retval None
<>	144:ef7eb2e8f9f7	428	*/
<>	144:ef7eb2e8f9f7	429	__weak void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi)
<>	144:ef7eb2e8f9f7	430	{
<>	144:ef7eb2e8f9f7	431	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	432	UNUSED(hspi);
<>	144:ef7eb2e8f9f7	433
<>	144:ef7eb2e8f9f7	434	/* NOTE : This function should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	435	the HAL_SPI_MspInit should be implemented in the user file
<>	144:ef7eb2e8f9f7	436	*/
<>	144:ef7eb2e8f9f7	437	}
<>	144:ef7eb2e8f9f7	438
<>	144:ef7eb2e8f9f7	439	/**
AnnaBridge	167:e84263d55307	440	* @brief De-Initialize the SPI MSP.
AnnaBridge	181:57724642e740	441	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	442	* the configuration information for SPI module.
<>	144:ef7eb2e8f9f7	443	* @retval None
<>	144:ef7eb2e8f9f7	444	*/
<>	144:ef7eb2e8f9f7	445	__weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi)
<>	144:ef7eb2e8f9f7	446	{
<>	144:ef7eb2e8f9f7	447	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	448	UNUSED(hspi);
<>	144:ef7eb2e8f9f7	449
<>	144:ef7eb2e8f9f7	450	/* NOTE : This function should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	451	the HAL_SPI_MspDeInit should be implemented in the user file
<>	144:ef7eb2e8f9f7	452	*/
<>	144:ef7eb2e8f9f7	453	}
<>	144:ef7eb2e8f9f7	454
<>	144:ef7eb2e8f9f7	455	/**
<>	144:ef7eb2e8f9f7	456	* @}
<>	144:ef7eb2e8f9f7	457	*/
<>	144:ef7eb2e8f9f7	458
<>	144:ef7eb2e8f9f7	459	/** @defgroup SPI_Exported_Functions_Group2 IO operation functions
<>	144:ef7eb2e8f9f7	460	* @brief Data transfers functions
<>	144:ef7eb2e8f9f7	461	*
<>	144:ef7eb2e8f9f7	462	@verbatim
<>	144:ef7eb2e8f9f7	463	==============================================================================
<>	144:ef7eb2e8f9f7	464	##### IO operation functions #####
<>	144:ef7eb2e8f9f7	465	===============================================================================
<>	144:ef7eb2e8f9f7	466	[..]
<>	144:ef7eb2e8f9f7	467	This subsection provides a set of functions allowing to manage the SPI
<>	144:ef7eb2e8f9f7	468	data transfers.
<>	144:ef7eb2e8f9f7	469
<>	144:ef7eb2e8f9f7	470	[..] The SPI supports master and slave mode :
<>	144:ef7eb2e8f9f7	471
<>	144:ef7eb2e8f9f7	472	(#) There are two modes of transfer:
<>	144:ef7eb2e8f9f7	473	(++) Blocking mode: The communication is performed in polling mode.
<>	144:ef7eb2e8f9f7	474	The HAL status of all data processing is returned by the same function
<>	144:ef7eb2e8f9f7	475	after finishing transfer.
<>	144:ef7eb2e8f9f7	476	(++) No-Blocking mode: The communication is performed using Interrupts
AnnaBridge	167:e84263d55307	477	or DMA, These APIs return the HAL status.
AnnaBridge	167:e84263d55307	478	The end of the data processing will be indicated through the
AnnaBridge	167:e84263d55307	479	dedicated SPI IRQ when using Interrupt mode or the DMA IRQ when
AnnaBridge	167:e84263d55307	480	using DMA mode.
AnnaBridge	167:e84263d55307	481	The HAL_SPI_TxCpltCallback(), HAL_SPI_RxCpltCallback() and HAL_SPI_TxRxCpltCallback() user callbacks
AnnaBridge	167:e84263d55307	482	will be executed respectively at the end of the transmit or Receive process
AnnaBridge	167:e84263d55307	483	The HAL_SPI_ErrorCallback()user callback will be executed when a communication error is detected
<>	144:ef7eb2e8f9f7	484
<>	144:ef7eb2e8f9f7	485	(#) APIs provided for these 2 transfer modes (Blocking mode or Non blocking mode using either Interrupt or DMA)
<>	144:ef7eb2e8f9f7	486	exist for 1Line (simplex) and 2Lines (full duplex) modes.
<>	144:ef7eb2e8f9f7	487
<>	144:ef7eb2e8f9f7	488	@endverbatim
<>	144:ef7eb2e8f9f7	489	* @{
<>	144:ef7eb2e8f9f7	490	*/
<>	144:ef7eb2e8f9f7	491
<>	144:ef7eb2e8f9f7	492	/**
<>	144:ef7eb2e8f9f7	493	* @brief Transmit an amount of data in blocking mode.
AnnaBridge	181:57724642e740	494	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	495	* the configuration information for SPI module.
AnnaBridge	181:57724642e740	496	* @param pData pointer to data buffer
AnnaBridge	181:57724642e740	497	* @param Size amount of data to be sent
AnnaBridge	181:57724642e740	498	* @param Timeout Timeout duration
<>	144:ef7eb2e8f9f7	499	* @retval HAL status
<>	144:ef7eb2e8f9f7	500	*/
<>	144:ef7eb2e8f9f7	501	HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size, uint32_t Timeout)
<>	144:ef7eb2e8f9f7	502	{
AnnaBridge	167:e84263d55307	503	uint32_t tickstart = 0U;
<>	144:ef7eb2e8f9f7	504	HAL_StatusTypeDef errorcode = HAL_OK;
<>	144:ef7eb2e8f9f7	505
AnnaBridge	167:e84263d55307	506	/* Check Direction parameter */
<>	144:ef7eb2e8f9f7	507	assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
<>	144:ef7eb2e8f9f7	508
<>	144:ef7eb2e8f9f7	509	/* Process Locked */
<>	144:ef7eb2e8f9f7	510	__HAL_LOCK(hspi);
<>	144:ef7eb2e8f9f7	511
AnnaBridge	167:e84263d55307	512	/* Init tickstart for timeout management*/
AnnaBridge	167:e84263d55307	513	tickstart = HAL_GetTick();
AnnaBridge	167:e84263d55307	514
AnnaBridge	167:e84263d55307	515	if (hspi->State != HAL_SPI_STATE_READY)
<>	144:ef7eb2e8f9f7	516	{
<>	144:ef7eb2e8f9f7	517	errorcode = HAL_BUSY;
<>	144:ef7eb2e8f9f7	518	goto error;
<>	144:ef7eb2e8f9f7	519	}
<>	144:ef7eb2e8f9f7	520
AnnaBridge	167:e84263d55307	521	if ((pData == NULL) \|\| (Size == 0U))
<>	144:ef7eb2e8f9f7	522	{
<>	144:ef7eb2e8f9f7	523	errorcode = HAL_ERROR;
<>	144:ef7eb2e8f9f7	524	goto error;
<>	144:ef7eb2e8f9f7	525	}
<>	144:ef7eb2e8f9f7	526
<>	144:ef7eb2e8f9f7	527	/* Set the transaction information */
<>	144:ef7eb2e8f9f7	528	hspi->State = HAL_SPI_STATE_BUSY_TX;
<>	144:ef7eb2e8f9f7	529	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
AnnaBridge	167:e84263d55307	530	hspi->pTxBuffPtr = (uint8_t *)pData;
<>	144:ef7eb2e8f9f7	531	hspi->TxXferSize = Size;
<>	144:ef7eb2e8f9f7	532	hspi->TxXferCount = Size;
AnnaBridge	167:e84263d55307	533
AnnaBridge	167:e84263d55307	534	/Init field not used in handle to zero /
<>	144:ef7eb2e8f9f7	535	hspi->pRxBuffPtr = (uint8_t *)NULL;
AnnaBridge	167:e84263d55307	536	hspi->RxXferSize = 0U;
AnnaBridge	167:e84263d55307	537	hspi->RxXferCount = 0U;
AnnaBridge	167:e84263d55307	538	hspi->TxISR = NULL;
AnnaBridge	167:e84263d55307	539	hspi->RxISR = NULL;
<>	144:ef7eb2e8f9f7	540
<>	144:ef7eb2e8f9f7	541	/* Configure communication direction : 1Line */
AnnaBridge	167:e84263d55307	542	if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
<>	144:ef7eb2e8f9f7	543	{
<>	144:ef7eb2e8f9f7	544	SPI_1LINE_TX(hspi);
<>	144:ef7eb2e8f9f7	545	}
<>	144:ef7eb2e8f9f7	546
AnnaBridge	167:e84263d55307	547	#if (USE_SPI_CRC != 0U)
<>	144:ef7eb2e8f9f7	548	/* Reset CRC Calculation */
AnnaBridge	167:e84263d55307	549	if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<>	144:ef7eb2e8f9f7	550	{
<>	144:ef7eb2e8f9f7	551	SPI_RESET_CRC(hspi);
<>	144:ef7eb2e8f9f7	552	}
AnnaBridge	167:e84263d55307	553	#endif /* USE_SPI_CRC */
<>	144:ef7eb2e8f9f7	554
<>	144:ef7eb2e8f9f7	555	/* Check if the SPI is already enabled */
AnnaBridge	167:e84263d55307	556	if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
<>	144:ef7eb2e8f9f7	557	{
<>	144:ef7eb2e8f9f7	558	/* Enable SPI peripheral */
<>	144:ef7eb2e8f9f7	559	__HAL_SPI_ENABLE(hspi);
<>	144:ef7eb2e8f9f7	560	}
<>	144:ef7eb2e8f9f7	561
<>	144:ef7eb2e8f9f7	562	/* Transmit data in 16 Bit mode */
AnnaBridge	167:e84263d55307	563	if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
<>	144:ef7eb2e8f9f7	564	{
AnnaBridge	167:e84263d55307	565	if ((hspi->Init.Mode == SPI_MODE_SLAVE) \|\| (hspi->TxXferCount == 0x01U))
AnnaBridge	167:e84263d55307	566	{
AnnaBridge	167:e84263d55307	567	hspi->Instance->DR = ((uint16_t )pData);
AnnaBridge	167:e84263d55307	568	pData += sizeof(uint16_t);
AnnaBridge	167:e84263d55307	569	hspi->TxXferCount--;
AnnaBridge	167:e84263d55307	570	}
<>	144:ef7eb2e8f9f7	571	/* Transmit data in 16 Bit mode */
AnnaBridge	167:e84263d55307	572	while (hspi->TxXferCount > 0U)
<>	144:ef7eb2e8f9f7	573	{
<>	144:ef7eb2e8f9f7	574	/* Wait until TXE flag is set to send data */
AnnaBridge	167:e84263d55307	575	if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE))
<>	144:ef7eb2e8f9f7	576	{
AnnaBridge	167:e84263d55307	577	hspi->Instance->DR = ((uint16_t )pData);
AnnaBridge	167:e84263d55307	578	pData += sizeof(uint16_t);
AnnaBridge	167:e84263d55307	579	hspi->TxXferCount--;
<>	144:ef7eb2e8f9f7	580	}
<>	144:ef7eb2e8f9f7	581	else
<>	144:ef7eb2e8f9f7	582	{
<>	144:ef7eb2e8f9f7	583	/* Timeout management */
AnnaBridge	167:e84263d55307	584	if ((Timeout == 0U) \|\| ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick() - tickstart) >= Timeout)))
<>	144:ef7eb2e8f9f7	585	{
<>	144:ef7eb2e8f9f7	586	errorcode = HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	587	goto error;
<>	144:ef7eb2e8f9f7	588	}
<>	144:ef7eb2e8f9f7	589	}
<>	144:ef7eb2e8f9f7	590	}
<>	144:ef7eb2e8f9f7	591	}
<>	144:ef7eb2e8f9f7	592	/* Transmit data in 8 Bit mode */
<>	144:ef7eb2e8f9f7	593	else
<>	144:ef7eb2e8f9f7	594	{
AnnaBridge	167:e84263d55307	595	if ((hspi->Init.Mode == SPI_MODE_SLAVE) \|\| (hspi->TxXferCount == 0x01U))
AnnaBridge	167:e84263d55307	596	{
AnnaBridge	167:e84263d55307	597	if (hspi->TxXferCount > 1U)
AnnaBridge	167:e84263d55307	598	{
AnnaBridge	167:e84263d55307	599	/* write on the data register in packing mode */
AnnaBridge	167:e84263d55307	600	hspi->Instance->DR = ((uint16_t )pData);
AnnaBridge	167:e84263d55307	601	pData += sizeof(uint16_t);
AnnaBridge	167:e84263d55307	602	hspi->TxXferCount -= 2U;
AnnaBridge	167:e84263d55307	603	}
AnnaBridge	167:e84263d55307	604	else
AnnaBridge	167:e84263d55307	605	{
AnnaBridge	167:e84263d55307	606	((__IO uint8_t )&hspi->Instance->DR) = (*pData++);
AnnaBridge	167:e84263d55307	607	hspi->TxXferCount--;
AnnaBridge	167:e84263d55307	608	}
AnnaBridge	167:e84263d55307	609	}
AnnaBridge	167:e84263d55307	610	while (hspi->TxXferCount > 0U)
<>	144:ef7eb2e8f9f7	611	{
<>	144:ef7eb2e8f9f7	612	/* Wait until TXE flag is set to send data */
AnnaBridge	167:e84263d55307	613	if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE))
<>	144:ef7eb2e8f9f7	614	{
AnnaBridge	167:e84263d55307	615	if (hspi->TxXferCount > 1U)
<>	144:ef7eb2e8f9f7	616	{
<>	144:ef7eb2e8f9f7	617	/* write on the data register in packing mode */
AnnaBridge	167:e84263d55307	618	hspi->Instance->DR = ((uint16_t )pData);
AnnaBridge	167:e84263d55307	619	pData += sizeof(uint16_t);
AnnaBridge	167:e84263d55307	620	hspi->TxXferCount -= 2U;
<>	144:ef7eb2e8f9f7	621	}
<>	144:ef7eb2e8f9f7	622	else
<>	144:ef7eb2e8f9f7	623	{
AnnaBridge	167:e84263d55307	624	((__IO uint8_t )&hspi->Instance->DR) = (*pData++);
<>	144:ef7eb2e8f9f7	625	hspi->TxXferCount--;
<>	144:ef7eb2e8f9f7	626	}
<>	144:ef7eb2e8f9f7	627	}
<>	144:ef7eb2e8f9f7	628	else
<>	144:ef7eb2e8f9f7	629	{
<>	144:ef7eb2e8f9f7	630	/* Timeout management */
AnnaBridge	167:e84263d55307	631	if ((Timeout == 0U) \|\| ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick() - tickstart) >= Timeout)))
<>	144:ef7eb2e8f9f7	632	{
<>	144:ef7eb2e8f9f7	633	errorcode = HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	634	goto error;
<>	144:ef7eb2e8f9f7	635	}
<>	144:ef7eb2e8f9f7	636	}
<>	144:ef7eb2e8f9f7	637	}
<>	144:ef7eb2e8f9f7	638	}
AnnaBridge	167:e84263d55307	639	#if (USE_SPI_CRC != 0U)
<>	144:ef7eb2e8f9f7	640	/* Enable CRC Transmission */
AnnaBridge	167:e84263d55307	641	if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<>	144:ef7eb2e8f9f7	642	{
AnnaBridge	167:e84263d55307	643	SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
<>	144:ef7eb2e8f9f7	644	}
AnnaBridge	167:e84263d55307	645	#endif /* USE_SPI_CRC */
<>	144:ef7eb2e8f9f7	646
<>	144:ef7eb2e8f9f7	647	/* Check the end of the transaction */
AnnaBridge	167:e84263d55307	648	if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	649	{
<>	144:ef7eb2e8f9f7	650	hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
<>	144:ef7eb2e8f9f7	651	}
AnnaBridge	167:e84263d55307	652
AnnaBridge	181:57724642e740	653	// Added for MBED PR #4975
AnnaBridge	173:e131a1973e81	654	if (hspi->Init.Direction == SPI_DIRECTION_1LINE) {
AnnaBridge	173:e131a1973e81	655	__HAL_SPI_DISABLE(hspi);
AnnaBridge	173:e131a1973e81	656	}
AnnaBridge	173:e131a1973e81	657
<>	144:ef7eb2e8f9f7	658	/* Clear overrun flag in 2 Lines communication mode because received is not read */
AnnaBridge	167:e84263d55307	659	if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
<>	144:ef7eb2e8f9f7	660	{
<>	144:ef7eb2e8f9f7	661	__HAL_SPI_CLEAR_OVRFLAG(hspi);
<>	144:ef7eb2e8f9f7	662	}
<>	144:ef7eb2e8f9f7	663
AnnaBridge	167:e84263d55307	664	if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
<>	144:ef7eb2e8f9f7	665	{
<>	144:ef7eb2e8f9f7	666	errorcode = HAL_ERROR;
<>	144:ef7eb2e8f9f7	667	}
<>	144:ef7eb2e8f9f7	668
<>	144:ef7eb2e8f9f7	669	error:
<>	144:ef7eb2e8f9f7	670	hspi->State = HAL_SPI_STATE_READY;
<>	144:ef7eb2e8f9f7	671	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	672	__HAL_UNLOCK(hspi);
<>	144:ef7eb2e8f9f7	673	return errorcode;
<>	144:ef7eb2e8f9f7	674	}
<>	144:ef7eb2e8f9f7	675
<>	144:ef7eb2e8f9f7	676	/**
<>	144:ef7eb2e8f9f7	677	* @brief Receive an amount of data in blocking mode.
AnnaBridge	181:57724642e740	678	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	679	* the configuration information for SPI module.
AnnaBridge	181:57724642e740	680	* @param pData pointer to data buffer
AnnaBridge	181:57724642e740	681	* @param Size amount of data to be received
AnnaBridge	181:57724642e740	682	* @param Timeout Timeout duration
<>	144:ef7eb2e8f9f7	683	* @retval HAL status
<>	144:ef7eb2e8f9f7	684	*/
<>	144:ef7eb2e8f9f7	685	HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size, uint32_t Timeout)
<>	144:ef7eb2e8f9f7	686	{
AnnaBridge	167:e84263d55307	687	#if (USE_SPI_CRC != 0U)
AnnaBridge	167:e84263d55307	688	__IO uint16_t tmpreg = 0U;
AnnaBridge	167:e84263d55307	689	#endif /* USE_SPI_CRC */
AnnaBridge	167:e84263d55307	690	uint32_t tickstart = 0U;
<>	144:ef7eb2e8f9f7	691	HAL_StatusTypeDef errorcode = HAL_OK;
AnnaBridge	167:e84263d55307	692
AnnaBridge	167:e84263d55307	693	if ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))
<>	144:ef7eb2e8f9f7	694	{
AnnaBridge	167:e84263d55307	695	hspi->State = HAL_SPI_STATE_BUSY_RX;
AnnaBridge	167:e84263d55307	696	/* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
AnnaBridge	167:e84263d55307	697	return HAL_SPI_TransmitReceive(hspi, pData, pData, Size, Timeout);
<>	144:ef7eb2e8f9f7	698	}
<>	144:ef7eb2e8f9f7	699
<>	144:ef7eb2e8f9f7	700	/* Process Locked */
<>	144:ef7eb2e8f9f7	701	__HAL_LOCK(hspi);
<>	144:ef7eb2e8f9f7	702
AnnaBridge	167:e84263d55307	703	/* Init tickstart for timeout management*/
AnnaBridge	167:e84263d55307	704	tickstart = HAL_GetTick();
AnnaBridge	167:e84263d55307	705
AnnaBridge	167:e84263d55307	706	if (hspi->State != HAL_SPI_STATE_READY)
<>	144:ef7eb2e8f9f7	707	{
<>	144:ef7eb2e8f9f7	708	errorcode = HAL_BUSY;
<>	144:ef7eb2e8f9f7	709	goto error;
<>	144:ef7eb2e8f9f7	710	}
<>	144:ef7eb2e8f9f7	711
AnnaBridge	167:e84263d55307	712	if ((pData == NULL) \|\| (Size == 0U))
<>	144:ef7eb2e8f9f7	713	{
<>	144:ef7eb2e8f9f7	714	errorcode = HAL_ERROR;
<>	144:ef7eb2e8f9f7	715	goto error;
<>	144:ef7eb2e8f9f7	716	}
<>	144:ef7eb2e8f9f7	717
AnnaBridge	167:e84263d55307	718	/* Set the transaction information */
<>	144:ef7eb2e8f9f7	719	hspi->State = HAL_SPI_STATE_BUSY_RX;
<>	144:ef7eb2e8f9f7	720	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
AnnaBridge	167:e84263d55307	721	hspi->pRxBuffPtr = (uint8_t *)pData;
<>	144:ef7eb2e8f9f7	722	hspi->RxXferSize = Size;
<>	144:ef7eb2e8f9f7	723	hspi->RxXferCount = Size;
AnnaBridge	167:e84263d55307	724
AnnaBridge	167:e84263d55307	725	/Init field not used in handle to zero /
<>	144:ef7eb2e8f9f7	726	hspi->pTxBuffPtr = (uint8_t *)NULL;
AnnaBridge	167:e84263d55307	727	hspi->TxXferSize = 0U;
AnnaBridge	167:e84263d55307	728	hspi->TxXferCount = 0U;
AnnaBridge	167:e84263d55307	729	hspi->RxISR = NULL;
AnnaBridge	167:e84263d55307	730	hspi->TxISR = NULL;
AnnaBridge	167:e84263d55307	731
AnnaBridge	167:e84263d55307	732	#if (USE_SPI_CRC != 0U)
<>	144:ef7eb2e8f9f7	733	/* Reset CRC Calculation */
AnnaBridge	167:e84263d55307	734	if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<>	144:ef7eb2e8f9f7	735	{
<>	144:ef7eb2e8f9f7	736	SPI_RESET_CRC(hspi);
<>	144:ef7eb2e8f9f7	737	/* this is done to handle the CRCNEXT before the latest data */
<>	144:ef7eb2e8f9f7	738	hspi->RxXferCount--;
<>	144:ef7eb2e8f9f7	739	}
AnnaBridge	167:e84263d55307	740	#endif /* USE_SPI_CRC */
AnnaBridge	167:e84263d55307	741
AnnaBridge	167:e84263d55307	742	/* Set the Rx Fifo threshold */
AnnaBridge	167:e84263d55307	743	if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
<>	144:ef7eb2e8f9f7	744	{
AnnaBridge	181:57724642e740	745	/* Set RX Fifo threshold according the reception data length: 16bit */
<>	144:ef7eb2e8f9f7	746	CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
<>	144:ef7eb2e8f9f7	747	}
<>	144:ef7eb2e8f9f7	748	else
<>	144:ef7eb2e8f9f7	749	{
AnnaBridge	181:57724642e740	750	/* Set RX Fifo threshold according the reception data length: 8bit */
<>	144:ef7eb2e8f9f7	751	SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
<>	144:ef7eb2e8f9f7	752	}
<>	144:ef7eb2e8f9f7	753
AnnaBridge	167:e84263d55307	754	/* Configure communication direction: 1Line */
AnnaBridge	167:e84263d55307	755	if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
<>	144:ef7eb2e8f9f7	756	{
<>	144:ef7eb2e8f9f7	757	SPI_1LINE_RX(hspi);
<>	144:ef7eb2e8f9f7	758	}
<>	144:ef7eb2e8f9f7	759
<>	144:ef7eb2e8f9f7	760	/* Check if the SPI is already enabled */
AnnaBridge	167:e84263d55307	761	if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
<>	144:ef7eb2e8f9f7	762	{
<>	144:ef7eb2e8f9f7	763	/* Enable SPI peripheral */
<>	144:ef7eb2e8f9f7	764	__HAL_SPI_ENABLE(hspi);
<>	144:ef7eb2e8f9f7	765	}
<>	144:ef7eb2e8f9f7	766
AnnaBridge	167:e84263d55307	767	/* Receive data in 8 Bit mode */
AnnaBridge	167:e84263d55307	768	if (hspi->Init.DataSize <= SPI_DATASIZE_8BIT)
<>	144:ef7eb2e8f9f7	769	{
<>	144:ef7eb2e8f9f7	770	/* Transfer loop */
AnnaBridge	167:e84263d55307	771	while (hspi->RxXferCount > 0U)
<>	144:ef7eb2e8f9f7	772	{
<>	144:ef7eb2e8f9f7	773	/* Check the RXNE flag */
AnnaBridge	167:e84263d55307	774	if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE))
<>	144:ef7eb2e8f9f7	775	{
<>	144:ef7eb2e8f9f7	776	/* read the received data */
AnnaBridge	167:e84263d55307	777	(* (uint8_t )pData) = (__IO uint8_t *)&hspi->Instance->DR;
AnnaBridge	167:e84263d55307	778	pData += sizeof(uint8_t);
<>	144:ef7eb2e8f9f7	779	hspi->RxXferCount--;
<>	144:ef7eb2e8f9f7	780	}
<>	144:ef7eb2e8f9f7	781	else
<>	144:ef7eb2e8f9f7	782	{
<>	144:ef7eb2e8f9f7	783	/* Timeout management */
AnnaBridge	167:e84263d55307	784	if ((Timeout == 0U) \|\| ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick() - tickstart) >= Timeout)))
<>	144:ef7eb2e8f9f7	785	{
<>	144:ef7eb2e8f9f7	786	errorcode = HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	787	goto error;
<>	144:ef7eb2e8f9f7	788	}
<>	144:ef7eb2e8f9f7	789	}
<>	144:ef7eb2e8f9f7	790	}
<>	144:ef7eb2e8f9f7	791	}
<>	144:ef7eb2e8f9f7	792	else
<>	144:ef7eb2e8f9f7	793	{
<>	144:ef7eb2e8f9f7	794	/* Transfer loop */
AnnaBridge	167:e84263d55307	795	while (hspi->RxXferCount > 0U)
<>	144:ef7eb2e8f9f7	796	{
<>	144:ef7eb2e8f9f7	797	/* Check the RXNE flag */
AnnaBridge	167:e84263d55307	798	if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE))
<>	144:ef7eb2e8f9f7	799	{
AnnaBridge	167:e84263d55307	800	((uint16_t )pData) = hspi->Instance->DR;
AnnaBridge	167:e84263d55307	801	pData += sizeof(uint16_t);
<>	144:ef7eb2e8f9f7	802	hspi->RxXferCount--;
<>	144:ef7eb2e8f9f7	803	}
<>	144:ef7eb2e8f9f7	804	else
<>	144:ef7eb2e8f9f7	805	{
<>	144:ef7eb2e8f9f7	806	/* Timeout management */
AnnaBridge	167:e84263d55307	807	if ((Timeout == 0U) \|\| ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick() - tickstart) >= Timeout)))
<>	144:ef7eb2e8f9f7	808	{
<>	144:ef7eb2e8f9f7	809	errorcode = HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	810	goto error;
<>	144:ef7eb2e8f9f7	811	}
<>	144:ef7eb2e8f9f7	812	}
<>	144:ef7eb2e8f9f7	813	}
<>	144:ef7eb2e8f9f7	814	}
<>	144:ef7eb2e8f9f7	815
AnnaBridge	167:e84263d55307	816	#if (USE_SPI_CRC != 0U)
<>	144:ef7eb2e8f9f7	817	/* Handle the CRC Transmission */
AnnaBridge	167:e84263d55307	818	if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<>	144:ef7eb2e8f9f7	819	{
<>	144:ef7eb2e8f9f7	820	/* freeze the CRC before the latest data */
AnnaBridge	167:e84263d55307	821	SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
<>	144:ef7eb2e8f9f7	822
<>	144:ef7eb2e8f9f7	823	/* Read the latest data */
AnnaBridge	167:e84263d55307	824	if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	825	{
<>	144:ef7eb2e8f9f7	826	/* the latest data has not been received */
<>	144:ef7eb2e8f9f7	827	errorcode = HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	828	goto error;
<>	144:ef7eb2e8f9f7	829	}
<>	144:ef7eb2e8f9f7	830
<>	144:ef7eb2e8f9f7	831	/* Receive last data in 16 Bit mode */
AnnaBridge	167:e84263d55307	832	if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
<>	144:ef7eb2e8f9f7	833	{
AnnaBridge	167:e84263d55307	834	((uint16_t )pData) = hspi->Instance->DR;
<>	144:ef7eb2e8f9f7	835	}
<>	144:ef7eb2e8f9f7	836	/* Receive last data in 8 Bit mode */
<>	144:ef7eb2e8f9f7	837	else
<>	144:ef7eb2e8f9f7	838	{
AnnaBridge	167:e84263d55307	839	((uint8_t )pData) = (__IO uint8_t )&hspi->Instance->DR;
<>	144:ef7eb2e8f9f7	840	}
<>	144:ef7eb2e8f9f7	841
AnnaBridge	167:e84263d55307	842	/* Wait the CRC data */
AnnaBridge	167:e84263d55307	843	if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	844	{
AnnaBridge	167:e84263d55307	845	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
<>	144:ef7eb2e8f9f7	846	errorcode = HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	847	goto error;
<>	144:ef7eb2e8f9f7	848	}
<>	144:ef7eb2e8f9f7	849
AnnaBridge	167:e84263d55307	850	/* Read CRC to Flush DR and RXNE flag */
AnnaBridge	167:e84263d55307	851	if (hspi->Init.DataSize == SPI_DATASIZE_16BIT)
<>	144:ef7eb2e8f9f7	852	{
<>	144:ef7eb2e8f9f7	853	tmpreg = hspi->Instance->DR;
AnnaBridge	167:e84263d55307	854	/* To avoid GCC warning */
AnnaBridge	167:e84263d55307	855	UNUSED(tmpreg);
<>	144:ef7eb2e8f9f7	856	}
<>	144:ef7eb2e8f9f7	857	else
<>	144:ef7eb2e8f9f7	858	{
<>	144:ef7eb2e8f9f7	859	tmpreg = (__IO uint8_t )&hspi->Instance->DR;
AnnaBridge	167:e84263d55307	860	/* To avoid GCC warning */
AnnaBridge	167:e84263d55307	861	UNUSED(tmpreg);
AnnaBridge	167:e84263d55307	862
AnnaBridge	167:e84263d55307	863	if ((hspi->Init.DataSize == SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))
<>	144:ef7eb2e8f9f7	864	{
AnnaBridge	167:e84263d55307	865	if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	866	{
<>	144:ef7eb2e8f9f7	867	/* Error on the CRC reception */
AnnaBridge	167:e84263d55307	868	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
<>	144:ef7eb2e8f9f7	869	errorcode = HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	870	goto error;
<>	144:ef7eb2e8f9f7	871	}
<>	144:ef7eb2e8f9f7	872	tmpreg = (__IO uint8_t )&hspi->Instance->DR;
AnnaBridge	167:e84263d55307	873	/* To avoid GCC warning */
AnnaBridge	167:e84263d55307	874	UNUSED(tmpreg);
<>	144:ef7eb2e8f9f7	875	}
<>	144:ef7eb2e8f9f7	876	}
<>	144:ef7eb2e8f9f7	877	}
AnnaBridge	167:e84263d55307	878	#endif /* USE_SPI_CRC */
AnnaBridge	167:e84263d55307	879
<>	144:ef7eb2e8f9f7	880	/* Check the end of the transaction */
AnnaBridge	167:e84263d55307	881	if (SPI_EndRxTransaction(hspi, Timeout, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	882	{
<>	144:ef7eb2e8f9f7	883	hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
<>	144:ef7eb2e8f9f7	884	}
<>	144:ef7eb2e8f9f7	885
AnnaBridge	167:e84263d55307	886	#if (USE_SPI_CRC != 0U)
<>	144:ef7eb2e8f9f7	887	/* Check if CRC error occurred */
AnnaBridge	167:e84263d55307	888	if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))
<>	144:ef7eb2e8f9f7	889	{
AnnaBridge	167:e84263d55307	890	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
<>	144:ef7eb2e8f9f7	891	__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
<>	144:ef7eb2e8f9f7	892	}
AnnaBridge	167:e84263d55307	893	#endif /* USE_SPI_CRC */
AnnaBridge	167:e84263d55307	894
AnnaBridge	167:e84263d55307	895	if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
<>	144:ef7eb2e8f9f7	896	{
<>	144:ef7eb2e8f9f7	897	errorcode = HAL_ERROR;
<>	144:ef7eb2e8f9f7	898	}
<>	144:ef7eb2e8f9f7	899
<>	144:ef7eb2e8f9f7	900	error :
<>	144:ef7eb2e8f9f7	901	hspi->State = HAL_SPI_STATE_READY;
<>	144:ef7eb2e8f9f7	902	__HAL_UNLOCK(hspi);
<>	144:ef7eb2e8f9f7	903	return errorcode;
<>	144:ef7eb2e8f9f7	904	}
<>	144:ef7eb2e8f9f7	905
<>	144:ef7eb2e8f9f7	906	/**
<>	144:ef7eb2e8f9f7	907	* @brief Transmit and Receive an amount of data in blocking mode.
AnnaBridge	181:57724642e740	908	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	909	* the configuration information for SPI module.
AnnaBridge	181:57724642e740	910	* @param pTxData pointer to transmission data buffer
AnnaBridge	181:57724642e740	911	* @param pRxData pointer to reception data buffer
AnnaBridge	181:57724642e740	912	* @param Size amount of data to be sent and received
AnnaBridge	181:57724642e740	913	* @param Timeout Timeout duration
<>	144:ef7eb2e8f9f7	914	* @retval HAL status
<>	144:ef7eb2e8f9f7	915	*/
AnnaBridge	167:e84263d55307	916	HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef hspi, uint8_t pTxData, uint8_t *pRxData, uint16_t Size,
AnnaBridge	167:e84263d55307	917	uint32_t Timeout)
<>	144:ef7eb2e8f9f7	918	{
AnnaBridge	167:e84263d55307	919	uint32_t tmp = 0U, tmp1 = 0U;
AnnaBridge	167:e84263d55307	920	#if (USE_SPI_CRC != 0U)
AnnaBridge	167:e84263d55307	921	__IO uint16_t tmpreg = 0U;
AnnaBridge	167:e84263d55307	922	#endif /* USE_SPI_CRC */
AnnaBridge	167:e84263d55307	923	uint32_t tickstart = 0U;
AnnaBridge	167:e84263d55307	924	/* Variable used to alternate Rx and Tx during transfer */
AnnaBridge	167:e84263d55307	925	uint32_t txallowed = 1U;
<>	144:ef7eb2e8f9f7	926	HAL_StatusTypeDef errorcode = HAL_OK;
AnnaBridge	167:e84263d55307	927
AnnaBridge	167:e84263d55307	928	/* Check Direction parameter */
<>	144:ef7eb2e8f9f7	929	assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
<>	144:ef7eb2e8f9f7	930
<>	144:ef7eb2e8f9f7	931	/* Process Locked */
<>	144:ef7eb2e8f9f7	932	__HAL_LOCK(hspi);
<>	144:ef7eb2e8f9f7	933
AnnaBridge	167:e84263d55307	934	/* Init tickstart for timeout management*/
AnnaBridge	167:e84263d55307	935	tickstart = HAL_GetTick();
AnnaBridge	167:e84263d55307	936
AnnaBridge	167:e84263d55307	937	tmp = hspi->State;
AnnaBridge	167:e84263d55307	938	tmp1 = hspi->Init.Mode;
AnnaBridge	167:e84263d55307	939
AnnaBridge	167:e84263d55307	940	if (!((tmp == HAL_SPI_STATE_READY) \|\| \
AnnaBridge	167:e84263d55307	941	((tmp1 == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp == HAL_SPI_STATE_BUSY_RX))))
<>	144:ef7eb2e8f9f7	942	{
<>	144:ef7eb2e8f9f7	943	errorcode = HAL_BUSY;
<>	144:ef7eb2e8f9f7	944	goto error;
<>	144:ef7eb2e8f9f7	945	}
<>	144:ef7eb2e8f9f7	946
AnnaBridge	167:e84263d55307	947	if ((pTxData == NULL) \|\| (pRxData == NULL) \|\| (Size == 0U))
<>	144:ef7eb2e8f9f7	948	{
<>	144:ef7eb2e8f9f7	949	errorcode = HAL_ERROR;
<>	144:ef7eb2e8f9f7	950	goto error;
<>	144:ef7eb2e8f9f7	951	}
<>	144:ef7eb2e8f9f7	952
AnnaBridge	167:e84263d55307	953	/* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
AnnaBridge	167:e84263d55307	954	if (hspi->State != HAL_SPI_STATE_BUSY_RX)
AnnaBridge	167:e84263d55307	955	{
AnnaBridge	167:e84263d55307	956	hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
AnnaBridge	167:e84263d55307	957	}
AnnaBridge	167:e84263d55307	958
AnnaBridge	167:e84263d55307	959	/* Set the transaction information */
<>	144:ef7eb2e8f9f7	960	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
AnnaBridge	167:e84263d55307	961	hspi->pRxBuffPtr = (uint8_t *)pRxData;
<>	144:ef7eb2e8f9f7	962	hspi->RxXferCount = Size;
<>	144:ef7eb2e8f9f7	963	hspi->RxXferSize = Size;
AnnaBridge	167:e84263d55307	964	hspi->pTxBuffPtr = (uint8_t *)pTxData;
<>	144:ef7eb2e8f9f7	965	hspi->TxXferCount = Size;
<>	144:ef7eb2e8f9f7	966	hspi->TxXferSize = Size;
<>	144:ef7eb2e8f9f7	967
AnnaBridge	167:e84263d55307	968	/Init field not used in handle to zero /
AnnaBridge	167:e84263d55307	969	hspi->RxISR = NULL;
AnnaBridge	167:e84263d55307	970	hspi->TxISR = NULL;
AnnaBridge	167:e84263d55307	971
AnnaBridge	167:e84263d55307	972	#if (USE_SPI_CRC != 0U)
<>	144:ef7eb2e8f9f7	973	/* Reset CRC Calculation */
AnnaBridge	167:e84263d55307	974	if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<>	144:ef7eb2e8f9f7	975	{
<>	144:ef7eb2e8f9f7	976	SPI_RESET_CRC(hspi);
<>	144:ef7eb2e8f9f7	977	}
AnnaBridge	167:e84263d55307	978	#endif /* USE_SPI_CRC */
AnnaBridge	167:e84263d55307	979
AnnaBridge	167:e84263d55307	980	/* Set the Rx Fifo threshold */
AnnaBridge	167:e84263d55307	981	if ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) \|\| (hspi->RxXferCount > 1U))
<>	144:ef7eb2e8f9f7	982	{
AnnaBridge	181:57724642e740	983	/* Set fiforxthreshold according the reception data length: 16bit */
<>	144:ef7eb2e8f9f7	984	CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
<>	144:ef7eb2e8f9f7	985	}
<>	144:ef7eb2e8f9f7	986	else
<>	144:ef7eb2e8f9f7	987	{
AnnaBridge	181:57724642e740	988	/* Set fiforxthreshold according the reception data length: 8bit */
<>	144:ef7eb2e8f9f7	989	SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
<>	144:ef7eb2e8f9f7	990	}
<>	144:ef7eb2e8f9f7	991
<>	144:ef7eb2e8f9f7	992	/* Check if the SPI is already enabled */
AnnaBridge	167:e84263d55307	993	if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
<>	144:ef7eb2e8f9f7	994	{
<>	144:ef7eb2e8f9f7	995	/* Enable SPI peripheral */
<>	144:ef7eb2e8f9f7	996	__HAL_SPI_ENABLE(hspi);
<>	144:ef7eb2e8f9f7	997	}
<>	144:ef7eb2e8f9f7	998
<>	144:ef7eb2e8f9f7	999	/* Transmit and Receive data in 16 Bit mode */
AnnaBridge	167:e84263d55307	1000	if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
<>	144:ef7eb2e8f9f7	1001	{
AnnaBridge	167:e84263d55307	1002	if ((hspi->Init.Mode == SPI_MODE_SLAVE) \|\| (hspi->TxXferCount == 0x01U))
AnnaBridge	167:e84263d55307	1003	{
AnnaBridge	167:e84263d55307	1004	hspi->Instance->DR = ((uint16_t )pTxData);
AnnaBridge	167:e84263d55307	1005	pTxData += sizeof(uint16_t);
AnnaBridge	167:e84263d55307	1006	hspi->TxXferCount--;
AnnaBridge	167:e84263d55307	1007	}
AnnaBridge	167:e84263d55307	1008	while ((hspi->TxXferCount > 0U) \|\| (hspi->RxXferCount > 0U))
<>	144:ef7eb2e8f9f7	1009	{
<>	144:ef7eb2e8f9f7	1010	/* Check TXE flag */
AnnaBridge	167:e84263d55307	1011	if (txallowed && (hspi->TxXferCount > 0U) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)))
<>	144:ef7eb2e8f9f7	1012	{
AnnaBridge	167:e84263d55307	1013	hspi->Instance->DR = ((uint16_t )pTxData);
AnnaBridge	167:e84263d55307	1014	pTxData += sizeof(uint16_t);
<>	144:ef7eb2e8f9f7	1015	hspi->TxXferCount--;
AnnaBridge	167:e84263d55307	1016	/* Next Data is a reception (Rx). Tx not allowed */
AnnaBridge	167:e84263d55307	1017	txallowed = 0U;
AnnaBridge	167:e84263d55307	1018
AnnaBridge	167:e84263d55307	1019	#if (USE_SPI_CRC != 0U)
<>	144:ef7eb2e8f9f7	1020	/* Enable CRC Transmission */
AnnaBridge	167:e84263d55307	1021	if ((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
<>	144:ef7eb2e8f9f7	1022	{
AnnaBridge	167:e84263d55307	1023	/* Set NSS Soft to received correctly the CRC on slave mode with NSS pulse activated */
AnnaBridge	167:e84263d55307	1024	if (((hspi->Instance->CR1 & SPI_CR1_MSTR) == 0U) && ((hspi->Instance->CR2 & SPI_CR2_NSSP) == SPI_CR2_NSSP))
AnnaBridge	167:e84263d55307	1025	{
AnnaBridge	167:e84263d55307	1026	SET_BIT(hspi->Instance->CR1, SPI_CR1_SSM);
AnnaBridge	167:e84263d55307	1027	}
AnnaBridge	167:e84263d55307	1028	SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
<>	144:ef7eb2e8f9f7	1029	}
AnnaBridge	167:e84263d55307	1030	#endif /* USE_SPI_CRC */
<>	144:ef7eb2e8f9f7	1031	}
<>	144:ef7eb2e8f9f7	1032
<>	144:ef7eb2e8f9f7	1033	/* Check RXNE flag */
AnnaBridge	167:e84263d55307	1034	if ((hspi->RxXferCount > 0U) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)))
<>	144:ef7eb2e8f9f7	1035	{
AnnaBridge	167:e84263d55307	1036	((uint16_t )pRxData) = hspi->Instance->DR;
AnnaBridge	167:e84263d55307	1037	pRxData += sizeof(uint16_t);
<>	144:ef7eb2e8f9f7	1038	hspi->RxXferCount--;
AnnaBridge	167:e84263d55307	1039	/* Next Data is a Transmission (Tx). Tx is allowed */
AnnaBridge	167:e84263d55307	1040	txallowed = 1U;
<>	144:ef7eb2e8f9f7	1041	}
AnnaBridge	167:e84263d55307	1042	if ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick() - tickstart) >= Timeout))
<>	144:ef7eb2e8f9f7	1043	{
<>	144:ef7eb2e8f9f7	1044	errorcode = HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	1045	goto error;
<>	144:ef7eb2e8f9f7	1046	}
<>	144:ef7eb2e8f9f7	1047	}
<>	144:ef7eb2e8f9f7	1048	}
<>	144:ef7eb2e8f9f7	1049	/* Transmit and Receive data in 8 Bit mode */
<>	144:ef7eb2e8f9f7	1050	else
<>	144:ef7eb2e8f9f7	1051	{
AnnaBridge	167:e84263d55307	1052	if ((hspi->Init.Mode == SPI_MODE_SLAVE) \|\| (hspi->TxXferCount == 0x01U))
AnnaBridge	167:e84263d55307	1053	{
AnnaBridge	167:e84263d55307	1054	if (hspi->TxXferCount > 1U)
AnnaBridge	167:e84263d55307	1055	{
AnnaBridge	167:e84263d55307	1056	hspi->Instance->DR = ((uint16_t )pTxData);
AnnaBridge	167:e84263d55307	1057	pTxData += sizeof(uint16_t);
AnnaBridge	167:e84263d55307	1058	hspi->TxXferCount -= 2U;
AnnaBridge	167:e84263d55307	1059	}
AnnaBridge	167:e84263d55307	1060	else
AnnaBridge	167:e84263d55307	1061	{
AnnaBridge	167:e84263d55307	1062	(__IO uint8_t )&hspi->Instance->DR = (*pTxData++);
AnnaBridge	167:e84263d55307	1063	hspi->TxXferCount--;
AnnaBridge	167:e84263d55307	1064	}
AnnaBridge	167:e84263d55307	1065	}
AnnaBridge	167:e84263d55307	1066	while ((hspi->TxXferCount > 0U) \|\| (hspi->RxXferCount > 0U))
<>	144:ef7eb2e8f9f7	1067	{
AnnaBridge	181:57724642e740	1068	/* Check TXE flag */
AnnaBridge	167:e84263d55307	1069	if (txallowed && (hspi->TxXferCount > 0U) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)))
<>	144:ef7eb2e8f9f7	1070	{
AnnaBridge	167:e84263d55307	1071	if (hspi->TxXferCount > 1U)
<>	144:ef7eb2e8f9f7	1072	{
AnnaBridge	167:e84263d55307	1073	hspi->Instance->DR = ((uint16_t )pTxData);
AnnaBridge	167:e84263d55307	1074	pTxData += sizeof(uint16_t);
AnnaBridge	167:e84263d55307	1075	hspi->TxXferCount -= 2U;
<>	144:ef7eb2e8f9f7	1076	}
<>	144:ef7eb2e8f9f7	1077	else
<>	144:ef7eb2e8f9f7	1078	{
AnnaBridge	167:e84263d55307	1079	(__IO uint8_t )&hspi->Instance->DR = (*pTxData++);
<>	144:ef7eb2e8f9f7	1080	hspi->TxXferCount--;
<>	144:ef7eb2e8f9f7	1081	}
AnnaBridge	167:e84263d55307	1082	/* Next Data is a reception (Rx). Tx not allowed */
AnnaBridge	167:e84263d55307	1083	txallowed = 0U;
AnnaBridge	167:e84263d55307	1084
AnnaBridge	167:e84263d55307	1085	#if (USE_SPI_CRC != 0U)
<>	144:ef7eb2e8f9f7	1086	/* Enable CRC Transmission */
AnnaBridge	167:e84263d55307	1087	if ((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
<>	144:ef7eb2e8f9f7	1088	{
AnnaBridge	167:e84263d55307	1089	/* Set NSS Soft to received correctly the CRC on slave mode with NSS pulse activated */
AnnaBridge	167:e84263d55307	1090	if (((hspi->Instance->CR1 & SPI_CR1_MSTR) == 0U) && ((hspi->Instance->CR2 & SPI_CR2_NSSP) == SPI_CR2_NSSP))
AnnaBridge	167:e84263d55307	1091	{
AnnaBridge	167:e84263d55307	1092	SET_BIT(hspi->Instance->CR1, SPI_CR1_SSM);
AnnaBridge	167:e84263d55307	1093	}
AnnaBridge	167:e84263d55307	1094	SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
<>	144:ef7eb2e8f9f7	1095	}
AnnaBridge	167:e84263d55307	1096	#endif /* USE_SPI_CRC */
<>	144:ef7eb2e8f9f7	1097	}
<>	144:ef7eb2e8f9f7	1098
<>	144:ef7eb2e8f9f7	1099	/* Wait until RXNE flag is reset */
AnnaBridge	167:e84263d55307	1100	if ((hspi->RxXferCount > 0U) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)))
<>	144:ef7eb2e8f9f7	1101	{
AnnaBridge	167:e84263d55307	1102	if (hspi->RxXferCount > 1U)
<>	144:ef7eb2e8f9f7	1103	{
AnnaBridge	167:e84263d55307	1104	((uint16_t )pRxData) = hspi->Instance->DR;
AnnaBridge	167:e84263d55307	1105	pRxData += sizeof(uint16_t);
AnnaBridge	167:e84263d55307	1106	hspi->RxXferCount -= 2U;
AnnaBridge	167:e84263d55307	1107	if (hspi->RxXferCount <= 1U)
<>	144:ef7eb2e8f9f7	1108	{
AnnaBridge	181:57724642e740	1109	/* Set RX Fifo threshold before to switch on 8 bit data size */
<>	144:ef7eb2e8f9f7	1110	SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
<>	144:ef7eb2e8f9f7	1111	}
<>	144:ef7eb2e8f9f7	1112	}
<>	144:ef7eb2e8f9f7	1113	else
<>	144:ef7eb2e8f9f7	1114	{
AnnaBridge	167:e84263d55307	1115	((uint8_t )pRxData++) = (__IO uint8_t )&hspi->Instance->DR;
<>	144:ef7eb2e8f9f7	1116	hspi->RxXferCount--;
<>	144:ef7eb2e8f9f7	1117	}
AnnaBridge	167:e84263d55307	1118	/* Next Data is a Transmission (Tx). Tx is allowed */
AnnaBridge	167:e84263d55307	1119	txallowed = 1U;
<>	144:ef7eb2e8f9f7	1120	}
AnnaBridge	167:e84263d55307	1121	if ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick() - tickstart) >= Timeout))
<>	144:ef7eb2e8f9f7	1122	{
<>	144:ef7eb2e8f9f7	1123	errorcode = HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	1124	goto error;
<>	144:ef7eb2e8f9f7	1125	}
<>	144:ef7eb2e8f9f7	1126	}
<>	144:ef7eb2e8f9f7	1127	}
<>	144:ef7eb2e8f9f7	1128
AnnaBridge	167:e84263d55307	1129	#if (USE_SPI_CRC != 0U)
<>	144:ef7eb2e8f9f7	1130	/* Read CRC from DR to close CRC calculation process */
AnnaBridge	167:e84263d55307	1131	if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<>	144:ef7eb2e8f9f7	1132	{
<>	144:ef7eb2e8f9f7	1133	/* Wait until TXE flag */
AnnaBridge	167:e84263d55307	1134	if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	1135	{
<>	144:ef7eb2e8f9f7	1136	/* Error on the CRC reception */
AnnaBridge	167:e84263d55307	1137	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
<>	144:ef7eb2e8f9f7	1138	errorcode = HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	1139	goto error;
<>	144:ef7eb2e8f9f7	1140	}
AnnaBridge	167:e84263d55307	1141	/* Read CRC */
AnnaBridge	167:e84263d55307	1142	if (hspi->Init.DataSize == SPI_DATASIZE_16BIT)
<>	144:ef7eb2e8f9f7	1143	{
<>	144:ef7eb2e8f9f7	1144	tmpreg = hspi->Instance->DR;
AnnaBridge	167:e84263d55307	1145	/* To avoid GCC warning */
AnnaBridge	167:e84263d55307	1146	UNUSED(tmpreg);
<>	144:ef7eb2e8f9f7	1147	}
<>	144:ef7eb2e8f9f7	1148	else
<>	144:ef7eb2e8f9f7	1149	{
<>	144:ef7eb2e8f9f7	1150	tmpreg = (__IO uint8_t )&hspi->Instance->DR;
AnnaBridge	167:e84263d55307	1151	/* To avoid GCC warning */
AnnaBridge	167:e84263d55307	1152	UNUSED(tmpreg);
AnnaBridge	167:e84263d55307	1153
AnnaBridge	167:e84263d55307	1154	if (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)
<>	144:ef7eb2e8f9f7	1155	{
AnnaBridge	167:e84263d55307	1156	if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	1157	{
<>	144:ef7eb2e8f9f7	1158	/* Error on the CRC reception */
AnnaBridge	167:e84263d55307	1159	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
<>	144:ef7eb2e8f9f7	1160	errorcode = HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	1161	goto error;
<>	144:ef7eb2e8f9f7	1162	}
<>	144:ef7eb2e8f9f7	1163	tmpreg = (__IO uint8_t )&hspi->Instance->DR;
AnnaBridge	167:e84263d55307	1164	/* To avoid GCC warning */
AnnaBridge	167:e84263d55307	1165	UNUSED(tmpreg);
<>	144:ef7eb2e8f9f7	1166	}
<>	144:ef7eb2e8f9f7	1167	}
<>	144:ef7eb2e8f9f7	1168	}
<>	144:ef7eb2e8f9f7	1169
<>	144:ef7eb2e8f9f7	1170	/* Check if CRC error occurred */
AnnaBridge	167:e84263d55307	1171	if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))
<>	144:ef7eb2e8f9f7	1172	{
AnnaBridge	167:e84263d55307	1173	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
<>	144:ef7eb2e8f9f7	1174	/* Clear CRC Flag */
<>	144:ef7eb2e8f9f7	1175	__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
<>	144:ef7eb2e8f9f7	1176
<>	144:ef7eb2e8f9f7	1177	errorcode = HAL_ERROR;
<>	144:ef7eb2e8f9f7	1178	}
AnnaBridge	167:e84263d55307	1179	#endif /* USE_SPI_CRC */
<>	144:ef7eb2e8f9f7	1180
<>	144:ef7eb2e8f9f7	1181	/* Check the end of the transaction */
AnnaBridge	167:e84263d55307	1182	if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	1183	{
AnnaBridge	181:57724642e740	1184	errorcode = HAL_ERROR;
<>	144:ef7eb2e8f9f7	1185	hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
<>	144:ef7eb2e8f9f7	1186	}
<>	144:ef7eb2e8f9f7	1187
<>	144:ef7eb2e8f9f7	1188	error :
<>	144:ef7eb2e8f9f7	1189	hspi->State = HAL_SPI_STATE_READY;
<>	144:ef7eb2e8f9f7	1190	__HAL_UNLOCK(hspi);
<>	144:ef7eb2e8f9f7	1191	return errorcode;
<>	144:ef7eb2e8f9f7	1192	}
<>	144:ef7eb2e8f9f7	1193
<>	144:ef7eb2e8f9f7	1194	/**
<>	144:ef7eb2e8f9f7	1195	* @brief Transmit an amount of data in non-blocking mode with Interrupt.
AnnaBridge	181:57724642e740	1196	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	1197	* the configuration information for SPI module.
AnnaBridge	181:57724642e740	1198	* @param pData pointer to data buffer
AnnaBridge	181:57724642e740	1199	* @param Size amount of data to be sent
<>	144:ef7eb2e8f9f7	1200	* @retval HAL status
<>	144:ef7eb2e8f9f7	1201	*/
<>	144:ef7eb2e8f9f7	1202	HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size)
<>	144:ef7eb2e8f9f7	1203	{
<>	144:ef7eb2e8f9f7	1204	HAL_StatusTypeDef errorcode = HAL_OK;
AnnaBridge	167:e84263d55307	1205
AnnaBridge	167:e84263d55307	1206	/* Check Direction parameter */
<>	144:ef7eb2e8f9f7	1207	assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
<>	144:ef7eb2e8f9f7	1208
<>	144:ef7eb2e8f9f7	1209	/* Process Locked */
<>	144:ef7eb2e8f9f7	1210	__HAL_LOCK(hspi);
<>	144:ef7eb2e8f9f7	1211
AnnaBridge	167:e84263d55307	1212	if ((pData == NULL) \|\| (Size == 0U))
<>	144:ef7eb2e8f9f7	1213	{
<>	144:ef7eb2e8f9f7	1214	errorcode = HAL_ERROR;
<>	144:ef7eb2e8f9f7	1215	goto error;
<>	144:ef7eb2e8f9f7	1216	}
<>	144:ef7eb2e8f9f7	1217
AnnaBridge	167:e84263d55307	1218	if (hspi->State != HAL_SPI_STATE_READY)
<>	144:ef7eb2e8f9f7	1219	{
<>	144:ef7eb2e8f9f7	1220	errorcode = HAL_BUSY;
<>	144:ef7eb2e8f9f7	1221	goto error;
<>	144:ef7eb2e8f9f7	1222	}
<>	144:ef7eb2e8f9f7	1223
AnnaBridge	167:e84263d55307	1224	/* Set the transaction information */
<>	144:ef7eb2e8f9f7	1225	hspi->State = HAL_SPI_STATE_BUSY_TX;
<>	144:ef7eb2e8f9f7	1226	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
AnnaBridge	167:e84263d55307	1227	hspi->pTxBuffPtr = (uint8_t *)pData;
<>	144:ef7eb2e8f9f7	1228	hspi->TxXferSize = Size;
<>	144:ef7eb2e8f9f7	1229	hspi->TxXferCount = Size;
AnnaBridge	167:e84263d55307	1230
AnnaBridge	167:e84263d55307	1231	/* Init field not used in handle to zero */
<>	144:ef7eb2e8f9f7	1232	hspi->pRxBuffPtr = (uint8_t *)NULL;
AnnaBridge	167:e84263d55307	1233	hspi->RxXferSize = 0U;
AnnaBridge	167:e84263d55307	1234	hspi->RxXferCount = 0U;
AnnaBridge	167:e84263d55307	1235	hspi->RxISR = NULL;
<>	144:ef7eb2e8f9f7	1236
<>	144:ef7eb2e8f9f7	1237	/* Set the function for IT treatment */
AnnaBridge	167:e84263d55307	1238	if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
<>	144:ef7eb2e8f9f7	1239	{
<>	144:ef7eb2e8f9f7	1240	hspi->TxISR = SPI_TxISR_16BIT;
<>	144:ef7eb2e8f9f7	1241	}
<>	144:ef7eb2e8f9f7	1242	else
<>	144:ef7eb2e8f9f7	1243	{
<>	144:ef7eb2e8f9f7	1244	hspi->TxISR = SPI_TxISR_8BIT;
<>	144:ef7eb2e8f9f7	1245	}
<>	144:ef7eb2e8f9f7	1246
<>	144:ef7eb2e8f9f7	1247	/* Configure communication direction : 1Line */
AnnaBridge	167:e84263d55307	1248	if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
<>	144:ef7eb2e8f9f7	1249	{
<>	144:ef7eb2e8f9f7	1250	SPI_1LINE_TX(hspi);
<>	144:ef7eb2e8f9f7	1251	}
<>	144:ef7eb2e8f9f7	1252
AnnaBridge	167:e84263d55307	1253	#if (USE_SPI_CRC != 0U)
<>	144:ef7eb2e8f9f7	1254	/* Reset CRC Calculation */
AnnaBridge	167:e84263d55307	1255	if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<>	144:ef7eb2e8f9f7	1256	{
<>	144:ef7eb2e8f9f7	1257	SPI_RESET_CRC(hspi);
<>	144:ef7eb2e8f9f7	1258	}
AnnaBridge	167:e84263d55307	1259	#endif /* USE_SPI_CRC */
<>	144:ef7eb2e8f9f7	1260
<>	144:ef7eb2e8f9f7	1261	/* Enable TXE and ERR interrupt */
AnnaBridge	167:e84263d55307	1262	__HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE \| SPI_IT_ERR));
<>	144:ef7eb2e8f9f7	1263
<>	144:ef7eb2e8f9f7	1264
<>	144:ef7eb2e8f9f7	1265	/* Check if the SPI is already enabled */
AnnaBridge	167:e84263d55307	1266	if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
<>	144:ef7eb2e8f9f7	1267	{
<>	144:ef7eb2e8f9f7	1268	/* Enable SPI peripheral */
<>	144:ef7eb2e8f9f7	1269	__HAL_SPI_ENABLE(hspi);
<>	144:ef7eb2e8f9f7	1270	}
<>	144:ef7eb2e8f9f7	1271
<>	144:ef7eb2e8f9f7	1272	error :
<>	144:ef7eb2e8f9f7	1273	__HAL_UNLOCK(hspi);
<>	144:ef7eb2e8f9f7	1274	return errorcode;
<>	144:ef7eb2e8f9f7	1275	}
<>	144:ef7eb2e8f9f7	1276
<>	144:ef7eb2e8f9f7	1277	/**
<>	144:ef7eb2e8f9f7	1278	* @brief Receive an amount of data in non-blocking mode with Interrupt.
AnnaBridge	181:57724642e740	1279	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	1280	* the configuration information for SPI module.
AnnaBridge	181:57724642e740	1281	* @param pData pointer to data buffer
AnnaBridge	181:57724642e740	1282	* @param Size amount of data to be sent
<>	144:ef7eb2e8f9f7	1283	* @retval HAL status
<>	144:ef7eb2e8f9f7	1284	*/
<>	144:ef7eb2e8f9f7	1285	HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size)
<>	144:ef7eb2e8f9f7	1286	{
<>	144:ef7eb2e8f9f7	1287	HAL_StatusTypeDef errorcode = HAL_OK;
AnnaBridge	167:e84263d55307	1288
AnnaBridge	167:e84263d55307	1289	if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
AnnaBridge	167:e84263d55307	1290	{
AnnaBridge	167:e84263d55307	1291	hspi->State = HAL_SPI_STATE_BUSY_RX;
AnnaBridge	167:e84263d55307	1292	/* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
AnnaBridge	167:e84263d55307	1293	return HAL_SPI_TransmitReceive_IT(hspi, pData, pData, Size);
AnnaBridge	167:e84263d55307	1294	}
<>	144:ef7eb2e8f9f7	1295
<>	144:ef7eb2e8f9f7	1296	/* Process Locked */
<>	144:ef7eb2e8f9f7	1297	__HAL_LOCK(hspi);
<>	144:ef7eb2e8f9f7	1298
AnnaBridge	167:e84263d55307	1299	if (hspi->State != HAL_SPI_STATE_READY)
<>	144:ef7eb2e8f9f7	1300	{
<>	144:ef7eb2e8f9f7	1301	errorcode = HAL_BUSY;
<>	144:ef7eb2e8f9f7	1302	goto error;
<>	144:ef7eb2e8f9f7	1303	}
AnnaBridge	167:e84263d55307	1304
AnnaBridge	167:e84263d55307	1305	if ((pData == NULL) \|\| (Size == 0U))
<>	144:ef7eb2e8f9f7	1306	{
<>	144:ef7eb2e8f9f7	1307	errorcode = HAL_ERROR;
<>	144:ef7eb2e8f9f7	1308	goto error;
<>	144:ef7eb2e8f9f7	1309	}
<>	144:ef7eb2e8f9f7	1310
AnnaBridge	167:e84263d55307	1311	/* Set the transaction information */
<>	144:ef7eb2e8f9f7	1312	hspi->State = HAL_SPI_STATE_BUSY_RX;
<>	144:ef7eb2e8f9f7	1313	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
AnnaBridge	167:e84263d55307	1314	hspi->pRxBuffPtr = (uint8_t *)pData;
<>	144:ef7eb2e8f9f7	1315	hspi->RxXferSize = Size;
<>	144:ef7eb2e8f9f7	1316	hspi->RxXferCount = Size;
AnnaBridge	167:e84263d55307	1317
AnnaBridge	167:e84263d55307	1318	/* Init field not used in handle to zero */
<>	144:ef7eb2e8f9f7	1319	hspi->pTxBuffPtr = (uint8_t *)NULL;
AnnaBridge	167:e84263d55307	1320	hspi->TxXferSize = 0U;
AnnaBridge	167:e84263d55307	1321	hspi->TxXferCount = 0U;
AnnaBridge	167:e84263d55307	1322	hspi->TxISR = NULL;
AnnaBridge	167:e84263d55307	1323
AnnaBridge	167:e84263d55307	1324	/* Check the data size to adapt Rx threshold and the set the function for IT treatment */
AnnaBridge	167:e84263d55307	1325	if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
<>	144:ef7eb2e8f9f7	1326	{
AnnaBridge	181:57724642e740	1327	/* Set RX Fifo threshold according the reception data length: 16 bit */
<>	144:ef7eb2e8f9f7	1328	CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
<>	144:ef7eb2e8f9f7	1329	hspi->RxISR = SPI_RxISR_16BIT;
<>	144:ef7eb2e8f9f7	1330	}
<>	144:ef7eb2e8f9f7	1331	else
<>	144:ef7eb2e8f9f7	1332	{
AnnaBridge	181:57724642e740	1333	/* Set RX Fifo threshold according the reception data length: 8 bit */
<>	144:ef7eb2e8f9f7	1334	SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
<>	144:ef7eb2e8f9f7	1335	hspi->RxISR = SPI_RxISR_8BIT;
<>	144:ef7eb2e8f9f7	1336	}
<>	144:ef7eb2e8f9f7	1337
<>	144:ef7eb2e8f9f7	1338	/* Configure communication direction : 1Line */
AnnaBridge	167:e84263d55307	1339	if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
<>	144:ef7eb2e8f9f7	1340	{
<>	144:ef7eb2e8f9f7	1341	SPI_1LINE_RX(hspi);
<>	144:ef7eb2e8f9f7	1342	}
<>	144:ef7eb2e8f9f7	1343
AnnaBridge	167:e84263d55307	1344	#if (USE_SPI_CRC != 0U)
<>	144:ef7eb2e8f9f7	1345	/* Reset CRC Calculation */
AnnaBridge	167:e84263d55307	1346	if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<>	144:ef7eb2e8f9f7	1347	{
AnnaBridge	167:e84263d55307	1348	hspi->CRCSize = 1U;
AnnaBridge	167:e84263d55307	1349	if ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))
AnnaBridge	167:e84263d55307	1350	{
AnnaBridge	167:e84263d55307	1351	hspi->CRCSize = 2U;
AnnaBridge	167:e84263d55307	1352	}
<>	144:ef7eb2e8f9f7	1353	SPI_RESET_CRC(hspi);
<>	144:ef7eb2e8f9f7	1354	}
AnnaBridge	167:e84263d55307	1355	else
AnnaBridge	167:e84263d55307	1356	{
AnnaBridge	167:e84263d55307	1357	hspi->CRCSize = 0U;
AnnaBridge	167:e84263d55307	1358	}
AnnaBridge	167:e84263d55307	1359	#endif /* USE_SPI_CRC */
<>	144:ef7eb2e8f9f7	1360
<>	144:ef7eb2e8f9f7	1361	/* Enable TXE and ERR interrupt */
<>	144:ef7eb2e8f9f7	1362	__HAL_SPI_ENABLE_IT(hspi, (SPI_IT_RXNE \| SPI_IT_ERR));
<>	144:ef7eb2e8f9f7	1363
AnnaBridge	167:e84263d55307	1364	/* Note : The SPI must be enabled after unlocking current process
AnnaBridge	167:e84263d55307	1365	to avoid the risk of SPI interrupt handle execution before current
AnnaBridge	167:e84263d55307	1366	process unlock */
AnnaBridge	167:e84263d55307	1367
<>	144:ef7eb2e8f9f7	1368	/* Check if the SPI is already enabled */
AnnaBridge	167:e84263d55307	1369	if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
<>	144:ef7eb2e8f9f7	1370	{
<>	144:ef7eb2e8f9f7	1371	/* Enable SPI peripheral */
<>	144:ef7eb2e8f9f7	1372	__HAL_SPI_ENABLE(hspi);
<>	144:ef7eb2e8f9f7	1373	}
<>	144:ef7eb2e8f9f7	1374
<>	144:ef7eb2e8f9f7	1375	error :
<>	144:ef7eb2e8f9f7	1376	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	1377	__HAL_UNLOCK(hspi);
<>	144:ef7eb2e8f9f7	1378	return errorcode;
<>	144:ef7eb2e8f9f7	1379	}
<>	144:ef7eb2e8f9f7	1380
<>	144:ef7eb2e8f9f7	1381	/**
<>	144:ef7eb2e8f9f7	1382	* @brief Transmit and Receive an amount of data in non-blocking mode with Interrupt.
AnnaBridge	181:57724642e740	1383	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	1384	* the configuration information for SPI module.
AnnaBridge	181:57724642e740	1385	* @param pTxData pointer to transmission data buffer
AnnaBridge	181:57724642e740	1386	* @param pRxData pointer to reception data buffer
AnnaBridge	181:57724642e740	1387	* @param Size amount of data to be sent and received
<>	144:ef7eb2e8f9f7	1388	* @retval HAL status
<>	144:ef7eb2e8f9f7	1389	*/
<>	144:ef7eb2e8f9f7	1390	HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef hspi, uint8_t pTxData, uint8_t *pRxData, uint16_t Size)
<>	144:ef7eb2e8f9f7	1391	{
AnnaBridge	167:e84263d55307	1392	uint32_t tmp = 0U, tmp1 = 0U;
<>	144:ef7eb2e8f9f7	1393	HAL_StatusTypeDef errorcode = HAL_OK;
AnnaBridge	167:e84263d55307	1394
AnnaBridge	167:e84263d55307	1395	/* Check Direction parameter */
<>	144:ef7eb2e8f9f7	1396	assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
<>	144:ef7eb2e8f9f7	1397
<>	144:ef7eb2e8f9f7	1398	/* Process locked */
<>	144:ef7eb2e8f9f7	1399	__HAL_LOCK(hspi);
<>	144:ef7eb2e8f9f7	1400
AnnaBridge	167:e84263d55307	1401	tmp = hspi->State;
AnnaBridge	167:e84263d55307	1402	tmp1 = hspi->Init.Mode;
AnnaBridge	167:e84263d55307	1403
AnnaBridge	167:e84263d55307	1404	if (!((tmp == HAL_SPI_STATE_READY) \|\| \
AnnaBridge	167:e84263d55307	1405	((tmp1 == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp == HAL_SPI_STATE_BUSY_RX))))
<>	144:ef7eb2e8f9f7	1406	{
<>	144:ef7eb2e8f9f7	1407	errorcode = HAL_BUSY;
<>	144:ef7eb2e8f9f7	1408	goto error;
<>	144:ef7eb2e8f9f7	1409	}
<>	144:ef7eb2e8f9f7	1410
AnnaBridge	167:e84263d55307	1411	if ((pTxData == NULL) \|\| (pRxData == NULL) \|\| (Size == 0U))
<>	144:ef7eb2e8f9f7	1412	{
<>	144:ef7eb2e8f9f7	1413	errorcode = HAL_ERROR;
<>	144:ef7eb2e8f9f7	1414	goto error;
<>	144:ef7eb2e8f9f7	1415	}
<>	144:ef7eb2e8f9f7	1416
AnnaBridge	167:e84263d55307	1417	/* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
AnnaBridge	167:e84263d55307	1418	if (hspi->State != HAL_SPI_STATE_BUSY_RX)
<>	144:ef7eb2e8f9f7	1419	{
<>	144:ef7eb2e8f9f7	1420	hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
<>	144:ef7eb2e8f9f7	1421	}
<>	144:ef7eb2e8f9f7	1422
AnnaBridge	167:e84263d55307	1423	/* Set the transaction information */
<>	144:ef7eb2e8f9f7	1424	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
AnnaBridge	167:e84263d55307	1425	hspi->pTxBuffPtr = (uint8_t *)pTxData;
<>	144:ef7eb2e8f9f7	1426	hspi->TxXferSize = Size;
<>	144:ef7eb2e8f9f7	1427	hspi->TxXferCount = Size;
AnnaBridge	167:e84263d55307	1428	hspi->pRxBuffPtr = (uint8_t *)pRxData;
<>	144:ef7eb2e8f9f7	1429	hspi->RxXferSize = Size;
<>	144:ef7eb2e8f9f7	1430	hspi->RxXferCount = Size;
<>	144:ef7eb2e8f9f7	1431
<>	144:ef7eb2e8f9f7	1432	/* Set the function for IT treatment */
AnnaBridge	167:e84263d55307	1433	if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
<>	144:ef7eb2e8f9f7	1434	{
AnnaBridge	167:e84263d55307	1435	hspi->RxISR = SPI_2linesRxISR_16BIT;
AnnaBridge	167:e84263d55307	1436	hspi->TxISR = SPI_2linesTxISR_16BIT;
<>	144:ef7eb2e8f9f7	1437	}
<>	144:ef7eb2e8f9f7	1438	else
<>	144:ef7eb2e8f9f7	1439	{
AnnaBridge	167:e84263d55307	1440	hspi->RxISR = SPI_2linesRxISR_8BIT;
AnnaBridge	167:e84263d55307	1441	hspi->TxISR = SPI_2linesTxISR_8BIT;
<>	144:ef7eb2e8f9f7	1442	}
<>	144:ef7eb2e8f9f7	1443
AnnaBridge	167:e84263d55307	1444	#if (USE_SPI_CRC != 0U)
<>	144:ef7eb2e8f9f7	1445	/* Reset CRC Calculation */
AnnaBridge	167:e84263d55307	1446	if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<>	144:ef7eb2e8f9f7	1447	{
AnnaBridge	167:e84263d55307	1448	hspi->CRCSize = 1U;
AnnaBridge	167:e84263d55307	1449	if ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))
AnnaBridge	167:e84263d55307	1450	{
AnnaBridge	167:e84263d55307	1451	hspi->CRCSize = 2U;
AnnaBridge	167:e84263d55307	1452	}
<>	144:ef7eb2e8f9f7	1453	SPI_RESET_CRC(hspi);
<>	144:ef7eb2e8f9f7	1454	}
AnnaBridge	167:e84263d55307	1455	else
<>	144:ef7eb2e8f9f7	1456	{
AnnaBridge	167:e84263d55307	1457	hspi->CRCSize = 0U;
AnnaBridge	167:e84263d55307	1458	}
AnnaBridge	167:e84263d55307	1459	#endif /* USE_SPI_CRC */
AnnaBridge	167:e84263d55307	1460
AnnaBridge	167:e84263d55307	1461	/* Check if packing mode is enabled and if there is more than 2 data to receive */
AnnaBridge	167:e84263d55307	1462	if ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) \|\| (hspi->RxXferCount >= 2U))
AnnaBridge	167:e84263d55307	1463	{
AnnaBridge	181:57724642e740	1464	/* Set RX Fifo threshold according the reception data length: 16 bit */
<>	144:ef7eb2e8f9f7	1465	CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
<>	144:ef7eb2e8f9f7	1466	}
<>	144:ef7eb2e8f9f7	1467	else
<>	144:ef7eb2e8f9f7	1468	{
AnnaBridge	181:57724642e740	1469	/* Set RX Fifo threshold according the reception data length: 8 bit */
<>	144:ef7eb2e8f9f7	1470	SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
<>	144:ef7eb2e8f9f7	1471	}
<>	144:ef7eb2e8f9f7	1472
<>	144:ef7eb2e8f9f7	1473	/* Enable TXE, RXNE and ERR interrupt */
<>	144:ef7eb2e8f9f7	1474	__HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE \| SPI_IT_RXNE \| SPI_IT_ERR));
<>	144:ef7eb2e8f9f7	1475
<>	144:ef7eb2e8f9f7	1476	/* Check if the SPI is already enabled */
AnnaBridge	167:e84263d55307	1477	if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
<>	144:ef7eb2e8f9f7	1478	{
<>	144:ef7eb2e8f9f7	1479	/* Enable SPI peripheral */
<>	144:ef7eb2e8f9f7	1480	__HAL_SPI_ENABLE(hspi);
<>	144:ef7eb2e8f9f7	1481	}
<>	144:ef7eb2e8f9f7	1482
<>	144:ef7eb2e8f9f7	1483	error :
<>	144:ef7eb2e8f9f7	1484	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	1485	__HAL_UNLOCK(hspi);
<>	144:ef7eb2e8f9f7	1486	return errorcode;
<>	144:ef7eb2e8f9f7	1487	}
<>	144:ef7eb2e8f9f7	1488
<>	144:ef7eb2e8f9f7	1489	/**
<>	144:ef7eb2e8f9f7	1490	* @brief Transmit an amount of data in non-blocking mode with DMA.
AnnaBridge	181:57724642e740	1491	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	1492	* the configuration information for SPI module.
AnnaBridge	181:57724642e740	1493	* @param pData pointer to data buffer
AnnaBridge	181:57724642e740	1494	* @param Size amount of data to be sent
<>	144:ef7eb2e8f9f7	1495	* @retval HAL status
<>	144:ef7eb2e8f9f7	1496	*/
<>	144:ef7eb2e8f9f7	1497	HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size)
<>	144:ef7eb2e8f9f7	1498	{
<>	144:ef7eb2e8f9f7	1499	HAL_StatusTypeDef errorcode = HAL_OK;
AnnaBridge	181:57724642e740	1500
AnnaBridge	181:57724642e740	1501	/* Check tx dma handle */
AnnaBridge	167:e84263d55307	1502	assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx));
AnnaBridge	167:e84263d55307	1503
AnnaBridge	167:e84263d55307	1504	/* Check Direction parameter */
<>	144:ef7eb2e8f9f7	1505	assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
<>	144:ef7eb2e8f9f7	1506
<>	144:ef7eb2e8f9f7	1507	/* Process Locked */
<>	144:ef7eb2e8f9f7	1508	__HAL_LOCK(hspi);
<>	144:ef7eb2e8f9f7	1509
AnnaBridge	167:e84263d55307	1510	if (hspi->State != HAL_SPI_STATE_READY)
<>	144:ef7eb2e8f9f7	1511	{
<>	144:ef7eb2e8f9f7	1512	errorcode = HAL_BUSY;
<>	144:ef7eb2e8f9f7	1513	goto error;
<>	144:ef7eb2e8f9f7	1514	}
<>	144:ef7eb2e8f9f7	1515
AnnaBridge	167:e84263d55307	1516	if ((pData == NULL) \|\| (Size == 0U))
<>	144:ef7eb2e8f9f7	1517	{
<>	144:ef7eb2e8f9f7	1518	errorcode = HAL_ERROR;
<>	144:ef7eb2e8f9f7	1519	goto error;
<>	144:ef7eb2e8f9f7	1520	}
<>	144:ef7eb2e8f9f7	1521
AnnaBridge	167:e84263d55307	1522	/* Set the transaction information */
<>	144:ef7eb2e8f9f7	1523	hspi->State = HAL_SPI_STATE_BUSY_TX;
<>	144:ef7eb2e8f9f7	1524	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
AnnaBridge	167:e84263d55307	1525	hspi->pTxBuffPtr = (uint8_t *)pData;
<>	144:ef7eb2e8f9f7	1526	hspi->TxXferSize = Size;
<>	144:ef7eb2e8f9f7	1527	hspi->TxXferCount = Size;
AnnaBridge	167:e84263d55307	1528
AnnaBridge	167:e84263d55307	1529	/* Init field not used in handle to zero */
<>	144:ef7eb2e8f9f7	1530	hspi->pRxBuffPtr = (uint8_t *)NULL;
AnnaBridge	167:e84263d55307	1531	hspi->TxISR = NULL;
AnnaBridge	167:e84263d55307	1532	hspi->RxISR = NULL;
AnnaBridge	167:e84263d55307	1533	hspi->RxXferSize = 0U;
AnnaBridge	167:e84263d55307	1534	hspi->RxXferCount = 0U;
<>	144:ef7eb2e8f9f7	1535
<>	144:ef7eb2e8f9f7	1536	/* Configure communication direction : 1Line */
AnnaBridge	167:e84263d55307	1537	if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
<>	144:ef7eb2e8f9f7	1538	{
<>	144:ef7eb2e8f9f7	1539	SPI_1LINE_TX(hspi);
<>	144:ef7eb2e8f9f7	1540	}
<>	144:ef7eb2e8f9f7	1541
AnnaBridge	167:e84263d55307	1542	#if (USE_SPI_CRC != 0U)
<>	144:ef7eb2e8f9f7	1543	/* Reset CRC Calculation */
AnnaBridge	167:e84263d55307	1544	if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<>	144:ef7eb2e8f9f7	1545	{
<>	144:ef7eb2e8f9f7	1546	SPI_RESET_CRC(hspi);
<>	144:ef7eb2e8f9f7	1547	}
AnnaBridge	167:e84263d55307	1548	#endif /* USE_SPI_CRC */
<>	144:ef7eb2e8f9f7	1549
<>	144:ef7eb2e8f9f7	1550	/* Set the SPI TxDMA Half transfer complete callback */
<>	144:ef7eb2e8f9f7	1551	hspi->hdmatx->XferHalfCpltCallback = SPI_DMAHalfTransmitCplt;
<>	144:ef7eb2e8f9f7	1552
<>	144:ef7eb2e8f9f7	1553	/* Set the SPI TxDMA transfer complete callback */
<>	144:ef7eb2e8f9f7	1554	hspi->hdmatx->XferCpltCallback = SPI_DMATransmitCplt;
<>	144:ef7eb2e8f9f7	1555
<>	144:ef7eb2e8f9f7	1556	/* Set the DMA error callback */
<>	144:ef7eb2e8f9f7	1557	hspi->hdmatx->XferErrorCallback = SPI_DMAError;
<>	144:ef7eb2e8f9f7	1558
AnnaBridge	167:e84263d55307	1559	/* Set the DMA AbortCpltCallback */
AnnaBridge	167:e84263d55307	1560	hspi->hdmatx->XferAbortCallback = NULL;
AnnaBridge	167:e84263d55307	1561
<>	144:ef7eb2e8f9f7	1562	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
AnnaBridge	167:e84263d55307	1563	/* Packing mode is enabled only if the DMA setting is HALWORD */
AnnaBridge	167:e84263d55307	1564	if ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD))
<>	144:ef7eb2e8f9f7	1565	{
<>	144:ef7eb2e8f9f7	1566	/* Check the even/odd of the data size + crc if enabled */
AnnaBridge	167:e84263d55307	1567	if ((hspi->TxXferCount & 0x1U) == 0U)
<>	144:ef7eb2e8f9f7	1568	{
<>	144:ef7eb2e8f9f7	1569	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
AnnaBridge	167:e84263d55307	1570	hspi->TxXferCount = (hspi->TxXferCount >> 1U);
<>	144:ef7eb2e8f9f7	1571	}
<>	144:ef7eb2e8f9f7	1572	else
<>	144:ef7eb2e8f9f7	1573	{
<>	144:ef7eb2e8f9f7	1574	SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
AnnaBridge	167:e84263d55307	1575	hspi->TxXferCount = (hspi->TxXferCount >> 1U) + 1U;
<>	144:ef7eb2e8f9f7	1576	}
<>	144:ef7eb2e8f9f7	1577	}
<>	144:ef7eb2e8f9f7	1578
AnnaBridge	167:e84263d55307	1579	/* Enable the Tx DMA Stream/Channel */
<>	144:ef7eb2e8f9f7	1580	HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount);
<>	144:ef7eb2e8f9f7	1581
<>	144:ef7eb2e8f9f7	1582	/* Check if the SPI is already enabled */
AnnaBridge	167:e84263d55307	1583	if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
<>	144:ef7eb2e8f9f7	1584	{
<>	144:ef7eb2e8f9f7	1585	/* Enable SPI peripheral */
<>	144:ef7eb2e8f9f7	1586	__HAL_SPI_ENABLE(hspi);
<>	144:ef7eb2e8f9f7	1587	}
<>	144:ef7eb2e8f9f7	1588
AnnaBridge	167:e84263d55307	1589	/* Enable the SPI Error Interrupt Bit */
AnnaBridge	167:e84263d55307	1590	__HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR));
AnnaBridge	167:e84263d55307	1591
<>	144:ef7eb2e8f9f7	1592	/* Enable Tx DMA Request */
<>	144:ef7eb2e8f9f7	1593	SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
<>	144:ef7eb2e8f9f7	1594
<>	144:ef7eb2e8f9f7	1595	error :
<>	144:ef7eb2e8f9f7	1596	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	1597	__HAL_UNLOCK(hspi);
<>	144:ef7eb2e8f9f7	1598	return errorcode;
<>	144:ef7eb2e8f9f7	1599	}
<>	144:ef7eb2e8f9f7	1600
<>	144:ef7eb2e8f9f7	1601	/**
<>	144:ef7eb2e8f9f7	1602	* @brief Receive an amount of data in non-blocking mode with DMA.
AnnaBridge	167:e84263d55307	1603	* @note In case of MASTER mode and SPI_DIRECTION_2LINES direction, hdmatx shall be defined.
AnnaBridge	181:57724642e740	1604	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	1605	* the configuration information for SPI module.
AnnaBridge	181:57724642e740	1606	* @param pData pointer to data buffer
AnnaBridge	167:e84263d55307	1607	* @note When the CRC feature is enabled the pData Length must be Size + 1.
AnnaBridge	181:57724642e740	1608	* @param Size amount of data to be sent
<>	144:ef7eb2e8f9f7	1609	* @retval HAL status
<>	144:ef7eb2e8f9f7	1610	*/
<>	144:ef7eb2e8f9f7	1611	HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size)
<>	144:ef7eb2e8f9f7	1612	{
<>	144:ef7eb2e8f9f7	1613	HAL_StatusTypeDef errorcode = HAL_OK;
AnnaBridge	181:57724642e740	1614
AnnaBridge	181:57724642e740	1615	/* Check rx dma handle */
AnnaBridge	167:e84263d55307	1616	assert_param(IS_SPI_DMA_HANDLE(hspi->hdmarx));
AnnaBridge	167:e84263d55307	1617
AnnaBridge	167:e84263d55307	1618	if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
AnnaBridge	167:e84263d55307	1619	{
AnnaBridge	167:e84263d55307	1620	hspi->State = HAL_SPI_STATE_BUSY_RX;
AnnaBridge	181:57724642e740	1621
AnnaBridge	181:57724642e740	1622	/* Check tx dma handle */
AnnaBridge	167:e84263d55307	1623	assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx));
AnnaBridge	167:e84263d55307	1624
AnnaBridge	167:e84263d55307	1625	/* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
AnnaBridge	167:e84263d55307	1626	return HAL_SPI_TransmitReceive_DMA(hspi, pData, pData, Size);
AnnaBridge	167:e84263d55307	1627	}
<>	144:ef7eb2e8f9f7	1628
<>	144:ef7eb2e8f9f7	1629	/* Process Locked */
<>	144:ef7eb2e8f9f7	1630	__HAL_LOCK(hspi);
<>	144:ef7eb2e8f9f7	1631
AnnaBridge	167:e84263d55307	1632	if (hspi->State != HAL_SPI_STATE_READY)
<>	144:ef7eb2e8f9f7	1633	{
<>	144:ef7eb2e8f9f7	1634	errorcode = HAL_BUSY;
<>	144:ef7eb2e8f9f7	1635	goto error;
<>	144:ef7eb2e8f9f7	1636	}
<>	144:ef7eb2e8f9f7	1637
AnnaBridge	167:e84263d55307	1638	if ((pData == NULL) \|\| (Size == 0U))
<>	144:ef7eb2e8f9f7	1639	{
<>	144:ef7eb2e8f9f7	1640	errorcode = HAL_ERROR;
<>	144:ef7eb2e8f9f7	1641	goto error;
<>	144:ef7eb2e8f9f7	1642	}
<>	144:ef7eb2e8f9f7	1643
AnnaBridge	167:e84263d55307	1644	/* Set the transaction information */
<>	144:ef7eb2e8f9f7	1645	hspi->State = HAL_SPI_STATE_BUSY_RX;
<>	144:ef7eb2e8f9f7	1646	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
AnnaBridge	167:e84263d55307	1647	hspi->pRxBuffPtr = (uint8_t *)pData;
<>	144:ef7eb2e8f9f7	1648	hspi->RxXferSize = Size;
<>	144:ef7eb2e8f9f7	1649	hspi->RxXferCount = Size;
AnnaBridge	167:e84263d55307	1650
AnnaBridge	167:e84263d55307	1651	/Init field not used in handle to zero /
AnnaBridge	167:e84263d55307	1652	hspi->RxISR = NULL;
AnnaBridge	167:e84263d55307	1653	hspi->TxISR = NULL;
AnnaBridge	167:e84263d55307	1654	hspi->TxXferSize = 0U;
AnnaBridge	167:e84263d55307	1655	hspi->TxXferCount = 0U;
<>	144:ef7eb2e8f9f7	1656
<>	144:ef7eb2e8f9f7	1657	/* Configure communication direction : 1Line */
AnnaBridge	167:e84263d55307	1658	if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
<>	144:ef7eb2e8f9f7	1659	{
<>	144:ef7eb2e8f9f7	1660	SPI_1LINE_RX(hspi);
<>	144:ef7eb2e8f9f7	1661	}
<>	144:ef7eb2e8f9f7	1662
AnnaBridge	167:e84263d55307	1663	#if (USE_SPI_CRC != 0U)
<>	144:ef7eb2e8f9f7	1664	/* Reset CRC Calculation */
AnnaBridge	167:e84263d55307	1665	if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<>	144:ef7eb2e8f9f7	1666	{
<>	144:ef7eb2e8f9f7	1667	SPI_RESET_CRC(hspi);
<>	144:ef7eb2e8f9f7	1668	}
AnnaBridge	167:e84263d55307	1669	#endif /* USE_SPI_CRC */
AnnaBridge	167:e84263d55307	1670
<>	144:ef7eb2e8f9f7	1671
<>	144:ef7eb2e8f9f7	1672	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
AnnaBridge	167:e84263d55307	1673	if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
<>	144:ef7eb2e8f9f7	1674	{
AnnaBridge	181:57724642e740	1675	/* Set RX Fifo threshold according the reception data length: 16bit */
<>	144:ef7eb2e8f9f7	1676	CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
<>	144:ef7eb2e8f9f7	1677	}
<>	144:ef7eb2e8f9f7	1678	else
<>	144:ef7eb2e8f9f7	1679	{
AnnaBridge	181:57724642e740	1680	/* Set RX Fifo threshold according the reception data length: 8bit */
<>	144:ef7eb2e8f9f7	1681	SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
AnnaBridge	167:e84263d55307	1682
AnnaBridge	167:e84263d55307	1683	if (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
AnnaBridge	167:e84263d55307	1684	{
AnnaBridge	181:57724642e740	1685	/* Set RX Fifo threshold according the reception data length: 16bit */
AnnaBridge	167:e84263d55307	1686	CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
AnnaBridge	167:e84263d55307	1687
AnnaBridge	167:e84263d55307	1688	if ((hspi->RxXferCount & 0x1U) == 0x0U)
AnnaBridge	167:e84263d55307	1689	{
AnnaBridge	167:e84263d55307	1690	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
AnnaBridge	167:e84263d55307	1691	hspi->RxXferCount = hspi->RxXferCount >> 1U;
AnnaBridge	167:e84263d55307	1692	}
AnnaBridge	167:e84263d55307	1693	else
AnnaBridge	167:e84263d55307	1694	{
AnnaBridge	167:e84263d55307	1695	SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
AnnaBridge	167:e84263d55307	1696	hspi->RxXferCount = (hspi->RxXferCount >> 1U) + 1U;
AnnaBridge	167:e84263d55307	1697	}
AnnaBridge	167:e84263d55307	1698	}
<>	144:ef7eb2e8f9f7	1699	}
<>	144:ef7eb2e8f9f7	1700
<>	144:ef7eb2e8f9f7	1701	/* Set the SPI RxDMA Half transfer complete callback */
<>	144:ef7eb2e8f9f7	1702	hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
<>	144:ef7eb2e8f9f7	1703
<>	144:ef7eb2e8f9f7	1704	/* Set the SPI Rx DMA transfer complete callback */
<>	144:ef7eb2e8f9f7	1705	hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
<>	144:ef7eb2e8f9f7	1706
<>	144:ef7eb2e8f9f7	1707	/* Set the DMA error callback */
<>	144:ef7eb2e8f9f7	1708	hspi->hdmarx->XferErrorCallback = SPI_DMAError;
<>	144:ef7eb2e8f9f7	1709
AnnaBridge	167:e84263d55307	1710	/* Set the DMA AbortCpltCallback */
AnnaBridge	167:e84263d55307	1711	hspi->hdmarx->XferAbortCallback = NULL;
AnnaBridge	167:e84263d55307	1712
AnnaBridge	167:e84263d55307	1713	/* Enable the Rx DMA Stream/Channel */
<>	144:ef7eb2e8f9f7	1714	HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount);
<>	144:ef7eb2e8f9f7	1715
<>	144:ef7eb2e8f9f7	1716	/* Check if the SPI is already enabled */
AnnaBridge	167:e84263d55307	1717	if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
<>	144:ef7eb2e8f9f7	1718	{
<>	144:ef7eb2e8f9f7	1719	/* Enable SPI peripheral */
<>	144:ef7eb2e8f9f7	1720	__HAL_SPI_ENABLE(hspi);
<>	144:ef7eb2e8f9f7	1721	}
<>	144:ef7eb2e8f9f7	1722
AnnaBridge	167:e84263d55307	1723	/* Enable the SPI Error Interrupt Bit */
AnnaBridge	167:e84263d55307	1724	__HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR));
AnnaBridge	167:e84263d55307	1725
AnnaBridge	167:e84263d55307	1726	/* Enable Rx DMA Request */
AnnaBridge	167:e84263d55307	1727	SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
AnnaBridge	167:e84263d55307	1728
<>	144:ef7eb2e8f9f7	1729	error:
<>	144:ef7eb2e8f9f7	1730	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	1731	__HAL_UNLOCK(hspi);
<>	144:ef7eb2e8f9f7	1732	return errorcode;
<>	144:ef7eb2e8f9f7	1733	}
<>	144:ef7eb2e8f9f7	1734
<>	144:ef7eb2e8f9f7	1735	/**
<>	144:ef7eb2e8f9f7	1736	* @brief Transmit and Receive an amount of data in non-blocking mode with DMA.
AnnaBridge	181:57724642e740	1737	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	1738	* the configuration information for SPI module.
AnnaBridge	181:57724642e740	1739	* @param pTxData pointer to transmission data buffer
AnnaBridge	181:57724642e740	1740	* @param pRxData pointer to reception data buffer
AnnaBridge	167:e84263d55307	1741	* @note When the CRC feature is enabled the pRxData Length must be Size + 1
AnnaBridge	181:57724642e740	1742	* @param Size amount of data to be sent
<>	144:ef7eb2e8f9f7	1743	* @retval HAL status
<>	144:ef7eb2e8f9f7	1744	*/
AnnaBridge	167:e84263d55307	1745	HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef hspi, uint8_t pTxData, uint8_t *pRxData,
AnnaBridge	167:e84263d55307	1746	uint16_t Size)
<>	144:ef7eb2e8f9f7	1747	{
AnnaBridge	167:e84263d55307	1748	uint32_t tmp = 0U, tmp1 = 0U;
<>	144:ef7eb2e8f9f7	1749	HAL_StatusTypeDef errorcode = HAL_OK;
AnnaBridge	181:57724642e740	1750
AnnaBridge	181:57724642e740	1751	/* Check rx & tx dma handles */
AnnaBridge	167:e84263d55307	1752	assert_param(IS_SPI_DMA_HANDLE(hspi->hdmarx));
AnnaBridge	167:e84263d55307	1753	assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx));
AnnaBridge	167:e84263d55307	1754
AnnaBridge	167:e84263d55307	1755	/* Check Direction parameter */
<>	144:ef7eb2e8f9f7	1756	assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
<>	144:ef7eb2e8f9f7	1757
<>	144:ef7eb2e8f9f7	1758	/* Process locked */
<>	144:ef7eb2e8f9f7	1759	__HAL_LOCK(hspi);
<>	144:ef7eb2e8f9f7	1760
AnnaBridge	167:e84263d55307	1761	tmp = hspi->State;
AnnaBridge	167:e84263d55307	1762	tmp1 = hspi->Init.Mode;
AnnaBridge	167:e84263d55307	1763	if (!((tmp == HAL_SPI_STATE_READY) \|\|
AnnaBridge	167:e84263d55307	1764	((tmp1 == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp == HAL_SPI_STATE_BUSY_RX))))
<>	144:ef7eb2e8f9f7	1765	{
<>	144:ef7eb2e8f9f7	1766	errorcode = HAL_BUSY;
<>	144:ef7eb2e8f9f7	1767	goto error;
<>	144:ef7eb2e8f9f7	1768	}
<>	144:ef7eb2e8f9f7	1769
AnnaBridge	167:e84263d55307	1770	if ((pTxData == NULL) \|\| (pRxData == NULL) \|\| (Size == 0U))
<>	144:ef7eb2e8f9f7	1771	{
<>	144:ef7eb2e8f9f7	1772	errorcode = HAL_ERROR;
<>	144:ef7eb2e8f9f7	1773	goto error;
<>	144:ef7eb2e8f9f7	1774	}
<>	144:ef7eb2e8f9f7	1775
AnnaBridge	167:e84263d55307	1776	/* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
AnnaBridge	167:e84263d55307	1777	if (hspi->State != HAL_SPI_STATE_BUSY_RX)
<>	144:ef7eb2e8f9f7	1778	{
<>	144:ef7eb2e8f9f7	1779	hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
<>	144:ef7eb2e8f9f7	1780	}
<>	144:ef7eb2e8f9f7	1781
AnnaBridge	167:e84263d55307	1782	/* Set the transaction information */
<>	144:ef7eb2e8f9f7	1783	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
<>	144:ef7eb2e8f9f7	1784	hspi->pTxBuffPtr = (uint8_t *)pTxData;
<>	144:ef7eb2e8f9f7	1785	hspi->TxXferSize = Size;
<>	144:ef7eb2e8f9f7	1786	hspi->TxXferCount = Size;
<>	144:ef7eb2e8f9f7	1787	hspi->pRxBuffPtr = (uint8_t *)pRxData;
<>	144:ef7eb2e8f9f7	1788	hspi->RxXferSize = Size;
<>	144:ef7eb2e8f9f7	1789	hspi->RxXferCount = Size;
<>	144:ef7eb2e8f9f7	1790
AnnaBridge	167:e84263d55307	1791	/* Init field not used in handle to zero */
AnnaBridge	167:e84263d55307	1792	hspi->RxISR = NULL;
AnnaBridge	167:e84263d55307	1793	hspi->TxISR = NULL;
AnnaBridge	167:e84263d55307	1794
AnnaBridge	167:e84263d55307	1795	#if (USE_SPI_CRC != 0U)
AnnaBridge	167:e84263d55307	1796	/* Reset CRC Calculation */
AnnaBridge	167:e84263d55307	1797	if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<>	144:ef7eb2e8f9f7	1798	{
<>	144:ef7eb2e8f9f7	1799	SPI_RESET_CRC(hspi);
<>	144:ef7eb2e8f9f7	1800	}
AnnaBridge	167:e84263d55307	1801	#endif /* USE_SPI_CRC */
AnnaBridge	167:e84263d55307	1802
<>	144:ef7eb2e8f9f7	1803	/* Reset the threshold bit */
<>	144:ef7eb2e8f9f7	1804	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX \| SPI_CR2_LDMARX);
<>	144:ef7eb2e8f9f7	1805
AnnaBridge	167:e84263d55307	1806	/* The packing mode management is enabled by the DMA settings according the spi data size */
AnnaBridge	167:e84263d55307	1807	if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
<>	144:ef7eb2e8f9f7	1808	{
AnnaBridge	167:e84263d55307	1809	/* Set fiforxthreshold according the reception data length: 16bit */
<>	144:ef7eb2e8f9f7	1810	CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
<>	144:ef7eb2e8f9f7	1811	}
<>	144:ef7eb2e8f9f7	1812	else
<>	144:ef7eb2e8f9f7	1813	{
AnnaBridge	181:57724642e740	1814	/* Set RX Fifo threshold according the reception data length: 8bit */
<>	144:ef7eb2e8f9f7	1815	SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
<>	144:ef7eb2e8f9f7	1816
AnnaBridge	167:e84263d55307	1817	if (hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
<>	144:ef7eb2e8f9f7	1818	{
AnnaBridge	167:e84263d55307	1819	if ((hspi->TxXferSize & 0x1U) == 0x0U)
<>	144:ef7eb2e8f9f7	1820	{
<>	144:ef7eb2e8f9f7	1821	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
AnnaBridge	167:e84263d55307	1822	hspi->TxXferCount = hspi->TxXferCount >> 1U;
<>	144:ef7eb2e8f9f7	1823	}
<>	144:ef7eb2e8f9f7	1824	else
<>	144:ef7eb2e8f9f7	1825	{
<>	144:ef7eb2e8f9f7	1826	SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
AnnaBridge	167:e84263d55307	1827	hspi->TxXferCount = (hspi->TxXferCount >> 1U) + 1U;
<>	144:ef7eb2e8f9f7	1828	}
<>	144:ef7eb2e8f9f7	1829	}
<>	144:ef7eb2e8f9f7	1830
AnnaBridge	167:e84263d55307	1831	if (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
<>	144:ef7eb2e8f9f7	1832	{
AnnaBridge	181:57724642e740	1833	/* Set RX Fifo threshold according the reception data length: 16bit */
<>	144:ef7eb2e8f9f7	1834	CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
<>	144:ef7eb2e8f9f7	1835
AnnaBridge	167:e84263d55307	1836	if ((hspi->RxXferCount & 0x1U) == 0x0U)
<>	144:ef7eb2e8f9f7	1837	{
<>	144:ef7eb2e8f9f7	1838	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
AnnaBridge	167:e84263d55307	1839	hspi->RxXferCount = hspi->RxXferCount >> 1U;
<>	144:ef7eb2e8f9f7	1840	}
<>	144:ef7eb2e8f9f7	1841	else
<>	144:ef7eb2e8f9f7	1842	{
<>	144:ef7eb2e8f9f7	1843	SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
AnnaBridge	167:e84263d55307	1844	hspi->RxXferCount = (hspi->RxXferCount >> 1U) + 1U;
<>	144:ef7eb2e8f9f7	1845	}
<>	144:ef7eb2e8f9f7	1846	}
<>	144:ef7eb2e8f9f7	1847	}
<>	144:ef7eb2e8f9f7	1848
AnnaBridge	167:e84263d55307	1849	/* Check if we are in Rx only or in Rx/Tx Mode and configure the DMA transfer complete callback */
AnnaBridge	167:e84263d55307	1850	if (hspi->State == HAL_SPI_STATE_BUSY_RX)
<>	144:ef7eb2e8f9f7	1851	{
<>	144:ef7eb2e8f9f7	1852	/* Set the SPI Rx DMA Half transfer complete callback */
<>	144:ef7eb2e8f9f7	1853	hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
AnnaBridge	167:e84263d55307	1854	hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
<>	144:ef7eb2e8f9f7	1855	}
<>	144:ef7eb2e8f9f7	1856	else
<>	144:ef7eb2e8f9f7	1857	{
AnnaBridge	167:e84263d55307	1858	/* Set the SPI Tx/Rx DMA Half transfer complete callback */
<>	144:ef7eb2e8f9f7	1859	hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfTransmitReceiveCplt;
AnnaBridge	167:e84263d55307	1860	hspi->hdmarx->XferCpltCallback = SPI_DMATransmitReceiveCplt;
<>	144:ef7eb2e8f9f7	1861	}
<>	144:ef7eb2e8f9f7	1862
<>	144:ef7eb2e8f9f7	1863	/* Set the DMA error callback */
<>	144:ef7eb2e8f9f7	1864	hspi->hdmarx->XferErrorCallback = SPI_DMAError;
<>	144:ef7eb2e8f9f7	1865
AnnaBridge	167:e84263d55307	1866	/* Set the DMA AbortCpltCallback */
AnnaBridge	167:e84263d55307	1867	hspi->hdmarx->XferAbortCallback = NULL;
AnnaBridge	167:e84263d55307	1868
AnnaBridge	167:e84263d55307	1869	/* Enable the Rx DMA Stream/Channel */
AnnaBridge	167:e84263d55307	1870	HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount);
AnnaBridge	167:e84263d55307	1871
<>	144:ef7eb2e8f9f7	1872	/* Enable Rx DMA Request */
<>	144:ef7eb2e8f9f7	1873	SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
<>	144:ef7eb2e8f9f7	1874
AnnaBridge	167:e84263d55307	1875	/* Set the SPI Tx DMA transfer complete callback as NULL because the communication closing
AnnaBridge	167:e84263d55307	1876	is performed in DMA reception complete callback */
<>	144:ef7eb2e8f9f7	1877	hspi->hdmatx->XferHalfCpltCallback = NULL;
<>	144:ef7eb2e8f9f7	1878	hspi->hdmatx->XferCpltCallback = NULL;
<>	144:ef7eb2e8f9f7	1879	hspi->hdmatx->XferErrorCallback = NULL;
AnnaBridge	167:e84263d55307	1880	hspi->hdmatx->XferAbortCallback = NULL;
AnnaBridge	167:e84263d55307	1881
AnnaBridge	167:e84263d55307	1882	/* Enable the Tx DMA Stream/Channel */
<>	144:ef7eb2e8f9f7	1883	HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount);
<>	144:ef7eb2e8f9f7	1884
<>	144:ef7eb2e8f9f7	1885	/* Check if the SPI is already enabled */
AnnaBridge	167:e84263d55307	1886	if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
<>	144:ef7eb2e8f9f7	1887	{
<>	144:ef7eb2e8f9f7	1888	/* Enable SPI peripheral */
<>	144:ef7eb2e8f9f7	1889	__HAL_SPI_ENABLE(hspi);
<>	144:ef7eb2e8f9f7	1890	}
AnnaBridge	167:e84263d55307	1891	/* Enable the SPI Error Interrupt Bit */
AnnaBridge	167:e84263d55307	1892	__HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR));
<>	144:ef7eb2e8f9f7	1893
<>	144:ef7eb2e8f9f7	1894	/* Enable Tx DMA Request */
<>	144:ef7eb2e8f9f7	1895	SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
<>	144:ef7eb2e8f9f7	1896
<>	144:ef7eb2e8f9f7	1897	error :
<>	144:ef7eb2e8f9f7	1898	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	1899	__HAL_UNLOCK(hspi);
<>	144:ef7eb2e8f9f7	1900	return errorcode;
<>	144:ef7eb2e8f9f7	1901	}
<>	144:ef7eb2e8f9f7	1902
<>	144:ef7eb2e8f9f7	1903	/**
AnnaBridge	167:e84263d55307	1904	* @brief Abort ongoing transfer (blocking mode).
AnnaBridge	167:e84263d55307	1905	* @param hspi SPI handle.
AnnaBridge	167:e84263d55307	1906	* @note This procedure could be used for aborting any ongoing transfer (Tx and Rx),
AnnaBridge	167:e84263d55307	1907	* started in Interrupt or DMA mode.
AnnaBridge	167:e84263d55307	1908	* This procedure performs following operations :
AnnaBridge	167:e84263d55307	1909	* - Disable SPI Interrupts (depending of transfer direction)
AnnaBridge	167:e84263d55307	1910	* - Disable the DMA transfer in the peripheral register (if enabled)
AnnaBridge	167:e84263d55307	1911	* - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
AnnaBridge	167:e84263d55307	1912	* - Set handle State to READY
AnnaBridge	167:e84263d55307	1913	* @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
AnnaBridge	167:e84263d55307	1914	* @retval HAL status
AnnaBridge	167:e84263d55307	1915	*/
AnnaBridge	167:e84263d55307	1916	HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi)
AnnaBridge	167:e84263d55307	1917	{
AnnaBridge	167:e84263d55307	1918	HAL_StatusTypeDef errorcode;
AnnaBridge	167:e84263d55307	1919	__IO uint32_t count, resetcount;
AnnaBridge	167:e84263d55307	1920
AnnaBridge	167:e84263d55307	1921	/* Initialized local variable */
AnnaBridge	167:e84263d55307	1922	errorcode = HAL_OK;
AnnaBridge	167:e84263d55307	1923	resetcount = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
AnnaBridge	167:e84263d55307	1924	count = resetcount;
AnnaBridge	167:e84263d55307	1925
AnnaBridge	167:e84263d55307	1926	/* Disable TXEIE, RXNEIE and ERRIE(mode fault event, overrun error, TI frame error) interrupts */
AnnaBridge	167:e84263d55307	1927	if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE))
AnnaBridge	167:e84263d55307	1928	{
AnnaBridge	167:e84263d55307	1929	hspi->TxISR = SPI_AbortTx_ISR;
AnnaBridge	167:e84263d55307	1930	/* Wait HAL_SPI_STATE_ABORT state */
AnnaBridge	167:e84263d55307	1931	do
AnnaBridge	167:e84263d55307	1932	{
AnnaBridge	167:e84263d55307	1933	if (count-- == 0U)
AnnaBridge	167:e84263d55307	1934	{
AnnaBridge	167:e84263d55307	1935	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
AnnaBridge	167:e84263d55307	1936	break;
AnnaBridge	167:e84263d55307	1937	}
AnnaBridge	167:e84263d55307	1938	}
AnnaBridge	167:e84263d55307	1939	while (hspi->State != HAL_SPI_STATE_ABORT);
AnnaBridge	167:e84263d55307	1940	/* Reset Timeout Counter */
AnnaBridge	167:e84263d55307	1941	count = resetcount;
AnnaBridge	167:e84263d55307	1942	}
AnnaBridge	167:e84263d55307	1943
AnnaBridge	167:e84263d55307	1944	if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE))
AnnaBridge	167:e84263d55307	1945	{
AnnaBridge	167:e84263d55307	1946	hspi->RxISR = SPI_AbortRx_ISR;
AnnaBridge	167:e84263d55307	1947	/* Wait HAL_SPI_STATE_ABORT state */
AnnaBridge	167:e84263d55307	1948	do
AnnaBridge	167:e84263d55307	1949	{
AnnaBridge	167:e84263d55307	1950	if (count-- == 0U)
AnnaBridge	167:e84263d55307	1951	{
AnnaBridge	167:e84263d55307	1952	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
AnnaBridge	167:e84263d55307	1953	break;
AnnaBridge	167:e84263d55307	1954	}
AnnaBridge	167:e84263d55307	1955	}
AnnaBridge	167:e84263d55307	1956	while (hspi->State != HAL_SPI_STATE_ABORT);
AnnaBridge	167:e84263d55307	1957	/* Reset Timeout Counter */
AnnaBridge	167:e84263d55307	1958	count = resetcount;
AnnaBridge	167:e84263d55307	1959	}
AnnaBridge	167:e84263d55307	1960
AnnaBridge	167:e84263d55307	1961	/* Clear ERRIE interrupts in case of DMA Mode */
AnnaBridge	167:e84263d55307	1962	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE);
AnnaBridge	167:e84263d55307	1963
AnnaBridge	167:e84263d55307	1964	/* Disable the SPI DMA Tx or SPI DMA Rx request if enabled */
AnnaBridge	167:e84263d55307	1965	if ((HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN)) \|\| (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN)))
AnnaBridge	167:e84263d55307	1966	{
AnnaBridge	167:e84263d55307	1967	/* Abort the SPI DMA Tx Stream/Channel : use blocking DMA Abort API (no callback) */
AnnaBridge	167:e84263d55307	1968	if (hspi->hdmatx != NULL)
AnnaBridge	167:e84263d55307	1969	{
AnnaBridge	167:e84263d55307	1970	/* Set the SPI DMA Abort callback :
AnnaBridge	167:e84263d55307	1971	will lead to call HAL_SPI_AbortCpltCallback() at end of DMA abort procedure */
AnnaBridge	167:e84263d55307	1972	hspi->hdmatx->XferAbortCallback = NULL;
AnnaBridge	167:e84263d55307	1973
AnnaBridge	167:e84263d55307	1974	/* Abort DMA Tx Handle linked to SPI Peripheral */
AnnaBridge	167:e84263d55307	1975	if (HAL_DMA_Abort(hspi->hdmatx) != HAL_OK)
AnnaBridge	167:e84263d55307	1976	{
AnnaBridge	167:e84263d55307	1977	hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
AnnaBridge	167:e84263d55307	1978	}
AnnaBridge	167:e84263d55307	1979
AnnaBridge	167:e84263d55307	1980	/* Disable Tx DMA Request */
AnnaBridge	167:e84263d55307	1981	CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXDMAEN));
AnnaBridge	167:e84263d55307	1982
AnnaBridge	167:e84263d55307	1983	if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
AnnaBridge	167:e84263d55307	1984	{
AnnaBridge	167:e84263d55307	1985	hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
AnnaBridge	167:e84263d55307	1986	}
AnnaBridge	167:e84263d55307	1987
AnnaBridge	167:e84263d55307	1988	/* Disable SPI Peripheral */
AnnaBridge	167:e84263d55307	1989	__HAL_SPI_DISABLE(hspi);
AnnaBridge	167:e84263d55307	1990
AnnaBridge	167:e84263d55307	1991	/* Empty the FRLVL fifo */
AnnaBridge	167:e84263d55307	1992	if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
AnnaBridge	167:e84263d55307	1993	{
AnnaBridge	167:e84263d55307	1994	hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
AnnaBridge	167:e84263d55307	1995	}
AnnaBridge	167:e84263d55307	1996	}
AnnaBridge	167:e84263d55307	1997	/* Abort the SPI DMA Rx Stream/Channel : use blocking DMA Abort API (no callback) */
AnnaBridge	167:e84263d55307	1998	if (hspi->hdmarx != NULL)
AnnaBridge	167:e84263d55307	1999	{
AnnaBridge	167:e84263d55307	2000	/* Set the SPI DMA Abort callback :
AnnaBridge	167:e84263d55307	2001	will lead to call HAL_SPI_AbortCpltCallback() at end of DMA abort procedure */
AnnaBridge	167:e84263d55307	2002	hspi->hdmarx->XferAbortCallback = NULL;
AnnaBridge	167:e84263d55307	2003
AnnaBridge	167:e84263d55307	2004	/* Abort DMA Rx Handle linked to SPI Peripheral */
AnnaBridge	167:e84263d55307	2005	if (HAL_DMA_Abort(hspi->hdmarx) != HAL_OK)
AnnaBridge	167:e84263d55307	2006	{
AnnaBridge	167:e84263d55307	2007	hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
AnnaBridge	167:e84263d55307	2008	}
AnnaBridge	167:e84263d55307	2009
AnnaBridge	167:e84263d55307	2010	/* Disable peripheral */
AnnaBridge	167:e84263d55307	2011	__HAL_SPI_DISABLE(hspi);
AnnaBridge	167:e84263d55307	2012
AnnaBridge	167:e84263d55307	2013	/* Control the BSY flag */
AnnaBridge	167:e84263d55307	2014	if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
AnnaBridge	167:e84263d55307	2015	{
AnnaBridge	167:e84263d55307	2016	hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
AnnaBridge	167:e84263d55307	2017	}
AnnaBridge	167:e84263d55307	2018
AnnaBridge	167:e84263d55307	2019	/* Empty the FRLVL fifo */
AnnaBridge	167:e84263d55307	2020	if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
AnnaBridge	167:e84263d55307	2021	{
AnnaBridge	167:e84263d55307	2022	hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
AnnaBridge	167:e84263d55307	2023	}
AnnaBridge	167:e84263d55307	2024
AnnaBridge	167:e84263d55307	2025	/* Disable Rx DMA Request */
AnnaBridge	167:e84263d55307	2026	CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_RXDMAEN));
AnnaBridge	167:e84263d55307	2027	}
AnnaBridge	167:e84263d55307	2028	}
AnnaBridge	167:e84263d55307	2029	/* Reset Tx and Rx transfer counters */
AnnaBridge	167:e84263d55307	2030	hspi->RxXferCount = 0U;
AnnaBridge	167:e84263d55307	2031	hspi->TxXferCount = 0U;
AnnaBridge	167:e84263d55307	2032
AnnaBridge	167:e84263d55307	2033	/* Check error during Abort procedure */
AnnaBridge	167:e84263d55307	2034	if (hspi->ErrorCode == HAL_SPI_ERROR_ABORT)
AnnaBridge	167:e84263d55307	2035	{
AnnaBridge	167:e84263d55307	2036	/* return HAL_Error in case of error during Abort procedure */
AnnaBridge	167:e84263d55307	2037	errorcode = HAL_ERROR;
AnnaBridge	167:e84263d55307	2038	}
AnnaBridge	167:e84263d55307	2039	else
AnnaBridge	167:e84263d55307	2040	{
AnnaBridge	167:e84263d55307	2041	/* Reset errorCode */
AnnaBridge	167:e84263d55307	2042	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
AnnaBridge	167:e84263d55307	2043	}
AnnaBridge	167:e84263d55307	2044
AnnaBridge	167:e84263d55307	2045	/* Clear the Error flags in the SR register */
AnnaBridge	167:e84263d55307	2046	__HAL_SPI_CLEAR_OVRFLAG(hspi);
AnnaBridge	167:e84263d55307	2047	__HAL_SPI_CLEAR_FREFLAG(hspi);
AnnaBridge	167:e84263d55307	2048
AnnaBridge	167:e84263d55307	2049	/* Restore hspi->state to ready */
AnnaBridge	167:e84263d55307	2050	hspi->State = HAL_SPI_STATE_READY;
AnnaBridge	167:e84263d55307	2051
AnnaBridge	167:e84263d55307	2052	return errorcode;
AnnaBridge	167:e84263d55307	2053	}
AnnaBridge	167:e84263d55307	2054
AnnaBridge	167:e84263d55307	2055	/**
AnnaBridge	167:e84263d55307	2056	* @brief Abort ongoing transfer (Interrupt mode).
AnnaBridge	167:e84263d55307	2057	* @param hspi SPI handle.
AnnaBridge	167:e84263d55307	2058	* @note This procedure could be used for aborting any ongoing transfer (Tx and Rx),
AnnaBridge	167:e84263d55307	2059	* started in Interrupt or DMA mode.
AnnaBridge	167:e84263d55307	2060	* This procedure performs following operations :
AnnaBridge	167:e84263d55307	2061	* - Disable SPI Interrupts (depending of transfer direction)
AnnaBridge	167:e84263d55307	2062	* - Disable the DMA transfer in the peripheral register (if enabled)
AnnaBridge	167:e84263d55307	2063	* - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
AnnaBridge	167:e84263d55307	2064	* - Set handle State to READY
AnnaBridge	167:e84263d55307	2065	* - At abort completion, call user abort complete callback
AnnaBridge	167:e84263d55307	2066	* @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
AnnaBridge	167:e84263d55307	2067	* considered as completed only when user abort complete callback is executed (not when exiting function).
AnnaBridge	167:e84263d55307	2068	* @retval HAL status
AnnaBridge	167:e84263d55307	2069	*/
AnnaBridge	167:e84263d55307	2070	HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi)
AnnaBridge	167:e84263d55307	2071	{
AnnaBridge	167:e84263d55307	2072	HAL_StatusTypeDef errorcode;
AnnaBridge	167:e84263d55307	2073	uint32_t abortcplt ;
AnnaBridge	167:e84263d55307	2074	__IO uint32_t count, resetcount;
AnnaBridge	167:e84263d55307	2075
AnnaBridge	167:e84263d55307	2076	/* Initialized local variable */
AnnaBridge	167:e84263d55307	2077	errorcode = HAL_OK;
AnnaBridge	167:e84263d55307	2078	abortcplt = 1U;
AnnaBridge	167:e84263d55307	2079	resetcount = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
AnnaBridge	167:e84263d55307	2080	count = resetcount;
AnnaBridge	167:e84263d55307	2081
AnnaBridge	167:e84263d55307	2082	/* Change Rx and Tx Irq Handler to Disable TXEIE, RXNEIE and ERRIE interrupts */
AnnaBridge	167:e84263d55307	2083	if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE))
AnnaBridge	167:e84263d55307	2084	{
AnnaBridge	167:e84263d55307	2085	hspi->TxISR = SPI_AbortTx_ISR;
AnnaBridge	167:e84263d55307	2086	/* Wait HAL_SPI_STATE_ABORT state */
AnnaBridge	167:e84263d55307	2087	do
AnnaBridge	167:e84263d55307	2088	{
AnnaBridge	167:e84263d55307	2089	if (count-- == 0U)
AnnaBridge	167:e84263d55307	2090	{
AnnaBridge	167:e84263d55307	2091	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
AnnaBridge	167:e84263d55307	2092	break;
AnnaBridge	167:e84263d55307	2093	}
AnnaBridge	167:e84263d55307	2094	}
AnnaBridge	167:e84263d55307	2095	while (hspi->State != HAL_SPI_STATE_ABORT);
AnnaBridge	167:e84263d55307	2096	/* Reset Timeout Counter */
AnnaBridge	167:e84263d55307	2097	count = resetcount;
AnnaBridge	167:e84263d55307	2098	}
AnnaBridge	167:e84263d55307	2099
AnnaBridge	167:e84263d55307	2100	if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE))
AnnaBridge	167:e84263d55307	2101	{
AnnaBridge	167:e84263d55307	2102	hspi->RxISR = SPI_AbortRx_ISR;
AnnaBridge	167:e84263d55307	2103	/* Wait HAL_SPI_STATE_ABORT state */
AnnaBridge	167:e84263d55307	2104	do
AnnaBridge	167:e84263d55307	2105	{
AnnaBridge	167:e84263d55307	2106	if (count-- == 0U)
AnnaBridge	167:e84263d55307	2107	{
AnnaBridge	167:e84263d55307	2108	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
AnnaBridge	167:e84263d55307	2109	break;
AnnaBridge	167:e84263d55307	2110	}
AnnaBridge	167:e84263d55307	2111	}
AnnaBridge	167:e84263d55307	2112	while (hspi->State != HAL_SPI_STATE_ABORT);
AnnaBridge	167:e84263d55307	2113	/* Reset Timeout Counter */
AnnaBridge	167:e84263d55307	2114	count = resetcount;
AnnaBridge	167:e84263d55307	2115	}
AnnaBridge	167:e84263d55307	2116
AnnaBridge	167:e84263d55307	2117	/* Clear ERRIE interrupts in case of DMA Mode */
AnnaBridge	167:e84263d55307	2118	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE);
AnnaBridge	167:e84263d55307	2119
AnnaBridge	167:e84263d55307	2120	/* If DMA Tx and/or DMA Rx Handles are associated to SPI Handle, DMA Abort complete callbacks should be initialised
AnnaBridge	167:e84263d55307	2121	before any call to DMA Abort functions */
AnnaBridge	167:e84263d55307	2122	/* DMA Tx Handle is valid */
AnnaBridge	167:e84263d55307	2123	if (hspi->hdmatx != NULL)
AnnaBridge	167:e84263d55307	2124	{
AnnaBridge	167:e84263d55307	2125	/* Set DMA Abort Complete callback if UART DMA Tx request if enabled.
AnnaBridge	167:e84263d55307	2126	Otherwise, set it to NULL */
AnnaBridge	167:e84263d55307	2127	if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN))
AnnaBridge	167:e84263d55307	2128	{
AnnaBridge	167:e84263d55307	2129	hspi->hdmatx->XferAbortCallback = SPI_DMATxAbortCallback;
AnnaBridge	167:e84263d55307	2130	}
AnnaBridge	167:e84263d55307	2131	else
AnnaBridge	167:e84263d55307	2132	{
AnnaBridge	167:e84263d55307	2133	hspi->hdmatx->XferAbortCallback = NULL;
AnnaBridge	167:e84263d55307	2134	}
AnnaBridge	167:e84263d55307	2135	}
AnnaBridge	167:e84263d55307	2136	/* DMA Rx Handle is valid */
AnnaBridge	167:e84263d55307	2137	if (hspi->hdmarx != NULL)
AnnaBridge	167:e84263d55307	2138	{
AnnaBridge	167:e84263d55307	2139	/* Set DMA Abort Complete callback if UART DMA Rx request if enabled.
AnnaBridge	167:e84263d55307	2140	Otherwise, set it to NULL */
AnnaBridge	167:e84263d55307	2141	if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN))
AnnaBridge	167:e84263d55307	2142	{
AnnaBridge	167:e84263d55307	2143	hspi->hdmarx->XferAbortCallback = SPI_DMARxAbortCallback;
AnnaBridge	167:e84263d55307	2144	}
AnnaBridge	167:e84263d55307	2145	else
AnnaBridge	167:e84263d55307	2146	{
AnnaBridge	167:e84263d55307	2147	hspi->hdmarx->XferAbortCallback = NULL;
AnnaBridge	167:e84263d55307	2148	}
AnnaBridge	167:e84263d55307	2149	}
AnnaBridge	167:e84263d55307	2150
AnnaBridge	167:e84263d55307	2151	/* Disable the SPI DMA Tx or the SPI Rx request if enabled */
AnnaBridge	167:e84263d55307	2152	if ((HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN)) && (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN)))
AnnaBridge	167:e84263d55307	2153	{
AnnaBridge	167:e84263d55307	2154	/* Abort the SPI DMA Tx Stream/Channel */
AnnaBridge	167:e84263d55307	2155	if (hspi->hdmatx != NULL)
AnnaBridge	167:e84263d55307	2156	{
AnnaBridge	167:e84263d55307	2157	/* Abort DMA Tx Handle linked to SPI Peripheral */
AnnaBridge	167:e84263d55307	2158	if (HAL_DMA_Abort_IT(hspi->hdmatx) != HAL_OK)
AnnaBridge	167:e84263d55307	2159	{
AnnaBridge	167:e84263d55307	2160	hspi->hdmatx->XferAbortCallback = NULL;
AnnaBridge	167:e84263d55307	2161	hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
AnnaBridge	167:e84263d55307	2162	}
AnnaBridge	167:e84263d55307	2163	else
AnnaBridge	167:e84263d55307	2164	{
AnnaBridge	167:e84263d55307	2165	abortcplt = 0U;
AnnaBridge	167:e84263d55307	2166	}
AnnaBridge	167:e84263d55307	2167	}
AnnaBridge	167:e84263d55307	2168	/* Abort the SPI DMA Rx Stream/Channel */
AnnaBridge	167:e84263d55307	2169	if (hspi->hdmarx != NULL)
AnnaBridge	167:e84263d55307	2170	{
AnnaBridge	167:e84263d55307	2171	/* Abort DMA Rx Handle linked to SPI Peripheral */
AnnaBridge	167:e84263d55307	2172	if (HAL_DMA_Abort_IT(hspi->hdmarx) != HAL_OK)
AnnaBridge	167:e84263d55307	2173	{
AnnaBridge	167:e84263d55307	2174	hspi->hdmarx->XferAbortCallback = NULL;
AnnaBridge	167:e84263d55307	2175	hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
AnnaBridge	167:e84263d55307	2176	abortcplt = 1U;
AnnaBridge	167:e84263d55307	2177	}
AnnaBridge	167:e84263d55307	2178	else
AnnaBridge	167:e84263d55307	2179	{
AnnaBridge	167:e84263d55307	2180	abortcplt = 0U;
AnnaBridge	167:e84263d55307	2181	}
AnnaBridge	167:e84263d55307	2182	}
AnnaBridge	167:e84263d55307	2183	}
AnnaBridge	167:e84263d55307	2184
AnnaBridge	167:e84263d55307	2185	/* Disable the SPI DMA Tx or the SPI Rx request if enabled */
AnnaBridge	167:e84263d55307	2186	if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN))
AnnaBridge	167:e84263d55307	2187	{
AnnaBridge	167:e84263d55307	2188	/* Abort the SPI DMA Tx Stream/Channel */
AnnaBridge	167:e84263d55307	2189	if (hspi->hdmatx != NULL)
AnnaBridge	167:e84263d55307	2190	{
AnnaBridge	167:e84263d55307	2191	/* Abort DMA Tx Handle linked to SPI Peripheral */
AnnaBridge	167:e84263d55307	2192	if (HAL_DMA_Abort_IT(hspi->hdmatx) != HAL_OK)
AnnaBridge	167:e84263d55307	2193	{
AnnaBridge	167:e84263d55307	2194	hspi->hdmatx->XferAbortCallback = NULL;
AnnaBridge	167:e84263d55307	2195	hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
AnnaBridge	167:e84263d55307	2196	}
AnnaBridge	167:e84263d55307	2197	else
AnnaBridge	167:e84263d55307	2198	{
AnnaBridge	167:e84263d55307	2199	abortcplt = 0U;
AnnaBridge	167:e84263d55307	2200	}
AnnaBridge	167:e84263d55307	2201	}
AnnaBridge	167:e84263d55307	2202	}
AnnaBridge	167:e84263d55307	2203	/* Disable the SPI DMA Tx or the SPI Rx request if enabled */
AnnaBridge	167:e84263d55307	2204	if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN))
AnnaBridge	167:e84263d55307	2205	{
AnnaBridge	167:e84263d55307	2206	/* Abort the SPI DMA Rx Stream/Channel */
AnnaBridge	167:e84263d55307	2207	if (hspi->hdmarx != NULL)
AnnaBridge	167:e84263d55307	2208	{
AnnaBridge	167:e84263d55307	2209	/* Abort DMA Rx Handle linked to SPI Peripheral */
AnnaBridge	167:e84263d55307	2210	if (HAL_DMA_Abort_IT(hspi->hdmarx) != HAL_OK)
AnnaBridge	167:e84263d55307	2211	{
AnnaBridge	167:e84263d55307	2212	hspi->hdmarx->XferAbortCallback = NULL;
AnnaBridge	167:e84263d55307	2213	hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
AnnaBridge	167:e84263d55307	2214	}
AnnaBridge	167:e84263d55307	2215	else
AnnaBridge	167:e84263d55307	2216	{
AnnaBridge	167:e84263d55307	2217	abortcplt = 0U;
AnnaBridge	167:e84263d55307	2218	}
AnnaBridge	167:e84263d55307	2219	}
AnnaBridge	167:e84263d55307	2220	}
AnnaBridge	167:e84263d55307	2221
AnnaBridge	167:e84263d55307	2222	if (abortcplt == 1U)
AnnaBridge	167:e84263d55307	2223	{
AnnaBridge	167:e84263d55307	2224	/* Reset Tx and Rx transfer counters */
AnnaBridge	167:e84263d55307	2225	hspi->RxXferCount = 0U;
AnnaBridge	167:e84263d55307	2226	hspi->TxXferCount = 0U;
AnnaBridge	167:e84263d55307	2227
AnnaBridge	167:e84263d55307	2228	/* Check error during Abort procedure */
AnnaBridge	167:e84263d55307	2229	if (hspi->ErrorCode == HAL_SPI_ERROR_ABORT)
AnnaBridge	167:e84263d55307	2230	{
AnnaBridge	167:e84263d55307	2231	/* return HAL_Error in case of error during Abort procedure */
AnnaBridge	167:e84263d55307	2232	errorcode = HAL_ERROR;
AnnaBridge	167:e84263d55307	2233	}
AnnaBridge	167:e84263d55307	2234	else
AnnaBridge	167:e84263d55307	2235	{
AnnaBridge	167:e84263d55307	2236	/* Reset errorCode */
AnnaBridge	167:e84263d55307	2237	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
AnnaBridge	167:e84263d55307	2238	}
AnnaBridge	167:e84263d55307	2239
AnnaBridge	167:e84263d55307	2240	/* Clear the Error flags in the SR register */
AnnaBridge	167:e84263d55307	2241	__HAL_SPI_CLEAR_OVRFLAG(hspi);
AnnaBridge	167:e84263d55307	2242	__HAL_SPI_CLEAR_FREFLAG(hspi);
AnnaBridge	167:e84263d55307	2243
AnnaBridge	167:e84263d55307	2244	/* Restore hspi->State to Ready */
AnnaBridge	167:e84263d55307	2245	hspi->State = HAL_SPI_STATE_READY;
AnnaBridge	167:e84263d55307	2246
AnnaBridge	167:e84263d55307	2247	/* As no DMA to be aborted, call directly user Abort complete callback */
AnnaBridge	167:e84263d55307	2248	HAL_SPI_AbortCpltCallback(hspi);
AnnaBridge	167:e84263d55307	2249	}
AnnaBridge	167:e84263d55307	2250
AnnaBridge	167:e84263d55307	2251	return errorcode;
AnnaBridge	167:e84263d55307	2252	}
AnnaBridge	167:e84263d55307	2253
AnnaBridge	167:e84263d55307	2254	/**
AnnaBridge	167:e84263d55307	2255	* @brief Pause the DMA Transfer.
AnnaBridge	181:57724642e740	2256	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	2257	* the configuration information for the specified SPI module.
<>	144:ef7eb2e8f9f7	2258	* @retval HAL status
<>	144:ef7eb2e8f9f7	2259	*/
<>	144:ef7eb2e8f9f7	2260	HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi)
<>	144:ef7eb2e8f9f7	2261	{
<>	144:ef7eb2e8f9f7	2262	/* Process Locked */
<>	144:ef7eb2e8f9f7	2263	__HAL_LOCK(hspi);
<>	144:ef7eb2e8f9f7	2264
<>	144:ef7eb2e8f9f7	2265	/* Disable the SPI DMA Tx & Rx requests */
<>	144:ef7eb2e8f9f7	2266	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN \| SPI_CR2_RXDMAEN);
<>	144:ef7eb2e8f9f7	2267
<>	144:ef7eb2e8f9f7	2268	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	2269	__HAL_UNLOCK(hspi);
<>	144:ef7eb2e8f9f7	2270
<>	144:ef7eb2e8f9f7	2271	return HAL_OK;
<>	144:ef7eb2e8f9f7	2272	}
<>	144:ef7eb2e8f9f7	2273
<>	144:ef7eb2e8f9f7	2274	/**
AnnaBridge	167:e84263d55307	2275	* @brief Resume the DMA Transfer.
AnnaBridge	181:57724642e740	2276	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	2277	* the configuration information for the specified SPI module.
<>	144:ef7eb2e8f9f7	2278	* @retval HAL status
<>	144:ef7eb2e8f9f7	2279	*/
<>	144:ef7eb2e8f9f7	2280	HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi)
<>	144:ef7eb2e8f9f7	2281	{
<>	144:ef7eb2e8f9f7	2282	/* Process Locked */
<>	144:ef7eb2e8f9f7	2283	__HAL_LOCK(hspi);
<>	144:ef7eb2e8f9f7	2284
<>	144:ef7eb2e8f9f7	2285	/* Enable the SPI DMA Tx & Rx requests */
<>	144:ef7eb2e8f9f7	2286	SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN \| SPI_CR2_RXDMAEN);
<>	144:ef7eb2e8f9f7	2287
<>	144:ef7eb2e8f9f7	2288	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	2289	__HAL_UNLOCK(hspi);
<>	144:ef7eb2e8f9f7	2290
<>	144:ef7eb2e8f9f7	2291	return HAL_OK;
<>	144:ef7eb2e8f9f7	2292	}
<>	144:ef7eb2e8f9f7	2293
<>	144:ef7eb2e8f9f7	2294	/**
AnnaBridge	181:57724642e740	2295	* @brief Stop the DMA Transfer.
AnnaBridge	181:57724642e740	2296	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	2297	* the configuration information for the specified SPI module.
<>	144:ef7eb2e8f9f7	2298	* @retval HAL status
<>	144:ef7eb2e8f9f7	2299	*/
<>	144:ef7eb2e8f9f7	2300	HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi)
<>	144:ef7eb2e8f9f7	2301	{
<>	144:ef7eb2e8f9f7	2302	/* The Lock is not implemented on this API to allow the user application
<>	144:ef7eb2e8f9f7	2303	to call the HAL SPI API under callbacks HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback():
<>	144:ef7eb2e8f9f7	2304	when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated
<>	144:ef7eb2e8f9f7	2305	and the correspond call back is executed HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback()
<>	144:ef7eb2e8f9f7	2306	*/
<>	144:ef7eb2e8f9f7	2307
AnnaBridge	167:e84263d55307	2308	/* Abort the SPI DMA tx Stream/Channel */
AnnaBridge	167:e84263d55307	2309	if (hspi->hdmatx != NULL)
<>	144:ef7eb2e8f9f7	2310	{
<>	144:ef7eb2e8f9f7	2311	HAL_DMA_Abort(hspi->hdmatx);
<>	144:ef7eb2e8f9f7	2312	}
AnnaBridge	167:e84263d55307	2313	/* Abort the SPI DMA rx Stream/Channel */
AnnaBridge	167:e84263d55307	2314	if (hspi->hdmarx != NULL)
<>	144:ef7eb2e8f9f7	2315	{
<>	144:ef7eb2e8f9f7	2316	HAL_DMA_Abort(hspi->hdmarx);
<>	144:ef7eb2e8f9f7	2317	}
<>	144:ef7eb2e8f9f7	2318
<>	144:ef7eb2e8f9f7	2319	/* Disable the SPI DMA Tx & Rx requests */
<>	144:ef7eb2e8f9f7	2320	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN \| SPI_CR2_RXDMAEN);
<>	144:ef7eb2e8f9f7	2321	hspi->State = HAL_SPI_STATE_READY;
<>	144:ef7eb2e8f9f7	2322	return HAL_OK;
<>	144:ef7eb2e8f9f7	2323	}
<>	144:ef7eb2e8f9f7	2324
<>	144:ef7eb2e8f9f7	2325	/**
<>	144:ef7eb2e8f9f7	2326	* @brief Handle SPI interrupt request.
AnnaBridge	181:57724642e740	2327	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	2328	* the configuration information for the specified SPI module.
<>	144:ef7eb2e8f9f7	2329	* @retval None
<>	144:ef7eb2e8f9f7	2330	*/
<>	144:ef7eb2e8f9f7	2331	void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi)
<>	144:ef7eb2e8f9f7	2332	{
<>	144:ef7eb2e8f9f7	2333	uint32_t itsource = hspi->Instance->CR2;
<>	144:ef7eb2e8f9f7	2334	uint32_t itflag = hspi->Instance->SR;
<>	144:ef7eb2e8f9f7	2335
<>	144:ef7eb2e8f9f7	2336	/* SPI in mode Receiver ----------------------------------------------------*/
AnnaBridge	167:e84263d55307	2337	if (((itflag & SPI_FLAG_OVR) == RESET) &&
AnnaBridge	167:e84263d55307	2338	((itflag & SPI_FLAG_RXNE) != RESET) && ((itsource & SPI_IT_RXNE) != RESET))
<>	144:ef7eb2e8f9f7	2339	{
<>	144:ef7eb2e8f9f7	2340	hspi->RxISR(hspi);
<>	144:ef7eb2e8f9f7	2341	return;
<>	144:ef7eb2e8f9f7	2342	}
<>	144:ef7eb2e8f9f7	2343
AnnaBridge	167:e84263d55307	2344	/* SPI in mode Transmitter -------------------------------------------------*/
AnnaBridge	167:e84263d55307	2345	if (((itflag & SPI_FLAG_TXE) != RESET) && ((itsource & SPI_IT_TXE) != RESET))
<>	144:ef7eb2e8f9f7	2346	{
<>	144:ef7eb2e8f9f7	2347	hspi->TxISR(hspi);
<>	144:ef7eb2e8f9f7	2348	return;
<>	144:ef7eb2e8f9f7	2349	}
<>	144:ef7eb2e8f9f7	2350
AnnaBridge	167:e84263d55307	2351	/* SPI in Error Treatment --------------------------------------------------*/
AnnaBridge	167:e84263d55307	2352	if (((itflag & (SPI_FLAG_MODF \| SPI_FLAG_OVR \| SPI_FLAG_FRE)) != RESET) && ((itsource & SPI_IT_ERR) != RESET))
<>	144:ef7eb2e8f9f7	2353	{
AnnaBridge	167:e84263d55307	2354	/* SPI Overrun error interrupt occurred ----------------------------------*/
AnnaBridge	167:e84263d55307	2355	if ((itflag & SPI_FLAG_OVR) != RESET)
<>	144:ef7eb2e8f9f7	2356	{
AnnaBridge	167:e84263d55307	2357	if (hspi->State != HAL_SPI_STATE_BUSY_TX)
<>	144:ef7eb2e8f9f7	2358	{
AnnaBridge	167:e84263d55307	2359	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_OVR);
<>	144:ef7eb2e8f9f7	2360	__HAL_SPI_CLEAR_OVRFLAG(hspi);
<>	144:ef7eb2e8f9f7	2361	}
<>	144:ef7eb2e8f9f7	2362	else
<>	144:ef7eb2e8f9f7	2363	{
AnnaBridge	167:e84263d55307	2364	__HAL_SPI_CLEAR_OVRFLAG(hspi);
<>	144:ef7eb2e8f9f7	2365	return;
<>	144:ef7eb2e8f9f7	2366	}
<>	144:ef7eb2e8f9f7	2367	}
<>	144:ef7eb2e8f9f7	2368
AnnaBridge	167:e84263d55307	2369	/* SPI Mode Fault error interrupt occurred -------------------------------*/
AnnaBridge	167:e84263d55307	2370	if ((itflag & SPI_FLAG_MODF) != RESET)
<>	144:ef7eb2e8f9f7	2371	{
AnnaBridge	167:e84263d55307	2372	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_MODF);
<>	144:ef7eb2e8f9f7	2373	__HAL_SPI_CLEAR_MODFFLAG(hspi);
<>	144:ef7eb2e8f9f7	2374	}
<>	144:ef7eb2e8f9f7	2375
AnnaBridge	167:e84263d55307	2376	/* SPI Frame error interrupt occurred ------------------------------------*/
AnnaBridge	167:e84263d55307	2377	if ((itflag & SPI_FLAG_FRE) != RESET)
<>	144:ef7eb2e8f9f7	2378	{
AnnaBridge	167:e84263d55307	2379	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FRE);
<>	144:ef7eb2e8f9f7	2380	__HAL_SPI_CLEAR_FREFLAG(hspi);
<>	144:ef7eb2e8f9f7	2381	}
<>	144:ef7eb2e8f9f7	2382
AnnaBridge	167:e84263d55307	2383	if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
AnnaBridge	167:e84263d55307	2384	{
AnnaBridge	167:e84263d55307	2385	/* Disable all interrupts */
AnnaBridge	167:e84263d55307	2386	__HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE \| SPI_IT_TXE \| SPI_IT_ERR);
AnnaBridge	167:e84263d55307	2387
AnnaBridge	167:e84263d55307	2388	hspi->State = HAL_SPI_STATE_READY;
AnnaBridge	167:e84263d55307	2389	/* Disable the SPI DMA requests if enabled */
AnnaBridge	167:e84263d55307	2390	if ((HAL_IS_BIT_SET(itsource, SPI_CR2_TXDMAEN)) \|\| (HAL_IS_BIT_SET(itsource, SPI_CR2_RXDMAEN)))
AnnaBridge	167:e84263d55307	2391	{
AnnaBridge	167:e84263d55307	2392	CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXDMAEN \| SPI_CR2_RXDMAEN));
AnnaBridge	167:e84263d55307	2393
AnnaBridge	167:e84263d55307	2394	/* Abort the SPI DMA Rx channel */
AnnaBridge	167:e84263d55307	2395	if (hspi->hdmarx != NULL)
AnnaBridge	167:e84263d55307	2396	{
AnnaBridge	167:e84263d55307	2397	/* Set the SPI DMA Abort callback :
AnnaBridge	167:e84263d55307	2398	will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */
AnnaBridge	167:e84263d55307	2399	hspi->hdmarx->XferAbortCallback = SPI_DMAAbortOnError;
AnnaBridge	167:e84263d55307	2400	HAL_DMA_Abort_IT(hspi->hdmarx);
AnnaBridge	167:e84263d55307	2401	}
AnnaBridge	167:e84263d55307	2402	/* Abort the SPI DMA Tx channel */
AnnaBridge	167:e84263d55307	2403	if (hspi->hdmatx != NULL)
AnnaBridge	167:e84263d55307	2404	{
AnnaBridge	167:e84263d55307	2405	/* Set the SPI DMA Abort callback :
AnnaBridge	167:e84263d55307	2406	will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */
AnnaBridge	167:e84263d55307	2407	hspi->hdmatx->XferAbortCallback = SPI_DMAAbortOnError;
AnnaBridge	167:e84263d55307	2408	HAL_DMA_Abort_IT(hspi->hdmatx);
AnnaBridge	167:e84263d55307	2409	}
AnnaBridge	167:e84263d55307	2410	}
AnnaBridge	167:e84263d55307	2411	else
AnnaBridge	167:e84263d55307	2412	{
AnnaBridge	167:e84263d55307	2413	/* Call user error callback */
AnnaBridge	167:e84263d55307	2414	HAL_SPI_ErrorCallback(hspi);
AnnaBridge	167:e84263d55307	2415	}
AnnaBridge	167:e84263d55307	2416	}
<>	144:ef7eb2e8f9f7	2417	return;
<>	144:ef7eb2e8f9f7	2418	}
<>	144:ef7eb2e8f9f7	2419	}
<>	144:ef7eb2e8f9f7	2420
<>	144:ef7eb2e8f9f7	2421	/**
AnnaBridge	181:57724642e740	2422	* @brief Tx Transfer completed callback.
AnnaBridge	181:57724642e740	2423	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	2424	* the configuration information for SPI module.
<>	144:ef7eb2e8f9f7	2425	* @retval None
<>	144:ef7eb2e8f9f7	2426	*/
<>	144:ef7eb2e8f9f7	2427	__weak void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi)
<>	144:ef7eb2e8f9f7	2428	{
<>	144:ef7eb2e8f9f7	2429	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	2430	UNUSED(hspi);
<>	144:ef7eb2e8f9f7	2431
<>	144:ef7eb2e8f9f7	2432	/* NOTE : This function should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	2433	the HAL_SPI_TxCpltCallback should be implemented in the user file
<>	144:ef7eb2e8f9f7	2434	*/
<>	144:ef7eb2e8f9f7	2435	}
<>	144:ef7eb2e8f9f7	2436
<>	144:ef7eb2e8f9f7	2437	/**
AnnaBridge	181:57724642e740	2438	* @brief Rx Transfer completed callback.
AnnaBridge	181:57724642e740	2439	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	2440	* the configuration information for SPI module.
<>	144:ef7eb2e8f9f7	2441	* @retval None
<>	144:ef7eb2e8f9f7	2442	*/
<>	144:ef7eb2e8f9f7	2443	__weak void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi)
<>	144:ef7eb2e8f9f7	2444	{
<>	144:ef7eb2e8f9f7	2445	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	2446	UNUSED(hspi);
<>	144:ef7eb2e8f9f7	2447
<>	144:ef7eb2e8f9f7	2448	/* NOTE : This function should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	2449	the HAL_SPI_RxCpltCallback should be implemented in the user file
<>	144:ef7eb2e8f9f7	2450	*/
<>	144:ef7eb2e8f9f7	2451	}
<>	144:ef7eb2e8f9f7	2452
<>	144:ef7eb2e8f9f7	2453	/**
AnnaBridge	181:57724642e740	2454	* @brief Tx and Rx Transfer completed callback.
AnnaBridge	181:57724642e740	2455	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	2456	* the configuration information for SPI module.
<>	144:ef7eb2e8f9f7	2457	* @retval None
<>	144:ef7eb2e8f9f7	2458	*/
<>	144:ef7eb2e8f9f7	2459	__weak void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi)
<>	144:ef7eb2e8f9f7	2460	{
<>	144:ef7eb2e8f9f7	2461	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	2462	UNUSED(hspi);
<>	144:ef7eb2e8f9f7	2463
<>	144:ef7eb2e8f9f7	2464	/* NOTE : This function should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	2465	the HAL_SPI_TxRxCpltCallback should be implemented in the user file
<>	144:ef7eb2e8f9f7	2466	*/
<>	144:ef7eb2e8f9f7	2467	}
<>	144:ef7eb2e8f9f7	2468
<>	144:ef7eb2e8f9f7	2469	/**
AnnaBridge	181:57724642e740	2470	* @brief Tx Half Transfer completed callback.
AnnaBridge	181:57724642e740	2471	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	2472	* the configuration information for SPI module.
<>	144:ef7eb2e8f9f7	2473	* @retval None
<>	144:ef7eb2e8f9f7	2474	*/
<>	144:ef7eb2e8f9f7	2475	__weak void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi)
<>	144:ef7eb2e8f9f7	2476	{
<>	144:ef7eb2e8f9f7	2477	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	2478	UNUSED(hspi);
<>	144:ef7eb2e8f9f7	2479
<>	144:ef7eb2e8f9f7	2480	/* NOTE : This function should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	2481	the HAL_SPI_TxHalfCpltCallback should be implemented in the user file
<>	144:ef7eb2e8f9f7	2482	*/
<>	144:ef7eb2e8f9f7	2483	}
<>	144:ef7eb2e8f9f7	2484
<>	144:ef7eb2e8f9f7	2485	/**
AnnaBridge	181:57724642e740	2486	* @brief Rx Half Transfer completed callback.
AnnaBridge	181:57724642e740	2487	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	2488	* the configuration information for SPI module.
<>	144:ef7eb2e8f9f7	2489	* @retval None
<>	144:ef7eb2e8f9f7	2490	*/
<>	144:ef7eb2e8f9f7	2491	__weak void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi)
<>	144:ef7eb2e8f9f7	2492	{
<>	144:ef7eb2e8f9f7	2493	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	2494	UNUSED(hspi);
<>	144:ef7eb2e8f9f7	2495
<>	144:ef7eb2e8f9f7	2496	/* NOTE : This function should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	2497	the HAL_SPI_RxHalfCpltCallback() should be implemented in the user file
<>	144:ef7eb2e8f9f7	2498	*/
<>	144:ef7eb2e8f9f7	2499	}
<>	144:ef7eb2e8f9f7	2500
<>	144:ef7eb2e8f9f7	2501	/**
AnnaBridge	181:57724642e740	2502	* @brief Tx and Rx Half Transfer callback.
AnnaBridge	181:57724642e740	2503	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	2504	* the configuration information for SPI module.
<>	144:ef7eb2e8f9f7	2505	* @retval None
<>	144:ef7eb2e8f9f7	2506	*/
<>	144:ef7eb2e8f9f7	2507	__weak void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi)
<>	144:ef7eb2e8f9f7	2508	{
<>	144:ef7eb2e8f9f7	2509	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	2510	UNUSED(hspi);
<>	144:ef7eb2e8f9f7	2511
<>	144:ef7eb2e8f9f7	2512	/* NOTE : This function should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	2513	the HAL_SPI_TxRxHalfCpltCallback() should be implemented in the user file
<>	144:ef7eb2e8f9f7	2514	*/
<>	144:ef7eb2e8f9f7	2515	}
<>	144:ef7eb2e8f9f7	2516
<>	144:ef7eb2e8f9f7	2517	/**
AnnaBridge	181:57724642e740	2518	* @brief SPI error callback.
AnnaBridge	181:57724642e740	2519	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	2520	* the configuration information for SPI module.
<>	144:ef7eb2e8f9f7	2521	* @retval None
<>	144:ef7eb2e8f9f7	2522	*/
<>	144:ef7eb2e8f9f7	2523	__weak void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi)
<>	144:ef7eb2e8f9f7	2524	{
<>	144:ef7eb2e8f9f7	2525	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	2526	UNUSED(hspi);
<>	144:ef7eb2e8f9f7	2527
<>	144:ef7eb2e8f9f7	2528	/* NOTE : This function should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	2529	the HAL_SPI_ErrorCallback should be implemented in the user file
<>	144:ef7eb2e8f9f7	2530	*/
<>	144:ef7eb2e8f9f7	2531	/* NOTE : The ErrorCode parameter in the hspi handle is updated by the SPI processes
<>	144:ef7eb2e8f9f7	2532	and user can use HAL_SPI_GetError() API to check the latest error occurred
<>	144:ef7eb2e8f9f7	2533	*/
<>	144:ef7eb2e8f9f7	2534	}
<>	144:ef7eb2e8f9f7	2535
<>	144:ef7eb2e8f9f7	2536	/**
AnnaBridge	167:e84263d55307	2537	* @brief SPI Abort Complete callback.
AnnaBridge	167:e84263d55307	2538	* @param hspi SPI handle.
AnnaBridge	167:e84263d55307	2539	* @retval None
AnnaBridge	167:e84263d55307	2540	*/
AnnaBridge	167:e84263d55307	2541	__weak void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi)
AnnaBridge	167:e84263d55307	2542	{
AnnaBridge	167:e84263d55307	2543	/* Prevent unused argument(s) compilation warning */
AnnaBridge	167:e84263d55307	2544	UNUSED(hspi);
AnnaBridge	167:e84263d55307	2545
AnnaBridge	167:e84263d55307	2546	/* NOTE : This function should not be modified, when the callback is needed,
AnnaBridge	167:e84263d55307	2547	the HAL_SPI_AbortCpltCallback can be implemented in the user file.
AnnaBridge	167:e84263d55307	2548	*/
AnnaBridge	167:e84263d55307	2549	}
AnnaBridge	167:e84263d55307	2550
AnnaBridge	167:e84263d55307	2551	/**
<>	144:ef7eb2e8f9f7	2552	* @}
<>	144:ef7eb2e8f9f7	2553	*/
<>	144:ef7eb2e8f9f7	2554
<>	144:ef7eb2e8f9f7	2555	/** @defgroup SPI_Exported_Functions_Group3 Peripheral State and Errors functions
AnnaBridge	167:e84263d55307	2556	* @brief SPI control functions
<>	144:ef7eb2e8f9f7	2557	*
<>	144:ef7eb2e8f9f7	2558	@verbatim
<>	144:ef7eb2e8f9f7	2559	===============================================================================
<>	144:ef7eb2e8f9f7	2560	##### Peripheral State and Errors functions #####
<>	144:ef7eb2e8f9f7	2561	===============================================================================
<>	144:ef7eb2e8f9f7	2562	[..]
<>	144:ef7eb2e8f9f7	2563	This subsection provides a set of functions allowing to control the SPI.
<>	144:ef7eb2e8f9f7	2564	(+) HAL_SPI_GetState() API can be helpful to check in run-time the state of the SPI peripheral
<>	144:ef7eb2e8f9f7	2565	(+) HAL_SPI_GetError() check in run-time Errors occurring during communication
<>	144:ef7eb2e8f9f7	2566	@endverbatim
<>	144:ef7eb2e8f9f7	2567	* @{
<>	144:ef7eb2e8f9f7	2568	*/
<>	144:ef7eb2e8f9f7	2569
<>	144:ef7eb2e8f9f7	2570	/**
<>	144:ef7eb2e8f9f7	2571	* @brief Return the SPI handle state.
AnnaBridge	181:57724642e740	2572	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	2573	* the configuration information for SPI module.
<>	144:ef7eb2e8f9f7	2574	* @retval SPI state
<>	144:ef7eb2e8f9f7	2575	*/
<>	144:ef7eb2e8f9f7	2576	HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi)
<>	144:ef7eb2e8f9f7	2577	{
<>	144:ef7eb2e8f9f7	2578	/* Return SPI handle state */
<>	144:ef7eb2e8f9f7	2579	return hspi->State;
<>	144:ef7eb2e8f9f7	2580	}
<>	144:ef7eb2e8f9f7	2581
<>	144:ef7eb2e8f9f7	2582	/**
<>	144:ef7eb2e8f9f7	2583	* @brief Return the SPI error code.
AnnaBridge	181:57724642e740	2584	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	2585	* the configuration information for SPI module.
<>	144:ef7eb2e8f9f7	2586	* @retval SPI error code in bitmap format
<>	144:ef7eb2e8f9f7	2587	*/
<>	144:ef7eb2e8f9f7	2588	uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi)
<>	144:ef7eb2e8f9f7	2589	{
AnnaBridge	167:e84263d55307	2590	/* Return SPI ErrorCode */
<>	144:ef7eb2e8f9f7	2591	return hspi->ErrorCode;
<>	144:ef7eb2e8f9f7	2592	}
<>	144:ef7eb2e8f9f7	2593
<>	144:ef7eb2e8f9f7	2594	/**
<>	144:ef7eb2e8f9f7	2595	* @}
<>	144:ef7eb2e8f9f7	2596	*/
<>	144:ef7eb2e8f9f7	2597
<>	144:ef7eb2e8f9f7	2598	/**
<>	144:ef7eb2e8f9f7	2599	* @}
<>	144:ef7eb2e8f9f7	2600	*/
<>	144:ef7eb2e8f9f7	2601
<>	144:ef7eb2e8f9f7	2602	/** @addtogroup SPI_Private_Functions
AnnaBridge	167:e84263d55307	2603	* @brief Private functions
<>	144:ef7eb2e8f9f7	2604	* @{
<>	144:ef7eb2e8f9f7	2605	*/
<>	144:ef7eb2e8f9f7	2606
<>	144:ef7eb2e8f9f7	2607	/**
AnnaBridge	181:57724642e740	2608	* @brief DMA SPI transmit process complete callback.
AnnaBridge	181:57724642e740	2609	* @param hdma pointer to a DMA_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	2610	* the configuration information for the specified DMA module.
<>	144:ef7eb2e8f9f7	2611	* @retval None
<>	144:ef7eb2e8f9f7	2612	*/
<>	144:ef7eb2e8f9f7	2613	static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma)
<>	144:ef7eb2e8f9f7	2614	{
AnnaBridge	167:e84263d55307	2615	SPI_HandleTypeDef hspi = (SPI_HandleTypeDef )((DMA_HandleTypeDef *)hdma)->Parent;
AnnaBridge	167:e84263d55307	2616	uint32_t tickstart = 0U;
AnnaBridge	167:e84263d55307	2617
AnnaBridge	167:e84263d55307	2618	/* Init tickstart for timeout managment*/
AnnaBridge	167:e84263d55307	2619	tickstart = HAL_GetTick();
AnnaBridge	167:e84263d55307	2620
AnnaBridge	167:e84263d55307	2621	/* DMA Normal Mode */
AnnaBridge	167:e84263d55307	2622	if ((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC)
<>	144:ef7eb2e8f9f7	2623	{
AnnaBridge	167:e84263d55307	2624	/* Disable ERR interrupt */
AnnaBridge	167:e84263d55307	2625	__HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
AnnaBridge	167:e84263d55307	2626
<>	144:ef7eb2e8f9f7	2627	/* Disable Tx DMA Request */
<>	144:ef7eb2e8f9f7	2628	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
<>	144:ef7eb2e8f9f7	2629
<>	144:ef7eb2e8f9f7	2630	/* Check the end of the transaction */
AnnaBridge	167:e84263d55307	2631	if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	2632	{
AnnaBridge	167:e84263d55307	2633	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
<>	144:ef7eb2e8f9f7	2634	}
<>	144:ef7eb2e8f9f7	2635
<>	144:ef7eb2e8f9f7	2636	/* Clear overrun flag in 2 Lines communication mode because received data is not read */
AnnaBridge	167:e84263d55307	2637	if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
<>	144:ef7eb2e8f9f7	2638	{
<>	144:ef7eb2e8f9f7	2639	__HAL_SPI_CLEAR_OVRFLAG(hspi);
<>	144:ef7eb2e8f9f7	2640	}
<>	144:ef7eb2e8f9f7	2641
AnnaBridge	167:e84263d55307	2642	hspi->TxXferCount = 0U;
<>	144:ef7eb2e8f9f7	2643	hspi->State = HAL_SPI_STATE_READY;
<>	144:ef7eb2e8f9f7	2644
AnnaBridge	167:e84263d55307	2645	if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
<>	144:ef7eb2e8f9f7	2646	{
<>	144:ef7eb2e8f9f7	2647	HAL_SPI_ErrorCallback(hspi);
<>	144:ef7eb2e8f9f7	2648	return;
<>	144:ef7eb2e8f9f7	2649	}
<>	144:ef7eb2e8f9f7	2650	}
<>	144:ef7eb2e8f9f7	2651	HAL_SPI_TxCpltCallback(hspi);
<>	144:ef7eb2e8f9f7	2652	}
<>	144:ef7eb2e8f9f7	2653
<>	144:ef7eb2e8f9f7	2654	/**
AnnaBridge	181:57724642e740	2655	* @brief DMA SPI receive process complete callback.
AnnaBridge	181:57724642e740	2656	* @param hdma pointer to a DMA_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	2657	* the configuration information for the specified DMA module.
<>	144:ef7eb2e8f9f7	2658	* @retval None
<>	144:ef7eb2e8f9f7	2659	*/
<>	144:ef7eb2e8f9f7	2660	static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
<>	144:ef7eb2e8f9f7	2661	{
AnnaBridge	167:e84263d55307	2662	SPI_HandleTypeDef hspi = (SPI_HandleTypeDef )((DMA_HandleTypeDef *)hdma)->Parent;
AnnaBridge	167:e84263d55307	2663	uint32_t tickstart = 0U;
AnnaBridge	167:e84263d55307	2664	#if (USE_SPI_CRC != 0U)
AnnaBridge	167:e84263d55307	2665	__IO uint16_t tmpreg = 0U;
AnnaBridge	167:e84263d55307	2666	#endif /* USE_SPI_CRC */
AnnaBridge	167:e84263d55307	2667
AnnaBridge	167:e84263d55307	2668	/* Init tickstart for timeout management*/
AnnaBridge	167:e84263d55307	2669	tickstart = HAL_GetTick();
AnnaBridge	167:e84263d55307	2670
AnnaBridge	167:e84263d55307	2671	/* DMA Normal Mode */
AnnaBridge	167:e84263d55307	2672	if ((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC)
<>	144:ef7eb2e8f9f7	2673	{
AnnaBridge	167:e84263d55307	2674	/* Disable ERR interrupt */
AnnaBridge	167:e84263d55307	2675	__HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
AnnaBridge	167:e84263d55307	2676
AnnaBridge	167:e84263d55307	2677	#if (USE_SPI_CRC != 0U)
<>	144:ef7eb2e8f9f7	2678	/* CRC handling */
AnnaBridge	167:e84263d55307	2679	if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<>	144:ef7eb2e8f9f7	2680	{
AnnaBridge	167:e84263d55307	2681	/* Wait until RXNE flag */
AnnaBridge	167:e84263d55307	2682	if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	2683	{
<>	144:ef7eb2e8f9f7	2684	/* Error on the CRC reception */
AnnaBridge	167:e84263d55307	2685	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
<>	144:ef7eb2e8f9f7	2686	}
AnnaBridge	167:e84263d55307	2687	/* Read CRC */
AnnaBridge	167:e84263d55307	2688	if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
<>	144:ef7eb2e8f9f7	2689	{
<>	144:ef7eb2e8f9f7	2690	tmpreg = hspi->Instance->DR;
AnnaBridge	167:e84263d55307	2691	/* To avoid GCC warning */
AnnaBridge	167:e84263d55307	2692	UNUSED(tmpreg);
<>	144:ef7eb2e8f9f7	2693	}
<>	144:ef7eb2e8f9f7	2694	else
<>	144:ef7eb2e8f9f7	2695	{
<>	144:ef7eb2e8f9f7	2696	tmpreg = (__IO uint8_t )&hspi->Instance->DR;
AnnaBridge	167:e84263d55307	2697	/* To avoid GCC warning */
AnnaBridge	167:e84263d55307	2698	UNUSED(tmpreg);
AnnaBridge	167:e84263d55307	2699
AnnaBridge	167:e84263d55307	2700	if (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)
<>	144:ef7eb2e8f9f7	2701	{
AnnaBridge	167:e84263d55307	2702	if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	2703	{
<>	144:ef7eb2e8f9f7	2704	/* Error on the CRC reception */
AnnaBridge	167:e84263d55307	2705	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
<>	144:ef7eb2e8f9f7	2706	}
<>	144:ef7eb2e8f9f7	2707	tmpreg = (__IO uint8_t )&hspi->Instance->DR;
AnnaBridge	167:e84263d55307	2708	/* To avoid GCC warning */
AnnaBridge	167:e84263d55307	2709	UNUSED(tmpreg);
<>	144:ef7eb2e8f9f7	2710	}
<>	144:ef7eb2e8f9f7	2711	}
<>	144:ef7eb2e8f9f7	2712	}
AnnaBridge	167:e84263d55307	2713	#endif /* USE_SPI_CRC */
<>	144:ef7eb2e8f9f7	2714
<>	144:ef7eb2e8f9f7	2715	/* Disable Rx/Tx DMA Request (done by default to handle the case master rx direction 2 lines) */
<>	144:ef7eb2e8f9f7	2716	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN \| SPI_CR2_RXDMAEN);
<>	144:ef7eb2e8f9f7	2717
<>	144:ef7eb2e8f9f7	2718	/* Check the end of the transaction */
AnnaBridge	167:e84263d55307	2719	if (SPI_EndRxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	2720	{
AnnaBridge	167:e84263d55307	2721	hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
<>	144:ef7eb2e8f9f7	2722	}
<>	144:ef7eb2e8f9f7	2723
AnnaBridge	167:e84263d55307	2724	hspi->RxXferCount = 0U;
<>	144:ef7eb2e8f9f7	2725	hspi->State = HAL_SPI_STATE_READY;
<>	144:ef7eb2e8f9f7	2726
AnnaBridge	167:e84263d55307	2727	#if (USE_SPI_CRC != 0U)
<>	144:ef7eb2e8f9f7	2728	/* Check if CRC error occurred */
AnnaBridge	167:e84263d55307	2729	if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))
<>	144:ef7eb2e8f9f7	2730	{
AnnaBridge	167:e84263d55307	2731	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
<>	144:ef7eb2e8f9f7	2732	__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
<>	144:ef7eb2e8f9f7	2733	}
AnnaBridge	167:e84263d55307	2734	#endif /* USE_SPI_CRC */
AnnaBridge	167:e84263d55307	2735
AnnaBridge	167:e84263d55307	2736	if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
<>	144:ef7eb2e8f9f7	2737	{
<>	144:ef7eb2e8f9f7	2738	HAL_SPI_ErrorCallback(hspi);
<>	144:ef7eb2e8f9f7	2739	return;
<>	144:ef7eb2e8f9f7	2740	}
<>	144:ef7eb2e8f9f7	2741	}
<>	144:ef7eb2e8f9f7	2742	HAL_SPI_RxCpltCallback(hspi);
<>	144:ef7eb2e8f9f7	2743	}
<>	144:ef7eb2e8f9f7	2744
<>	144:ef7eb2e8f9f7	2745	/**
AnnaBridge	167:e84263d55307	2746	* @brief DMA SPI transmit receive process complete callback.
AnnaBridge	181:57724642e740	2747	* @param hdma pointer to a DMA_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	2748	* the configuration information for the specified DMA module.
<>	144:ef7eb2e8f9f7	2749	* @retval None
<>	144:ef7eb2e8f9f7	2750	*/
<>	144:ef7eb2e8f9f7	2751	static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma)
<>	144:ef7eb2e8f9f7	2752	{
AnnaBridge	167:e84263d55307	2753	SPI_HandleTypeDef hspi = (SPI_HandleTypeDef )((DMA_HandleTypeDef *)hdma)->Parent;
AnnaBridge	167:e84263d55307	2754	uint32_t tickstart = 0U;
AnnaBridge	167:e84263d55307	2755	#if (USE_SPI_CRC != 0U)
AnnaBridge	167:e84263d55307	2756	__IO int16_t tmpreg = 0U;
AnnaBridge	167:e84263d55307	2757	#endif /* USE_SPI_CRC */
AnnaBridge	167:e84263d55307	2758	/* Init tickstart for timeout management*/
AnnaBridge	167:e84263d55307	2759	tickstart = HAL_GetTick();
AnnaBridge	167:e84263d55307	2760
AnnaBridge	167:e84263d55307	2761	/* DMA Normal Mode */
AnnaBridge	167:e84263d55307	2762	if ((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC)
<>	144:ef7eb2e8f9f7	2763	{
AnnaBridge	167:e84263d55307	2764	/* Disable ERR interrupt */
AnnaBridge	167:e84263d55307	2765	__HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
AnnaBridge	167:e84263d55307	2766
AnnaBridge	167:e84263d55307	2767	#if (USE_SPI_CRC != 0U)
<>	144:ef7eb2e8f9f7	2768	/* CRC handling */
AnnaBridge	167:e84263d55307	2769	if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<>	144:ef7eb2e8f9f7	2770	{
AnnaBridge	167:e84263d55307	2771	if ((hspi->Init.DataSize == SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_8BIT))
<>	144:ef7eb2e8f9f7	2772	{
AnnaBridge	167:e84263d55307	2773	if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_QUARTER_FULL, SPI_DEFAULT_TIMEOUT,
AnnaBridge	167:e84263d55307	2774	tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	2775	{
<>	144:ef7eb2e8f9f7	2776	/* Error on the CRC reception */
AnnaBridge	167:e84263d55307	2777	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
<>	144:ef7eb2e8f9f7	2778	}
AnnaBridge	167:e84263d55307	2779	/* Read CRC to Flush DR and RXNE flag */
<>	144:ef7eb2e8f9f7	2780	tmpreg = (__IO uint8_t )&hspi->Instance->DR;
AnnaBridge	167:e84263d55307	2781	/* To avoid GCC warning */
AnnaBridge	167:e84263d55307	2782	UNUSED(tmpreg);
<>	144:ef7eb2e8f9f7	2783	}
<>	144:ef7eb2e8f9f7	2784	else
<>	144:ef7eb2e8f9f7	2785	{
AnnaBridge	167:e84263d55307	2786	if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_HALF_FULL, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	2787	{
<>	144:ef7eb2e8f9f7	2788	/* Error on the CRC reception */
AnnaBridge	167:e84263d55307	2789	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
<>	144:ef7eb2e8f9f7	2790	}
AnnaBridge	167:e84263d55307	2791	/* Read CRC to Flush DR and RXNE flag */
<>	144:ef7eb2e8f9f7	2792	tmpreg = hspi->Instance->DR;
AnnaBridge	167:e84263d55307	2793	/* To avoid GCC warning */
AnnaBridge	167:e84263d55307	2794	UNUSED(tmpreg);
<>	144:ef7eb2e8f9f7	2795	}
<>	144:ef7eb2e8f9f7	2796	}
AnnaBridge	167:e84263d55307	2797	#endif /* USE_SPI_CRC */
<>	144:ef7eb2e8f9f7	2798
<>	144:ef7eb2e8f9f7	2799	/* Check the end of the transaction */
AnnaBridge	167:e84263d55307	2800	if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	2801	{
AnnaBridge	167:e84263d55307	2802	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
<>	144:ef7eb2e8f9f7	2803	}
AnnaBridge	167:e84263d55307	2804
<>	144:ef7eb2e8f9f7	2805	/* Disable Rx/Tx DMA Request */
<>	144:ef7eb2e8f9f7	2806	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN \| SPI_CR2_RXDMAEN);
<>	144:ef7eb2e8f9f7	2807
AnnaBridge	167:e84263d55307	2808	hspi->TxXferCount = 0U;
AnnaBridge	167:e84263d55307	2809	hspi->RxXferCount = 0U;
<>	144:ef7eb2e8f9f7	2810	hspi->State = HAL_SPI_STATE_READY;
<>	144:ef7eb2e8f9f7	2811
AnnaBridge	167:e84263d55307	2812	#if (USE_SPI_CRC != 0U)
<>	144:ef7eb2e8f9f7	2813	/* Check if CRC error occurred */
AnnaBridge	167:e84263d55307	2814	if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))
<>	144:ef7eb2e8f9f7	2815	{
AnnaBridge	167:e84263d55307	2816	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
<>	144:ef7eb2e8f9f7	2817	__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
<>	144:ef7eb2e8f9f7	2818	}
AnnaBridge	167:e84263d55307	2819	#endif /* USE_SPI_CRC */
AnnaBridge	167:e84263d55307	2820
AnnaBridge	167:e84263d55307	2821	if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
<>	144:ef7eb2e8f9f7	2822	{
<>	144:ef7eb2e8f9f7	2823	HAL_SPI_ErrorCallback(hspi);
<>	144:ef7eb2e8f9f7	2824	return;
<>	144:ef7eb2e8f9f7	2825	}
<>	144:ef7eb2e8f9f7	2826	}
<>	144:ef7eb2e8f9f7	2827	HAL_SPI_TxRxCpltCallback(hspi);
<>	144:ef7eb2e8f9f7	2828	}
<>	144:ef7eb2e8f9f7	2829
<>	144:ef7eb2e8f9f7	2830	/**
AnnaBridge	167:e84263d55307	2831	* @brief DMA SPI half transmit process complete callback.
AnnaBridge	181:57724642e740	2832	* @param hdma pointer to a DMA_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	2833	* the configuration information for the specified DMA module.
<>	144:ef7eb2e8f9f7	2834	* @retval None
<>	144:ef7eb2e8f9f7	2835	*/
<>	144:ef7eb2e8f9f7	2836	static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma)
<>	144:ef7eb2e8f9f7	2837	{
AnnaBridge	167:e84263d55307	2838	SPI_HandleTypeDef hspi = (SPI_HandleTypeDef )((DMA_HandleTypeDef *)hdma)->Parent;
<>	144:ef7eb2e8f9f7	2839
<>	144:ef7eb2e8f9f7	2840	HAL_SPI_TxHalfCpltCallback(hspi);
<>	144:ef7eb2e8f9f7	2841	}
<>	144:ef7eb2e8f9f7	2842
<>	144:ef7eb2e8f9f7	2843	/**
AnnaBridge	167:e84263d55307	2844	* @brief DMA SPI half receive process complete callback
AnnaBridge	181:57724642e740	2845	* @param hdma pointer to a DMA_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	2846	* the configuration information for the specified DMA module.
<>	144:ef7eb2e8f9f7	2847	* @retval None
<>	144:ef7eb2e8f9f7	2848	*/
<>	144:ef7eb2e8f9f7	2849	static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma)
<>	144:ef7eb2e8f9f7	2850	{
AnnaBridge	167:e84263d55307	2851	SPI_HandleTypeDef hspi = (SPI_HandleTypeDef )((DMA_HandleTypeDef *)hdma)->Parent;
<>	144:ef7eb2e8f9f7	2852
<>	144:ef7eb2e8f9f7	2853	HAL_SPI_RxHalfCpltCallback(hspi);
<>	144:ef7eb2e8f9f7	2854	}
<>	144:ef7eb2e8f9f7	2855
<>	144:ef7eb2e8f9f7	2856	/**
AnnaBridge	167:e84263d55307	2857	* @brief DMA SPI half transmit receive process complete callback.
AnnaBridge	181:57724642e740	2858	* @param hdma pointer to a DMA_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	2859	* the configuration information for the specified DMA module.
<>	144:ef7eb2e8f9f7	2860	* @retval None
<>	144:ef7eb2e8f9f7	2861	*/
<>	144:ef7eb2e8f9f7	2862	static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma)
<>	144:ef7eb2e8f9f7	2863	{
AnnaBridge	167:e84263d55307	2864	SPI_HandleTypeDef hspi = (SPI_HandleTypeDef )((DMA_HandleTypeDef *)hdma)->Parent;
<>	144:ef7eb2e8f9f7	2865
<>	144:ef7eb2e8f9f7	2866	HAL_SPI_TxRxHalfCpltCallback(hspi);
<>	144:ef7eb2e8f9f7	2867	}
<>	144:ef7eb2e8f9f7	2868
<>	144:ef7eb2e8f9f7	2869	/**
AnnaBridge	167:e84263d55307	2870	* @brief DMA SPI communication error callback.
AnnaBridge	181:57724642e740	2871	* @param hdma pointer to a DMA_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	2872	* the configuration information for the specified DMA module.
<>	144:ef7eb2e8f9f7	2873	* @retval None
<>	144:ef7eb2e8f9f7	2874	*/
<>	144:ef7eb2e8f9f7	2875	static void SPI_DMAError(DMA_HandleTypeDef *hdma)
<>	144:ef7eb2e8f9f7	2876	{
AnnaBridge	167:e84263d55307	2877	SPI_HandleTypeDef hspi = (SPI_HandleTypeDef )((DMA_HandleTypeDef *)hdma)->Parent;
<>	144:ef7eb2e8f9f7	2878
<>	144:ef7eb2e8f9f7	2879	/* Stop the disable DMA transfer on SPI side */
<>	144:ef7eb2e8f9f7	2880	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN \| SPI_CR2_RXDMAEN);
<>	144:ef7eb2e8f9f7	2881
AnnaBridge	167:e84263d55307	2882	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
<>	144:ef7eb2e8f9f7	2883	hspi->State = HAL_SPI_STATE_READY;
<>	144:ef7eb2e8f9f7	2884	HAL_SPI_ErrorCallback(hspi);
<>	144:ef7eb2e8f9f7	2885	}
<>	144:ef7eb2e8f9f7	2886
<>	144:ef7eb2e8f9f7	2887	/**
AnnaBridge	167:e84263d55307	2888	* @brief DMA SPI communication abort callback, when initiated by HAL services on Error
AnnaBridge	167:e84263d55307	2889	* (To be called at end of DMA Abort procedure following error occurrence).
AnnaBridge	167:e84263d55307	2890	* @param hdma DMA handle.
AnnaBridge	167:e84263d55307	2891	* @retval None
AnnaBridge	167:e84263d55307	2892	*/
AnnaBridge	167:e84263d55307	2893	static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma)
AnnaBridge	167:e84263d55307	2894	{
AnnaBridge	167:e84263d55307	2895	SPI_HandleTypeDef hspi = (SPI_HandleTypeDef )((DMA_HandleTypeDef *)hdma)->Parent;
AnnaBridge	167:e84263d55307	2896	hspi->RxXferCount = 0U;
AnnaBridge	167:e84263d55307	2897	hspi->TxXferCount = 0U;
AnnaBridge	167:e84263d55307	2898
AnnaBridge	167:e84263d55307	2899	HAL_SPI_ErrorCallback(hspi);
AnnaBridge	167:e84263d55307	2900	}
AnnaBridge	167:e84263d55307	2901
AnnaBridge	167:e84263d55307	2902	/**
AnnaBridge	167:e84263d55307	2903	* @brief DMA SPI Tx communication abort callback, when initiated by user
AnnaBridge	167:e84263d55307	2904	* (To be called at end of DMA Tx Abort procedure following user abort request).
AnnaBridge	167:e84263d55307	2905	* @note When this callback is executed, User Abort complete call back is called only if no
AnnaBridge	167:e84263d55307	2906	* Abort still ongoing for Rx DMA Handle.
AnnaBridge	167:e84263d55307	2907	* @param hdma DMA handle.
AnnaBridge	167:e84263d55307	2908	* @retval None
AnnaBridge	167:e84263d55307	2909	*/
AnnaBridge	167:e84263d55307	2910	static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
AnnaBridge	167:e84263d55307	2911	{
AnnaBridge	167:e84263d55307	2912	SPI_HandleTypeDef hspi = (SPI_HandleTypeDef )((DMA_HandleTypeDef *)hdma)->Parent;
AnnaBridge	167:e84263d55307	2913
AnnaBridge	167:e84263d55307	2914	hspi->hdmatx->XferAbortCallback = NULL;
AnnaBridge	167:e84263d55307	2915
AnnaBridge	167:e84263d55307	2916	/* Disable Tx DMA Request */
AnnaBridge	167:e84263d55307	2917	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
AnnaBridge	167:e84263d55307	2918
AnnaBridge	167:e84263d55307	2919	if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
AnnaBridge	167:e84263d55307	2920	{
AnnaBridge	167:e84263d55307	2921	hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
AnnaBridge	167:e84263d55307	2922	}
AnnaBridge	167:e84263d55307	2923
AnnaBridge	167:e84263d55307	2924	/* Disable SPI Peripheral */
AnnaBridge	167:e84263d55307	2925	__HAL_SPI_DISABLE(hspi);
AnnaBridge	167:e84263d55307	2926
AnnaBridge	167:e84263d55307	2927	/* Empty the FRLVL fifo */
AnnaBridge	167:e84263d55307	2928	if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
AnnaBridge	167:e84263d55307	2929	{
AnnaBridge	167:e84263d55307	2930	hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
AnnaBridge	167:e84263d55307	2931	}
AnnaBridge	167:e84263d55307	2932
AnnaBridge	167:e84263d55307	2933	/* Check if an Abort process is still ongoing */
AnnaBridge	167:e84263d55307	2934	if (hspi->hdmarx != NULL)
AnnaBridge	167:e84263d55307	2935	{
AnnaBridge	167:e84263d55307	2936	if (hspi->hdmarx->XferAbortCallback != NULL)
AnnaBridge	167:e84263d55307	2937	{
AnnaBridge	167:e84263d55307	2938	return;
AnnaBridge	167:e84263d55307	2939	}
AnnaBridge	167:e84263d55307	2940	}
AnnaBridge	167:e84263d55307	2941
AnnaBridge	167:e84263d55307	2942	/* No Abort process still ongoing : All DMA Stream/Channel are aborted, call user Abort Complete callback */
AnnaBridge	167:e84263d55307	2943	hspi->RxXferCount = 0U;
AnnaBridge	167:e84263d55307	2944	hspi->TxXferCount = 0U;
AnnaBridge	167:e84263d55307	2945
AnnaBridge	167:e84263d55307	2946	/* Check no error during Abort procedure */
AnnaBridge	167:e84263d55307	2947	if (hspi->ErrorCode != HAL_SPI_ERROR_ABORT)
AnnaBridge	167:e84263d55307	2948	{
AnnaBridge	167:e84263d55307	2949	/* Reset errorCode */
AnnaBridge	167:e84263d55307	2950	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
AnnaBridge	167:e84263d55307	2951	}
AnnaBridge	167:e84263d55307	2952
AnnaBridge	167:e84263d55307	2953	/* Clear the Error flags in the SR register */
AnnaBridge	167:e84263d55307	2954	__HAL_SPI_CLEAR_OVRFLAG(hspi);
AnnaBridge	167:e84263d55307	2955	__HAL_SPI_CLEAR_FREFLAG(hspi);
AnnaBridge	167:e84263d55307	2956
AnnaBridge	167:e84263d55307	2957	/* Restore hspi->State to Ready */
AnnaBridge	167:e84263d55307	2958	hspi->State = HAL_SPI_STATE_READY;
AnnaBridge	167:e84263d55307	2959
AnnaBridge	167:e84263d55307	2960	/* Call user Abort complete callback */
AnnaBridge	167:e84263d55307	2961	HAL_SPI_AbortCpltCallback(hspi);
AnnaBridge	167:e84263d55307	2962	}
AnnaBridge	167:e84263d55307	2963
AnnaBridge	167:e84263d55307	2964	/**
AnnaBridge	167:e84263d55307	2965	* @brief DMA SPI Rx communication abort callback, when initiated by user
AnnaBridge	167:e84263d55307	2966	* (To be called at end of DMA Rx Abort procedure following user abort request).
AnnaBridge	167:e84263d55307	2967	* @note When this callback is executed, User Abort complete call back is called only if no
AnnaBridge	167:e84263d55307	2968	* Abort still ongoing for Tx DMA Handle.
AnnaBridge	167:e84263d55307	2969	* @param hdma DMA handle.
AnnaBridge	167:e84263d55307	2970	* @retval None
AnnaBridge	167:e84263d55307	2971	*/
AnnaBridge	167:e84263d55307	2972	static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
AnnaBridge	167:e84263d55307	2973	{
AnnaBridge	167:e84263d55307	2974	SPI_HandleTypeDef hspi = (SPI_HandleTypeDef )((DMA_HandleTypeDef *)hdma)->Parent;
AnnaBridge	167:e84263d55307	2975
AnnaBridge	167:e84263d55307	2976	/* Disable SPI Peripheral */
AnnaBridge	167:e84263d55307	2977	__HAL_SPI_DISABLE(hspi);
AnnaBridge	167:e84263d55307	2978
AnnaBridge	167:e84263d55307	2979	hspi->hdmarx->XferAbortCallback = NULL;
AnnaBridge	167:e84263d55307	2980
AnnaBridge	167:e84263d55307	2981	/* Disable Rx DMA Request */
AnnaBridge	167:e84263d55307	2982	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
AnnaBridge	167:e84263d55307	2983
AnnaBridge	167:e84263d55307	2984	/* Control the BSY flag */
AnnaBridge	167:e84263d55307	2985	if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
AnnaBridge	167:e84263d55307	2986	{
AnnaBridge	167:e84263d55307	2987	hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
AnnaBridge	167:e84263d55307	2988	}
AnnaBridge	167:e84263d55307	2989
AnnaBridge	167:e84263d55307	2990	/* Empty the FRLVL fifo */
AnnaBridge	167:e84263d55307	2991	if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
AnnaBridge	167:e84263d55307	2992	{
AnnaBridge	167:e84263d55307	2993	hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
AnnaBridge	167:e84263d55307	2994	}
AnnaBridge	167:e84263d55307	2995
AnnaBridge	167:e84263d55307	2996	/* Check if an Abort process is still ongoing */
AnnaBridge	167:e84263d55307	2997	if (hspi->hdmatx != NULL)
AnnaBridge	167:e84263d55307	2998	{
AnnaBridge	167:e84263d55307	2999	if (hspi->hdmatx->XferAbortCallback != NULL)
AnnaBridge	167:e84263d55307	3000	{
AnnaBridge	167:e84263d55307	3001	return;
AnnaBridge	167:e84263d55307	3002	}
AnnaBridge	167:e84263d55307	3003	}
AnnaBridge	167:e84263d55307	3004
AnnaBridge	167:e84263d55307	3005	/* No Abort process still ongoing : All DMA Stream/Channel are aborted, call user Abort Complete callback */
AnnaBridge	167:e84263d55307	3006	hspi->RxXferCount = 0U;
AnnaBridge	167:e84263d55307	3007	hspi->TxXferCount = 0U;
AnnaBridge	167:e84263d55307	3008
AnnaBridge	167:e84263d55307	3009	/* Check no error during Abort procedure */
AnnaBridge	167:e84263d55307	3010	if (hspi->ErrorCode != HAL_SPI_ERROR_ABORT)
AnnaBridge	167:e84263d55307	3011	{
AnnaBridge	167:e84263d55307	3012	/* Reset errorCode */
AnnaBridge	167:e84263d55307	3013	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
AnnaBridge	167:e84263d55307	3014	}
AnnaBridge	167:e84263d55307	3015
AnnaBridge	167:e84263d55307	3016	/* Clear the Error flags in the SR register */
AnnaBridge	167:e84263d55307	3017	__HAL_SPI_CLEAR_OVRFLAG(hspi);
AnnaBridge	167:e84263d55307	3018	__HAL_SPI_CLEAR_FREFLAG(hspi);
AnnaBridge	167:e84263d55307	3019
AnnaBridge	167:e84263d55307	3020	/* Restore hspi->State to Ready */
AnnaBridge	167:e84263d55307	3021	hspi->State = HAL_SPI_STATE_READY;
AnnaBridge	167:e84263d55307	3022
AnnaBridge	167:e84263d55307	3023	/* Call user Abort complete callback */
AnnaBridge	167:e84263d55307	3024	HAL_SPI_AbortCpltCallback(hspi);
AnnaBridge	167:e84263d55307	3025	}
AnnaBridge	167:e84263d55307	3026
AnnaBridge	167:e84263d55307	3027	/**
<>	144:ef7eb2e8f9f7	3028	* @brief Rx 8-bit handler for Transmit and Receive in Interrupt mode.
AnnaBridge	181:57724642e740	3029	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	3030	* the configuration information for SPI module.
<>	144:ef7eb2e8f9f7	3031	* @retval None
<>	144:ef7eb2e8f9f7	3032	*/
<>	144:ef7eb2e8f9f7	3033	static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
<>	144:ef7eb2e8f9f7	3034	{
<>	144:ef7eb2e8f9f7	3035	/* Receive data in packing mode */
AnnaBridge	167:e84263d55307	3036	if (hspi->RxXferCount > 1U)
<>	144:ef7eb2e8f9f7	3037	{
AnnaBridge	167:e84263d55307	3038	((uint16_t )hspi->pRxBuffPtr) = hspi->Instance->DR;
<>	144:ef7eb2e8f9f7	3039	hspi->pRxBuffPtr += sizeof(uint16_t);
AnnaBridge	167:e84263d55307	3040	hspi->RxXferCount -= 2U;
AnnaBridge	167:e84263d55307	3041	if (hspi->RxXferCount == 1U)
<>	144:ef7eb2e8f9f7	3042	{
AnnaBridge	181:57724642e740	3043	/* Set RX Fifo threshold according the reception data length: 8bit */
<>	144:ef7eb2e8f9f7	3044	SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
<>	144:ef7eb2e8f9f7	3045	}
<>	144:ef7eb2e8f9f7	3046	}
<>	144:ef7eb2e8f9f7	3047	/* Receive data in 8 Bit mode */
<>	144:ef7eb2e8f9f7	3048	else
<>	144:ef7eb2e8f9f7	3049	{
<>	144:ef7eb2e8f9f7	3050	hspi->pRxBuffPtr++ = ((__IO uint8_t *)&hspi->Instance->DR);
<>	144:ef7eb2e8f9f7	3051	hspi->RxXferCount--;
<>	144:ef7eb2e8f9f7	3052	}
<>	144:ef7eb2e8f9f7	3053
AnnaBridge	181:57724642e740	3054	/* Check end of the reception */
AnnaBridge	167:e84263d55307	3055	if (hspi->RxXferCount == 0U)
<>	144:ef7eb2e8f9f7	3056	{
AnnaBridge	167:e84263d55307	3057	#if (USE_SPI_CRC != 0U)
AnnaBridge	167:e84263d55307	3058	if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<>	144:ef7eb2e8f9f7	3059	{
<>	144:ef7eb2e8f9f7	3060	SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
<>	144:ef7eb2e8f9f7	3061	hspi->RxISR = SPI_2linesRxISR_8BITCRC;
<>	144:ef7eb2e8f9f7	3062	return;
<>	144:ef7eb2e8f9f7	3063	}
AnnaBridge	167:e84263d55307	3064	#endif /* USE_SPI_CRC */
AnnaBridge	167:e84263d55307	3065
AnnaBridge	167:e84263d55307	3066	/* Disable RXNE and ERR interrupt */
AnnaBridge	167:e84263d55307	3067	__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE \| SPI_IT_ERR));
AnnaBridge	167:e84263d55307	3068
AnnaBridge	167:e84263d55307	3069	if (hspi->TxXferCount == 0U)
<>	144:ef7eb2e8f9f7	3070	{
<>	144:ef7eb2e8f9f7	3071	SPI_CloseRxTx_ISR(hspi);
<>	144:ef7eb2e8f9f7	3072	}
<>	144:ef7eb2e8f9f7	3073	}
<>	144:ef7eb2e8f9f7	3074	}
<>	144:ef7eb2e8f9f7	3075
AnnaBridge	167:e84263d55307	3076	#if (USE_SPI_CRC != 0U)
<>	144:ef7eb2e8f9f7	3077	/**
<>	144:ef7eb2e8f9f7	3078	* @brief Rx 8-bit handler for Transmit and Receive in Interrupt mode.
AnnaBridge	181:57724642e740	3079	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	3080	* the configuration information for SPI module.
<>	144:ef7eb2e8f9f7	3081	* @retval None
<>	144:ef7eb2e8f9f7	3082	*/
<>	144:ef7eb2e8f9f7	3083	static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
<>	144:ef7eb2e8f9f7	3084	{
AnnaBridge	167:e84263d55307	3085	__IO uint8_t tmpreg = 0U;
AnnaBridge	167:e84263d55307	3086
AnnaBridge	167:e84263d55307	3087	/* Read data register to flush CRC */
AnnaBridge	167:e84263d55307	3088	tmpreg = ((__IO uint8_t )&hspi->Instance->DR);
AnnaBridge	167:e84263d55307	3089
AnnaBridge	167:e84263d55307	3090	/* To avoid GCC warning */
AnnaBridge	167:e84263d55307	3091	UNUSED(tmpreg);
<>	144:ef7eb2e8f9f7	3092
<>	144:ef7eb2e8f9f7	3093	hspi->CRCSize--;
<>	144:ef7eb2e8f9f7	3094
AnnaBridge	181:57724642e740	3095	/* Check end of the reception */
AnnaBridge	167:e84263d55307	3096	if (hspi->CRCSize == 0U)
<>	144:ef7eb2e8f9f7	3097	{
AnnaBridge	167:e84263d55307	3098	/* Disable RXNE and ERR interrupt */
AnnaBridge	167:e84263d55307	3099	__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE \| SPI_IT_ERR));
AnnaBridge	167:e84263d55307	3100
AnnaBridge	167:e84263d55307	3101	if (hspi->TxXferCount == 0U)
<>	144:ef7eb2e8f9f7	3102	{
<>	144:ef7eb2e8f9f7	3103	SPI_CloseRxTx_ISR(hspi);
<>	144:ef7eb2e8f9f7	3104	}
<>	144:ef7eb2e8f9f7	3105	}
<>	144:ef7eb2e8f9f7	3106	}
AnnaBridge	167:e84263d55307	3107	#endif /* USE_SPI_CRC */
<>	144:ef7eb2e8f9f7	3108
<>	144:ef7eb2e8f9f7	3109	/**
<>	144:ef7eb2e8f9f7	3110	* @brief Tx 8-bit handler for Transmit and Receive in Interrupt mode.
AnnaBridge	181:57724642e740	3111	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	3112	* the configuration information for SPI module.
<>	144:ef7eb2e8f9f7	3113	* @retval None
<>	144:ef7eb2e8f9f7	3114	*/
<>	144:ef7eb2e8f9f7	3115	static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
<>	144:ef7eb2e8f9f7	3116	{
<>	144:ef7eb2e8f9f7	3117	/* Transmit data in packing Bit mode */
AnnaBridge	167:e84263d55307	3118	if (hspi->TxXferCount >= 2U)
<>	144:ef7eb2e8f9f7	3119	{
<>	144:ef7eb2e8f9f7	3120	hspi->Instance->DR = ((uint16_t )hspi->pTxBuffPtr);
<>	144:ef7eb2e8f9f7	3121	hspi->pTxBuffPtr += sizeof(uint16_t);
AnnaBridge	167:e84263d55307	3122	hspi->TxXferCount -= 2U;
<>	144:ef7eb2e8f9f7	3123	}
<>	144:ef7eb2e8f9f7	3124	/* Transmit data in 8 Bit mode */
<>	144:ef7eb2e8f9f7	3125	else
<>	144:ef7eb2e8f9f7	3126	{
<>	144:ef7eb2e8f9f7	3127	(__IO uint8_t )&hspi->Instance->DR = (*hspi->pTxBuffPtr++);
<>	144:ef7eb2e8f9f7	3128	hspi->TxXferCount--;
<>	144:ef7eb2e8f9f7	3129	}
<>	144:ef7eb2e8f9f7	3130
AnnaBridge	181:57724642e740	3131	/* Check the end of the transmission */
AnnaBridge	167:e84263d55307	3132	if (hspi->TxXferCount == 0U)
<>	144:ef7eb2e8f9f7	3133	{
AnnaBridge	167:e84263d55307	3134	#if (USE_SPI_CRC != 0U)
AnnaBridge	167:e84263d55307	3135	if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<>	144:ef7eb2e8f9f7	3136	{
AnnaBridge	167:e84263d55307	3137	/* Set CRC Next Bit to send CRC */
AnnaBridge	167:e84263d55307	3138	SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
AnnaBridge	167:e84263d55307	3139	/* Disable TXE interrupt */
AnnaBridge	167:e84263d55307	3140	__HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
AnnaBridge	167:e84263d55307	3141	return;
<>	144:ef7eb2e8f9f7	3142	}
AnnaBridge	167:e84263d55307	3143	#endif /* USE_SPI_CRC */
AnnaBridge	167:e84263d55307	3144
<>	144:ef7eb2e8f9f7	3145	/* Disable TXE interrupt */
<>	144:ef7eb2e8f9f7	3146	__HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
<>	144:ef7eb2e8f9f7	3147
AnnaBridge	167:e84263d55307	3148	if (hspi->RxXferCount == 0U)
<>	144:ef7eb2e8f9f7	3149	{
<>	144:ef7eb2e8f9f7	3150	SPI_CloseRxTx_ISR(hspi);
<>	144:ef7eb2e8f9f7	3151	}
<>	144:ef7eb2e8f9f7	3152	}
<>	144:ef7eb2e8f9f7	3153	}
<>	144:ef7eb2e8f9f7	3154
<>	144:ef7eb2e8f9f7	3155	/**
<>	144:ef7eb2e8f9f7	3156	* @brief Rx 16-bit handler for Transmit and Receive in Interrupt mode.
AnnaBridge	181:57724642e740	3157	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	3158	* the configuration information for SPI module.
<>	144:ef7eb2e8f9f7	3159	* @retval None
<>	144:ef7eb2e8f9f7	3160	*/
<>	144:ef7eb2e8f9f7	3161	static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
<>	144:ef7eb2e8f9f7	3162	{
<>	144:ef7eb2e8f9f7	3163	/* Receive data in 16 Bit mode */
AnnaBridge	167:e84263d55307	3164	((uint16_t )hspi->pRxBuffPtr) = hspi->Instance->DR;
<>	144:ef7eb2e8f9f7	3165	hspi->pRxBuffPtr += sizeof(uint16_t);
<>	144:ef7eb2e8f9f7	3166	hspi->RxXferCount--;
<>	144:ef7eb2e8f9f7	3167
AnnaBridge	167:e84263d55307	3168	if (hspi->RxXferCount == 0U)
<>	144:ef7eb2e8f9f7	3169	{
AnnaBridge	167:e84263d55307	3170	#if (USE_SPI_CRC != 0U)
AnnaBridge	167:e84263d55307	3171	if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<>	144:ef7eb2e8f9f7	3172	{
<>	144:ef7eb2e8f9f7	3173	hspi->RxISR = SPI_2linesRxISR_16BITCRC;
<>	144:ef7eb2e8f9f7	3174	return;
<>	144:ef7eb2e8f9f7	3175	}
AnnaBridge	167:e84263d55307	3176	#endif /* USE_SPI_CRC */
<>	144:ef7eb2e8f9f7	3177
<>	144:ef7eb2e8f9f7	3178	/* Disable RXNE interrupt */
<>	144:ef7eb2e8f9f7	3179	__HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
<>	144:ef7eb2e8f9f7	3180
AnnaBridge	167:e84263d55307	3181	if (hspi->TxXferCount == 0U)
<>	144:ef7eb2e8f9f7	3182	{
<>	144:ef7eb2e8f9f7	3183	SPI_CloseRxTx_ISR(hspi);
<>	144:ef7eb2e8f9f7	3184	}
<>	144:ef7eb2e8f9f7	3185	}
<>	144:ef7eb2e8f9f7	3186	}
<>	144:ef7eb2e8f9f7	3187
AnnaBridge	167:e84263d55307	3188	#if (USE_SPI_CRC != 0U)
<>	144:ef7eb2e8f9f7	3189	/**
<>	144:ef7eb2e8f9f7	3190	* @brief Manage the CRC 16-bit receive for Transmit and Receive in Interrupt mode.
AnnaBridge	181:57724642e740	3191	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	3192	* the configuration information for SPI module.
<>	144:ef7eb2e8f9f7	3193	* @retval None
<>	144:ef7eb2e8f9f7	3194	*/
<>	144:ef7eb2e8f9f7	3195	static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
<>	144:ef7eb2e8f9f7	3196	{
<>	144:ef7eb2e8f9f7	3197	/* Receive data in 16 Bit mode */
AnnaBridge	167:e84263d55307	3198	__IO uint16_t tmpreg = 0U;
AnnaBridge	167:e84263d55307	3199
AnnaBridge	167:e84263d55307	3200	/* Read data register to flush CRC */
AnnaBridge	167:e84263d55307	3201	tmpreg = hspi->Instance->DR;
AnnaBridge	167:e84263d55307	3202
AnnaBridge	167:e84263d55307	3203	/* To avoid GCC warning */
AnnaBridge	167:e84263d55307	3204	UNUSED(tmpreg);
<>	144:ef7eb2e8f9f7	3205
<>	144:ef7eb2e8f9f7	3206	/* Disable RXNE interrupt */
<>	144:ef7eb2e8f9f7	3207	__HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
<>	144:ef7eb2e8f9f7	3208
<>	144:ef7eb2e8f9f7	3209	SPI_CloseRxTx_ISR(hspi);
<>	144:ef7eb2e8f9f7	3210	}
AnnaBridge	167:e84263d55307	3211	#endif /* USE_SPI_CRC */
<>	144:ef7eb2e8f9f7	3212
<>	144:ef7eb2e8f9f7	3213	/**
<>	144:ef7eb2e8f9f7	3214	* @brief Tx 16-bit handler for Transmit and Receive in Interrupt mode.
AnnaBridge	181:57724642e740	3215	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	3216	* the configuration information for SPI module.
<>	144:ef7eb2e8f9f7	3217	* @retval None
<>	144:ef7eb2e8f9f7	3218	*/
<>	144:ef7eb2e8f9f7	3219	static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
<>	144:ef7eb2e8f9f7	3220	{
<>	144:ef7eb2e8f9f7	3221	/* Transmit data in 16 Bit mode */
<>	144:ef7eb2e8f9f7	3222	hspi->Instance->DR = ((uint16_t )hspi->pTxBuffPtr);
<>	144:ef7eb2e8f9f7	3223	hspi->pTxBuffPtr += sizeof(uint16_t);
<>	144:ef7eb2e8f9f7	3224	hspi->TxXferCount--;
<>	144:ef7eb2e8f9f7	3225
<>	144:ef7eb2e8f9f7	3226	/* Enable CRC Transmission */
AnnaBridge	167:e84263d55307	3227	if (hspi->TxXferCount == 0U)
<>	144:ef7eb2e8f9f7	3228	{
AnnaBridge	167:e84263d55307	3229	#if (USE_SPI_CRC != 0U)
AnnaBridge	167:e84263d55307	3230	if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<>	144:ef7eb2e8f9f7	3231	{
AnnaBridge	167:e84263d55307	3232	/* Set CRC Next Bit to send CRC */
AnnaBridge	167:e84263d55307	3233	SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
AnnaBridge	167:e84263d55307	3234	/* Disable TXE interrupt */
AnnaBridge	167:e84263d55307	3235	__HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
AnnaBridge	167:e84263d55307	3236	return;
<>	144:ef7eb2e8f9f7	3237	}
AnnaBridge	167:e84263d55307	3238	#endif /* USE_SPI_CRC */
AnnaBridge	167:e84263d55307	3239
<>	144:ef7eb2e8f9f7	3240	/* Disable TXE interrupt */
<>	144:ef7eb2e8f9f7	3241	__HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
<>	144:ef7eb2e8f9f7	3242
AnnaBridge	167:e84263d55307	3243	if (hspi->RxXferCount == 0U)
<>	144:ef7eb2e8f9f7	3244	{
<>	144:ef7eb2e8f9f7	3245	SPI_CloseRxTx_ISR(hspi);
<>	144:ef7eb2e8f9f7	3246	}
<>	144:ef7eb2e8f9f7	3247	}
<>	144:ef7eb2e8f9f7	3248	}
<>	144:ef7eb2e8f9f7	3249
AnnaBridge	167:e84263d55307	3250	#if (USE_SPI_CRC != 0U)
<>	144:ef7eb2e8f9f7	3251	/**
<>	144:ef7eb2e8f9f7	3252	* @brief Manage the CRC 8-bit receive in Interrupt context.
AnnaBridge	181:57724642e740	3253	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	3254	* the configuration information for SPI module.
<>	144:ef7eb2e8f9f7	3255	* @retval None
<>	144:ef7eb2e8f9f7	3256	*/
<>	144:ef7eb2e8f9f7	3257	static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
<>	144:ef7eb2e8f9f7	3258	{
AnnaBridge	167:e84263d55307	3259	__IO uint8_t tmpreg = 0U;
AnnaBridge	167:e84263d55307	3260
AnnaBridge	167:e84263d55307	3261	/* Read data register to flush CRC */
AnnaBridge	167:e84263d55307	3262	tmpreg = ((__IO uint8_t )&hspi->Instance->DR);
AnnaBridge	167:e84263d55307	3263
AnnaBridge	167:e84263d55307	3264	/* To avoid GCC warning */
AnnaBridge	167:e84263d55307	3265	UNUSED(tmpreg);
<>	144:ef7eb2e8f9f7	3266
<>	144:ef7eb2e8f9f7	3267	hspi->CRCSize--;
<>	144:ef7eb2e8f9f7	3268
AnnaBridge	167:e84263d55307	3269	if (hspi->CRCSize == 0U)
<>	144:ef7eb2e8f9f7	3270	{
<>	144:ef7eb2e8f9f7	3271	SPI_CloseRx_ISR(hspi);
<>	144:ef7eb2e8f9f7	3272	}
<>	144:ef7eb2e8f9f7	3273	}
AnnaBridge	167:e84263d55307	3274	#endif /* USE_SPI_CRC */
<>	144:ef7eb2e8f9f7	3275
<>	144:ef7eb2e8f9f7	3276	/**
<>	144:ef7eb2e8f9f7	3277	* @brief Manage the receive 8-bit in Interrupt context.
AnnaBridge	181:57724642e740	3278	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	3279	* the configuration information for SPI module.
<>	144:ef7eb2e8f9f7	3280	* @retval None
<>	144:ef7eb2e8f9f7	3281	*/
<>	144:ef7eb2e8f9f7	3282	static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
<>	144:ef7eb2e8f9f7	3283	{
<>	144:ef7eb2e8f9f7	3284	hspi->pRxBuffPtr++ = ((__IO uint8_t *)&hspi->Instance->DR);
<>	144:ef7eb2e8f9f7	3285	hspi->RxXferCount--;
<>	144:ef7eb2e8f9f7	3286
AnnaBridge	167:e84263d55307	3287	#if (USE_SPI_CRC != 0U)
<>	144:ef7eb2e8f9f7	3288	/* Enable CRC Transmission */
AnnaBridge	167:e84263d55307	3289	if ((hspi->RxXferCount == 1U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
<>	144:ef7eb2e8f9f7	3290	{
AnnaBridge	167:e84263d55307	3291	SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
<>	144:ef7eb2e8f9f7	3292	}
AnnaBridge	167:e84263d55307	3293	#endif /* USE_SPI_CRC */
AnnaBridge	167:e84263d55307	3294
AnnaBridge	167:e84263d55307	3295	if (hspi->RxXferCount == 0U)
<>	144:ef7eb2e8f9f7	3296	{
AnnaBridge	167:e84263d55307	3297	#if (USE_SPI_CRC != 0U)
AnnaBridge	167:e84263d55307	3298	if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<>	144:ef7eb2e8f9f7	3299	{
<>	144:ef7eb2e8f9f7	3300	hspi->RxISR = SPI_RxISR_8BITCRC;
<>	144:ef7eb2e8f9f7	3301	return;
<>	144:ef7eb2e8f9f7	3302	}
AnnaBridge	167:e84263d55307	3303	#endif /* USE_SPI_CRC */
<>	144:ef7eb2e8f9f7	3304	SPI_CloseRx_ISR(hspi);
<>	144:ef7eb2e8f9f7	3305	}
<>	144:ef7eb2e8f9f7	3306	}
<>	144:ef7eb2e8f9f7	3307
AnnaBridge	167:e84263d55307	3308	#if (USE_SPI_CRC != 0U)
<>	144:ef7eb2e8f9f7	3309	/**
<>	144:ef7eb2e8f9f7	3310	* @brief Manage the CRC 16-bit receive in Interrupt context.
AnnaBridge	181:57724642e740	3311	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	3312	* the configuration information for SPI module.
<>	144:ef7eb2e8f9f7	3313	* @retval None
<>	144:ef7eb2e8f9f7	3314	*/
<>	144:ef7eb2e8f9f7	3315	static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
<>	144:ef7eb2e8f9f7	3316	{
AnnaBridge	167:e84263d55307	3317	__IO uint16_t tmpreg = 0U;
AnnaBridge	167:e84263d55307	3318
AnnaBridge	167:e84263d55307	3319	/* Read data register to flush CRC */
<>	144:ef7eb2e8f9f7	3320	tmpreg = hspi->Instance->DR;
AnnaBridge	167:e84263d55307	3321
AnnaBridge	167:e84263d55307	3322	/* To avoid GCC warning */
AnnaBridge	167:e84263d55307	3323	UNUSED(tmpreg);
<>	144:ef7eb2e8f9f7	3324
<>	144:ef7eb2e8f9f7	3325	/* Disable RXNE and ERR interrupt */
<>	144:ef7eb2e8f9f7	3326	__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE \| SPI_IT_ERR));
<>	144:ef7eb2e8f9f7	3327
<>	144:ef7eb2e8f9f7	3328	SPI_CloseRx_ISR(hspi);
<>	144:ef7eb2e8f9f7	3329	}
AnnaBridge	167:e84263d55307	3330	#endif /* USE_SPI_CRC */
<>	144:ef7eb2e8f9f7	3331
<>	144:ef7eb2e8f9f7	3332	/**
<>	144:ef7eb2e8f9f7	3333	* @brief Manage the 16-bit receive in Interrupt context.
AnnaBridge	181:57724642e740	3334	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	3335	* the configuration information for SPI module.
<>	144:ef7eb2e8f9f7	3336	* @retval None
<>	144:ef7eb2e8f9f7	3337	*/
<>	144:ef7eb2e8f9f7	3338	static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
<>	144:ef7eb2e8f9f7	3339	{
<>	144:ef7eb2e8f9f7	3340	((uint16_t )hspi->pRxBuffPtr) = hspi->Instance->DR;
<>	144:ef7eb2e8f9f7	3341	hspi->pRxBuffPtr += sizeof(uint16_t);
<>	144:ef7eb2e8f9f7	3342	hspi->RxXferCount--;
<>	144:ef7eb2e8f9f7	3343
AnnaBridge	167:e84263d55307	3344	#if (USE_SPI_CRC != 0U)
<>	144:ef7eb2e8f9f7	3345	/* Enable CRC Transmission */
AnnaBridge	167:e84263d55307	3346	if ((hspi->RxXferCount == 1U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
<>	144:ef7eb2e8f9f7	3347	{
AnnaBridge	167:e84263d55307	3348	SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
<>	144:ef7eb2e8f9f7	3349	}
AnnaBridge	167:e84263d55307	3350	#endif /* USE_SPI_CRC */
AnnaBridge	167:e84263d55307	3351
AnnaBridge	167:e84263d55307	3352	if (hspi->RxXferCount == 0U)
<>	144:ef7eb2e8f9f7	3353	{
AnnaBridge	167:e84263d55307	3354	#if (USE_SPI_CRC != 0U)
AnnaBridge	167:e84263d55307	3355	if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<>	144:ef7eb2e8f9f7	3356	{
<>	144:ef7eb2e8f9f7	3357	hspi->RxISR = SPI_RxISR_16BITCRC;
<>	144:ef7eb2e8f9f7	3358	return;
<>	144:ef7eb2e8f9f7	3359	}
AnnaBridge	167:e84263d55307	3360	#endif /* USE_SPI_CRC */
<>	144:ef7eb2e8f9f7	3361	SPI_CloseRx_ISR(hspi);
<>	144:ef7eb2e8f9f7	3362	}
<>	144:ef7eb2e8f9f7	3363	}
<>	144:ef7eb2e8f9f7	3364
<>	144:ef7eb2e8f9f7	3365	/**
<>	144:ef7eb2e8f9f7	3366	* @brief Handle the data 8-bit transmit in Interrupt mode.
AnnaBridge	181:57724642e740	3367	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	3368	* the configuration information for SPI module.
<>	144:ef7eb2e8f9f7	3369	* @retval None
<>	144:ef7eb2e8f9f7	3370	*/
<>	144:ef7eb2e8f9f7	3371	static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
<>	144:ef7eb2e8f9f7	3372	{
<>	144:ef7eb2e8f9f7	3373	(__IO uint8_t )&hspi->Instance->DR = (*hspi->pTxBuffPtr++);
<>	144:ef7eb2e8f9f7	3374	hspi->TxXferCount--;
<>	144:ef7eb2e8f9f7	3375
AnnaBridge	167:e84263d55307	3376	if (hspi->TxXferCount == 0U)
<>	144:ef7eb2e8f9f7	3377	{
AnnaBridge	167:e84263d55307	3378	#if (USE_SPI_CRC != 0U)
AnnaBridge	167:e84263d55307	3379	if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<>	144:ef7eb2e8f9f7	3380	{
<>	144:ef7eb2e8f9f7	3381	/* Enable CRC Transmission */
AnnaBridge	167:e84263d55307	3382	SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
<>	144:ef7eb2e8f9f7	3383	}
AnnaBridge	167:e84263d55307	3384	#endif /* USE_SPI_CRC */
<>	144:ef7eb2e8f9f7	3385	SPI_CloseTx_ISR(hspi);
<>	144:ef7eb2e8f9f7	3386	}
<>	144:ef7eb2e8f9f7	3387	}
<>	144:ef7eb2e8f9f7	3388
<>	144:ef7eb2e8f9f7	3389	/**
<>	144:ef7eb2e8f9f7	3390	* @brief Handle the data 16-bit transmit in Interrupt mode.
AnnaBridge	181:57724642e740	3391	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	3392	* the configuration information for SPI module.
<>	144:ef7eb2e8f9f7	3393	* @retval None
<>	144:ef7eb2e8f9f7	3394	*/
<>	144:ef7eb2e8f9f7	3395	static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
<>	144:ef7eb2e8f9f7	3396	{
<>	144:ef7eb2e8f9f7	3397	/* Transmit data in 16 Bit mode */
<>	144:ef7eb2e8f9f7	3398	hspi->Instance->DR = ((uint16_t )hspi->pTxBuffPtr);
<>	144:ef7eb2e8f9f7	3399	hspi->pTxBuffPtr += sizeof(uint16_t);
<>	144:ef7eb2e8f9f7	3400	hspi->TxXferCount--;
<>	144:ef7eb2e8f9f7	3401
AnnaBridge	167:e84263d55307	3402	if (hspi->TxXferCount == 0U)
<>	144:ef7eb2e8f9f7	3403	{
AnnaBridge	167:e84263d55307	3404	#if (USE_SPI_CRC != 0U)
AnnaBridge	167:e84263d55307	3405	if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<>	144:ef7eb2e8f9f7	3406	{
<>	144:ef7eb2e8f9f7	3407	/* Enable CRC Transmission */
AnnaBridge	167:e84263d55307	3408	SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
<>	144:ef7eb2e8f9f7	3409	}
AnnaBridge	167:e84263d55307	3410	#endif /* USE_SPI_CRC */
<>	144:ef7eb2e8f9f7	3411	SPI_CloseTx_ISR(hspi);
<>	144:ef7eb2e8f9f7	3412	}
<>	144:ef7eb2e8f9f7	3413	}
<>	144:ef7eb2e8f9f7	3414
<>	144:ef7eb2e8f9f7	3415	/**
AnnaBridge	181:57724642e740	3416	* @brief Handle SPI Communication Timeout.
AnnaBridge	181:57724642e740	3417	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
AnnaBridge	167:e84263d55307	3418	* the configuration information for SPI module.
AnnaBridge	181:57724642e740	3419	* @param Flag SPI flag to check
AnnaBridge	181:57724642e740	3420	* @param State flag state to check
AnnaBridge	181:57724642e740	3421	* @param Timeout Timeout duration
AnnaBridge	181:57724642e740	3422	* @param Tickstart tick start value
<>	144:ef7eb2e8f9f7	3423	* @retval HAL status
<>	144:ef7eb2e8f9f7	3424	*/
AnnaBridge	167:e84263d55307	3425	static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, uint32_t State,
AnnaBridge	167:e84263d55307	3426	uint32_t Timeout, uint32_t Tickstart)
<>	144:ef7eb2e8f9f7	3427	{
AnnaBridge	167:e84263d55307	3428	while ((__HAL_SPI_GET_FLAG(hspi, Flag) ? SET : RESET) != State)
<>	144:ef7eb2e8f9f7	3429	{
AnnaBridge	167:e84263d55307	3430	if (Timeout != HAL_MAX_DELAY)
<>	144:ef7eb2e8f9f7	3431	{
AnnaBridge	167:e84263d55307	3432	if ((Timeout == 0U) \|\| ((HAL_GetTick() - Tickstart) >= Timeout))
<>	144:ef7eb2e8f9f7	3433	{
<>	144:ef7eb2e8f9f7	3434	/* Disable the SPI and reset the CRC: the CRC value should be cleared
<>	144:ef7eb2e8f9f7	3435	on both master and slave sides in order to resynchronize the master
<>	144:ef7eb2e8f9f7	3436	and slave for their respective CRC calculation */
<>	144:ef7eb2e8f9f7	3437
<>	144:ef7eb2e8f9f7	3438	/* Disable TXE, RXNE and ERR interrupts for the interrupt process */
<>	144:ef7eb2e8f9f7	3439	__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE \| SPI_IT_RXNE \| SPI_IT_ERR));
<>	144:ef7eb2e8f9f7	3440
AnnaBridge	167:e84263d55307	3441	if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
AnnaBridge	167:e84263d55307	3442	\|\| (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
<>	144:ef7eb2e8f9f7	3443	{
<>	144:ef7eb2e8f9f7	3444	/* Disable SPI peripheral */
<>	144:ef7eb2e8f9f7	3445	__HAL_SPI_DISABLE(hspi);
<>	144:ef7eb2e8f9f7	3446	}
<>	144:ef7eb2e8f9f7	3447
<>	144:ef7eb2e8f9f7	3448	/* Reset CRC Calculation */
AnnaBridge	167:e84263d55307	3449	if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<>	144:ef7eb2e8f9f7	3450	{
<>	144:ef7eb2e8f9f7	3451	SPI_RESET_CRC(hspi);
<>	144:ef7eb2e8f9f7	3452	}
<>	144:ef7eb2e8f9f7	3453
<>	144:ef7eb2e8f9f7	3454	hspi->State = HAL_SPI_STATE_READY;
<>	144:ef7eb2e8f9f7	3455
<>	144:ef7eb2e8f9f7	3456	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	3457	__HAL_UNLOCK(hspi);
<>	144:ef7eb2e8f9f7	3458
<>	144:ef7eb2e8f9f7	3459	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	3460	}
<>	144:ef7eb2e8f9f7	3461	}
<>	144:ef7eb2e8f9f7	3462	}
<>	144:ef7eb2e8f9f7	3463
<>	144:ef7eb2e8f9f7	3464	return HAL_OK;
<>	144:ef7eb2e8f9f7	3465	}
<>	144:ef7eb2e8f9f7	3466
<>	144:ef7eb2e8f9f7	3467	/**
AnnaBridge	181:57724642e740	3468	* @brief Handle SPI FIFO Communication Timeout.
AnnaBridge	181:57724642e740	3469	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
AnnaBridge	167:e84263d55307	3470	* the configuration information for SPI module.
AnnaBridge	181:57724642e740	3471	* @param Fifo Fifo to check
AnnaBridge	181:57724642e740	3472	* @param State Fifo state to check
AnnaBridge	181:57724642e740	3473	* @param Timeout Timeout duration
AnnaBridge	181:57724642e740	3474	* @param Tickstart tick start value
AnnaBridge	167:e84263d55307	3475	* @retval HAL status
AnnaBridge	167:e84263d55307	3476	*/
AnnaBridge	167:e84263d55307	3477	static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State,
AnnaBridge	167:e84263d55307	3478	uint32_t Timeout, uint32_t Tickstart)
AnnaBridge	167:e84263d55307	3479	{
AnnaBridge	167:e84263d55307	3480	__IO uint8_t tmpreg;
AnnaBridge	167:e84263d55307	3481
AnnaBridge	167:e84263d55307	3482	while ((hspi->Instance->SR & Fifo) != State)
AnnaBridge	167:e84263d55307	3483	{
AnnaBridge	167:e84263d55307	3484	if ((Fifo == SPI_SR_FRLVL) && (State == SPI_FRLVL_EMPTY))
AnnaBridge	167:e84263d55307	3485	{
AnnaBridge	167:e84263d55307	3486	tmpreg = ((__IO uint8_t )&hspi->Instance->DR);
AnnaBridge	167:e84263d55307	3487	/* To avoid GCC warning */
AnnaBridge	167:e84263d55307	3488	UNUSED(tmpreg);
AnnaBridge	167:e84263d55307	3489	}
AnnaBridge	167:e84263d55307	3490
AnnaBridge	167:e84263d55307	3491	if (Timeout != HAL_MAX_DELAY)
AnnaBridge	167:e84263d55307	3492	{
AnnaBridge	167:e84263d55307	3493	if ((Timeout == 0U) \|\| ((HAL_GetTick() - Tickstart) >= Timeout))
AnnaBridge	167:e84263d55307	3494	{
AnnaBridge	167:e84263d55307	3495	/* Disable the SPI and reset the CRC: the CRC value should be cleared
AnnaBridge	167:e84263d55307	3496	on both master and slave sides in order to resynchronize the master
AnnaBridge	167:e84263d55307	3497	and slave for their respective CRC calculation */
AnnaBridge	167:e84263d55307	3498
AnnaBridge	167:e84263d55307	3499	/* Disable TXE, RXNE and ERR interrupts for the interrupt process */
AnnaBridge	167:e84263d55307	3500	__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE \| SPI_IT_RXNE \| SPI_IT_ERR));
AnnaBridge	167:e84263d55307	3501
AnnaBridge	167:e84263d55307	3502	if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
AnnaBridge	167:e84263d55307	3503	\|\| (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
AnnaBridge	167:e84263d55307	3504	{
AnnaBridge	167:e84263d55307	3505	/* Disable SPI peripheral */
AnnaBridge	167:e84263d55307	3506	__HAL_SPI_DISABLE(hspi);
AnnaBridge	167:e84263d55307	3507	}
AnnaBridge	167:e84263d55307	3508
AnnaBridge	167:e84263d55307	3509	/* Reset CRC Calculation */
AnnaBridge	167:e84263d55307	3510	if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
AnnaBridge	167:e84263d55307	3511	{
AnnaBridge	167:e84263d55307	3512	SPI_RESET_CRC(hspi);
AnnaBridge	167:e84263d55307	3513	}
AnnaBridge	167:e84263d55307	3514
AnnaBridge	167:e84263d55307	3515	hspi->State = HAL_SPI_STATE_READY;
AnnaBridge	167:e84263d55307	3516
AnnaBridge	167:e84263d55307	3517	/* Process Unlocked */
AnnaBridge	167:e84263d55307	3518	__HAL_UNLOCK(hspi);
AnnaBridge	167:e84263d55307	3519
AnnaBridge	167:e84263d55307	3520	return HAL_TIMEOUT;
AnnaBridge	167:e84263d55307	3521	}
AnnaBridge	167:e84263d55307	3522	}
AnnaBridge	167:e84263d55307	3523	}
AnnaBridge	167:e84263d55307	3524
AnnaBridge	167:e84263d55307	3525	return HAL_OK;
AnnaBridge	167:e84263d55307	3526	}
AnnaBridge	167:e84263d55307	3527
AnnaBridge	167:e84263d55307	3528	/**
AnnaBridge	167:e84263d55307	3529	* @brief Handle the check of the RX transaction complete.
AnnaBridge	181:57724642e740	3530	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	3531	* the configuration information for SPI module.
AnnaBridge	181:57724642e740	3532	* @param Timeout Timeout duration
AnnaBridge	181:57724642e740	3533	* @param Tickstart tick start value
AnnaBridge	167:e84263d55307	3534	* @retval HAL status
<>	144:ef7eb2e8f9f7	3535	*/
AnnaBridge	167:e84263d55307	3536	static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart)
<>	144:ef7eb2e8f9f7	3537	{
AnnaBridge	167:e84263d55307	3538	if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
AnnaBridge	167:e84263d55307	3539	\|\| (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
<>	144:ef7eb2e8f9f7	3540	{
<>	144:ef7eb2e8f9f7	3541	/* Disable SPI peripheral */
<>	144:ef7eb2e8f9f7	3542	__HAL_SPI_DISABLE(hspi);
<>	144:ef7eb2e8f9f7	3543	}
AnnaBridge	167:e84263d55307	3544
<>	144:ef7eb2e8f9f7	3545	/* Control the BSY flag */
AnnaBridge	167:e84263d55307	3546	if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	3547	{
AnnaBridge	167:e84263d55307	3548	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
<>	144:ef7eb2e8f9f7	3549	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	3550	}
<>	144:ef7eb2e8f9f7	3551
AnnaBridge	167:e84263d55307	3552	if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
AnnaBridge	167:e84263d55307	3553	\|\| (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
<>	144:ef7eb2e8f9f7	3554	{
<>	144:ef7eb2e8f9f7	3555	/* Empty the FRLVL fifo */
AnnaBridge	167:e84263d55307	3556	if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, Timeout, Tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	3557	{
AnnaBridge	167:e84263d55307	3558	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
<>	144:ef7eb2e8f9f7	3559	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	3560	}
<>	144:ef7eb2e8f9f7	3561	}
<>	144:ef7eb2e8f9f7	3562	return HAL_OK;
<>	144:ef7eb2e8f9f7	3563	}
<>	144:ef7eb2e8f9f7	3564
<>	144:ef7eb2e8f9f7	3565	/**
AnnaBridge	167:e84263d55307	3566	* @brief Handle the check of the RXTX or TX transaction complete.
AnnaBridge	181:57724642e740	3567	* @param hspi SPI handle
AnnaBridge	181:57724642e740	3568	* @param Timeout Timeout duration
AnnaBridge	181:57724642e740	3569	* @param Tickstart tick start value
AnnaBridge	167:e84263d55307	3570	* @retval HAL status
<>	144:ef7eb2e8f9f7	3571	*/
AnnaBridge	167:e84263d55307	3572	static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart)
<>	144:ef7eb2e8f9f7	3573	{
<>	144:ef7eb2e8f9f7	3574	/* Control if the TX fifo is empty */
AnnaBridge	167:e84263d55307	3575	if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FTLVL, SPI_FTLVL_EMPTY, Timeout, Tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	3576	{
AnnaBridge	167:e84263d55307	3577	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
<>	144:ef7eb2e8f9f7	3578	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	3579	}
AnnaBridge	181:57724642e740	3580
<>	144:ef7eb2e8f9f7	3581	/* Control the BSY flag */
AnnaBridge	167:e84263d55307	3582	if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	3583	{
AnnaBridge	167:e84263d55307	3584	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
AnnaBridge	167:e84263d55307	3585	return HAL_TIMEOUT;
AnnaBridge	167:e84263d55307	3586	}
AnnaBridge	167:e84263d55307	3587
AnnaBridge	167:e84263d55307	3588	/* Control if the RX fifo is empty */
AnnaBridge	167:e84263d55307	3589	if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, Timeout, Tickstart) != HAL_OK)
AnnaBridge	167:e84263d55307	3590	{
AnnaBridge	167:e84263d55307	3591	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
<>	144:ef7eb2e8f9f7	3592	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	3593	}
AnnaBridge	181:57724642e740	3594
<>	144:ef7eb2e8f9f7	3595	return HAL_OK;
<>	144:ef7eb2e8f9f7	3596	}
<>	144:ef7eb2e8f9f7	3597
<>	144:ef7eb2e8f9f7	3598	/**
AnnaBridge	167:e84263d55307	3599	* @brief Handle the end of the RXTX transaction.
AnnaBridge	181:57724642e740	3600	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	3601	* the configuration information for SPI module.
<>	144:ef7eb2e8f9f7	3602	* @retval None
<>	144:ef7eb2e8f9f7	3603	*/
<>	144:ef7eb2e8f9f7	3604	static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi)
<>	144:ef7eb2e8f9f7	3605	{
AnnaBridge	167:e84263d55307	3606	uint32_t tickstart = 0U;
AnnaBridge	167:e84263d55307	3607
AnnaBridge	167:e84263d55307	3608	/* Init tickstart for timeout managment*/
AnnaBridge	167:e84263d55307	3609	tickstart = HAL_GetTick();
AnnaBridge	167:e84263d55307	3610
<>	144:ef7eb2e8f9f7	3611	/* Disable ERR interrupt */
<>	144:ef7eb2e8f9f7	3612	__HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
<>	144:ef7eb2e8f9f7	3613
<>	144:ef7eb2e8f9f7	3614	/* Check the end of the transaction */
AnnaBridge	167:e84263d55307	3615	if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	3616	{
AnnaBridge	167:e84263d55307	3617	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
<>	144:ef7eb2e8f9f7	3618	}
<>	144:ef7eb2e8f9f7	3619
AnnaBridge	167:e84263d55307	3620	#if (USE_SPI_CRC != 0U)
<>	144:ef7eb2e8f9f7	3621	/* Check if CRC error occurred */
AnnaBridge	167:e84263d55307	3622	if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
<>	144:ef7eb2e8f9f7	3623	{
<>	144:ef7eb2e8f9f7	3624	hspi->State = HAL_SPI_STATE_READY;
AnnaBridge	167:e84263d55307	3625	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
<>	144:ef7eb2e8f9f7	3626	__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
<>	144:ef7eb2e8f9f7	3627	HAL_SPI_ErrorCallback(hspi);
<>	144:ef7eb2e8f9f7	3628	}
<>	144:ef7eb2e8f9f7	3629	else
<>	144:ef7eb2e8f9f7	3630	{
AnnaBridge	167:e84263d55307	3631	#endif /* USE_SPI_CRC */
AnnaBridge	167:e84263d55307	3632	if (hspi->ErrorCode == HAL_SPI_ERROR_NONE)
<>	144:ef7eb2e8f9f7	3633	{
AnnaBridge	167:e84263d55307	3634	if (hspi->State == HAL_SPI_STATE_BUSY_RX)
<>	144:ef7eb2e8f9f7	3635	{
AnnaBridge	167:e84263d55307	3636	hspi->State = HAL_SPI_STATE_READY;
<>	144:ef7eb2e8f9f7	3637	HAL_SPI_RxCpltCallback(hspi);
<>	144:ef7eb2e8f9f7	3638	}
<>	144:ef7eb2e8f9f7	3639	else
<>	144:ef7eb2e8f9f7	3640	{
AnnaBridge	167:e84263d55307	3641	hspi->State = HAL_SPI_STATE_READY;
<>	144:ef7eb2e8f9f7	3642	HAL_SPI_TxRxCpltCallback(hspi);
<>	144:ef7eb2e8f9f7	3643	}
<>	144:ef7eb2e8f9f7	3644	}
<>	144:ef7eb2e8f9f7	3645	else
<>	144:ef7eb2e8f9f7	3646	{
<>	144:ef7eb2e8f9f7	3647	hspi->State = HAL_SPI_STATE_READY;
<>	144:ef7eb2e8f9f7	3648	HAL_SPI_ErrorCallback(hspi);
<>	144:ef7eb2e8f9f7	3649	}
AnnaBridge	167:e84263d55307	3650	#if (USE_SPI_CRC != 0U)
<>	144:ef7eb2e8f9f7	3651	}
AnnaBridge	167:e84263d55307	3652	#endif /* USE_SPI_CRC */
<>	144:ef7eb2e8f9f7	3653	}
<>	144:ef7eb2e8f9f7	3654
<>	144:ef7eb2e8f9f7	3655	/**
AnnaBridge	167:e84263d55307	3656	* @brief Handle the end of the RX transaction.
AnnaBridge	181:57724642e740	3657	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	3658	* the configuration information for SPI module.
<>	144:ef7eb2e8f9f7	3659	* @retval None
<>	144:ef7eb2e8f9f7	3660	*/
<>	144:ef7eb2e8f9f7	3661	static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi)
<>	144:ef7eb2e8f9f7	3662	{
AnnaBridge	167:e84263d55307	3663	/* Disable RXNE and ERR interrupt */
AnnaBridge	167:e84263d55307	3664	__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE \| SPI_IT_ERR));
AnnaBridge	167:e84263d55307	3665
AnnaBridge	167:e84263d55307	3666	/* Check the end of the transaction */
AnnaBridge	167:e84263d55307	3667	if (SPI_EndRxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
AnnaBridge	167:e84263d55307	3668	{
AnnaBridge	167:e84263d55307	3669	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
AnnaBridge	167:e84263d55307	3670	}
AnnaBridge	167:e84263d55307	3671	hspi->State = HAL_SPI_STATE_READY;
AnnaBridge	167:e84263d55307	3672
AnnaBridge	167:e84263d55307	3673	#if (USE_SPI_CRC != 0U)
AnnaBridge	167:e84263d55307	3674	/* Check if CRC error occurred */
AnnaBridge	167:e84263d55307	3675	if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
AnnaBridge	167:e84263d55307	3676	{
AnnaBridge	167:e84263d55307	3677	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
AnnaBridge	167:e84263d55307	3678	__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
AnnaBridge	167:e84263d55307	3679	HAL_SPI_ErrorCallback(hspi);
AnnaBridge	167:e84263d55307	3680	}
AnnaBridge	167:e84263d55307	3681	else
AnnaBridge	167:e84263d55307	3682	{
AnnaBridge	167:e84263d55307	3683	#endif /* USE_SPI_CRC */
AnnaBridge	167:e84263d55307	3684	if (hspi->ErrorCode == HAL_SPI_ERROR_NONE)
<>	144:ef7eb2e8f9f7	3685	{
AnnaBridge	167:e84263d55307	3686	HAL_SPI_RxCpltCallback(hspi);
<>	144:ef7eb2e8f9f7	3687	}
<>	144:ef7eb2e8f9f7	3688	else
<>	144:ef7eb2e8f9f7	3689	{
AnnaBridge	167:e84263d55307	3690	HAL_SPI_ErrorCallback(hspi);
<>	144:ef7eb2e8f9f7	3691	}
AnnaBridge	167:e84263d55307	3692	#if (USE_SPI_CRC != 0U)
AnnaBridge	167:e84263d55307	3693	}
AnnaBridge	167:e84263d55307	3694	#endif /* USE_SPI_CRC */
<>	144:ef7eb2e8f9f7	3695	}
<>	144:ef7eb2e8f9f7	3696
<>	144:ef7eb2e8f9f7	3697	/**
AnnaBridge	167:e84263d55307	3698	* @brief Handle the end of the TX transaction.
AnnaBridge	181:57724642e740	3699	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	3700	* the configuration information for SPI module.
<>	144:ef7eb2e8f9f7	3701	* @retval None
<>	144:ef7eb2e8f9f7	3702	*/
<>	144:ef7eb2e8f9f7	3703	static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi)
<>	144:ef7eb2e8f9f7	3704	{
AnnaBridge	167:e84263d55307	3705	uint32_t tickstart = 0U;
AnnaBridge	167:e84263d55307	3706
AnnaBridge	167:e84263d55307	3707	/* Init tickstart for timeout management*/
AnnaBridge	167:e84263d55307	3708	tickstart = HAL_GetTick();
AnnaBridge	167:e84263d55307	3709
<>	144:ef7eb2e8f9f7	3710	/* Disable TXE and ERR interrupt */
<>	144:ef7eb2e8f9f7	3711	__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE \| SPI_IT_ERR));
<>	144:ef7eb2e8f9f7	3712
<>	144:ef7eb2e8f9f7	3713	/* Check the end of the transaction */
AnnaBridge	167:e84263d55307	3714	if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	3715	{
AnnaBridge	167:e84263d55307	3716	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
<>	144:ef7eb2e8f9f7	3717	}
<>	144:ef7eb2e8f9f7	3718
<>	144:ef7eb2e8f9f7	3719	/* Clear overrun flag in 2 Lines communication mode because received is not read */
AnnaBridge	167:e84263d55307	3720	if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
<>	144:ef7eb2e8f9f7	3721	{
<>	144:ef7eb2e8f9f7	3722	__HAL_SPI_CLEAR_OVRFLAG(hspi);
<>	144:ef7eb2e8f9f7	3723	}
<>	144:ef7eb2e8f9f7	3724
<>	144:ef7eb2e8f9f7	3725	hspi->State = HAL_SPI_STATE_READY;
AnnaBridge	167:e84263d55307	3726	if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
<>	144:ef7eb2e8f9f7	3727	{
<>	144:ef7eb2e8f9f7	3728	HAL_SPI_ErrorCallback(hspi);
<>	144:ef7eb2e8f9f7	3729	}
<>	144:ef7eb2e8f9f7	3730	else
<>	144:ef7eb2e8f9f7	3731	{
<>	144:ef7eb2e8f9f7	3732	HAL_SPI_TxCpltCallback(hspi);
<>	144:ef7eb2e8f9f7	3733	}
<>	144:ef7eb2e8f9f7	3734	}
<>	144:ef7eb2e8f9f7	3735
<>	144:ef7eb2e8f9f7	3736	/**
AnnaBridge	167:e84263d55307	3737	* @brief Handle abort a Rx transaction.
AnnaBridge	181:57724642e740	3738	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
AnnaBridge	167:e84263d55307	3739	* the configuration information for SPI module.
AnnaBridge	167:e84263d55307	3740	* @retval None
AnnaBridge	167:e84263d55307	3741	*/
AnnaBridge	167:e84263d55307	3742	static void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi)
AnnaBridge	167:e84263d55307	3743	{
AnnaBridge	167:e84263d55307	3744	__IO uint32_t count;
AnnaBridge	181:57724642e740	3745
AnnaBridge	167:e84263d55307	3746	/* Disable SPI Peripheral */
AnnaBridge	167:e84263d55307	3747	__HAL_SPI_DISABLE(hspi);
AnnaBridge	181:57724642e740	3748
AnnaBridge	167:e84263d55307	3749	count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
AnnaBridge	167:e84263d55307	3750
AnnaBridge	167:e84263d55307	3751	/* Disable TXEIE, RXNEIE and ERRIE(mode fault event, overrun error, TI frame error) interrupts */
AnnaBridge	167:e84263d55307	3752	CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXEIE \| SPI_CR2_RXNEIE \| SPI_CR2_ERRIE));
AnnaBridge	181:57724642e740	3753
AnnaBridge	167:e84263d55307	3754	/* Check RXNEIE is disabled */
AnnaBridge	167:e84263d55307	3755	do
AnnaBridge	167:e84263d55307	3756	{
AnnaBridge	167:e84263d55307	3757	if (count-- == 0U)
AnnaBridge	167:e84263d55307	3758	{
AnnaBridge	167:e84263d55307	3759	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
AnnaBridge	167:e84263d55307	3760	break;
AnnaBridge	167:e84263d55307	3761	}
AnnaBridge	167:e84263d55307	3762	}
AnnaBridge	167:e84263d55307	3763	while (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE));
AnnaBridge	167:e84263d55307	3764
AnnaBridge	167:e84263d55307	3765	/* Control the BSY flag */
AnnaBridge	167:e84263d55307	3766	if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
AnnaBridge	167:e84263d55307	3767	{
AnnaBridge	167:e84263d55307	3768	hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
AnnaBridge	167:e84263d55307	3769	}
AnnaBridge	167:e84263d55307	3770
AnnaBridge	167:e84263d55307	3771	/* Empty the FRLVL fifo */
AnnaBridge	167:e84263d55307	3772	if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
AnnaBridge	167:e84263d55307	3773	{
AnnaBridge	167:e84263d55307	3774	hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
AnnaBridge	167:e84263d55307	3775	}
AnnaBridge	167:e84263d55307	3776
AnnaBridge	167:e84263d55307	3777	hspi->State = HAL_SPI_STATE_ABORT;
AnnaBridge	167:e84263d55307	3778	}
AnnaBridge	167:e84263d55307	3779
AnnaBridge	167:e84263d55307	3780	/**
AnnaBridge	167:e84263d55307	3781	* @brief Handle abort a Tx or Rx/Tx transaction.
AnnaBridge	181:57724642e740	3782	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
AnnaBridge	167:e84263d55307	3783	* the configuration information for SPI module.
AnnaBridge	167:e84263d55307	3784	* @retval None
AnnaBridge	167:e84263d55307	3785	*/
AnnaBridge	167:e84263d55307	3786	static void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi)
AnnaBridge	167:e84263d55307	3787	{
AnnaBridge	167:e84263d55307	3788	__IO uint32_t count;
AnnaBridge	181:57724642e740	3789
AnnaBridge	167:e84263d55307	3790	count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
AnnaBridge	181:57724642e740	3791
AnnaBridge	167:e84263d55307	3792	/* Disable TXEIE, RXNEIE and ERRIE(mode fault event, overrun error, TI frame error) interrupts */
AnnaBridge	167:e84263d55307	3793	CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXEIE \| SPI_CR2_RXNEIE \| SPI_CR2_ERRIE));
AnnaBridge	181:57724642e740	3794
AnnaBridge	167:e84263d55307	3795	/* Check TXEIE is disabled */
AnnaBridge	167:e84263d55307	3796	do
AnnaBridge	167:e84263d55307	3797	{
AnnaBridge	167:e84263d55307	3798	if (count-- == 0U)
AnnaBridge	167:e84263d55307	3799	{
AnnaBridge	167:e84263d55307	3800	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
AnnaBridge	167:e84263d55307	3801	break;
AnnaBridge	167:e84263d55307	3802	}
AnnaBridge	167:e84263d55307	3803	}
AnnaBridge	167:e84263d55307	3804	while (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE));
AnnaBridge	167:e84263d55307	3805
AnnaBridge	167:e84263d55307	3806	if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
AnnaBridge	167:e84263d55307	3807	{
AnnaBridge	167:e84263d55307	3808	hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
AnnaBridge	167:e84263d55307	3809	}
AnnaBridge	167:e84263d55307	3810
AnnaBridge	167:e84263d55307	3811	/* Disable SPI Peripheral */
AnnaBridge	167:e84263d55307	3812	__HAL_SPI_DISABLE(hspi);
AnnaBridge	167:e84263d55307	3813
AnnaBridge	167:e84263d55307	3814	/* Empty the FRLVL fifo */
AnnaBridge	167:e84263d55307	3815	if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
AnnaBridge	167:e84263d55307	3816	{
AnnaBridge	167:e84263d55307	3817	hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
AnnaBridge	167:e84263d55307	3818	}
AnnaBridge	167:e84263d55307	3819
AnnaBridge	167:e84263d55307	3820	hspi->State = HAL_SPI_STATE_ABORT;
AnnaBridge	167:e84263d55307	3821	}
AnnaBridge	167:e84263d55307	3822
AnnaBridge	167:e84263d55307	3823	/**
<>	144:ef7eb2e8f9f7	3824	* @}
<>	144:ef7eb2e8f9f7	3825	*/
<>	144:ef7eb2e8f9f7	3826
<>	144:ef7eb2e8f9f7	3827	#endif /* HAL_SPI_MODULE_ENABLED */
<>	144:ef7eb2e8f9f7	3828
<>	144:ef7eb2e8f9f7	3829	/**
<>	144:ef7eb2e8f9f7	3830	* @}
<>	144:ef7eb2e8f9f7	3831	*/
<>	144:ef7eb2e8f9f7	3832
<>	144:ef7eb2e8f9f7	3833	/**
<>	144:ef7eb2e8f9f7	3834	* @}
<>	144:ef7eb2e8f9f7	3835	*/
<>	144:ef7eb2e8f9f7	3836
<>	144:ef7eb2e8f9f7	3837	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/