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targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/efm32lg_timer.h@0:9b334a45a8ff, 2015-10-01 (annotated)

Committer:
bogdanm
Date:
Thu Oct 01 15:25:22 2015 +0300
Revision:
0:9b334a45a8ff
Child:
50:a417edff4437
Initial commit on mbed-dev



Replaces mbed-src (now inactive)

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 0:9b334a45a8ff 1 /**************************************************************************//**
bogdanm 0:9b334a45a8ff 2 * @file efm32lg_timer.h
bogdanm 0:9b334a45a8ff 3 * @brief EFM32LG_TIMER register and bit field definitions
bogdanm 0:9b334a45a8ff 4 * @version 3.20.6
bogdanm 0:9b334a45a8ff 5 ******************************************************************************
bogdanm 0:9b334a45a8ff 6 * @section License
bogdanm 0:9b334a45a8ff 7 * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
bogdanm 0:9b334a45a8ff 8 ******************************************************************************
bogdanm 0:9b334a45a8ff 9 *
bogdanm 0:9b334a45a8ff 10 * Permission is granted to anyone to use this software for any purpose,
bogdanm 0:9b334a45a8ff 11 * including commercial applications, and to alter it and redistribute it
bogdanm 0:9b334a45a8ff 12 * freely, subject to the following restrictions:
bogdanm 0:9b334a45a8ff 13 *
bogdanm 0:9b334a45a8ff 14 * 1. The origin of this software must not be misrepresented; you must not
bogdanm 0:9b334a45a8ff 15 * claim that you wrote the original software.@n
bogdanm 0:9b334a45a8ff 16 * 2. Altered source versions must be plainly marked as such, and must not be
bogdanm 0:9b334a45a8ff 17 * misrepresented as being the original software.@n
bogdanm 0:9b334a45a8ff 18 * 3. This notice may not be removed or altered from any source distribution.
bogdanm 0:9b334a45a8ff 19 *
bogdanm 0:9b334a45a8ff 20 * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
bogdanm 0:9b334a45a8ff 21 * has no obligation to support this Software. Silicon Laboratories, Inc. is
bogdanm 0:9b334a45a8ff 22 * providing the Software "AS IS", with no express or implied warranties of any
bogdanm 0:9b334a45a8ff 23 * kind, including, but not limited to, any implied warranties of
bogdanm 0:9b334a45a8ff 24 * merchantability or fitness for any particular purpose or warranties against
bogdanm 0:9b334a45a8ff 25 * infringement of any proprietary rights of a third party.
bogdanm 0:9b334a45a8ff 26 *
bogdanm 0:9b334a45a8ff 27 * Silicon Laboratories, Inc. will not be liable for any consequential,
bogdanm 0:9b334a45a8ff 28 * incidental, or special damages, or any other relief, or for any claim by
bogdanm 0:9b334a45a8ff 29 * any third party, arising from your use of this Software.
bogdanm 0:9b334a45a8ff 30 *
bogdanm 0:9b334a45a8ff 31 *****************************************************************************/
bogdanm 0:9b334a45a8ff 32 /**************************************************************************//**
bogdanm 0:9b334a45a8ff 33 * @defgroup EFM32LG_TIMER
bogdanm 0:9b334a45a8ff 34 * @{
bogdanm 0:9b334a45a8ff 35 * @brief EFM32LG_TIMER Register Declaration
bogdanm 0:9b334a45a8ff 36 *****************************************************************************/
bogdanm 0:9b334a45a8ff 37 typedef struct
bogdanm 0:9b334a45a8ff 38 {
bogdanm 0:9b334a45a8ff 39 __IO uint32_t CTRL; /**< Control Register */
bogdanm 0:9b334a45a8ff 40 __IO uint32_t CMD; /**< Command Register */
bogdanm 0:9b334a45a8ff 41 __I uint32_t STATUS; /**< Status Register */
bogdanm 0:9b334a45a8ff 42 __IO uint32_t IEN; /**< Interrupt Enable Register */
bogdanm 0:9b334a45a8ff 43 __I uint32_t IF; /**< Interrupt Flag Register */
bogdanm 0:9b334a45a8ff 44 __IO uint32_t IFS; /**< Interrupt Flag Set Register */
bogdanm 0:9b334a45a8ff 45 __IO uint32_t IFC; /**< Interrupt Flag Clear Register */
bogdanm 0:9b334a45a8ff 46 __IO uint32_t TOP; /**< Counter Top Value Register */
bogdanm 0:9b334a45a8ff 47 __IO uint32_t TOPB; /**< Counter Top Value Buffer Register */
bogdanm 0:9b334a45a8ff 48 __IO uint32_t CNT; /**< Counter Value Register */
bogdanm 0:9b334a45a8ff 49 __IO uint32_t ROUTE; /**< I/O Routing Register */
bogdanm 0:9b334a45a8ff 50
bogdanm 0:9b334a45a8ff 51 uint32_t RESERVED0[1]; /**< Reserved registers */
bogdanm 0:9b334a45a8ff 52
bogdanm 0:9b334a45a8ff 53 TIMER_CC_TypeDef CC[3]; /**< Compare/Capture Channel */
bogdanm 0:9b334a45a8ff 54
bogdanm 0:9b334a45a8ff 55 uint32_t RESERVED1[4]; /**< Reserved for future use **/
bogdanm 0:9b334a45a8ff 56 __IO uint32_t DTCTRL; /**< DTI Control Register */
bogdanm 0:9b334a45a8ff 57 __IO uint32_t DTTIME; /**< DTI Time Control Register */
bogdanm 0:9b334a45a8ff 58 __IO uint32_t DTFC; /**< DTI Fault Configuration Register */
bogdanm 0:9b334a45a8ff 59 __IO uint32_t DTOGEN; /**< DTI Output Generation Enable Register */
bogdanm 0:9b334a45a8ff 60 __I uint32_t DTFAULT; /**< DTI Fault Register */
bogdanm 0:9b334a45a8ff 61 __O uint32_t DTFAULTC; /**< DTI Fault Clear Register */
bogdanm 0:9b334a45a8ff 62 __IO uint32_t DTLOCK; /**< DTI Configuration Lock Register */
bogdanm 0:9b334a45a8ff 63 } TIMER_TypeDef; /** @} */
bogdanm 0:9b334a45a8ff 64
bogdanm 0:9b334a45a8ff 65 /**************************************************************************//**
bogdanm 0:9b334a45a8ff 66 * @defgroup EFM32LG_TIMER_BitFields
bogdanm 0:9b334a45a8ff 67 * @{
bogdanm 0:9b334a45a8ff 68 *****************************************************************************/
bogdanm 0:9b334a45a8ff 69
bogdanm 0:9b334a45a8ff 70 /* Bit fields for TIMER CTRL */
bogdanm 0:9b334a45a8ff 71 #define _TIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for TIMER_CTRL */
bogdanm 0:9b334a45a8ff 72 #define _TIMER_CTRL_MASK 0x3F032FFBUL /**< Mask for TIMER_CTRL */
bogdanm 0:9b334a45a8ff 73 #define _TIMER_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */
bogdanm 0:9b334a45a8ff 74 #define _TIMER_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */
bogdanm 0:9b334a45a8ff 75 #define _TIMER_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */
bogdanm 0:9b334a45a8ff 76 #define _TIMER_CTRL_MODE_UP 0x00000000UL /**< Mode UP for TIMER_CTRL */
bogdanm 0:9b334a45a8ff 77 #define _TIMER_CTRL_MODE_DOWN 0x00000001UL /**< Mode DOWN for TIMER_CTRL */
bogdanm 0:9b334a45a8ff 78 #define _TIMER_CTRL_MODE_UPDOWN 0x00000002UL /**< Mode UPDOWN for TIMER_CTRL */
bogdanm 0:9b334a45a8ff 79 #define _TIMER_CTRL_MODE_QDEC 0x00000003UL /**< Mode QDEC for TIMER_CTRL */
bogdanm 0:9b334a45a8ff 80 #define TIMER_CTRL_MODE_DEFAULT (_TIMER_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CTRL */
bogdanm 0:9b334a45a8ff 81 #define TIMER_CTRL_MODE_UP (_TIMER_CTRL_MODE_UP << 0) /**< Shifted mode UP for TIMER_CTRL */
bogdanm 0:9b334a45a8ff 82 #define TIMER_CTRL_MODE_DOWN (_TIMER_CTRL_MODE_DOWN << 0) /**< Shifted mode DOWN for TIMER_CTRL */
bogdanm 0:9b334a45a8ff 83 #define TIMER_CTRL_MODE_UPDOWN (_TIMER_CTRL_MODE_UPDOWN << 0) /**< Shifted mode UPDOWN for TIMER_CTRL */
bogdanm 0:9b334a45a8ff 84 #define TIMER_CTRL_MODE_QDEC (_TIMER_CTRL_MODE_QDEC << 0) /**< Shifted mode QDEC for TIMER_CTRL */
bogdanm 0:9b334a45a8ff 85 #define TIMER_CTRL_SYNC (0x1UL << 3) /**< Timer Start/Stop/Reload Synchronization */
bogdanm 0:9b334a45a8ff 86 #define _TIMER_CTRL_SYNC_SHIFT 3 /**< Shift value for TIMER_SYNC */
bogdanm 0:9b334a45a8ff 87 #define _TIMER_CTRL_SYNC_MASK 0x8UL /**< Bit mask for TIMER_SYNC */
bogdanm 0:9b334a45a8ff 88 #define _TIMER_CTRL_SYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */
bogdanm 0:9b334a45a8ff 89 #define TIMER_CTRL_SYNC_DEFAULT (_TIMER_CTRL_SYNC_DEFAULT << 3) /**< Shifted mode DEFAULT for TIMER_CTRL */
bogdanm 0:9b334a45a8ff 90 #define TIMER_CTRL_OSMEN (0x1UL << 4) /**< One-shot Mode Enable */
bogdanm 0:9b334a45a8ff 91 #define _TIMER_CTRL_OSMEN_SHIFT 4 /**< Shift value for TIMER_OSMEN */
bogdanm 0:9b334a45a8ff 92 #define _TIMER_CTRL_OSMEN_MASK 0x10UL /**< Bit mask for TIMER_OSMEN */
bogdanm 0:9b334a45a8ff 93 #define _TIMER_CTRL_OSMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */
bogdanm 0:9b334a45a8ff 94 #define TIMER_CTRL_OSMEN_DEFAULT (_TIMER_CTRL_OSMEN_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_CTRL */
bogdanm 0:9b334a45a8ff 95 #define TIMER_CTRL_QDM (0x1UL << 5) /**< Quadrature Decoder Mode Selection */
bogdanm 0:9b334a45a8ff 96 #define _TIMER_CTRL_QDM_SHIFT 5 /**< Shift value for TIMER_QDM */
bogdanm 0:9b334a45a8ff 97 #define _TIMER_CTRL_QDM_MASK 0x20UL /**< Bit mask for TIMER_QDM */
bogdanm 0:9b334a45a8ff 98 #define _TIMER_CTRL_QDM_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */
bogdanm 0:9b334a45a8ff 99 #define _TIMER_CTRL_QDM_X2 0x00000000UL /**< Mode X2 for TIMER_CTRL */
bogdanm 0:9b334a45a8ff 100 #define _TIMER_CTRL_QDM_X4 0x00000001UL /**< Mode X4 for TIMER_CTRL */
bogdanm 0:9b334a45a8ff 101 #define TIMER_CTRL_QDM_DEFAULT (_TIMER_CTRL_QDM_DEFAULT << 5) /**< Shifted mode DEFAULT for TIMER_CTRL */
bogdanm 0:9b334a45a8ff 102 #define TIMER_CTRL_QDM_X2 (_TIMER_CTRL_QDM_X2 << 5) /**< Shifted mode X2 for TIMER_CTRL */
bogdanm 0:9b334a45a8ff 103 #define TIMER_CTRL_QDM_X4 (_TIMER_CTRL_QDM_X4 << 5) /**< Shifted mode X4 for TIMER_CTRL */
bogdanm 0:9b334a45a8ff 104 #define TIMER_CTRL_DEBUGRUN (0x1UL << 6) /**< Debug Mode Run Enable */
bogdanm 0:9b334a45a8ff 105 #define _TIMER_CTRL_DEBUGRUN_SHIFT 6 /**< Shift value for TIMER_DEBUGRUN */
bogdanm 0:9b334a45a8ff 106 #define _TIMER_CTRL_DEBUGRUN_MASK 0x40UL /**< Bit mask for TIMER_DEBUGRUN */
bogdanm 0:9b334a45a8ff 107 #define _TIMER_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */
bogdanm 0:9b334a45a8ff 108 #define TIMER_CTRL_DEBUGRUN_DEFAULT (_TIMER_CTRL_DEBUGRUN_DEFAULT << 6) /**< Shifted mode DEFAULT for TIMER_CTRL */
bogdanm 0:9b334a45a8ff 109 #define TIMER_CTRL_DMACLRACT (0x1UL << 7) /**< DMA Request Clear on Active */
bogdanm 0:9b334a45a8ff 110 #define _TIMER_CTRL_DMACLRACT_SHIFT 7 /**< Shift value for TIMER_DMACLRACT */
bogdanm 0:9b334a45a8ff 111 #define _TIMER_CTRL_DMACLRACT_MASK 0x80UL /**< Bit mask for TIMER_DMACLRACT */
bogdanm 0:9b334a45a8ff 112 #define _TIMER_CTRL_DMACLRACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */
bogdanm 0:9b334a45a8ff 113 #define TIMER_CTRL_DMACLRACT_DEFAULT (_TIMER_CTRL_DMACLRACT_DEFAULT << 7) /**< Shifted mode DEFAULT for TIMER_CTRL */
bogdanm 0:9b334a45a8ff 114 #define _TIMER_CTRL_RISEA_SHIFT 8 /**< Shift value for TIMER_RISEA */
bogdanm 0:9b334a45a8ff 115 #define _TIMER_CTRL_RISEA_MASK 0x300UL /**< Bit mask for TIMER_RISEA */
bogdanm 0:9b334a45a8ff 116 #define _TIMER_CTRL_RISEA_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */
bogdanm 0:9b334a45a8ff 117 #define _TIMER_CTRL_RISEA_NONE 0x00000000UL /**< Mode NONE for TIMER_CTRL */
bogdanm 0:9b334a45a8ff 118 #define _TIMER_CTRL_RISEA_START 0x00000001UL /**< Mode START for TIMER_CTRL */
bogdanm 0:9b334a45a8ff 119 #define _TIMER_CTRL_RISEA_STOP 0x00000002UL /**< Mode STOP for TIMER_CTRL */
bogdanm 0:9b334a45a8ff 120 #define _TIMER_CTRL_RISEA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for TIMER_CTRL */
bogdanm 0:9b334a45a8ff 121 #define TIMER_CTRL_RISEA_DEFAULT (_TIMER_CTRL_RISEA_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_CTRL */
bogdanm 0:9b334a45a8ff 122 #define TIMER_CTRL_RISEA_NONE (_TIMER_CTRL_RISEA_NONE << 8) /**< Shifted mode NONE for TIMER_CTRL */
bogdanm 0:9b334a45a8ff 123 #define TIMER_CTRL_RISEA_START (_TIMER_CTRL_RISEA_START << 8) /**< Shifted mode START for TIMER_CTRL */
bogdanm 0:9b334a45a8ff 124 #define TIMER_CTRL_RISEA_STOP (_TIMER_CTRL_RISEA_STOP << 8) /**< Shifted mode STOP for TIMER_CTRL */
bogdanm 0:9b334a45a8ff 125 #define TIMER_CTRL_RISEA_RELOADSTART (_TIMER_CTRL_RISEA_RELOADSTART << 8) /**< Shifted mode RELOADSTART for TIMER_CTRL */
bogdanm 0:9b334a45a8ff 126 #define _TIMER_CTRL_FALLA_SHIFT 10 /**< Shift value for TIMER_FALLA */
bogdanm 0:9b334a45a8ff 127 #define _TIMER_CTRL_FALLA_MASK 0xC00UL /**< Bit mask for TIMER_FALLA */
bogdanm 0:9b334a45a8ff 128 #define _TIMER_CTRL_FALLA_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */
bogdanm 0:9b334a45a8ff 129 #define _TIMER_CTRL_FALLA_NONE 0x00000000UL /**< Mode NONE for TIMER_CTRL */
bogdanm 0:9b334a45a8ff 130 #define _TIMER_CTRL_FALLA_START 0x00000001UL /**< Mode START for TIMER_CTRL */
bogdanm 0:9b334a45a8ff 131 #define _TIMER_CTRL_FALLA_STOP 0x00000002UL /**< Mode STOP for TIMER_CTRL */
bogdanm 0:9b334a45a8ff 132 #define _TIMER_CTRL_FALLA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for TIMER_CTRL */
bogdanm 0:9b334a45a8ff 133 #define TIMER_CTRL_FALLA_DEFAULT (_TIMER_CTRL_FALLA_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_CTRL */
bogdanm 0:9b334a45a8ff 134 #define TIMER_CTRL_FALLA_NONE (_TIMER_CTRL_FALLA_NONE << 10) /**< Shifted mode NONE for TIMER_CTRL */
bogdanm 0:9b334a45a8ff 135 #define TIMER_CTRL_FALLA_START (_TIMER_CTRL_FALLA_START << 10) /**< Shifted mode START for TIMER_CTRL */
bogdanm 0:9b334a45a8ff 136 #define TIMER_CTRL_FALLA_STOP (_TIMER_CTRL_FALLA_STOP << 10) /**< Shifted mode STOP for TIMER_CTRL */
bogdanm 0:9b334a45a8ff 137 #define TIMER_CTRL_FALLA_RELOADSTART (_TIMER_CTRL_FALLA_RELOADSTART << 10) /**< Shifted mode RELOADSTART for TIMER_CTRL */
bogdanm 0:9b334a45a8ff 138 #define TIMER_CTRL_X2CNT (0x1UL << 13) /**< 2x Count Mode */
bogdanm 0:9b334a45a8ff 139 #define _TIMER_CTRL_X2CNT_SHIFT 13 /**< Shift value for TIMER_X2CNT */
bogdanm 0:9b334a45a8ff 140 #define _TIMER_CTRL_X2CNT_MASK 0x2000UL /**< Bit mask for TIMER_X2CNT */
bogdanm 0:9b334a45a8ff 141 #define _TIMER_CTRL_X2CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */
bogdanm 0:9b334a45a8ff 142 #define TIMER_CTRL_X2CNT_DEFAULT (_TIMER_CTRL_X2CNT_DEFAULT << 13) /**< Shifted mode DEFAULT for TIMER_CTRL */
bogdanm 0:9b334a45a8ff 143 #define _TIMER_CTRL_CLKSEL_SHIFT 16 /**< Shift value for TIMER_CLKSEL */
bogdanm 0:9b334a45a8ff 144 #define _TIMER_CTRL_CLKSEL_MASK 0x30000UL /**< Bit mask for TIMER_CLKSEL */
bogdanm 0:9b334a45a8ff 145 #define _TIMER_CTRL_CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */
bogdanm 0:9b334a45a8ff 146 #define _TIMER_CTRL_CLKSEL_PRESCHFPERCLK 0x00000000UL /**< Mode PRESCHFPERCLK for TIMER_CTRL */
bogdanm 0:9b334a45a8ff 147 #define _TIMER_CTRL_CLKSEL_CC1 0x00000001UL /**< Mode CC1 for TIMER_CTRL */
bogdanm 0:9b334a45a8ff 148 #define _TIMER_CTRL_CLKSEL_TIMEROUF 0x00000002UL /**< Mode TIMEROUF for TIMER_CTRL */
bogdanm 0:9b334a45a8ff 149 #define TIMER_CTRL_CLKSEL_DEFAULT (_TIMER_CTRL_CLKSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for TIMER_CTRL */
bogdanm 0:9b334a45a8ff 150 #define TIMER_CTRL_CLKSEL_PRESCHFPERCLK (_TIMER_CTRL_CLKSEL_PRESCHFPERCLK << 16) /**< Shifted mode PRESCHFPERCLK for TIMER_CTRL */
bogdanm 0:9b334a45a8ff 151 #define TIMER_CTRL_CLKSEL_CC1 (_TIMER_CTRL_CLKSEL_CC1 << 16) /**< Shifted mode CC1 for TIMER_CTRL */
bogdanm 0:9b334a45a8ff 152 #define TIMER_CTRL_CLKSEL_TIMEROUF (_TIMER_CTRL_CLKSEL_TIMEROUF << 16) /**< Shifted mode TIMEROUF for TIMER_CTRL */
bogdanm 0:9b334a45a8ff 153 #define _TIMER_CTRL_PRESC_SHIFT 24 /**< Shift value for TIMER_PRESC */
bogdanm 0:9b334a45a8ff 154 #define _TIMER_CTRL_PRESC_MASK 0xF000000UL /**< Bit mask for TIMER_PRESC */
bogdanm 0:9b334a45a8ff 155 #define _TIMER_CTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */
bogdanm 0:9b334a45a8ff 156 #define _TIMER_CTRL_PRESC_DIV1 0x00000000UL /**< Mode DIV1 for TIMER_CTRL */
bogdanm 0:9b334a45a8ff 157 #define _TIMER_CTRL_PRESC_DIV2 0x00000001UL /**< Mode DIV2 for TIMER_CTRL */
bogdanm 0:9b334a45a8ff 158 #define _TIMER_CTRL_PRESC_DIV4 0x00000002UL /**< Mode DIV4 for TIMER_CTRL */
bogdanm 0:9b334a45a8ff 159 #define _TIMER_CTRL_PRESC_DIV8 0x00000003UL /**< Mode DIV8 for TIMER_CTRL */
bogdanm 0:9b334a45a8ff 160 #define _TIMER_CTRL_PRESC_DIV16 0x00000004UL /**< Mode DIV16 for TIMER_CTRL */
bogdanm 0:9b334a45a8ff 161 #define _TIMER_CTRL_PRESC_DIV32 0x00000005UL /**< Mode DIV32 for TIMER_CTRL */
bogdanm 0:9b334a45a8ff 162 #define _TIMER_CTRL_PRESC_DIV64 0x00000006UL /**< Mode DIV64 for TIMER_CTRL */
bogdanm 0:9b334a45a8ff 163 #define _TIMER_CTRL_PRESC_DIV128 0x00000007UL /**< Mode DIV128 for TIMER_CTRL */
bogdanm 0:9b334a45a8ff 164 #define _TIMER_CTRL_PRESC_DIV256 0x00000008UL /**< Mode DIV256 for TIMER_CTRL */
bogdanm 0:9b334a45a8ff 165 #define _TIMER_CTRL_PRESC_DIV512 0x00000009UL /**< Mode DIV512 for TIMER_CTRL */
bogdanm 0:9b334a45a8ff 166 #define _TIMER_CTRL_PRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for TIMER_CTRL */
bogdanm 0:9b334a45a8ff 167 #define TIMER_CTRL_PRESC_DEFAULT (_TIMER_CTRL_PRESC_DEFAULT << 24) /**< Shifted mode DEFAULT for TIMER_CTRL */
bogdanm 0:9b334a45a8ff 168 #define TIMER_CTRL_PRESC_DIV1 (_TIMER_CTRL_PRESC_DIV1 << 24) /**< Shifted mode DIV1 for TIMER_CTRL */
bogdanm 0:9b334a45a8ff 169 #define TIMER_CTRL_PRESC_DIV2 (_TIMER_CTRL_PRESC_DIV2 << 24) /**< Shifted mode DIV2 for TIMER_CTRL */
bogdanm 0:9b334a45a8ff 170 #define TIMER_CTRL_PRESC_DIV4 (_TIMER_CTRL_PRESC_DIV4 << 24) /**< Shifted mode DIV4 for TIMER_CTRL */
bogdanm 0:9b334a45a8ff 171 #define TIMER_CTRL_PRESC_DIV8 (_TIMER_CTRL_PRESC_DIV8 << 24) /**< Shifted mode DIV8 for TIMER_CTRL */
bogdanm 0:9b334a45a8ff 172 #define TIMER_CTRL_PRESC_DIV16 (_TIMER_CTRL_PRESC_DIV16 << 24) /**< Shifted mode DIV16 for TIMER_CTRL */
bogdanm 0:9b334a45a8ff 173 #define TIMER_CTRL_PRESC_DIV32 (_TIMER_CTRL_PRESC_DIV32 << 24) /**< Shifted mode DIV32 for TIMER_CTRL */
bogdanm 0:9b334a45a8ff 174 #define TIMER_CTRL_PRESC_DIV64 (_TIMER_CTRL_PRESC_DIV64 << 24) /**< Shifted mode DIV64 for TIMER_CTRL */
bogdanm 0:9b334a45a8ff 175 #define TIMER_CTRL_PRESC_DIV128 (_TIMER_CTRL_PRESC_DIV128 << 24) /**< Shifted mode DIV128 for TIMER_CTRL */
bogdanm 0:9b334a45a8ff 176 #define TIMER_CTRL_PRESC_DIV256 (_TIMER_CTRL_PRESC_DIV256 << 24) /**< Shifted mode DIV256 for TIMER_CTRL */
bogdanm 0:9b334a45a8ff 177 #define TIMER_CTRL_PRESC_DIV512 (_TIMER_CTRL_PRESC_DIV512 << 24) /**< Shifted mode DIV512 for TIMER_CTRL */
bogdanm 0:9b334a45a8ff 178 #define TIMER_CTRL_PRESC_DIV1024 (_TIMER_CTRL_PRESC_DIV1024 << 24) /**< Shifted mode DIV1024 for TIMER_CTRL */
bogdanm 0:9b334a45a8ff 179 #define TIMER_CTRL_ATI (0x1UL << 28) /**< Always Track Inputs */
bogdanm 0:9b334a45a8ff 180 #define _TIMER_CTRL_ATI_SHIFT 28 /**< Shift value for TIMER_ATI */
bogdanm 0:9b334a45a8ff 181 #define _TIMER_CTRL_ATI_MASK 0x10000000UL /**< Bit mask for TIMER_ATI */
bogdanm 0:9b334a45a8ff 182 #define _TIMER_CTRL_ATI_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */
bogdanm 0:9b334a45a8ff 183 #define TIMER_CTRL_ATI_DEFAULT (_TIMER_CTRL_ATI_DEFAULT << 28) /**< Shifted mode DEFAULT for TIMER_CTRL */
bogdanm 0:9b334a45a8ff 184 #define TIMER_CTRL_RSSCOIST (0x1UL << 29) /**< Reload-Start Sets Compare Ouptut initial State */
bogdanm 0:9b334a45a8ff 185 #define _TIMER_CTRL_RSSCOIST_SHIFT 29 /**< Shift value for TIMER_RSSCOIST */
bogdanm 0:9b334a45a8ff 186 #define _TIMER_CTRL_RSSCOIST_MASK 0x20000000UL /**< Bit mask for TIMER_RSSCOIST */
bogdanm 0:9b334a45a8ff 187 #define _TIMER_CTRL_RSSCOIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */
bogdanm 0:9b334a45a8ff 188 #define TIMER_CTRL_RSSCOIST_DEFAULT (_TIMER_CTRL_RSSCOIST_DEFAULT << 29) /**< Shifted mode DEFAULT for TIMER_CTRL */
bogdanm 0:9b334a45a8ff 189
bogdanm 0:9b334a45a8ff 190 /* Bit fields for TIMER CMD */
bogdanm 0:9b334a45a8ff 191 #define _TIMER_CMD_RESETVALUE 0x00000000UL /**< Default value for TIMER_CMD */
bogdanm 0:9b334a45a8ff 192 #define _TIMER_CMD_MASK 0x00000003UL /**< Mask for TIMER_CMD */
bogdanm 0:9b334a45a8ff 193 #define TIMER_CMD_START (0x1UL << 0) /**< Start Timer */
bogdanm 0:9b334a45a8ff 194 #define _TIMER_CMD_START_SHIFT 0 /**< Shift value for TIMER_START */
bogdanm 0:9b334a45a8ff 195 #define _TIMER_CMD_START_MASK 0x1UL /**< Bit mask for TIMER_START */
bogdanm 0:9b334a45a8ff 196 #define _TIMER_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CMD */
bogdanm 0:9b334a45a8ff 197 #define TIMER_CMD_START_DEFAULT (_TIMER_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CMD */
bogdanm 0:9b334a45a8ff 198 #define TIMER_CMD_STOP (0x1UL << 1) /**< Stop Timer */
bogdanm 0:9b334a45a8ff 199 #define _TIMER_CMD_STOP_SHIFT 1 /**< Shift value for TIMER_STOP */
bogdanm 0:9b334a45a8ff 200 #define _TIMER_CMD_STOP_MASK 0x2UL /**< Bit mask for TIMER_STOP */
bogdanm 0:9b334a45a8ff 201 #define _TIMER_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CMD */
bogdanm 0:9b334a45a8ff 202 #define TIMER_CMD_STOP_DEFAULT (_TIMER_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_CMD */
bogdanm 0:9b334a45a8ff 203
bogdanm 0:9b334a45a8ff 204 /* Bit fields for TIMER STATUS */
bogdanm 0:9b334a45a8ff 205 #define _TIMER_STATUS_RESETVALUE 0x00000000UL /**< Default value for TIMER_STATUS */
bogdanm 0:9b334a45a8ff 206 #define _TIMER_STATUS_MASK 0x07070707UL /**< Mask for TIMER_STATUS */
bogdanm 0:9b334a45a8ff 207 #define TIMER_STATUS_RUNNING (0x1UL << 0) /**< Running */
bogdanm 0:9b334a45a8ff 208 #define _TIMER_STATUS_RUNNING_SHIFT 0 /**< Shift value for TIMER_RUNNING */
bogdanm 0:9b334a45a8ff 209 #define _TIMER_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for TIMER_RUNNING */
bogdanm 0:9b334a45a8ff 210 #define _TIMER_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */
bogdanm 0:9b334a45a8ff 211 #define TIMER_STATUS_RUNNING_DEFAULT (_TIMER_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_STATUS */
bogdanm 0:9b334a45a8ff 212 #define TIMER_STATUS_DIR (0x1UL << 1) /**< Direction */
bogdanm 0:9b334a45a8ff 213 #define _TIMER_STATUS_DIR_SHIFT 1 /**< Shift value for TIMER_DIR */
bogdanm 0:9b334a45a8ff 214 #define _TIMER_STATUS_DIR_MASK 0x2UL /**< Bit mask for TIMER_DIR */
bogdanm 0:9b334a45a8ff 215 #define _TIMER_STATUS_DIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */
bogdanm 0:9b334a45a8ff 216 #define _TIMER_STATUS_DIR_UP 0x00000000UL /**< Mode UP for TIMER_STATUS */
bogdanm 0:9b334a45a8ff 217 #define _TIMER_STATUS_DIR_DOWN 0x00000001UL /**< Mode DOWN for TIMER_STATUS */
bogdanm 0:9b334a45a8ff 218 #define TIMER_STATUS_DIR_DEFAULT (_TIMER_STATUS_DIR_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_STATUS */
bogdanm 0:9b334a45a8ff 219 #define TIMER_STATUS_DIR_UP (_TIMER_STATUS_DIR_UP << 1) /**< Shifted mode UP for TIMER_STATUS */
bogdanm 0:9b334a45a8ff 220 #define TIMER_STATUS_DIR_DOWN (_TIMER_STATUS_DIR_DOWN << 1) /**< Shifted mode DOWN for TIMER_STATUS */
bogdanm 0:9b334a45a8ff 221 #define TIMER_STATUS_TOPBV (0x1UL << 2) /**< TOPB Valid */
bogdanm 0:9b334a45a8ff 222 #define _TIMER_STATUS_TOPBV_SHIFT 2 /**< Shift value for TIMER_TOPBV */
bogdanm 0:9b334a45a8ff 223 #define _TIMER_STATUS_TOPBV_MASK 0x4UL /**< Bit mask for TIMER_TOPBV */
bogdanm 0:9b334a45a8ff 224 #define _TIMER_STATUS_TOPBV_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */
bogdanm 0:9b334a45a8ff 225 #define TIMER_STATUS_TOPBV_DEFAULT (_TIMER_STATUS_TOPBV_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_STATUS */
bogdanm 0:9b334a45a8ff 226 #define TIMER_STATUS_CCVBV0 (0x1UL << 8) /**< CC0 CCVB Valid */
bogdanm 0:9b334a45a8ff 227 #define _TIMER_STATUS_CCVBV0_SHIFT 8 /**< Shift value for TIMER_CCVBV0 */
bogdanm 0:9b334a45a8ff 228 #define _TIMER_STATUS_CCVBV0_MASK 0x100UL /**< Bit mask for TIMER_CCVBV0 */
bogdanm 0:9b334a45a8ff 229 #define _TIMER_STATUS_CCVBV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */
bogdanm 0:9b334a45a8ff 230 #define TIMER_STATUS_CCVBV0_DEFAULT (_TIMER_STATUS_CCVBV0_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_STATUS */
bogdanm 0:9b334a45a8ff 231 #define TIMER_STATUS_CCVBV1 (0x1UL << 9) /**< CC1 CCVB Valid */
bogdanm 0:9b334a45a8ff 232 #define _TIMER_STATUS_CCVBV1_SHIFT 9 /**< Shift value for TIMER_CCVBV1 */
bogdanm 0:9b334a45a8ff 233 #define _TIMER_STATUS_CCVBV1_MASK 0x200UL /**< Bit mask for TIMER_CCVBV1 */
bogdanm 0:9b334a45a8ff 234 #define _TIMER_STATUS_CCVBV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */
bogdanm 0:9b334a45a8ff 235 #define TIMER_STATUS_CCVBV1_DEFAULT (_TIMER_STATUS_CCVBV1_DEFAULT << 9) /**< Shifted mode DEFAULT for TIMER_STATUS */
bogdanm 0:9b334a45a8ff 236 #define TIMER_STATUS_CCVBV2 (0x1UL << 10) /**< CC2 CCVB Valid */
bogdanm 0:9b334a45a8ff 237 #define _TIMER_STATUS_CCVBV2_SHIFT 10 /**< Shift value for TIMER_CCVBV2 */
bogdanm 0:9b334a45a8ff 238 #define _TIMER_STATUS_CCVBV2_MASK 0x400UL /**< Bit mask for TIMER_CCVBV2 */
bogdanm 0:9b334a45a8ff 239 #define _TIMER_STATUS_CCVBV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */
bogdanm 0:9b334a45a8ff 240 #define TIMER_STATUS_CCVBV2_DEFAULT (_TIMER_STATUS_CCVBV2_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_STATUS */
bogdanm 0:9b334a45a8ff 241 #define TIMER_STATUS_ICV0 (0x1UL << 16) /**< CC0 Input Capture Valid */
bogdanm 0:9b334a45a8ff 242 #define _TIMER_STATUS_ICV0_SHIFT 16 /**< Shift value for TIMER_ICV0 */
bogdanm 0:9b334a45a8ff 243 #define _TIMER_STATUS_ICV0_MASK 0x10000UL /**< Bit mask for TIMER_ICV0 */
bogdanm 0:9b334a45a8ff 244 #define _TIMER_STATUS_ICV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */
bogdanm 0:9b334a45a8ff 245 #define TIMER_STATUS_ICV0_DEFAULT (_TIMER_STATUS_ICV0_DEFAULT << 16) /**< Shifted mode DEFAULT for TIMER_STATUS */
bogdanm 0:9b334a45a8ff 246 #define TIMER_STATUS_ICV1 (0x1UL << 17) /**< CC1 Input Capture Valid */
bogdanm 0:9b334a45a8ff 247 #define _TIMER_STATUS_ICV1_SHIFT 17 /**< Shift value for TIMER_ICV1 */
bogdanm 0:9b334a45a8ff 248 #define _TIMER_STATUS_ICV1_MASK 0x20000UL /**< Bit mask for TIMER_ICV1 */
bogdanm 0:9b334a45a8ff 249 #define _TIMER_STATUS_ICV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */
bogdanm 0:9b334a45a8ff 250 #define TIMER_STATUS_ICV1_DEFAULT (_TIMER_STATUS_ICV1_DEFAULT << 17) /**< Shifted mode DEFAULT for TIMER_STATUS */
bogdanm 0:9b334a45a8ff 251 #define TIMER_STATUS_ICV2 (0x1UL << 18) /**< CC2 Input Capture Valid */
bogdanm 0:9b334a45a8ff 252 #define _TIMER_STATUS_ICV2_SHIFT 18 /**< Shift value for TIMER_ICV2 */
bogdanm 0:9b334a45a8ff 253 #define _TIMER_STATUS_ICV2_MASK 0x40000UL /**< Bit mask for TIMER_ICV2 */
bogdanm 0:9b334a45a8ff 254 #define _TIMER_STATUS_ICV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */
bogdanm 0:9b334a45a8ff 255 #define TIMER_STATUS_ICV2_DEFAULT (_TIMER_STATUS_ICV2_DEFAULT << 18) /**< Shifted mode DEFAULT for TIMER_STATUS */
bogdanm 0:9b334a45a8ff 256 #define TIMER_STATUS_CCPOL0 (0x1UL << 24) /**< CC0 Polarity */
bogdanm 0:9b334a45a8ff 257 #define _TIMER_STATUS_CCPOL0_SHIFT 24 /**< Shift value for TIMER_CCPOL0 */
bogdanm 0:9b334a45a8ff 258 #define _TIMER_STATUS_CCPOL0_MASK 0x1000000UL /**< Bit mask for TIMER_CCPOL0 */
bogdanm 0:9b334a45a8ff 259 #define _TIMER_STATUS_CCPOL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */
bogdanm 0:9b334a45a8ff 260 #define _TIMER_STATUS_CCPOL0_LOWRISE 0x00000000UL /**< Mode LOWRISE for TIMER_STATUS */
bogdanm 0:9b334a45a8ff 261 #define _TIMER_STATUS_CCPOL0_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for TIMER_STATUS */
bogdanm 0:9b334a45a8ff 262 #define TIMER_STATUS_CCPOL0_DEFAULT (_TIMER_STATUS_CCPOL0_DEFAULT << 24) /**< Shifted mode DEFAULT for TIMER_STATUS */
bogdanm 0:9b334a45a8ff 263 #define TIMER_STATUS_CCPOL0_LOWRISE (_TIMER_STATUS_CCPOL0_LOWRISE << 24) /**< Shifted mode LOWRISE for TIMER_STATUS */
bogdanm 0:9b334a45a8ff 264 #define TIMER_STATUS_CCPOL0_HIGHFALL (_TIMER_STATUS_CCPOL0_HIGHFALL << 24) /**< Shifted mode HIGHFALL for TIMER_STATUS */
bogdanm 0:9b334a45a8ff 265 #define TIMER_STATUS_CCPOL1 (0x1UL << 25) /**< CC1 Polarity */
bogdanm 0:9b334a45a8ff 266 #define _TIMER_STATUS_CCPOL1_SHIFT 25 /**< Shift value for TIMER_CCPOL1 */
bogdanm 0:9b334a45a8ff 267 #define _TIMER_STATUS_CCPOL1_MASK 0x2000000UL /**< Bit mask for TIMER_CCPOL1 */
bogdanm 0:9b334a45a8ff 268 #define _TIMER_STATUS_CCPOL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */
bogdanm 0:9b334a45a8ff 269 #define _TIMER_STATUS_CCPOL1_LOWRISE 0x00000000UL /**< Mode LOWRISE for TIMER_STATUS */
bogdanm 0:9b334a45a8ff 270 #define _TIMER_STATUS_CCPOL1_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for TIMER_STATUS */
bogdanm 0:9b334a45a8ff 271 #define TIMER_STATUS_CCPOL1_DEFAULT (_TIMER_STATUS_CCPOL1_DEFAULT << 25) /**< Shifted mode DEFAULT for TIMER_STATUS */
bogdanm 0:9b334a45a8ff 272 #define TIMER_STATUS_CCPOL1_LOWRISE (_TIMER_STATUS_CCPOL1_LOWRISE << 25) /**< Shifted mode LOWRISE for TIMER_STATUS */
bogdanm 0:9b334a45a8ff 273 #define TIMER_STATUS_CCPOL1_HIGHFALL (_TIMER_STATUS_CCPOL1_HIGHFALL << 25) /**< Shifted mode HIGHFALL for TIMER_STATUS */
bogdanm 0:9b334a45a8ff 274 #define TIMER_STATUS_CCPOL2 (0x1UL << 26) /**< CC2 Polarity */
bogdanm 0:9b334a45a8ff 275 #define _TIMER_STATUS_CCPOL2_SHIFT 26 /**< Shift value for TIMER_CCPOL2 */
bogdanm 0:9b334a45a8ff 276 #define _TIMER_STATUS_CCPOL2_MASK 0x4000000UL /**< Bit mask for TIMER_CCPOL2 */
bogdanm 0:9b334a45a8ff 277 #define _TIMER_STATUS_CCPOL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */
bogdanm 0:9b334a45a8ff 278 #define _TIMER_STATUS_CCPOL2_LOWRISE 0x00000000UL /**< Mode LOWRISE for TIMER_STATUS */
bogdanm 0:9b334a45a8ff 279 #define _TIMER_STATUS_CCPOL2_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for TIMER_STATUS */
bogdanm 0:9b334a45a8ff 280 #define TIMER_STATUS_CCPOL2_DEFAULT (_TIMER_STATUS_CCPOL2_DEFAULT << 26) /**< Shifted mode DEFAULT for TIMER_STATUS */
bogdanm 0:9b334a45a8ff 281 #define TIMER_STATUS_CCPOL2_LOWRISE (_TIMER_STATUS_CCPOL2_LOWRISE << 26) /**< Shifted mode LOWRISE for TIMER_STATUS */
bogdanm 0:9b334a45a8ff 282 #define TIMER_STATUS_CCPOL2_HIGHFALL (_TIMER_STATUS_CCPOL2_HIGHFALL << 26) /**< Shifted mode HIGHFALL for TIMER_STATUS */
bogdanm 0:9b334a45a8ff 283
bogdanm 0:9b334a45a8ff 284 /* Bit fields for TIMER IEN */
bogdanm 0:9b334a45a8ff 285 #define _TIMER_IEN_RESETVALUE 0x00000000UL /**< Default value for TIMER_IEN */
bogdanm 0:9b334a45a8ff 286 #define _TIMER_IEN_MASK 0x00000773UL /**< Mask for TIMER_IEN */
bogdanm 0:9b334a45a8ff 287 #define TIMER_IEN_OF (0x1UL << 0) /**< Overflow Interrupt Enable */
bogdanm 0:9b334a45a8ff 288 #define _TIMER_IEN_OF_SHIFT 0 /**< Shift value for TIMER_OF */
bogdanm 0:9b334a45a8ff 289 #define _TIMER_IEN_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */
bogdanm 0:9b334a45a8ff 290 #define _TIMER_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */
bogdanm 0:9b334a45a8ff 291 #define TIMER_IEN_OF_DEFAULT (_TIMER_IEN_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_IEN */
bogdanm 0:9b334a45a8ff 292 #define TIMER_IEN_UF (0x1UL << 1) /**< Underflow Interrupt Enable */
bogdanm 0:9b334a45a8ff 293 #define _TIMER_IEN_UF_SHIFT 1 /**< Shift value for TIMER_UF */
bogdanm 0:9b334a45a8ff 294 #define _TIMER_IEN_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */
bogdanm 0:9b334a45a8ff 295 #define _TIMER_IEN_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */
bogdanm 0:9b334a45a8ff 296 #define TIMER_IEN_UF_DEFAULT (_TIMER_IEN_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_IEN */
bogdanm 0:9b334a45a8ff 297 #define TIMER_IEN_CC0 (0x1UL << 4) /**< CC Channel 0 Interrupt Enable */
bogdanm 0:9b334a45a8ff 298 #define _TIMER_IEN_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */
bogdanm 0:9b334a45a8ff 299 #define _TIMER_IEN_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */
bogdanm 0:9b334a45a8ff 300 #define _TIMER_IEN_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */
bogdanm 0:9b334a45a8ff 301 #define TIMER_IEN_CC0_DEFAULT (_TIMER_IEN_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_IEN */
bogdanm 0:9b334a45a8ff 302 #define TIMER_IEN_CC1 (0x1UL << 5) /**< CC Channel 1 Interrupt Enable */
bogdanm 0:9b334a45a8ff 303 #define _TIMER_IEN_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */
bogdanm 0:9b334a45a8ff 304 #define _TIMER_IEN_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */
bogdanm 0:9b334a45a8ff 305 #define _TIMER_IEN_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */
bogdanm 0:9b334a45a8ff 306 #define TIMER_IEN_CC1_DEFAULT (_TIMER_IEN_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for TIMER_IEN */
bogdanm 0:9b334a45a8ff 307 #define TIMER_IEN_CC2 (0x1UL << 6) /**< CC Channel 2 Interrupt Enable */
bogdanm 0:9b334a45a8ff 308 #define _TIMER_IEN_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */
bogdanm 0:9b334a45a8ff 309 #define _TIMER_IEN_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */
bogdanm 0:9b334a45a8ff 310 #define _TIMER_IEN_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */
bogdanm 0:9b334a45a8ff 311 #define TIMER_IEN_CC2_DEFAULT (_TIMER_IEN_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for TIMER_IEN */
bogdanm 0:9b334a45a8ff 312 #define TIMER_IEN_ICBOF0 (0x1UL << 8) /**< CC Channel 0 Input Capture Buffer Overflow Interrupt Enable */
bogdanm 0:9b334a45a8ff 313 #define _TIMER_IEN_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */
bogdanm 0:9b334a45a8ff 314 #define _TIMER_IEN_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */
bogdanm 0:9b334a45a8ff 315 #define _TIMER_IEN_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */
bogdanm 0:9b334a45a8ff 316 #define TIMER_IEN_ICBOF0_DEFAULT (_TIMER_IEN_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_IEN */
bogdanm 0:9b334a45a8ff 317 #define TIMER_IEN_ICBOF1 (0x1UL << 9) /**< CC Channel 1 Input Capture Buffer Overflow Interrupt Enable */
bogdanm 0:9b334a45a8ff 318 #define _TIMER_IEN_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */
bogdanm 0:9b334a45a8ff 319 #define _TIMER_IEN_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */
bogdanm 0:9b334a45a8ff 320 #define _TIMER_IEN_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */
bogdanm 0:9b334a45a8ff 321 #define TIMER_IEN_ICBOF1_DEFAULT (_TIMER_IEN_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for TIMER_IEN */
bogdanm 0:9b334a45a8ff 322 #define TIMER_IEN_ICBOF2 (0x1UL << 10) /**< CC Channel 2 Input Capture Buffer Overflow Interrupt Enable */
bogdanm 0:9b334a45a8ff 323 #define _TIMER_IEN_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */
bogdanm 0:9b334a45a8ff 324 #define _TIMER_IEN_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */
bogdanm 0:9b334a45a8ff 325 #define _TIMER_IEN_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */
bogdanm 0:9b334a45a8ff 326 #define TIMER_IEN_ICBOF2_DEFAULT (_TIMER_IEN_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_IEN */
bogdanm 0:9b334a45a8ff 327
bogdanm 0:9b334a45a8ff 328 /* Bit fields for TIMER IF */
bogdanm 0:9b334a45a8ff 329 #define _TIMER_IF_RESETVALUE 0x00000000UL /**< Default value for TIMER_IF */
bogdanm 0:9b334a45a8ff 330 #define _TIMER_IF_MASK 0x00000773UL /**< Mask for TIMER_IF */
bogdanm 0:9b334a45a8ff 331 #define TIMER_IF_OF (0x1UL << 0) /**< Overflow Interrupt Flag */
bogdanm 0:9b334a45a8ff 332 #define _TIMER_IF_OF_SHIFT 0 /**< Shift value for TIMER_OF */
bogdanm 0:9b334a45a8ff 333 #define _TIMER_IF_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */
bogdanm 0:9b334a45a8ff 334 #define _TIMER_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */
bogdanm 0:9b334a45a8ff 335 #define TIMER_IF_OF_DEFAULT (_TIMER_IF_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_IF */
bogdanm 0:9b334a45a8ff 336 #define TIMER_IF_UF (0x1UL << 1) /**< Underflow Interrupt Flag */
bogdanm 0:9b334a45a8ff 337 #define _TIMER_IF_UF_SHIFT 1 /**< Shift value for TIMER_UF */
bogdanm 0:9b334a45a8ff 338 #define _TIMER_IF_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */
bogdanm 0:9b334a45a8ff 339 #define _TIMER_IF_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */
bogdanm 0:9b334a45a8ff 340 #define TIMER_IF_UF_DEFAULT (_TIMER_IF_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_IF */
bogdanm 0:9b334a45a8ff 341 #define TIMER_IF_CC0 (0x1UL << 4) /**< CC Channel 0 Interrupt Flag */
bogdanm 0:9b334a45a8ff 342 #define _TIMER_IF_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */
bogdanm 0:9b334a45a8ff 343 #define _TIMER_IF_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */
bogdanm 0:9b334a45a8ff 344 #define _TIMER_IF_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */
bogdanm 0:9b334a45a8ff 345 #define TIMER_IF_CC0_DEFAULT (_TIMER_IF_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_IF */
bogdanm 0:9b334a45a8ff 346 #define TIMER_IF_CC1 (0x1UL << 5) /**< CC Channel 1 Interrupt Flag */
bogdanm 0:9b334a45a8ff 347 #define _TIMER_IF_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */
bogdanm 0:9b334a45a8ff 348 #define _TIMER_IF_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */
bogdanm 0:9b334a45a8ff 349 #define _TIMER_IF_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */
bogdanm 0:9b334a45a8ff 350 #define TIMER_IF_CC1_DEFAULT (_TIMER_IF_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for TIMER_IF */
bogdanm 0:9b334a45a8ff 351 #define TIMER_IF_CC2 (0x1UL << 6) /**< CC Channel 2 Interrupt Flag */
bogdanm 0:9b334a45a8ff 352 #define _TIMER_IF_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */
bogdanm 0:9b334a45a8ff 353 #define _TIMER_IF_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */
bogdanm 0:9b334a45a8ff 354 #define _TIMER_IF_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */
bogdanm 0:9b334a45a8ff 355 #define TIMER_IF_CC2_DEFAULT (_TIMER_IF_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for TIMER_IF */
bogdanm 0:9b334a45a8ff 356 #define TIMER_IF_ICBOF0 (0x1UL << 8) /**< CC Channel 0 Input Capture Buffer Overflow Interrupt Flag */
bogdanm 0:9b334a45a8ff 357 #define _TIMER_IF_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */
bogdanm 0:9b334a45a8ff 358 #define _TIMER_IF_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */
bogdanm 0:9b334a45a8ff 359 #define _TIMER_IF_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */
bogdanm 0:9b334a45a8ff 360 #define TIMER_IF_ICBOF0_DEFAULT (_TIMER_IF_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_IF */
bogdanm 0:9b334a45a8ff 361 #define TIMER_IF_ICBOF1 (0x1UL << 9) /**< CC Channel 1 Input Capture Buffer Overflow Interrupt Flag */
bogdanm 0:9b334a45a8ff 362 #define _TIMER_IF_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */
bogdanm 0:9b334a45a8ff 363 #define _TIMER_IF_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */
bogdanm 0:9b334a45a8ff 364 #define _TIMER_IF_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */
bogdanm 0:9b334a45a8ff 365 #define TIMER_IF_ICBOF1_DEFAULT (_TIMER_IF_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for TIMER_IF */
bogdanm 0:9b334a45a8ff 366 #define TIMER_IF_ICBOF2 (0x1UL << 10) /**< CC Channel 2 Input Capture Buffer Overflow Interrupt Flag */
bogdanm 0:9b334a45a8ff 367 #define _TIMER_IF_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */
bogdanm 0:9b334a45a8ff 368 #define _TIMER_IF_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */
bogdanm 0:9b334a45a8ff 369 #define _TIMER_IF_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */
bogdanm 0:9b334a45a8ff 370 #define TIMER_IF_ICBOF2_DEFAULT (_TIMER_IF_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_IF */
bogdanm 0:9b334a45a8ff 371
bogdanm 0:9b334a45a8ff 372 /* Bit fields for TIMER IFS */
bogdanm 0:9b334a45a8ff 373 #define _TIMER_IFS_RESETVALUE 0x00000000UL /**< Default value for TIMER_IFS */
bogdanm 0:9b334a45a8ff 374 #define _TIMER_IFS_MASK 0x00000773UL /**< Mask for TIMER_IFS */
bogdanm 0:9b334a45a8ff 375 #define TIMER_IFS_OF (0x1UL << 0) /**< Overflow Interrupt Flag Set */
bogdanm 0:9b334a45a8ff 376 #define _TIMER_IFS_OF_SHIFT 0 /**< Shift value for TIMER_OF */
bogdanm 0:9b334a45a8ff 377 #define _TIMER_IFS_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */
bogdanm 0:9b334a45a8ff 378 #define _TIMER_IFS_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFS */
bogdanm 0:9b334a45a8ff 379 #define TIMER_IFS_OF_DEFAULT (_TIMER_IFS_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_IFS */
bogdanm 0:9b334a45a8ff 380 #define TIMER_IFS_UF (0x1UL << 1) /**< Underflow Interrupt Flag Set */
bogdanm 0:9b334a45a8ff 381 #define _TIMER_IFS_UF_SHIFT 1 /**< Shift value for TIMER_UF */
bogdanm 0:9b334a45a8ff 382 #define _TIMER_IFS_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */
bogdanm 0:9b334a45a8ff 383 #define _TIMER_IFS_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFS */
bogdanm 0:9b334a45a8ff 384 #define TIMER_IFS_UF_DEFAULT (_TIMER_IFS_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_IFS */
bogdanm 0:9b334a45a8ff 385 #define TIMER_IFS_CC0 (0x1UL << 4) /**< CC Channel 0 Interrupt Flag Set */
bogdanm 0:9b334a45a8ff 386 #define _TIMER_IFS_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */
bogdanm 0:9b334a45a8ff 387 #define _TIMER_IFS_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */
bogdanm 0:9b334a45a8ff 388 #define _TIMER_IFS_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFS */
bogdanm 0:9b334a45a8ff 389 #define TIMER_IFS_CC0_DEFAULT (_TIMER_IFS_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_IFS */
bogdanm 0:9b334a45a8ff 390 #define TIMER_IFS_CC1 (0x1UL << 5) /**< CC Channel 1 Interrupt Flag Set */
bogdanm 0:9b334a45a8ff 391 #define _TIMER_IFS_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */
bogdanm 0:9b334a45a8ff 392 #define _TIMER_IFS_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */
bogdanm 0:9b334a45a8ff 393 #define _TIMER_IFS_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFS */
bogdanm 0:9b334a45a8ff 394 #define TIMER_IFS_CC1_DEFAULT (_TIMER_IFS_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for TIMER_IFS */
bogdanm 0:9b334a45a8ff 395 #define TIMER_IFS_CC2 (0x1UL << 6) /**< CC Channel 2 Interrupt Flag Set */
bogdanm 0:9b334a45a8ff 396 #define _TIMER_IFS_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */
bogdanm 0:9b334a45a8ff 397 #define _TIMER_IFS_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */
bogdanm 0:9b334a45a8ff 398 #define _TIMER_IFS_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFS */
bogdanm 0:9b334a45a8ff 399 #define TIMER_IFS_CC2_DEFAULT (_TIMER_IFS_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for TIMER_IFS */
bogdanm 0:9b334a45a8ff 400 #define TIMER_IFS_ICBOF0 (0x1UL << 8) /**< CC Channel 0 Input Capture Buffer Overflow Interrupt Flag Set */
bogdanm 0:9b334a45a8ff 401 #define _TIMER_IFS_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */
bogdanm 0:9b334a45a8ff 402 #define _TIMER_IFS_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */
bogdanm 0:9b334a45a8ff 403 #define _TIMER_IFS_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFS */
bogdanm 0:9b334a45a8ff 404 #define TIMER_IFS_ICBOF0_DEFAULT (_TIMER_IFS_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_IFS */
bogdanm 0:9b334a45a8ff 405 #define TIMER_IFS_ICBOF1 (0x1UL << 9) /**< CC Channel 1 Input Capture Buffer Overflow Interrupt Flag Set */
bogdanm 0:9b334a45a8ff 406 #define _TIMER_IFS_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */
bogdanm 0:9b334a45a8ff 407 #define _TIMER_IFS_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */
bogdanm 0:9b334a45a8ff 408 #define _TIMER_IFS_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFS */
bogdanm 0:9b334a45a8ff 409 #define TIMER_IFS_ICBOF1_DEFAULT (_TIMER_IFS_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for TIMER_IFS */
bogdanm 0:9b334a45a8ff 410 #define TIMER_IFS_ICBOF2 (0x1UL << 10) /**< CC Channel 2 Input Capture Buffer Overflow Interrupt Flag Set */
bogdanm 0:9b334a45a8ff 411 #define _TIMER_IFS_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */
bogdanm 0:9b334a45a8ff 412 #define _TIMER_IFS_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */
bogdanm 0:9b334a45a8ff 413 #define _TIMER_IFS_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFS */
bogdanm 0:9b334a45a8ff 414 #define TIMER_IFS_ICBOF2_DEFAULT (_TIMER_IFS_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_IFS */
bogdanm 0:9b334a45a8ff 415
bogdanm 0:9b334a45a8ff 416 /* Bit fields for TIMER IFC */
bogdanm 0:9b334a45a8ff 417 #define _TIMER_IFC_RESETVALUE 0x00000000UL /**< Default value for TIMER_IFC */
bogdanm 0:9b334a45a8ff 418 #define _TIMER_IFC_MASK 0x00000773UL /**< Mask for TIMER_IFC */
bogdanm 0:9b334a45a8ff 419 #define TIMER_IFC_OF (0x1UL << 0) /**< Overflow Interrupt Flag Clear */
bogdanm 0:9b334a45a8ff 420 #define _TIMER_IFC_OF_SHIFT 0 /**< Shift value for TIMER_OF */
bogdanm 0:9b334a45a8ff 421 #define _TIMER_IFC_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */
bogdanm 0:9b334a45a8ff 422 #define _TIMER_IFC_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFC */
bogdanm 0:9b334a45a8ff 423 #define TIMER_IFC_OF_DEFAULT (_TIMER_IFC_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_IFC */
bogdanm 0:9b334a45a8ff 424 #define TIMER_IFC_UF (0x1UL << 1) /**< Underflow Interrupt Flag Clear */
bogdanm 0:9b334a45a8ff 425 #define _TIMER_IFC_UF_SHIFT 1 /**< Shift value for TIMER_UF */
bogdanm 0:9b334a45a8ff 426 #define _TIMER_IFC_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */
bogdanm 0:9b334a45a8ff 427 #define _TIMER_IFC_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFC */
bogdanm 0:9b334a45a8ff 428 #define TIMER_IFC_UF_DEFAULT (_TIMER_IFC_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_IFC */
bogdanm 0:9b334a45a8ff 429 #define TIMER_IFC_CC0 (0x1UL << 4) /**< CC Channel 0 Interrupt Flag Clear */
bogdanm 0:9b334a45a8ff 430 #define _TIMER_IFC_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */
bogdanm 0:9b334a45a8ff 431 #define _TIMER_IFC_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */
bogdanm 0:9b334a45a8ff 432 #define _TIMER_IFC_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFC */
bogdanm 0:9b334a45a8ff 433 #define TIMER_IFC_CC0_DEFAULT (_TIMER_IFC_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_IFC */
bogdanm 0:9b334a45a8ff 434 #define TIMER_IFC_CC1 (0x1UL << 5) /**< CC Channel 1 Interrupt Flag Clear */
bogdanm 0:9b334a45a8ff 435 #define _TIMER_IFC_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */
bogdanm 0:9b334a45a8ff 436 #define _TIMER_IFC_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */
bogdanm 0:9b334a45a8ff 437 #define _TIMER_IFC_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFC */
bogdanm 0:9b334a45a8ff 438 #define TIMER_IFC_CC1_DEFAULT (_TIMER_IFC_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for TIMER_IFC */
bogdanm 0:9b334a45a8ff 439 #define TIMER_IFC_CC2 (0x1UL << 6) /**< CC Channel 2 Interrupt Flag Clear */
bogdanm 0:9b334a45a8ff 440 #define _TIMER_IFC_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */
bogdanm 0:9b334a45a8ff 441 #define _TIMER_IFC_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */
bogdanm 0:9b334a45a8ff 442 #define _TIMER_IFC_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFC */
bogdanm 0:9b334a45a8ff 443 #define TIMER_IFC_CC2_DEFAULT (_TIMER_IFC_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for TIMER_IFC */
bogdanm 0:9b334a45a8ff 444 #define TIMER_IFC_ICBOF0 (0x1UL << 8) /**< CC Channel 0 Input Capture Buffer Overflow Interrupt Flag Clear */
bogdanm 0:9b334a45a8ff 445 #define _TIMER_IFC_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */
bogdanm 0:9b334a45a8ff 446 #define _TIMER_IFC_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */
bogdanm 0:9b334a45a8ff 447 #define _TIMER_IFC_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFC */
bogdanm 0:9b334a45a8ff 448 #define TIMER_IFC_ICBOF0_DEFAULT (_TIMER_IFC_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_IFC */
bogdanm 0:9b334a45a8ff 449 #define TIMER_IFC_ICBOF1 (0x1UL << 9) /**< CC Channel 1 Input Capture Buffer Overflow Interrupt Flag Clear */
bogdanm 0:9b334a45a8ff 450 #define _TIMER_IFC_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */
bogdanm 0:9b334a45a8ff 451 #define _TIMER_IFC_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */
bogdanm 0:9b334a45a8ff 452 #define _TIMER_IFC_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFC */
bogdanm 0:9b334a45a8ff 453 #define TIMER_IFC_ICBOF1_DEFAULT (_TIMER_IFC_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for TIMER_IFC */
bogdanm 0:9b334a45a8ff 454 #define TIMER_IFC_ICBOF2 (0x1UL << 10) /**< CC Channel 2 Input Capture Buffer Overflow Interrupt Flag Clear */
bogdanm 0:9b334a45a8ff 455 #define _TIMER_IFC_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */
bogdanm 0:9b334a45a8ff 456 #define _TIMER_IFC_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */
bogdanm 0:9b334a45a8ff 457 #define _TIMER_IFC_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFC */
bogdanm 0:9b334a45a8ff 458 #define TIMER_IFC_ICBOF2_DEFAULT (_TIMER_IFC_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_IFC */
bogdanm 0:9b334a45a8ff 459
bogdanm 0:9b334a45a8ff 460 /* Bit fields for TIMER TOP */
bogdanm 0:9b334a45a8ff 461 #define _TIMER_TOP_RESETVALUE 0x0000FFFFUL /**< Default value for TIMER_TOP */
bogdanm 0:9b334a45a8ff 462 #define _TIMER_TOP_MASK 0x0000FFFFUL /**< Mask for TIMER_TOP */
bogdanm 0:9b334a45a8ff 463 #define _TIMER_TOP_TOP_SHIFT 0 /**< Shift value for TIMER_TOP */
bogdanm 0:9b334a45a8ff 464 #define _TIMER_TOP_TOP_MASK 0xFFFFUL /**< Bit mask for TIMER_TOP */
bogdanm 0:9b334a45a8ff 465 #define _TIMER_TOP_TOP_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for TIMER_TOP */
bogdanm 0:9b334a45a8ff 466 #define TIMER_TOP_TOP_DEFAULT (_TIMER_TOP_TOP_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_TOP */
bogdanm 0:9b334a45a8ff 467
bogdanm 0:9b334a45a8ff 468 /* Bit fields for TIMER TOPB */
bogdanm 0:9b334a45a8ff 469 #define _TIMER_TOPB_RESETVALUE 0x00000000UL /**< Default value for TIMER_TOPB */
bogdanm 0:9b334a45a8ff 470 #define _TIMER_TOPB_MASK 0x0000FFFFUL /**< Mask for TIMER_TOPB */
bogdanm 0:9b334a45a8ff 471 #define _TIMER_TOPB_TOPB_SHIFT 0 /**< Shift value for TIMER_TOPB */
bogdanm 0:9b334a45a8ff 472 #define _TIMER_TOPB_TOPB_MASK 0xFFFFUL /**< Bit mask for TIMER_TOPB */
bogdanm 0:9b334a45a8ff 473 #define _TIMER_TOPB_TOPB_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_TOPB */
bogdanm 0:9b334a45a8ff 474 #define TIMER_TOPB_TOPB_DEFAULT (_TIMER_TOPB_TOPB_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_TOPB */
bogdanm 0:9b334a45a8ff 475
bogdanm 0:9b334a45a8ff 476 /* Bit fields for TIMER CNT */
bogdanm 0:9b334a45a8ff 477 #define _TIMER_CNT_RESETVALUE 0x00000000UL /**< Default value for TIMER_CNT */
bogdanm 0:9b334a45a8ff 478 #define _TIMER_CNT_MASK 0x0000FFFFUL /**< Mask for TIMER_CNT */
bogdanm 0:9b334a45a8ff 479 #define _TIMER_CNT_CNT_SHIFT 0 /**< Shift value for TIMER_CNT */
bogdanm 0:9b334a45a8ff 480 #define _TIMER_CNT_CNT_MASK 0xFFFFUL /**< Bit mask for TIMER_CNT */
bogdanm 0:9b334a45a8ff 481 #define _TIMER_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CNT */
bogdanm 0:9b334a45a8ff 482 #define TIMER_CNT_CNT_DEFAULT (_TIMER_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CNT */
bogdanm 0:9b334a45a8ff 483
bogdanm 0:9b334a45a8ff 484 /* Bit fields for TIMER ROUTE */
bogdanm 0:9b334a45a8ff 485 #define _TIMER_ROUTE_RESETVALUE 0x00000000UL /**< Default value for TIMER_ROUTE */
bogdanm 0:9b334a45a8ff 486 #define _TIMER_ROUTE_MASK 0x00070707UL /**< Mask for TIMER_ROUTE */
bogdanm 0:9b334a45a8ff 487 #define TIMER_ROUTE_CC0PEN (0x1UL << 0) /**< CC Channel 0 Pin Enable */
bogdanm 0:9b334a45a8ff 488 #define _TIMER_ROUTE_CC0PEN_SHIFT 0 /**< Shift value for TIMER_CC0PEN */
bogdanm 0:9b334a45a8ff 489 #define _TIMER_ROUTE_CC0PEN_MASK 0x1UL /**< Bit mask for TIMER_CC0PEN */
bogdanm 0:9b334a45a8ff 490 #define _TIMER_ROUTE_CC0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_ROUTE */
bogdanm 0:9b334a45a8ff 491 #define TIMER_ROUTE_CC0PEN_DEFAULT (_TIMER_ROUTE_CC0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_ROUTE */
bogdanm 0:9b334a45a8ff 492 #define TIMER_ROUTE_CC1PEN (0x1UL << 1) /**< CC Channel 1 Pin Enable */
bogdanm 0:9b334a45a8ff 493 #define _TIMER_ROUTE_CC1PEN_SHIFT 1 /**< Shift value for TIMER_CC1PEN */
bogdanm 0:9b334a45a8ff 494 #define _TIMER_ROUTE_CC1PEN_MASK 0x2UL /**< Bit mask for TIMER_CC1PEN */
bogdanm 0:9b334a45a8ff 495 #define _TIMER_ROUTE_CC1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_ROUTE */
bogdanm 0:9b334a45a8ff 496 #define TIMER_ROUTE_CC1PEN_DEFAULT (_TIMER_ROUTE_CC1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_ROUTE */
bogdanm 0:9b334a45a8ff 497 #define TIMER_ROUTE_CC2PEN (0x1UL << 2) /**< CC Channel 2 Pin Enable */
bogdanm 0:9b334a45a8ff 498 #define _TIMER_ROUTE_CC2PEN_SHIFT 2 /**< Shift value for TIMER_CC2PEN */
bogdanm 0:9b334a45a8ff 499 #define _TIMER_ROUTE_CC2PEN_MASK 0x4UL /**< Bit mask for TIMER_CC2PEN */
bogdanm 0:9b334a45a8ff 500 #define _TIMER_ROUTE_CC2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_ROUTE */
bogdanm 0:9b334a45a8ff 501 #define TIMER_ROUTE_CC2PEN_DEFAULT (_TIMER_ROUTE_CC2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_ROUTE */
bogdanm 0:9b334a45a8ff 502 #define TIMER_ROUTE_CDTI0PEN (0x1UL << 8) /**< CC Channel 0 Complementary Dead-Time Insertion Pin Enable */
bogdanm 0:9b334a45a8ff 503 #define _TIMER_ROUTE_CDTI0PEN_SHIFT 8 /**< Shift value for TIMER_CDTI0PEN */
bogdanm 0:9b334a45a8ff 504 #define _TIMER_ROUTE_CDTI0PEN_MASK 0x100UL /**< Bit mask for TIMER_CDTI0PEN */
bogdanm 0:9b334a45a8ff 505 #define _TIMER_ROUTE_CDTI0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_ROUTE */
bogdanm 0:9b334a45a8ff 506 #define TIMER_ROUTE_CDTI0PEN_DEFAULT (_TIMER_ROUTE_CDTI0PEN_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_ROUTE */
bogdanm 0:9b334a45a8ff 507 #define TIMER_ROUTE_CDTI1PEN (0x1UL << 9) /**< CC Channel 1 Complementary Dead-Time Insertion Pin Enable */
bogdanm 0:9b334a45a8ff 508 #define _TIMER_ROUTE_CDTI1PEN_SHIFT 9 /**< Shift value for TIMER_CDTI1PEN */
bogdanm 0:9b334a45a8ff 509 #define _TIMER_ROUTE_CDTI1PEN_MASK 0x200UL /**< Bit mask for TIMER_CDTI1PEN */
bogdanm 0:9b334a45a8ff 510 #define _TIMER_ROUTE_CDTI1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_ROUTE */
bogdanm 0:9b334a45a8ff 511 #define TIMER_ROUTE_CDTI1PEN_DEFAULT (_TIMER_ROUTE_CDTI1PEN_DEFAULT << 9) /**< Shifted mode DEFAULT for TIMER_ROUTE */
bogdanm 0:9b334a45a8ff 512 #define TIMER_ROUTE_CDTI2PEN (0x1UL << 10) /**< CC Channel 2 Complementary Dead-Time Insertion Pin Enable */
bogdanm 0:9b334a45a8ff 513 #define _TIMER_ROUTE_CDTI2PEN_SHIFT 10 /**< Shift value for TIMER_CDTI2PEN */
bogdanm 0:9b334a45a8ff 514 #define _TIMER_ROUTE_CDTI2PEN_MASK 0x400UL /**< Bit mask for TIMER_CDTI2PEN */
bogdanm 0:9b334a45a8ff 515 #define _TIMER_ROUTE_CDTI2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_ROUTE */
bogdanm 0:9b334a45a8ff 516 #define TIMER_ROUTE_CDTI2PEN_DEFAULT (_TIMER_ROUTE_CDTI2PEN_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_ROUTE */
bogdanm 0:9b334a45a8ff 517 #define _TIMER_ROUTE_LOCATION_SHIFT 16 /**< Shift value for TIMER_LOCATION */
bogdanm 0:9b334a45a8ff 518 #define _TIMER_ROUTE_LOCATION_MASK 0x70000UL /**< Bit mask for TIMER_LOCATION */
bogdanm 0:9b334a45a8ff 519 #define _TIMER_ROUTE_LOCATION_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_ROUTE */
bogdanm 0:9b334a45a8ff 520 #define _TIMER_ROUTE_LOCATION_LOC0 0x00000000UL /**< Mode LOC0 for TIMER_ROUTE */
bogdanm 0:9b334a45a8ff 521 #define _TIMER_ROUTE_LOCATION_LOC1 0x00000001UL /**< Mode LOC1 for TIMER_ROUTE */
bogdanm 0:9b334a45a8ff 522 #define _TIMER_ROUTE_LOCATION_LOC2 0x00000002UL /**< Mode LOC2 for TIMER_ROUTE */
bogdanm 0:9b334a45a8ff 523 #define _TIMER_ROUTE_LOCATION_LOC3 0x00000003UL /**< Mode LOC3 for TIMER_ROUTE */
bogdanm 0:9b334a45a8ff 524 #define _TIMER_ROUTE_LOCATION_LOC4 0x00000004UL /**< Mode LOC4 for TIMER_ROUTE */
bogdanm 0:9b334a45a8ff 525 #define _TIMER_ROUTE_LOCATION_LOC5 0x00000005UL /**< Mode LOC5 for TIMER_ROUTE */
bogdanm 0:9b334a45a8ff 526 #define TIMER_ROUTE_LOCATION_DEFAULT (_TIMER_ROUTE_LOCATION_DEFAULT << 16) /**< Shifted mode DEFAULT for TIMER_ROUTE */
bogdanm 0:9b334a45a8ff 527 #define TIMER_ROUTE_LOCATION_LOC0 (_TIMER_ROUTE_LOCATION_LOC0 << 16) /**< Shifted mode LOC0 for TIMER_ROUTE */
bogdanm 0:9b334a45a8ff 528 #define TIMER_ROUTE_LOCATION_LOC1 (_TIMER_ROUTE_LOCATION_LOC1 << 16) /**< Shifted mode LOC1 for TIMER_ROUTE */
bogdanm 0:9b334a45a8ff 529 #define TIMER_ROUTE_LOCATION_LOC2 (_TIMER_ROUTE_LOCATION_LOC2 << 16) /**< Shifted mode LOC2 for TIMER_ROUTE */
bogdanm 0:9b334a45a8ff 530 #define TIMER_ROUTE_LOCATION_LOC3 (_TIMER_ROUTE_LOCATION_LOC3 << 16) /**< Shifted mode LOC3 for TIMER_ROUTE */
bogdanm 0:9b334a45a8ff 531 #define TIMER_ROUTE_LOCATION_LOC4 (_TIMER_ROUTE_LOCATION_LOC4 << 16) /**< Shifted mode LOC4 for TIMER_ROUTE */
bogdanm 0:9b334a45a8ff 532 #define TIMER_ROUTE_LOCATION_LOC5 (_TIMER_ROUTE_LOCATION_LOC5 << 16) /**< Shifted mode LOC5 for TIMER_ROUTE */
bogdanm 0:9b334a45a8ff 533
bogdanm 0:9b334a45a8ff 534 /* Bit fields for TIMER CC_CTRL */
bogdanm 0:9b334a45a8ff 535 #define _TIMER_CC_CTRL_RESETVALUE 0x00000000UL /**< Default value for TIMER_CC_CTRL */
bogdanm 0:9b334a45a8ff 536 #define _TIMER_CC_CTRL_MASK 0x0F3F3F17UL /**< Mask for TIMER_CC_CTRL */
bogdanm 0:9b334a45a8ff 537 #define _TIMER_CC_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */
bogdanm 0:9b334a45a8ff 538 #define _TIMER_CC_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */
bogdanm 0:9b334a45a8ff 539 #define _TIMER_CC_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */
bogdanm 0:9b334a45a8ff 540 #define _TIMER_CC_CTRL_MODE_OFF 0x00000000UL /**< Mode OFF for TIMER_CC_CTRL */
bogdanm 0:9b334a45a8ff 541 #define _TIMER_CC_CTRL_MODE_INPUTCAPTURE 0x00000001UL /**< Mode INPUTCAPTURE for TIMER_CC_CTRL */
bogdanm 0:9b334a45a8ff 542 #define _TIMER_CC_CTRL_MODE_OUTPUTCOMPARE 0x00000002UL /**< Mode OUTPUTCOMPARE for TIMER_CC_CTRL */
bogdanm 0:9b334a45a8ff 543 #define _TIMER_CC_CTRL_MODE_PWM 0x00000003UL /**< Mode PWM for TIMER_CC_CTRL */
bogdanm 0:9b334a45a8ff 544 #define TIMER_CC_CTRL_MODE_DEFAULT (_TIMER_CC_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */
bogdanm 0:9b334a45a8ff 545 #define TIMER_CC_CTRL_MODE_OFF (_TIMER_CC_CTRL_MODE_OFF << 0) /**< Shifted mode OFF for TIMER_CC_CTRL */
bogdanm 0:9b334a45a8ff 546 #define TIMER_CC_CTRL_MODE_INPUTCAPTURE (_TIMER_CC_CTRL_MODE_INPUTCAPTURE << 0) /**< Shifted mode INPUTCAPTURE for TIMER_CC_CTRL */
bogdanm 0:9b334a45a8ff 547 #define TIMER_CC_CTRL_MODE_OUTPUTCOMPARE (_TIMER_CC_CTRL_MODE_OUTPUTCOMPARE << 0) /**< Shifted mode OUTPUTCOMPARE for TIMER_CC_CTRL */
bogdanm 0:9b334a45a8ff 548 #define TIMER_CC_CTRL_MODE_PWM (_TIMER_CC_CTRL_MODE_PWM << 0) /**< Shifted mode PWM for TIMER_CC_CTRL */
bogdanm 0:9b334a45a8ff 549 #define TIMER_CC_CTRL_OUTINV (0x1UL << 2) /**< Output Invert */
bogdanm 0:9b334a45a8ff 550 #define _TIMER_CC_CTRL_OUTINV_SHIFT 2 /**< Shift value for TIMER_OUTINV */
bogdanm 0:9b334a45a8ff 551 #define _TIMER_CC_CTRL_OUTINV_MASK 0x4UL /**< Bit mask for TIMER_OUTINV */
bogdanm 0:9b334a45a8ff 552 #define _TIMER_CC_CTRL_OUTINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */
bogdanm 0:9b334a45a8ff 553 #define TIMER_CC_CTRL_OUTINV_DEFAULT (_TIMER_CC_CTRL_OUTINV_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */
bogdanm 0:9b334a45a8ff 554 #define TIMER_CC_CTRL_COIST (0x1UL << 4) /**< Compare Output Initial State */
bogdanm 0:9b334a45a8ff 555 #define _TIMER_CC_CTRL_COIST_SHIFT 4 /**< Shift value for TIMER_COIST */
bogdanm 0:9b334a45a8ff 556 #define _TIMER_CC_CTRL_COIST_MASK 0x10UL /**< Bit mask for TIMER_COIST */
bogdanm 0:9b334a45a8ff 557 #define _TIMER_CC_CTRL_COIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */
bogdanm 0:9b334a45a8ff 558 #define TIMER_CC_CTRL_COIST_DEFAULT (_TIMER_CC_CTRL_COIST_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */
bogdanm 0:9b334a45a8ff 559 #define _TIMER_CC_CTRL_CMOA_SHIFT 8 /**< Shift value for TIMER_CMOA */
bogdanm 0:9b334a45a8ff 560 #define _TIMER_CC_CTRL_CMOA_MASK 0x300UL /**< Bit mask for TIMER_CMOA */
bogdanm 0:9b334a45a8ff 561 #define _TIMER_CC_CTRL_CMOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */
bogdanm 0:9b334a45a8ff 562 #define _TIMER_CC_CTRL_CMOA_NONE 0x00000000UL /**< Mode NONE for TIMER_CC_CTRL */
bogdanm 0:9b334a45a8ff 563 #define _TIMER_CC_CTRL_CMOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for TIMER_CC_CTRL */
bogdanm 0:9b334a45a8ff 564 #define _TIMER_CC_CTRL_CMOA_CLEAR 0x00000002UL /**< Mode CLEAR for TIMER_CC_CTRL */
bogdanm 0:9b334a45a8ff 565 #define _TIMER_CC_CTRL_CMOA_SET 0x00000003UL /**< Mode SET for TIMER_CC_CTRL */
bogdanm 0:9b334a45a8ff 566 #define TIMER_CC_CTRL_CMOA_DEFAULT (_TIMER_CC_CTRL_CMOA_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */
bogdanm 0:9b334a45a8ff 567 #define TIMER_CC_CTRL_CMOA_NONE (_TIMER_CC_CTRL_CMOA_NONE << 8) /**< Shifted mode NONE for TIMER_CC_CTRL */
bogdanm 0:9b334a45a8ff 568 #define TIMER_CC_CTRL_CMOA_TOGGLE (_TIMER_CC_CTRL_CMOA_TOGGLE << 8) /**< Shifted mode TOGGLE for TIMER_CC_CTRL */
bogdanm 0:9b334a45a8ff 569 #define TIMER_CC_CTRL_CMOA_CLEAR (_TIMER_CC_CTRL_CMOA_CLEAR << 8) /**< Shifted mode CLEAR for TIMER_CC_CTRL */
bogdanm 0:9b334a45a8ff 570 #define TIMER_CC_CTRL_CMOA_SET (_TIMER_CC_CTRL_CMOA_SET << 8) /**< Shifted mode SET for TIMER_CC_CTRL */
bogdanm 0:9b334a45a8ff 571 #define _TIMER_CC_CTRL_COFOA_SHIFT 10 /**< Shift value for TIMER_COFOA */
bogdanm 0:9b334a45a8ff 572 #define _TIMER_CC_CTRL_COFOA_MASK 0xC00UL /**< Bit mask for TIMER_COFOA */
bogdanm 0:9b334a45a8ff 573 #define _TIMER_CC_CTRL_COFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */
bogdanm 0:9b334a45a8ff 574 #define _TIMER_CC_CTRL_COFOA_NONE 0x00000000UL /**< Mode NONE for TIMER_CC_CTRL */
bogdanm 0:9b334a45a8ff 575 #define _TIMER_CC_CTRL_COFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for TIMER_CC_CTRL */
bogdanm 0:9b334a45a8ff 576 #define _TIMER_CC_CTRL_COFOA_CLEAR 0x00000002UL /**< Mode CLEAR for TIMER_CC_CTRL */
bogdanm 0:9b334a45a8ff 577 #define _TIMER_CC_CTRL_COFOA_SET 0x00000003UL /**< Mode SET for TIMER_CC_CTRL */
bogdanm 0:9b334a45a8ff 578 #define TIMER_CC_CTRL_COFOA_DEFAULT (_TIMER_CC_CTRL_COFOA_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */
bogdanm 0:9b334a45a8ff 579 #define TIMER_CC_CTRL_COFOA_NONE (_TIMER_CC_CTRL_COFOA_NONE << 10) /**< Shifted mode NONE for TIMER_CC_CTRL */
bogdanm 0:9b334a45a8ff 580 #define TIMER_CC_CTRL_COFOA_TOGGLE (_TIMER_CC_CTRL_COFOA_TOGGLE << 10) /**< Shifted mode TOGGLE for TIMER_CC_CTRL */
bogdanm 0:9b334a45a8ff 581 #define TIMER_CC_CTRL_COFOA_CLEAR (_TIMER_CC_CTRL_COFOA_CLEAR << 10) /**< Shifted mode CLEAR for TIMER_CC_CTRL */
bogdanm 0:9b334a45a8ff 582 #define TIMER_CC_CTRL_COFOA_SET (_TIMER_CC_CTRL_COFOA_SET << 10) /**< Shifted mode SET for TIMER_CC_CTRL */
bogdanm 0:9b334a45a8ff 583 #define _TIMER_CC_CTRL_CUFOA_SHIFT 12 /**< Shift value for TIMER_CUFOA */
bogdanm 0:9b334a45a8ff 584 #define _TIMER_CC_CTRL_CUFOA_MASK 0x3000UL /**< Bit mask for TIMER_CUFOA */
bogdanm 0:9b334a45a8ff 585 #define _TIMER_CC_CTRL_CUFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */
bogdanm 0:9b334a45a8ff 586 #define _TIMER_CC_CTRL_CUFOA_NONE 0x00000000UL /**< Mode NONE for TIMER_CC_CTRL */
bogdanm 0:9b334a45a8ff 587 #define _TIMER_CC_CTRL_CUFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for TIMER_CC_CTRL */
bogdanm 0:9b334a45a8ff 588 #define _TIMER_CC_CTRL_CUFOA_CLEAR 0x00000002UL /**< Mode CLEAR for TIMER_CC_CTRL */
bogdanm 0:9b334a45a8ff 589 #define _TIMER_CC_CTRL_CUFOA_SET 0x00000003UL /**< Mode SET for TIMER_CC_CTRL */
bogdanm 0:9b334a45a8ff 590 #define TIMER_CC_CTRL_CUFOA_DEFAULT (_TIMER_CC_CTRL_CUFOA_DEFAULT << 12) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */
bogdanm 0:9b334a45a8ff 591 #define TIMER_CC_CTRL_CUFOA_NONE (_TIMER_CC_CTRL_CUFOA_NONE << 12) /**< Shifted mode NONE for TIMER_CC_CTRL */
bogdanm 0:9b334a45a8ff 592 #define TIMER_CC_CTRL_CUFOA_TOGGLE (_TIMER_CC_CTRL_CUFOA_TOGGLE << 12) /**< Shifted mode TOGGLE for TIMER_CC_CTRL */
bogdanm 0:9b334a45a8ff 593 #define TIMER_CC_CTRL_CUFOA_CLEAR (_TIMER_CC_CTRL_CUFOA_CLEAR << 12) /**< Shifted mode CLEAR for TIMER_CC_CTRL */
bogdanm 0:9b334a45a8ff 594 #define TIMER_CC_CTRL_CUFOA_SET (_TIMER_CC_CTRL_CUFOA_SET << 12) /**< Shifted mode SET for TIMER_CC_CTRL */
bogdanm 0:9b334a45a8ff 595 #define _TIMER_CC_CTRL_PRSSEL_SHIFT 16 /**< Shift value for TIMER_PRSSEL */
bogdanm 0:9b334a45a8ff 596 #define _TIMER_CC_CTRL_PRSSEL_MASK 0xF0000UL /**< Bit mask for TIMER_PRSSEL */
bogdanm 0:9b334a45a8ff 597 #define _TIMER_CC_CTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */
bogdanm 0:9b334a45a8ff 598 #define _TIMER_CC_CTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for TIMER_CC_CTRL */
bogdanm 0:9b334a45a8ff 599 #define _TIMER_CC_CTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for TIMER_CC_CTRL */
bogdanm 0:9b334a45a8ff 600 #define _TIMER_CC_CTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for TIMER_CC_CTRL */
bogdanm 0:9b334a45a8ff 601 #define _TIMER_CC_CTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for TIMER_CC_CTRL */
bogdanm 0:9b334a45a8ff 602 #define _TIMER_CC_CTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for TIMER_CC_CTRL */
bogdanm 0:9b334a45a8ff 603 #define _TIMER_CC_CTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for TIMER_CC_CTRL */
bogdanm 0:9b334a45a8ff 604 #define _TIMER_CC_CTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for TIMER_CC_CTRL */
bogdanm 0:9b334a45a8ff 605 #define _TIMER_CC_CTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for TIMER_CC_CTRL */
bogdanm 0:9b334a45a8ff 606 #define _TIMER_CC_CTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for TIMER_CC_CTRL */
bogdanm 0:9b334a45a8ff 607 #define _TIMER_CC_CTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for TIMER_CC_CTRL */
bogdanm 0:9b334a45a8ff 608 #define _TIMER_CC_CTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for TIMER_CC_CTRL */
bogdanm 0:9b334a45a8ff 609 #define _TIMER_CC_CTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for TIMER_CC_CTRL */
bogdanm 0:9b334a45a8ff 610 #define TIMER_CC_CTRL_PRSSEL_DEFAULT (_TIMER_CC_CTRL_PRSSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */
bogdanm 0:9b334a45a8ff 611 #define TIMER_CC_CTRL_PRSSEL_PRSCH0 (_TIMER_CC_CTRL_PRSSEL_PRSCH0 << 16) /**< Shifted mode PRSCH0 for TIMER_CC_CTRL */
bogdanm 0:9b334a45a8ff 612 #define TIMER_CC_CTRL_PRSSEL_PRSCH1 (_TIMER_CC_CTRL_PRSSEL_PRSCH1 << 16) /**< Shifted mode PRSCH1 for TIMER_CC_CTRL */
bogdanm 0:9b334a45a8ff 613 #define TIMER_CC_CTRL_PRSSEL_PRSCH2 (_TIMER_CC_CTRL_PRSSEL_PRSCH2 << 16) /**< Shifted mode PRSCH2 for TIMER_CC_CTRL */
bogdanm 0:9b334a45a8ff 614 #define TIMER_CC_CTRL_PRSSEL_PRSCH3 (_TIMER_CC_CTRL_PRSSEL_PRSCH3 << 16) /**< Shifted mode PRSCH3 for TIMER_CC_CTRL */
bogdanm 0:9b334a45a8ff 615 #define TIMER_CC_CTRL_PRSSEL_PRSCH4 (_TIMER_CC_CTRL_PRSSEL_PRSCH4 << 16) /**< Shifted mode PRSCH4 for TIMER_CC_CTRL */
bogdanm 0:9b334a45a8ff 616 #define TIMER_CC_CTRL_PRSSEL_PRSCH5 (_TIMER_CC_CTRL_PRSSEL_PRSCH5 << 16) /**< Shifted mode PRSCH5 for TIMER_CC_CTRL */
bogdanm 0:9b334a45a8ff 617 #define TIMER_CC_CTRL_PRSSEL_PRSCH6 (_TIMER_CC_CTRL_PRSSEL_PRSCH6 << 16) /**< Shifted mode PRSCH6 for TIMER_CC_CTRL */
bogdanm 0:9b334a45a8ff 618 #define TIMER_CC_CTRL_PRSSEL_PRSCH7 (_TIMER_CC_CTRL_PRSSEL_PRSCH7 << 16) /**< Shifted mode PRSCH7 for TIMER_CC_CTRL */
bogdanm 0:9b334a45a8ff 619 #define TIMER_CC_CTRL_PRSSEL_PRSCH8 (_TIMER_CC_CTRL_PRSSEL_PRSCH8 << 16) /**< Shifted mode PRSCH8 for TIMER_CC_CTRL */
bogdanm 0:9b334a45a8ff 620 #define TIMER_CC_CTRL_PRSSEL_PRSCH9 (_TIMER_CC_CTRL_PRSSEL_PRSCH9 << 16) /**< Shifted mode PRSCH9 for TIMER_CC_CTRL */
bogdanm 0:9b334a45a8ff 621 #define TIMER_CC_CTRL_PRSSEL_PRSCH10 (_TIMER_CC_CTRL_PRSSEL_PRSCH10 << 16) /**< Shifted mode PRSCH10 for TIMER_CC_CTRL */
bogdanm 0:9b334a45a8ff 622 #define TIMER_CC_CTRL_PRSSEL_PRSCH11 (_TIMER_CC_CTRL_PRSSEL_PRSCH11 << 16) /**< Shifted mode PRSCH11 for TIMER_CC_CTRL */
bogdanm 0:9b334a45a8ff 623 #define TIMER_CC_CTRL_INSEL (0x1UL << 20) /**< Input Selection */
bogdanm 0:9b334a45a8ff 624 #define _TIMER_CC_CTRL_INSEL_SHIFT 20 /**< Shift value for TIMER_INSEL */
bogdanm 0:9b334a45a8ff 625 #define _TIMER_CC_CTRL_INSEL_MASK 0x100000UL /**< Bit mask for TIMER_INSEL */
bogdanm 0:9b334a45a8ff 626 #define _TIMER_CC_CTRL_INSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */
bogdanm 0:9b334a45a8ff 627 #define _TIMER_CC_CTRL_INSEL_PIN 0x00000000UL /**< Mode PIN for TIMER_CC_CTRL */
bogdanm 0:9b334a45a8ff 628 #define _TIMER_CC_CTRL_INSEL_PRS 0x00000001UL /**< Mode PRS for TIMER_CC_CTRL */
bogdanm 0:9b334a45a8ff 629 #define TIMER_CC_CTRL_INSEL_DEFAULT (_TIMER_CC_CTRL_INSEL_DEFAULT << 20) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */
bogdanm 0:9b334a45a8ff 630 #define TIMER_CC_CTRL_INSEL_PIN (_TIMER_CC_CTRL_INSEL_PIN << 20) /**< Shifted mode PIN for TIMER_CC_CTRL */
bogdanm 0:9b334a45a8ff 631 #define TIMER_CC_CTRL_INSEL_PRS (_TIMER_CC_CTRL_INSEL_PRS << 20) /**< Shifted mode PRS for TIMER_CC_CTRL */
bogdanm 0:9b334a45a8ff 632 #define TIMER_CC_CTRL_FILT (0x1UL << 21) /**< Digital Filter */
bogdanm 0:9b334a45a8ff 633 #define _TIMER_CC_CTRL_FILT_SHIFT 21 /**< Shift value for TIMER_FILT */
bogdanm 0:9b334a45a8ff 634 #define _TIMER_CC_CTRL_FILT_MASK 0x200000UL /**< Bit mask for TIMER_FILT */
bogdanm 0:9b334a45a8ff 635 #define _TIMER_CC_CTRL_FILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */
bogdanm 0:9b334a45a8ff 636 #define _TIMER_CC_CTRL_FILT_DISABLE 0x00000000UL /**< Mode DISABLE for TIMER_CC_CTRL */
bogdanm 0:9b334a45a8ff 637 #define _TIMER_CC_CTRL_FILT_ENABLE 0x00000001UL /**< Mode ENABLE for TIMER_CC_CTRL */
bogdanm 0:9b334a45a8ff 638 #define TIMER_CC_CTRL_FILT_DEFAULT (_TIMER_CC_CTRL_FILT_DEFAULT << 21) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */
bogdanm 0:9b334a45a8ff 639 #define TIMER_CC_CTRL_FILT_DISABLE (_TIMER_CC_CTRL_FILT_DISABLE << 21) /**< Shifted mode DISABLE for TIMER_CC_CTRL */
bogdanm 0:9b334a45a8ff 640 #define TIMER_CC_CTRL_FILT_ENABLE (_TIMER_CC_CTRL_FILT_ENABLE << 21) /**< Shifted mode ENABLE for TIMER_CC_CTRL */
bogdanm 0:9b334a45a8ff 641 #define _TIMER_CC_CTRL_ICEDGE_SHIFT 24 /**< Shift value for TIMER_ICEDGE */
bogdanm 0:9b334a45a8ff 642 #define _TIMER_CC_CTRL_ICEDGE_MASK 0x3000000UL /**< Bit mask for TIMER_ICEDGE */
bogdanm 0:9b334a45a8ff 643 #define _TIMER_CC_CTRL_ICEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */
bogdanm 0:9b334a45a8ff 644 #define _TIMER_CC_CTRL_ICEDGE_RISING 0x00000000UL /**< Mode RISING for TIMER_CC_CTRL */
bogdanm 0:9b334a45a8ff 645 #define _TIMER_CC_CTRL_ICEDGE_FALLING 0x00000001UL /**< Mode FALLING for TIMER_CC_CTRL */
bogdanm 0:9b334a45a8ff 646 #define _TIMER_CC_CTRL_ICEDGE_BOTH 0x00000002UL /**< Mode BOTH for TIMER_CC_CTRL */
bogdanm 0:9b334a45a8ff 647 #define _TIMER_CC_CTRL_ICEDGE_NONE 0x00000003UL /**< Mode NONE for TIMER_CC_CTRL */
bogdanm 0:9b334a45a8ff 648 #define TIMER_CC_CTRL_ICEDGE_DEFAULT (_TIMER_CC_CTRL_ICEDGE_DEFAULT << 24) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */
bogdanm 0:9b334a45a8ff 649 #define TIMER_CC_CTRL_ICEDGE_RISING (_TIMER_CC_CTRL_ICEDGE_RISING << 24) /**< Shifted mode RISING for TIMER_CC_CTRL */
bogdanm 0:9b334a45a8ff 650 #define TIMER_CC_CTRL_ICEDGE_FALLING (_TIMER_CC_CTRL_ICEDGE_FALLING << 24) /**< Shifted mode FALLING for TIMER_CC_CTRL */
bogdanm 0:9b334a45a8ff 651 #define TIMER_CC_CTRL_ICEDGE_BOTH (_TIMER_CC_CTRL_ICEDGE_BOTH << 24) /**< Shifted mode BOTH for TIMER_CC_CTRL */
bogdanm 0:9b334a45a8ff 652 #define TIMER_CC_CTRL_ICEDGE_NONE (_TIMER_CC_CTRL_ICEDGE_NONE << 24) /**< Shifted mode NONE for TIMER_CC_CTRL */
bogdanm 0:9b334a45a8ff 653 #define _TIMER_CC_CTRL_ICEVCTRL_SHIFT 26 /**< Shift value for TIMER_ICEVCTRL */
bogdanm 0:9b334a45a8ff 654 #define _TIMER_CC_CTRL_ICEVCTRL_MASK 0xC000000UL /**< Bit mask for TIMER_ICEVCTRL */
bogdanm 0:9b334a45a8ff 655 #define _TIMER_CC_CTRL_ICEVCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */
bogdanm 0:9b334a45a8ff 656 #define _TIMER_CC_CTRL_ICEVCTRL_EVERYEDGE 0x00000000UL /**< Mode EVERYEDGE for TIMER_CC_CTRL */
bogdanm 0:9b334a45a8ff 657 #define _TIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE 0x00000001UL /**< Mode EVERYSECONDEDGE for TIMER_CC_CTRL */
bogdanm 0:9b334a45a8ff 658 #define _TIMER_CC_CTRL_ICEVCTRL_RISING 0x00000002UL /**< Mode RISING for TIMER_CC_CTRL */
bogdanm 0:9b334a45a8ff 659 #define _TIMER_CC_CTRL_ICEVCTRL_FALLING 0x00000003UL /**< Mode FALLING for TIMER_CC_CTRL */
bogdanm 0:9b334a45a8ff 660 #define TIMER_CC_CTRL_ICEVCTRL_DEFAULT (_TIMER_CC_CTRL_ICEVCTRL_DEFAULT << 26) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */
bogdanm 0:9b334a45a8ff 661 #define TIMER_CC_CTRL_ICEVCTRL_EVERYEDGE (_TIMER_CC_CTRL_ICEVCTRL_EVERYEDGE << 26) /**< Shifted mode EVERYEDGE for TIMER_CC_CTRL */
bogdanm 0:9b334a45a8ff 662 #define TIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE (_TIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE << 26) /**< Shifted mode EVERYSECONDEDGE for TIMER_CC_CTRL */
bogdanm 0:9b334a45a8ff 663 #define TIMER_CC_CTRL_ICEVCTRL_RISING (_TIMER_CC_CTRL_ICEVCTRL_RISING << 26) /**< Shifted mode RISING for TIMER_CC_CTRL */
bogdanm 0:9b334a45a8ff 664 #define TIMER_CC_CTRL_ICEVCTRL_FALLING (_TIMER_CC_CTRL_ICEVCTRL_FALLING << 26) /**< Shifted mode FALLING for TIMER_CC_CTRL */
bogdanm 0:9b334a45a8ff 665
bogdanm 0:9b334a45a8ff 666 /* Bit fields for TIMER CC_CCV */
bogdanm 0:9b334a45a8ff 667 #define _TIMER_CC_CCV_RESETVALUE 0x00000000UL /**< Default value for TIMER_CC_CCV */
bogdanm 0:9b334a45a8ff 668 #define _TIMER_CC_CCV_MASK 0x0000FFFFUL /**< Mask for TIMER_CC_CCV */
bogdanm 0:9b334a45a8ff 669 #define _TIMER_CC_CCV_CCV_SHIFT 0 /**< Shift value for TIMER_CCV */
bogdanm 0:9b334a45a8ff 670 #define _TIMER_CC_CCV_CCV_MASK 0xFFFFUL /**< Bit mask for TIMER_CCV */
bogdanm 0:9b334a45a8ff 671 #define _TIMER_CC_CCV_CCV_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CCV */
bogdanm 0:9b334a45a8ff 672 #define TIMER_CC_CCV_CCV_DEFAULT (_TIMER_CC_CCV_CCV_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CC_CCV */
bogdanm 0:9b334a45a8ff 673
bogdanm 0:9b334a45a8ff 674 /* Bit fields for TIMER CC_CCVP */
bogdanm 0:9b334a45a8ff 675 #define _TIMER_CC_CCVP_RESETVALUE 0x00000000UL /**< Default value for TIMER_CC_CCVP */
bogdanm 0:9b334a45a8ff 676 #define _TIMER_CC_CCVP_MASK 0x0000FFFFUL /**< Mask for TIMER_CC_CCVP */
bogdanm 0:9b334a45a8ff 677 #define _TIMER_CC_CCVP_CCVP_SHIFT 0 /**< Shift value for TIMER_CCVP */
bogdanm 0:9b334a45a8ff 678 #define _TIMER_CC_CCVP_CCVP_MASK 0xFFFFUL /**< Bit mask for TIMER_CCVP */
bogdanm 0:9b334a45a8ff 679 #define _TIMER_CC_CCVP_CCVP_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CCVP */
bogdanm 0:9b334a45a8ff 680 #define TIMER_CC_CCVP_CCVP_DEFAULT (_TIMER_CC_CCVP_CCVP_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CC_CCVP */
bogdanm 0:9b334a45a8ff 681
bogdanm 0:9b334a45a8ff 682 /* Bit fields for TIMER CC_CCVB */
bogdanm 0:9b334a45a8ff 683 #define _TIMER_CC_CCVB_RESETVALUE 0x00000000UL /**< Default value for TIMER_CC_CCVB */
bogdanm 0:9b334a45a8ff 684 #define _TIMER_CC_CCVB_MASK 0x0000FFFFUL /**< Mask for TIMER_CC_CCVB */
bogdanm 0:9b334a45a8ff 685 #define _TIMER_CC_CCVB_CCVB_SHIFT 0 /**< Shift value for TIMER_CCVB */
bogdanm 0:9b334a45a8ff 686 #define _TIMER_CC_CCVB_CCVB_MASK 0xFFFFUL /**< Bit mask for TIMER_CCVB */
bogdanm 0:9b334a45a8ff 687 #define _TIMER_CC_CCVB_CCVB_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CCVB */
bogdanm 0:9b334a45a8ff 688 #define TIMER_CC_CCVB_CCVB_DEFAULT (_TIMER_CC_CCVB_CCVB_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CC_CCVB */
bogdanm 0:9b334a45a8ff 689
bogdanm 0:9b334a45a8ff 690 /* Bit fields for TIMER DTCTRL */
bogdanm 0:9b334a45a8ff 691 #define _TIMER_DTCTRL_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTCTRL */
bogdanm 0:9b334a45a8ff 692 #define _TIMER_DTCTRL_MASK 0x010000FFUL /**< Mask for TIMER_DTCTRL */
bogdanm 0:9b334a45a8ff 693 #define TIMER_DTCTRL_DTEN (0x1UL << 0) /**< DTI Enable */
bogdanm 0:9b334a45a8ff 694 #define _TIMER_DTCTRL_DTEN_SHIFT 0 /**< Shift value for TIMER_DTEN */
bogdanm 0:9b334a45a8ff 695 #define _TIMER_DTCTRL_DTEN_MASK 0x1UL /**< Bit mask for TIMER_DTEN */
bogdanm 0:9b334a45a8ff 696 #define _TIMER_DTCTRL_DTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCTRL */
bogdanm 0:9b334a45a8ff 697 #define TIMER_DTCTRL_DTEN_DEFAULT (_TIMER_DTCTRL_DTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTCTRL */
bogdanm 0:9b334a45a8ff 698 #define TIMER_DTCTRL_DTDAS (0x1UL << 1) /**< DTI Automatic Start-up Functionality */
bogdanm 0:9b334a45a8ff 699 #define _TIMER_DTCTRL_DTDAS_SHIFT 1 /**< Shift value for TIMER_DTDAS */
bogdanm 0:9b334a45a8ff 700 #define _TIMER_DTCTRL_DTDAS_MASK 0x2UL /**< Bit mask for TIMER_DTDAS */
bogdanm 0:9b334a45a8ff 701 #define _TIMER_DTCTRL_DTDAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCTRL */
bogdanm 0:9b334a45a8ff 702 #define _TIMER_DTCTRL_DTDAS_NORESTART 0x00000000UL /**< Mode NORESTART for TIMER_DTCTRL */
bogdanm 0:9b334a45a8ff 703 #define _TIMER_DTCTRL_DTDAS_RESTART 0x00000001UL /**< Mode RESTART for TIMER_DTCTRL */
bogdanm 0:9b334a45a8ff 704 #define TIMER_DTCTRL_DTDAS_DEFAULT (_TIMER_DTCTRL_DTDAS_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_DTCTRL */
bogdanm 0:9b334a45a8ff 705 #define TIMER_DTCTRL_DTDAS_NORESTART (_TIMER_DTCTRL_DTDAS_NORESTART << 1) /**< Shifted mode NORESTART for TIMER_DTCTRL */
bogdanm 0:9b334a45a8ff 706 #define TIMER_DTCTRL_DTDAS_RESTART (_TIMER_DTCTRL_DTDAS_RESTART << 1) /**< Shifted mode RESTART for TIMER_DTCTRL */
bogdanm 0:9b334a45a8ff 707 #define TIMER_DTCTRL_DTIPOL (0x1UL << 2) /**< DTI Inactive Polarity */
bogdanm 0:9b334a45a8ff 708 #define _TIMER_DTCTRL_DTIPOL_SHIFT 2 /**< Shift value for TIMER_DTIPOL */
bogdanm 0:9b334a45a8ff 709 #define _TIMER_DTCTRL_DTIPOL_MASK 0x4UL /**< Bit mask for TIMER_DTIPOL */
bogdanm 0:9b334a45a8ff 710 #define _TIMER_DTCTRL_DTIPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCTRL */
bogdanm 0:9b334a45a8ff 711 #define TIMER_DTCTRL_DTIPOL_DEFAULT (_TIMER_DTCTRL_DTIPOL_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_DTCTRL */
bogdanm 0:9b334a45a8ff 712 #define TIMER_DTCTRL_DTCINV (0x1UL << 3) /**< DTI Complementary Output Invert. */
bogdanm 0:9b334a45a8ff 713 #define _TIMER_DTCTRL_DTCINV_SHIFT 3 /**< Shift value for TIMER_DTCINV */
bogdanm 0:9b334a45a8ff 714 #define _TIMER_DTCTRL_DTCINV_MASK 0x8UL /**< Bit mask for TIMER_DTCINV */
bogdanm 0:9b334a45a8ff 715 #define _TIMER_DTCTRL_DTCINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCTRL */
bogdanm 0:9b334a45a8ff 716 #define TIMER_DTCTRL_DTCINV_DEFAULT (_TIMER_DTCTRL_DTCINV_DEFAULT << 3) /**< Shifted mode DEFAULT for TIMER_DTCTRL */
bogdanm 0:9b334a45a8ff 717 #define _TIMER_DTCTRL_DTPRSSEL_SHIFT 4 /**< Shift value for TIMER_DTPRSSEL */
bogdanm 0:9b334a45a8ff 718 #define _TIMER_DTCTRL_DTPRSSEL_MASK 0xF0UL /**< Bit mask for TIMER_DTPRSSEL */
bogdanm 0:9b334a45a8ff 719 #define _TIMER_DTCTRL_DTPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCTRL */
bogdanm 0:9b334a45a8ff 720 #define _TIMER_DTCTRL_DTPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for TIMER_DTCTRL */
bogdanm 0:9b334a45a8ff 721 #define _TIMER_DTCTRL_DTPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for TIMER_DTCTRL */
bogdanm 0:9b334a45a8ff 722 #define _TIMER_DTCTRL_DTPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for TIMER_DTCTRL */
bogdanm 0:9b334a45a8ff 723 #define _TIMER_DTCTRL_DTPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for TIMER_DTCTRL */
bogdanm 0:9b334a45a8ff 724 #define _TIMER_DTCTRL_DTPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for TIMER_DTCTRL */
bogdanm 0:9b334a45a8ff 725 #define _TIMER_DTCTRL_DTPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for TIMER_DTCTRL */
bogdanm 0:9b334a45a8ff 726 #define _TIMER_DTCTRL_DTPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for TIMER_DTCTRL */
bogdanm 0:9b334a45a8ff 727 #define _TIMER_DTCTRL_DTPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for TIMER_DTCTRL */
bogdanm 0:9b334a45a8ff 728 #define _TIMER_DTCTRL_DTPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for TIMER_DTCTRL */
bogdanm 0:9b334a45a8ff 729 #define _TIMER_DTCTRL_DTPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for TIMER_DTCTRL */
bogdanm 0:9b334a45a8ff 730 #define _TIMER_DTCTRL_DTPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for TIMER_DTCTRL */
bogdanm 0:9b334a45a8ff 731 #define _TIMER_DTCTRL_DTPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for TIMER_DTCTRL */
bogdanm 0:9b334a45a8ff 732 #define TIMER_DTCTRL_DTPRSSEL_DEFAULT (_TIMER_DTCTRL_DTPRSSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_DTCTRL */
bogdanm 0:9b334a45a8ff 733 #define TIMER_DTCTRL_DTPRSSEL_PRSCH0 (_TIMER_DTCTRL_DTPRSSEL_PRSCH0 << 4) /**< Shifted mode PRSCH0 for TIMER_DTCTRL */
bogdanm 0:9b334a45a8ff 734 #define TIMER_DTCTRL_DTPRSSEL_PRSCH1 (_TIMER_DTCTRL_DTPRSSEL_PRSCH1 << 4) /**< Shifted mode PRSCH1 for TIMER_DTCTRL */
bogdanm 0:9b334a45a8ff 735 #define TIMER_DTCTRL_DTPRSSEL_PRSCH2 (_TIMER_DTCTRL_DTPRSSEL_PRSCH2 << 4) /**< Shifted mode PRSCH2 for TIMER_DTCTRL */
bogdanm 0:9b334a45a8ff 736 #define TIMER_DTCTRL_DTPRSSEL_PRSCH3 (_TIMER_DTCTRL_DTPRSSEL_PRSCH3 << 4) /**< Shifted mode PRSCH3 for TIMER_DTCTRL */
bogdanm 0:9b334a45a8ff 737 #define TIMER_DTCTRL_DTPRSSEL_PRSCH4 (_TIMER_DTCTRL_DTPRSSEL_PRSCH4 << 4) /**< Shifted mode PRSCH4 for TIMER_DTCTRL */
bogdanm 0:9b334a45a8ff 738 #define TIMER_DTCTRL_DTPRSSEL_PRSCH5 (_TIMER_DTCTRL_DTPRSSEL_PRSCH5 << 4) /**< Shifted mode PRSCH5 for TIMER_DTCTRL */
bogdanm 0:9b334a45a8ff 739 #define TIMER_DTCTRL_DTPRSSEL_PRSCH6 (_TIMER_DTCTRL_DTPRSSEL_PRSCH6 << 4) /**< Shifted mode PRSCH6 for TIMER_DTCTRL */
bogdanm 0:9b334a45a8ff 740 #define TIMER_DTCTRL_DTPRSSEL_PRSCH7 (_TIMER_DTCTRL_DTPRSSEL_PRSCH7 << 4) /**< Shifted mode PRSCH7 for TIMER_DTCTRL */
bogdanm 0:9b334a45a8ff 741 #define TIMER_DTCTRL_DTPRSSEL_PRSCH8 (_TIMER_DTCTRL_DTPRSSEL_PRSCH8 << 4) /**< Shifted mode PRSCH8 for TIMER_DTCTRL */
bogdanm 0:9b334a45a8ff 742 #define TIMER_DTCTRL_DTPRSSEL_PRSCH9 (_TIMER_DTCTRL_DTPRSSEL_PRSCH9 << 4) /**< Shifted mode PRSCH9 for TIMER_DTCTRL */
bogdanm 0:9b334a45a8ff 743 #define TIMER_DTCTRL_DTPRSSEL_PRSCH10 (_TIMER_DTCTRL_DTPRSSEL_PRSCH10 << 4) /**< Shifted mode PRSCH10 for TIMER_DTCTRL */
bogdanm 0:9b334a45a8ff 744 #define TIMER_DTCTRL_DTPRSSEL_PRSCH11 (_TIMER_DTCTRL_DTPRSSEL_PRSCH11 << 4) /**< Shifted mode PRSCH11 for TIMER_DTCTRL */
bogdanm 0:9b334a45a8ff 745 #define TIMER_DTCTRL_DTPRSEN (0x1UL << 24) /**< DTI PRS Source Enable */
bogdanm 0:9b334a45a8ff 746 #define _TIMER_DTCTRL_DTPRSEN_SHIFT 24 /**< Shift value for TIMER_DTPRSEN */
bogdanm 0:9b334a45a8ff 747 #define _TIMER_DTCTRL_DTPRSEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRSEN */
bogdanm 0:9b334a45a8ff 748 #define _TIMER_DTCTRL_DTPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCTRL */
bogdanm 0:9b334a45a8ff 749 #define TIMER_DTCTRL_DTPRSEN_DEFAULT (_TIMER_DTCTRL_DTPRSEN_DEFAULT << 24) /**< Shifted mode DEFAULT for TIMER_DTCTRL */
bogdanm 0:9b334a45a8ff 750
bogdanm 0:9b334a45a8ff 751 /* Bit fields for TIMER DTTIME */
bogdanm 0:9b334a45a8ff 752 #define _TIMER_DTTIME_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTTIME */
bogdanm 0:9b334a45a8ff 753 #define _TIMER_DTTIME_MASK 0x003F3F0FUL /**< Mask for TIMER_DTTIME */
bogdanm 0:9b334a45a8ff 754 #define _TIMER_DTTIME_DTPRESC_SHIFT 0 /**< Shift value for TIMER_DTPRESC */
bogdanm 0:9b334a45a8ff 755 #define _TIMER_DTTIME_DTPRESC_MASK 0xFUL /**< Bit mask for TIMER_DTPRESC */
bogdanm 0:9b334a45a8ff 756 #define _TIMER_DTTIME_DTPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTTIME */
bogdanm 0:9b334a45a8ff 757 #define _TIMER_DTTIME_DTPRESC_DIV1 0x00000000UL /**< Mode DIV1 for TIMER_DTTIME */
bogdanm 0:9b334a45a8ff 758 #define _TIMER_DTTIME_DTPRESC_DIV2 0x00000001UL /**< Mode DIV2 for TIMER_DTTIME */
bogdanm 0:9b334a45a8ff 759 #define _TIMER_DTTIME_DTPRESC_DIV4 0x00000002UL /**< Mode DIV4 for TIMER_DTTIME */
bogdanm 0:9b334a45a8ff 760 #define _TIMER_DTTIME_DTPRESC_DIV8 0x00000003UL /**< Mode DIV8 for TIMER_DTTIME */
bogdanm 0:9b334a45a8ff 761 #define _TIMER_DTTIME_DTPRESC_DIV16 0x00000004UL /**< Mode DIV16 for TIMER_DTTIME */
bogdanm 0:9b334a45a8ff 762 #define _TIMER_DTTIME_DTPRESC_DIV32 0x00000005UL /**< Mode DIV32 for TIMER_DTTIME */
bogdanm 0:9b334a45a8ff 763 #define _TIMER_DTTIME_DTPRESC_DIV64 0x00000006UL /**< Mode DIV64 for TIMER_DTTIME */
bogdanm 0:9b334a45a8ff 764 #define _TIMER_DTTIME_DTPRESC_DIV128 0x00000007UL /**< Mode DIV128 for TIMER_DTTIME */
bogdanm 0:9b334a45a8ff 765 #define _TIMER_DTTIME_DTPRESC_DIV256 0x00000008UL /**< Mode DIV256 for TIMER_DTTIME */
bogdanm 0:9b334a45a8ff 766 #define _TIMER_DTTIME_DTPRESC_DIV512 0x00000009UL /**< Mode DIV512 for TIMER_DTTIME */
bogdanm 0:9b334a45a8ff 767 #define _TIMER_DTTIME_DTPRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for TIMER_DTTIME */
bogdanm 0:9b334a45a8ff 768 #define TIMER_DTTIME_DTPRESC_DEFAULT (_TIMER_DTTIME_DTPRESC_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTTIME */
bogdanm 0:9b334a45a8ff 769 #define TIMER_DTTIME_DTPRESC_DIV1 (_TIMER_DTTIME_DTPRESC_DIV1 << 0) /**< Shifted mode DIV1 for TIMER_DTTIME */
bogdanm 0:9b334a45a8ff 770 #define TIMER_DTTIME_DTPRESC_DIV2 (_TIMER_DTTIME_DTPRESC_DIV2 << 0) /**< Shifted mode DIV2 for TIMER_DTTIME */
bogdanm 0:9b334a45a8ff 771 #define TIMER_DTTIME_DTPRESC_DIV4 (_TIMER_DTTIME_DTPRESC_DIV4 << 0) /**< Shifted mode DIV4 for TIMER_DTTIME */
bogdanm 0:9b334a45a8ff 772 #define TIMER_DTTIME_DTPRESC_DIV8 (_TIMER_DTTIME_DTPRESC_DIV8 << 0) /**< Shifted mode DIV8 for TIMER_DTTIME */
bogdanm 0:9b334a45a8ff 773 #define TIMER_DTTIME_DTPRESC_DIV16 (_TIMER_DTTIME_DTPRESC_DIV16 << 0) /**< Shifted mode DIV16 for TIMER_DTTIME */
bogdanm 0:9b334a45a8ff 774 #define TIMER_DTTIME_DTPRESC_DIV32 (_TIMER_DTTIME_DTPRESC_DIV32 << 0) /**< Shifted mode DIV32 for TIMER_DTTIME */
bogdanm 0:9b334a45a8ff 775 #define TIMER_DTTIME_DTPRESC_DIV64 (_TIMER_DTTIME_DTPRESC_DIV64 << 0) /**< Shifted mode DIV64 for TIMER_DTTIME */
bogdanm 0:9b334a45a8ff 776 #define TIMER_DTTIME_DTPRESC_DIV128 (_TIMER_DTTIME_DTPRESC_DIV128 << 0) /**< Shifted mode DIV128 for TIMER_DTTIME */
bogdanm 0:9b334a45a8ff 777 #define TIMER_DTTIME_DTPRESC_DIV256 (_TIMER_DTTIME_DTPRESC_DIV256 << 0) /**< Shifted mode DIV256 for TIMER_DTTIME */
bogdanm 0:9b334a45a8ff 778 #define TIMER_DTTIME_DTPRESC_DIV512 (_TIMER_DTTIME_DTPRESC_DIV512 << 0) /**< Shifted mode DIV512 for TIMER_DTTIME */
bogdanm 0:9b334a45a8ff 779 #define TIMER_DTTIME_DTPRESC_DIV1024 (_TIMER_DTTIME_DTPRESC_DIV1024 << 0) /**< Shifted mode DIV1024 for TIMER_DTTIME */
bogdanm 0:9b334a45a8ff 780 #define _TIMER_DTTIME_DTRISET_SHIFT 8 /**< Shift value for TIMER_DTRISET */
bogdanm 0:9b334a45a8ff 781 #define _TIMER_DTTIME_DTRISET_MASK 0x3F00UL /**< Bit mask for TIMER_DTRISET */
bogdanm 0:9b334a45a8ff 782 #define _TIMER_DTTIME_DTRISET_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTTIME */
bogdanm 0:9b334a45a8ff 783 #define TIMER_DTTIME_DTRISET_DEFAULT (_TIMER_DTTIME_DTRISET_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_DTTIME */
bogdanm 0:9b334a45a8ff 784 #define _TIMER_DTTIME_DTFALLT_SHIFT 16 /**< Shift value for TIMER_DTFALLT */
bogdanm 0:9b334a45a8ff 785 #define _TIMER_DTTIME_DTFALLT_MASK 0x3F0000UL /**< Bit mask for TIMER_DTFALLT */
bogdanm 0:9b334a45a8ff 786 #define _TIMER_DTTIME_DTFALLT_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTTIME */
bogdanm 0:9b334a45a8ff 787 #define TIMER_DTTIME_DTFALLT_DEFAULT (_TIMER_DTTIME_DTFALLT_DEFAULT << 16) /**< Shifted mode DEFAULT for TIMER_DTTIME */
bogdanm 0:9b334a45a8ff 788
bogdanm 0:9b334a45a8ff 789 /* Bit fields for TIMER DTFC */
bogdanm 0:9b334a45a8ff 790 #define _TIMER_DTFC_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTFC */
bogdanm 0:9b334a45a8ff 791 #define _TIMER_DTFC_MASK 0x0F030707UL /**< Mask for TIMER_DTFC */
bogdanm 0:9b334a45a8ff 792 #define _TIMER_DTFC_DTPRS0FSEL_SHIFT 0 /**< Shift value for TIMER_DTPRS0FSEL */
bogdanm 0:9b334a45a8ff 793 #define _TIMER_DTFC_DTPRS0FSEL_MASK 0x7UL /**< Bit mask for TIMER_DTPRS0FSEL */
bogdanm 0:9b334a45a8ff 794 #define _TIMER_DTFC_DTPRS0FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFC */
bogdanm 0:9b334a45a8ff 795 #define _TIMER_DTFC_DTPRS0FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for TIMER_DTFC */
bogdanm 0:9b334a45a8ff 796 #define _TIMER_DTFC_DTPRS0FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for TIMER_DTFC */
bogdanm 0:9b334a45a8ff 797 #define _TIMER_DTFC_DTPRS0FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for TIMER_DTFC */
bogdanm 0:9b334a45a8ff 798 #define _TIMER_DTFC_DTPRS0FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for TIMER_DTFC */
bogdanm 0:9b334a45a8ff 799 #define _TIMER_DTFC_DTPRS0FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for TIMER_DTFC */
bogdanm 0:9b334a45a8ff 800 #define _TIMER_DTFC_DTPRS0FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for TIMER_DTFC */
bogdanm 0:9b334a45a8ff 801 #define _TIMER_DTFC_DTPRS0FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for TIMER_DTFC */
bogdanm 0:9b334a45a8ff 802 #define _TIMER_DTFC_DTPRS0FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for TIMER_DTFC */
bogdanm 0:9b334a45a8ff 803 #define TIMER_DTFC_DTPRS0FSEL_DEFAULT (_TIMER_DTFC_DTPRS0FSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTFC */
bogdanm 0:9b334a45a8ff 804 #define TIMER_DTFC_DTPRS0FSEL_PRSCH0 (_TIMER_DTFC_DTPRS0FSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for TIMER_DTFC */
bogdanm 0:9b334a45a8ff 805 #define TIMER_DTFC_DTPRS0FSEL_PRSCH1 (_TIMER_DTFC_DTPRS0FSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for TIMER_DTFC */
bogdanm 0:9b334a45a8ff 806 #define TIMER_DTFC_DTPRS0FSEL_PRSCH2 (_TIMER_DTFC_DTPRS0FSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for TIMER_DTFC */
bogdanm 0:9b334a45a8ff 807 #define TIMER_DTFC_DTPRS0FSEL_PRSCH3 (_TIMER_DTFC_DTPRS0FSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for TIMER_DTFC */
bogdanm 0:9b334a45a8ff 808 #define TIMER_DTFC_DTPRS0FSEL_PRSCH4 (_TIMER_DTFC_DTPRS0FSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for TIMER_DTFC */
bogdanm 0:9b334a45a8ff 809 #define TIMER_DTFC_DTPRS0FSEL_PRSCH5 (_TIMER_DTFC_DTPRS0FSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for TIMER_DTFC */
bogdanm 0:9b334a45a8ff 810 #define TIMER_DTFC_DTPRS0FSEL_PRSCH6 (_TIMER_DTFC_DTPRS0FSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for TIMER_DTFC */
bogdanm 0:9b334a45a8ff 811 #define TIMER_DTFC_DTPRS0FSEL_PRSCH7 (_TIMER_DTFC_DTPRS0FSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for TIMER_DTFC */
bogdanm 0:9b334a45a8ff 812 #define _TIMER_DTFC_DTPRS1FSEL_SHIFT 8 /**< Shift value for TIMER_DTPRS1FSEL */
bogdanm 0:9b334a45a8ff 813 #define _TIMER_DTFC_DTPRS1FSEL_MASK 0x700UL /**< Bit mask for TIMER_DTPRS1FSEL */
bogdanm 0:9b334a45a8ff 814 #define _TIMER_DTFC_DTPRS1FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFC */
bogdanm 0:9b334a45a8ff 815 #define _TIMER_DTFC_DTPRS1FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for TIMER_DTFC */
bogdanm 0:9b334a45a8ff 816 #define _TIMER_DTFC_DTPRS1FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for TIMER_DTFC */
bogdanm 0:9b334a45a8ff 817 #define _TIMER_DTFC_DTPRS1FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for TIMER_DTFC */
bogdanm 0:9b334a45a8ff 818 #define _TIMER_DTFC_DTPRS1FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for TIMER_DTFC */
bogdanm 0:9b334a45a8ff 819 #define _TIMER_DTFC_DTPRS1FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for TIMER_DTFC */
bogdanm 0:9b334a45a8ff 820 #define _TIMER_DTFC_DTPRS1FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for TIMER_DTFC */
bogdanm 0:9b334a45a8ff 821 #define _TIMER_DTFC_DTPRS1FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for TIMER_DTFC */
bogdanm 0:9b334a45a8ff 822 #define _TIMER_DTFC_DTPRS1FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for TIMER_DTFC */
bogdanm 0:9b334a45a8ff 823 #define TIMER_DTFC_DTPRS1FSEL_DEFAULT (_TIMER_DTFC_DTPRS1FSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_DTFC */
bogdanm 0:9b334a45a8ff 824 #define TIMER_DTFC_DTPRS1FSEL_PRSCH0 (_TIMER_DTFC_DTPRS1FSEL_PRSCH0 << 8) /**< Shifted mode PRSCH0 for TIMER_DTFC */
bogdanm 0:9b334a45a8ff 825 #define TIMER_DTFC_DTPRS1FSEL_PRSCH1 (_TIMER_DTFC_DTPRS1FSEL_PRSCH1 << 8) /**< Shifted mode PRSCH1 for TIMER_DTFC */
bogdanm 0:9b334a45a8ff 826 #define TIMER_DTFC_DTPRS1FSEL_PRSCH2 (_TIMER_DTFC_DTPRS1FSEL_PRSCH2 << 8) /**< Shifted mode PRSCH2 for TIMER_DTFC */
bogdanm 0:9b334a45a8ff 827 #define TIMER_DTFC_DTPRS1FSEL_PRSCH3 (_TIMER_DTFC_DTPRS1FSEL_PRSCH3 << 8) /**< Shifted mode PRSCH3 for TIMER_DTFC */
bogdanm 0:9b334a45a8ff 828 #define TIMER_DTFC_DTPRS1FSEL_PRSCH4 (_TIMER_DTFC_DTPRS1FSEL_PRSCH4 << 8) /**< Shifted mode PRSCH4 for TIMER_DTFC */
bogdanm 0:9b334a45a8ff 829 #define TIMER_DTFC_DTPRS1FSEL_PRSCH5 (_TIMER_DTFC_DTPRS1FSEL_PRSCH5 << 8) /**< Shifted mode PRSCH5 for TIMER_DTFC */
bogdanm 0:9b334a45a8ff 830 #define TIMER_DTFC_DTPRS1FSEL_PRSCH6 (_TIMER_DTFC_DTPRS1FSEL_PRSCH6 << 8) /**< Shifted mode PRSCH6 for TIMER_DTFC */
bogdanm 0:9b334a45a8ff 831 #define TIMER_DTFC_DTPRS1FSEL_PRSCH7 (_TIMER_DTFC_DTPRS1FSEL_PRSCH7 << 8) /**< Shifted mode PRSCH7 for TIMER_DTFC */
bogdanm 0:9b334a45a8ff 832 #define _TIMER_DTFC_DTFA_SHIFT 16 /**< Shift value for TIMER_DTFA */
bogdanm 0:9b334a45a8ff 833 #define _TIMER_DTFC_DTFA_MASK 0x30000UL /**< Bit mask for TIMER_DTFA */
bogdanm 0:9b334a45a8ff 834 #define _TIMER_DTFC_DTFA_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFC */
bogdanm 0:9b334a45a8ff 835 #define _TIMER_DTFC_DTFA_NONE 0x00000000UL /**< Mode NONE for TIMER_DTFC */
bogdanm 0:9b334a45a8ff 836 #define _TIMER_DTFC_DTFA_INACTIVE 0x00000001UL /**< Mode INACTIVE for TIMER_DTFC */
bogdanm 0:9b334a45a8ff 837 #define _TIMER_DTFC_DTFA_CLEAR 0x00000002UL /**< Mode CLEAR for TIMER_DTFC */
bogdanm 0:9b334a45a8ff 838 #define _TIMER_DTFC_DTFA_TRISTATE 0x00000003UL /**< Mode TRISTATE for TIMER_DTFC */
bogdanm 0:9b334a45a8ff 839 #define TIMER_DTFC_DTFA_DEFAULT (_TIMER_DTFC_DTFA_DEFAULT << 16) /**< Shifted mode DEFAULT for TIMER_DTFC */
bogdanm 0:9b334a45a8ff 840 #define TIMER_DTFC_DTFA_NONE (_TIMER_DTFC_DTFA_NONE << 16) /**< Shifted mode NONE for TIMER_DTFC */
bogdanm 0:9b334a45a8ff 841 #define TIMER_DTFC_DTFA_INACTIVE (_TIMER_DTFC_DTFA_INACTIVE << 16) /**< Shifted mode INACTIVE for TIMER_DTFC */
bogdanm 0:9b334a45a8ff 842 #define TIMER_DTFC_DTFA_CLEAR (_TIMER_DTFC_DTFA_CLEAR << 16) /**< Shifted mode CLEAR for TIMER_DTFC */
bogdanm 0:9b334a45a8ff 843 #define TIMER_DTFC_DTFA_TRISTATE (_TIMER_DTFC_DTFA_TRISTATE << 16) /**< Shifted mode TRISTATE for TIMER_DTFC */
bogdanm 0:9b334a45a8ff 844 #define TIMER_DTFC_DTPRS0FEN (0x1UL << 24) /**< DTI PRS 0 Fault Enable */
bogdanm 0:9b334a45a8ff 845 #define _TIMER_DTFC_DTPRS0FEN_SHIFT 24 /**< Shift value for TIMER_DTPRS0FEN */
bogdanm 0:9b334a45a8ff 846 #define _TIMER_DTFC_DTPRS0FEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRS0FEN */
bogdanm 0:9b334a45a8ff 847 #define _TIMER_DTFC_DTPRS0FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFC */
bogdanm 0:9b334a45a8ff 848 #define TIMER_DTFC_DTPRS0FEN_DEFAULT (_TIMER_DTFC_DTPRS0FEN_DEFAULT << 24) /**< Shifted mode DEFAULT for TIMER_DTFC */
bogdanm 0:9b334a45a8ff 849 #define TIMER_DTFC_DTPRS1FEN (0x1UL << 25) /**< DTI PRS 1 Fault Enable */
bogdanm 0:9b334a45a8ff 850 #define _TIMER_DTFC_DTPRS1FEN_SHIFT 25 /**< Shift value for TIMER_DTPRS1FEN */
bogdanm 0:9b334a45a8ff 851 #define _TIMER_DTFC_DTPRS1FEN_MASK 0x2000000UL /**< Bit mask for TIMER_DTPRS1FEN */
bogdanm 0:9b334a45a8ff 852 #define _TIMER_DTFC_DTPRS1FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFC */
bogdanm 0:9b334a45a8ff 853 #define TIMER_DTFC_DTPRS1FEN_DEFAULT (_TIMER_DTFC_DTPRS1FEN_DEFAULT << 25) /**< Shifted mode DEFAULT for TIMER_DTFC */
bogdanm 0:9b334a45a8ff 854 #define TIMER_DTFC_DTDBGFEN (0x1UL << 26) /**< DTI Debugger Fault Enable */
bogdanm 0:9b334a45a8ff 855 #define _TIMER_DTFC_DTDBGFEN_SHIFT 26 /**< Shift value for TIMER_DTDBGFEN */
bogdanm 0:9b334a45a8ff 856 #define _TIMER_DTFC_DTDBGFEN_MASK 0x4000000UL /**< Bit mask for TIMER_DTDBGFEN */
bogdanm 0:9b334a45a8ff 857 #define _TIMER_DTFC_DTDBGFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFC */
bogdanm 0:9b334a45a8ff 858 #define TIMER_DTFC_DTDBGFEN_DEFAULT (_TIMER_DTFC_DTDBGFEN_DEFAULT << 26) /**< Shifted mode DEFAULT for TIMER_DTFC */
bogdanm 0:9b334a45a8ff 859 #define TIMER_DTFC_DTLOCKUPFEN (0x1UL << 27) /**< DTI Lockup Fault Enable */
bogdanm 0:9b334a45a8ff 860 #define _TIMER_DTFC_DTLOCKUPFEN_SHIFT 27 /**< Shift value for TIMER_DTLOCKUPFEN */
bogdanm 0:9b334a45a8ff 861 #define _TIMER_DTFC_DTLOCKUPFEN_MASK 0x8000000UL /**< Bit mask for TIMER_DTLOCKUPFEN */
bogdanm 0:9b334a45a8ff 862 #define _TIMER_DTFC_DTLOCKUPFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFC */
bogdanm 0:9b334a45a8ff 863 #define TIMER_DTFC_DTLOCKUPFEN_DEFAULT (_TIMER_DTFC_DTLOCKUPFEN_DEFAULT << 27) /**< Shifted mode DEFAULT for TIMER_DTFC */
bogdanm 0:9b334a45a8ff 864
bogdanm 0:9b334a45a8ff 865 /* Bit fields for TIMER DTOGEN */
bogdanm 0:9b334a45a8ff 866 #define _TIMER_DTOGEN_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTOGEN */
bogdanm 0:9b334a45a8ff 867 #define _TIMER_DTOGEN_MASK 0x0000003FUL /**< Mask for TIMER_DTOGEN */
bogdanm 0:9b334a45a8ff 868 #define TIMER_DTOGEN_DTOGCC0EN (0x1UL << 0) /**< DTI CC0 Output Generation Enable */
bogdanm 0:9b334a45a8ff 869 #define _TIMER_DTOGEN_DTOGCC0EN_SHIFT 0 /**< Shift value for TIMER_DTOGCC0EN */
bogdanm 0:9b334a45a8ff 870 #define _TIMER_DTOGEN_DTOGCC0EN_MASK 0x1UL /**< Bit mask for TIMER_DTOGCC0EN */
bogdanm 0:9b334a45a8ff 871 #define _TIMER_DTOGEN_DTOGCC0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTOGEN */
bogdanm 0:9b334a45a8ff 872 #define TIMER_DTOGEN_DTOGCC0EN_DEFAULT (_TIMER_DTOGEN_DTOGCC0EN_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTOGEN */
bogdanm 0:9b334a45a8ff 873 #define TIMER_DTOGEN_DTOGCC1EN (0x1UL << 1) /**< DTI CC1 Output Generation Enable */
bogdanm 0:9b334a45a8ff 874 #define _TIMER_DTOGEN_DTOGCC1EN_SHIFT 1 /**< Shift value for TIMER_DTOGCC1EN */
bogdanm 0:9b334a45a8ff 875 #define _TIMER_DTOGEN_DTOGCC1EN_MASK 0x2UL /**< Bit mask for TIMER_DTOGCC1EN */
bogdanm 0:9b334a45a8ff 876 #define _TIMER_DTOGEN_DTOGCC1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTOGEN */
bogdanm 0:9b334a45a8ff 877 #define TIMER_DTOGEN_DTOGCC1EN_DEFAULT (_TIMER_DTOGEN_DTOGCC1EN_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_DTOGEN */
bogdanm 0:9b334a45a8ff 878 #define TIMER_DTOGEN_DTOGCC2EN (0x1UL << 2) /**< DTI CC2 Output Generation Enable */
bogdanm 0:9b334a45a8ff 879 #define _TIMER_DTOGEN_DTOGCC2EN_SHIFT 2 /**< Shift value for TIMER_DTOGCC2EN */
bogdanm 0:9b334a45a8ff 880 #define _TIMER_DTOGEN_DTOGCC2EN_MASK 0x4UL /**< Bit mask for TIMER_DTOGCC2EN */
bogdanm 0:9b334a45a8ff 881 #define _TIMER_DTOGEN_DTOGCC2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTOGEN */
bogdanm 0:9b334a45a8ff 882 #define TIMER_DTOGEN_DTOGCC2EN_DEFAULT (_TIMER_DTOGEN_DTOGCC2EN_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_DTOGEN */
bogdanm 0:9b334a45a8ff 883 #define TIMER_DTOGEN_DTOGCDTI0EN (0x1UL << 3) /**< DTI CDTI0 Output Generation Enable */
bogdanm 0:9b334a45a8ff 884 #define _TIMER_DTOGEN_DTOGCDTI0EN_SHIFT 3 /**< Shift value for TIMER_DTOGCDTI0EN */
bogdanm 0:9b334a45a8ff 885 #define _TIMER_DTOGEN_DTOGCDTI0EN_MASK 0x8UL /**< Bit mask for TIMER_DTOGCDTI0EN */
bogdanm 0:9b334a45a8ff 886 #define _TIMER_DTOGEN_DTOGCDTI0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTOGEN */
bogdanm 0:9b334a45a8ff 887 #define TIMER_DTOGEN_DTOGCDTI0EN_DEFAULT (_TIMER_DTOGEN_DTOGCDTI0EN_DEFAULT << 3) /**< Shifted mode DEFAULT for TIMER_DTOGEN */
bogdanm 0:9b334a45a8ff 888 #define TIMER_DTOGEN_DTOGCDTI1EN (0x1UL << 4) /**< DTI CDTI1 Output Generation Enable */
bogdanm 0:9b334a45a8ff 889 #define _TIMER_DTOGEN_DTOGCDTI1EN_SHIFT 4 /**< Shift value for TIMER_DTOGCDTI1EN */
bogdanm 0:9b334a45a8ff 890 #define _TIMER_DTOGEN_DTOGCDTI1EN_MASK 0x10UL /**< Bit mask for TIMER_DTOGCDTI1EN */
bogdanm 0:9b334a45a8ff 891 #define _TIMER_DTOGEN_DTOGCDTI1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTOGEN */
bogdanm 0:9b334a45a8ff 892 #define TIMER_DTOGEN_DTOGCDTI1EN_DEFAULT (_TIMER_DTOGEN_DTOGCDTI1EN_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_DTOGEN */
bogdanm 0:9b334a45a8ff 893 #define TIMER_DTOGEN_DTOGCDTI2EN (0x1UL << 5) /**< DTI CDTI2 Output Generation Enable */
bogdanm 0:9b334a45a8ff 894 #define _TIMER_DTOGEN_DTOGCDTI2EN_SHIFT 5 /**< Shift value for TIMER_DTOGCDTI2EN */
bogdanm 0:9b334a45a8ff 895 #define _TIMER_DTOGEN_DTOGCDTI2EN_MASK 0x20UL /**< Bit mask for TIMER_DTOGCDTI2EN */
bogdanm 0:9b334a45a8ff 896 #define _TIMER_DTOGEN_DTOGCDTI2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTOGEN */
bogdanm 0:9b334a45a8ff 897 #define TIMER_DTOGEN_DTOGCDTI2EN_DEFAULT (_TIMER_DTOGEN_DTOGCDTI2EN_DEFAULT << 5) /**< Shifted mode DEFAULT for TIMER_DTOGEN */
bogdanm 0:9b334a45a8ff 898
bogdanm 0:9b334a45a8ff 899 /* Bit fields for TIMER DTFAULT */
bogdanm 0:9b334a45a8ff 900 #define _TIMER_DTFAULT_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTFAULT */
bogdanm 0:9b334a45a8ff 901 #define _TIMER_DTFAULT_MASK 0x0000000FUL /**< Mask for TIMER_DTFAULT */
bogdanm 0:9b334a45a8ff 902 #define TIMER_DTFAULT_DTPRS0F (0x1UL << 0) /**< DTI PRS 0 Fault */
bogdanm 0:9b334a45a8ff 903 #define _TIMER_DTFAULT_DTPRS0F_SHIFT 0 /**< Shift value for TIMER_DTPRS0F */
bogdanm 0:9b334a45a8ff 904 #define _TIMER_DTFAULT_DTPRS0F_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0F */
bogdanm 0:9b334a45a8ff 905 #define _TIMER_DTFAULT_DTPRS0F_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULT */
bogdanm 0:9b334a45a8ff 906 #define TIMER_DTFAULT_DTPRS0F_DEFAULT (_TIMER_DTFAULT_DTPRS0F_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTFAULT */
bogdanm 0:9b334a45a8ff 907 #define TIMER_DTFAULT_DTPRS1F (0x1UL << 1) /**< DTI PRS 1 Fault */
bogdanm 0:9b334a45a8ff 908 #define _TIMER_DTFAULT_DTPRS1F_SHIFT 1 /**< Shift value for TIMER_DTPRS1F */
bogdanm 0:9b334a45a8ff 909 #define _TIMER_DTFAULT_DTPRS1F_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1F */
bogdanm 0:9b334a45a8ff 910 #define _TIMER_DTFAULT_DTPRS1F_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULT */
bogdanm 0:9b334a45a8ff 911 #define TIMER_DTFAULT_DTPRS1F_DEFAULT (_TIMER_DTFAULT_DTPRS1F_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_DTFAULT */
bogdanm 0:9b334a45a8ff 912 #define TIMER_DTFAULT_DTDBGF (0x1UL << 2) /**< DTI Debugger Fault */
bogdanm 0:9b334a45a8ff 913 #define _TIMER_DTFAULT_DTDBGF_SHIFT 2 /**< Shift value for TIMER_DTDBGF */
bogdanm 0:9b334a45a8ff 914 #define _TIMER_DTFAULT_DTDBGF_MASK 0x4UL /**< Bit mask for TIMER_DTDBGF */
bogdanm 0:9b334a45a8ff 915 #define _TIMER_DTFAULT_DTDBGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULT */
bogdanm 0:9b334a45a8ff 916 #define TIMER_DTFAULT_DTDBGF_DEFAULT (_TIMER_DTFAULT_DTDBGF_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_DTFAULT */
bogdanm 0:9b334a45a8ff 917 #define TIMER_DTFAULT_DTLOCKUPF (0x1UL << 3) /**< DTI Lockup Fault */
bogdanm 0:9b334a45a8ff 918 #define _TIMER_DTFAULT_DTLOCKUPF_SHIFT 3 /**< Shift value for TIMER_DTLOCKUPF */
bogdanm 0:9b334a45a8ff 919 #define _TIMER_DTFAULT_DTLOCKUPF_MASK 0x8UL /**< Bit mask for TIMER_DTLOCKUPF */
bogdanm 0:9b334a45a8ff 920 #define _TIMER_DTFAULT_DTLOCKUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULT */
bogdanm 0:9b334a45a8ff 921 #define TIMER_DTFAULT_DTLOCKUPF_DEFAULT (_TIMER_DTFAULT_DTLOCKUPF_DEFAULT << 3) /**< Shifted mode DEFAULT for TIMER_DTFAULT */
bogdanm 0:9b334a45a8ff 922
bogdanm 0:9b334a45a8ff 923 /* Bit fields for TIMER DTFAULTC */
bogdanm 0:9b334a45a8ff 924 #define _TIMER_DTFAULTC_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTFAULTC */
bogdanm 0:9b334a45a8ff 925 #define _TIMER_DTFAULTC_MASK 0x0000000FUL /**< Mask for TIMER_DTFAULTC */
bogdanm 0:9b334a45a8ff 926 #define TIMER_DTFAULTC_DTPRS0FC (0x1UL << 0) /**< DTI PRS0 Fault Clear */
bogdanm 0:9b334a45a8ff 927 #define _TIMER_DTFAULTC_DTPRS0FC_SHIFT 0 /**< Shift value for TIMER_DTPRS0FC */
bogdanm 0:9b334a45a8ff 928 #define _TIMER_DTFAULTC_DTPRS0FC_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0FC */
bogdanm 0:9b334a45a8ff 929 #define _TIMER_DTFAULTC_DTPRS0FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULTC */
bogdanm 0:9b334a45a8ff 930 #define TIMER_DTFAULTC_DTPRS0FC_DEFAULT (_TIMER_DTFAULTC_DTPRS0FC_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTFAULTC */
bogdanm 0:9b334a45a8ff 931 #define TIMER_DTFAULTC_DTPRS1FC (0x1UL << 1) /**< DTI PRS1 Fault Clear */
bogdanm 0:9b334a45a8ff 932 #define _TIMER_DTFAULTC_DTPRS1FC_SHIFT 1 /**< Shift value for TIMER_DTPRS1FC */
bogdanm 0:9b334a45a8ff 933 #define _TIMER_DTFAULTC_DTPRS1FC_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1FC */
bogdanm 0:9b334a45a8ff 934 #define _TIMER_DTFAULTC_DTPRS1FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULTC */
bogdanm 0:9b334a45a8ff 935 #define TIMER_DTFAULTC_DTPRS1FC_DEFAULT (_TIMER_DTFAULTC_DTPRS1FC_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_DTFAULTC */
bogdanm 0:9b334a45a8ff 936 #define TIMER_DTFAULTC_DTDBGFC (0x1UL << 2) /**< DTI Debugger Fault Clear */
bogdanm 0:9b334a45a8ff 937 #define _TIMER_DTFAULTC_DTDBGFC_SHIFT 2 /**< Shift value for TIMER_DTDBGFC */
bogdanm 0:9b334a45a8ff 938 #define _TIMER_DTFAULTC_DTDBGFC_MASK 0x4UL /**< Bit mask for TIMER_DTDBGFC */
bogdanm 0:9b334a45a8ff 939 #define _TIMER_DTFAULTC_DTDBGFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULTC */
bogdanm 0:9b334a45a8ff 940 #define TIMER_DTFAULTC_DTDBGFC_DEFAULT (_TIMER_DTFAULTC_DTDBGFC_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_DTFAULTC */
bogdanm 0:9b334a45a8ff 941 #define TIMER_DTFAULTC_TLOCKUPFC (0x1UL << 3) /**< DTI Lockup Fault Clear */
bogdanm 0:9b334a45a8ff 942 #define _TIMER_DTFAULTC_TLOCKUPFC_SHIFT 3 /**< Shift value for TIMER_TLOCKUPFC */
bogdanm 0:9b334a45a8ff 943 #define _TIMER_DTFAULTC_TLOCKUPFC_MASK 0x8UL /**< Bit mask for TIMER_TLOCKUPFC */
bogdanm 0:9b334a45a8ff 944 #define _TIMER_DTFAULTC_TLOCKUPFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULTC */
bogdanm 0:9b334a45a8ff 945 #define TIMER_DTFAULTC_TLOCKUPFC_DEFAULT (_TIMER_DTFAULTC_TLOCKUPFC_DEFAULT << 3) /**< Shifted mode DEFAULT for TIMER_DTFAULTC */
bogdanm 0:9b334a45a8ff 946
bogdanm 0:9b334a45a8ff 947 /* Bit fields for TIMER DTLOCK */
bogdanm 0:9b334a45a8ff 948 #define _TIMER_DTLOCK_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTLOCK */
bogdanm 0:9b334a45a8ff 949 #define _TIMER_DTLOCK_MASK 0x0000FFFFUL /**< Mask for TIMER_DTLOCK */
bogdanm 0:9b334a45a8ff 950 #define _TIMER_DTLOCK_LOCKKEY_SHIFT 0 /**< Shift value for TIMER_LOCKKEY */
bogdanm 0:9b334a45a8ff 951 #define _TIMER_DTLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_LOCKKEY */
bogdanm 0:9b334a45a8ff 952 #define _TIMER_DTLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTLOCK */
bogdanm 0:9b334a45a8ff 953 #define _TIMER_DTLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for TIMER_DTLOCK */
bogdanm 0:9b334a45a8ff 954 #define _TIMER_DTLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for TIMER_DTLOCK */
bogdanm 0:9b334a45a8ff 955 #define _TIMER_DTLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for TIMER_DTLOCK */
bogdanm 0:9b334a45a8ff 956 #define _TIMER_DTLOCK_LOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for TIMER_DTLOCK */
bogdanm 0:9b334a45a8ff 957 #define TIMER_DTLOCK_LOCKKEY_DEFAULT (_TIMER_DTLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTLOCK */
bogdanm 0:9b334a45a8ff 958 #define TIMER_DTLOCK_LOCKKEY_LOCK (_TIMER_DTLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for TIMER_DTLOCK */
bogdanm 0:9b334a45a8ff 959 #define TIMER_DTLOCK_LOCKKEY_UNLOCKED (_TIMER_DTLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for TIMER_DTLOCK */
bogdanm 0:9b334a45a8ff 960 #define TIMER_DTLOCK_LOCKKEY_LOCKED (_TIMER_DTLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for TIMER_DTLOCK */
bogdanm 0:9b334a45a8ff 961 #define TIMER_DTLOCK_LOCKKEY_UNLOCK (_TIMER_DTLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for TIMER_DTLOCK */
bogdanm 0:9b334a45a8ff 962
bogdanm 0:9b334a45a8ff 963 /** @} End of group EFM32LG_TIMER */
bogdanm 0:9b334a45a8ff 964
bogdanm 0:9b334a45a8ff 965