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targets/TARGET_Maxim/TARGET_MAX32600/rtc_api.c@186:707f6e361f3e, 2018-06-22 (annotated)

Committer:
Anna Bridge
Date:
Fri Jun 22 16:45:37 2018 +0100
Revision:
186:707f6e361f3e
Parent:
174:b96e65c34a4d
Child:
188:bcfe06ba3d64
mbed-dev library. Release version 162

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /*******************************************************************************
<> 144:ef7eb2e8f9f7 2 * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
<> 144:ef7eb2e8f9f7 3 *
<> 144:ef7eb2e8f9f7 4 * Permission is hereby granted, free of charge, to any person obtaining a
<> 144:ef7eb2e8f9f7 5 * copy of this software and associated documentation files (the "Software"),
<> 144:ef7eb2e8f9f7 6 * to deal in the Software without restriction, including without limitation
<> 144:ef7eb2e8f9f7 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
<> 144:ef7eb2e8f9f7 8 * and/or sell copies of the Software, and to permit persons to whom the
<> 144:ef7eb2e8f9f7 9 * Software is furnished to do so, subject to the following conditions:
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 * The above copyright notice and this permission notice shall be included
<> 144:ef7eb2e8f9f7 12 * in all copies or substantial portions of the Software.
<> 144:ef7eb2e8f9f7 13 *
<> 144:ef7eb2e8f9f7 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
<> 144:ef7eb2e8f9f7 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
<> 144:ef7eb2e8f9f7 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
<> 144:ef7eb2e8f9f7 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
<> 144:ef7eb2e8f9f7 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
<> 144:ef7eb2e8f9f7 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
<> 144:ef7eb2e8f9f7 20 * OTHER DEALINGS IN THE SOFTWARE.
<> 144:ef7eb2e8f9f7 21 *
<> 144:ef7eb2e8f9f7 22 * Except as contained in this notice, the name of Maxim Integrated
<> 144:ef7eb2e8f9f7 23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
<> 144:ef7eb2e8f9f7 24 * Products, Inc. Branding Policy.
<> 144:ef7eb2e8f9f7 25 *
<> 144:ef7eb2e8f9f7 26 * The mere transfer of this software does not imply any licenses
<> 144:ef7eb2e8f9f7 27 * of trade secrets, proprietary technology, copyrights, patents,
<> 144:ef7eb2e8f9f7 28 * trademarks, maskwork rights, or any other form of intellectual
<> 144:ef7eb2e8f9f7 29 * property whatsoever. Maxim Integrated Products, Inc. retains all
<> 144:ef7eb2e8f9f7 30 * ownership rights.
<> 144:ef7eb2e8f9f7 31 *******************************************************************************
<> 144:ef7eb2e8f9f7 32 */
<> 144:ef7eb2e8f9f7 33
<> 144:ef7eb2e8f9f7 34 #include "rtc_api.h"
<> 144:ef7eb2e8f9f7 35 #include "lp_ticker_api.h"
Anna Bridge 186:707f6e361f3e 36 #include "ticker_api.h"
<> 144:ef7eb2e8f9f7 37 #include "cmsis.h"
<> 144:ef7eb2e8f9f7 38 #include "rtc_regs.h"
<> 144:ef7eb2e8f9f7 39 #include "pwrseq_regs.h"
<> 144:ef7eb2e8f9f7 40 #include "clkman_regs.h"
<> 144:ef7eb2e8f9f7 41
<> 144:ef7eb2e8f9f7 42 #define PRESCALE_VAL MXC_E_RTC_PRESCALE_DIV_2_0 // Set the divider for the 4kHz clock
<> 144:ef7eb2e8f9f7 43 #define SHIFT_AMT (MXC_E_RTC_PRESCALE_DIV_2_12 - PRESCALE_VAL)
<> 144:ef7eb2e8f9f7 44
<> 144:ef7eb2e8f9f7 45 #define WINDOW 1000
<> 144:ef7eb2e8f9f7 46
<> 144:ef7eb2e8f9f7 47 static int rtc_inited = 0;
<> 144:ef7eb2e8f9f7 48 static volatile uint32_t overflow_cnt = 0;
<> 144:ef7eb2e8f9f7 49
<> 144:ef7eb2e8f9f7 50 static uint64_t rtc_read64(void);
<> 144:ef7eb2e8f9f7 51
<> 144:ef7eb2e8f9f7 52 //******************************************************************************
<> 144:ef7eb2e8f9f7 53 static void overflow_handler(void)
<> 144:ef7eb2e8f9f7 54 {
<> 144:ef7eb2e8f9f7 55 MXC_RTCTMR->flags = MXC_F_RTC_FLAGS_OVERFLOW;
<> 144:ef7eb2e8f9f7 56 MXC_PWRSEQ->flags = MXC_F_PWRSEQ_MSK_FLAGS_RTC_ROLLOVER;
<> 144:ef7eb2e8f9f7 57 overflow_cnt++;
<> 144:ef7eb2e8f9f7 58 }
<> 144:ef7eb2e8f9f7 59
<> 144:ef7eb2e8f9f7 60 //******************************************************************************
<> 144:ef7eb2e8f9f7 61 void rtc_init(void)
<> 144:ef7eb2e8f9f7 62 {
<> 144:ef7eb2e8f9f7 63 if (rtc_inited) {
<> 144:ef7eb2e8f9f7 64 return;
<> 144:ef7eb2e8f9f7 65 }
<> 144:ef7eb2e8f9f7 66 rtc_inited = 1;
<> 144:ef7eb2e8f9f7 67
<> 144:ef7eb2e8f9f7 68 overflow_cnt = 0;
<> 144:ef7eb2e8f9f7 69
<> 144:ef7eb2e8f9f7 70 // Enable the clock to the synchronizer
<> 144:ef7eb2e8f9f7 71 MXC_CLKMAN->clk_ctrl_13_rtc_int_sync = MXC_E_CLKMAN_CLK_SCALE_ENABLED;
<> 144:ef7eb2e8f9f7 72
<> 144:ef7eb2e8f9f7 73 // Enable the clock to the RTC
<> 144:ef7eb2e8f9f7 74 MXC_PWRSEQ->reg0 |= MXC_F_PWRSEQ_REG0_PWR_RTCEN_RUN;
<> 144:ef7eb2e8f9f7 75
<> 144:ef7eb2e8f9f7 76 // Prepare interrupt handlers
Anna Bridge 186:707f6e361f3e 77 #ifdef DEVICE_LPTICKER
<> 144:ef7eb2e8f9f7 78 NVIC_SetVector(RTC0_IRQn, (uint32_t)lp_ticker_irq_handler);
<> 144:ef7eb2e8f9f7 79 NVIC_EnableIRQ(RTC0_IRQn);
Anna Bridge 186:707f6e361f3e 80 #endif
<> 144:ef7eb2e8f9f7 81 NVIC_SetVector(RTC3_IRQn, (uint32_t)overflow_handler);
<> 144:ef7eb2e8f9f7 82 NVIC_EnableIRQ(RTC3_IRQn);
<> 144:ef7eb2e8f9f7 83
<> 144:ef7eb2e8f9f7 84 // Enable wakeup on RTC rollover
<> 144:ef7eb2e8f9f7 85 MXC_PWRSEQ->msk_flags &= ~MXC_F_PWRSEQ_MSK_FLAGS_RTC_ROLLOVER;
<> 144:ef7eb2e8f9f7 86
<> 144:ef7eb2e8f9f7 87 /* RTC registers are only reset on a power cycle. Do not reconfigure the RTC
<> 144:ef7eb2e8f9f7 88 * if it is already running.
<> 144:ef7eb2e8f9f7 89 */
<> 144:ef7eb2e8f9f7 90 if (!(MXC_RTCTMR->ctrl & MXC_F_RTC_CTRL_ENABLE)) {
<> 144:ef7eb2e8f9f7 91 // Set the clock divider
<> 144:ef7eb2e8f9f7 92 MXC_RTCTMR->prescale = PRESCALE_VAL;
<> 144:ef7eb2e8f9f7 93
<> 144:ef7eb2e8f9f7 94 // Enable the overflow interrupt
<> 144:ef7eb2e8f9f7 95 MXC_RTCTMR->inten |= MXC_F_RTC_FLAGS_OVERFLOW;
<> 144:ef7eb2e8f9f7 96
<> 144:ef7eb2e8f9f7 97 // Restart the timer from 0
<> 144:ef7eb2e8f9f7 98 MXC_RTCTMR->timer = 0;
<> 144:ef7eb2e8f9f7 99
<> 144:ef7eb2e8f9f7 100 // Enable the RTC
<> 144:ef7eb2e8f9f7 101 MXC_RTCTMR->ctrl |= MXC_F_RTC_CTRL_ENABLE;
<> 144:ef7eb2e8f9f7 102 }
<> 144:ef7eb2e8f9f7 103 }
<> 144:ef7eb2e8f9f7 104
<> 144:ef7eb2e8f9f7 105 //******************************************************************************
<> 144:ef7eb2e8f9f7 106 void lp_ticker_init(void)
<> 144:ef7eb2e8f9f7 107 {
<> 144:ef7eb2e8f9f7 108 rtc_init();
<> 144:ef7eb2e8f9f7 109 }
<> 144:ef7eb2e8f9f7 110
<> 144:ef7eb2e8f9f7 111 //******************************************************************************
<> 144:ef7eb2e8f9f7 112 void rtc_free(void)
<> 144:ef7eb2e8f9f7 113 {
<> 144:ef7eb2e8f9f7 114 if (MXC_RTCTMR->ctrl & MXC_F_RTC_CTRL_ENABLE) {
<> 144:ef7eb2e8f9f7 115 // Clear and disable RTC
<> 144:ef7eb2e8f9f7 116 MXC_RTCTMR->ctrl |= MXC_F_RTC_CTRL_CLEAR;
<> 144:ef7eb2e8f9f7 117 MXC_RTCTMR->ctrl &= ~MXC_F_RTC_CTRL_ENABLE;
<> 144:ef7eb2e8f9f7 118
<> 144:ef7eb2e8f9f7 119 // Wait for pending transactions
<> 144:ef7eb2e8f9f7 120 while(MXC_RTCTMR->ctrl & MXC_F_RTC_CTRL_PENDING);
<> 144:ef7eb2e8f9f7 121 }
<> 144:ef7eb2e8f9f7 122
<> 144:ef7eb2e8f9f7 123 // Disable the clock to the RTC
<> 144:ef7eb2e8f9f7 124 MXC_PWRSEQ->reg0 &= ~(MXC_F_PWRSEQ_REG0_PWR_RTCEN_RUN | MXC_F_PWRSEQ_REG0_PWR_RTCEN_SLP);
<> 144:ef7eb2e8f9f7 125
<> 144:ef7eb2e8f9f7 126 // Disable the clock to the synchronizer
<> 144:ef7eb2e8f9f7 127 MXC_CLKMAN->clk_ctrl_13_rtc_int_sync = MXC_E_CLKMAN_CLK_SCALE_DISABLED;
<> 144:ef7eb2e8f9f7 128 }
<> 144:ef7eb2e8f9f7 129
<> 144:ef7eb2e8f9f7 130 //******************************************************************************
<> 144:ef7eb2e8f9f7 131 int rtc_isenabled(void)
<> 144:ef7eb2e8f9f7 132 {
<> 144:ef7eb2e8f9f7 133 return (MXC_RTCTMR->ctrl & MXC_F_RTC_CTRL_ENABLE);
<> 144:ef7eb2e8f9f7 134 }
<> 144:ef7eb2e8f9f7 135
<> 144:ef7eb2e8f9f7 136 //******************************************************************************
<> 144:ef7eb2e8f9f7 137 time_t rtc_read(void)
<> 144:ef7eb2e8f9f7 138 {
<> 144:ef7eb2e8f9f7 139 uint32_t ovf_cnt_1, ovf_cnt_2, timer_cnt;
<> 144:ef7eb2e8f9f7 140 uint32_t ovf1, ovf2;
<> 144:ef7eb2e8f9f7 141
<> 144:ef7eb2e8f9f7 142 // Ensure coherency between overflow_cnt and timer
<> 144:ef7eb2e8f9f7 143 do {
<> 144:ef7eb2e8f9f7 144 ovf_cnt_1 = overflow_cnt;
<> 144:ef7eb2e8f9f7 145 ovf1 = MXC_RTCTMR->flags & MXC_F_RTC_FLAGS_OVERFLOW;
<> 144:ef7eb2e8f9f7 146 timer_cnt = MXC_RTCTMR->timer;
<> 144:ef7eb2e8f9f7 147 ovf2 = MXC_RTCTMR->flags & MXC_F_RTC_FLAGS_OVERFLOW;
<> 144:ef7eb2e8f9f7 148 ovf_cnt_2 = overflow_cnt;
<> 144:ef7eb2e8f9f7 149 } while ((ovf_cnt_1 != ovf_cnt_2) || (ovf1 != ovf2));
<> 144:ef7eb2e8f9f7 150
<> 144:ef7eb2e8f9f7 151 // Account for an unserviced interrupt
<> 144:ef7eb2e8f9f7 152 if (ovf1) {
<> 144:ef7eb2e8f9f7 153 ovf_cnt_1++;
<> 144:ef7eb2e8f9f7 154 }
<> 144:ef7eb2e8f9f7 155
<> 144:ef7eb2e8f9f7 156 return (timer_cnt >> SHIFT_AMT) + (ovf_cnt_1 << (32 - SHIFT_AMT));
<> 144:ef7eb2e8f9f7 157 }
<> 144:ef7eb2e8f9f7 158
<> 144:ef7eb2e8f9f7 159 //******************************************************************************
<> 144:ef7eb2e8f9f7 160 static uint64_t rtc_read64(void)
<> 144:ef7eb2e8f9f7 161 {
<> 144:ef7eb2e8f9f7 162 uint32_t ovf_cnt_1, ovf_cnt_2, timer_cnt;
<> 144:ef7eb2e8f9f7 163 uint32_t ovf1, ovf2;
<> 144:ef7eb2e8f9f7 164 uint64_t current_us;
<> 144:ef7eb2e8f9f7 165
<> 144:ef7eb2e8f9f7 166 // Ensure coherency between overflow_cnt and timer
<> 144:ef7eb2e8f9f7 167 do {
<> 144:ef7eb2e8f9f7 168 ovf_cnt_1 = overflow_cnt;
<> 144:ef7eb2e8f9f7 169 ovf1 = MXC_RTCTMR->flags & MXC_F_RTC_FLAGS_OVERFLOW;
<> 144:ef7eb2e8f9f7 170 timer_cnt = MXC_RTCTMR->timer;
<> 144:ef7eb2e8f9f7 171 ovf2 = MXC_RTCTMR->flags & MXC_F_RTC_FLAGS_OVERFLOW;
<> 144:ef7eb2e8f9f7 172 ovf_cnt_2 = overflow_cnt;
<> 144:ef7eb2e8f9f7 173 } while ((ovf_cnt_1 != ovf_cnt_2) || (ovf1 != ovf2));
<> 144:ef7eb2e8f9f7 174
<> 144:ef7eb2e8f9f7 175 // Account for an unserviced interrupt
<> 144:ef7eb2e8f9f7 176 if (ovf1) {
<> 144:ef7eb2e8f9f7 177 ovf_cnt_1++;
<> 144:ef7eb2e8f9f7 178 }
<> 144:ef7eb2e8f9f7 179
<> 144:ef7eb2e8f9f7 180 current_us = (((uint64_t)timer_cnt * 1000000) >> SHIFT_AMT) + (((uint64_t)ovf_cnt_1 * 1000000) << (32 - SHIFT_AMT));
<> 144:ef7eb2e8f9f7 181
<> 144:ef7eb2e8f9f7 182 return current_us;
<> 144:ef7eb2e8f9f7 183 }
<> 144:ef7eb2e8f9f7 184
<> 144:ef7eb2e8f9f7 185 //******************************************************************************
<> 144:ef7eb2e8f9f7 186 void rtc_write(time_t t)
<> 144:ef7eb2e8f9f7 187 {
<> 144:ef7eb2e8f9f7 188 MXC_RTCTMR->ctrl &= ~MXC_F_RTC_CTRL_ENABLE; // disable the timer while updating
<> 144:ef7eb2e8f9f7 189 MXC_RTCTMR->timer = t << SHIFT_AMT;
<> 144:ef7eb2e8f9f7 190 overflow_cnt = t >> (32 - SHIFT_AMT);
<> 144:ef7eb2e8f9f7 191 MXC_RTCTMR->ctrl |= MXC_F_RTC_CTRL_ENABLE; // enable the timer while updating
<> 144:ef7eb2e8f9f7 192 }
<> 144:ef7eb2e8f9f7 193
<> 144:ef7eb2e8f9f7 194 //******************************************************************************
<> 144:ef7eb2e8f9f7 195 void lp_ticker_set_interrupt(timestamp_t timestamp)
<> 144:ef7eb2e8f9f7 196 {
<> 144:ef7eb2e8f9f7 197 uint32_t comp_value;
<> 144:ef7eb2e8f9f7 198 uint64_t curr_ts64;
<> 144:ef7eb2e8f9f7 199 uint64_t ts64;
<> 144:ef7eb2e8f9f7 200
<> 144:ef7eb2e8f9f7 201 // Note: interrupts are disabled before this function is called.
<> 144:ef7eb2e8f9f7 202
<> 144:ef7eb2e8f9f7 203 // Disable the alarm while it is prepared
<> 144:ef7eb2e8f9f7 204 MXC_RTCTMR->inten &= ~MXC_F_RTC_INTEN_COMP0;
<> 144:ef7eb2e8f9f7 205
<> 144:ef7eb2e8f9f7 206 curr_ts64 = rtc_read64();
<> 144:ef7eb2e8f9f7 207 ts64 = (uint64_t)timestamp | (curr_ts64 & 0xFFFFFFFF00000000ULL);
<> 144:ef7eb2e8f9f7 208
<> 144:ef7eb2e8f9f7 209 // If this event is older than a recent window, it must be in the future
<> 144:ef7eb2e8f9f7 210 if ((ts64 < (curr_ts64 - WINDOW)) && ((curr_ts64 - WINDOW) < curr_ts64)) {
<> 144:ef7eb2e8f9f7 211 ts64 += 0x100000000ULL;
<> 144:ef7eb2e8f9f7 212 }
<> 144:ef7eb2e8f9f7 213
<> 144:ef7eb2e8f9f7 214 uint32_t timer = MXC_RTCTMR->timer;
<> 144:ef7eb2e8f9f7 215 if (ts64 <= curr_ts64) {
<> 144:ef7eb2e8f9f7 216 // This event has already occurred. Set the alarm to expire immediately.
<> 144:ef7eb2e8f9f7 217 comp_value = timer + 1;
<> 144:ef7eb2e8f9f7 218 } else {
<> 144:ef7eb2e8f9f7 219 comp_value = (ts64 << SHIFT_AMT) / 1000000;
<> 144:ef7eb2e8f9f7 220 }
<> 144:ef7eb2e8f9f7 221
<> 144:ef7eb2e8f9f7 222 // Ensure that the compare value is far enough in the future to guarantee the interrupt occurs.
<> 144:ef7eb2e8f9f7 223 if ((comp_value < (timer + 2)) && (comp_value > (timer - 10))) {
<> 144:ef7eb2e8f9f7 224 comp_value = timer + 2;
<> 144:ef7eb2e8f9f7 225 }
<> 144:ef7eb2e8f9f7 226
<> 144:ef7eb2e8f9f7 227 MXC_RTCTMR->comp[0] = comp_value;
<> 144:ef7eb2e8f9f7 228 MXC_RTCTMR->flags = MXC_F_RTC_FLAGS_COMP0; // clear interrupt
<> 144:ef7eb2e8f9f7 229 MXC_RTCTMR->inten |= MXC_F_RTC_INTEN_COMP0; // enable the interrupt
<> 144:ef7eb2e8f9f7 230
<> 144:ef7eb2e8f9f7 231 // Enable wakeup from RTC
<> 144:ef7eb2e8f9f7 232 MXC_PWRSEQ->msk_flags &= ~MXC_F_PWRSEQ_MSK_FLAGS_RTC_CMPR0;
<> 144:ef7eb2e8f9f7 233 }
<> 144:ef7eb2e8f9f7 234
AnnaBridge 174:b96e65c34a4d 235 void lp_ticker_fire_interrupt(void)
AnnaBridge 174:b96e65c34a4d 236 {
AnnaBridge 174:b96e65c34a4d 237 NVIC_SetPendingIRQ(RTC0_IRQn);
AnnaBridge 174:b96e65c34a4d 238 }
AnnaBridge 174:b96e65c34a4d 239
<> 144:ef7eb2e8f9f7 240 //******************************************************************************
Anna Bridge 186:707f6e361f3e 241 void lp_ticker_disable_interrupt(void)
<> 144:ef7eb2e8f9f7 242 {
<> 144:ef7eb2e8f9f7 243 MXC_RTCTMR->inten &= ~MXC_F_RTC_INTEN_COMP0;
<> 144:ef7eb2e8f9f7 244 }
<> 144:ef7eb2e8f9f7 245
<> 144:ef7eb2e8f9f7 246 //******************************************************************************
Anna Bridge 186:707f6e361f3e 247 void lp_ticker_clear_interrupt(void)
<> 144:ef7eb2e8f9f7 248 {
<> 144:ef7eb2e8f9f7 249 MXC_RTCTMR->flags = MXC_F_RTC_FLAGS_ASYNC_CLR_FLAGS;
<> 144:ef7eb2e8f9f7 250 MXC_PWRSEQ->flags = MXC_F_PWRSEQ_MSK_FLAGS_RTC_CMPR0;
<> 144:ef7eb2e8f9f7 251 }
<> 144:ef7eb2e8f9f7 252
<> 144:ef7eb2e8f9f7 253 //******************************************************************************
Anna Bridge 186:707f6e361f3e 254 uint32_t lp_ticker_read(void)
<> 144:ef7eb2e8f9f7 255 {
<> 144:ef7eb2e8f9f7 256 return rtc_read64();
<> 144:ef7eb2e8f9f7 257 }