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targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_eth.h@161:2cc1468da177, 2017-03-30 (annotated)

Committer:
<>
Date:
Thu Mar 30 13:45:57 2017 +0100
Revision:
161:2cc1468da177
Parent:
157:ff67d9f36b67
Child:
168:9672193075cf
This updates the lib to the mbed lib v139

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f7xx_hal_eth.h
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 161:2cc1468da177 5 * @version V1.2.0
<> 161:2cc1468da177 6 * @date 30-December-2016
<> 144:ef7eb2e8f9f7 7 * @brief Header file of ETH HAL module.
<> 144:ef7eb2e8f9f7 8 ******************************************************************************
<> 144:ef7eb2e8f9f7 9 * @attention
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 12 *
<> 144:ef7eb2e8f9f7 13 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 14 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 15 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 16 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 18 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 19 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 21 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 22 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 23 *
<> 144:ef7eb2e8f9f7 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 34 *
<> 144:ef7eb2e8f9f7 35 ******************************************************************************
<> 144:ef7eb2e8f9f7 36 */
<> 144:ef7eb2e8f9f7 37
<> 144:ef7eb2e8f9f7 38 /* Define to prevent recursive inclusion -------------------------------------*/
<> 144:ef7eb2e8f9f7 39 #ifndef __STM32F7xx_HAL_ETH_H
<> 144:ef7eb2e8f9f7 40 #define __STM32F7xx_HAL_ETH_H
<> 144:ef7eb2e8f9f7 41
<> 144:ef7eb2e8f9f7 42 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 43 extern "C" {
<> 144:ef7eb2e8f9f7 44 #endif
<> 144:ef7eb2e8f9f7 45
<> 144:ef7eb2e8f9f7 46 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 47 #include "stm32f7xx_hal_def.h"
<> 144:ef7eb2e8f9f7 48
<> 161:2cc1468da177 49 #if defined (ETH)
<> 161:2cc1468da177 50
<> 144:ef7eb2e8f9f7 51 /** @addtogroup STM32F7xx_HAL_Driver
<> 144:ef7eb2e8f9f7 52 * @{
<> 144:ef7eb2e8f9f7 53 */
<> 144:ef7eb2e8f9f7 54
<> 144:ef7eb2e8f9f7 55 /** @addtogroup ETH
<> 144:ef7eb2e8f9f7 56 * @{
<> 144:ef7eb2e8f9f7 57 */
<> 144:ef7eb2e8f9f7 58
<> 144:ef7eb2e8f9f7 59 /** @addtogroup ETH_Private_Macros
<> 144:ef7eb2e8f9f7 60 * @{
<> 144:ef7eb2e8f9f7 61 */
<> 144:ef7eb2e8f9f7 62 #define IS_ETH_PHY_ADDRESS(ADDRESS) ((ADDRESS) <= 0x20)
<> 144:ef7eb2e8f9f7 63 #define IS_ETH_AUTONEGOTIATION(CMD) (((CMD) == ETH_AUTONEGOTIATION_ENABLE) || \
<> 144:ef7eb2e8f9f7 64 ((CMD) == ETH_AUTONEGOTIATION_DISABLE))
<> 144:ef7eb2e8f9f7 65 #define IS_ETH_SPEED(SPEED) (((SPEED) == ETH_SPEED_10M) || \
<> 144:ef7eb2e8f9f7 66 ((SPEED) == ETH_SPEED_100M))
<> 144:ef7eb2e8f9f7 67 #define IS_ETH_DUPLEX_MODE(MODE) (((MODE) == ETH_MODE_FULLDUPLEX) || \
<> 144:ef7eb2e8f9f7 68 ((MODE) == ETH_MODE_HALFDUPLEX))
<> 144:ef7eb2e8f9f7 69 #define IS_ETH_RX_MODE(MODE) (((MODE) == ETH_RXPOLLING_MODE) || \
<> 144:ef7eb2e8f9f7 70 ((MODE) == ETH_RXINTERRUPT_MODE))
<> 144:ef7eb2e8f9f7 71 #define IS_ETH_CHECKSUM_MODE(MODE) (((MODE) == ETH_CHECKSUM_BY_HARDWARE) || \
<> 144:ef7eb2e8f9f7 72 ((MODE) == ETH_CHECKSUM_BY_SOFTWARE))
<> 144:ef7eb2e8f9f7 73 #define IS_ETH_MEDIA_INTERFACE(MODE) (((MODE) == ETH_MEDIA_INTERFACE_MII) || \
<> 144:ef7eb2e8f9f7 74 ((MODE) == ETH_MEDIA_INTERFACE_RMII))
<> 144:ef7eb2e8f9f7 75 #define IS_ETH_WATCHDOG(CMD) (((CMD) == ETH_WATCHDOG_ENABLE) || \
<> 144:ef7eb2e8f9f7 76 ((CMD) == ETH_WATCHDOG_DISABLE))
<> 144:ef7eb2e8f9f7 77 #define IS_ETH_JABBER(CMD) (((CMD) == ETH_JABBER_ENABLE) || \
<> 144:ef7eb2e8f9f7 78 ((CMD) == ETH_JABBER_DISABLE))
<> 144:ef7eb2e8f9f7 79 #define IS_ETH_INTER_FRAME_GAP(GAP) (((GAP) == ETH_INTERFRAMEGAP_96BIT) || \
<> 144:ef7eb2e8f9f7 80 ((GAP) == ETH_INTERFRAMEGAP_88BIT) || \
<> 144:ef7eb2e8f9f7 81 ((GAP) == ETH_INTERFRAMEGAP_80BIT) || \
<> 144:ef7eb2e8f9f7 82 ((GAP) == ETH_INTERFRAMEGAP_72BIT) || \
<> 144:ef7eb2e8f9f7 83 ((GAP) == ETH_INTERFRAMEGAP_64BIT) || \
<> 144:ef7eb2e8f9f7 84 ((GAP) == ETH_INTERFRAMEGAP_56BIT) || \
<> 144:ef7eb2e8f9f7 85 ((GAP) == ETH_INTERFRAMEGAP_48BIT) || \
<> 144:ef7eb2e8f9f7 86 ((GAP) == ETH_INTERFRAMEGAP_40BIT))
<> 144:ef7eb2e8f9f7 87 #define IS_ETH_CARRIER_SENSE(CMD) (((CMD) == ETH_CARRIERSENCE_ENABLE) || \
<> 144:ef7eb2e8f9f7 88 ((CMD) == ETH_CARRIERSENCE_DISABLE))
<> 144:ef7eb2e8f9f7 89 #define IS_ETH_RECEIVE_OWN(CMD) (((CMD) == ETH_RECEIVEOWN_ENABLE) || \
<> 144:ef7eb2e8f9f7 90 ((CMD) == ETH_RECEIVEOWN_DISABLE))
<> 144:ef7eb2e8f9f7 91 #define IS_ETH_LOOPBACK_MODE(CMD) (((CMD) == ETH_LOOPBACKMODE_ENABLE) || \
<> 144:ef7eb2e8f9f7 92 ((CMD) == ETH_LOOPBACKMODE_DISABLE))
<> 144:ef7eb2e8f9f7 93 #define IS_ETH_CHECKSUM_OFFLOAD(CMD) (((CMD) == ETH_CHECKSUMOFFLAOD_ENABLE) || \
<> 144:ef7eb2e8f9f7 94 ((CMD) == ETH_CHECKSUMOFFLAOD_DISABLE))
<> 144:ef7eb2e8f9f7 95 #define IS_ETH_RETRY_TRANSMISSION(CMD) (((CMD) == ETH_RETRYTRANSMISSION_ENABLE) || \
<> 144:ef7eb2e8f9f7 96 ((CMD) == ETH_RETRYTRANSMISSION_DISABLE))
<> 144:ef7eb2e8f9f7 97 #define IS_ETH_AUTOMATIC_PADCRC_STRIP(CMD) (((CMD) == ETH_AUTOMATICPADCRCSTRIP_ENABLE) || \
<> 144:ef7eb2e8f9f7 98 ((CMD) == ETH_AUTOMATICPADCRCSTRIP_DISABLE))
<> 144:ef7eb2e8f9f7 99 #define IS_ETH_BACKOFF_LIMIT(LIMIT) (((LIMIT) == ETH_BACKOFFLIMIT_10) || \
<> 144:ef7eb2e8f9f7 100 ((LIMIT) == ETH_BACKOFFLIMIT_8) || \
<> 144:ef7eb2e8f9f7 101 ((LIMIT) == ETH_BACKOFFLIMIT_4) || \
<> 144:ef7eb2e8f9f7 102 ((LIMIT) == ETH_BACKOFFLIMIT_1))
<> 144:ef7eb2e8f9f7 103 #define IS_ETH_DEFERRAL_CHECK(CMD) (((CMD) == ETH_DEFFERRALCHECK_ENABLE) || \
<> 144:ef7eb2e8f9f7 104 ((CMD) == ETH_DEFFERRALCHECK_DISABLE))
<> 144:ef7eb2e8f9f7 105 #define IS_ETH_RECEIVE_ALL(CMD) (((CMD) == ETH_RECEIVEALL_ENABLE) || \
<> 144:ef7eb2e8f9f7 106 ((CMD) == ETH_RECEIVEAll_DISABLE))
<> 144:ef7eb2e8f9f7 107 #define IS_ETH_SOURCE_ADDR_FILTER(CMD) (((CMD) == ETH_SOURCEADDRFILTER_NORMAL_ENABLE) || \
<> 144:ef7eb2e8f9f7 108 ((CMD) == ETH_SOURCEADDRFILTER_INVERSE_ENABLE) || \
<> 144:ef7eb2e8f9f7 109 ((CMD) == ETH_SOURCEADDRFILTER_DISABLE))
<> 144:ef7eb2e8f9f7 110 #define IS_ETH_CONTROL_FRAMES(PASS) (((PASS) == ETH_PASSCONTROLFRAMES_BLOCKALL) || \
<> 144:ef7eb2e8f9f7 111 ((PASS) == ETH_PASSCONTROLFRAMES_FORWARDALL) || \
<> 144:ef7eb2e8f9f7 112 ((PASS) == ETH_PASSCONTROLFRAMES_FORWARDPASSEDADDRFILTER))
<> 144:ef7eb2e8f9f7 113 #define IS_ETH_BROADCAST_FRAMES_RECEPTION(CMD) (((CMD) == ETH_BROADCASTFRAMESRECEPTION_ENABLE) || \
<> 144:ef7eb2e8f9f7 114 ((CMD) == ETH_BROADCASTFRAMESRECEPTION_DISABLE))
<> 144:ef7eb2e8f9f7 115 #define IS_ETH_DESTINATION_ADDR_FILTER(FILTER) (((FILTER) == ETH_DESTINATIONADDRFILTER_NORMAL) || \
<> 144:ef7eb2e8f9f7 116 ((FILTER) == ETH_DESTINATIONADDRFILTER_INVERSE))
<> 144:ef7eb2e8f9f7 117 #define IS_ETH_PROMISCUOUS_MODE(CMD) (((CMD) == ETH_PROMISCUOUS_MODE_ENABLE) || \
<> 144:ef7eb2e8f9f7 118 ((CMD) == ETH_PROMISCUOUS_MODE_DISABLE))
<> 144:ef7eb2e8f9f7 119 #define IS_ETH_MULTICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_MULTICASTFRAMESFILTER_PERFECTHASHTABLE) || \
<> 144:ef7eb2e8f9f7 120 ((FILTER) == ETH_MULTICASTFRAMESFILTER_HASHTABLE) || \
<> 144:ef7eb2e8f9f7 121 ((FILTER) == ETH_MULTICASTFRAMESFILTER_PERFECT) || \
<> 144:ef7eb2e8f9f7 122 ((FILTER) == ETH_MULTICASTFRAMESFILTER_NONE))
<> 144:ef7eb2e8f9f7 123 #define IS_ETH_UNICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_UNICASTFRAMESFILTER_PERFECTHASHTABLE) || \
<> 144:ef7eb2e8f9f7 124 ((FILTER) == ETH_UNICASTFRAMESFILTER_HASHTABLE) || \
<> 144:ef7eb2e8f9f7 125 ((FILTER) == ETH_UNICASTFRAMESFILTER_PERFECT))
<> 144:ef7eb2e8f9f7 126 #define IS_ETH_PAUSE_TIME(TIME) ((TIME) <= 0xFFFF)
<> 144:ef7eb2e8f9f7 127 #define IS_ETH_ZEROQUANTA_PAUSE(CMD) (((CMD) == ETH_ZEROQUANTAPAUSE_ENABLE) || \
<> 144:ef7eb2e8f9f7 128 ((CMD) == ETH_ZEROQUANTAPAUSE_DISABLE))
<> 144:ef7eb2e8f9f7 129 #define IS_ETH_PAUSE_LOW_THRESHOLD(THRESHOLD) (((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS4) || \
<> 144:ef7eb2e8f9f7 130 ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS28) || \
<> 144:ef7eb2e8f9f7 131 ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS144) || \
<> 144:ef7eb2e8f9f7 132 ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS256))
<> 144:ef7eb2e8f9f7 133 #define IS_ETH_UNICAST_PAUSE_FRAME_DETECT(CMD) (((CMD) == ETH_UNICASTPAUSEFRAMEDETECT_ENABLE) || \
<> 144:ef7eb2e8f9f7 134 ((CMD) == ETH_UNICASTPAUSEFRAMEDETECT_DISABLE))
<> 144:ef7eb2e8f9f7 135 #define IS_ETH_RECEIVE_FLOWCONTROL(CMD) (((CMD) == ETH_RECEIVEFLOWCONTROL_ENABLE) || \
<> 144:ef7eb2e8f9f7 136 ((CMD) == ETH_RECEIVEFLOWCONTROL_DISABLE))
<> 144:ef7eb2e8f9f7 137 #define IS_ETH_TRANSMIT_FLOWCONTROL(CMD) (((CMD) == ETH_TRANSMITFLOWCONTROL_ENABLE) || \
<> 144:ef7eb2e8f9f7 138 ((CMD) == ETH_TRANSMITFLOWCONTROL_DISABLE))
<> 144:ef7eb2e8f9f7 139 #define IS_ETH_VLAN_TAG_COMPARISON(COMPARISON) (((COMPARISON) == ETH_VLANTAGCOMPARISON_12BIT) || \
<> 144:ef7eb2e8f9f7 140 ((COMPARISON) == ETH_VLANTAGCOMPARISON_16BIT))
<> 144:ef7eb2e8f9f7 141 #define IS_ETH_VLAN_TAG_IDENTIFIER(IDENTIFIER) ((IDENTIFIER) <= 0xFFFF)
<> 144:ef7eb2e8f9f7 142 #define IS_ETH_MAC_ADDRESS0123(ADDRESS) (((ADDRESS) == ETH_MAC_ADDRESS0) || \
<> 144:ef7eb2e8f9f7 143 ((ADDRESS) == ETH_MAC_ADDRESS1) || \
<> 144:ef7eb2e8f9f7 144 ((ADDRESS) == ETH_MAC_ADDRESS2) || \
<> 144:ef7eb2e8f9f7 145 ((ADDRESS) == ETH_MAC_ADDRESS3))
<> 144:ef7eb2e8f9f7 146 #define IS_ETH_MAC_ADDRESS123(ADDRESS) (((ADDRESS) == ETH_MAC_ADDRESS1) || \
<> 144:ef7eb2e8f9f7 147 ((ADDRESS) == ETH_MAC_ADDRESS2) || \
<> 144:ef7eb2e8f9f7 148 ((ADDRESS) == ETH_MAC_ADDRESS3))
<> 144:ef7eb2e8f9f7 149 #define IS_ETH_MAC_ADDRESS_FILTER(FILTER) (((FILTER) == ETH_MAC_ADDRESSFILTER_SA) || \
<> 144:ef7eb2e8f9f7 150 ((FILTER) == ETH_MAC_ADDRESSFILTER_DA))
<> 144:ef7eb2e8f9f7 151 #define IS_ETH_MAC_ADDRESS_MASK(MASK) (((MASK) == ETH_MAC_ADDRESSMASK_BYTE6) || \
<> 144:ef7eb2e8f9f7 152 ((MASK) == ETH_MAC_ADDRESSMASK_BYTE5) || \
<> 144:ef7eb2e8f9f7 153 ((MASK) == ETH_MAC_ADDRESSMASK_BYTE4) || \
<> 144:ef7eb2e8f9f7 154 ((MASK) == ETH_MAC_ADDRESSMASK_BYTE3) || \
<> 144:ef7eb2e8f9f7 155 ((MASK) == ETH_MAC_ADDRESSMASK_BYTE2) || \
<> 144:ef7eb2e8f9f7 156 ((MASK) == ETH_MAC_ADDRESSMASK_BYTE1))
<> 144:ef7eb2e8f9f7 157 #define IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(CMD) (((CMD) == ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE) || \
<> 144:ef7eb2e8f9f7 158 ((CMD) == ETH_DROPTCPIPCHECKSUMERRORFRAME_DISABLE))
<> 144:ef7eb2e8f9f7 159 #define IS_ETH_RECEIVE_STORE_FORWARD(CMD) (((CMD) == ETH_RECEIVESTOREFORWARD_ENABLE) || \
<> 144:ef7eb2e8f9f7 160 ((CMD) == ETH_RECEIVESTOREFORWARD_DISABLE))
<> 144:ef7eb2e8f9f7 161 #define IS_ETH_FLUSH_RECEIVE_FRAME(CMD) (((CMD) == ETH_FLUSHRECEIVEDFRAME_ENABLE) || \
<> 144:ef7eb2e8f9f7 162 ((CMD) == ETH_FLUSHRECEIVEDFRAME_DISABLE))
<> 144:ef7eb2e8f9f7 163 #define IS_ETH_TRANSMIT_STORE_FORWARD(CMD) (((CMD) == ETH_TRANSMITSTOREFORWARD_ENABLE) || \
<> 144:ef7eb2e8f9f7 164 ((CMD) == ETH_TRANSMITSTOREFORWARD_DISABLE))
<> 144:ef7eb2e8f9f7 165 #define IS_ETH_TRANSMIT_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_64BYTES) || \
<> 144:ef7eb2e8f9f7 166 ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_128BYTES) || \
<> 144:ef7eb2e8f9f7 167 ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_192BYTES) || \
<> 144:ef7eb2e8f9f7 168 ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_256BYTES) || \
<> 144:ef7eb2e8f9f7 169 ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_40BYTES) || \
<> 144:ef7eb2e8f9f7 170 ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_32BYTES) || \
<> 144:ef7eb2e8f9f7 171 ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_24BYTES) || \
<> 144:ef7eb2e8f9f7 172 ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_16BYTES))
<> 144:ef7eb2e8f9f7 173 #define IS_ETH_FORWARD_ERROR_FRAMES(CMD) (((CMD) == ETH_FORWARDERRORFRAMES_ENABLE) || \
<> 144:ef7eb2e8f9f7 174 ((CMD) == ETH_FORWARDERRORFRAMES_DISABLE))
<> 144:ef7eb2e8f9f7 175 #define IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES(CMD) (((CMD) == ETH_FORWARDUNDERSIZEDGOODFRAMES_ENABLE) || \
<> 144:ef7eb2e8f9f7 176 ((CMD) == ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE))
<> 144:ef7eb2e8f9f7 177 #define IS_ETH_RECEIVE_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES) || \
<> 144:ef7eb2e8f9f7 178 ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_32BYTES) || \
<> 144:ef7eb2e8f9f7 179 ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_96BYTES) || \
<> 144:ef7eb2e8f9f7 180 ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_128BYTES))
<> 144:ef7eb2e8f9f7 181 #define IS_ETH_SECOND_FRAME_OPERATE(CMD) (((CMD) == ETH_SECONDFRAMEOPERARTE_ENABLE) || \
<> 144:ef7eb2e8f9f7 182 ((CMD) == ETH_SECONDFRAMEOPERARTE_DISABLE))
<> 144:ef7eb2e8f9f7 183 #define IS_ETH_ADDRESS_ALIGNED_BEATS(CMD) (((CMD) == ETH_ADDRESSALIGNEDBEATS_ENABLE) || \
<> 144:ef7eb2e8f9f7 184 ((CMD) == ETH_ADDRESSALIGNEDBEATS_DISABLE))
<> 144:ef7eb2e8f9f7 185 #define IS_ETH_FIXED_BURST(CMD) (((CMD) == ETH_FIXEDBURST_ENABLE) || \
<> 144:ef7eb2e8f9f7 186 ((CMD) == ETH_FIXEDBURST_DISABLE))
<> 144:ef7eb2e8f9f7 187 #define IS_ETH_RXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_RXDMABURSTLENGTH_1BEAT) || \
<> 144:ef7eb2e8f9f7 188 ((LENGTH) == ETH_RXDMABURSTLENGTH_2BEAT) || \
<> 144:ef7eb2e8f9f7 189 ((LENGTH) == ETH_RXDMABURSTLENGTH_4BEAT) || \
<> 144:ef7eb2e8f9f7 190 ((LENGTH) == ETH_RXDMABURSTLENGTH_8BEAT) || \
<> 144:ef7eb2e8f9f7 191 ((LENGTH) == ETH_RXDMABURSTLENGTH_16BEAT) || \
<> 144:ef7eb2e8f9f7 192 ((LENGTH) == ETH_RXDMABURSTLENGTH_32BEAT) || \
<> 144:ef7eb2e8f9f7 193 ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_4BEAT) || \
<> 144:ef7eb2e8f9f7 194 ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_8BEAT) || \
<> 144:ef7eb2e8f9f7 195 ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_16BEAT) || \
<> 144:ef7eb2e8f9f7 196 ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_32BEAT) || \
<> 144:ef7eb2e8f9f7 197 ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_64BEAT) || \
<> 144:ef7eb2e8f9f7 198 ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_128BEAT))
<> 144:ef7eb2e8f9f7 199 #define IS_ETH_TXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_TXDMABURSTLENGTH_1BEAT) || \
<> 144:ef7eb2e8f9f7 200 ((LENGTH) == ETH_TXDMABURSTLENGTH_2BEAT) || \
<> 144:ef7eb2e8f9f7 201 ((LENGTH) == ETH_TXDMABURSTLENGTH_4BEAT) || \
<> 144:ef7eb2e8f9f7 202 ((LENGTH) == ETH_TXDMABURSTLENGTH_8BEAT) || \
<> 144:ef7eb2e8f9f7 203 ((LENGTH) == ETH_TXDMABURSTLENGTH_16BEAT) || \
<> 144:ef7eb2e8f9f7 204 ((LENGTH) == ETH_TXDMABURSTLENGTH_32BEAT) || \
<> 144:ef7eb2e8f9f7 205 ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_4BEAT) || \
<> 144:ef7eb2e8f9f7 206 ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_8BEAT) || \
<> 144:ef7eb2e8f9f7 207 ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_16BEAT) || \
<> 144:ef7eb2e8f9f7 208 ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_32BEAT) || \
<> 144:ef7eb2e8f9f7 209 ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_64BEAT) || \
<> 144:ef7eb2e8f9f7 210 ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_128BEAT))
<> 144:ef7eb2e8f9f7 211 #define IS_ETH_DMA_DESC_SKIP_LENGTH(LENGTH) ((LENGTH) <= 0x1F)
<> 144:ef7eb2e8f9f7 212 #define IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(RATIO) (((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1) || \
<> 144:ef7eb2e8f9f7 213 ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_2_1) || \
<> 144:ef7eb2e8f9f7 214 ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_3_1) || \
<> 144:ef7eb2e8f9f7 215 ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1) || \
<> 144:ef7eb2e8f9f7 216 ((RATIO) == ETH_DMAARBITRATION_RXPRIORTX))
<> 144:ef7eb2e8f9f7 217 #define IS_ETH_DMATXDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMATXDESC_OWN) || \
<> 144:ef7eb2e8f9f7 218 ((FLAG) == ETH_DMATXDESC_IC) || \
<> 144:ef7eb2e8f9f7 219 ((FLAG) == ETH_DMATXDESC_LS) || \
<> 144:ef7eb2e8f9f7 220 ((FLAG) == ETH_DMATXDESC_FS) || \
<> 144:ef7eb2e8f9f7 221 ((FLAG) == ETH_DMATXDESC_DC) || \
<> 144:ef7eb2e8f9f7 222 ((FLAG) == ETH_DMATXDESC_DP) || \
<> 144:ef7eb2e8f9f7 223 ((FLAG) == ETH_DMATXDESC_TTSE) || \
<> 144:ef7eb2e8f9f7 224 ((FLAG) == ETH_DMATXDESC_TER) || \
<> 144:ef7eb2e8f9f7 225 ((FLAG) == ETH_DMATXDESC_TCH) || \
<> 144:ef7eb2e8f9f7 226 ((FLAG) == ETH_DMATXDESC_TTSS) || \
<> 144:ef7eb2e8f9f7 227 ((FLAG) == ETH_DMATXDESC_IHE) || \
<> 144:ef7eb2e8f9f7 228 ((FLAG) == ETH_DMATXDESC_ES) || \
<> 144:ef7eb2e8f9f7 229 ((FLAG) == ETH_DMATXDESC_JT) || \
<> 144:ef7eb2e8f9f7 230 ((FLAG) == ETH_DMATXDESC_FF) || \
<> 144:ef7eb2e8f9f7 231 ((FLAG) == ETH_DMATXDESC_PCE) || \
<> 144:ef7eb2e8f9f7 232 ((FLAG) == ETH_DMATXDESC_LCA) || \
<> 144:ef7eb2e8f9f7 233 ((FLAG) == ETH_DMATXDESC_NC) || \
<> 144:ef7eb2e8f9f7 234 ((FLAG) == ETH_DMATXDESC_LCO) || \
<> 144:ef7eb2e8f9f7 235 ((FLAG) == ETH_DMATXDESC_EC) || \
<> 144:ef7eb2e8f9f7 236 ((FLAG) == ETH_DMATXDESC_VF) || \
<> 144:ef7eb2e8f9f7 237 ((FLAG) == ETH_DMATXDESC_CC) || \
<> 144:ef7eb2e8f9f7 238 ((FLAG) == ETH_DMATXDESC_ED) || \
<> 144:ef7eb2e8f9f7 239 ((FLAG) == ETH_DMATXDESC_UF) || \
<> 144:ef7eb2e8f9f7 240 ((FLAG) == ETH_DMATXDESC_DB))
<> 144:ef7eb2e8f9f7 241 #define IS_ETH_DMA_TXDESC_SEGMENT(SEGMENT) (((SEGMENT) == ETH_DMATXDESC_LASTSEGMENTS) || \
<> 144:ef7eb2e8f9f7 242 ((SEGMENT) == ETH_DMATXDESC_FIRSTSEGMENT))
<> 144:ef7eb2e8f9f7 243 #define IS_ETH_DMA_TXDESC_CHECKSUM(CHECKSUM) (((CHECKSUM) == ETH_DMATXDESC_CHECKSUMBYPASS) || \
<> 144:ef7eb2e8f9f7 244 ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMIPV4HEADER) || \
<> 144:ef7eb2e8f9f7 245 ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT) || \
<> 144:ef7eb2e8f9f7 246 ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL))
<> 144:ef7eb2e8f9f7 247 #define IS_ETH_DMATXDESC_BUFFER_SIZE(SIZE) ((SIZE) <= 0x1FFF)
<> 144:ef7eb2e8f9f7 248 #define IS_ETH_DMARXDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMARXDESC_OWN) || \
<> 144:ef7eb2e8f9f7 249 ((FLAG) == ETH_DMARXDESC_AFM) || \
<> 144:ef7eb2e8f9f7 250 ((FLAG) == ETH_DMARXDESC_ES) || \
<> 144:ef7eb2e8f9f7 251 ((FLAG) == ETH_DMARXDESC_DE) || \
<> 144:ef7eb2e8f9f7 252 ((FLAG) == ETH_DMARXDESC_SAF) || \
<> 144:ef7eb2e8f9f7 253 ((FLAG) == ETH_DMARXDESC_LE) || \
<> 144:ef7eb2e8f9f7 254 ((FLAG) == ETH_DMARXDESC_OE) || \
<> 144:ef7eb2e8f9f7 255 ((FLAG) == ETH_DMARXDESC_VLAN) || \
<> 144:ef7eb2e8f9f7 256 ((FLAG) == ETH_DMARXDESC_FS) || \
<> 144:ef7eb2e8f9f7 257 ((FLAG) == ETH_DMARXDESC_LS) || \
<> 144:ef7eb2e8f9f7 258 ((FLAG) == ETH_DMARXDESC_IPV4HCE) || \
<> 144:ef7eb2e8f9f7 259 ((FLAG) == ETH_DMARXDESC_LC) || \
<> 144:ef7eb2e8f9f7 260 ((FLAG) == ETH_DMARXDESC_FT) || \
<> 144:ef7eb2e8f9f7 261 ((FLAG) == ETH_DMARXDESC_RWT) || \
<> 144:ef7eb2e8f9f7 262 ((FLAG) == ETH_DMARXDESC_RE) || \
<> 144:ef7eb2e8f9f7 263 ((FLAG) == ETH_DMARXDESC_DBE) || \
<> 144:ef7eb2e8f9f7 264 ((FLAG) == ETH_DMARXDESC_CE) || \
<> 144:ef7eb2e8f9f7 265 ((FLAG) == ETH_DMARXDESC_MAMPCE))
<> 144:ef7eb2e8f9f7 266 #define IS_ETH_DMA_RXDESC_BUFFER(BUFFER) (((BUFFER) == ETH_DMARXDESC_BUFFER1) || \
<> 144:ef7eb2e8f9f7 267 ((BUFFER) == ETH_DMARXDESC_BUFFER2))
<> 144:ef7eb2e8f9f7 268 #define IS_ETH_PMT_GET_FLAG(FLAG) (((FLAG) == ETH_PMT_FLAG_WUFR) || \
<> 144:ef7eb2e8f9f7 269 ((FLAG) == ETH_PMT_FLAG_MPR))
<> 144:ef7eb2e8f9f7 270 #define IS_ETH_DMA_FLAG(FLAG) ((((FLAG) & (uint32_t)0xC7FE1800) == 0x00) && ((FLAG) != 0x00))
<> 144:ef7eb2e8f9f7 271 #define IS_ETH_DMA_GET_FLAG(FLAG) (((FLAG) == ETH_DMA_FLAG_TST) || ((FLAG) == ETH_DMA_FLAG_PMT) || \
<> 144:ef7eb2e8f9f7 272 ((FLAG) == ETH_DMA_FLAG_MMC) || ((FLAG) == ETH_DMA_FLAG_DATATRANSFERERROR) || \
<> 144:ef7eb2e8f9f7 273 ((FLAG) == ETH_DMA_FLAG_READWRITEERROR) || ((FLAG) == ETH_DMA_FLAG_ACCESSERROR) || \
<> 144:ef7eb2e8f9f7 274 ((FLAG) == ETH_DMA_FLAG_NIS) || ((FLAG) == ETH_DMA_FLAG_AIS) || \
<> 144:ef7eb2e8f9f7 275 ((FLAG) == ETH_DMA_FLAG_ER) || ((FLAG) == ETH_DMA_FLAG_FBE) || \
<> 144:ef7eb2e8f9f7 276 ((FLAG) == ETH_DMA_FLAG_ET) || ((FLAG) == ETH_DMA_FLAG_RWT) || \
<> 144:ef7eb2e8f9f7 277 ((FLAG) == ETH_DMA_FLAG_RPS) || ((FLAG) == ETH_DMA_FLAG_RBU) || \
<> 144:ef7eb2e8f9f7 278 ((FLAG) == ETH_DMA_FLAG_R) || ((FLAG) == ETH_DMA_FLAG_TU) || \
<> 144:ef7eb2e8f9f7 279 ((FLAG) == ETH_DMA_FLAG_RO) || ((FLAG) == ETH_DMA_FLAG_TJT) || \
<> 144:ef7eb2e8f9f7 280 ((FLAG) == ETH_DMA_FLAG_TBU) || ((FLAG) == ETH_DMA_FLAG_TPS) || \
<> 144:ef7eb2e8f9f7 281 ((FLAG) == ETH_DMA_FLAG_T))
<> 144:ef7eb2e8f9f7 282 #define IS_ETH_MAC_IT(IT) ((((IT) & (uint32_t)0xFFFFFDF1) == 0x00) && ((IT) != 0x00))
<> 144:ef7eb2e8f9f7 283 #define IS_ETH_MAC_GET_IT(IT) (((IT) == ETH_MAC_IT_TST) || ((IT) == ETH_MAC_IT_MMCT) || \
<> 144:ef7eb2e8f9f7 284 ((IT) == ETH_MAC_IT_MMCR) || ((IT) == ETH_MAC_IT_MMC) || \
<> 144:ef7eb2e8f9f7 285 ((IT) == ETH_MAC_IT_PMT))
<> 144:ef7eb2e8f9f7 286 #define IS_ETH_MAC_GET_FLAG(FLAG) (((FLAG) == ETH_MAC_FLAG_TST) || ((FLAG) == ETH_MAC_FLAG_MMCT) || \
<> 144:ef7eb2e8f9f7 287 ((FLAG) == ETH_MAC_FLAG_MMCR) || ((FLAG) == ETH_MAC_FLAG_MMC) || \
<> 144:ef7eb2e8f9f7 288 ((FLAG) == ETH_MAC_FLAG_PMT))
<> 144:ef7eb2e8f9f7 289 #define IS_ETH_DMA_IT(IT) ((((IT) & (uint32_t)0xC7FE1800) == 0x00) && ((IT) != 0x00))
<> 144:ef7eb2e8f9f7 290 #define IS_ETH_DMA_GET_IT(IT) (((IT) == ETH_DMA_IT_TST) || ((IT) == ETH_DMA_IT_PMT) || \
<> 144:ef7eb2e8f9f7 291 ((IT) == ETH_DMA_IT_MMC) || ((IT) == ETH_DMA_IT_NIS) || \
<> 144:ef7eb2e8f9f7 292 ((IT) == ETH_DMA_IT_AIS) || ((IT) == ETH_DMA_IT_ER) || \
<> 144:ef7eb2e8f9f7 293 ((IT) == ETH_DMA_IT_FBE) || ((IT) == ETH_DMA_IT_ET) || \
<> 144:ef7eb2e8f9f7 294 ((IT) == ETH_DMA_IT_RWT) || ((IT) == ETH_DMA_IT_RPS) || \
<> 144:ef7eb2e8f9f7 295 ((IT) == ETH_DMA_IT_RBU) || ((IT) == ETH_DMA_IT_R) || \
<> 144:ef7eb2e8f9f7 296 ((IT) == ETH_DMA_IT_TU) || ((IT) == ETH_DMA_IT_RO) || \
<> 144:ef7eb2e8f9f7 297 ((IT) == ETH_DMA_IT_TJT) || ((IT) == ETH_DMA_IT_TBU) || \
<> 144:ef7eb2e8f9f7 298 ((IT) == ETH_DMA_IT_TPS) || ((IT) == ETH_DMA_IT_T))
<> 144:ef7eb2e8f9f7 299 #define IS_ETH_DMA_GET_OVERFLOW(OVERFLOW) (((OVERFLOW) == ETH_DMA_OVERFLOW_RXFIFOCOUNTER) || \
<> 144:ef7eb2e8f9f7 300 ((OVERFLOW) == ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER))
<> 144:ef7eb2e8f9f7 301 #define IS_ETH_MMC_IT(IT) (((((IT) & (uint32_t)0xFFDF3FFF) == 0x00) || (((IT) & (uint32_t)0xEFFDFF9F) == 0x00)) && \
<> 144:ef7eb2e8f9f7 302 ((IT) != 0x00))
<> 144:ef7eb2e8f9f7 303 #define IS_ETH_MMC_GET_IT(IT) (((IT) == ETH_MMC_IT_TGF) || ((IT) == ETH_MMC_IT_TGFMSC) || \
<> 144:ef7eb2e8f9f7 304 ((IT) == ETH_MMC_IT_TGFSC) || ((IT) == ETH_MMC_IT_RGUF) || \
<> 144:ef7eb2e8f9f7 305 ((IT) == ETH_MMC_IT_RFAE) || ((IT) == ETH_MMC_IT_RFCE))
<> 144:ef7eb2e8f9f7 306 #define IS_ETH_ENHANCED_DESCRIPTOR_FORMAT(CMD) (((CMD) == ETH_DMAENHANCEDDESCRIPTOR_ENABLE) || \
<> 144:ef7eb2e8f9f7 307 ((CMD) == ETH_DMAENHANCEDDESCRIPTOR_DISABLE))
<> 144:ef7eb2e8f9f7 308
<> 144:ef7eb2e8f9f7 309
<> 144:ef7eb2e8f9f7 310 /**
<> 144:ef7eb2e8f9f7 311 * @}
<> 144:ef7eb2e8f9f7 312 */
<> 144:ef7eb2e8f9f7 313
<> 144:ef7eb2e8f9f7 314 /** @addtogroup ETH_Private_Defines
<> 144:ef7eb2e8f9f7 315 * @{
<> 144:ef7eb2e8f9f7 316 */
<> 144:ef7eb2e8f9f7 317 /* Delay to wait when writing to some Ethernet registers */
<> 144:ef7eb2e8f9f7 318 #define ETH_REG_WRITE_DELAY ((uint32_t)0x00000001U)
<> 144:ef7eb2e8f9f7 319
<> 144:ef7eb2e8f9f7 320 /* Ethernet Errors */
<> 144:ef7eb2e8f9f7 321 #define ETH_SUCCESS ((uint32_t)0U)
<> 144:ef7eb2e8f9f7 322 #define ETH_ERROR ((uint32_t)1U)
<> 144:ef7eb2e8f9f7 323
<> 144:ef7eb2e8f9f7 324 /* Ethernet DMA Tx descriptors Collision Count Shift */
<> 144:ef7eb2e8f9f7 325 #define ETH_DMATXDESC_COLLISION_COUNTSHIFT ((uint32_t)3U)
<> 144:ef7eb2e8f9f7 326
<> 144:ef7eb2e8f9f7 327 /* Ethernet DMA Tx descriptors Buffer2 Size Shift */
<> 144:ef7eb2e8f9f7 328 #define ETH_DMATXDESC_BUFFER2_SIZESHIFT ((uint32_t)16U)
<> 144:ef7eb2e8f9f7 329
<> 144:ef7eb2e8f9f7 330 /* Ethernet DMA Rx descriptors Frame Length Shift */
<> 144:ef7eb2e8f9f7 331 #define ETH_DMARXDESC_FRAME_LENGTHSHIFT ((uint32_t)16U)
<> 144:ef7eb2e8f9f7 332
<> 144:ef7eb2e8f9f7 333 /* Ethernet DMA Rx descriptors Buffer2 Size Shift */
<> 144:ef7eb2e8f9f7 334 #define ETH_DMARXDESC_BUFFER2_SIZESHIFT ((uint32_t)16U)
<> 144:ef7eb2e8f9f7 335
<> 144:ef7eb2e8f9f7 336 /* Ethernet DMA Rx descriptors Frame length Shift */
<> 144:ef7eb2e8f9f7 337 #define ETH_DMARXDESC_FRAMELENGTHSHIFT ((uint32_t)16)
<> 144:ef7eb2e8f9f7 338
<> 144:ef7eb2e8f9f7 339 /* Ethernet MAC address offsets */
<> 144:ef7eb2e8f9f7 340 #define ETH_MAC_ADDR_HBASE (uint32_t)(ETH_MAC_BASE + (uint32_t)0x40U) /* Ethernet MAC address high offset */
<> 144:ef7eb2e8f9f7 341 #define ETH_MAC_ADDR_LBASE (uint32_t)(ETH_MAC_BASE + (uint32_t)0x44U) /* Ethernet MAC address low offset */
<> 144:ef7eb2e8f9f7 342
<> 144:ef7eb2e8f9f7 343 /* Ethernet MACMIIAR register Mask */
<> 144:ef7eb2e8f9f7 344 #define ETH_MACMIIAR_CR_MASK ((uint32_t)0xFFFFFFE3U)
<> 144:ef7eb2e8f9f7 345
<> 144:ef7eb2e8f9f7 346 /* Ethernet MACCR register Mask */
<> 144:ef7eb2e8f9f7 347 #define ETH_MACCR_CLEAR_MASK ((uint32_t)0xFF20810FU)
<> 144:ef7eb2e8f9f7 348
<> 144:ef7eb2e8f9f7 349 /* Ethernet MACFCR register Mask */
<> 144:ef7eb2e8f9f7 350 #define ETH_MACFCR_CLEAR_MASK ((uint32_t)0x0000FF41U)
<> 144:ef7eb2e8f9f7 351
<> 144:ef7eb2e8f9f7 352 /* Ethernet DMAOMR register Mask */
<> 144:ef7eb2e8f9f7 353 #define ETH_DMAOMR_CLEAR_MASK ((uint32_t)0xF8DE3F23U)
<> 144:ef7eb2e8f9f7 354
<> 144:ef7eb2e8f9f7 355 /* Ethernet Remote Wake-up frame register length */
<> 144:ef7eb2e8f9f7 356 #define ETH_WAKEUP_REGISTER_LENGTH 8U
<> 144:ef7eb2e8f9f7 357
<> 144:ef7eb2e8f9f7 358 /* Ethernet Missed frames counter Shift */
<> 144:ef7eb2e8f9f7 359 #define ETH_DMA_RX_OVERFLOW_MISSEDFRAMES_COUNTERSHIFT 17U
<> 144:ef7eb2e8f9f7 360 /**
<> 144:ef7eb2e8f9f7 361 * @}
<> 144:ef7eb2e8f9f7 362 */
<> 144:ef7eb2e8f9f7 363
<> 144:ef7eb2e8f9f7 364 /* Exported types ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 365 /** @defgroup ETH_Exported_Types ETH Exported Types
<> 144:ef7eb2e8f9f7 366 * @{
<> 144:ef7eb2e8f9f7 367 */
<> 144:ef7eb2e8f9f7 368
<> 144:ef7eb2e8f9f7 369 /**
<> 144:ef7eb2e8f9f7 370 * @brief HAL State structures definition
<> 144:ef7eb2e8f9f7 371 */
<> 144:ef7eb2e8f9f7 372 typedef enum
<> 144:ef7eb2e8f9f7 373 {
<> 144:ef7eb2e8f9f7 374 HAL_ETH_STATE_RESET = 0x00U, /*!< Peripheral not yet Initialized or disabled */
<> 144:ef7eb2e8f9f7 375 HAL_ETH_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */
<> 144:ef7eb2e8f9f7 376 HAL_ETH_STATE_BUSY = 0x02U, /*!< an internal process is ongoing */
<> 144:ef7eb2e8f9f7 377 HAL_ETH_STATE_BUSY_TX = 0x12U, /*!< Data Transmission process is ongoing */
<> 144:ef7eb2e8f9f7 378 HAL_ETH_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing */
<> 144:ef7eb2e8f9f7 379 HAL_ETH_STATE_BUSY_TX_RX = 0x32U, /*!< Data Transmission and Reception process is ongoing */
<> 144:ef7eb2e8f9f7 380 HAL_ETH_STATE_BUSY_WR = 0x42U, /*!< Write process is ongoing */
<> 144:ef7eb2e8f9f7 381 HAL_ETH_STATE_BUSY_RD = 0x82U, /*!< Read process is ongoing */
<> 144:ef7eb2e8f9f7 382 HAL_ETH_STATE_TIMEOUT = 0x03U, /*!< Timeout state */
<> 144:ef7eb2e8f9f7 383 HAL_ETH_STATE_ERROR = 0x04U /*!< Reception process is ongoing */
<> 144:ef7eb2e8f9f7 384 }HAL_ETH_StateTypeDef;
<> 144:ef7eb2e8f9f7 385
<> 144:ef7eb2e8f9f7 386 /**
<> 144:ef7eb2e8f9f7 387 * @brief ETH Init Structure definition
<> 144:ef7eb2e8f9f7 388 */
<> 144:ef7eb2e8f9f7 389
<> 144:ef7eb2e8f9f7 390 typedef struct
<> 144:ef7eb2e8f9f7 391 {
<> 144:ef7eb2e8f9f7 392 uint32_t AutoNegotiation; /*!< Selects or not the AutoNegotiation mode for the external PHY
<> 144:ef7eb2e8f9f7 393 The AutoNegotiation allows an automatic setting of the Speed (10/100Mbps)
<> 144:ef7eb2e8f9f7 394 and the mode (half/full-duplex).
<> 144:ef7eb2e8f9f7 395 This parameter can be a value of @ref ETH_AutoNegotiation */
<> 144:ef7eb2e8f9f7 396
<> 144:ef7eb2e8f9f7 397 uint32_t Speed; /*!< Sets the Ethernet speed: 10/100 Mbps.
<> 144:ef7eb2e8f9f7 398 This parameter can be a value of @ref ETH_Speed */
<> 144:ef7eb2e8f9f7 399
<> 144:ef7eb2e8f9f7 400 uint32_t DuplexMode; /*!< Selects the MAC duplex mode: Half-Duplex or Full-Duplex mode
<> 144:ef7eb2e8f9f7 401 This parameter can be a value of @ref ETH_Duplex_Mode */
<> 144:ef7eb2e8f9f7 402
<> 144:ef7eb2e8f9f7 403 uint16_t PhyAddress; /*!< Ethernet PHY address.
<> 144:ef7eb2e8f9f7 404 This parameter must be a number between Min_Data = 0 and Max_Data = 32 */
<> 144:ef7eb2e8f9f7 405
<> 144:ef7eb2e8f9f7 406 uint8_t *MACAddr; /*!< MAC Address of used Hardware: must be pointer on an array of 6 bytes */
<> 144:ef7eb2e8f9f7 407
<> 144:ef7eb2e8f9f7 408 uint32_t RxMode; /*!< Selects the Ethernet Rx mode: Polling mode, Interrupt mode.
<> 144:ef7eb2e8f9f7 409 This parameter can be a value of @ref ETH_Rx_Mode */
<> 144:ef7eb2e8f9f7 410
<> 144:ef7eb2e8f9f7 411 uint32_t ChecksumMode; /*!< Selects if the checksum is check by hardware or by software.
<> 144:ef7eb2e8f9f7 412 This parameter can be a value of @ref ETH_Checksum_Mode */
<> 144:ef7eb2e8f9f7 413
<> 144:ef7eb2e8f9f7 414 uint32_t MediaInterface ; /*!< Selects the media-independent interface or the reduced media-independent interface.
<> 144:ef7eb2e8f9f7 415 This parameter can be a value of @ref ETH_Media_Interface */
<> 144:ef7eb2e8f9f7 416
<> 144:ef7eb2e8f9f7 417 } ETH_InitTypeDef;
<> 144:ef7eb2e8f9f7 418
<> 144:ef7eb2e8f9f7 419
<> 144:ef7eb2e8f9f7 420 /**
<> 144:ef7eb2e8f9f7 421 * @brief ETH MAC Configuration Structure definition
<> 144:ef7eb2e8f9f7 422 */
<> 144:ef7eb2e8f9f7 423
<> 144:ef7eb2e8f9f7 424 typedef struct
<> 144:ef7eb2e8f9f7 425 {
<> 144:ef7eb2e8f9f7 426 uint32_t Watchdog; /*!< Selects or not the Watchdog timer
<> 144:ef7eb2e8f9f7 427 When enabled, the MAC allows no more then 2048 bytes to be received.
<> 144:ef7eb2e8f9f7 428 When disabled, the MAC can receive up to 16384 bytes.
<> 144:ef7eb2e8f9f7 429 This parameter can be a value of @ref ETH_Watchdog */
<> 144:ef7eb2e8f9f7 430
<> 144:ef7eb2e8f9f7 431 uint32_t Jabber; /*!< Selects or not Jabber timer
<> 144:ef7eb2e8f9f7 432 When enabled, the MAC allows no more then 2048 bytes to be sent.
<> 144:ef7eb2e8f9f7 433 When disabled, the MAC can send up to 16384 bytes.
<> 144:ef7eb2e8f9f7 434 This parameter can be a value of @ref ETH_Jabber */
<> 144:ef7eb2e8f9f7 435
<> 144:ef7eb2e8f9f7 436 uint32_t InterFrameGap; /*!< Selects the minimum IFG between frames during transmission.
<> 144:ef7eb2e8f9f7 437 This parameter can be a value of @ref ETH_Inter_Frame_Gap */
<> 144:ef7eb2e8f9f7 438
<> 144:ef7eb2e8f9f7 439 uint32_t CarrierSense; /*!< Selects or not the Carrier Sense.
<> 144:ef7eb2e8f9f7 440 This parameter can be a value of @ref ETH_Carrier_Sense */
<> 144:ef7eb2e8f9f7 441
<> 144:ef7eb2e8f9f7 442 uint32_t ReceiveOwn; /*!< Selects or not the ReceiveOwn,
<> 144:ef7eb2e8f9f7 443 ReceiveOwn allows the reception of frames when the TX_EN signal is asserted
<> 144:ef7eb2e8f9f7 444 in Half-Duplex mode.
<> 144:ef7eb2e8f9f7 445 This parameter can be a value of @ref ETH_Receive_Own */
<> 144:ef7eb2e8f9f7 446
<> 144:ef7eb2e8f9f7 447 uint32_t LoopbackMode; /*!< Selects or not the internal MAC MII Loopback mode.
<> 144:ef7eb2e8f9f7 448 This parameter can be a value of @ref ETH_Loop_Back_Mode */
<> 144:ef7eb2e8f9f7 449
<> 144:ef7eb2e8f9f7 450 uint32_t ChecksumOffload; /*!< Selects or not the IPv4 checksum checking for received frame payloads' TCP/UDP/ICMP headers.
<> 144:ef7eb2e8f9f7 451 This parameter can be a value of @ref ETH_Checksum_Offload */
<> 144:ef7eb2e8f9f7 452
<> 144:ef7eb2e8f9f7 453 uint32_t RetryTransmission; /*!< Selects or not the MAC attempt retries transmission, based on the settings of BL,
<> 144:ef7eb2e8f9f7 454 when a collision occurs (Half-Duplex mode).
<> 144:ef7eb2e8f9f7 455 This parameter can be a value of @ref ETH_Retry_Transmission */
<> 144:ef7eb2e8f9f7 456
<> 144:ef7eb2e8f9f7 457 uint32_t AutomaticPadCRCStrip; /*!< Selects or not the Automatic MAC Pad/CRC Stripping.
<> 144:ef7eb2e8f9f7 458 This parameter can be a value of @ref ETH_Automatic_Pad_CRC_Strip */
<> 144:ef7eb2e8f9f7 459
<> 144:ef7eb2e8f9f7 460 uint32_t BackOffLimit; /*!< Selects the BackOff limit value.
<> 144:ef7eb2e8f9f7 461 This parameter can be a value of @ref ETH_Back_Off_Limit */
<> 144:ef7eb2e8f9f7 462
<> 144:ef7eb2e8f9f7 463 uint32_t DeferralCheck; /*!< Selects or not the deferral check function (Half-Duplex mode).
<> 144:ef7eb2e8f9f7 464 This parameter can be a value of @ref ETH_Deferral_Check */
<> 144:ef7eb2e8f9f7 465
<> 144:ef7eb2e8f9f7 466 uint32_t ReceiveAll; /*!< Selects or not all frames reception by the MAC (No filtering).
<> 144:ef7eb2e8f9f7 467 This parameter can be a value of @ref ETH_Receive_All */
<> 144:ef7eb2e8f9f7 468
<> 144:ef7eb2e8f9f7 469 uint32_t SourceAddrFilter; /*!< Selects the Source Address Filter mode.
<> 144:ef7eb2e8f9f7 470 This parameter can be a value of @ref ETH_Source_Addr_Filter */
<> 144:ef7eb2e8f9f7 471
<> 144:ef7eb2e8f9f7 472 uint32_t PassControlFrames; /*!< Sets the forwarding mode of the control frames (including unicast and multicast PAUSE frames)
<> 144:ef7eb2e8f9f7 473 This parameter can be a value of @ref ETH_Pass_Control_Frames */
<> 144:ef7eb2e8f9f7 474
<> 144:ef7eb2e8f9f7 475 uint32_t BroadcastFramesReception; /*!< Selects or not the reception of Broadcast Frames.
<> 144:ef7eb2e8f9f7 476 This parameter can be a value of @ref ETH_Broadcast_Frames_Reception */
<> 144:ef7eb2e8f9f7 477
<> 144:ef7eb2e8f9f7 478 uint32_t DestinationAddrFilter; /*!< Sets the destination filter mode for both unicast and multicast frames.
<> 144:ef7eb2e8f9f7 479 This parameter can be a value of @ref ETH_Destination_Addr_Filter */
<> 144:ef7eb2e8f9f7 480
<> 144:ef7eb2e8f9f7 481 uint32_t PromiscuousMode; /*!< Selects or not the Promiscuous Mode
<> 144:ef7eb2e8f9f7 482 This parameter can be a value of @ref ETH_Promiscuous_Mode */
<> 144:ef7eb2e8f9f7 483
<> 144:ef7eb2e8f9f7 484 uint32_t MulticastFramesFilter; /*!< Selects the Multicast Frames filter mode: None/HashTableFilter/PerfectFilter/PerfectHashTableFilter.
<> 144:ef7eb2e8f9f7 485 This parameter can be a value of @ref ETH_Multicast_Frames_Filter */
<> 144:ef7eb2e8f9f7 486
<> 144:ef7eb2e8f9f7 487 uint32_t UnicastFramesFilter; /*!< Selects the Unicast Frames filter mode: HashTableFilter/PerfectFilter/PerfectHashTableFilter.
<> 144:ef7eb2e8f9f7 488 This parameter can be a value of @ref ETH_Unicast_Frames_Filter */
<> 144:ef7eb2e8f9f7 489
<> 144:ef7eb2e8f9f7 490 uint32_t HashTableHigh; /*!< This field holds the higher 32 bits of Hash table.
<> 144:ef7eb2e8f9f7 491 This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFFFFF */
<> 144:ef7eb2e8f9f7 492
<> 144:ef7eb2e8f9f7 493 uint32_t HashTableLow; /*!< This field holds the lower 32 bits of Hash table.
<> 144:ef7eb2e8f9f7 494 This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFFFFF */
<> 144:ef7eb2e8f9f7 495
<> 144:ef7eb2e8f9f7 496 uint32_t PauseTime; /*!< This field holds the value to be used in the Pause Time field in the transmit control frame.
<> 144:ef7eb2e8f9f7 497 This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFF */
<> 144:ef7eb2e8f9f7 498
<> 144:ef7eb2e8f9f7 499 uint32_t ZeroQuantaPause; /*!< Selects or not the automatic generation of Zero-Quanta Pause Control frames.
<> 144:ef7eb2e8f9f7 500 This parameter can be a value of @ref ETH_Zero_Quanta_Pause */
<> 144:ef7eb2e8f9f7 501
<> 144:ef7eb2e8f9f7 502 uint32_t PauseLowThreshold; /*!< This field configures the threshold of the PAUSE to be checked for
<> 144:ef7eb2e8f9f7 503 automatic retransmission of PAUSE Frame.
<> 144:ef7eb2e8f9f7 504 This parameter can be a value of @ref ETH_Pause_Low_Threshold */
<> 144:ef7eb2e8f9f7 505
<> 144:ef7eb2e8f9f7 506 uint32_t UnicastPauseFrameDetect; /*!< Selects or not the MAC detection of the Pause frames (with MAC Address0
<> 144:ef7eb2e8f9f7 507 unicast address and unique multicast address).
<> 144:ef7eb2e8f9f7 508 This parameter can be a value of @ref ETH_Unicast_Pause_Frame_Detect */
<> 144:ef7eb2e8f9f7 509
<> 144:ef7eb2e8f9f7 510 uint32_t ReceiveFlowControl; /*!< Enables or disables the MAC to decode the received Pause frame and
<> 144:ef7eb2e8f9f7 511 disable its transmitter for a specified time (Pause Time)
<> 144:ef7eb2e8f9f7 512 This parameter can be a value of @ref ETH_Receive_Flow_Control */
<> 144:ef7eb2e8f9f7 513
<> 144:ef7eb2e8f9f7 514 uint32_t TransmitFlowControl; /*!< Enables or disables the MAC to transmit Pause frames (Full-Duplex mode)
<> 144:ef7eb2e8f9f7 515 or the MAC back-pressure operation (Half-Duplex mode)
<> 144:ef7eb2e8f9f7 516 This parameter can be a value of @ref ETH_Transmit_Flow_Control */
<> 144:ef7eb2e8f9f7 517
<> 144:ef7eb2e8f9f7 518 uint32_t VLANTagComparison; /*!< Selects the 12-bit VLAN identifier or the complete 16-bit VLAN tag for
<> 144:ef7eb2e8f9f7 519 comparison and filtering.
<> 144:ef7eb2e8f9f7 520 This parameter can be a value of @ref ETH_VLAN_Tag_Comparison */
<> 144:ef7eb2e8f9f7 521
<> 144:ef7eb2e8f9f7 522 uint32_t VLANTagIdentifier; /*!< Holds the VLAN tag identifier for receive frames */
<> 144:ef7eb2e8f9f7 523
<> 144:ef7eb2e8f9f7 524 } ETH_MACInitTypeDef;
<> 144:ef7eb2e8f9f7 525
<> 144:ef7eb2e8f9f7 526
<> 144:ef7eb2e8f9f7 527 /**
<> 144:ef7eb2e8f9f7 528 * @brief ETH DMA Configuration Structure definition
<> 144:ef7eb2e8f9f7 529 */
<> 144:ef7eb2e8f9f7 530
<> 144:ef7eb2e8f9f7 531 typedef struct
<> 144:ef7eb2e8f9f7 532 {
<> 144:ef7eb2e8f9f7 533 uint32_t DropTCPIPChecksumErrorFrame; /*!< Selects or not the Dropping of TCP/IP Checksum Error Frames.
<> 144:ef7eb2e8f9f7 534 This parameter can be a value of @ref ETH_Drop_TCP_IP_Checksum_Error_Frame */
<> 144:ef7eb2e8f9f7 535
<> 144:ef7eb2e8f9f7 536 uint32_t ReceiveStoreForward; /*!< Enables or disables the Receive store and forward mode.
<> 144:ef7eb2e8f9f7 537 This parameter can be a value of @ref ETH_Receive_Store_Forward */
<> 144:ef7eb2e8f9f7 538
<> 144:ef7eb2e8f9f7 539 uint32_t FlushReceivedFrame; /*!< Enables or disables the flushing of received frames.
<> 144:ef7eb2e8f9f7 540 This parameter can be a value of @ref ETH_Flush_Received_Frame */
<> 144:ef7eb2e8f9f7 541
<> 144:ef7eb2e8f9f7 542 uint32_t TransmitStoreForward; /*!< Enables or disables Transmit store and forward mode.
<> 144:ef7eb2e8f9f7 543 This parameter can be a value of @ref ETH_Transmit_Store_Forward */
<> 144:ef7eb2e8f9f7 544
<> 144:ef7eb2e8f9f7 545 uint32_t TransmitThresholdControl; /*!< Selects or not the Transmit Threshold Control.
<> 144:ef7eb2e8f9f7 546 This parameter can be a value of @ref ETH_Transmit_Threshold_Control */
<> 144:ef7eb2e8f9f7 547
<> 144:ef7eb2e8f9f7 548 uint32_t ForwardErrorFrames; /*!< Selects or not the forward to the DMA of erroneous frames.
<> 144:ef7eb2e8f9f7 549 This parameter can be a value of @ref ETH_Forward_Error_Frames */
<> 144:ef7eb2e8f9f7 550
<> 144:ef7eb2e8f9f7 551 uint32_t ForwardUndersizedGoodFrames; /*!< Enables or disables the Rx FIFO to forward Undersized frames (frames with no Error
<> 144:ef7eb2e8f9f7 552 and length less than 64 bytes) including pad-bytes and CRC)
<> 144:ef7eb2e8f9f7 553 This parameter can be a value of @ref ETH_Forward_Undersized_Good_Frames */
<> 144:ef7eb2e8f9f7 554
<> 144:ef7eb2e8f9f7 555 uint32_t ReceiveThresholdControl; /*!< Selects the threshold level of the Receive FIFO.
<> 144:ef7eb2e8f9f7 556 This parameter can be a value of @ref ETH_Receive_Threshold_Control */
<> 144:ef7eb2e8f9f7 557
<> 144:ef7eb2e8f9f7 558 uint32_t SecondFrameOperate; /*!< Selects or not the Operate on second frame mode, which allows the DMA to process a second
<> 144:ef7eb2e8f9f7 559 frame of Transmit data even before obtaining the status for the first frame.
<> 144:ef7eb2e8f9f7 560 This parameter can be a value of @ref ETH_Second_Frame_Operate */
<> 144:ef7eb2e8f9f7 561
<> 144:ef7eb2e8f9f7 562 uint32_t AddressAlignedBeats; /*!< Enables or disables the Address Aligned Beats.
<> 144:ef7eb2e8f9f7 563 This parameter can be a value of @ref ETH_Address_Aligned_Beats */
<> 144:ef7eb2e8f9f7 564
<> 144:ef7eb2e8f9f7 565 uint32_t FixedBurst; /*!< Enables or disables the AHB Master interface fixed burst transfers.
<> 144:ef7eb2e8f9f7 566 This parameter can be a value of @ref ETH_Fixed_Burst */
<> 144:ef7eb2e8f9f7 567
<> 144:ef7eb2e8f9f7 568 uint32_t RxDMABurstLength; /*!< Indicates the maximum number of beats to be transferred in one Rx DMA transaction.
<> 144:ef7eb2e8f9f7 569 This parameter can be a value of @ref ETH_Rx_DMA_Burst_Length */
<> 144:ef7eb2e8f9f7 570
<> 144:ef7eb2e8f9f7 571 uint32_t TxDMABurstLength; /*!< Indicates the maximum number of beats to be transferred in one Tx DMA transaction.
<> 144:ef7eb2e8f9f7 572 This parameter can be a value of @ref ETH_Tx_DMA_Burst_Length */
<> 144:ef7eb2e8f9f7 573
<> 144:ef7eb2e8f9f7 574 uint32_t EnhancedDescriptorFormat; /*!< Enables the enhanced descriptor format.
<> 144:ef7eb2e8f9f7 575 This parameter can be a value of @ref ETH_DMA_Enhanced_descriptor_format */
<> 144:ef7eb2e8f9f7 576
<> 144:ef7eb2e8f9f7 577 uint32_t DescriptorSkipLength; /*!< Specifies the number of word to skip between two unchained descriptors (Ring mode)
<> 144:ef7eb2e8f9f7 578 This parameter must be a number between Min_Data = 0 and Max_Data = 32 */
<> 144:ef7eb2e8f9f7 579
<> 144:ef7eb2e8f9f7 580 uint32_t DMAArbitration; /*!< Selects the DMA Tx/Rx arbitration.
<> 144:ef7eb2e8f9f7 581 This parameter can be a value of @ref ETH_DMA_Arbitration */
<> 144:ef7eb2e8f9f7 582 } ETH_DMAInitTypeDef;
<> 144:ef7eb2e8f9f7 583
<> 144:ef7eb2e8f9f7 584
<> 144:ef7eb2e8f9f7 585 /**
<> 144:ef7eb2e8f9f7 586 * @brief ETH DMA Descriptors data structure definition
<> 144:ef7eb2e8f9f7 587 */
<> 144:ef7eb2e8f9f7 588
<> 144:ef7eb2e8f9f7 589 typedef struct
<> 144:ef7eb2e8f9f7 590 {
<> 144:ef7eb2e8f9f7 591 __IO uint32_t Status; /*!< Status */
<> 144:ef7eb2e8f9f7 592
<> 144:ef7eb2e8f9f7 593 uint32_t ControlBufferSize; /*!< Control and Buffer1, Buffer2 lengths */
<> 144:ef7eb2e8f9f7 594
<> 144:ef7eb2e8f9f7 595 uint32_t Buffer1Addr; /*!< Buffer1 address pointer */
<> 144:ef7eb2e8f9f7 596
<> 144:ef7eb2e8f9f7 597 uint32_t Buffer2NextDescAddr; /*!< Buffer2 or next descriptor address pointer */
<> 144:ef7eb2e8f9f7 598
<> 144:ef7eb2e8f9f7 599 /*!< Enhanced Ethernet DMA PTP Descriptors */
<> 144:ef7eb2e8f9f7 600 uint32_t ExtendedStatus; /*!< Extended status for PTP receive descriptor */
<> 144:ef7eb2e8f9f7 601
<> 144:ef7eb2e8f9f7 602 uint32_t Reserved1; /*!< Reserved */
<> 144:ef7eb2e8f9f7 603
<> 144:ef7eb2e8f9f7 604 uint32_t TimeStampLow; /*!< Time Stamp Low value for transmit and receive */
<> 144:ef7eb2e8f9f7 605
<> 144:ef7eb2e8f9f7 606 uint32_t TimeStampHigh; /*!< Time Stamp High value for transmit and receive */
<> 144:ef7eb2e8f9f7 607
<> 144:ef7eb2e8f9f7 608 } ETH_DMADescTypeDef;
<> 144:ef7eb2e8f9f7 609
<> 144:ef7eb2e8f9f7 610
<> 144:ef7eb2e8f9f7 611 /**
<> 144:ef7eb2e8f9f7 612 * @brief Received Frame Informations structure definition
<> 144:ef7eb2e8f9f7 613 */
<> 144:ef7eb2e8f9f7 614 typedef struct
<> 144:ef7eb2e8f9f7 615 {
<> 144:ef7eb2e8f9f7 616 ETH_DMADescTypeDef *FSRxDesc; /*!< First Segment Rx Desc */
<> 144:ef7eb2e8f9f7 617
<> 144:ef7eb2e8f9f7 618 ETH_DMADescTypeDef *LSRxDesc; /*!< Last Segment Rx Desc */
<> 144:ef7eb2e8f9f7 619
<> 144:ef7eb2e8f9f7 620 uint32_t SegCount; /*!< Segment count */
<> 144:ef7eb2e8f9f7 621
<> 144:ef7eb2e8f9f7 622 uint32_t length; /*!< Frame length */
<> 144:ef7eb2e8f9f7 623
<> 144:ef7eb2e8f9f7 624 uint32_t buffer; /*!< Frame buffer */
<> 144:ef7eb2e8f9f7 625
<> 144:ef7eb2e8f9f7 626 } ETH_DMARxFrameInfos;
<> 144:ef7eb2e8f9f7 627
<> 144:ef7eb2e8f9f7 628
<> 144:ef7eb2e8f9f7 629 /**
<> 144:ef7eb2e8f9f7 630 * @brief ETH Handle Structure definition
<> 144:ef7eb2e8f9f7 631 */
<> 144:ef7eb2e8f9f7 632
<> 144:ef7eb2e8f9f7 633 typedef struct
<> 144:ef7eb2e8f9f7 634 {
<> 144:ef7eb2e8f9f7 635 ETH_TypeDef *Instance; /*!< Register base address */
<> 144:ef7eb2e8f9f7 636
<> 144:ef7eb2e8f9f7 637 ETH_InitTypeDef Init; /*!< Ethernet Init Configuration */
<> 144:ef7eb2e8f9f7 638
<> 144:ef7eb2e8f9f7 639 uint32_t LinkStatus; /*!< Ethernet link status */
<> 144:ef7eb2e8f9f7 640
<> 144:ef7eb2e8f9f7 641 ETH_DMADescTypeDef *RxDesc; /*!< Rx descriptor to Get */
<> 144:ef7eb2e8f9f7 642
<> 144:ef7eb2e8f9f7 643 ETH_DMADescTypeDef *TxDesc; /*!< Tx descriptor to Set */
<> 144:ef7eb2e8f9f7 644
<> 144:ef7eb2e8f9f7 645 ETH_DMARxFrameInfos RxFrameInfos; /*!< last Rx frame infos */
<> 144:ef7eb2e8f9f7 646
<> 144:ef7eb2e8f9f7 647 __IO HAL_ETH_StateTypeDef State; /*!< ETH communication state */
<> 144:ef7eb2e8f9f7 648
<> 144:ef7eb2e8f9f7 649 HAL_LockTypeDef Lock; /*!< ETH Lock */
<> 144:ef7eb2e8f9f7 650
<> 144:ef7eb2e8f9f7 651 } ETH_HandleTypeDef;
<> 144:ef7eb2e8f9f7 652
<> 144:ef7eb2e8f9f7 653 /**
<> 144:ef7eb2e8f9f7 654 * @}
<> 144:ef7eb2e8f9f7 655 */
<> 144:ef7eb2e8f9f7 656
<> 144:ef7eb2e8f9f7 657 /* Exported constants --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 658 /** @defgroup ETH_Exported_Constants ETH Exported Constants
<> 144:ef7eb2e8f9f7 659 * @{
<> 144:ef7eb2e8f9f7 660 */
<> 144:ef7eb2e8f9f7 661
<> 144:ef7eb2e8f9f7 662 /** @defgroup ETH_Buffers_setting ETH Buffers setting
<> 144:ef7eb2e8f9f7 663 * @{
<> 144:ef7eb2e8f9f7 664 */
<> 144:ef7eb2e8f9f7 665 #define ETH_MAX_PACKET_SIZE ((uint32_t)1524U) /*!< ETH_HEADER + ETH_EXTRA + ETH_VLAN_TAG + ETH_MAX_ETH_PAYLOAD + ETH_CRC */
<> 144:ef7eb2e8f9f7 666 #define ETH_HEADER ((uint32_t)14U) /*!< 6 byte Dest addr, 6 byte Src addr, 2 byte length/type */
<> 144:ef7eb2e8f9f7 667 #define ETH_CRC ((uint32_t)4U) /*!< Ethernet CRC */
<> 144:ef7eb2e8f9f7 668 #define ETH_EXTRA ((uint32_t)2U) /*!< Extra bytes in some cases */
<> 144:ef7eb2e8f9f7 669 #define ETH_VLAN_TAG ((uint32_t)4U) /*!< optional 802.1q VLAN Tag */
<> 144:ef7eb2e8f9f7 670 #define ETH_MIN_ETH_PAYLOAD ((uint32_t)46U) /*!< Minimum Ethernet payload size */
<> 144:ef7eb2e8f9f7 671 #define ETH_MAX_ETH_PAYLOAD ((uint32_t)1500U) /*!< Maximum Ethernet payload size */
<> 144:ef7eb2e8f9f7 672 #define ETH_JUMBO_FRAME_PAYLOAD ((uint32_t)9000U) /*!< Jumbo frame payload size */
<> 144:ef7eb2e8f9f7 673
<> 144:ef7eb2e8f9f7 674 /* Ethernet driver receive buffers are organized in a chained linked-list, when
<> 144:ef7eb2e8f9f7 675 an Ethernet packet is received, the Rx-DMA will transfer the packet from RxFIFO
<> 144:ef7eb2e8f9f7 676 to the driver receive buffers memory.
<> 144:ef7eb2e8f9f7 677
<> 144:ef7eb2e8f9f7 678 Depending on the size of the received Ethernet packet and the size of
<> 144:ef7eb2e8f9f7 679 each Ethernet driver receive buffer, the received packet can take one or more
<> 144:ef7eb2e8f9f7 680 Ethernet driver receive buffer.
<> 144:ef7eb2e8f9f7 681
<> 144:ef7eb2e8f9f7 682 In below are defined the size of one Ethernet driver receive buffer ETH_RX_BUF_SIZE
<> 144:ef7eb2e8f9f7 683 and the total count of the driver receive buffers ETH_RXBUFNB.
<> 144:ef7eb2e8f9f7 684
<> 144:ef7eb2e8f9f7 685 The configured value for ETH_RX_BUF_SIZE and ETH_RXBUFNB are only provided as
<> 144:ef7eb2e8f9f7 686 example, they can be reconfigured in the application layer to fit the application
<> 144:ef7eb2e8f9f7 687 needs */
<> 144:ef7eb2e8f9f7 688
<> 144:ef7eb2e8f9f7 689 /* Here we configure each Ethernet driver receive buffer to fit the Max size Ethernet
<> 144:ef7eb2e8f9f7 690 packet */
<> 144:ef7eb2e8f9f7 691 #ifndef ETH_RX_BUF_SIZE
<> 144:ef7eb2e8f9f7 692 #define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE
<> 144:ef7eb2e8f9f7 693 #endif
<> 144:ef7eb2e8f9f7 694
<> 144:ef7eb2e8f9f7 695 /* 5 Ethernet driver receive buffers are used (in a chained linked list)*/
<> 144:ef7eb2e8f9f7 696 #ifndef ETH_RXBUFNB
<> 157:ff67d9f36b67 697 #define ETH_RXBUFNB ((uint32_t)5U) /* 5 Rx buffers of size ETH_RX_BUF_SIZE */
<> 144:ef7eb2e8f9f7 698 #endif
<> 144:ef7eb2e8f9f7 699
<> 144:ef7eb2e8f9f7 700
<> 144:ef7eb2e8f9f7 701 /* Ethernet driver transmit buffers are organized in a chained linked-list, when
<> 144:ef7eb2e8f9f7 702 an Ethernet packet is transmitted, Tx-DMA will transfer the packet from the
<> 144:ef7eb2e8f9f7 703 driver transmit buffers memory to the TxFIFO.
<> 144:ef7eb2e8f9f7 704
<> 144:ef7eb2e8f9f7 705 Depending on the size of the Ethernet packet to be transmitted and the size of
<> 144:ef7eb2e8f9f7 706 each Ethernet driver transmit buffer, the packet to be transmitted can take
<> 144:ef7eb2e8f9f7 707 one or more Ethernet driver transmit buffer.
<> 144:ef7eb2e8f9f7 708
<> 144:ef7eb2e8f9f7 709 In below are defined the size of one Ethernet driver transmit buffer ETH_TX_BUF_SIZE
<> 144:ef7eb2e8f9f7 710 and the total count of the driver transmit buffers ETH_TXBUFNB.
<> 144:ef7eb2e8f9f7 711
<> 144:ef7eb2e8f9f7 712 The configured value for ETH_TX_BUF_SIZE and ETH_TXBUFNB are only provided as
<> 144:ef7eb2e8f9f7 713 example, they can be reconfigured in the application layer to fit the application
<> 144:ef7eb2e8f9f7 714 needs */
<> 144:ef7eb2e8f9f7 715
<> 144:ef7eb2e8f9f7 716 /* Here we configure each Ethernet driver transmit buffer to fit the Max size Ethernet
<> 144:ef7eb2e8f9f7 717 packet */
<> 144:ef7eb2e8f9f7 718 #ifndef ETH_TX_BUF_SIZE
<> 144:ef7eb2e8f9f7 719 #define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE
<> 144:ef7eb2e8f9f7 720 #endif
<> 144:ef7eb2e8f9f7 721
<> 144:ef7eb2e8f9f7 722 /* 5 Ethernet driver transmit buffers are used (in a chained linked list)*/
<> 144:ef7eb2e8f9f7 723 #ifndef ETH_TXBUFNB
<> 157:ff67d9f36b67 724 #define ETH_TXBUFNB ((uint32_t)5U) /* 5 Tx buffers of size ETH_TX_BUF_SIZE */
<> 144:ef7eb2e8f9f7 725 #endif
<> 144:ef7eb2e8f9f7 726
<> 144:ef7eb2e8f9f7 727 /**
<> 144:ef7eb2e8f9f7 728 * @}
<> 144:ef7eb2e8f9f7 729 */
<> 144:ef7eb2e8f9f7 730
<> 144:ef7eb2e8f9f7 731 /** @defgroup ETH_DMA_TX_Descriptor ETH DMA TX Descriptor
<> 144:ef7eb2e8f9f7 732 * @{
<> 144:ef7eb2e8f9f7 733 */
<> 144:ef7eb2e8f9f7 734
<> 144:ef7eb2e8f9f7 735 /*
<> 144:ef7eb2e8f9f7 736 DMA Tx Descriptor
<> 144:ef7eb2e8f9f7 737 -----------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 738 TDES0 | OWN(31) | CTRL[30:26] | Reserved[25:24] | CTRL[23:20] | Reserved[19:17] | Status[16:0] |
<> 144:ef7eb2e8f9f7 739 -----------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 740 TDES1 | Reserved[31:29] | Buffer2 ByteCount[28:16] | Reserved[15:13] | Buffer1 ByteCount[12:0] |
<> 144:ef7eb2e8f9f7 741 -----------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 742 TDES2 | Buffer1 Address [31:0] |
<> 144:ef7eb2e8f9f7 743 -----------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 744 TDES3 | Buffer2 Address [31:0] / Next Descriptor Address [31:0] |
<> 144:ef7eb2e8f9f7 745 -----------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 746 */
<> 144:ef7eb2e8f9f7 747
<> 144:ef7eb2e8f9f7 748 /**
<> 144:ef7eb2e8f9f7 749 * @brief Bit definition of TDES0 register: DMA Tx descriptor status register
<> 144:ef7eb2e8f9f7 750 */
<> 144:ef7eb2e8f9f7 751 #define ETH_DMATXDESC_OWN ((uint32_t)0x80000000U) /*!< OWN bit: descriptor is owned by DMA engine */
<> 144:ef7eb2e8f9f7 752 #define ETH_DMATXDESC_IC ((uint32_t)0x40000000U) /*!< Interrupt on Completion */
<> 144:ef7eb2e8f9f7 753 #define ETH_DMATXDESC_LS ((uint32_t)0x20000000U) /*!< Last Segment */
<> 144:ef7eb2e8f9f7 754 #define ETH_DMATXDESC_FS ((uint32_t)0x10000000U) /*!< First Segment */
<> 144:ef7eb2e8f9f7 755 #define ETH_DMATXDESC_DC ((uint32_t)0x08000000U) /*!< Disable CRC */
<> 144:ef7eb2e8f9f7 756 #define ETH_DMATXDESC_DP ((uint32_t)0x04000000U) /*!< Disable Padding */
<> 144:ef7eb2e8f9f7 757 #define ETH_DMATXDESC_TTSE ((uint32_t)0x02000000U) /*!< Transmit Time Stamp Enable */
<> 144:ef7eb2e8f9f7 758 #define ETH_DMATXDESC_CIC ((uint32_t)0x00C00000U) /*!< Checksum Insertion Control: 4 cases */
<> 144:ef7eb2e8f9f7 759 #define ETH_DMATXDESC_CIC_BYPASS ((uint32_t)0x00000000U) /*!< Do Nothing: Checksum Engine is bypassed */
<> 144:ef7eb2e8f9f7 760 #define ETH_DMATXDESC_CIC_IPV4HEADER ((uint32_t)0x00400000U) /*!< IPV4 header Checksum Insertion */
<> 144:ef7eb2e8f9f7 761 #define ETH_DMATXDESC_CIC_TCPUDPICMP_SEGMENT ((uint32_t)0x00800000U) /*!< TCP/UDP/ICMP Checksum Insertion calculated over segment only */
<> 144:ef7eb2e8f9f7 762 #define ETH_DMATXDESC_CIC_TCPUDPICMP_FULL ((uint32_t)0x00C00000U) /*!< TCP/UDP/ICMP Checksum Insertion fully calculated */
<> 144:ef7eb2e8f9f7 763 #define ETH_DMATXDESC_TER ((uint32_t)0x00200000U) /*!< Transmit End of Ring */
<> 144:ef7eb2e8f9f7 764 #define ETH_DMATXDESC_TCH ((uint32_t)0x00100000U) /*!< Second Address Chained */
<> 144:ef7eb2e8f9f7 765 #define ETH_DMATXDESC_TTSS ((uint32_t)0x00020000U) /*!< Tx Time Stamp Status */
<> 144:ef7eb2e8f9f7 766 #define ETH_DMATXDESC_IHE ((uint32_t)0x00010000U) /*!< IP Header Error */
<> 144:ef7eb2e8f9f7 767 #define ETH_DMATXDESC_ES ((uint32_t)0x00008000U) /*!< Error summary: OR of the following bits: UE || ED || EC || LCO || NC || LCA || FF || JT */
<> 144:ef7eb2e8f9f7 768 #define ETH_DMATXDESC_JT ((uint32_t)0x00004000U) /*!< Jabber Timeout */
<> 144:ef7eb2e8f9f7 769 #define ETH_DMATXDESC_FF ((uint32_t)0x00002000U) /*!< Frame Flushed: DMA/MTL flushed the frame due to SW flush */
<> 144:ef7eb2e8f9f7 770 #define ETH_DMATXDESC_PCE ((uint32_t)0x00001000U) /*!< Payload Checksum Error */
<> 144:ef7eb2e8f9f7 771 #define ETH_DMATXDESC_LCA ((uint32_t)0x00000800U) /*!< Loss of Carrier: carrier lost during transmission */
<> 144:ef7eb2e8f9f7 772 #define ETH_DMATXDESC_NC ((uint32_t)0x00000400U) /*!< No Carrier: no carrier signal from the transceiver */
<> 144:ef7eb2e8f9f7 773 #define ETH_DMATXDESC_LCO ((uint32_t)0x00000200U) /*!< Late Collision: transmission aborted due to collision */
<> 144:ef7eb2e8f9f7 774 #define ETH_DMATXDESC_EC ((uint32_t)0x00000100U) /*!< Excessive Collision: transmission aborted after 16 collisions */
<> 144:ef7eb2e8f9f7 775 #define ETH_DMATXDESC_VF ((uint32_t)0x00000080U) /*!< VLAN Frame */
<> 144:ef7eb2e8f9f7 776 #define ETH_DMATXDESC_CC ((uint32_t)0x00000078U) /*!< Collision Count */
<> 144:ef7eb2e8f9f7 777 #define ETH_DMATXDESC_ED ((uint32_t)0x00000004U) /*!< Excessive Deferral */
<> 144:ef7eb2e8f9f7 778 #define ETH_DMATXDESC_UF ((uint32_t)0x00000002U) /*!< Underflow Error: late data arrival from the memory */
<> 144:ef7eb2e8f9f7 779 #define ETH_DMATXDESC_DB ((uint32_t)0x00000001U) /*!< Deferred Bit */
<> 144:ef7eb2e8f9f7 780
<> 144:ef7eb2e8f9f7 781 /**
<> 144:ef7eb2e8f9f7 782 * @brief Bit definition of TDES1 register
<> 144:ef7eb2e8f9f7 783 */
<> 144:ef7eb2e8f9f7 784 #define ETH_DMATXDESC_TBS2 ((uint32_t)0x1FFF0000U) /*!< Transmit Buffer2 Size */
<> 144:ef7eb2e8f9f7 785 #define ETH_DMATXDESC_TBS1 ((uint32_t)0x00001FFFU) /*!< Transmit Buffer1 Size */
<> 144:ef7eb2e8f9f7 786
<> 144:ef7eb2e8f9f7 787 /**
<> 144:ef7eb2e8f9f7 788 * @brief Bit definition of TDES2 register
<> 144:ef7eb2e8f9f7 789 */
<> 144:ef7eb2e8f9f7 790 #define ETH_DMATXDESC_B1AP ((uint32_t)0xFFFFFFFFU) /*!< Buffer1 Address Pointer */
<> 144:ef7eb2e8f9f7 791
<> 144:ef7eb2e8f9f7 792 /**
<> 144:ef7eb2e8f9f7 793 * @brief Bit definition of TDES3 register
<> 144:ef7eb2e8f9f7 794 */
<> 144:ef7eb2e8f9f7 795 #define ETH_DMATXDESC_B2AP ((uint32_t)0xFFFFFFFFU) /*!< Buffer2 Address Pointer */
<> 144:ef7eb2e8f9f7 796
<> 144:ef7eb2e8f9f7 797 /*---------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 798 TDES6 | Transmit Time Stamp Low [31:0] |
<> 144:ef7eb2e8f9f7 799 -----------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 800 TDES7 | Transmit Time Stamp High [31:0] |
<> 144:ef7eb2e8f9f7 801 ----------------------------------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 802
<> 144:ef7eb2e8f9f7 803 /* Bit definition of TDES6 register */
<> 144:ef7eb2e8f9f7 804 #define ETH_DMAPTPTXDESC_TTSL ((uint32_t)0xFFFFFFFFU) /* Transmit Time Stamp Low */
<> 144:ef7eb2e8f9f7 805
<> 144:ef7eb2e8f9f7 806 /* Bit definition of TDES7 register */
<> 144:ef7eb2e8f9f7 807 #define ETH_DMAPTPTXDESC_TTSH ((uint32_t)0xFFFFFFFFU) /* Transmit Time Stamp High */
<> 144:ef7eb2e8f9f7 808
<> 144:ef7eb2e8f9f7 809 /**
<> 144:ef7eb2e8f9f7 810 * @}
<> 144:ef7eb2e8f9f7 811 */
<> 144:ef7eb2e8f9f7 812 /** @defgroup ETH_DMA_RX_Descriptor ETH DMA RX Descriptor
<> 144:ef7eb2e8f9f7 813 * @{
<> 144:ef7eb2e8f9f7 814 */
<> 144:ef7eb2e8f9f7 815
<> 144:ef7eb2e8f9f7 816 /*
<> 144:ef7eb2e8f9f7 817 DMA Rx Descriptor
<> 144:ef7eb2e8f9f7 818 --------------------------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 819 RDES0 | OWN(31) | Status [30:0] |
<> 144:ef7eb2e8f9f7 820 ---------------------------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 821 RDES1 | CTRL(31) | Reserved[30:29] | Buffer2 ByteCount[28:16] | CTRL[15:14] | Reserved(13) | Buffer1 ByteCount[12:0] |
<> 144:ef7eb2e8f9f7 822 ---------------------------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 823 RDES2 | Buffer1 Address [31:0] |
<> 144:ef7eb2e8f9f7 824 ---------------------------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 825 RDES3 | Buffer2 Address [31:0] / Next Descriptor Address [31:0] |
<> 144:ef7eb2e8f9f7 826 ---------------------------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 827 */
<> 144:ef7eb2e8f9f7 828
<> 144:ef7eb2e8f9f7 829 /**
<> 144:ef7eb2e8f9f7 830 * @brief Bit definition of RDES0 register: DMA Rx descriptor status register
<> 144:ef7eb2e8f9f7 831 */
<> 144:ef7eb2e8f9f7 832 #define ETH_DMARXDESC_OWN ((uint32_t)0x80000000U) /*!< OWN bit: descriptor is owned by DMA engine */
<> 144:ef7eb2e8f9f7 833 #define ETH_DMARXDESC_AFM ((uint32_t)0x40000000U) /*!< DA Filter Fail for the rx frame */
<> 144:ef7eb2e8f9f7 834 #define ETH_DMARXDESC_FL ((uint32_t)0x3FFF0000U) /*!< Receive descriptor frame length */
<> 144:ef7eb2e8f9f7 835 #define ETH_DMARXDESC_ES ((uint32_t)0x00008000U) /*!< Error summary: OR of the following bits: DE || OE || IPC || LC || RWT || RE || CE */
<> 144:ef7eb2e8f9f7 836 #define ETH_DMARXDESC_DE ((uint32_t)0x00004000U) /*!< Descriptor error: no more descriptors for receive frame */
<> 144:ef7eb2e8f9f7 837 #define ETH_DMARXDESC_SAF ((uint32_t)0x00002000U) /*!< SA Filter Fail for the received frame */
<> 144:ef7eb2e8f9f7 838 #define ETH_DMARXDESC_LE ((uint32_t)0x00001000U) /*!< Frame size not matching with length field */
<> 144:ef7eb2e8f9f7 839 #define ETH_DMARXDESC_OE ((uint32_t)0x00000800U) /*!< Overflow Error: Frame was damaged due to buffer overflow */
<> 144:ef7eb2e8f9f7 840 #define ETH_DMARXDESC_VLAN ((uint32_t)0x00000400U) /*!< VLAN Tag: received frame is a VLAN frame */
<> 144:ef7eb2e8f9f7 841 #define ETH_DMARXDESC_FS ((uint32_t)0x00000200U) /*!< First descriptor of the frame */
<> 144:ef7eb2e8f9f7 842 #define ETH_DMARXDESC_LS ((uint32_t)0x00000100U) /*!< Last descriptor of the frame */
<> 144:ef7eb2e8f9f7 843 #define ETH_DMARXDESC_IPV4HCE ((uint32_t)0x00000080U) /*!< IPC Checksum Error: Rx Ipv4 header checksum error */
<> 144:ef7eb2e8f9f7 844 #define ETH_DMARXDESC_LC ((uint32_t)0x00000040U) /*!< Late collision occurred during reception */
<> 144:ef7eb2e8f9f7 845 #define ETH_DMARXDESC_FT ((uint32_t)0x00000020U) /*!< Frame type - Ethernet, otherwise 802.3 */
<> 144:ef7eb2e8f9f7 846 #define ETH_DMARXDESC_RWT ((uint32_t)0x00000010U) /*!< Receive Watchdog Timeout: watchdog timer expired during reception */
<> 144:ef7eb2e8f9f7 847 #define ETH_DMARXDESC_RE ((uint32_t)0x00000008U) /*!< Receive error: error reported by MII interface */
<> 144:ef7eb2e8f9f7 848 #define ETH_DMARXDESC_DBE ((uint32_t)0x00000004U) /*!< Dribble bit error: frame contains non int multiple of 8 bits */
<> 144:ef7eb2e8f9f7 849 #define ETH_DMARXDESC_CE ((uint32_t)0x00000002U) /*!< CRC error */
<> 144:ef7eb2e8f9f7 850 #define ETH_DMARXDESC_MAMPCE ((uint32_t)0x00000001U) /*!< Rx MAC Address/Payload Checksum Error: Rx MAC address matched/ Rx Payload Checksum Error */
<> 144:ef7eb2e8f9f7 851
<> 144:ef7eb2e8f9f7 852 /**
<> 144:ef7eb2e8f9f7 853 * @brief Bit definition of RDES1 register
<> 144:ef7eb2e8f9f7 854 */
<> 144:ef7eb2e8f9f7 855 #define ETH_DMARXDESC_DIC ((uint32_t)0x80000000U) /*!< Disable Interrupt on Completion */
<> 144:ef7eb2e8f9f7 856 #define ETH_DMARXDESC_RBS2 ((uint32_t)0x1FFF0000U) /*!< Receive Buffer2 Size */
<> 144:ef7eb2e8f9f7 857 #define ETH_DMARXDESC_RER ((uint32_t)0x00008000U) /*!< Receive End of Ring */
<> 144:ef7eb2e8f9f7 858 #define ETH_DMARXDESC_RCH ((uint32_t)0x00004000U) /*!< Second Address Chained */
<> 144:ef7eb2e8f9f7 859 #define ETH_DMARXDESC_RBS1 ((uint32_t)0x00001FFFU) /*!< Receive Buffer1 Size */
<> 144:ef7eb2e8f9f7 860
<> 144:ef7eb2e8f9f7 861 /**
<> 144:ef7eb2e8f9f7 862 * @brief Bit definition of RDES2 register
<> 144:ef7eb2e8f9f7 863 */
<> 144:ef7eb2e8f9f7 864 #define ETH_DMARXDESC_B1AP ((uint32_t)0xFFFFFFFFU) /*!< Buffer1 Address Pointer */
<> 144:ef7eb2e8f9f7 865
<> 144:ef7eb2e8f9f7 866 /**
<> 144:ef7eb2e8f9f7 867 * @brief Bit definition of RDES3 register
<> 144:ef7eb2e8f9f7 868 */
<> 144:ef7eb2e8f9f7 869 #define ETH_DMARXDESC_B2AP ((uint32_t)0xFFFFFFFFU) /*!< Buffer2 Address Pointer */
<> 144:ef7eb2e8f9f7 870
<> 144:ef7eb2e8f9f7 871 /*---------------------------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 872 RDES4 | Reserved[31:15] | Extended Status [14:0] |
<> 144:ef7eb2e8f9f7 873 ---------------------------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 874 RDES5 | Reserved[31:0] |
<> 144:ef7eb2e8f9f7 875 ---------------------------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 876 RDES6 | Receive Time Stamp Low [31:0] |
<> 144:ef7eb2e8f9f7 877 ---------------------------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 878 RDES7 | Receive Time Stamp High [31:0] |
<> 144:ef7eb2e8f9f7 879 --------------------------------------------------------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 880
<> 144:ef7eb2e8f9f7 881 /* Bit definition of RDES4 register */
<> 144:ef7eb2e8f9f7 882 #define ETH_DMAPTPRXDESC_PTPV ((uint32_t)0x00002000U) /* PTP Version */
<> 144:ef7eb2e8f9f7 883 #define ETH_DMAPTPRXDESC_PTPFT ((uint32_t)0x00001000U) /* PTP Frame Type */
<> 144:ef7eb2e8f9f7 884 #define ETH_DMAPTPRXDESC_PTPMT ((uint32_t)0x00000F00U) /* PTP Message Type */
<> 144:ef7eb2e8f9f7 885 #define ETH_DMAPTPRXDESC_PTPMT_SYNC ((uint32_t)0x00000100U) /* SYNC message (all clock types) */
<> 144:ef7eb2e8f9f7 886 #define ETH_DMAPTPRXDESC_PTPMT_FOLLOWUP ((uint32_t)0x00000200U) /* FollowUp message (all clock types) */
<> 144:ef7eb2e8f9f7 887 #define ETH_DMAPTPRXDESC_PTPMT_DELAYREQ ((uint32_t)0x00000300U) /* DelayReq message (all clock types) */
<> 144:ef7eb2e8f9f7 888 #define ETH_DMAPTPRXDESC_PTPMT_DELAYRESP ((uint32_t)0x00000400U) /* DelayResp message (all clock types) */
<> 144:ef7eb2e8f9f7 889 #define ETH_DMAPTPRXDESC_PTPMT_PDELAYREQ_ANNOUNCE ((uint32_t)0x00000500U) /* PdelayReq message (peer-to-peer transparent clock) or Announce message (Ordinary or Boundary clock) */
<> 144:ef7eb2e8f9f7 890 #define ETH_DMAPTPRXDESC_PTPMT_PDELAYRESP_MANAG ((uint32_t)0x00000600U) /* PdelayResp message (peer-to-peer transparent clock) or Management message (Ordinary or Boundary clock) */
<> 144:ef7eb2e8f9f7 891 #define ETH_DMAPTPRXDESC_PTPMT_PDELAYRESPFOLLOWUP_SIGNAL ((uint32_t)0x00000700U) /* PdelayRespFollowUp message (peer-to-peer transparent clock) or Signaling message (Ordinary or Boundary clock) */
<> 144:ef7eb2e8f9f7 892 #define ETH_DMAPTPRXDESC_IPV6PR ((uint32_t)0x00000080U) /* IPv6 Packet Received */
<> 144:ef7eb2e8f9f7 893 #define ETH_DMAPTPRXDESC_IPV4PR ((uint32_t)0x00000040U) /* IPv4 Packet Received */
<> 144:ef7eb2e8f9f7 894 #define ETH_DMAPTPRXDESC_IPCB ((uint32_t)0x00000020U) /* IP Checksum Bypassed */
<> 144:ef7eb2e8f9f7 895 #define ETH_DMAPTPRXDESC_IPPE ((uint32_t)0x00000010U) /* IP Payload Error */
<> 144:ef7eb2e8f9f7 896 #define ETH_DMAPTPRXDESC_IPHE ((uint32_t)0x00000008U) /* IP Header Error */
<> 144:ef7eb2e8f9f7 897 #define ETH_DMAPTPRXDESC_IPPT ((uint32_t)0x00000007U) /* IP Payload Type */
<> 144:ef7eb2e8f9f7 898 #define ETH_DMAPTPRXDESC_IPPT_UDP ((uint32_t)0x00000001U) /* UDP payload encapsulated in the IP datagram */
<> 144:ef7eb2e8f9f7 899 #define ETH_DMAPTPRXDESC_IPPT_TCP ((uint32_t)0x00000002U) /* TCP payload encapsulated in the IP datagram */
<> 144:ef7eb2e8f9f7 900 #define ETH_DMAPTPRXDESC_IPPT_ICMP ((uint32_t)0x00000003U) /* ICMP payload encapsulated in the IP datagram */
<> 144:ef7eb2e8f9f7 901
<> 144:ef7eb2e8f9f7 902 /* Bit definition of RDES6 register */
<> 144:ef7eb2e8f9f7 903 #define ETH_DMAPTPRXDESC_RTSL ((uint32_t)0xFFFFFFFFU) /* Receive Time Stamp Low */
<> 144:ef7eb2e8f9f7 904
<> 144:ef7eb2e8f9f7 905 /* Bit definition of RDES7 register */
<> 144:ef7eb2e8f9f7 906 #define ETH_DMAPTPRXDESC_RTSH ((uint32_t)0xFFFFFFFFU) /* Receive Time Stamp High */
<> 144:ef7eb2e8f9f7 907 /**
<> 144:ef7eb2e8f9f7 908 * @}
<> 144:ef7eb2e8f9f7 909 */
<> 144:ef7eb2e8f9f7 910 /** @defgroup ETH_AutoNegotiation ETH AutoNegotiation
<> 144:ef7eb2e8f9f7 911 * @{
<> 144:ef7eb2e8f9f7 912 */
<> 144:ef7eb2e8f9f7 913 #define ETH_AUTONEGOTIATION_ENABLE ((uint32_t)0x00000001U)
<> 144:ef7eb2e8f9f7 914 #define ETH_AUTONEGOTIATION_DISABLE ((uint32_t)0x00000000U)
<> 144:ef7eb2e8f9f7 915
<> 144:ef7eb2e8f9f7 916 /**
<> 144:ef7eb2e8f9f7 917 * @}
<> 144:ef7eb2e8f9f7 918 */
<> 144:ef7eb2e8f9f7 919 /** @defgroup ETH_Speed ETH Speed
<> 144:ef7eb2e8f9f7 920 * @{
<> 144:ef7eb2e8f9f7 921 */
<> 144:ef7eb2e8f9f7 922 #define ETH_SPEED_10M ((uint32_t)0x00000000U)
<> 144:ef7eb2e8f9f7 923 #define ETH_SPEED_100M ((uint32_t)0x00004000U)
<> 144:ef7eb2e8f9f7 924
<> 144:ef7eb2e8f9f7 925 /**
<> 144:ef7eb2e8f9f7 926 * @}
<> 144:ef7eb2e8f9f7 927 */
<> 144:ef7eb2e8f9f7 928 /** @defgroup ETH_Duplex_Mode ETH Duplex Mode
<> 144:ef7eb2e8f9f7 929 * @{
<> 144:ef7eb2e8f9f7 930 */
<> 144:ef7eb2e8f9f7 931 #define ETH_MODE_FULLDUPLEX ((uint32_t)0x00000800U)
<> 144:ef7eb2e8f9f7 932 #define ETH_MODE_HALFDUPLEX ((uint32_t)0x00000000U)
<> 144:ef7eb2e8f9f7 933 /**
<> 144:ef7eb2e8f9f7 934 * @}
<> 144:ef7eb2e8f9f7 935 */
<> 144:ef7eb2e8f9f7 936 /** @defgroup ETH_Rx_Mode ETH Rx Mode
<> 144:ef7eb2e8f9f7 937 * @{
<> 144:ef7eb2e8f9f7 938 */
<> 144:ef7eb2e8f9f7 939 #define ETH_RXPOLLING_MODE ((uint32_t)0x00000000U)
<> 144:ef7eb2e8f9f7 940 #define ETH_RXINTERRUPT_MODE ((uint32_t)0x00000001U)
<> 144:ef7eb2e8f9f7 941 /**
<> 144:ef7eb2e8f9f7 942 * @}
<> 144:ef7eb2e8f9f7 943 */
<> 144:ef7eb2e8f9f7 944
<> 144:ef7eb2e8f9f7 945 /** @defgroup ETH_Checksum_Mode ETH Checksum Mode
<> 144:ef7eb2e8f9f7 946 * @{
<> 144:ef7eb2e8f9f7 947 */
<> 144:ef7eb2e8f9f7 948 #define ETH_CHECKSUM_BY_HARDWARE ((uint32_t)0x00000000U)
<> 144:ef7eb2e8f9f7 949 #define ETH_CHECKSUM_BY_SOFTWARE ((uint32_t)0x00000001U)
<> 144:ef7eb2e8f9f7 950 /**
<> 144:ef7eb2e8f9f7 951 * @}
<> 144:ef7eb2e8f9f7 952 */
<> 144:ef7eb2e8f9f7 953
<> 144:ef7eb2e8f9f7 954 /** @defgroup ETH_Media_Interface ETH Media Interface
<> 144:ef7eb2e8f9f7 955 * @{
<> 144:ef7eb2e8f9f7 956 */
<> 144:ef7eb2e8f9f7 957 #define ETH_MEDIA_INTERFACE_MII ((uint32_t)0x00000000U)
<> 144:ef7eb2e8f9f7 958 #define ETH_MEDIA_INTERFACE_RMII ((uint32_t)SYSCFG_PMC_MII_RMII_SEL)
<> 144:ef7eb2e8f9f7 959 /**
<> 144:ef7eb2e8f9f7 960 * @}
<> 144:ef7eb2e8f9f7 961 */
<> 144:ef7eb2e8f9f7 962
<> 144:ef7eb2e8f9f7 963 /** @defgroup ETH_Watchdog ETH Watchdog
<> 144:ef7eb2e8f9f7 964 * @{
<> 144:ef7eb2e8f9f7 965 */
<> 144:ef7eb2e8f9f7 966 #define ETH_WATCHDOG_ENABLE ((uint32_t)0x00000000U)
<> 144:ef7eb2e8f9f7 967 #define ETH_WATCHDOG_DISABLE ((uint32_t)0x00800000U)
<> 144:ef7eb2e8f9f7 968 /**
<> 144:ef7eb2e8f9f7 969 * @}
<> 144:ef7eb2e8f9f7 970 */
<> 144:ef7eb2e8f9f7 971
<> 144:ef7eb2e8f9f7 972 /** @defgroup ETH_Jabber ETH Jabber
<> 144:ef7eb2e8f9f7 973 * @{
<> 144:ef7eb2e8f9f7 974 */
<> 144:ef7eb2e8f9f7 975 #define ETH_JABBER_ENABLE ((uint32_t)0x00000000U)
<> 144:ef7eb2e8f9f7 976 #define ETH_JABBER_DISABLE ((uint32_t)0x00400000U)
<> 144:ef7eb2e8f9f7 977 /**
<> 144:ef7eb2e8f9f7 978 * @}
<> 144:ef7eb2e8f9f7 979 */
<> 144:ef7eb2e8f9f7 980
<> 144:ef7eb2e8f9f7 981 /** @defgroup ETH_Inter_Frame_Gap ETH Inter Frame Gap
<> 144:ef7eb2e8f9f7 982 * @{
<> 144:ef7eb2e8f9f7 983 */
<> 144:ef7eb2e8f9f7 984 #define ETH_INTERFRAMEGAP_96BIT ((uint32_t)0x00000000U) /*!< minimum IFG between frames during transmission is 96Bit */
<> 144:ef7eb2e8f9f7 985 #define ETH_INTERFRAMEGAP_88BIT ((uint32_t)0x00020000U) /*!< minimum IFG between frames during transmission is 88Bit */
<> 144:ef7eb2e8f9f7 986 #define ETH_INTERFRAMEGAP_80BIT ((uint32_t)0x00040000U) /*!< minimum IFG between frames during transmission is 80Bit */
<> 144:ef7eb2e8f9f7 987 #define ETH_INTERFRAMEGAP_72BIT ((uint32_t)0x00060000U) /*!< minimum IFG between frames during transmission is 72Bit */
<> 144:ef7eb2e8f9f7 988 #define ETH_INTERFRAMEGAP_64BIT ((uint32_t)0x00080000U) /*!< minimum IFG between frames during transmission is 64Bit */
<> 144:ef7eb2e8f9f7 989 #define ETH_INTERFRAMEGAP_56BIT ((uint32_t)0x000A0000U) /*!< minimum IFG between frames during transmission is 56Bit */
<> 144:ef7eb2e8f9f7 990 #define ETH_INTERFRAMEGAP_48BIT ((uint32_t)0x000C0000U) /*!< minimum IFG between frames during transmission is 48Bit */
<> 144:ef7eb2e8f9f7 991 #define ETH_INTERFRAMEGAP_40BIT ((uint32_t)0x000E0000U) /*!< minimum IFG between frames during transmission is 40Bit */
<> 144:ef7eb2e8f9f7 992 /**
<> 144:ef7eb2e8f9f7 993 * @}
<> 144:ef7eb2e8f9f7 994 */
<> 144:ef7eb2e8f9f7 995
<> 144:ef7eb2e8f9f7 996 /** @defgroup ETH_Carrier_Sense ETH Carrier Sense
<> 144:ef7eb2e8f9f7 997 * @{
<> 144:ef7eb2e8f9f7 998 */
<> 144:ef7eb2e8f9f7 999 #define ETH_CARRIERSENCE_ENABLE ((uint32_t)0x00000000U)
<> 144:ef7eb2e8f9f7 1000 #define ETH_CARRIERSENCE_DISABLE ((uint32_t)0x00010000U)
<> 144:ef7eb2e8f9f7 1001 /**
<> 144:ef7eb2e8f9f7 1002 * @}
<> 144:ef7eb2e8f9f7 1003 */
<> 144:ef7eb2e8f9f7 1004
<> 144:ef7eb2e8f9f7 1005 /** @defgroup ETH_Receive_Own ETH Receive Own
<> 144:ef7eb2e8f9f7 1006 * @{
<> 144:ef7eb2e8f9f7 1007 */
<> 144:ef7eb2e8f9f7 1008 #define ETH_RECEIVEOWN_ENABLE ((uint32_t)0x00000000U)
<> 144:ef7eb2e8f9f7 1009 #define ETH_RECEIVEOWN_DISABLE ((uint32_t)0x00002000U)
<> 144:ef7eb2e8f9f7 1010 /**
<> 144:ef7eb2e8f9f7 1011 * @}
<> 144:ef7eb2e8f9f7 1012 */
<> 144:ef7eb2e8f9f7 1013
<> 144:ef7eb2e8f9f7 1014 /** @defgroup ETH_Loop_Back_Mode ETH Loop Back Mode
<> 144:ef7eb2e8f9f7 1015 * @{
<> 144:ef7eb2e8f9f7 1016 */
<> 144:ef7eb2e8f9f7 1017 #define ETH_LOOPBACKMODE_ENABLE ((uint32_t)0x00001000U)
<> 144:ef7eb2e8f9f7 1018 #define ETH_LOOPBACKMODE_DISABLE ((uint32_t)0x00000000U)
<> 144:ef7eb2e8f9f7 1019 /**
<> 144:ef7eb2e8f9f7 1020 * @}
<> 144:ef7eb2e8f9f7 1021 */
<> 144:ef7eb2e8f9f7 1022
<> 144:ef7eb2e8f9f7 1023 /** @defgroup ETH_Checksum_Offload ETH Checksum Offload
<> 144:ef7eb2e8f9f7 1024 * @{
<> 144:ef7eb2e8f9f7 1025 */
<> 144:ef7eb2e8f9f7 1026 #define ETH_CHECKSUMOFFLAOD_ENABLE ((uint32_t)0x00000400U)
<> 144:ef7eb2e8f9f7 1027 #define ETH_CHECKSUMOFFLAOD_DISABLE ((uint32_t)0x00000000U)
<> 144:ef7eb2e8f9f7 1028 /**
<> 144:ef7eb2e8f9f7 1029 * @}
<> 144:ef7eb2e8f9f7 1030 */
<> 144:ef7eb2e8f9f7 1031
<> 144:ef7eb2e8f9f7 1032 /** @defgroup ETH_Retry_Transmission ETH Retry Transmission
<> 144:ef7eb2e8f9f7 1033 * @{
<> 144:ef7eb2e8f9f7 1034 */
<> 144:ef7eb2e8f9f7 1035 #define ETH_RETRYTRANSMISSION_ENABLE ((uint32_t)0x00000000U)
<> 144:ef7eb2e8f9f7 1036 #define ETH_RETRYTRANSMISSION_DISABLE ((uint32_t)0x00000200U)
<> 144:ef7eb2e8f9f7 1037 /**
<> 144:ef7eb2e8f9f7 1038 * @}
<> 144:ef7eb2e8f9f7 1039 */
<> 144:ef7eb2e8f9f7 1040
<> 144:ef7eb2e8f9f7 1041 /** @defgroup ETH_Automatic_Pad_CRC_Strip ETH Automatic Pad CRC Strip
<> 144:ef7eb2e8f9f7 1042 * @{
<> 144:ef7eb2e8f9f7 1043 */
<> 144:ef7eb2e8f9f7 1044 #define ETH_AUTOMATICPADCRCSTRIP_ENABLE ((uint32_t)0x00000080U)
<> 144:ef7eb2e8f9f7 1045 #define ETH_AUTOMATICPADCRCSTRIP_DISABLE ((uint32_t)0x00000000U)
<> 144:ef7eb2e8f9f7 1046 /**
<> 144:ef7eb2e8f9f7 1047 * @}
<> 144:ef7eb2e8f9f7 1048 */
<> 144:ef7eb2e8f9f7 1049
<> 144:ef7eb2e8f9f7 1050 /** @defgroup ETH_Back_Off_Limit ETH Back Off Limit
<> 144:ef7eb2e8f9f7 1051 * @{
<> 144:ef7eb2e8f9f7 1052 */
<> 144:ef7eb2e8f9f7 1053 #define ETH_BACKOFFLIMIT_10 ((uint32_t)0x00000000U)
<> 144:ef7eb2e8f9f7 1054 #define ETH_BACKOFFLIMIT_8 ((uint32_t)0x00000020U)
<> 144:ef7eb2e8f9f7 1055 #define ETH_BACKOFFLIMIT_4 ((uint32_t)0x00000040U)
<> 144:ef7eb2e8f9f7 1056 #define ETH_BACKOFFLIMIT_1 ((uint32_t)0x00000060U)
<> 144:ef7eb2e8f9f7 1057 /**
<> 144:ef7eb2e8f9f7 1058 * @}
<> 144:ef7eb2e8f9f7 1059 */
<> 144:ef7eb2e8f9f7 1060
<> 144:ef7eb2e8f9f7 1061 /** @defgroup ETH_Deferral_Check ETH Deferral Check
<> 144:ef7eb2e8f9f7 1062 * @{
<> 144:ef7eb2e8f9f7 1063 */
<> 144:ef7eb2e8f9f7 1064 #define ETH_DEFFERRALCHECK_ENABLE ((uint32_t)0x00000010U)
<> 144:ef7eb2e8f9f7 1065 #define ETH_DEFFERRALCHECK_DISABLE ((uint32_t)0x00000000U)
<> 144:ef7eb2e8f9f7 1066 /**
<> 144:ef7eb2e8f9f7 1067 * @}
<> 144:ef7eb2e8f9f7 1068 */
<> 144:ef7eb2e8f9f7 1069
<> 144:ef7eb2e8f9f7 1070 /** @defgroup ETH_Receive_All ETH Receive All
<> 144:ef7eb2e8f9f7 1071 * @{
<> 144:ef7eb2e8f9f7 1072 */
<> 144:ef7eb2e8f9f7 1073 #define ETH_RECEIVEALL_ENABLE ((uint32_t)0x80000000U)
<> 144:ef7eb2e8f9f7 1074 #define ETH_RECEIVEAll_DISABLE ((uint32_t)0x00000000U)
<> 144:ef7eb2e8f9f7 1075 /**
<> 144:ef7eb2e8f9f7 1076 * @}
<> 144:ef7eb2e8f9f7 1077 */
<> 144:ef7eb2e8f9f7 1078
<> 144:ef7eb2e8f9f7 1079 /** @defgroup ETH_Source_Addr_Filter ETH Source Addr Filter
<> 144:ef7eb2e8f9f7 1080 * @{
<> 144:ef7eb2e8f9f7 1081 */
<> 144:ef7eb2e8f9f7 1082 #define ETH_SOURCEADDRFILTER_NORMAL_ENABLE ((uint32_t)0x00000200U)
<> 144:ef7eb2e8f9f7 1083 #define ETH_SOURCEADDRFILTER_INVERSE_ENABLE ((uint32_t)0x00000300U)
<> 144:ef7eb2e8f9f7 1084 #define ETH_SOURCEADDRFILTER_DISABLE ((uint32_t)0x00000000U)
<> 144:ef7eb2e8f9f7 1085 /**
<> 144:ef7eb2e8f9f7 1086 * @}
<> 144:ef7eb2e8f9f7 1087 */
<> 144:ef7eb2e8f9f7 1088
<> 144:ef7eb2e8f9f7 1089 /** @defgroup ETH_Pass_Control_Frames ETH Pass Control Frames
<> 144:ef7eb2e8f9f7 1090 * @{
<> 144:ef7eb2e8f9f7 1091 */
<> 144:ef7eb2e8f9f7 1092 #define ETH_PASSCONTROLFRAMES_BLOCKALL ((uint32_t)0x00000040U) /*!< MAC filters all control frames from reaching the application */
<> 144:ef7eb2e8f9f7 1093 #define ETH_PASSCONTROLFRAMES_FORWARDALL ((uint32_t)0x00000080U) /*!< MAC forwards all control frames to application even if they fail the Address Filter */
<> 144:ef7eb2e8f9f7 1094 #define ETH_PASSCONTROLFRAMES_FORWARDPASSEDADDRFILTER ((uint32_t)0x000000C0U) /*!< MAC forwards control frames that pass the Address Filter. */
<> 144:ef7eb2e8f9f7 1095 /**
<> 144:ef7eb2e8f9f7 1096 * @}
<> 144:ef7eb2e8f9f7 1097 */
<> 144:ef7eb2e8f9f7 1098
<> 144:ef7eb2e8f9f7 1099 /** @defgroup ETH_Broadcast_Frames_Reception ETH Broadcast Frames Reception
<> 144:ef7eb2e8f9f7 1100 * @{
<> 144:ef7eb2e8f9f7 1101 */
<> 144:ef7eb2e8f9f7 1102 #define ETH_BROADCASTFRAMESRECEPTION_ENABLE ((uint32_t)0x00000000U)
<> 144:ef7eb2e8f9f7 1103 #define ETH_BROADCASTFRAMESRECEPTION_DISABLE ((uint32_t)0x00000020U)
<> 144:ef7eb2e8f9f7 1104 /**
<> 144:ef7eb2e8f9f7 1105 * @}
<> 144:ef7eb2e8f9f7 1106 */
<> 144:ef7eb2e8f9f7 1107
<> 144:ef7eb2e8f9f7 1108 /** @defgroup ETH_Destination_Addr_Filter ETH Destination Addr Filter
<> 144:ef7eb2e8f9f7 1109 * @{
<> 144:ef7eb2e8f9f7 1110 */
<> 144:ef7eb2e8f9f7 1111 #define ETH_DESTINATIONADDRFILTER_NORMAL ((uint32_t)0x00000000U)
<> 144:ef7eb2e8f9f7 1112 #define ETH_DESTINATIONADDRFILTER_INVERSE ((uint32_t)0x00000008U)
<> 144:ef7eb2e8f9f7 1113 /**
<> 144:ef7eb2e8f9f7 1114 * @}
<> 144:ef7eb2e8f9f7 1115 */
<> 144:ef7eb2e8f9f7 1116
<> 144:ef7eb2e8f9f7 1117 /** @defgroup ETH_Promiscuous_Mode ETH Promiscuous Mode
<> 144:ef7eb2e8f9f7 1118 * @{
<> 144:ef7eb2e8f9f7 1119 */
<> 144:ef7eb2e8f9f7 1120 #define ETH_PROMISCUOUS_MODE_ENABLE ((uint32_t)0x00000001U)
<> 144:ef7eb2e8f9f7 1121 #define ETH_PROMISCUOUS_MODE_DISABLE ((uint32_t)0x00000000U)
<> 144:ef7eb2e8f9f7 1122 /**
<> 144:ef7eb2e8f9f7 1123 * @}
<> 144:ef7eb2e8f9f7 1124 */
<> 144:ef7eb2e8f9f7 1125
<> 144:ef7eb2e8f9f7 1126 /** @defgroup ETH_Multicast_Frames_Filter ETH Multicast Frames Filter
<> 144:ef7eb2e8f9f7 1127 * @{
<> 144:ef7eb2e8f9f7 1128 */
<> 144:ef7eb2e8f9f7 1129 #define ETH_MULTICASTFRAMESFILTER_PERFECTHASHTABLE ((uint32_t)0x00000404U)
<> 144:ef7eb2e8f9f7 1130 #define ETH_MULTICASTFRAMESFILTER_HASHTABLE ((uint32_t)0x00000004U)
<> 144:ef7eb2e8f9f7 1131 #define ETH_MULTICASTFRAMESFILTER_PERFECT ((uint32_t)0x00000000U)
<> 144:ef7eb2e8f9f7 1132 #define ETH_MULTICASTFRAMESFILTER_NONE ((uint32_t)0x00000010U)
<> 144:ef7eb2e8f9f7 1133 /**
<> 144:ef7eb2e8f9f7 1134 * @}
<> 144:ef7eb2e8f9f7 1135 */
<> 144:ef7eb2e8f9f7 1136
<> 144:ef7eb2e8f9f7 1137 /** @defgroup ETH_Unicast_Frames_Filter ETH Unicast Frames Filter
<> 144:ef7eb2e8f9f7 1138 * @{
<> 144:ef7eb2e8f9f7 1139 */
<> 144:ef7eb2e8f9f7 1140 #define ETH_UNICASTFRAMESFILTER_PERFECTHASHTABLE ((uint32_t)0x00000402U)
<> 144:ef7eb2e8f9f7 1141 #define ETH_UNICASTFRAMESFILTER_HASHTABLE ((uint32_t)0x00000002U)
<> 144:ef7eb2e8f9f7 1142 #define ETH_UNICASTFRAMESFILTER_PERFECT ((uint32_t)0x00000000U)
<> 144:ef7eb2e8f9f7 1143 /**
<> 144:ef7eb2e8f9f7 1144 * @}
<> 144:ef7eb2e8f9f7 1145 */
<> 144:ef7eb2e8f9f7 1146
<> 144:ef7eb2e8f9f7 1147 /** @defgroup ETH_Zero_Quanta_Pause ETH Zero Quanta Pause
<> 144:ef7eb2e8f9f7 1148 * @{
<> 144:ef7eb2e8f9f7 1149 */
<> 144:ef7eb2e8f9f7 1150 #define ETH_ZEROQUANTAPAUSE_ENABLE ((uint32_t)0x00000000U)
<> 144:ef7eb2e8f9f7 1151 #define ETH_ZEROQUANTAPAUSE_DISABLE ((uint32_t)0x00000080U)
<> 144:ef7eb2e8f9f7 1152 /**
<> 144:ef7eb2e8f9f7 1153 * @}
<> 144:ef7eb2e8f9f7 1154 */
<> 144:ef7eb2e8f9f7 1155
<> 144:ef7eb2e8f9f7 1156 /** @defgroup ETH_Pause_Low_Threshold ETH Pause Low Threshold
<> 144:ef7eb2e8f9f7 1157 * @{
<> 144:ef7eb2e8f9f7 1158 */
<> 144:ef7eb2e8f9f7 1159 #define ETH_PAUSELOWTHRESHOLD_MINUS4 ((uint32_t)0x00000000U) /*!< Pause time minus 4 slot times */
<> 144:ef7eb2e8f9f7 1160 #define ETH_PAUSELOWTHRESHOLD_MINUS28 ((uint32_t)0x00000010U) /*!< Pause time minus 28 slot times */
<> 144:ef7eb2e8f9f7 1161 #define ETH_PAUSELOWTHRESHOLD_MINUS144 ((uint32_t)0x00000020U) /*!< Pause time minus 144 slot times */
<> 144:ef7eb2e8f9f7 1162 #define ETH_PAUSELOWTHRESHOLD_MINUS256 ((uint32_t)0x00000030U) /*!< Pause time minus 256 slot times */
<> 144:ef7eb2e8f9f7 1163 /**
<> 144:ef7eb2e8f9f7 1164 * @}
<> 144:ef7eb2e8f9f7 1165 */
<> 144:ef7eb2e8f9f7 1166
<> 144:ef7eb2e8f9f7 1167 /** @defgroup ETH_Unicast_Pause_Frame_Detect ETH Unicast Pause Frame Detect
<> 144:ef7eb2e8f9f7 1168 * @{
<> 144:ef7eb2e8f9f7 1169 */
<> 144:ef7eb2e8f9f7 1170 #define ETH_UNICASTPAUSEFRAMEDETECT_ENABLE ((uint32_t)0x00000008U)
<> 144:ef7eb2e8f9f7 1171 #define ETH_UNICASTPAUSEFRAMEDETECT_DISABLE ((uint32_t)0x00000000U)
<> 144:ef7eb2e8f9f7 1172 /**
<> 144:ef7eb2e8f9f7 1173 * @}
<> 144:ef7eb2e8f9f7 1174 */
<> 144:ef7eb2e8f9f7 1175
<> 144:ef7eb2e8f9f7 1176 /** @defgroup ETH_Receive_Flow_Control ETH Receive Flow Control
<> 144:ef7eb2e8f9f7 1177 * @{
<> 144:ef7eb2e8f9f7 1178 */
<> 144:ef7eb2e8f9f7 1179 #define ETH_RECEIVEFLOWCONTROL_ENABLE ((uint32_t)0x00000004U)
<> 144:ef7eb2e8f9f7 1180 #define ETH_RECEIVEFLOWCONTROL_DISABLE ((uint32_t)0x00000000U)
<> 144:ef7eb2e8f9f7 1181 /**
<> 144:ef7eb2e8f9f7 1182 * @}
<> 144:ef7eb2e8f9f7 1183 */
<> 144:ef7eb2e8f9f7 1184
<> 144:ef7eb2e8f9f7 1185 /** @defgroup ETH_Transmit_Flow_Control ETH Transmit Flow Control
<> 144:ef7eb2e8f9f7 1186 * @{
<> 144:ef7eb2e8f9f7 1187 */
<> 144:ef7eb2e8f9f7 1188 #define ETH_TRANSMITFLOWCONTROL_ENABLE ((uint32_t)0x00000002U)
<> 144:ef7eb2e8f9f7 1189 #define ETH_TRANSMITFLOWCONTROL_DISABLE ((uint32_t)0x00000000U)
<> 144:ef7eb2e8f9f7 1190 /**
<> 144:ef7eb2e8f9f7 1191 * @}
<> 144:ef7eb2e8f9f7 1192 */
<> 144:ef7eb2e8f9f7 1193
<> 144:ef7eb2e8f9f7 1194 /** @defgroup ETH_VLAN_Tag_Comparison ETH VLAN Tag Comparison
<> 144:ef7eb2e8f9f7 1195 * @{
<> 144:ef7eb2e8f9f7 1196 */
<> 144:ef7eb2e8f9f7 1197 #define ETH_VLANTAGCOMPARISON_12BIT ((uint32_t)0x00010000U)
<> 144:ef7eb2e8f9f7 1198 #define ETH_VLANTAGCOMPARISON_16BIT ((uint32_t)0x00000000U)
<> 144:ef7eb2e8f9f7 1199 /**
<> 144:ef7eb2e8f9f7 1200 * @}
<> 144:ef7eb2e8f9f7 1201 */
<> 144:ef7eb2e8f9f7 1202
<> 144:ef7eb2e8f9f7 1203 /** @defgroup ETH_MAC_addresses ETH MAC addresses
<> 144:ef7eb2e8f9f7 1204 * @{
<> 144:ef7eb2e8f9f7 1205 */
<> 144:ef7eb2e8f9f7 1206 #define ETH_MAC_ADDRESS0 ((uint32_t)0x00000000U)
<> 144:ef7eb2e8f9f7 1207 #define ETH_MAC_ADDRESS1 ((uint32_t)0x00000008U)
<> 144:ef7eb2e8f9f7 1208 #define ETH_MAC_ADDRESS2 ((uint32_t)0x00000010U)
<> 144:ef7eb2e8f9f7 1209 #define ETH_MAC_ADDRESS3 ((uint32_t)0x00000018U)
<> 144:ef7eb2e8f9f7 1210 /**
<> 144:ef7eb2e8f9f7 1211 * @}
<> 144:ef7eb2e8f9f7 1212 */
<> 144:ef7eb2e8f9f7 1213
<> 144:ef7eb2e8f9f7 1214 /** @defgroup ETH_MAC_addresses_filter_SA_DA ETH MAC addresses filter SA DA
<> 144:ef7eb2e8f9f7 1215 * @{
<> 144:ef7eb2e8f9f7 1216 */
<> 144:ef7eb2e8f9f7 1217 #define ETH_MAC_ADDRESSFILTER_SA ((uint32_t)0x00000000U)
<> 144:ef7eb2e8f9f7 1218 #define ETH_MAC_ADDRESSFILTER_DA ((uint32_t)0x00000008U)
<> 144:ef7eb2e8f9f7 1219 /**
<> 144:ef7eb2e8f9f7 1220 * @}
<> 144:ef7eb2e8f9f7 1221 */
<> 144:ef7eb2e8f9f7 1222
<> 144:ef7eb2e8f9f7 1223 /** @defgroup ETH_MAC_addresses_filter_Mask_bytes ETH MAC addresses filter Mask bytes
<> 144:ef7eb2e8f9f7 1224 * @{
<> 144:ef7eb2e8f9f7 1225 */
<> 144:ef7eb2e8f9f7 1226 #define ETH_MAC_ADDRESSMASK_BYTE6 ((uint32_t)0x20000000U) /*!< Mask MAC Address high reg bits [15:8] */
<> 144:ef7eb2e8f9f7 1227 #define ETH_MAC_ADDRESSMASK_BYTE5 ((uint32_t)0x10000000U) /*!< Mask MAC Address high reg bits [7:0] */
<> 144:ef7eb2e8f9f7 1228 #define ETH_MAC_ADDRESSMASK_BYTE4 ((uint32_t)0x08000000U) /*!< Mask MAC Address low reg bits [31:24] */
<> 144:ef7eb2e8f9f7 1229 #define ETH_MAC_ADDRESSMASK_BYTE3 ((uint32_t)0x04000000U) /*!< Mask MAC Address low reg bits [23:16] */
<> 144:ef7eb2e8f9f7 1230 #define ETH_MAC_ADDRESSMASK_BYTE2 ((uint32_t)0x02000000U) /*!< Mask MAC Address low reg bits [15:8] */
<> 144:ef7eb2e8f9f7 1231 #define ETH_MAC_ADDRESSMASK_BYTE1 ((uint32_t)0x01000000U) /*!< Mask MAC Address low reg bits [70] */
<> 144:ef7eb2e8f9f7 1232 /**
<> 144:ef7eb2e8f9f7 1233 * @}
<> 144:ef7eb2e8f9f7 1234 */
<> 144:ef7eb2e8f9f7 1235
<> 144:ef7eb2e8f9f7 1236 /** @defgroup ETH_Drop_TCP_IP_Checksum_Error_Frame ETH Drop TCP IP Checksum Error Frame
<> 144:ef7eb2e8f9f7 1237 * @{
<> 144:ef7eb2e8f9f7 1238 */
<> 144:ef7eb2e8f9f7 1239 #define ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE ((uint32_t)0x00000000U)
<> 144:ef7eb2e8f9f7 1240 #define ETH_DROPTCPIPCHECKSUMERRORFRAME_DISABLE ((uint32_t)0x04000000U)
<> 144:ef7eb2e8f9f7 1241 /**
<> 144:ef7eb2e8f9f7 1242 * @}
<> 144:ef7eb2e8f9f7 1243 */
<> 144:ef7eb2e8f9f7 1244
<> 144:ef7eb2e8f9f7 1245 /** @defgroup ETH_Receive_Store_Forward ETH Receive Store Forward
<> 144:ef7eb2e8f9f7 1246 * @{
<> 144:ef7eb2e8f9f7 1247 */
<> 144:ef7eb2e8f9f7 1248 #define ETH_RECEIVESTOREFORWARD_ENABLE ((uint32_t)0x02000000U)
<> 144:ef7eb2e8f9f7 1249 #define ETH_RECEIVESTOREFORWARD_DISABLE ((uint32_t)0x00000000U)
<> 144:ef7eb2e8f9f7 1250 /**
<> 144:ef7eb2e8f9f7 1251 * @}
<> 144:ef7eb2e8f9f7 1252 */
<> 144:ef7eb2e8f9f7 1253
<> 144:ef7eb2e8f9f7 1254 /** @defgroup ETH_Flush_Received_Frame ETH Flush Received Frame
<> 144:ef7eb2e8f9f7 1255 * @{
<> 144:ef7eb2e8f9f7 1256 */
<> 144:ef7eb2e8f9f7 1257 #define ETH_FLUSHRECEIVEDFRAME_ENABLE ((uint32_t)0x00000000U)
<> 144:ef7eb2e8f9f7 1258 #define ETH_FLUSHRECEIVEDFRAME_DISABLE ((uint32_t)0x01000000U)
<> 144:ef7eb2e8f9f7 1259 /**
<> 144:ef7eb2e8f9f7 1260 * @}
<> 144:ef7eb2e8f9f7 1261 */
<> 144:ef7eb2e8f9f7 1262
<> 144:ef7eb2e8f9f7 1263 /** @defgroup ETH_Transmit_Store_Forward ETH Transmit Store Forward
<> 144:ef7eb2e8f9f7 1264 * @{
<> 144:ef7eb2e8f9f7 1265 */
<> 144:ef7eb2e8f9f7 1266 #define ETH_TRANSMITSTOREFORWARD_ENABLE ((uint32_t)0x00200000U)
<> 144:ef7eb2e8f9f7 1267 #define ETH_TRANSMITSTOREFORWARD_DISABLE ((uint32_t)0x00000000U)
<> 144:ef7eb2e8f9f7 1268 /**
<> 144:ef7eb2e8f9f7 1269 * @}
<> 144:ef7eb2e8f9f7 1270 */
<> 144:ef7eb2e8f9f7 1271
<> 144:ef7eb2e8f9f7 1272 /** @defgroup ETH_Transmit_Threshold_Control ETH Transmit Threshold Control
<> 144:ef7eb2e8f9f7 1273 * @{
<> 144:ef7eb2e8f9f7 1274 */
<> 144:ef7eb2e8f9f7 1275 #define ETH_TRANSMITTHRESHOLDCONTROL_64BYTES ((uint32_t)0x00000000U) /*!< threshold level of the MTL Transmit FIFO is 64 Bytes */
<> 144:ef7eb2e8f9f7 1276 #define ETH_TRANSMITTHRESHOLDCONTROL_128BYTES ((uint32_t)0x00004000U) /*!< threshold level of the MTL Transmit FIFO is 128 Bytes */
<> 144:ef7eb2e8f9f7 1277 #define ETH_TRANSMITTHRESHOLDCONTROL_192BYTES ((uint32_t)0x00008000U) /*!< threshold level of the MTL Transmit FIFO is 192 Bytes */
<> 144:ef7eb2e8f9f7 1278 #define ETH_TRANSMITTHRESHOLDCONTROL_256BYTES ((uint32_t)0x0000C000U) /*!< threshold level of the MTL Transmit FIFO is 256 Bytes */
<> 144:ef7eb2e8f9f7 1279 #define ETH_TRANSMITTHRESHOLDCONTROL_40BYTES ((uint32_t)0x00010000U) /*!< threshold level of the MTL Transmit FIFO is 40 Bytes */
<> 144:ef7eb2e8f9f7 1280 #define ETH_TRANSMITTHRESHOLDCONTROL_32BYTES ((uint32_t)0x00014000U) /*!< threshold level of the MTL Transmit FIFO is 32 Bytes */
<> 144:ef7eb2e8f9f7 1281 #define ETH_TRANSMITTHRESHOLDCONTROL_24BYTES ((uint32_t)0x00018000U) /*!< threshold level of the MTL Transmit FIFO is 24 Bytes */
<> 144:ef7eb2e8f9f7 1282 #define ETH_TRANSMITTHRESHOLDCONTROL_16BYTES ((uint32_t)0x0001C000U) /*!< threshold level of the MTL Transmit FIFO is 16 Bytes */
<> 144:ef7eb2e8f9f7 1283 /**
<> 144:ef7eb2e8f9f7 1284 * @}
<> 144:ef7eb2e8f9f7 1285 */
<> 144:ef7eb2e8f9f7 1286
<> 144:ef7eb2e8f9f7 1287 /** @defgroup ETH_Forward_Error_Frames ETH Forward Error Frames
<> 144:ef7eb2e8f9f7 1288 * @{
<> 144:ef7eb2e8f9f7 1289 */
<> 144:ef7eb2e8f9f7 1290 #define ETH_FORWARDERRORFRAMES_ENABLE ((uint32_t)0x00000080U)
<> 144:ef7eb2e8f9f7 1291 #define ETH_FORWARDERRORFRAMES_DISABLE ((uint32_t)0x00000000U)
<> 144:ef7eb2e8f9f7 1292 /**
<> 144:ef7eb2e8f9f7 1293 * @}
<> 144:ef7eb2e8f9f7 1294 */
<> 144:ef7eb2e8f9f7 1295
<> 144:ef7eb2e8f9f7 1296 /** @defgroup ETH_Forward_Undersized_Good_Frames ETH Forward Undersized Good Frames
<> 144:ef7eb2e8f9f7 1297 * @{
<> 144:ef7eb2e8f9f7 1298 */
<> 144:ef7eb2e8f9f7 1299 #define ETH_FORWARDUNDERSIZEDGOODFRAMES_ENABLE ((uint32_t)0x00000040U)
<> 144:ef7eb2e8f9f7 1300 #define ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE ((uint32_t)0x00000000U)
<> 144:ef7eb2e8f9f7 1301 /**
<> 144:ef7eb2e8f9f7 1302 * @}
<> 144:ef7eb2e8f9f7 1303 */
<> 144:ef7eb2e8f9f7 1304
<> 144:ef7eb2e8f9f7 1305 /** @defgroup ETH_Receive_Threshold_Control ETH Receive Threshold Control
<> 144:ef7eb2e8f9f7 1306 * @{
<> 144:ef7eb2e8f9f7 1307 */
<> 144:ef7eb2e8f9f7 1308 #define ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES ((uint32_t)0x00000000U) /*!< threshold level of the MTL Receive FIFO is 64 Bytes */
<> 144:ef7eb2e8f9f7 1309 #define ETH_RECEIVEDTHRESHOLDCONTROL_32BYTES ((uint32_t)0x00000008U) /*!< threshold level of the MTL Receive FIFO is 32 Bytes */
<> 144:ef7eb2e8f9f7 1310 #define ETH_RECEIVEDTHRESHOLDCONTROL_96BYTES ((uint32_t)0x00000010U) /*!< threshold level of the MTL Receive FIFO is 96 Bytes */
<> 144:ef7eb2e8f9f7 1311 #define ETH_RECEIVEDTHRESHOLDCONTROL_128BYTES ((uint32_t)0x00000018U) /*!< threshold level of the MTL Receive FIFO is 128 Bytes */
<> 144:ef7eb2e8f9f7 1312 /**
<> 144:ef7eb2e8f9f7 1313 * @}
<> 144:ef7eb2e8f9f7 1314 */
<> 144:ef7eb2e8f9f7 1315
<> 144:ef7eb2e8f9f7 1316 /** @defgroup ETH_Second_Frame_Operate ETH Second Frame Operate
<> 144:ef7eb2e8f9f7 1317 * @{
<> 144:ef7eb2e8f9f7 1318 */
<> 144:ef7eb2e8f9f7 1319 #define ETH_SECONDFRAMEOPERARTE_ENABLE ((uint32_t)0x00000004U)
<> 144:ef7eb2e8f9f7 1320 #define ETH_SECONDFRAMEOPERARTE_DISABLE ((uint32_t)0x00000000U)
<> 144:ef7eb2e8f9f7 1321 /**
<> 144:ef7eb2e8f9f7 1322 * @}
<> 144:ef7eb2e8f9f7 1323 */
<> 144:ef7eb2e8f9f7 1324
<> 144:ef7eb2e8f9f7 1325 /** @defgroup ETH_Address_Aligned_Beats ETH Address Aligned Beats
<> 144:ef7eb2e8f9f7 1326 * @{
<> 144:ef7eb2e8f9f7 1327 */
<> 144:ef7eb2e8f9f7 1328 #define ETH_ADDRESSALIGNEDBEATS_ENABLE ((uint32_t)0x02000000U)
<> 144:ef7eb2e8f9f7 1329 #define ETH_ADDRESSALIGNEDBEATS_DISABLE ((uint32_t)0x00000000U)
<> 144:ef7eb2e8f9f7 1330 /**
<> 144:ef7eb2e8f9f7 1331 * @}
<> 144:ef7eb2e8f9f7 1332 */
<> 144:ef7eb2e8f9f7 1333
<> 144:ef7eb2e8f9f7 1334 /** @defgroup ETH_Fixed_Burst ETH Fixed Burst
<> 144:ef7eb2e8f9f7 1335 * @{
<> 144:ef7eb2e8f9f7 1336 */
<> 144:ef7eb2e8f9f7 1337 #define ETH_FIXEDBURST_ENABLE ((uint32_t)0x00010000U)
<> 144:ef7eb2e8f9f7 1338 #define ETH_FIXEDBURST_DISABLE ((uint32_t)0x00000000U)
<> 144:ef7eb2e8f9f7 1339 /**
<> 144:ef7eb2e8f9f7 1340 * @}
<> 144:ef7eb2e8f9f7 1341 */
<> 144:ef7eb2e8f9f7 1342
<> 144:ef7eb2e8f9f7 1343 /** @defgroup ETH_Rx_DMA_Burst_Length ETH Rx DMA Burst Length
<> 144:ef7eb2e8f9f7 1344 * @{
<> 144:ef7eb2e8f9f7 1345 */
<> 144:ef7eb2e8f9f7 1346 #define ETH_RXDMABURSTLENGTH_1BEAT ((uint32_t)0x00020000U) /*!< maximum number of beats to be transferred in one RxDMA transaction is 1 */
<> 144:ef7eb2e8f9f7 1347 #define ETH_RXDMABURSTLENGTH_2BEAT ((uint32_t)0x00040000U) /*!< maximum number of beats to be transferred in one RxDMA transaction is 2 */
<> 144:ef7eb2e8f9f7 1348 #define ETH_RXDMABURSTLENGTH_4BEAT ((uint32_t)0x00080000U) /*!< maximum number of beats to be transferred in one RxDMA transaction is 4 */
<> 144:ef7eb2e8f9f7 1349 #define ETH_RXDMABURSTLENGTH_8BEAT ((uint32_t)0x00100000U) /*!< maximum number of beats to be transferred in one RxDMA transaction is 8 */
<> 144:ef7eb2e8f9f7 1350 #define ETH_RXDMABURSTLENGTH_16BEAT ((uint32_t)0x00200000U) /*!< maximum number of beats to be transferred in one RxDMA transaction is 16 */
<> 144:ef7eb2e8f9f7 1351 #define ETH_RXDMABURSTLENGTH_32BEAT ((uint32_t)0x00400000U) /*!< maximum number of beats to be transferred in one RxDMA transaction is 32 */
<> 144:ef7eb2e8f9f7 1352 #define ETH_RXDMABURSTLENGTH_4XPBL_4BEAT ((uint32_t)0x01020000U) /*!< maximum number of beats to be transferred in one RxDMA transaction is 4 */
<> 144:ef7eb2e8f9f7 1353 #define ETH_RXDMABURSTLENGTH_4XPBL_8BEAT ((uint32_t)0x01040000U) /*!< maximum number of beats to be transferred in one RxDMA transaction is 8 */
<> 144:ef7eb2e8f9f7 1354 #define ETH_RXDMABURSTLENGTH_4XPBL_16BEAT ((uint32_t)0x01080000U) /*!< maximum number of beats to be transferred in one RxDMA transaction is 16 */
<> 144:ef7eb2e8f9f7 1355 #define ETH_RXDMABURSTLENGTH_4XPBL_32BEAT ((uint32_t)0x01100000U) /*!< maximum number of beats to be transferred in one RxDMA transaction is 32 */
<> 144:ef7eb2e8f9f7 1356 #define ETH_RXDMABURSTLENGTH_4XPBL_64BEAT ((uint32_t)0x01200000U) /*!< maximum number of beats to be transferred in one RxDMA transaction is 64 */
<> 144:ef7eb2e8f9f7 1357 #define ETH_RXDMABURSTLENGTH_4XPBL_128BEAT ((uint32_t)0x01400000U) /*!< maximum number of beats to be transferred in one RxDMA transaction is 128 */
<> 144:ef7eb2e8f9f7 1358 /**
<> 144:ef7eb2e8f9f7 1359 * @}
<> 144:ef7eb2e8f9f7 1360 */
<> 144:ef7eb2e8f9f7 1361
<> 144:ef7eb2e8f9f7 1362 /** @defgroup ETH_Tx_DMA_Burst_Length ETH Tx DMA Burst Length
<> 144:ef7eb2e8f9f7 1363 * @{
<> 144:ef7eb2e8f9f7 1364 */
<> 144:ef7eb2e8f9f7 1365 #define ETH_TXDMABURSTLENGTH_1BEAT ((uint32_t)0x00000100U) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
<> 144:ef7eb2e8f9f7 1366 #define ETH_TXDMABURSTLENGTH_2BEAT ((uint32_t)0x00000200U) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
<> 144:ef7eb2e8f9f7 1367 #define ETH_TXDMABURSTLENGTH_4BEAT ((uint32_t)0x00000400U) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
<> 144:ef7eb2e8f9f7 1368 #define ETH_TXDMABURSTLENGTH_8BEAT ((uint32_t)0x00000800U) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
<> 144:ef7eb2e8f9f7 1369 #define ETH_TXDMABURSTLENGTH_16BEAT ((uint32_t)0x00001000U) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
<> 144:ef7eb2e8f9f7 1370 #define ETH_TXDMABURSTLENGTH_32BEAT ((uint32_t)0x00002000U) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
<> 144:ef7eb2e8f9f7 1371 #define ETH_TXDMABURSTLENGTH_4XPBL_4BEAT ((uint32_t)0x01000100U) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
<> 144:ef7eb2e8f9f7 1372 #define ETH_TXDMABURSTLENGTH_4XPBL_8BEAT ((uint32_t)0x01000200U) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
<> 144:ef7eb2e8f9f7 1373 #define ETH_TXDMABURSTLENGTH_4XPBL_16BEAT ((uint32_t)0x01000400U) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
<> 144:ef7eb2e8f9f7 1374 #define ETH_TXDMABURSTLENGTH_4XPBL_32BEAT ((uint32_t)0x01000800U) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
<> 144:ef7eb2e8f9f7 1375 #define ETH_TXDMABURSTLENGTH_4XPBL_64BEAT ((uint32_t)0x01001000U) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
<> 144:ef7eb2e8f9f7 1376 #define ETH_TXDMABURSTLENGTH_4XPBL_128BEAT ((uint32_t)0x01002000U) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
<> 144:ef7eb2e8f9f7 1377 /**
<> 144:ef7eb2e8f9f7 1378 * @}
<> 144:ef7eb2e8f9f7 1379 */
<> 144:ef7eb2e8f9f7 1380
<> 144:ef7eb2e8f9f7 1381 /** @defgroup ETH_DMA_Enhanced_descriptor_format ETH DMA Enhanced descriptor format
<> 144:ef7eb2e8f9f7 1382 * @{
<> 144:ef7eb2e8f9f7 1383 */
<> 144:ef7eb2e8f9f7 1384 #define ETH_DMAENHANCEDDESCRIPTOR_ENABLE ((uint32_t)0x00000080U)
<> 144:ef7eb2e8f9f7 1385 #define ETH_DMAENHANCEDDESCRIPTOR_DISABLE ((uint32_t)0x00000000U)
<> 144:ef7eb2e8f9f7 1386 /**
<> 144:ef7eb2e8f9f7 1387 * @}
<> 144:ef7eb2e8f9f7 1388 */
<> 144:ef7eb2e8f9f7 1389
<> 144:ef7eb2e8f9f7 1390 /** @defgroup ETH_DMA_Arbitration ETH DMA Arbitration
<> 144:ef7eb2e8f9f7 1391 * @{
<> 144:ef7eb2e8f9f7 1392 */
<> 144:ef7eb2e8f9f7 1393 #define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1 ((uint32_t)0x00000000U)
<> 144:ef7eb2e8f9f7 1394 #define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_2_1 ((uint32_t)0x00004000U)
<> 144:ef7eb2e8f9f7 1395 #define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_3_1 ((uint32_t)0x00008000U)
<> 144:ef7eb2e8f9f7 1396 #define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1 ((uint32_t)0x0000C000U)
<> 144:ef7eb2e8f9f7 1397 #define ETH_DMAARBITRATION_RXPRIORTX ((uint32_t)0x00000002U)
<> 144:ef7eb2e8f9f7 1398 /**
<> 144:ef7eb2e8f9f7 1399 * @}
<> 144:ef7eb2e8f9f7 1400 */
<> 144:ef7eb2e8f9f7 1401
<> 144:ef7eb2e8f9f7 1402 /** @defgroup ETH_DMA_Tx_descriptor_segment ETH DMA Tx descriptor segment
<> 144:ef7eb2e8f9f7 1403 * @{
<> 144:ef7eb2e8f9f7 1404 */
<> 144:ef7eb2e8f9f7 1405 #define ETH_DMATXDESC_LASTSEGMENTS ((uint32_t)0x40000000U) /*!< Last Segment */
<> 144:ef7eb2e8f9f7 1406 #define ETH_DMATXDESC_FIRSTSEGMENT ((uint32_t)0x20000000U) /*!< First Segment */
<> 144:ef7eb2e8f9f7 1407 /**
<> 144:ef7eb2e8f9f7 1408 * @}
<> 144:ef7eb2e8f9f7 1409 */
<> 144:ef7eb2e8f9f7 1410
<> 144:ef7eb2e8f9f7 1411 /** @defgroup ETH_DMA_Tx_descriptor_Checksum_Insertion_Control ETH DMA Tx descriptor Checksum Insertion Control
<> 144:ef7eb2e8f9f7 1412 * @{
<> 144:ef7eb2e8f9f7 1413 */
<> 144:ef7eb2e8f9f7 1414 #define ETH_DMATXDESC_CHECKSUMBYPASS ((uint32_t)0x00000000U) /*!< Checksum engine bypass */
<> 144:ef7eb2e8f9f7 1415 #define ETH_DMATXDESC_CHECKSUMIPV4HEADER ((uint32_t)0x00400000U) /*!< IPv4 header checksum insertion */
<> 144:ef7eb2e8f9f7 1416 #define ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT ((uint32_t)0x00800000U) /*!< TCP/UDP/ICMP checksum insertion. Pseudo header checksum is assumed to be present */
<> 144:ef7eb2e8f9f7 1417 #define ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL ((uint32_t)0x00C00000U) /*!< TCP/UDP/ICMP checksum fully in hardware including pseudo header */
<> 144:ef7eb2e8f9f7 1418 /**
<> 144:ef7eb2e8f9f7 1419 * @}
<> 144:ef7eb2e8f9f7 1420 */
<> 144:ef7eb2e8f9f7 1421
<> 144:ef7eb2e8f9f7 1422 /** @defgroup ETH_DMA_Rx_descriptor_buffers ETH DMA Rx descriptor buffers
<> 144:ef7eb2e8f9f7 1423 * @{
<> 144:ef7eb2e8f9f7 1424 */
<> 144:ef7eb2e8f9f7 1425 #define ETH_DMARXDESC_BUFFER1 ((uint32_t)0x00000000U) /*!< DMA Rx Desc Buffer1 */
<> 144:ef7eb2e8f9f7 1426 #define ETH_DMARXDESC_BUFFER2 ((uint32_t)0x00000001U) /*!< DMA Rx Desc Buffer2 */
<> 144:ef7eb2e8f9f7 1427 /**
<> 144:ef7eb2e8f9f7 1428 * @}
<> 144:ef7eb2e8f9f7 1429 */
<> 144:ef7eb2e8f9f7 1430
<> 144:ef7eb2e8f9f7 1431 /** @defgroup ETH_PMT_Flags ETH PMT Flags
<> 144:ef7eb2e8f9f7 1432 * @{
<> 144:ef7eb2e8f9f7 1433 */
<> 144:ef7eb2e8f9f7 1434 #define ETH_PMT_FLAG_WUFFRPR ((uint32_t)0x80000000U) /*!< Wake-Up Frame Filter Register Pointer Reset */
<> 144:ef7eb2e8f9f7 1435 #define ETH_PMT_FLAG_WUFR ((uint32_t)0x00000040U) /*!< Wake-Up Frame Received */
<> 144:ef7eb2e8f9f7 1436 #define ETH_PMT_FLAG_MPR ((uint32_t)0x00000020U) /*!< Magic Packet Received */
<> 144:ef7eb2e8f9f7 1437 /**
<> 144:ef7eb2e8f9f7 1438 * @}
<> 144:ef7eb2e8f9f7 1439 */
<> 144:ef7eb2e8f9f7 1440
<> 144:ef7eb2e8f9f7 1441 /** @defgroup ETH_MMC_Tx_Interrupts ETH MMC Tx Interrupts
<> 144:ef7eb2e8f9f7 1442 * @{
<> 144:ef7eb2e8f9f7 1443 */
<> 144:ef7eb2e8f9f7 1444 #define ETH_MMC_IT_TGF ((uint32_t)0x00200000U) /*!< When Tx good frame counter reaches half the maximum value */
<> 144:ef7eb2e8f9f7 1445 #define ETH_MMC_IT_TGFMSC ((uint32_t)0x00008000U) /*!< When Tx good multi col counter reaches half the maximum value */
<> 144:ef7eb2e8f9f7 1446 #define ETH_MMC_IT_TGFSC ((uint32_t)0x00004000U) /*!< When Tx good single col counter reaches half the maximum value */
<> 144:ef7eb2e8f9f7 1447 /**
<> 144:ef7eb2e8f9f7 1448 * @}
<> 144:ef7eb2e8f9f7 1449 */
<> 144:ef7eb2e8f9f7 1450
<> 144:ef7eb2e8f9f7 1451 /** @defgroup ETH_MMC_Rx_Interrupts ETH MMC Rx Interrupts
<> 144:ef7eb2e8f9f7 1452 * @{
<> 144:ef7eb2e8f9f7 1453 */
<> 144:ef7eb2e8f9f7 1454 #define ETH_MMC_IT_RGUF ((uint32_t)0x10020000U) /*!< When Rx good unicast frames counter reaches half the maximum value */
<> 144:ef7eb2e8f9f7 1455 #define ETH_MMC_IT_RFAE ((uint32_t)0x10000040U) /*!< When Rx alignment error counter reaches half the maximum value */
<> 144:ef7eb2e8f9f7 1456 #define ETH_MMC_IT_RFCE ((uint32_t)0x10000020U) /*!< When Rx crc error counter reaches half the maximum value */
<> 144:ef7eb2e8f9f7 1457 /**
<> 144:ef7eb2e8f9f7 1458 * @}
<> 144:ef7eb2e8f9f7 1459 */
<> 144:ef7eb2e8f9f7 1460
<> 144:ef7eb2e8f9f7 1461 /** @defgroup ETH_MAC_Flags ETH MAC Flags
<> 144:ef7eb2e8f9f7 1462 * @{
<> 144:ef7eb2e8f9f7 1463 */
<> 144:ef7eb2e8f9f7 1464 #define ETH_MAC_FLAG_TST ((uint32_t)0x00000200U) /*!< Time stamp trigger flag (on MAC) */
<> 144:ef7eb2e8f9f7 1465 #define ETH_MAC_FLAG_MMCT ((uint32_t)0x00000040U) /*!< MMC transmit flag */
<> 144:ef7eb2e8f9f7 1466 #define ETH_MAC_FLAG_MMCR ((uint32_t)0x00000020U) /*!< MMC receive flag */
<> 144:ef7eb2e8f9f7 1467 #define ETH_MAC_FLAG_MMC ((uint32_t)0x00000010U) /*!< MMC flag (on MAC) */
<> 144:ef7eb2e8f9f7 1468 #define ETH_MAC_FLAG_PMT ((uint32_t)0x00000008U) /*!< PMT flag (on MAC) */
<> 144:ef7eb2e8f9f7 1469 /**
<> 144:ef7eb2e8f9f7 1470 * @}
<> 144:ef7eb2e8f9f7 1471 */
<> 144:ef7eb2e8f9f7 1472
<> 144:ef7eb2e8f9f7 1473 /** @defgroup ETH_DMA_Flags ETH DMA Flags
<> 144:ef7eb2e8f9f7 1474 * @{
<> 144:ef7eb2e8f9f7 1475 */
<> 144:ef7eb2e8f9f7 1476 #define ETH_DMA_FLAG_TST ((uint32_t)0x20000000U) /*!< Time-stamp trigger interrupt (on DMA) */
<> 144:ef7eb2e8f9f7 1477 #define ETH_DMA_FLAG_PMT ((uint32_t)0x10000000U) /*!< PMT interrupt (on DMA) */
<> 144:ef7eb2e8f9f7 1478 #define ETH_DMA_FLAG_MMC ((uint32_t)0x08000000U) /*!< MMC interrupt (on DMA) */
<> 144:ef7eb2e8f9f7 1479 #define ETH_DMA_FLAG_DATATRANSFERERROR ((uint32_t)0x00800000U) /*!< Error bits 0-Rx DMA, 1-Tx DMA */
<> 144:ef7eb2e8f9f7 1480 #define ETH_DMA_FLAG_READWRITEERROR ((uint32_t)0x01000000U) /*!< Error bits 0-write transfer, 1-read transfer */
<> 144:ef7eb2e8f9f7 1481 #define ETH_DMA_FLAG_ACCESSERROR ((uint32_t)0x02000000U) /*!< Error bits 0-data buffer, 1-desc. access */
<> 144:ef7eb2e8f9f7 1482 #define ETH_DMA_FLAG_NIS ((uint32_t)0x00010000U) /*!< Normal interrupt summary flag */
<> 144:ef7eb2e8f9f7 1483 #define ETH_DMA_FLAG_AIS ((uint32_t)0x00008000U) /*!< Abnormal interrupt summary flag */
<> 144:ef7eb2e8f9f7 1484 #define ETH_DMA_FLAG_ER ((uint32_t)0x00004000U) /*!< Early receive flag */
<> 144:ef7eb2e8f9f7 1485 #define ETH_DMA_FLAG_FBE ((uint32_t)0x00002000U) /*!< Fatal bus error flag */
<> 144:ef7eb2e8f9f7 1486 #define ETH_DMA_FLAG_ET ((uint32_t)0x00000400U) /*!< Early transmit flag */
<> 144:ef7eb2e8f9f7 1487 #define ETH_DMA_FLAG_RWT ((uint32_t)0x00000200U) /*!< Receive watchdog timeout flag */
<> 144:ef7eb2e8f9f7 1488 #define ETH_DMA_FLAG_RPS ((uint32_t)0x00000100U) /*!< Receive process stopped flag */
<> 144:ef7eb2e8f9f7 1489 #define ETH_DMA_FLAG_RBU ((uint32_t)0x00000080U) /*!< Receive buffer unavailable flag */
<> 144:ef7eb2e8f9f7 1490 #define ETH_DMA_FLAG_R ((uint32_t)0x00000040U) /*!< Receive flag */
<> 144:ef7eb2e8f9f7 1491 #define ETH_DMA_FLAG_TU ((uint32_t)0x00000020U) /*!< Underflow flag */
<> 144:ef7eb2e8f9f7 1492 #define ETH_DMA_FLAG_RO ((uint32_t)0x00000010U) /*!< Overflow flag */
<> 144:ef7eb2e8f9f7 1493 #define ETH_DMA_FLAG_TJT ((uint32_t)0x00000008U) /*!< Transmit jabber timeout flag */
<> 144:ef7eb2e8f9f7 1494 #define ETH_DMA_FLAG_TBU ((uint32_t)0x00000004U) /*!< Transmit buffer unavailable flag */
<> 144:ef7eb2e8f9f7 1495 #define ETH_DMA_FLAG_TPS ((uint32_t)0x00000002U) /*!< Transmit process stopped flag */
<> 144:ef7eb2e8f9f7 1496 #define ETH_DMA_FLAG_T ((uint32_t)0x00000001U) /*!< Transmit flag */
<> 144:ef7eb2e8f9f7 1497 /**
<> 144:ef7eb2e8f9f7 1498 * @}
<> 144:ef7eb2e8f9f7 1499 */
<> 144:ef7eb2e8f9f7 1500
<> 144:ef7eb2e8f9f7 1501 /** @defgroup ETH_MAC_Interrupts ETH MAC Interrupts
<> 144:ef7eb2e8f9f7 1502 * @{
<> 144:ef7eb2e8f9f7 1503 */
<> 144:ef7eb2e8f9f7 1504 #define ETH_MAC_IT_TST ((uint32_t)0x00000200U) /*!< Time stamp trigger interrupt (on MAC) */
<> 144:ef7eb2e8f9f7 1505 #define ETH_MAC_IT_MMCT ((uint32_t)0x00000040U) /*!< MMC transmit interrupt */
<> 144:ef7eb2e8f9f7 1506 #define ETH_MAC_IT_MMCR ((uint32_t)0x00000020U) /*!< MMC receive interrupt */
<> 144:ef7eb2e8f9f7 1507 #define ETH_MAC_IT_MMC ((uint32_t)0x00000010U) /*!< MMC interrupt (on MAC) */
<> 144:ef7eb2e8f9f7 1508 #define ETH_MAC_IT_PMT ((uint32_t)0x00000008U) /*!< PMT interrupt (on MAC) */
<> 144:ef7eb2e8f9f7 1509 /**
<> 144:ef7eb2e8f9f7 1510 * @}
<> 144:ef7eb2e8f9f7 1511 */
<> 144:ef7eb2e8f9f7 1512
<> 144:ef7eb2e8f9f7 1513 /** @defgroup ETH_DMA_Interrupts ETH DMA Interrupts
<> 144:ef7eb2e8f9f7 1514 * @{
<> 144:ef7eb2e8f9f7 1515 */
<> 144:ef7eb2e8f9f7 1516 #define ETH_DMA_IT_TST ((uint32_t)0x20000000U) /*!< Time-stamp trigger interrupt (on DMA) */
<> 144:ef7eb2e8f9f7 1517 #define ETH_DMA_IT_PMT ((uint32_t)0x10000000U) /*!< PMT interrupt (on DMA) */
<> 144:ef7eb2e8f9f7 1518 #define ETH_DMA_IT_MMC ((uint32_t)0x08000000U) /*!< MMC interrupt (on DMA) */
<> 144:ef7eb2e8f9f7 1519 #define ETH_DMA_IT_NIS ((uint32_t)0x00010000U) /*!< Normal interrupt summary */
<> 144:ef7eb2e8f9f7 1520 #define ETH_DMA_IT_AIS ((uint32_t)0x00008000U) /*!< Abnormal interrupt summary */
<> 144:ef7eb2e8f9f7 1521 #define ETH_DMA_IT_ER ((uint32_t)0x00004000U) /*!< Early receive interrupt */
<> 144:ef7eb2e8f9f7 1522 #define ETH_DMA_IT_FBE ((uint32_t)0x00002000U) /*!< Fatal bus error interrupt */
<> 144:ef7eb2e8f9f7 1523 #define ETH_DMA_IT_ET ((uint32_t)0x00000400U) /*!< Early transmit interrupt */
<> 144:ef7eb2e8f9f7 1524 #define ETH_DMA_IT_RWT ((uint32_t)0x00000200U) /*!< Receive watchdog timeout interrupt */
<> 144:ef7eb2e8f9f7 1525 #define ETH_DMA_IT_RPS ((uint32_t)0x00000100U) /*!< Receive process stopped interrupt */
<> 144:ef7eb2e8f9f7 1526 #define ETH_DMA_IT_RBU ((uint32_t)0x00000080U) /*!< Receive buffer unavailable interrupt */
<> 144:ef7eb2e8f9f7 1527 #define ETH_DMA_IT_R ((uint32_t)0x00000040U) /*!< Receive interrupt */
<> 144:ef7eb2e8f9f7 1528 #define ETH_DMA_IT_TU ((uint32_t)0x00000020U) /*!< Underflow interrupt */
<> 144:ef7eb2e8f9f7 1529 #define ETH_DMA_IT_RO ((uint32_t)0x00000010U) /*!< Overflow interrupt */
<> 144:ef7eb2e8f9f7 1530 #define ETH_DMA_IT_TJT ((uint32_t)0x00000008U) /*!< Transmit jabber timeout interrupt */
<> 144:ef7eb2e8f9f7 1531 #define ETH_DMA_IT_TBU ((uint32_t)0x00000004U) /*!< Transmit buffer unavailable interrupt */
<> 144:ef7eb2e8f9f7 1532 #define ETH_DMA_IT_TPS ((uint32_t)0x00000002U) /*!< Transmit process stopped interrupt */
<> 144:ef7eb2e8f9f7 1533 #define ETH_DMA_IT_T ((uint32_t)0x00000001U) /*!< Transmit interrupt */
<> 144:ef7eb2e8f9f7 1534 /**
<> 144:ef7eb2e8f9f7 1535 * @}
<> 144:ef7eb2e8f9f7 1536 */
<> 144:ef7eb2e8f9f7 1537
<> 144:ef7eb2e8f9f7 1538 /** @defgroup ETH_DMA_transmit_process_state ETH DMA transmit process state
<> 144:ef7eb2e8f9f7 1539 * @{
<> 144:ef7eb2e8f9f7 1540 */
<> 144:ef7eb2e8f9f7 1541 #define ETH_DMA_TRANSMITPROCESS_STOPPED ((uint32_t)0x00000000U) /*!< Stopped - Reset or Stop Tx Command issued */
<> 144:ef7eb2e8f9f7 1542 #define ETH_DMA_TRANSMITPROCESS_FETCHING ((uint32_t)0x00100000U) /*!< Running - fetching the Tx descriptor */
<> 144:ef7eb2e8f9f7 1543 #define ETH_DMA_TRANSMITPROCESS_WAITING ((uint32_t)0x00200000U) /*!< Running - waiting for status */
<> 144:ef7eb2e8f9f7 1544 #define ETH_DMA_TRANSMITPROCESS_READING ((uint32_t)0x00300000U) /*!< Running - reading the data from host memory */
<> 144:ef7eb2e8f9f7 1545 #define ETH_DMA_TRANSMITPROCESS_SUSPENDED ((uint32_t)0x00600000U) /*!< Suspended - Tx Descriptor unavailable */
<> 144:ef7eb2e8f9f7 1546 #define ETH_DMA_TRANSMITPROCESS_CLOSING ((uint32_t)0x00700000U) /*!< Running - closing Rx descriptor */
<> 144:ef7eb2e8f9f7 1547
<> 144:ef7eb2e8f9f7 1548 /**
<> 144:ef7eb2e8f9f7 1549 * @}
<> 144:ef7eb2e8f9f7 1550 */
<> 144:ef7eb2e8f9f7 1551
<> 144:ef7eb2e8f9f7 1552
<> 144:ef7eb2e8f9f7 1553 /** @defgroup ETH_DMA_receive_process_state ETH DMA receive process state
<> 144:ef7eb2e8f9f7 1554 * @{
<> 144:ef7eb2e8f9f7 1555 */
<> 144:ef7eb2e8f9f7 1556 #define ETH_DMA_RECEIVEPROCESS_STOPPED ((uint32_t)0x00000000U) /*!< Stopped - Reset or Stop Rx Command issued */
<> 144:ef7eb2e8f9f7 1557 #define ETH_DMA_RECEIVEPROCESS_FETCHING ((uint32_t)0x00020000U) /*!< Running - fetching the Rx descriptor */
<> 144:ef7eb2e8f9f7 1558 #define ETH_DMA_RECEIVEPROCESS_WAITING ((uint32_t)0x00060000U) /*!< Running - waiting for packet */
<> 144:ef7eb2e8f9f7 1559 #define ETH_DMA_RECEIVEPROCESS_SUSPENDED ((uint32_t)0x00080000U) /*!< Suspended - Rx Descriptor unavailable */
<> 144:ef7eb2e8f9f7 1560 #define ETH_DMA_RECEIVEPROCESS_CLOSING ((uint32_t)0x000A0000U) /*!< Running - closing descriptor */
<> 144:ef7eb2e8f9f7 1561 #define ETH_DMA_RECEIVEPROCESS_QUEUING ((uint32_t)0x000E0000U) /*!< Running - queuing the receive frame into host memory */
<> 144:ef7eb2e8f9f7 1562
<> 144:ef7eb2e8f9f7 1563 /**
<> 144:ef7eb2e8f9f7 1564 * @}
<> 144:ef7eb2e8f9f7 1565 */
<> 144:ef7eb2e8f9f7 1566
<> 144:ef7eb2e8f9f7 1567 /** @defgroup ETH_DMA_overflow ETH DMA overflow
<> 144:ef7eb2e8f9f7 1568 * @{
<> 144:ef7eb2e8f9f7 1569 */
<> 144:ef7eb2e8f9f7 1570 #define ETH_DMA_OVERFLOW_RXFIFOCOUNTER ((uint32_t)0x10000000U) /*!< Overflow bit for FIFO overflow counter */
<> 144:ef7eb2e8f9f7 1571 #define ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER ((uint32_t)0x00010000U) /*!< Overflow bit for missed frame counter */
<> 144:ef7eb2e8f9f7 1572 /**
<> 144:ef7eb2e8f9f7 1573 * @}
<> 144:ef7eb2e8f9f7 1574 */
<> 144:ef7eb2e8f9f7 1575
<> 144:ef7eb2e8f9f7 1576 /** @defgroup ETH_EXTI_LINE_WAKEUP ETH EXTI LINE WAKEUP
<> 144:ef7eb2e8f9f7 1577 * @{
<> 144:ef7eb2e8f9f7 1578 */
<> 144:ef7eb2e8f9f7 1579 #define ETH_EXTI_LINE_WAKEUP ((uint32_t)0x00080000U) /*!< External interrupt line 19 Connected to the ETH EXTI Line */
<> 144:ef7eb2e8f9f7 1580
<> 144:ef7eb2e8f9f7 1581 /**
<> 144:ef7eb2e8f9f7 1582 * @}
<> 144:ef7eb2e8f9f7 1583 */
<> 144:ef7eb2e8f9f7 1584
<> 144:ef7eb2e8f9f7 1585 /**
<> 144:ef7eb2e8f9f7 1586 * @}
<> 144:ef7eb2e8f9f7 1587 */
<> 144:ef7eb2e8f9f7 1588
<> 144:ef7eb2e8f9f7 1589 /* Exported macro ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 1590 /** @defgroup ETH_Exported_Macros ETH Exported Macros
<> 144:ef7eb2e8f9f7 1591 * @brief macros to handle interrupts and specific clock configurations
<> 144:ef7eb2e8f9f7 1592 * @{
<> 144:ef7eb2e8f9f7 1593 */
<> 144:ef7eb2e8f9f7 1594
<> 144:ef7eb2e8f9f7 1595 /** @brief Reset ETH handle state
<> 144:ef7eb2e8f9f7 1596 * @param __HANDLE__: specifies the ETH handle.
<> 144:ef7eb2e8f9f7 1597 * @retval None
<> 144:ef7eb2e8f9f7 1598 */
<> 144:ef7eb2e8f9f7 1599 #define __HAL_ETH_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ETH_STATE_RESET)
<> 144:ef7eb2e8f9f7 1600
<> 144:ef7eb2e8f9f7 1601 /**
<> 144:ef7eb2e8f9f7 1602 * @brief Checks whether the specified Ethernet DMA Tx Desc flag is set or not.
<> 144:ef7eb2e8f9f7 1603 * @param __HANDLE__: ETH Handle
<> 144:ef7eb2e8f9f7 1604 * @param __FLAG__: specifies the flag of TDES0 to check.
<> 144:ef7eb2e8f9f7 1605 * @retval the ETH_DMATxDescFlag (SET or RESET).
<> 144:ef7eb2e8f9f7 1606 */
<> 144:ef7eb2e8f9f7 1607 #define __HAL_ETH_DMATXDESC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->TxDesc->Status & (__FLAG__) == (__FLAG__))
<> 144:ef7eb2e8f9f7 1608
<> 144:ef7eb2e8f9f7 1609 /**
<> 144:ef7eb2e8f9f7 1610 * @brief Checks whether the specified Ethernet DMA Rx Desc flag is set or not.
<> 144:ef7eb2e8f9f7 1611 * @param __HANDLE__: ETH Handle
<> 144:ef7eb2e8f9f7 1612 * @param __FLAG__: specifies the flag of RDES0 to check.
<> 144:ef7eb2e8f9f7 1613 * @retval the ETH_DMATxDescFlag (SET or RESET).
<> 144:ef7eb2e8f9f7 1614 */
<> 144:ef7eb2e8f9f7 1615 #define __HAL_ETH_DMARXDESC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->RxDesc->Status & (__FLAG__) == (__FLAG__))
<> 144:ef7eb2e8f9f7 1616
<> 144:ef7eb2e8f9f7 1617 /**
<> 144:ef7eb2e8f9f7 1618 * @brief Enables the specified DMA Rx Desc receive interrupt.
<> 144:ef7eb2e8f9f7 1619 * @param __HANDLE__: ETH Handle
<> 144:ef7eb2e8f9f7 1620 * @retval None
<> 144:ef7eb2e8f9f7 1621 */
<> 144:ef7eb2e8f9f7 1622 #define __HAL_ETH_DMARXDESC_ENABLE_IT(__HANDLE__) ((__HANDLE__)->RxDesc->ControlBufferSize &=(~(uint32_t)ETH_DMARXDESC_DIC))
<> 144:ef7eb2e8f9f7 1623
<> 144:ef7eb2e8f9f7 1624 /**
<> 144:ef7eb2e8f9f7 1625 * @brief Disables the specified DMA Rx Desc receive interrupt.
<> 144:ef7eb2e8f9f7 1626 * @param __HANDLE__: ETH Handle
<> 144:ef7eb2e8f9f7 1627 * @retval None
<> 144:ef7eb2e8f9f7 1628 */
<> 144:ef7eb2e8f9f7 1629 #define __HAL_ETH_DMARXDESC_DISABLE_IT(__HANDLE__) ((__HANDLE__)->RxDesc->ControlBufferSize |= ETH_DMARXDESC_DIC)
<> 144:ef7eb2e8f9f7 1630
<> 144:ef7eb2e8f9f7 1631 /**
<> 144:ef7eb2e8f9f7 1632 * @brief Set the specified DMA Rx Desc Own bit.
<> 144:ef7eb2e8f9f7 1633 * @param __HANDLE__: ETH Handle
<> 144:ef7eb2e8f9f7 1634 * @retval None
<> 144:ef7eb2e8f9f7 1635 */
<> 144:ef7eb2e8f9f7 1636 #define __HAL_ETH_DMARXDESC_SET_OWN_BIT(__HANDLE__) ((__HANDLE__)->RxDesc->Status |= ETH_DMARXDESC_OWN)
<> 144:ef7eb2e8f9f7 1637
<> 144:ef7eb2e8f9f7 1638 /**
<> 144:ef7eb2e8f9f7 1639 * @brief Returns the specified Ethernet DMA Tx Desc collision count.
<> 144:ef7eb2e8f9f7 1640 * @param __HANDLE__: ETH Handle
<> 144:ef7eb2e8f9f7 1641 * @retval The Transmit descriptor collision counter value.
<> 144:ef7eb2e8f9f7 1642 */
<> 144:ef7eb2e8f9f7 1643 #define __HAL_ETH_DMATXDESC_GET_COLLISION_COUNT(__HANDLE__) (((__HANDLE__)->TxDesc->Status & ETH_DMATXDESC_CC) >> ETH_DMATXDESC_COLLISION_COUNTSHIFT)
<> 144:ef7eb2e8f9f7 1644
<> 144:ef7eb2e8f9f7 1645 /**
<> 144:ef7eb2e8f9f7 1646 * @brief Set the specified DMA Tx Desc Own bit.
<> 144:ef7eb2e8f9f7 1647 * @param __HANDLE__: ETH Handle
<> 144:ef7eb2e8f9f7 1648 * @retval None
<> 144:ef7eb2e8f9f7 1649 */
<> 144:ef7eb2e8f9f7 1650 #define __HAL_ETH_DMATXDESC_SET_OWN_BIT(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_OWN)
<> 144:ef7eb2e8f9f7 1651
<> 144:ef7eb2e8f9f7 1652 /**
<> 144:ef7eb2e8f9f7 1653 * @brief Enables the specified DMA Tx Desc Transmit interrupt.
<> 144:ef7eb2e8f9f7 1654 * @param __HANDLE__: ETH Handle
<> 144:ef7eb2e8f9f7 1655 * @retval None
<> 144:ef7eb2e8f9f7 1656 */
<> 144:ef7eb2e8f9f7 1657 #define __HAL_ETH_DMATXDESC_ENABLE_IT(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_IC)
<> 144:ef7eb2e8f9f7 1658
<> 144:ef7eb2e8f9f7 1659 /**
<> 144:ef7eb2e8f9f7 1660 * @brief Disables the specified DMA Tx Desc Transmit interrupt.
<> 144:ef7eb2e8f9f7 1661 * @param __HANDLE__: ETH Handle
<> 144:ef7eb2e8f9f7 1662 * @retval None
<> 144:ef7eb2e8f9f7 1663 */
<> 144:ef7eb2e8f9f7 1664 #define __HAL_ETH_DMATXDESC_DISABLE_IT(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_IC)
<> 144:ef7eb2e8f9f7 1665
<> 144:ef7eb2e8f9f7 1666 /**
<> 144:ef7eb2e8f9f7 1667 * @brief Selects the specified Ethernet DMA Tx Desc Checksum Insertion.
<> 144:ef7eb2e8f9f7 1668 * @param __HANDLE__: ETH Handle
<> 144:ef7eb2e8f9f7 1669 * @param __CHECKSUM__: specifies is the DMA Tx desc checksum insertion.
<> 144:ef7eb2e8f9f7 1670 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1671 * @arg ETH_DMATXDESC_CHECKSUMBYPASS : Checksum bypass
<> 144:ef7eb2e8f9f7 1672 * @arg ETH_DMATXDESC_CHECKSUMIPV4HEADER : IPv4 header checksum
<> 144:ef7eb2e8f9f7 1673 * @arg ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT : TCP/UDP/ICMP checksum. Pseudo header checksum is assumed to be present
<> 144:ef7eb2e8f9f7 1674 * @arg ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL : TCP/UDP/ICMP checksum fully in hardware including pseudo header
<> 144:ef7eb2e8f9f7 1675 * @retval None
<> 144:ef7eb2e8f9f7 1676 */
<> 144:ef7eb2e8f9f7 1677 #define __HAL_ETH_DMATXDESC_CHECKSUM_INSERTION(__HANDLE__, __CHECKSUM__) ((__HANDLE__)->TxDesc->Status |= (__CHECKSUM__))
<> 144:ef7eb2e8f9f7 1678
<> 144:ef7eb2e8f9f7 1679 /**
<> 144:ef7eb2e8f9f7 1680 * @brief Enables the DMA Tx Desc CRC.
<> 144:ef7eb2e8f9f7 1681 * @param __HANDLE__: ETH Handle
<> 144:ef7eb2e8f9f7 1682 * @retval None
<> 144:ef7eb2e8f9f7 1683 */
<> 144:ef7eb2e8f9f7 1684 #define __HAL_ETH_DMATXDESC_CRC_ENABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_DC)
<> 144:ef7eb2e8f9f7 1685
<> 144:ef7eb2e8f9f7 1686 /**
<> 144:ef7eb2e8f9f7 1687 * @brief Disables the DMA Tx Desc CRC.
<> 144:ef7eb2e8f9f7 1688 * @param __HANDLE__: ETH Handle
<> 144:ef7eb2e8f9f7 1689 * @retval None
<> 144:ef7eb2e8f9f7 1690 */
<> 144:ef7eb2e8f9f7 1691 #define __HAL_ETH_DMATXDESC_CRC_DISABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_DC)
<> 144:ef7eb2e8f9f7 1692
<> 144:ef7eb2e8f9f7 1693 /**
<> 144:ef7eb2e8f9f7 1694 * @brief Enables the DMA Tx Desc padding for frame shorter than 64 bytes.
<> 144:ef7eb2e8f9f7 1695 * @param __HANDLE__: ETH Handle
<> 144:ef7eb2e8f9f7 1696 * @retval None
<> 144:ef7eb2e8f9f7 1697 */
<> 144:ef7eb2e8f9f7 1698 #define __HAL_ETH_DMATXDESC_SHORT_FRAME_PADDING_ENABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_DP)
<> 144:ef7eb2e8f9f7 1699
<> 144:ef7eb2e8f9f7 1700 /**
<> 144:ef7eb2e8f9f7 1701 * @brief Disables the DMA Tx Desc padding for frame shorter than 64 bytes.
<> 144:ef7eb2e8f9f7 1702 * @param __HANDLE__: ETH Handle
<> 144:ef7eb2e8f9f7 1703 * @retval None
<> 144:ef7eb2e8f9f7 1704 */
<> 144:ef7eb2e8f9f7 1705 #define __HAL_ETH_DMATXDESC_SHORT_FRAME_PADDING_DISABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_DP)
<> 144:ef7eb2e8f9f7 1706
<> 144:ef7eb2e8f9f7 1707 /**
<> 144:ef7eb2e8f9f7 1708 * @brief Enables the specified Ethernet MAC interrupts.
<> 144:ef7eb2e8f9f7 1709 * @param __HANDLE__ : ETH Handle
<> 144:ef7eb2e8f9f7 1710 * @param __INTERRUPT__: specifies the Ethernet MAC interrupt sources to be
<> 144:ef7eb2e8f9f7 1711 * enabled or disabled.
<> 144:ef7eb2e8f9f7 1712 * This parameter can be any combination of the following values:
<> 144:ef7eb2e8f9f7 1713 * @arg ETH_MAC_IT_TST : Time stamp trigger interrupt
<> 144:ef7eb2e8f9f7 1714 * @arg ETH_MAC_IT_PMT : PMT interrupt
<> 144:ef7eb2e8f9f7 1715 * @retval None
<> 144:ef7eb2e8f9f7 1716 */
<> 144:ef7eb2e8f9f7 1717 #define __HAL_ETH_MAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIMR |= (__INTERRUPT__))
<> 144:ef7eb2e8f9f7 1718
<> 144:ef7eb2e8f9f7 1719 /**
<> 144:ef7eb2e8f9f7 1720 * @brief Disables the specified Ethernet MAC interrupts.
<> 144:ef7eb2e8f9f7 1721 * @param __HANDLE__ : ETH Handle
<> 144:ef7eb2e8f9f7 1722 * @param __INTERRUPT__: specifies the Ethernet MAC interrupt sources to be
<> 144:ef7eb2e8f9f7 1723 * enabled or disabled.
<> 144:ef7eb2e8f9f7 1724 * This parameter can be any combination of the following values:
<> 144:ef7eb2e8f9f7 1725 * @arg ETH_MAC_IT_TST : Time stamp trigger interrupt
<> 144:ef7eb2e8f9f7 1726 * @arg ETH_MAC_IT_PMT : PMT interrupt
<> 144:ef7eb2e8f9f7 1727 * @retval None
<> 144:ef7eb2e8f9f7 1728 */
<> 144:ef7eb2e8f9f7 1729 #define __HAL_ETH_MAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIMR &= ~(__INTERRUPT__))
<> 144:ef7eb2e8f9f7 1730
<> 144:ef7eb2e8f9f7 1731 /**
<> 144:ef7eb2e8f9f7 1732 * @brief Initiate a Pause Control Frame (Full-duplex only).
<> 144:ef7eb2e8f9f7 1733 * @param __HANDLE__: ETH Handle
<> 144:ef7eb2e8f9f7 1734 * @retval None
<> 144:ef7eb2e8f9f7 1735 */
<> 144:ef7eb2e8f9f7 1736 #define __HAL_ETH_INITIATE_PAUSE_CONTROL_FRAME(__HANDLE__) ((__HANDLE__)->Instance->MACFCR |= ETH_MACFCR_FCBBPA)
<> 144:ef7eb2e8f9f7 1737
<> 144:ef7eb2e8f9f7 1738 /**
<> 144:ef7eb2e8f9f7 1739 * @brief Checks whether the Ethernet flow control busy bit is set or not.
<> 144:ef7eb2e8f9f7 1740 * @param __HANDLE__: ETH Handle
<> 144:ef7eb2e8f9f7 1741 * @retval The new state of flow control busy status bit (SET or RESET).
<> 144:ef7eb2e8f9f7 1742 */
<> 144:ef7eb2e8f9f7 1743 #define __HAL_ETH_GET_FLOW_CONTROL_BUSY_STATUS(__HANDLE__) (((__HANDLE__)->Instance->MACFCR & ETH_MACFCR_FCBBPA) == ETH_MACFCR_FCBBPA)
<> 144:ef7eb2e8f9f7 1744
<> 144:ef7eb2e8f9f7 1745 /**
<> 144:ef7eb2e8f9f7 1746 * @brief Enables the MAC Back Pressure operation activation (Half-duplex only).
<> 144:ef7eb2e8f9f7 1747 * @param __HANDLE__: ETH Handle
<> 144:ef7eb2e8f9f7 1748 * @retval None
<> 144:ef7eb2e8f9f7 1749 */
<> 144:ef7eb2e8f9f7 1750 #define __HAL_ETH_BACK_PRESSURE_ACTIVATION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACFCR |= ETH_MACFCR_FCBBPA)
<> 144:ef7eb2e8f9f7 1751
<> 144:ef7eb2e8f9f7 1752 /**
<> 144:ef7eb2e8f9f7 1753 * @brief Disables the MAC BackPressure operation activation (Half-duplex only).
<> 144:ef7eb2e8f9f7 1754 * @param __HANDLE__: ETH Handle
<> 144:ef7eb2e8f9f7 1755 * @retval None
<> 144:ef7eb2e8f9f7 1756 */
<> 144:ef7eb2e8f9f7 1757 #define __HAL_ETH_BACK_PRESSURE_ACTIVATION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACFCR &= ~ETH_MACFCR_FCBBPA)
<> 144:ef7eb2e8f9f7 1758
<> 144:ef7eb2e8f9f7 1759 /**
<> 144:ef7eb2e8f9f7 1760 * @brief Checks whether the specified Ethernet MAC flag is set or not.
<> 144:ef7eb2e8f9f7 1761 * @param __HANDLE__: ETH Handle
<> 144:ef7eb2e8f9f7 1762 * @param __FLAG__: specifies the flag to check.
<> 144:ef7eb2e8f9f7 1763 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1764 * @arg ETH_MAC_FLAG_TST : Time stamp trigger flag
<> 144:ef7eb2e8f9f7 1765 * @arg ETH_MAC_FLAG_MMCT : MMC transmit flag
<> 144:ef7eb2e8f9f7 1766 * @arg ETH_MAC_FLAG_MMCR : MMC receive flag
<> 144:ef7eb2e8f9f7 1767 * @arg ETH_MAC_FLAG_MMC : MMC flag
<> 144:ef7eb2e8f9f7 1768 * @arg ETH_MAC_FLAG_PMT : PMT flag
<> 144:ef7eb2e8f9f7 1769 * @retval The state of Ethernet MAC flag.
<> 144:ef7eb2e8f9f7 1770 */
<> 144:ef7eb2e8f9f7 1771 #define __HAL_ETH_MAC_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->MACSR &( __FLAG__)) == ( __FLAG__))
<> 144:ef7eb2e8f9f7 1772
<> 144:ef7eb2e8f9f7 1773 /**
<> 144:ef7eb2e8f9f7 1774 * @brief Enables the specified Ethernet DMA interrupts.
<> 144:ef7eb2e8f9f7 1775 * @param __HANDLE__ : ETH Handle
<> 144:ef7eb2e8f9f7 1776 * @param __INTERRUPT__: specifies the Ethernet DMA interrupt sources to be
<> 144:ef7eb2e8f9f7 1777 * enabled @ref ETH_DMA_Interrupts
<> 144:ef7eb2e8f9f7 1778 * @retval None
<> 144:ef7eb2e8f9f7 1779 */
<> 144:ef7eb2e8f9f7 1780 #define __HAL_ETH_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMAIER |= (__INTERRUPT__))
<> 144:ef7eb2e8f9f7 1781
<> 144:ef7eb2e8f9f7 1782 /**
<> 144:ef7eb2e8f9f7 1783 * @brief Disables the specified Ethernet DMA interrupts.
<> 144:ef7eb2e8f9f7 1784 * @param __HANDLE__ : ETH Handle
<> 144:ef7eb2e8f9f7 1785 * @param __INTERRUPT__: specifies the Ethernet DMA interrupt sources to be
<> 144:ef7eb2e8f9f7 1786 * disabled. @ref ETH_DMA_Interrupts
<> 144:ef7eb2e8f9f7 1787 * @retval None
<> 144:ef7eb2e8f9f7 1788 */
<> 144:ef7eb2e8f9f7 1789 #define __HAL_ETH_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMAIER &= ~(__INTERRUPT__))
<> 144:ef7eb2e8f9f7 1790
<> 144:ef7eb2e8f9f7 1791 /**
<> 144:ef7eb2e8f9f7 1792 * @brief Clears the Ethernet DMA IT pending bit.
<> 144:ef7eb2e8f9f7 1793 * @param __HANDLE__ : ETH Handle
<> 144:ef7eb2e8f9f7 1794 * @param __INTERRUPT__: specifies the interrupt pending bit to clear. @ref ETH_DMA_Interrupts
<> 144:ef7eb2e8f9f7 1795 * @retval None
<> 144:ef7eb2e8f9f7 1796 */
<> 144:ef7eb2e8f9f7 1797 #define __HAL_ETH_DMA_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMASR =(__INTERRUPT__))
<> 144:ef7eb2e8f9f7 1798
<> 144:ef7eb2e8f9f7 1799 /**
<> 144:ef7eb2e8f9f7 1800 * @brief Checks whether the specified Ethernet DMA flag is set or not.
<> 144:ef7eb2e8f9f7 1801 * @param __HANDLE__: ETH Handle
<> 144:ef7eb2e8f9f7 1802 * @param __FLAG__: specifies the flag to check. @ref ETH_DMA_Flags
<> 144:ef7eb2e8f9f7 1803 * @retval The new state of ETH_DMA_FLAG (SET or RESET).
<> 144:ef7eb2e8f9f7 1804 */
<> 144:ef7eb2e8f9f7 1805 #define __HAL_ETH_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->DMASR &( __FLAG__)) == ( __FLAG__))
<> 144:ef7eb2e8f9f7 1806
<> 144:ef7eb2e8f9f7 1807 /**
<> 144:ef7eb2e8f9f7 1808 * @brief Checks whether the specified Ethernet DMA flag is set or not.
<> 144:ef7eb2e8f9f7 1809 * @param __HANDLE__: ETH Handle
<> 144:ef7eb2e8f9f7 1810 * @param __FLAG__: specifies the flag to clear. @ref ETH_DMA_Flags
<> 144:ef7eb2e8f9f7 1811 * @retval The new state of ETH_DMA_FLAG (SET or RESET).
<> 144:ef7eb2e8f9f7 1812 */
<> 144:ef7eb2e8f9f7 1813 #define __HAL_ETH_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->DMASR = (__FLAG__))
<> 144:ef7eb2e8f9f7 1814
<> 144:ef7eb2e8f9f7 1815 /**
<> 144:ef7eb2e8f9f7 1816 * @brief Checks whether the specified Ethernet DMA overflow flag is set or not.
<> 144:ef7eb2e8f9f7 1817 * @param __HANDLE__: ETH Handle
<> 144:ef7eb2e8f9f7 1818 * @param __OVERFLOW__: specifies the DMA overflow flag to check.
<> 144:ef7eb2e8f9f7 1819 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1820 * @arg ETH_DMA_OVERFLOW_RXFIFOCOUNTER : Overflow for FIFO Overflows Counter
<> 144:ef7eb2e8f9f7 1821 * @arg ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER : Overflow for Buffer Unavailable Missed Frame Counter
<> 144:ef7eb2e8f9f7 1822 * @retval The state of Ethernet DMA overflow Flag (SET or RESET).
<> 144:ef7eb2e8f9f7 1823 */
<> 144:ef7eb2e8f9f7 1824 #define __HAL_ETH_GET_DMA_OVERFLOW_STATUS(__HANDLE__, __OVERFLOW__) (((__HANDLE__)->Instance->DMAMFBOCR & (__OVERFLOW__)) == (__OVERFLOW__))
<> 144:ef7eb2e8f9f7 1825
<> 144:ef7eb2e8f9f7 1826 /**
<> 144:ef7eb2e8f9f7 1827 * @brief Set the DMA Receive status watchdog timer register value
<> 144:ef7eb2e8f9f7 1828 * @param __HANDLE__: ETH Handle
<> 144:ef7eb2e8f9f7 1829 * @param __VALUE__: DMA Receive status watchdog timer register value
<> 144:ef7eb2e8f9f7 1830 * @retval None
<> 144:ef7eb2e8f9f7 1831 */
<> 144:ef7eb2e8f9f7 1832 #define __HAL_ETH_SET_RECEIVE_WATCHDOG_TIMER(__HANDLE__, __VALUE__) ((__HANDLE__)->Instance->DMARSWTR = (__VALUE__))
<> 144:ef7eb2e8f9f7 1833
<> 144:ef7eb2e8f9f7 1834 /**
<> 144:ef7eb2e8f9f7 1835 * @brief Enables any unicast packet filtered by the MAC address
<> 144:ef7eb2e8f9f7 1836 * recognition to be a wake-up frame.
<> 144:ef7eb2e8f9f7 1837 * @param __HANDLE__: ETH Handle.
<> 144:ef7eb2e8f9f7 1838 * @retval None
<> 144:ef7eb2e8f9f7 1839 */
<> 144:ef7eb2e8f9f7 1840 #define __HAL_ETH_GLOBAL_UNICAST_WAKEUP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_GU)
<> 144:ef7eb2e8f9f7 1841
<> 144:ef7eb2e8f9f7 1842 /**
<> 144:ef7eb2e8f9f7 1843 * @brief Disables any unicast packet filtered by the MAC address
<> 144:ef7eb2e8f9f7 1844 * recognition to be a wake-up frame.
<> 144:ef7eb2e8f9f7 1845 * @param __HANDLE__: ETH Handle.
<> 144:ef7eb2e8f9f7 1846 * @retval None
<> 144:ef7eb2e8f9f7 1847 */
<> 144:ef7eb2e8f9f7 1848 #define __HAL_ETH_GLOBAL_UNICAST_WAKEUP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_GU)
<> 144:ef7eb2e8f9f7 1849
<> 144:ef7eb2e8f9f7 1850 /**
<> 144:ef7eb2e8f9f7 1851 * @brief Enables the MAC Wake-Up Frame Detection.
<> 144:ef7eb2e8f9f7 1852 * @param __HANDLE__: ETH Handle.
<> 144:ef7eb2e8f9f7 1853 * @retval None
<> 144:ef7eb2e8f9f7 1854 */
<> 144:ef7eb2e8f9f7 1855 #define __HAL_ETH_WAKEUP_FRAME_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_WFE)
<> 144:ef7eb2e8f9f7 1856
<> 144:ef7eb2e8f9f7 1857 /**
<> 144:ef7eb2e8f9f7 1858 * @brief Disables the MAC Wake-Up Frame Detection.
<> 144:ef7eb2e8f9f7 1859 * @param __HANDLE__: ETH Handle.
<> 144:ef7eb2e8f9f7 1860 * @retval None
<> 144:ef7eb2e8f9f7 1861 */
<> 144:ef7eb2e8f9f7 1862 #define __HAL_ETH_WAKEUP_FRAME_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_WFE)
<> 144:ef7eb2e8f9f7 1863
<> 144:ef7eb2e8f9f7 1864 /**
<> 144:ef7eb2e8f9f7 1865 * @brief Enables the MAC Magic Packet Detection.
<> 144:ef7eb2e8f9f7 1866 * @param __HANDLE__: ETH Handle.
<> 144:ef7eb2e8f9f7 1867 * @retval None
<> 144:ef7eb2e8f9f7 1868 */
<> 144:ef7eb2e8f9f7 1869 #define __HAL_ETH_MAGIC_PACKET_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_MPE)
<> 144:ef7eb2e8f9f7 1870
<> 144:ef7eb2e8f9f7 1871 /**
<> 144:ef7eb2e8f9f7 1872 * @brief Disables the MAC Magic Packet Detection.
<> 144:ef7eb2e8f9f7 1873 * @param __HANDLE__: ETH Handle.
<> 144:ef7eb2e8f9f7 1874 * @retval None
<> 144:ef7eb2e8f9f7 1875 */
<> 144:ef7eb2e8f9f7 1876 #define __HAL_ETH_MAGIC_PACKET_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_WFE)
<> 144:ef7eb2e8f9f7 1877
<> 144:ef7eb2e8f9f7 1878 /**
<> 144:ef7eb2e8f9f7 1879 * @brief Enables the MAC Power Down.
<> 144:ef7eb2e8f9f7 1880 * @param __HANDLE__: ETH Handle
<> 144:ef7eb2e8f9f7 1881 * @retval None
<> 144:ef7eb2e8f9f7 1882 */
<> 144:ef7eb2e8f9f7 1883 #define __HAL_ETH_POWER_DOWN_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_PD)
<> 144:ef7eb2e8f9f7 1884
<> 144:ef7eb2e8f9f7 1885 /**
<> 144:ef7eb2e8f9f7 1886 * @brief Disables the MAC Power Down.
<> 144:ef7eb2e8f9f7 1887 * @param __HANDLE__: ETH Handle
<> 144:ef7eb2e8f9f7 1888 * @retval None
<> 144:ef7eb2e8f9f7 1889 */
<> 144:ef7eb2e8f9f7 1890 #define __HAL_ETH_POWER_DOWN_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_PD)
<> 144:ef7eb2e8f9f7 1891
<> 144:ef7eb2e8f9f7 1892 /**
<> 144:ef7eb2e8f9f7 1893 * @brief Checks whether the specified Ethernet PMT flag is set or not.
<> 144:ef7eb2e8f9f7 1894 * @param __HANDLE__: ETH Handle.
<> 144:ef7eb2e8f9f7 1895 * @param __FLAG__: specifies the flag to check.
<> 144:ef7eb2e8f9f7 1896 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1897 * @arg ETH_PMT_FLAG_WUFFRPR : Wake-Up Frame Filter Register Pointer Reset
<> 144:ef7eb2e8f9f7 1898 * @arg ETH_PMT_FLAG_WUFR : Wake-Up Frame Received
<> 144:ef7eb2e8f9f7 1899 * @arg ETH_PMT_FLAG_MPR : Magic Packet Received
<> 144:ef7eb2e8f9f7 1900 * @retval The new state of Ethernet PMT Flag (SET or RESET).
<> 144:ef7eb2e8f9f7 1901 */
<> 144:ef7eb2e8f9f7 1902 #define __HAL_ETH_GET_PMT_FLAG_STATUS(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->MACPMTCSR &( __FLAG__)) == ( __FLAG__))
<> 144:ef7eb2e8f9f7 1903
<> 144:ef7eb2e8f9f7 1904 /**
<> 144:ef7eb2e8f9f7 1905 * @brief Preset and Initialize the MMC counters to almost-full value: 0xFFFF_FFF0 (full - 16)
<> 144:ef7eb2e8f9f7 1906 * @param __HANDLE__: ETH Handle.
<> 144:ef7eb2e8f9f7 1907 * @retval None
<> 144:ef7eb2e8f9f7 1908 */
<> 144:ef7eb2e8f9f7 1909 #define __HAL_ETH_MMC_COUNTER_FULL_PRESET(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= (ETH_MMCCR_MCFHP | ETH_MMCCR_MCP))
<> 144:ef7eb2e8f9f7 1910
<> 144:ef7eb2e8f9f7 1911 /**
<> 144:ef7eb2e8f9f7 1912 * @brief Preset and Initialize the MMC counters to almost-half value: 0x7FFF_FFF0 (half - 16)
<> 144:ef7eb2e8f9f7 1913 * @param __HANDLE__: ETH Handle.
<> 144:ef7eb2e8f9f7 1914 * @retval None
<> 144:ef7eb2e8f9f7 1915 */
<> 144:ef7eb2e8f9f7 1916 #define __HAL_ETH_MMC_COUNTER_HALF_PRESET(__HANDLE__) do{(__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_MCFHP;\
<> 144:ef7eb2e8f9f7 1917 (__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_MCP;} while (0)
<> 144:ef7eb2e8f9f7 1918
<> 144:ef7eb2e8f9f7 1919 /**
<> 144:ef7eb2e8f9f7 1920 * @brief Enables the MMC Counter Freeze.
<> 144:ef7eb2e8f9f7 1921 * @param __HANDLE__: ETH Handle.
<> 144:ef7eb2e8f9f7 1922 * @retval None
<> 144:ef7eb2e8f9f7 1923 */
<> 144:ef7eb2e8f9f7 1924 #define __HAL_ETH_MMC_COUNTER_FREEZE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_MCF)
<> 144:ef7eb2e8f9f7 1925
<> 144:ef7eb2e8f9f7 1926 /**
<> 144:ef7eb2e8f9f7 1927 * @brief Disables the MMC Counter Freeze.
<> 144:ef7eb2e8f9f7 1928 * @param __HANDLE__: ETH Handle.
<> 144:ef7eb2e8f9f7 1929 * @retval None
<> 144:ef7eb2e8f9f7 1930 */
<> 144:ef7eb2e8f9f7 1931 #define __HAL_ETH_MMC_COUNTER_FREEZE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_MCF)
<> 144:ef7eb2e8f9f7 1932
<> 144:ef7eb2e8f9f7 1933 /**
<> 144:ef7eb2e8f9f7 1934 * @brief Enables the MMC Reset On Read.
<> 144:ef7eb2e8f9f7 1935 * @param __HANDLE__: ETH Handle.
<> 144:ef7eb2e8f9f7 1936 * @retval None
<> 144:ef7eb2e8f9f7 1937 */
<> 144:ef7eb2e8f9f7 1938 #define __HAL_ETH_ETH_MMC_RESET_ONREAD_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_ROR)
<> 144:ef7eb2e8f9f7 1939
<> 144:ef7eb2e8f9f7 1940 /**
<> 144:ef7eb2e8f9f7 1941 * @brief Disables the MMC Reset On Read.
<> 144:ef7eb2e8f9f7 1942 * @param __HANDLE__: ETH Handle.
<> 144:ef7eb2e8f9f7 1943 * @retval None
<> 144:ef7eb2e8f9f7 1944 */
<> 144:ef7eb2e8f9f7 1945 #define __HAL_ETH_ETH_MMC_RESET_ONREAD_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_ROR)
<> 144:ef7eb2e8f9f7 1946
<> 144:ef7eb2e8f9f7 1947 /**
<> 144:ef7eb2e8f9f7 1948 * @brief Enables the MMC Counter Stop Rollover.
<> 144:ef7eb2e8f9f7 1949 * @param __HANDLE__: ETH Handle.
<> 144:ef7eb2e8f9f7 1950 * @retval None
<> 144:ef7eb2e8f9f7 1951 */
<> 144:ef7eb2e8f9f7 1952 #define __HAL_ETH_ETH_MMC_COUNTER_ROLLOVER_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_CSR)
<> 144:ef7eb2e8f9f7 1953
<> 144:ef7eb2e8f9f7 1954 /**
<> 144:ef7eb2e8f9f7 1955 * @brief Disables the MMC Counter Stop Rollover.
<> 144:ef7eb2e8f9f7 1956 * @param __HANDLE__: ETH Handle.
<> 144:ef7eb2e8f9f7 1957 * @retval None
<> 144:ef7eb2e8f9f7 1958 */
<> 144:ef7eb2e8f9f7 1959 #define __HAL_ETH_ETH_MMC_COUNTER_ROLLOVER_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_CSR)
<> 144:ef7eb2e8f9f7 1960
<> 144:ef7eb2e8f9f7 1961 /**
<> 144:ef7eb2e8f9f7 1962 * @brief Resets the MMC Counters.
<> 144:ef7eb2e8f9f7 1963 * @param __HANDLE__: ETH Handle.
<> 144:ef7eb2e8f9f7 1964 * @retval None
<> 144:ef7eb2e8f9f7 1965 */
<> 144:ef7eb2e8f9f7 1966 #define __HAL_ETH_MMC_COUNTERS_RESET(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_CR)
<> 144:ef7eb2e8f9f7 1967
<> 144:ef7eb2e8f9f7 1968 /**
<> 144:ef7eb2e8f9f7 1969 * @brief Enables the specified Ethernet MMC Rx interrupts.
<> 144:ef7eb2e8f9f7 1970 * @param __HANDLE__: ETH Handle.
<> 144:ef7eb2e8f9f7 1971 * @param __INTERRUPT__: specifies the Ethernet MMC interrupt sources to be enabled or disabled.
<> 144:ef7eb2e8f9f7 1972 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1973 * @arg ETH_MMC_IT_RGUF : When Rx good unicast frames counter reaches half the maximum value
<> 144:ef7eb2e8f9f7 1974 * @arg ETH_MMC_IT_RFAE : When Rx alignment error counter reaches half the maximum value
<> 144:ef7eb2e8f9f7 1975 * @arg ETH_MMC_IT_RFCE : When Rx crc error counter reaches half the maximum value
<> 144:ef7eb2e8f9f7 1976 * @retval None
<> 144:ef7eb2e8f9f7 1977 */
<> 144:ef7eb2e8f9f7 1978 #define __HAL_ETH_MMC_RX_IT_ENABLE(__HANDLE__, __INTERRUPT__) (__HANDLE__)->Instance->MMCRIMR &= ~((__INTERRUPT__) & 0xEFFFFFFF)
<> 144:ef7eb2e8f9f7 1979 /**
<> 144:ef7eb2e8f9f7 1980 * @brief Disables the specified Ethernet MMC Rx interrupts.
<> 144:ef7eb2e8f9f7 1981 * @param __HANDLE__: ETH Handle.
<> 144:ef7eb2e8f9f7 1982 * @param __INTERRUPT__: specifies the Ethernet MMC interrupt sources to be enabled or disabled.
<> 144:ef7eb2e8f9f7 1983 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1984 * @arg ETH_MMC_IT_RGUF : When Rx good unicast frames counter reaches half the maximum value
<> 144:ef7eb2e8f9f7 1985 * @arg ETH_MMC_IT_RFAE : When Rx alignment error counter reaches half the maximum value
<> 144:ef7eb2e8f9f7 1986 * @arg ETH_MMC_IT_RFCE : When Rx crc error counter reaches half the maximum value
<> 144:ef7eb2e8f9f7 1987 * @retval None
<> 144:ef7eb2e8f9f7 1988 */
<> 144:ef7eb2e8f9f7 1989 #define __HAL_ETH_MMC_RX_IT_DISABLE(__HANDLE__, __INTERRUPT__) (__HANDLE__)->Instance->MMCRIMR |= ((__INTERRUPT__) & 0xEFFFFFFF)
<> 144:ef7eb2e8f9f7 1990 /**
<> 144:ef7eb2e8f9f7 1991 * @brief Enables the specified Ethernet MMC Tx interrupts.
<> 144:ef7eb2e8f9f7 1992 * @param __HANDLE__: ETH Handle.
<> 144:ef7eb2e8f9f7 1993 * @param __INTERRUPT__: specifies the Ethernet MMC interrupt sources to be enabled or disabled.
<> 144:ef7eb2e8f9f7 1994 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1995 * @arg ETH_MMC_IT_TGF : When Tx good frame counter reaches half the maximum value
<> 144:ef7eb2e8f9f7 1996 * @arg ETH_MMC_IT_TGFMSC: When Tx good multi col counter reaches half the maximum value
<> 144:ef7eb2e8f9f7 1997 * @arg ETH_MMC_IT_TGFSC : When Tx good single col counter reaches half the maximum value
<> 144:ef7eb2e8f9f7 1998 * @retval None
<> 144:ef7eb2e8f9f7 1999 */
<> 144:ef7eb2e8f9f7 2000 #define __HAL_ETH_MMC_TX_IT_ENABLE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MMCRIMR &= ~ (__INTERRUPT__))
<> 144:ef7eb2e8f9f7 2001
<> 144:ef7eb2e8f9f7 2002 /**
<> 144:ef7eb2e8f9f7 2003 * @brief Disables the specified Ethernet MMC Tx interrupts.
<> 144:ef7eb2e8f9f7 2004 * @param __HANDLE__: ETH Handle.
<> 144:ef7eb2e8f9f7 2005 * @param __INTERRUPT__: specifies the Ethernet MMC interrupt sources to be enabled or disabled.
<> 144:ef7eb2e8f9f7 2006 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 2007 * @arg ETH_MMC_IT_TGF : When Tx good frame counter reaches half the maximum value
<> 144:ef7eb2e8f9f7 2008 * @arg ETH_MMC_IT_TGFMSC: When Tx good multi col counter reaches half the maximum value
<> 144:ef7eb2e8f9f7 2009 * @arg ETH_MMC_IT_TGFSC : When Tx good single col counter reaches half the maximum value
<> 144:ef7eb2e8f9f7 2010 * @retval None
<> 144:ef7eb2e8f9f7 2011 */
<> 144:ef7eb2e8f9f7 2012 #define __HAL_ETH_MMC_TX_IT_DISABLE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MMCRIMR |= (__INTERRUPT__))
<> 144:ef7eb2e8f9f7 2013
<> 144:ef7eb2e8f9f7 2014 /**
<> 144:ef7eb2e8f9f7 2015 * @brief Enables the ETH External interrupt line.
<> 144:ef7eb2e8f9f7 2016 * @retval None
<> 144:ef7eb2e8f9f7 2017 */
<> 144:ef7eb2e8f9f7 2018 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR |= (ETH_EXTI_LINE_WAKEUP)
<> 144:ef7eb2e8f9f7 2019
<> 144:ef7eb2e8f9f7 2020 /**
<> 144:ef7eb2e8f9f7 2021 * @brief Disables the ETH External interrupt line.
<> 144:ef7eb2e8f9f7 2022 * @retval None
<> 144:ef7eb2e8f9f7 2023 */
<> 144:ef7eb2e8f9f7 2024 #define __HAL_ETH_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR &= ~(ETH_EXTI_LINE_WAKEUP)
<> 144:ef7eb2e8f9f7 2025
<> 144:ef7eb2e8f9f7 2026 /**
<> 144:ef7eb2e8f9f7 2027 * @brief Enable event on ETH External event line.
<> 144:ef7eb2e8f9f7 2028 * @retval None.
<> 144:ef7eb2e8f9f7 2029 */
<> 144:ef7eb2e8f9f7 2030 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_EVENT() EXTI->EMR |= (ETH_EXTI_LINE_WAKEUP)
<> 144:ef7eb2e8f9f7 2031
<> 144:ef7eb2e8f9f7 2032 /**
<> 144:ef7eb2e8f9f7 2033 * @brief Disable event on ETH External event line
<> 144:ef7eb2e8f9f7 2034 * @retval None.
<> 144:ef7eb2e8f9f7 2035 */
<> 144:ef7eb2e8f9f7 2036 #define __HAL_ETH_WAKEUP_EXTI_DISABLE_EVENT() EXTI->EMR &= ~(ETH_EXTI_LINE_WAKEUP)
<> 144:ef7eb2e8f9f7 2037
<> 144:ef7eb2e8f9f7 2038 /**
<> 144:ef7eb2e8f9f7 2039 * @brief Get flag of the ETH External interrupt line.
<> 144:ef7eb2e8f9f7 2040 * @retval None
<> 144:ef7eb2e8f9f7 2041 */
<> 144:ef7eb2e8f9f7 2042 #define __HAL_ETH_WAKEUP_EXTI_GET_FLAG() EXTI->PR & (ETH_EXTI_LINE_WAKEUP)
<> 144:ef7eb2e8f9f7 2043
<> 144:ef7eb2e8f9f7 2044 /**
<> 144:ef7eb2e8f9f7 2045 * @brief Clear flag of the ETH External interrupt line.
<> 144:ef7eb2e8f9f7 2046 * @retval None
<> 144:ef7eb2e8f9f7 2047 */
<> 144:ef7eb2e8f9f7 2048 #define __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG() EXTI->PR = (ETH_EXTI_LINE_WAKEUP)
<> 144:ef7eb2e8f9f7 2049
<> 144:ef7eb2e8f9f7 2050 /**
<> 144:ef7eb2e8f9f7 2051 * @brief Enables rising edge trigger to the ETH External interrupt line.
<> 144:ef7eb2e8f9f7 2052 * @retval None
<> 144:ef7eb2e8f9f7 2053 */
<> 144:ef7eb2e8f9f7 2054 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER() EXTI->RTSR |= ETH_EXTI_LINE_WAKEUP
<> 144:ef7eb2e8f9f7 2055
<> 144:ef7eb2e8f9f7 2056 /**
<> 144:ef7eb2e8f9f7 2057 * @brief Disables the rising edge trigger to the ETH External interrupt line.
<> 144:ef7eb2e8f9f7 2058 * @retval None
<> 144:ef7eb2e8f9f7 2059 */
<> 144:ef7eb2e8f9f7 2060 #define __HAL_ETH_WAKEUP_EXTI_DISABLE_RISING_EDGE_TRIGGER() EXTI->RTSR &= ~(ETH_EXTI_LINE_WAKEUP)
<> 144:ef7eb2e8f9f7 2061
<> 144:ef7eb2e8f9f7 2062 /**
<> 144:ef7eb2e8f9f7 2063 * @brief Enables falling edge trigger to the ETH External interrupt line.
<> 144:ef7eb2e8f9f7 2064 * @retval None
<> 144:ef7eb2e8f9f7 2065 */
<> 144:ef7eb2e8f9f7 2066 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER() EXTI->FTSR |= (ETH_EXTI_LINE_WAKEUP)
<> 144:ef7eb2e8f9f7 2067
<> 144:ef7eb2e8f9f7 2068 /**
<> 144:ef7eb2e8f9f7 2069 * @brief Disables falling edge trigger to the ETH External interrupt line.
<> 144:ef7eb2e8f9f7 2070 * @retval None
<> 144:ef7eb2e8f9f7 2071 */
<> 144:ef7eb2e8f9f7 2072 #define __HAL_ETH_WAKEUP_EXTI_DISABLE_FALLING_EDGE_TRIGGER() EXTI->FTSR &= ~(ETH_EXTI_LINE_WAKEUP)
<> 144:ef7eb2e8f9f7 2073
<> 144:ef7eb2e8f9f7 2074 /**
<> 144:ef7eb2e8f9f7 2075 * @brief Enables rising/falling edge trigger to the ETH External interrupt line.
<> 144:ef7eb2e8f9f7 2076 * @retval None
<> 144:ef7eb2e8f9f7 2077 */
<> 144:ef7eb2e8f9f7 2078 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER() EXTI->RTSR |= ETH_EXTI_LINE_WAKEUP;\
<> 144:ef7eb2e8f9f7 2079 EXTI->FTSR |= ETH_EXTI_LINE_WAKEUP
<> 144:ef7eb2e8f9f7 2080
<> 144:ef7eb2e8f9f7 2081 /**
<> 144:ef7eb2e8f9f7 2082 * @brief Disables rising/falling edge trigger to the ETH External interrupt line.
<> 144:ef7eb2e8f9f7 2083 * @retval None
<> 144:ef7eb2e8f9f7 2084 */
<> 144:ef7eb2e8f9f7 2085 #define __HAL_ETH_WAKEUP_EXTI_DISABLE_FALLINGRISING_TRIGGER() EXTI->RTSR &= ~(ETH_EXTI_LINE_WAKEUP);\
<> 144:ef7eb2e8f9f7 2086 EXTI->FTSR &= ~(ETH_EXTI_LINE_WAKEUP)
<> 144:ef7eb2e8f9f7 2087
<> 144:ef7eb2e8f9f7 2088 /**
<> 144:ef7eb2e8f9f7 2089 * @brief Generate a Software interrupt on selected EXTI line.
<> 144:ef7eb2e8f9f7 2090 * @retval None.
<> 144:ef7eb2e8f9f7 2091 */
<> 144:ef7eb2e8f9f7 2092 #define __HAL_ETH_WAKEUP_EXTI_GENERATE_SWIT() EXTI->SWIER|= ETH_EXTI_LINE_WAKEUP
<> 144:ef7eb2e8f9f7 2093
<> 144:ef7eb2e8f9f7 2094 /**
<> 144:ef7eb2e8f9f7 2095 * @}
<> 144:ef7eb2e8f9f7 2096 */
<> 144:ef7eb2e8f9f7 2097 /* Exported functions --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 2098
<> 144:ef7eb2e8f9f7 2099 /** @addtogroup ETH_Exported_Functions
<> 144:ef7eb2e8f9f7 2100 * @{
<> 144:ef7eb2e8f9f7 2101 */
<> 144:ef7eb2e8f9f7 2102
<> 144:ef7eb2e8f9f7 2103 /* Initialization and de-initialization functions ****************************/
<> 144:ef7eb2e8f9f7 2104
<> 144:ef7eb2e8f9f7 2105 /** @addtogroup ETH_Exported_Functions_Group1
<> 144:ef7eb2e8f9f7 2106 * @{
<> 144:ef7eb2e8f9f7 2107 */
<> 144:ef7eb2e8f9f7 2108 HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth);
<> 144:ef7eb2e8f9f7 2109 HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth);
<> 144:ef7eb2e8f9f7 2110 void HAL_ETH_MspInit(ETH_HandleTypeDef *heth);
<> 144:ef7eb2e8f9f7 2111 void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth);
<> 144:ef7eb2e8f9f7 2112 HAL_StatusTypeDef HAL_ETH_DMATxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMATxDescTab, uint8_t* TxBuff, uint32_t TxBuffCount);
<> 144:ef7eb2e8f9f7 2113 HAL_StatusTypeDef HAL_ETH_DMARxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMARxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount);
<> 144:ef7eb2e8f9f7 2114
<> 144:ef7eb2e8f9f7 2115 /**
<> 144:ef7eb2e8f9f7 2116 * @}
<> 144:ef7eb2e8f9f7 2117 */
<> 144:ef7eb2e8f9f7 2118 /* IO operation functions ****************************************************/
<> 144:ef7eb2e8f9f7 2119
<> 144:ef7eb2e8f9f7 2120 /** @addtogroup ETH_Exported_Functions_Group2
<> 144:ef7eb2e8f9f7 2121 * @{
<> 144:ef7eb2e8f9f7 2122 */
<> 144:ef7eb2e8f9f7 2123 HAL_StatusTypeDef HAL_ETH_TransmitFrame(ETH_HandleTypeDef *heth, uint32_t FrameLength);
<> 144:ef7eb2e8f9f7 2124 HAL_StatusTypeDef HAL_ETH_GetReceivedFrame(ETH_HandleTypeDef *heth);
<> 144:ef7eb2e8f9f7 2125 /* Communication with PHY functions*/
<> 144:ef7eb2e8f9f7 2126 HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t *RegValue);
<> 144:ef7eb2e8f9f7 2127 HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t RegValue);
<> 144:ef7eb2e8f9f7 2128 /* Non-Blocking mode: Interrupt */
<> 144:ef7eb2e8f9f7 2129 HAL_StatusTypeDef HAL_ETH_GetReceivedFrame_IT(ETH_HandleTypeDef *heth);
<> 144:ef7eb2e8f9f7 2130 void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth);
<> 144:ef7eb2e8f9f7 2131 /* Callback in non blocking modes (Interrupt) */
<> 144:ef7eb2e8f9f7 2132 void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth);
<> 144:ef7eb2e8f9f7 2133 void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth);
<> 144:ef7eb2e8f9f7 2134 void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth);
<> 144:ef7eb2e8f9f7 2135 /**
<> 144:ef7eb2e8f9f7 2136 * @}
<> 144:ef7eb2e8f9f7 2137 */
<> 144:ef7eb2e8f9f7 2138
<> 144:ef7eb2e8f9f7 2139 /* Peripheral Control functions **********************************************/
<> 144:ef7eb2e8f9f7 2140
<> 144:ef7eb2e8f9f7 2141 /** @addtogroup ETH_Exported_Functions_Group3
<> 144:ef7eb2e8f9f7 2142 * @{
<> 144:ef7eb2e8f9f7 2143 */
<> 144:ef7eb2e8f9f7 2144
<> 144:ef7eb2e8f9f7 2145 HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth);
<> 144:ef7eb2e8f9f7 2146 HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth);
<> 144:ef7eb2e8f9f7 2147 HAL_StatusTypeDef HAL_ETH_ConfigMAC(ETH_HandleTypeDef *heth, ETH_MACInitTypeDef *macconf);
<> 144:ef7eb2e8f9f7 2148 HAL_StatusTypeDef HAL_ETH_ConfigDMA(ETH_HandleTypeDef *heth, ETH_DMAInitTypeDef *dmaconf);
<> 144:ef7eb2e8f9f7 2149 /**
<> 144:ef7eb2e8f9f7 2150 * @}
<> 144:ef7eb2e8f9f7 2151 */
<> 144:ef7eb2e8f9f7 2152
<> 144:ef7eb2e8f9f7 2153 /* Peripheral State functions ************************************************/
<> 144:ef7eb2e8f9f7 2154
<> 144:ef7eb2e8f9f7 2155 /** @addtogroup ETH_Exported_Functions_Group4
<> 144:ef7eb2e8f9f7 2156 * @{
<> 144:ef7eb2e8f9f7 2157 */
<> 144:ef7eb2e8f9f7 2158 HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth);
<> 144:ef7eb2e8f9f7 2159 /**
<> 144:ef7eb2e8f9f7 2160 * @}
<> 144:ef7eb2e8f9f7 2161 */
<> 144:ef7eb2e8f9f7 2162
<> 144:ef7eb2e8f9f7 2163 /**
<> 144:ef7eb2e8f9f7 2164 * @}
<> 144:ef7eb2e8f9f7 2165 */
<> 144:ef7eb2e8f9f7 2166
<> 144:ef7eb2e8f9f7 2167 /**
<> 144:ef7eb2e8f9f7 2168 * @}
<> 144:ef7eb2e8f9f7 2169 */
<> 144:ef7eb2e8f9f7 2170
<> 144:ef7eb2e8f9f7 2171 /**
<> 144:ef7eb2e8f9f7 2172 * @}
<> 144:ef7eb2e8f9f7 2173 */
<> 157:ff67d9f36b67 2174 #endif /* ETH */
<> 157:ff67d9f36b67 2175
<> 144:ef7eb2e8f9f7 2176 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 2177 }
<> 144:ef7eb2e8f9f7 2178 #endif
<> 144:ef7eb2e8f9f7 2179
<> 144:ef7eb2e8f9f7 2180 #endif /* __STM32F7xx_HAL_ETH_H */
<> 144:ef7eb2e8f9f7 2181
<> 144:ef7eb2e8f9f7 2182
<> 144:ef7eb2e8f9f7 2183
<> 144:ef7eb2e8f9f7 2184 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/