mbed-dev | Mbed

Users » mbed_official » Code » mbed-dev

Dependents: Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_i2c.c@170:19eb464bc2be, 2017-08-03 (annotated)

Committer:: Kojto
Date:: Thu Aug 03 13:13:39 2017 +0100
Revision:: 170:19eb464bc2be
Parent:: 167:e84263d55307
Child:: 182:a56a73fd2a6f

This updates the lib to the mbed lib v 148

Who changed what in which revision?

User	Revision	Line number	New contents of line
<>	144:ef7eb2e8f9f7	1	/**
<>	144:ef7eb2e8f9f7	2	******************************************************************************
<>	144:ef7eb2e8f9f7	3	* @file stm32f4xx_hal_i2c.c
<>	144:ef7eb2e8f9f7	4	* @author MCD Application Team
AnnaBridge	167:e84263d55307	5	* @version V1.7.1
AnnaBridge	167:e84263d55307	6	* @date 14-April-2017
<>	144:ef7eb2e8f9f7	7	* @brief I2C HAL module driver.
<>	144:ef7eb2e8f9f7	8	* This file provides firmware functions to manage the following
<>	144:ef7eb2e8f9f7	9	* functionalities of the Inter Integrated Circuit (I2C) peripheral:
<>	144:ef7eb2e8f9f7	10	* + Initialization and de-initialization functions
<>	144:ef7eb2e8f9f7	11	* + IO operation functions
AnnaBridge	167:e84263d55307	12	* + Peripheral State, Mode and Error functions
<>	144:ef7eb2e8f9f7	13	*
<>	144:ef7eb2e8f9f7	14	@verbatim
<>	144:ef7eb2e8f9f7	15	==============================================================================
<>	144:ef7eb2e8f9f7	16	##### How to use this driver #####
<>	144:ef7eb2e8f9f7	17	==============================================================================
<>	144:ef7eb2e8f9f7	18	[..]
<>	144:ef7eb2e8f9f7	19	The I2C HAL driver can be used as follows:
<>	144:ef7eb2e8f9f7	20
<>	144:ef7eb2e8f9f7	21	(#) Declare a I2C_HandleTypeDef handle structure, for example:
<>	144:ef7eb2e8f9f7	22	I2C_HandleTypeDef hi2c;
<>	144:ef7eb2e8f9f7	23
AnnaBridge	167:e84263d55307	24	(#)Initialize the I2C low level resources by implementing the HAL_I2C_MspInit() API:
<>	144:ef7eb2e8f9f7	25	(##) Enable the I2Cx interface clock
<>	144:ef7eb2e8f9f7	26	(##) I2C pins configuration
<>	144:ef7eb2e8f9f7	27	(+++) Enable the clock for the I2C GPIOs
<>	144:ef7eb2e8f9f7	28	(+++) Configure I2C pins as alternate function open-drain
<>	144:ef7eb2e8f9f7	29	(##) NVIC configuration if you need to use interrupt process
<>	144:ef7eb2e8f9f7	30	(+++) Configure the I2Cx interrupt priority
<>	144:ef7eb2e8f9f7	31	(+++) Enable the NVIC I2C IRQ Channel
<>	144:ef7eb2e8f9f7	32	(##) DMA Configuration if you need to use DMA process
<>	144:ef7eb2e8f9f7	33	(+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive stream
<>	144:ef7eb2e8f9f7	34	(+++) Enable the DMAx interface clock using
<>	144:ef7eb2e8f9f7	35	(+++) Configure the DMA handle parameters
<>	144:ef7eb2e8f9f7	36	(+++) Configure the DMA Tx or Rx Stream
<>	144:ef7eb2e8f9f7	37	(+++) Associate the initialized DMA handle to the hi2c DMA Tx or Rx handle
<>	144:ef7eb2e8f9f7	38	(+++) Configure the priority and enable the NVIC for the transfer complete interrupt on
<>	144:ef7eb2e8f9f7	39	the DMA Tx or Rx Stream
<>	144:ef7eb2e8f9f7	40
<>	144:ef7eb2e8f9f7	41	(#) Configure the Communication Speed, Duty cycle, Addressing mode, Own Address1,
<>	144:ef7eb2e8f9f7	42	Dual Addressing mode, Own Address2, General call and Nostretch mode in the hi2c Init structure.
<>	144:ef7eb2e8f9f7	43
<>	144:ef7eb2e8f9f7	44	(#) Initialize the I2C registers by calling the HAL_I2C_Init(), configures also the low level Hardware
<>	144:ef7eb2e8f9f7	45	(GPIO, CLOCK, NVIC...etc) by calling the customized HAL_I2C_MspInit(&hi2c) API.
<>	144:ef7eb2e8f9f7	46
<>	144:ef7eb2e8f9f7	47	(#) To check if target device is ready for communication, use the function HAL_I2C_IsDeviceReady()
<>	144:ef7eb2e8f9f7	48
<>	144:ef7eb2e8f9f7	49	(#) For I2C IO and IO MEM operations, three operation modes are available within this driver :
<>	144:ef7eb2e8f9f7	50
<>	144:ef7eb2e8f9f7	51	* Polling mode IO operation *
<>	144:ef7eb2e8f9f7	52	=================================
<>	144:ef7eb2e8f9f7	53	[..]
<>	144:ef7eb2e8f9f7	54	(+) Transmit in master mode an amount of data in blocking mode using HAL_I2C_Master_Transmit()
<>	144:ef7eb2e8f9f7	55	(+) Receive in master mode an amount of data in blocking mode using HAL_I2C_Master_Receive()
<>	144:ef7eb2e8f9f7	56	(+) Transmit in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Transmit()
<>	144:ef7eb2e8f9f7	57	(+) Receive in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Receive()
<>	144:ef7eb2e8f9f7	58
<>	144:ef7eb2e8f9f7	59	* Polling mode IO MEM operation *
<>	144:ef7eb2e8f9f7	60	=====================================
<>	144:ef7eb2e8f9f7	61	[..]
<>	144:ef7eb2e8f9f7	62	(+) Write an amount of data in blocking mode to a specific memory address using HAL_I2C_Mem_Write()
<>	144:ef7eb2e8f9f7	63	(+) Read an amount of data in blocking mode from a specific memory address using HAL_I2C_Mem_Read()
<>	144:ef7eb2e8f9f7	64
<>	144:ef7eb2e8f9f7	65
<>	144:ef7eb2e8f9f7	66	* Interrupt mode IO operation *
<>	144:ef7eb2e8f9f7	67	===================================
<>	144:ef7eb2e8f9f7	68	[..]
<>	144:ef7eb2e8f9f7	69	(+) Transmit in master mode an amount of data in non blocking mode using HAL_I2C_Master_Transmit_IT()
<>	144:ef7eb2e8f9f7	70	(+) At transmission end of transfer HAL_I2C_MasterTxCpltCallback is executed and user can
<>	144:ef7eb2e8f9f7	71	add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback
<>	144:ef7eb2e8f9f7	72	(+) Receive in master mode an amount of data in non blocking mode using HAL_I2C_Master_Receive_IT()
<>	144:ef7eb2e8f9f7	73	(+) At reception end of transfer HAL_I2C_MasterRxCpltCallback is executed and user can
<>	144:ef7eb2e8f9f7	74	add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback
<>	144:ef7eb2e8f9f7	75	(+) Transmit in slave mode an amount of data in non blocking mode using HAL_I2C_Slave_Transmit_IT()
<>	144:ef7eb2e8f9f7	76	(+) At transmission end of transfer HAL_I2C_SlaveTxCpltCallback is executed and user can
<>	144:ef7eb2e8f9f7	77	add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback
<>	144:ef7eb2e8f9f7	78	(+) Receive in slave mode an amount of data in non blocking mode using HAL_I2C_Slave_Receive_IT()
<>	144:ef7eb2e8f9f7	79	(+) At reception end of transfer HAL_I2C_SlaveRxCpltCallback is executed and user can
<>	144:ef7eb2e8f9f7	80	add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback
<>	144:ef7eb2e8f9f7	81	(+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
<>	144:ef7eb2e8f9f7	82	add his own code by customization of function pointer HAL_I2C_ErrorCallback
AnnaBridge	167:e84263d55307	83	(+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
AnnaBridge	167:e84263d55307	84	(+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can
AnnaBridge	167:e84263d55307	85	add his own code by customization of function pointer HAL_I2C_AbortCpltCallback()
<>	144:ef7eb2e8f9f7	86
<>	144:ef7eb2e8f9f7	87	* Interrupt mode IO sequential operation *
<>	144:ef7eb2e8f9f7	88	==============================================
<>	144:ef7eb2e8f9f7	89	[..]
AnnaBridge	167:e84263d55307	90	(@) These interfaces allow to manage a sequential transfer with a repeated start condition
<>	144:ef7eb2e8f9f7	91	when a direction change during transfer
AnnaBridge	167:e84263d55307	92	[..]
AnnaBridge	167:e84263d55307	93	(+) A specific option field manage the different steps of a sequential transfer
AnnaBridge	167:e84263d55307	94	(+) Option field values are defined through @ref I2C_XFEROPTIONS and are listed below:
<>	144:ef7eb2e8f9f7	95	(++) I2C_FIRST_AND_LAST_FRAME: No sequential usage, functionnal is same as associated interfaces in no sequential mode
AnnaBridge	167:e84263d55307	96	(++) I2C_FIRST_FRAME: Sequential usage, this option allow to manage a sequence with start condition, address
AnnaBridge	167:e84263d55307	97	and data to transfer without a final stop condition
AnnaBridge	167:e84263d55307	98	(++) I2C_NEXT_FRAME: Sequential usage, this option allow to manage a sequence with a restart condition, address
AnnaBridge	167:e84263d55307	99	and with new data to transfer if the direction change or manage only the new data to transfer
AnnaBridge	167:e84263d55307	100	if no direction change and without a final stop condition in both cases
AnnaBridge	167:e84263d55307	101	(++) I2C_LAST_FRAME: Sequential usage, this option allow to manage a sequance with a restart condition, address
AnnaBridge	167:e84263d55307	102	and with new data to transfer if the direction change or manage only the new data to transfer
AnnaBridge	167:e84263d55307	103	if no direction change and with a final stop condition in both cases
AnnaBridge	167:e84263d55307	104
AnnaBridge	167:e84263d55307	105	(+) Differents sequential I2C interfaces are listed below:
AnnaBridge	167:e84263d55307	106	(++) Sequential transmit in master I2C mode an amount of data in non-blocking mode using HAL_I2C_Master_Sequential_Transmit_IT()
AnnaBridge	167:e84263d55307	107	(+++) At transmission end of current frame transfer, HAL_I2C_MasterTxCpltCallback() is executed and user can
<>	144:ef7eb2e8f9f7	108	add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback()
AnnaBridge	167:e84263d55307	109	(++) Sequential receive in master I2C mode an amount of data in non-blocking mode using HAL_I2C_Master_Sequential_Receive_IT()
AnnaBridge	167:e84263d55307	110	(+++) At reception end of current frame transfer, HAL_I2C_MasterRxCpltCallback() is executed and user can
<>	144:ef7eb2e8f9f7	111	add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
AnnaBridge	167:e84263d55307	112	(++) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
AnnaBridge	167:e84263d55307	113	(+++) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can
AnnaBridge	167:e84263d55307	114	add his own code by customization of function pointer HAL_I2C_AbortCpltCallback()
AnnaBridge	167:e84263d55307	115	(++) Enable/disable the Address listen mode in slave I2C mode using HAL_I2C_EnableListen_IT() HAL_I2C_DisableListen_IT()
AnnaBridge	167:e84263d55307	116	(+++) When address slave I2C match, HAL_I2C_AddrCallback() is executed and user can
<>	144:ef7eb2e8f9f7	117	add his own code to check the Address Match Code and the transmission direction request by master (Write/Read).
AnnaBridge	167:e84263d55307	118	(+++) At Listen mode end HAL_I2C_ListenCpltCallback() is executed and user can
<>	144:ef7eb2e8f9f7	119	add his own code by customization of function pointer HAL_I2C_ListenCpltCallback()
AnnaBridge	167:e84263d55307	120	(++) Sequential transmit in slave I2C mode an amount of data in non-blocking mode using HAL_I2C_Slave_Sequential_Transmit_IT()
AnnaBridge	167:e84263d55307	121	(+++) At transmission end of current frame transfer, HAL_I2C_SlaveTxCpltCallback() is executed and user can
<>	144:ef7eb2e8f9f7	122	add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback()
AnnaBridge	167:e84263d55307	123	(++) Sequential receive in slave I2C mode an amount of data in non-blocking mode using HAL_I2C_Slave_Sequential_Receive_IT()
AnnaBridge	167:e84263d55307	124	(+++) At reception end of current frame transfer, HAL_I2C_SlaveRxCpltCallback() is executed and user can
<>	144:ef7eb2e8f9f7	125	add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
AnnaBridge	167:e84263d55307	126	(++) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
AnnaBridge	167:e84263d55307	127	add his own code by customization of function pointer HAL_I2C_ErrorCallback()
AnnaBridge	167:e84263d55307	128	(++) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
AnnaBridge	167:e84263d55307	129	(++) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can
AnnaBridge	167:e84263d55307	130	add his own code by customization of function pointer HAL_I2C_AbortCpltCallback()
<>	144:ef7eb2e8f9f7	131
<>	144:ef7eb2e8f9f7	132	* Interrupt mode IO MEM operation *
<>	144:ef7eb2e8f9f7	133	=======================================
<>	144:ef7eb2e8f9f7	134	[..]
<>	144:ef7eb2e8f9f7	135	(+) Write an amount of data in no-blocking mode with Interrupt to a specific memory address using
<>	144:ef7eb2e8f9f7	136	HAL_I2C_Mem_Write_IT()
<>	144:ef7eb2e8f9f7	137	(+) At MEM end of write transfer HAL_I2C_MemTxCpltCallback is executed and user can
<>	144:ef7eb2e8f9f7	138	add his own code by customization of function pointer HAL_I2C_MemTxCpltCallback
<>	144:ef7eb2e8f9f7	139	(+) Read an amount of data in no-blocking mode with Interrupt from a specific memory address using
<>	144:ef7eb2e8f9f7	140	HAL_I2C_Mem_Read_IT()
<>	144:ef7eb2e8f9f7	141	(+) At MEM end of read transfer HAL_I2C_MemRxCpltCallback is executed and user can
<>	144:ef7eb2e8f9f7	142	add his own code by customization of function pointer HAL_I2C_MemRxCpltCallback
<>	144:ef7eb2e8f9f7	143	(+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
<>	144:ef7eb2e8f9f7	144	add his own code by customization of function pointer HAL_I2C_ErrorCallback
<>	144:ef7eb2e8f9f7	145
<>	144:ef7eb2e8f9f7	146	* DMA mode IO operation *
<>	144:ef7eb2e8f9f7	147	==============================
<>	144:ef7eb2e8f9f7	148	[..]
<>	144:ef7eb2e8f9f7	149	(+) Transmit in master mode an amount of data in non blocking mode (DMA) using
<>	144:ef7eb2e8f9f7	150	HAL_I2C_Master_Transmit_DMA()
<>	144:ef7eb2e8f9f7	151	(+) At transmission end of transfer HAL_I2C_MasterTxCpltCallback is executed and user can
<>	144:ef7eb2e8f9f7	152	add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback
<>	144:ef7eb2e8f9f7	153	(+) Receive in master mode an amount of data in non blocking mode (DMA) using
<>	144:ef7eb2e8f9f7	154	HAL_I2C_Master_Receive_DMA()
<>	144:ef7eb2e8f9f7	155	(+) At reception end of transfer HAL_I2C_MasterRxCpltCallback is executed and user can
<>	144:ef7eb2e8f9f7	156	add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback
<>	144:ef7eb2e8f9f7	157	(+) Transmit in slave mode an amount of data in non blocking mode (DMA) using
<>	144:ef7eb2e8f9f7	158	HAL_I2C_Slave_Transmit_DMA()
<>	144:ef7eb2e8f9f7	159	(+) At transmission end of transfer HAL_I2C_SlaveTxCpltCallback is executed and user can
<>	144:ef7eb2e8f9f7	160	add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback
<>	144:ef7eb2e8f9f7	161	(+) Receive in slave mode an amount of data in non blocking mode (DMA) using
<>	144:ef7eb2e8f9f7	162	HAL_I2C_Slave_Receive_DMA()
<>	144:ef7eb2e8f9f7	163	(+) At reception end of transfer HAL_I2C_SlaveRxCpltCallback is executed and user can
<>	144:ef7eb2e8f9f7	164	add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback
<>	144:ef7eb2e8f9f7	165	(+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
<>	144:ef7eb2e8f9f7	166	add his own code by customization of function pointer HAL_I2C_ErrorCallback
AnnaBridge	167:e84263d55307	167	(+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
AnnaBridge	167:e84263d55307	168	(+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can
AnnaBridge	167:e84263d55307	169	add his own code by customization of function pointer HAL_I2C_AbortCpltCallback()
<>	144:ef7eb2e8f9f7	170
<>	144:ef7eb2e8f9f7	171	* DMA mode IO MEM operation *
<>	144:ef7eb2e8f9f7	172	=================================
<>	144:ef7eb2e8f9f7	173	[..]
<>	144:ef7eb2e8f9f7	174	(+) Write an amount of data in no-blocking mode with DMA to a specific memory address using
<>	144:ef7eb2e8f9f7	175	HAL_I2C_Mem_Write_DMA()
<>	144:ef7eb2e8f9f7	176	(+) At MEM end of write transfer HAL_I2C_MemTxCpltCallback is executed and user can
<>	144:ef7eb2e8f9f7	177	add his own code by customization of function pointer HAL_I2C_MemTxCpltCallback
<>	144:ef7eb2e8f9f7	178	(+) Read an amount of data in no-blocking mode with DMA from a specific memory address using
<>	144:ef7eb2e8f9f7	179	HAL_I2C_Mem_Read_DMA()
<>	144:ef7eb2e8f9f7	180	(+) At MEM end of read transfer HAL_I2C_MemRxCpltCallback is executed and user can
<>	144:ef7eb2e8f9f7	181	add his own code by customization of function pointer HAL_I2C_MemRxCpltCallback
<>	144:ef7eb2e8f9f7	182	(+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
<>	144:ef7eb2e8f9f7	183	add his own code by customization of function pointer HAL_I2C_ErrorCallback
<>	144:ef7eb2e8f9f7	184
<>	144:ef7eb2e8f9f7	185
<>	144:ef7eb2e8f9f7	186	* I2C HAL driver macros list *
<>	144:ef7eb2e8f9f7	187	==================================
<>	144:ef7eb2e8f9f7	188	[..]
<>	144:ef7eb2e8f9f7	189	Below the list of most used macros in I2C HAL driver.
<>	144:ef7eb2e8f9f7	190
<>	144:ef7eb2e8f9f7	191	(+) __HAL_I2C_ENABLE: Enable the I2C peripheral
<>	144:ef7eb2e8f9f7	192	(+) __HAL_I2C_DISABLE: Disable the I2C peripheral
AnnaBridge	167:e84263d55307	193	(+) __HAL_I2C_GET_FLAG : Checks whether the specified I2C flag is set or not
AnnaBridge	167:e84263d55307	194	(+) __HAL_I2C_CLEAR_FLAG : Clear the specified I2C pending flag
<>	144:ef7eb2e8f9f7	195	(+) __HAL_I2C_ENABLE_IT: Enable the specified I2C interrupt
<>	144:ef7eb2e8f9f7	196	(+) __HAL_I2C_DISABLE_IT: Disable the specified I2C interrupt
<>	144:ef7eb2e8f9f7	197
<>	144:ef7eb2e8f9f7	198	[..]
<>	144:ef7eb2e8f9f7	199	(@) You can refer to the I2C HAL driver header file for more useful macros
<>	144:ef7eb2e8f9f7	200
<>	144:ef7eb2e8f9f7	201
<>	144:ef7eb2e8f9f7	202	@endverbatim
<>	144:ef7eb2e8f9f7	203	******************************************************************************
<>	144:ef7eb2e8f9f7	204	* @attention
<>	144:ef7eb2e8f9f7	205	*
AnnaBridge	167:e84263d55307	206	* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
<>	144:ef7eb2e8f9f7	207	*
<>	144:ef7eb2e8f9f7	208	* Redistribution and use in source and binary forms, with or without modification,
<>	144:ef7eb2e8f9f7	209	* are permitted provided that the following conditions are met:
<>	144:ef7eb2e8f9f7	210	* 1. Redistributions of source code must retain the above copyright notice,
<>	144:ef7eb2e8f9f7	211	* this list of conditions and the following disclaimer.
<>	144:ef7eb2e8f9f7	212	* 2. Redistributions in binary form must reproduce the above copyright notice,
<>	144:ef7eb2e8f9f7	213	* this list of conditions and the following disclaimer in the documentation
<>	144:ef7eb2e8f9f7	214	* and/or other materials provided with the distribution.
<>	144:ef7eb2e8f9f7	215	* 3. Neither the name of STMicroelectronics nor the names of its contributors
<>	144:ef7eb2e8f9f7	216	* may be used to endorse or promote products derived from this software
<>	144:ef7eb2e8f9f7	217	* without specific prior written permission.
<>	144:ef7eb2e8f9f7	218	*
<>	144:ef7eb2e8f9f7	219	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<>	144:ef7eb2e8f9f7	220	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<>	144:ef7eb2e8f9f7	221	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<>	144:ef7eb2e8f9f7	222	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<>	144:ef7eb2e8f9f7	223	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<>	144:ef7eb2e8f9f7	224	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<>	144:ef7eb2e8f9f7	225	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<>	144:ef7eb2e8f9f7	226	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<>	144:ef7eb2e8f9f7	227	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<>	144:ef7eb2e8f9f7	228	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<>	144:ef7eb2e8f9f7	229	*
<>	144:ef7eb2e8f9f7	230	******************************************************************************
<>	144:ef7eb2e8f9f7	231	*/
<>	144:ef7eb2e8f9f7	232
<>	144:ef7eb2e8f9f7	233	/* Includes ------------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	234	#include "stm32f4xx_hal.h"
<>	144:ef7eb2e8f9f7	235
<>	144:ef7eb2e8f9f7	236	/** @addtogroup STM32F4xx_HAL_Driver
<>	144:ef7eb2e8f9f7	237	* @{
<>	144:ef7eb2e8f9f7	238	*/
<>	144:ef7eb2e8f9f7	239
<>	144:ef7eb2e8f9f7	240	/** @defgroup I2C I2C
<>	144:ef7eb2e8f9f7	241	* @brief I2C HAL module driver
<>	144:ef7eb2e8f9f7	242	* @{
<>	144:ef7eb2e8f9f7	243	*/
<>	144:ef7eb2e8f9f7	244
<>	144:ef7eb2e8f9f7	245	#ifdef HAL_I2C_MODULE_ENABLED
<>	144:ef7eb2e8f9f7	246
<>	144:ef7eb2e8f9f7	247	/* Private typedef -----------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	248	/* Private define ------------------------------------------------------------*/
AnnaBridge	167:e84263d55307	249	/** @addtogroup I2C_Private_Define
<>	144:ef7eb2e8f9f7	250	* @{
<>	144:ef7eb2e8f9f7	251	*/
AnnaBridge	167:e84263d55307	252	#define I2C_TIMEOUT_FLAG 35U /!< Timeout 35 ms /
AnnaBridge	167:e84263d55307	253	#define I2C_TIMEOUT_BUSY_FLAG 25U /!< Timeout 25 ms /
AnnaBridge	167:e84263d55307	254	#define I2C_NO_OPTION_FRAME 0xFFFF0000U /!< XferOptions default value /
<>	144:ef7eb2e8f9f7	255
<>	144:ef7eb2e8f9f7	256	/* Private define for @ref PreviousState usage */
<>	144:ef7eb2e8f9f7	257	#define I2C_STATE_MSK ((uint32_t)((HAL_I2C_STATE_BUSY_TX \| HAL_I2C_STATE_BUSY_RX) & (~(uint32_t)HAL_I2C_STATE_READY))) /!< Mask State define, keep only RX and TX bits /
<>	144:ef7eb2e8f9f7	258	#define I2C_STATE_NONE ((uint32_t)(HAL_I2C_MODE_NONE)) /!< Default Value /
<>	144:ef7eb2e8f9f7	259	#define I2C_STATE_MASTER_BUSY_TX ((uint32_t)((HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) \| HAL_I2C_MODE_MASTER)) /!< Master Busy TX, combinaison of State LSB and Mode enum /
<>	144:ef7eb2e8f9f7	260	#define I2C_STATE_MASTER_BUSY_RX ((uint32_t)((HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) \| HAL_I2C_MODE_MASTER)) /!< Master Busy RX, combinaison of State LSB and Mode enum /
<>	144:ef7eb2e8f9f7	261	#define I2C_STATE_SLAVE_BUSY_TX ((uint32_t)((HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) \| HAL_I2C_MODE_SLAVE)) /!< Slave Busy TX, combinaison of State LSB and Mode enum /
<>	144:ef7eb2e8f9f7	262	#define I2C_STATE_SLAVE_BUSY_RX ((uint32_t)((HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) \| HAL_I2C_MODE_SLAVE)) /!< Slave Busy RX, combinaison of State LSB and Mode enum /
<>	144:ef7eb2e8f9f7	263
<>	144:ef7eb2e8f9f7	264	/**
<>	144:ef7eb2e8f9f7	265	* @}
<>	144:ef7eb2e8f9f7	266	*/
<>	144:ef7eb2e8f9f7	267
<>	144:ef7eb2e8f9f7	268	/* Private macro -------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	269	/* Private variables ---------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	270	/* Private function prototypes -----------------------------------------------*/
<>	144:ef7eb2e8f9f7	271	/** @addtogroup I2C_Private_Functions
<>	144:ef7eb2e8f9f7	272	* @{
<>	144:ef7eb2e8f9f7	273	*/
<>	144:ef7eb2e8f9f7	274	/* Private functions to handle DMA transfer */
<>	144:ef7eb2e8f9f7	275	static void I2C_DMAXferCplt(DMA_HandleTypeDef *hdma);
<>	144:ef7eb2e8f9f7	276	static void I2C_DMAError(DMA_HandleTypeDef *hdma);
<>	144:ef7eb2e8f9f7	277	static void I2C_DMAAbort(DMA_HandleTypeDef *hdma);
<>	144:ef7eb2e8f9f7	278
<>	144:ef7eb2e8f9f7	279	static void I2C_ITError(I2C_HandleTypeDef *hi2c);
<>	144:ef7eb2e8f9f7	280
<>	144:ef7eb2e8f9f7	281	static HAL_StatusTypeDef I2C_MasterRequestWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout, uint32_t Tickstart);
<>	144:ef7eb2e8f9f7	282	static HAL_StatusTypeDef I2C_MasterRequestRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout, uint32_t Tickstart);
<>	144:ef7eb2e8f9f7	283	static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart);
<>	144:ef7eb2e8f9f7	284	static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart);
<>	144:ef7eb2e8f9f7	285	static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart);
<>	144:ef7eb2e8f9f7	286	static HAL_StatusTypeDef I2C_WaitOnMasterAddressFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, uint32_t Timeout, uint32_t Tickstart);
<>	144:ef7eb2e8f9f7	287	static HAL_StatusTypeDef I2C_WaitOnTXEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
<>	144:ef7eb2e8f9f7	288	static HAL_StatusTypeDef I2C_WaitOnBTFFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
<>	144:ef7eb2e8f9f7	289	static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
<>	144:ef7eb2e8f9f7	290	static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
<>	144:ef7eb2e8f9f7	291	static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c);
<>	144:ef7eb2e8f9f7	292
<>	144:ef7eb2e8f9f7	293	/* Private functions for I2C transfer IRQ handler */
<>	144:ef7eb2e8f9f7	294	static HAL_StatusTypeDef I2C_MasterTransmit_TXE(I2C_HandleTypeDef *hi2c);
<>	144:ef7eb2e8f9f7	295	static HAL_StatusTypeDef I2C_MasterTransmit_BTF(I2C_HandleTypeDef *hi2c);
<>	144:ef7eb2e8f9f7	296	static HAL_StatusTypeDef I2C_MasterReceive_RXNE(I2C_HandleTypeDef *hi2c);
<>	144:ef7eb2e8f9f7	297	static HAL_StatusTypeDef I2C_MasterReceive_BTF(I2C_HandleTypeDef *hi2c);
<>	144:ef7eb2e8f9f7	298	static HAL_StatusTypeDef I2C_Master_SB(I2C_HandleTypeDef *hi2c);
<>	144:ef7eb2e8f9f7	299	static HAL_StatusTypeDef I2C_Master_ADD10(I2C_HandleTypeDef *hi2c);
<>	144:ef7eb2e8f9f7	300	static HAL_StatusTypeDef I2C_Master_ADDR(I2C_HandleTypeDef *hi2c);
<>	144:ef7eb2e8f9f7	301
<>	144:ef7eb2e8f9f7	302	static HAL_StatusTypeDef I2C_SlaveTransmit_TXE(I2C_HandleTypeDef *hi2c);
<>	144:ef7eb2e8f9f7	303	static HAL_StatusTypeDef I2C_SlaveTransmit_BTF(I2C_HandleTypeDef *hi2c);
<>	144:ef7eb2e8f9f7	304	static HAL_StatusTypeDef I2C_SlaveReceive_RXNE(I2C_HandleTypeDef *hi2c);
<>	144:ef7eb2e8f9f7	305	static HAL_StatusTypeDef I2C_SlaveReceive_BTF(I2C_HandleTypeDef *hi2c);
<>	144:ef7eb2e8f9f7	306	static HAL_StatusTypeDef I2C_Slave_ADDR(I2C_HandleTypeDef *hi2c);
<>	144:ef7eb2e8f9f7	307	static HAL_StatusTypeDef I2C_Slave_STOPF(I2C_HandleTypeDef *hi2c);
<>	144:ef7eb2e8f9f7	308	static HAL_StatusTypeDef I2C_Slave_AF(I2C_HandleTypeDef *hi2c);
<>	144:ef7eb2e8f9f7	309	/**
<>	144:ef7eb2e8f9f7	310	* @}
<>	144:ef7eb2e8f9f7	311	*/
<>	144:ef7eb2e8f9f7	312
<>	144:ef7eb2e8f9f7	313	/* Exported functions --------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	314	/** @defgroup I2C_Exported_Functions I2C Exported Functions
<>	144:ef7eb2e8f9f7	315	* @{
<>	144:ef7eb2e8f9f7	316	*/
<>	144:ef7eb2e8f9f7	317
<>	144:ef7eb2e8f9f7	318	/** @defgroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions
<>	144:ef7eb2e8f9f7	319	* @brief Initialization and Configuration functions
<>	144:ef7eb2e8f9f7	320	*
<>	144:ef7eb2e8f9f7	321	@verbatim
<>	144:ef7eb2e8f9f7	322	===============================================================================
<>	144:ef7eb2e8f9f7	323	##### Initialization and de-initialization functions #####
<>	144:ef7eb2e8f9f7	324	===============================================================================
<>	144:ef7eb2e8f9f7	325	[..] This subsection provides a set of functions allowing to initialize and
<>	144:ef7eb2e8f9f7	326	de-initialize the I2Cx peripheral:
<>	144:ef7eb2e8f9f7	327
<>	144:ef7eb2e8f9f7	328	(+) User must Implement HAL_I2C_MspInit() function in which he configures
<>	144:ef7eb2e8f9f7	329	all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC).
<>	144:ef7eb2e8f9f7	330
<>	144:ef7eb2e8f9f7	331	(+) Call the function HAL_I2C_Init() to configure the selected device with
<>	144:ef7eb2e8f9f7	332	the selected configuration:
<>	144:ef7eb2e8f9f7	333	(++) Communication Speed
<>	144:ef7eb2e8f9f7	334	(++) Duty cycle
<>	144:ef7eb2e8f9f7	335	(++) Addressing mode
<>	144:ef7eb2e8f9f7	336	(++) Own Address 1
<>	144:ef7eb2e8f9f7	337	(++) Dual Addressing mode
<>	144:ef7eb2e8f9f7	338	(++) Own Address 2
<>	144:ef7eb2e8f9f7	339	(++) General call mode
<>	144:ef7eb2e8f9f7	340	(++) Nostretch mode
<>	144:ef7eb2e8f9f7	341
<>	144:ef7eb2e8f9f7	342	(+) Call the function HAL_I2C_DeInit() to restore the default configuration
<>	144:ef7eb2e8f9f7	343	of the selected I2Cx peripheral.
<>	144:ef7eb2e8f9f7	344
<>	144:ef7eb2e8f9f7	345	@endverbatim
<>	144:ef7eb2e8f9f7	346	* @{
<>	144:ef7eb2e8f9f7	347	*/
<>	144:ef7eb2e8f9f7	348
<>	144:ef7eb2e8f9f7	349	/**
<>	144:ef7eb2e8f9f7	350	* @brief Initializes the I2C according to the specified parameters
<>	144:ef7eb2e8f9f7	351	* in the I2C_InitTypeDef and create the associated handle.
AnnaBridge	167:e84263d55307	352	* @param hi2c: pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	353	* the configuration information for I2C module
<>	144:ef7eb2e8f9f7	354	* @retval HAL status
<>	144:ef7eb2e8f9f7	355	*/
<>	144:ef7eb2e8f9f7	356	HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c)
<>	144:ef7eb2e8f9f7	357	{
<>	144:ef7eb2e8f9f7	358	uint32_t freqrange = 0U;
<>	144:ef7eb2e8f9f7	359	uint32_t pclk1 = 0U;
<>	144:ef7eb2e8f9f7	360
<>	144:ef7eb2e8f9f7	361	/* Check the I2C handle allocation */
<>	144:ef7eb2e8f9f7	362	if(hi2c == NULL)
<>	144:ef7eb2e8f9f7	363	{
<>	144:ef7eb2e8f9f7	364	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	365	}
<>	144:ef7eb2e8f9f7	366
<>	144:ef7eb2e8f9f7	367	/* Check the parameters */
<>	144:ef7eb2e8f9f7	368	assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
<>	144:ef7eb2e8f9f7	369	assert_param(IS_I2C_CLOCK_SPEED(hi2c->Init.ClockSpeed));
<>	144:ef7eb2e8f9f7	370	assert_param(IS_I2C_DUTY_CYCLE(hi2c->Init.DutyCycle));
<>	144:ef7eb2e8f9f7	371	assert_param(IS_I2C_OWN_ADDRESS1(hi2c->Init.OwnAddress1));
<>	144:ef7eb2e8f9f7	372	assert_param(IS_I2C_ADDRESSING_MODE(hi2c->Init.AddressingMode));
<>	144:ef7eb2e8f9f7	373	assert_param(IS_I2C_DUAL_ADDRESS(hi2c->Init.DualAddressMode));
<>	144:ef7eb2e8f9f7	374	assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2));
<>	144:ef7eb2e8f9f7	375	assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode));
<>	144:ef7eb2e8f9f7	376	assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode));
<>	144:ef7eb2e8f9f7	377
<>	144:ef7eb2e8f9f7	378	if(hi2c->State == HAL_I2C_STATE_RESET)
<>	144:ef7eb2e8f9f7	379	{
<>	144:ef7eb2e8f9f7	380	/* Allocate lock resource and initialize it */
<>	144:ef7eb2e8f9f7	381	hi2c->Lock = HAL_UNLOCKED;
<>	144:ef7eb2e8f9f7	382	/* Init the low level hardware : GPIO, CLOCK, NVIC */
<>	144:ef7eb2e8f9f7	383	HAL_I2C_MspInit(hi2c);
<>	144:ef7eb2e8f9f7	384	}
<>	144:ef7eb2e8f9f7	385
<>	144:ef7eb2e8f9f7	386	hi2c->State = HAL_I2C_STATE_BUSY;
<>	144:ef7eb2e8f9f7	387
<>	144:ef7eb2e8f9f7	388	/* Disable the selected I2C peripheral */
<>	144:ef7eb2e8f9f7	389	__HAL_I2C_DISABLE(hi2c);
<>	144:ef7eb2e8f9f7	390
<>	144:ef7eb2e8f9f7	391	/* Get PCLK1 frequency */
<>	144:ef7eb2e8f9f7	392	pclk1 = HAL_RCC_GetPCLK1Freq();
<>	144:ef7eb2e8f9f7	393
<>	144:ef7eb2e8f9f7	394	/* Calculate frequency range */
<>	144:ef7eb2e8f9f7	395	freqrange = I2C_FREQRANGE(pclk1);
<>	144:ef7eb2e8f9f7	396
<>	144:ef7eb2e8f9f7	397	/---------------------------- I2Cx CR2 Configuration ----------------------/
<>	144:ef7eb2e8f9f7	398	/* Configure I2Cx: Frequency range */
<>	144:ef7eb2e8f9f7	399	hi2c->Instance->CR2 = freqrange;
<>	144:ef7eb2e8f9f7	400
<>	144:ef7eb2e8f9f7	401	/---------------------------- I2Cx TRISE Configuration --------------------/
<>	144:ef7eb2e8f9f7	402	/* Configure I2Cx: Rise Time */
<>	144:ef7eb2e8f9f7	403	hi2c->Instance->TRISE = I2C_RISE_TIME(freqrange, hi2c->Init.ClockSpeed);
<>	144:ef7eb2e8f9f7	404
<>	144:ef7eb2e8f9f7	405	/---------------------------- I2Cx CCR Configuration ----------------------/
<>	144:ef7eb2e8f9f7	406	/* Configure I2Cx: Speed */
<>	144:ef7eb2e8f9f7	407	hi2c->Instance->CCR = I2C_SPEED(pclk1, hi2c->Init.ClockSpeed, hi2c->Init.DutyCycle);
<>	144:ef7eb2e8f9f7	408
<>	144:ef7eb2e8f9f7	409	/---------------------------- I2Cx CR1 Configuration ----------------------/
<>	144:ef7eb2e8f9f7	410	/* Configure I2Cx: Generalcall and NoStretch mode */
<>	144:ef7eb2e8f9f7	411	hi2c->Instance->CR1 = (hi2c->Init.GeneralCallMode \| hi2c->Init.NoStretchMode);
<>	144:ef7eb2e8f9f7	412
<>	144:ef7eb2e8f9f7	413	/---------------------------- I2Cx OAR1 Configuration ---------------------/
<>	144:ef7eb2e8f9f7	414	/* Configure I2Cx: Own Address1 and addressing mode */
<>	144:ef7eb2e8f9f7	415	hi2c->Instance->OAR1 = (hi2c->Init.AddressingMode \| hi2c->Init.OwnAddress1);
<>	144:ef7eb2e8f9f7	416
<>	144:ef7eb2e8f9f7	417	/---------------------------- I2Cx OAR2 Configuration ---------------------/
<>	144:ef7eb2e8f9f7	418	/* Configure I2Cx: Dual mode and Own Address2 */
<>	144:ef7eb2e8f9f7	419	hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode \| hi2c->Init.OwnAddress2);
<>	144:ef7eb2e8f9f7	420
<>	144:ef7eb2e8f9f7	421	/* Enable the selected I2C peripheral */
<>	144:ef7eb2e8f9f7	422	__HAL_I2C_ENABLE(hi2c);
<>	144:ef7eb2e8f9f7	423
<>	144:ef7eb2e8f9f7	424	hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
<>	144:ef7eb2e8f9f7	425	hi2c->State = HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	426	hi2c->PreviousState = I2C_STATE_NONE;
<>	144:ef7eb2e8f9f7	427	hi2c->Mode = HAL_I2C_MODE_NONE;
<>	144:ef7eb2e8f9f7	428
<>	144:ef7eb2e8f9f7	429	return HAL_OK;
<>	144:ef7eb2e8f9f7	430	}
<>	144:ef7eb2e8f9f7	431
<>	144:ef7eb2e8f9f7	432	/**
<>	144:ef7eb2e8f9f7	433	* @brief DeInitializes the I2C peripheral.
AnnaBridge	167:e84263d55307	434	* @param hi2c: pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	435	* the configuration information for I2C module
<>	144:ef7eb2e8f9f7	436	* @retval HAL status
<>	144:ef7eb2e8f9f7	437	*/
<>	144:ef7eb2e8f9f7	438	HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c)
<>	144:ef7eb2e8f9f7	439	{
<>	144:ef7eb2e8f9f7	440	/* Check the I2C handle allocation */
<>	144:ef7eb2e8f9f7	441	if(hi2c == NULL)
<>	144:ef7eb2e8f9f7	442	{
<>	144:ef7eb2e8f9f7	443	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	444	}
<>	144:ef7eb2e8f9f7	445
<>	144:ef7eb2e8f9f7	446	/* Check the parameters */
<>	144:ef7eb2e8f9f7	447	assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
<>	144:ef7eb2e8f9f7	448
<>	144:ef7eb2e8f9f7	449	hi2c->State = HAL_I2C_STATE_BUSY;
<>	144:ef7eb2e8f9f7	450
<>	144:ef7eb2e8f9f7	451	/* Disable the I2C Peripheral Clock */
<>	144:ef7eb2e8f9f7	452	__HAL_I2C_DISABLE(hi2c);
<>	144:ef7eb2e8f9f7	453
<>	144:ef7eb2e8f9f7	454	/* DeInit the low level hardware: GPIO, CLOCK, NVIC */
<>	144:ef7eb2e8f9f7	455	HAL_I2C_MspDeInit(hi2c);
<>	144:ef7eb2e8f9f7	456
AnnaBridge	167:e84263d55307	457	hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
AnnaBridge	167:e84263d55307	458	hi2c->State = HAL_I2C_STATE_RESET;
<>	144:ef7eb2e8f9f7	459	hi2c->PreviousState = I2C_STATE_NONE;
AnnaBridge	167:e84263d55307	460	hi2c->Mode = HAL_I2C_MODE_NONE;
AnnaBridge	167:e84263d55307	461
<>	144:ef7eb2e8f9f7	462	/* Release Lock */
<>	144:ef7eb2e8f9f7	463	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	464
<>	144:ef7eb2e8f9f7	465	return HAL_OK;
<>	144:ef7eb2e8f9f7	466	}
<>	144:ef7eb2e8f9f7	467
<>	144:ef7eb2e8f9f7	468	/**
<>	144:ef7eb2e8f9f7	469	* @brief I2C MSP Init.
AnnaBridge	167:e84263d55307	470	* @param hi2c: pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	471	* the configuration information for I2C module
<>	144:ef7eb2e8f9f7	472	* @retval None
<>	144:ef7eb2e8f9f7	473	*/
<>	144:ef7eb2e8f9f7	474	__weak void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c)
<>	144:ef7eb2e8f9f7	475	{
<>	144:ef7eb2e8f9f7	476	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	477	UNUSED(hi2c);
<>	144:ef7eb2e8f9f7	478	/* NOTE : This function Should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	479	the HAL_I2C_MspInit could be implemented in the user file
<>	144:ef7eb2e8f9f7	480	*/
<>	144:ef7eb2e8f9f7	481	}
<>	144:ef7eb2e8f9f7	482
<>	144:ef7eb2e8f9f7	483	/**
<>	144:ef7eb2e8f9f7	484	* @brief I2C MSP DeInit
AnnaBridge	167:e84263d55307	485	* @param hi2c: pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	486	* the configuration information for I2C module
<>	144:ef7eb2e8f9f7	487	* @retval None
<>	144:ef7eb2e8f9f7	488	*/
<>	144:ef7eb2e8f9f7	489	__weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c)
<>	144:ef7eb2e8f9f7	490	{
<>	144:ef7eb2e8f9f7	491	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	492	UNUSED(hi2c);
<>	144:ef7eb2e8f9f7	493	/* NOTE : This function Should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	494	the HAL_I2C_MspDeInit could be implemented in the user file
<>	144:ef7eb2e8f9f7	495	*/
<>	144:ef7eb2e8f9f7	496	}
<>	144:ef7eb2e8f9f7	497
<>	144:ef7eb2e8f9f7	498	/**
<>	144:ef7eb2e8f9f7	499	* @}
<>	144:ef7eb2e8f9f7	500	*/
<>	144:ef7eb2e8f9f7	501
<>	144:ef7eb2e8f9f7	502	/** @defgroup I2C_Exported_Functions_Group2 IO operation functions
<>	144:ef7eb2e8f9f7	503	* @brief Data transfers functions
<>	144:ef7eb2e8f9f7	504	*
<>	144:ef7eb2e8f9f7	505	@verbatim
<>	144:ef7eb2e8f9f7	506	===============================================================================
<>	144:ef7eb2e8f9f7	507	##### IO operation functions #####
<>	144:ef7eb2e8f9f7	508	===============================================================================
<>	144:ef7eb2e8f9f7	509	[..]
<>	144:ef7eb2e8f9f7	510	This subsection provides a set of functions allowing to manage the I2C data
<>	144:ef7eb2e8f9f7	511	transfers.
<>	144:ef7eb2e8f9f7	512
<>	144:ef7eb2e8f9f7	513	(#) There are two modes of transfer:
<>	144:ef7eb2e8f9f7	514	(++) Blocking mode : The communication is performed in the polling mode.
<>	144:ef7eb2e8f9f7	515	The status of all data processing is returned by the same function
<>	144:ef7eb2e8f9f7	516	after finishing transfer.
<>	144:ef7eb2e8f9f7	517	(++) No-Blocking mode : The communication is performed using Interrupts
<>	144:ef7eb2e8f9f7	518	or DMA. These functions return the status of the transfer startup.
<>	144:ef7eb2e8f9f7	519	The end of the data processing will be indicated through the
<>	144:ef7eb2e8f9f7	520	dedicated I2C IRQ when using Interrupt mode or the DMA IRQ when
<>	144:ef7eb2e8f9f7	521	using DMA mode.
<>	144:ef7eb2e8f9f7	522
<>	144:ef7eb2e8f9f7	523	(#) Blocking mode functions are :
<>	144:ef7eb2e8f9f7	524	(++) HAL_I2C_Master_Transmit()
<>	144:ef7eb2e8f9f7	525	(++) HAL_I2C_Master_Receive()
<>	144:ef7eb2e8f9f7	526	(++) HAL_I2C_Slave_Transmit()
<>	144:ef7eb2e8f9f7	527	(++) HAL_I2C_Slave_Receive()
<>	144:ef7eb2e8f9f7	528	(++) HAL_I2C_Mem_Write()
<>	144:ef7eb2e8f9f7	529	(++) HAL_I2C_Mem_Read()
<>	144:ef7eb2e8f9f7	530	(++) HAL_I2C_IsDeviceReady()
<>	144:ef7eb2e8f9f7	531
<>	144:ef7eb2e8f9f7	532	(#) No-Blocking mode functions with Interrupt are :
<>	144:ef7eb2e8f9f7	533	(++) HAL_I2C_Master_Transmit_IT()
<>	144:ef7eb2e8f9f7	534	(++) HAL_I2C_Master_Receive_IT()
<>	144:ef7eb2e8f9f7	535	(++) HAL_I2C_Slave_Transmit_IT()
<>	144:ef7eb2e8f9f7	536	(++) HAL_I2C_Slave_Receive_IT()
<>	144:ef7eb2e8f9f7	537	(++) HAL_I2C_Master_Sequential_Transmit_IT()
<>	144:ef7eb2e8f9f7	538	(++) HAL_I2C_Master_Sequential_Receive_IT()
<>	144:ef7eb2e8f9f7	539	(++) HAL_I2C_Slave_Sequential_Transmit_IT()
<>	144:ef7eb2e8f9f7	540	(++) HAL_I2C_Slave_Sequential_Receive_IT()
<>	144:ef7eb2e8f9f7	541	(++) HAL_I2C_Mem_Write_IT()
<>	144:ef7eb2e8f9f7	542	(++) HAL_I2C_Mem_Read_IT()
<>	144:ef7eb2e8f9f7	543
<>	144:ef7eb2e8f9f7	544	(#) No-Blocking mode functions with DMA are :
<>	144:ef7eb2e8f9f7	545	(++) HAL_I2C_Master_Transmit_DMA()
<>	144:ef7eb2e8f9f7	546	(++) HAL_I2C_Master_Receive_DMA()
<>	144:ef7eb2e8f9f7	547	(++) HAL_I2C_Slave_Transmit_DMA()
<>	144:ef7eb2e8f9f7	548	(++) HAL_I2C_Slave_Receive_DMA()
<>	144:ef7eb2e8f9f7	549	(++) HAL_I2C_Mem_Write_DMA()
<>	144:ef7eb2e8f9f7	550	(++) HAL_I2C_Mem_Read_DMA()
<>	144:ef7eb2e8f9f7	551
<>	144:ef7eb2e8f9f7	552	(#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
<>	144:ef7eb2e8f9f7	553	(++) HAL_I2C_MemTxCpltCallback()
<>	144:ef7eb2e8f9f7	554	(++) HAL_I2C_MemRxCpltCallback()
<>	144:ef7eb2e8f9f7	555	(++) HAL_I2C_MasterTxCpltCallback()
<>	144:ef7eb2e8f9f7	556	(++) HAL_I2C_MasterRxCpltCallback()
<>	144:ef7eb2e8f9f7	557	(++) HAL_I2C_SlaveTxCpltCallback()
<>	144:ef7eb2e8f9f7	558	(++) HAL_I2C_SlaveRxCpltCallback()
<>	144:ef7eb2e8f9f7	559	(++) HAL_I2C_ErrorCallback()
<>	144:ef7eb2e8f9f7	560	(++) HAL_I2C_AbortCpltCallback()
<>	144:ef7eb2e8f9f7	561
<>	144:ef7eb2e8f9f7	562	@endverbatim
<>	144:ef7eb2e8f9f7	563	* @{
<>	144:ef7eb2e8f9f7	564	*/
<>	144:ef7eb2e8f9f7	565
<>	144:ef7eb2e8f9f7	566	/**
<>	144:ef7eb2e8f9f7	567	* @brief Transmits in master mode an amount of data in blocking mode.
<>	144:ef7eb2e8f9f7	568	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
AnnaBridge	167:e84263d55307	569	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	570	* @param DevAddress Target device address: The device 7 bits address value
<>	144:ef7eb2e8f9f7	571	* in datasheet must be shift at right before call interface
<>	144:ef7eb2e8f9f7	572	* @param pData Pointer to data buffer
<>	144:ef7eb2e8f9f7	573	* @param Size Amount of data to be sent
<>	144:ef7eb2e8f9f7	574	* @param Timeout Timeout duration
<>	144:ef7eb2e8f9f7	575	* @retval HAL status
<>	144:ef7eb2e8f9f7	576	*/
<>	144:ef7eb2e8f9f7	577	HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef hi2c, uint16_t DevAddress, uint8_t pData, uint16_t Size, uint32_t Timeout)
<>	144:ef7eb2e8f9f7	578	{
<>	144:ef7eb2e8f9f7	579	uint32_t tickstart = 0x00U;
<>	144:ef7eb2e8f9f7	580
<>	144:ef7eb2e8f9f7	581	/* Init tickstart for timeout management*/
<>	144:ef7eb2e8f9f7	582	tickstart = HAL_GetTick();
AnnaBridge	167:e84263d55307	583
<>	144:ef7eb2e8f9f7	584	if(hi2c->State == HAL_I2C_STATE_READY)
<>	144:ef7eb2e8f9f7	585	{
<>	144:ef7eb2e8f9f7	586	/* Wait until BUSY flag is reset */
<>	144:ef7eb2e8f9f7	587	if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	588	{
<>	144:ef7eb2e8f9f7	589	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	590	}
<>	144:ef7eb2e8f9f7	591
<>	144:ef7eb2e8f9f7	592	/* Process Locked */
<>	144:ef7eb2e8f9f7	593	__HAL_LOCK(hi2c);
AnnaBridge	167:e84263d55307	594
AnnaBridge	167:e84263d55307	595	/* Check if the I2C is already enabled */
AnnaBridge	167:e84263d55307	596	if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
AnnaBridge	167:e84263d55307	597	{
AnnaBridge	167:e84263d55307	598	/* Enable I2C peripheral */
AnnaBridge	167:e84263d55307	599	__HAL_I2C_ENABLE(hi2c);
AnnaBridge	167:e84263d55307	600	}
AnnaBridge	167:e84263d55307	601
<>	144:ef7eb2e8f9f7	602	/* Disable Pos */
<>	144:ef7eb2e8f9f7	603	hi2c->Instance->CR1 &= ~I2C_CR1_POS;
AnnaBridge	167:e84263d55307	604
AnnaBridge	167:e84263d55307	605	hi2c->State = HAL_I2C_STATE_BUSY_TX;
AnnaBridge	167:e84263d55307	606	hi2c->Mode = HAL_I2C_MODE_MASTER;
<>	144:ef7eb2e8f9f7	607	hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
AnnaBridge	167:e84263d55307	608
AnnaBridge	167:e84263d55307	609	/* Prepare transfer parameters */
AnnaBridge	167:e84263d55307	610	hi2c->pBuffPtr = pData;
AnnaBridge	167:e84263d55307	611	hi2c->XferCount = Size;
<>	144:ef7eb2e8f9f7	612	hi2c->XferOptions = I2C_NO_OPTION_FRAME;
AnnaBridge	167:e84263d55307	613	hi2c->XferSize = hi2c->XferCount;
AnnaBridge	167:e84263d55307	614
<>	144:ef7eb2e8f9f7	615	/* Send Slave Address */
<>	144:ef7eb2e8f9f7	616	if(I2C_MasterRequestWrite(hi2c, DevAddress, Timeout, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	617	{
<>	144:ef7eb2e8f9f7	618	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
<>	144:ef7eb2e8f9f7	619	{
<>	144:ef7eb2e8f9f7	620	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	621	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	622	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	623	}
<>	144:ef7eb2e8f9f7	624	else
<>	144:ef7eb2e8f9f7	625	{
<>	144:ef7eb2e8f9f7	626	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	627	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	628	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	629	}
<>	144:ef7eb2e8f9f7	630	}
<>	144:ef7eb2e8f9f7	631
<>	144:ef7eb2e8f9f7	632	/* Clear ADDR flag */
<>	144:ef7eb2e8f9f7	633	__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
<>	144:ef7eb2e8f9f7	634
AnnaBridge	167:e84263d55307	635	while(hi2c->XferSize > 0U)
<>	144:ef7eb2e8f9f7	636	{
<>	144:ef7eb2e8f9f7	637	/* Wait until TXE flag is set */
<>	144:ef7eb2e8f9f7	638	if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	639	{
<>	144:ef7eb2e8f9f7	640	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
<>	144:ef7eb2e8f9f7	641	{
<>	144:ef7eb2e8f9f7	642	/* Generate Stop */
<>	144:ef7eb2e8f9f7	643	hi2c->Instance->CR1 \|= I2C_CR1_STOP;
<>	144:ef7eb2e8f9f7	644	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	645	}
<>	144:ef7eb2e8f9f7	646	else
<>	144:ef7eb2e8f9f7	647	{
<>	144:ef7eb2e8f9f7	648	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	649	}
<>	144:ef7eb2e8f9f7	650	}
<>	144:ef7eb2e8f9f7	651
<>	144:ef7eb2e8f9f7	652	/* Write data to DR */
AnnaBridge	167:e84263d55307	653	hi2c->Instance->DR = (*hi2c->pBuffPtr++);
AnnaBridge	167:e84263d55307	654	hi2c->XferCount--;
AnnaBridge	167:e84263d55307	655	hi2c->XferSize--;
AnnaBridge	167:e84263d55307	656
AnnaBridge	167:e84263d55307	657	if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (hi2c->XferSize != 0U))
<>	144:ef7eb2e8f9f7	658	{
<>	144:ef7eb2e8f9f7	659	/* Write data to DR */
AnnaBridge	167:e84263d55307	660	hi2c->Instance->DR = (*hi2c->pBuffPtr++);
AnnaBridge	167:e84263d55307	661	hi2c->XferCount--;
AnnaBridge	167:e84263d55307	662	hi2c->XferSize--;
<>	144:ef7eb2e8f9f7	663	}
<>	144:ef7eb2e8f9f7	664
<>	144:ef7eb2e8f9f7	665	/* Wait until BTF flag is set */
<>	144:ef7eb2e8f9f7	666	if(I2C_WaitOnBTFFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	667	{
<>	144:ef7eb2e8f9f7	668	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
<>	144:ef7eb2e8f9f7	669	{
<>	144:ef7eb2e8f9f7	670	/* Generate Stop */
<>	144:ef7eb2e8f9f7	671	hi2c->Instance->CR1 \|= I2C_CR1_STOP;
<>	144:ef7eb2e8f9f7	672	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	673	}
<>	144:ef7eb2e8f9f7	674	else
<>	144:ef7eb2e8f9f7	675	{
<>	144:ef7eb2e8f9f7	676	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	677	}
<>	144:ef7eb2e8f9f7	678	}
<>	144:ef7eb2e8f9f7	679	}
<>	144:ef7eb2e8f9f7	680
<>	144:ef7eb2e8f9f7	681	/* Generate Stop */
<>	144:ef7eb2e8f9f7	682	hi2c->Instance->CR1 \|= I2C_CR1_STOP;
<>	144:ef7eb2e8f9f7	683
<>	144:ef7eb2e8f9f7	684	hi2c->State = HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	685	hi2c->Mode = HAL_I2C_MODE_NONE;
<>	144:ef7eb2e8f9f7	686
<>	144:ef7eb2e8f9f7	687	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	688	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	689
<>	144:ef7eb2e8f9f7	690	return HAL_OK;
<>	144:ef7eb2e8f9f7	691	}
<>	144:ef7eb2e8f9f7	692	else
<>	144:ef7eb2e8f9f7	693	{
<>	144:ef7eb2e8f9f7	694	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	695	}
<>	144:ef7eb2e8f9f7	696	}
<>	144:ef7eb2e8f9f7	697
<>	144:ef7eb2e8f9f7	698	/**
AnnaBridge	167:e84263d55307	699	* @brief Receives in master mode an amount of data in blocking mode.
<>	144:ef7eb2e8f9f7	700	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
AnnaBridge	167:e84263d55307	701	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	702	* @param DevAddress Target device address: The device 7 bits address value
<>	144:ef7eb2e8f9f7	703	* in datasheet must be shift at right before call interface
<>	144:ef7eb2e8f9f7	704	* @param pData Pointer to data buffer
<>	144:ef7eb2e8f9f7	705	* @param Size Amount of data to be sent
<>	144:ef7eb2e8f9f7	706	* @param Timeout Timeout duration
<>	144:ef7eb2e8f9f7	707	* @retval HAL status
<>	144:ef7eb2e8f9f7	708	*/
<>	144:ef7eb2e8f9f7	709	HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef hi2c, uint16_t DevAddress, uint8_t pData, uint16_t Size, uint32_t Timeout)
<>	144:ef7eb2e8f9f7	710	{
<>	144:ef7eb2e8f9f7	711	uint32_t tickstart = 0x00U;
<>	144:ef7eb2e8f9f7	712
<>	144:ef7eb2e8f9f7	713	/* Init tickstart for timeout management*/
<>	144:ef7eb2e8f9f7	714	tickstart = HAL_GetTick();
AnnaBridge	167:e84263d55307	715
<>	144:ef7eb2e8f9f7	716	if(hi2c->State == HAL_I2C_STATE_READY)
<>	144:ef7eb2e8f9f7	717	{
<>	144:ef7eb2e8f9f7	718	/* Wait until BUSY flag is reset */
<>	144:ef7eb2e8f9f7	719	if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	720	{
<>	144:ef7eb2e8f9f7	721	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	722	}
AnnaBridge	167:e84263d55307	723
<>	144:ef7eb2e8f9f7	724	/* Process Locked */
<>	144:ef7eb2e8f9f7	725	__HAL_LOCK(hi2c);
AnnaBridge	167:e84263d55307	726
AnnaBridge	167:e84263d55307	727	/* Check if the I2C is already enabled */
AnnaBridge	167:e84263d55307	728	if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
AnnaBridge	167:e84263d55307	729	{
AnnaBridge	167:e84263d55307	730	/* Enable I2C peripheral */
AnnaBridge	167:e84263d55307	731	__HAL_I2C_ENABLE(hi2c);
AnnaBridge	167:e84263d55307	732	}
AnnaBridge	167:e84263d55307	733
<>	144:ef7eb2e8f9f7	734	/* Disable Pos */
<>	144:ef7eb2e8f9f7	735	hi2c->Instance->CR1 &= ~I2C_CR1_POS;
<>	144:ef7eb2e8f9f7	736
AnnaBridge	167:e84263d55307	737	hi2c->State = HAL_I2C_STATE_BUSY_RX;
AnnaBridge	167:e84263d55307	738	hi2c->Mode = HAL_I2C_MODE_MASTER;
AnnaBridge	167:e84263d55307	739	hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
AnnaBridge	167:e84263d55307	740
AnnaBridge	167:e84263d55307	741	/* Prepare transfer parameters */
AnnaBridge	167:e84263d55307	742	hi2c->pBuffPtr = pData;
AnnaBridge	167:e84263d55307	743	hi2c->XferCount = Size;
<>	144:ef7eb2e8f9f7	744	hi2c->XferOptions = I2C_NO_OPTION_FRAME;
AnnaBridge	167:e84263d55307	745	hi2c->XferSize = hi2c->XferCount;
AnnaBridge	167:e84263d55307	746
<>	144:ef7eb2e8f9f7	747	/* Send Slave Address */
<>	144:ef7eb2e8f9f7	748	if(I2C_MasterRequestRead(hi2c, DevAddress, Timeout, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	749	{
<>	144:ef7eb2e8f9f7	750	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
<>	144:ef7eb2e8f9f7	751	{
<>	144:ef7eb2e8f9f7	752	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	753	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	754	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	755	}
<>	144:ef7eb2e8f9f7	756	else
<>	144:ef7eb2e8f9f7	757	{
<>	144:ef7eb2e8f9f7	758	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	759	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	760	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	761	}
<>	144:ef7eb2e8f9f7	762	}
<>	144:ef7eb2e8f9f7	763
AnnaBridge	167:e84263d55307	764	if(hi2c->XferSize == 0U)
<>	144:ef7eb2e8f9f7	765	{
<>	144:ef7eb2e8f9f7	766	/* Clear ADDR flag */
<>	144:ef7eb2e8f9f7	767	__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
AnnaBridge	167:e84263d55307	768
<>	144:ef7eb2e8f9f7	769	/* Generate Stop */
<>	144:ef7eb2e8f9f7	770	hi2c->Instance->CR1 \|= I2C_CR1_STOP;
<>	144:ef7eb2e8f9f7	771	}
AnnaBridge	167:e84263d55307	772	else if(hi2c->XferSize == 1U)
<>	144:ef7eb2e8f9f7	773	{
<>	144:ef7eb2e8f9f7	774	/* Disable Acknowledge */
<>	144:ef7eb2e8f9f7	775	hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
<>	144:ef7eb2e8f9f7	776
<>	144:ef7eb2e8f9f7	777	/* Clear ADDR flag */
<>	144:ef7eb2e8f9f7	778	__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
<>	144:ef7eb2e8f9f7	779
<>	144:ef7eb2e8f9f7	780	/* Generate Stop */
<>	144:ef7eb2e8f9f7	781	hi2c->Instance->CR1 \|= I2C_CR1_STOP;
<>	144:ef7eb2e8f9f7	782	}
AnnaBridge	167:e84263d55307	783	else if(hi2c->XferSize == 2U)
<>	144:ef7eb2e8f9f7	784	{
<>	144:ef7eb2e8f9f7	785	/* Disable Acknowledge */
<>	144:ef7eb2e8f9f7	786	hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
<>	144:ef7eb2e8f9f7	787
<>	144:ef7eb2e8f9f7	788	/* Enable Pos */
<>	144:ef7eb2e8f9f7	789	hi2c->Instance->CR1 \|= I2C_CR1_POS;
<>	144:ef7eb2e8f9f7	790
<>	144:ef7eb2e8f9f7	791	/* Clear ADDR flag */
<>	144:ef7eb2e8f9f7	792	__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
<>	144:ef7eb2e8f9f7	793	}
<>	144:ef7eb2e8f9f7	794	else
<>	144:ef7eb2e8f9f7	795	{
<>	144:ef7eb2e8f9f7	796	/* Enable Acknowledge */
<>	144:ef7eb2e8f9f7	797	hi2c->Instance->CR1 \|= I2C_CR1_ACK;
<>	144:ef7eb2e8f9f7	798
<>	144:ef7eb2e8f9f7	799	/* Clear ADDR flag */
<>	144:ef7eb2e8f9f7	800	__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
<>	144:ef7eb2e8f9f7	801	}
<>	144:ef7eb2e8f9f7	802
AnnaBridge	167:e84263d55307	803	while(hi2c->XferSize > 0U)
<>	144:ef7eb2e8f9f7	804	{
AnnaBridge	167:e84263d55307	805	if(hi2c->XferSize <= 3U)
<>	144:ef7eb2e8f9f7	806	{
<>	144:ef7eb2e8f9f7	807	/* One byte */
AnnaBridge	167:e84263d55307	808	if(hi2c->XferSize == 1U)
<>	144:ef7eb2e8f9f7	809	{
<>	144:ef7eb2e8f9f7	810	/* Wait until RXNE flag is set */
<>	144:ef7eb2e8f9f7	811	if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	812	{
<>	144:ef7eb2e8f9f7	813	if(hi2c->ErrorCode == HAL_I2C_ERROR_TIMEOUT)
<>	144:ef7eb2e8f9f7	814	{
<>	144:ef7eb2e8f9f7	815	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	816	}
<>	144:ef7eb2e8f9f7	817	else
<>	144:ef7eb2e8f9f7	818	{
<>	144:ef7eb2e8f9f7	819	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	820	}
<>	144:ef7eb2e8f9f7	821	}
<>	144:ef7eb2e8f9f7	822
<>	144:ef7eb2e8f9f7	823	/* Read data from DR */
AnnaBridge	167:e84263d55307	824	(*hi2c->pBuffPtr++) = hi2c->Instance->DR;
AnnaBridge	167:e84263d55307	825	hi2c->XferSize--;
AnnaBridge	167:e84263d55307	826	hi2c->XferCount--;
<>	144:ef7eb2e8f9f7	827	}
<>	144:ef7eb2e8f9f7	828	/* Two bytes */
AnnaBridge	167:e84263d55307	829	else if(hi2c->XferSize == 2U)
<>	144:ef7eb2e8f9f7	830	{
<>	144:ef7eb2e8f9f7	831	/* Wait until BTF flag is set */
<>	144:ef7eb2e8f9f7	832	if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	833	{
<>	144:ef7eb2e8f9f7	834	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	835	}
<>	144:ef7eb2e8f9f7	836
<>	144:ef7eb2e8f9f7	837	/* Generate Stop */
<>	144:ef7eb2e8f9f7	838	hi2c->Instance->CR1 \|= I2C_CR1_STOP;
<>	144:ef7eb2e8f9f7	839
<>	144:ef7eb2e8f9f7	840	/* Read data from DR */
AnnaBridge	167:e84263d55307	841	(*hi2c->pBuffPtr++) = hi2c->Instance->DR;
AnnaBridge	167:e84263d55307	842	hi2c->XferSize--;
AnnaBridge	167:e84263d55307	843	hi2c->XferCount--;
<>	144:ef7eb2e8f9f7	844
<>	144:ef7eb2e8f9f7	845	/* Read data from DR */
AnnaBridge	167:e84263d55307	846	(*hi2c->pBuffPtr++) = hi2c->Instance->DR;
AnnaBridge	167:e84263d55307	847	hi2c->XferSize--;
AnnaBridge	167:e84263d55307	848	hi2c->XferCount--;
<>	144:ef7eb2e8f9f7	849	}
<>	144:ef7eb2e8f9f7	850	/* 3 Last bytes */
<>	144:ef7eb2e8f9f7	851	else
<>	144:ef7eb2e8f9f7	852	{
<>	144:ef7eb2e8f9f7	853	/* Wait until BTF flag is set */
<>	144:ef7eb2e8f9f7	854	if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	855	{
<>	144:ef7eb2e8f9f7	856	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	857	}
<>	144:ef7eb2e8f9f7	858
<>	144:ef7eb2e8f9f7	859	/* Disable Acknowledge */
<>	144:ef7eb2e8f9f7	860	hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
<>	144:ef7eb2e8f9f7	861
<>	144:ef7eb2e8f9f7	862	/* Read data from DR */
AnnaBridge	167:e84263d55307	863	(*hi2c->pBuffPtr++) = hi2c->Instance->DR;
AnnaBridge	167:e84263d55307	864	hi2c->XferSize--;
AnnaBridge	167:e84263d55307	865	hi2c->XferCount--;
<>	144:ef7eb2e8f9f7	866
<>	144:ef7eb2e8f9f7	867	/* Wait until BTF flag is set */
<>	144:ef7eb2e8f9f7	868	if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	869	{
<>	144:ef7eb2e8f9f7	870	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	871	}
<>	144:ef7eb2e8f9f7	872
<>	144:ef7eb2e8f9f7	873	/* Generate Stop */
<>	144:ef7eb2e8f9f7	874	hi2c->Instance->CR1 \|= I2C_CR1_STOP;
<>	144:ef7eb2e8f9f7	875
<>	144:ef7eb2e8f9f7	876	/* Read data from DR */
AnnaBridge	167:e84263d55307	877	(*hi2c->pBuffPtr++) = hi2c->Instance->DR;
AnnaBridge	167:e84263d55307	878	hi2c->XferSize--;
AnnaBridge	167:e84263d55307	879	hi2c->XferCount--;
<>	144:ef7eb2e8f9f7	880
<>	144:ef7eb2e8f9f7	881	/* Read data from DR */
AnnaBridge	167:e84263d55307	882	(*hi2c->pBuffPtr++) = hi2c->Instance->DR;
AnnaBridge	167:e84263d55307	883	hi2c->XferSize--;
AnnaBridge	167:e84263d55307	884	hi2c->XferCount--;
<>	144:ef7eb2e8f9f7	885	}
<>	144:ef7eb2e8f9f7	886	}
<>	144:ef7eb2e8f9f7	887	else
<>	144:ef7eb2e8f9f7	888	{
<>	144:ef7eb2e8f9f7	889	/* Wait until RXNE flag is set */
<>	144:ef7eb2e8f9f7	890	if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	891	{
<>	144:ef7eb2e8f9f7	892	if(hi2c->ErrorCode == HAL_I2C_ERROR_TIMEOUT)
<>	144:ef7eb2e8f9f7	893	{
<>	144:ef7eb2e8f9f7	894	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	895	}
<>	144:ef7eb2e8f9f7	896	else
<>	144:ef7eb2e8f9f7	897	{
<>	144:ef7eb2e8f9f7	898	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	899	}
<>	144:ef7eb2e8f9f7	900	}
<>	144:ef7eb2e8f9f7	901
<>	144:ef7eb2e8f9f7	902	/* Read data from DR */
AnnaBridge	167:e84263d55307	903	(*hi2c->pBuffPtr++) = hi2c->Instance->DR;
AnnaBridge	167:e84263d55307	904	hi2c->XferSize--;
AnnaBridge	167:e84263d55307	905	hi2c->XferCount--;
<>	144:ef7eb2e8f9f7	906
<>	144:ef7eb2e8f9f7	907	if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET)
<>	144:ef7eb2e8f9f7	908	{
<>	144:ef7eb2e8f9f7	909	/* Read data from DR */
AnnaBridge	167:e84263d55307	910	(*hi2c->pBuffPtr++) = hi2c->Instance->DR;
AnnaBridge	167:e84263d55307	911	hi2c->XferSize--;
AnnaBridge	167:e84263d55307	912	hi2c->XferCount--;
<>	144:ef7eb2e8f9f7	913	}
<>	144:ef7eb2e8f9f7	914	}
<>	144:ef7eb2e8f9f7	915	}
<>	144:ef7eb2e8f9f7	916
<>	144:ef7eb2e8f9f7	917	hi2c->State = HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	918	hi2c->Mode = HAL_I2C_MODE_NONE;
<>	144:ef7eb2e8f9f7	919
<>	144:ef7eb2e8f9f7	920	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	921	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	922
<>	144:ef7eb2e8f9f7	923	return HAL_OK;
<>	144:ef7eb2e8f9f7	924	}
<>	144:ef7eb2e8f9f7	925	else
<>	144:ef7eb2e8f9f7	926	{
<>	144:ef7eb2e8f9f7	927	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	928	}
<>	144:ef7eb2e8f9f7	929	}
<>	144:ef7eb2e8f9f7	930
<>	144:ef7eb2e8f9f7	931	/**
AnnaBridge	167:e84263d55307	932	* @brief Transmits in slave mode an amount of data in blocking mode.
<>	144:ef7eb2e8f9f7	933	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
AnnaBridge	167:e84263d55307	934	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	935	* @param pData Pointer to data buffer
<>	144:ef7eb2e8f9f7	936	* @param Size Amount of data to be sent
<>	144:ef7eb2e8f9f7	937	* @param Timeout Timeout duration
<>	144:ef7eb2e8f9f7	938	* @retval HAL status
<>	144:ef7eb2e8f9f7	939	*/
<>	144:ef7eb2e8f9f7	940	HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef hi2c, uint8_t pData, uint16_t Size, uint32_t Timeout)
<>	144:ef7eb2e8f9f7	941	{
<>	144:ef7eb2e8f9f7	942	uint32_t tickstart = 0x00U;
<>	144:ef7eb2e8f9f7	943
<>	144:ef7eb2e8f9f7	944	/* Init tickstart for timeout management*/
<>	144:ef7eb2e8f9f7	945	tickstart = HAL_GetTick();
<>	144:ef7eb2e8f9f7	946
<>	144:ef7eb2e8f9f7	947	if(hi2c->State == HAL_I2C_STATE_READY)
<>	144:ef7eb2e8f9f7	948	{
<>	144:ef7eb2e8f9f7	949	if((pData == NULL) \|\| (Size == 0U))
<>	144:ef7eb2e8f9f7	950	{
<>	144:ef7eb2e8f9f7	951	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	952	}
<>	144:ef7eb2e8f9f7	953
<>	144:ef7eb2e8f9f7	954	/* Process Locked */
<>	144:ef7eb2e8f9f7	955	__HAL_LOCK(hi2c);
<>	144:ef7eb2e8f9f7	956
AnnaBridge	167:e84263d55307	957	/* Check if the I2C is already enabled */
AnnaBridge	167:e84263d55307	958	if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
AnnaBridge	167:e84263d55307	959	{
AnnaBridge	167:e84263d55307	960	/* Enable I2C peripheral */
AnnaBridge	167:e84263d55307	961	__HAL_I2C_ENABLE(hi2c);
AnnaBridge	167:e84263d55307	962	}
AnnaBridge	167:e84263d55307	963
<>	144:ef7eb2e8f9f7	964	/* Disable Pos */
<>	144:ef7eb2e8f9f7	965	hi2c->Instance->CR1 &= ~I2C_CR1_POS;
<>	144:ef7eb2e8f9f7	966
AnnaBridge	167:e84263d55307	967	hi2c->State = HAL_I2C_STATE_BUSY_TX;
AnnaBridge	167:e84263d55307	968	hi2c->Mode = HAL_I2C_MODE_SLAVE;
AnnaBridge	167:e84263d55307	969	hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
AnnaBridge	167:e84263d55307	970
AnnaBridge	167:e84263d55307	971	/* Prepare transfer parameters */
AnnaBridge	167:e84263d55307	972	hi2c->pBuffPtr = pData;
AnnaBridge	167:e84263d55307	973	hi2c->XferCount = Size;
<>	144:ef7eb2e8f9f7	974	hi2c->XferOptions = I2C_NO_OPTION_FRAME;
AnnaBridge	167:e84263d55307	975	hi2c->XferSize = hi2c->XferCount;
AnnaBridge	167:e84263d55307	976
<>	144:ef7eb2e8f9f7	977	/* Enable Address Acknowledge */
<>	144:ef7eb2e8f9f7	978	hi2c->Instance->CR1 \|= I2C_CR1_ACK;
<>	144:ef7eb2e8f9f7	979
<>	144:ef7eb2e8f9f7	980	/* Wait until ADDR flag is set */
<>	144:ef7eb2e8f9f7	981	if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	982	{
<>	144:ef7eb2e8f9f7	983	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	984	}
<>	144:ef7eb2e8f9f7	985
<>	144:ef7eb2e8f9f7	986	/* Clear ADDR flag */
<>	144:ef7eb2e8f9f7	987	__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
<>	144:ef7eb2e8f9f7	988
<>	144:ef7eb2e8f9f7	989	/* If 10bit addressing mode is selected */
<>	144:ef7eb2e8f9f7	990	if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
<>	144:ef7eb2e8f9f7	991	{
<>	144:ef7eb2e8f9f7	992	/* Wait until ADDR flag is set */
<>	144:ef7eb2e8f9f7	993	if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	994	{
<>	144:ef7eb2e8f9f7	995	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	996	}
<>	144:ef7eb2e8f9f7	997
<>	144:ef7eb2e8f9f7	998	/* Clear ADDR flag */
<>	144:ef7eb2e8f9f7	999	__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
<>	144:ef7eb2e8f9f7	1000	}
<>	144:ef7eb2e8f9f7	1001
AnnaBridge	167:e84263d55307	1002	while(hi2c->XferSize > 0U)
<>	144:ef7eb2e8f9f7	1003	{
<>	144:ef7eb2e8f9f7	1004	/* Wait until TXE flag is set */
<>	144:ef7eb2e8f9f7	1005	if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	1006	{
<>	144:ef7eb2e8f9f7	1007	/* Disable Address Acknowledge */
<>	144:ef7eb2e8f9f7	1008	hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
AnnaBridge	167:e84263d55307	1009
<>	144:ef7eb2e8f9f7	1010	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
<>	144:ef7eb2e8f9f7	1011	{
<>	144:ef7eb2e8f9f7	1012	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	1013	}
<>	144:ef7eb2e8f9f7	1014	else
<>	144:ef7eb2e8f9f7	1015	{
<>	144:ef7eb2e8f9f7	1016	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	1017	}
<>	144:ef7eb2e8f9f7	1018	}
<>	144:ef7eb2e8f9f7	1019
<>	144:ef7eb2e8f9f7	1020	/* Write data to DR */
AnnaBridge	167:e84263d55307	1021	hi2c->Instance->DR = (*hi2c->pBuffPtr++);
AnnaBridge	167:e84263d55307	1022	hi2c->XferCount--;
AnnaBridge	167:e84263d55307	1023	hi2c->XferSize--;
AnnaBridge	167:e84263d55307	1024
AnnaBridge	167:e84263d55307	1025	if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (hi2c->XferSize != 0U))
<>	144:ef7eb2e8f9f7	1026	{
<>	144:ef7eb2e8f9f7	1027	/* Write data to DR */
AnnaBridge	167:e84263d55307	1028	hi2c->Instance->DR = (*hi2c->pBuffPtr++);
AnnaBridge	167:e84263d55307	1029	hi2c->XferCount--;
AnnaBridge	167:e84263d55307	1030	hi2c->XferSize--;
<>	144:ef7eb2e8f9f7	1031	}
<>	144:ef7eb2e8f9f7	1032	}
<>	144:ef7eb2e8f9f7	1033
<>	144:ef7eb2e8f9f7	1034	/* Wait until AF flag is set */
<>	144:ef7eb2e8f9f7	1035	if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_AF, RESET, Timeout, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	1036	{
<>	144:ef7eb2e8f9f7	1037	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	1038	}
<>	144:ef7eb2e8f9f7	1039
<>	144:ef7eb2e8f9f7	1040	/* Clear AF flag */
<>	144:ef7eb2e8f9f7	1041	__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
<>	144:ef7eb2e8f9f7	1042
<>	144:ef7eb2e8f9f7	1043	/* Disable Address Acknowledge */
<>	144:ef7eb2e8f9f7	1044	hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
<>	144:ef7eb2e8f9f7	1045
<>	144:ef7eb2e8f9f7	1046	hi2c->State = HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	1047	hi2c->Mode = HAL_I2C_MODE_NONE;
AnnaBridge	167:e84263d55307	1048
<>	144:ef7eb2e8f9f7	1049	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	1050	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	1051
<>	144:ef7eb2e8f9f7	1052	return HAL_OK;
<>	144:ef7eb2e8f9f7	1053	}
<>	144:ef7eb2e8f9f7	1054	else
<>	144:ef7eb2e8f9f7	1055	{
<>	144:ef7eb2e8f9f7	1056	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	1057	}
<>	144:ef7eb2e8f9f7	1058	}
<>	144:ef7eb2e8f9f7	1059
<>	144:ef7eb2e8f9f7	1060	/**
AnnaBridge	167:e84263d55307	1061	* @brief Receive in slave mode an amount of data in blocking mode
<>	144:ef7eb2e8f9f7	1062	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
AnnaBridge	167:e84263d55307	1063	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	1064	* @param pData Pointer to data buffer
<>	144:ef7eb2e8f9f7	1065	* @param Size Amount of data to be sent
<>	144:ef7eb2e8f9f7	1066	* @param Timeout Timeout duration
<>	144:ef7eb2e8f9f7	1067	* @retval HAL status
<>	144:ef7eb2e8f9f7	1068	*/
<>	144:ef7eb2e8f9f7	1069	HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef hi2c, uint8_t pData, uint16_t Size, uint32_t Timeout)
<>	144:ef7eb2e8f9f7	1070	{
<>	144:ef7eb2e8f9f7	1071	uint32_t tickstart = 0x00U;
AnnaBridge	167:e84263d55307	1072
<>	144:ef7eb2e8f9f7	1073	/* Init tickstart for timeout management*/
<>	144:ef7eb2e8f9f7	1074	tickstart = HAL_GetTick();
<>	144:ef7eb2e8f9f7	1075
<>	144:ef7eb2e8f9f7	1076	if(hi2c->State == HAL_I2C_STATE_READY)
<>	144:ef7eb2e8f9f7	1077	{
AnnaBridge	167:e84263d55307	1078	if((pData == NULL) \|\| (Size == 0))
<>	144:ef7eb2e8f9f7	1079	{
<>	144:ef7eb2e8f9f7	1080	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	1081	}
<>	144:ef7eb2e8f9f7	1082
<>	144:ef7eb2e8f9f7	1083	/* Process Locked */
<>	144:ef7eb2e8f9f7	1084	__HAL_LOCK(hi2c);
AnnaBridge	167:e84263d55307	1085
AnnaBridge	167:e84263d55307	1086	/* Check if the I2C is already enabled */
AnnaBridge	167:e84263d55307	1087	if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
AnnaBridge	167:e84263d55307	1088	{
AnnaBridge	167:e84263d55307	1089	/* Enable I2C peripheral */
AnnaBridge	167:e84263d55307	1090	__HAL_I2C_ENABLE(hi2c);
AnnaBridge	167:e84263d55307	1091	}
AnnaBridge	167:e84263d55307	1092
<>	144:ef7eb2e8f9f7	1093	/* Disable Pos */
<>	144:ef7eb2e8f9f7	1094	hi2c->Instance->CR1 &= ~I2C_CR1_POS;
<>	144:ef7eb2e8f9f7	1095
AnnaBridge	167:e84263d55307	1096	hi2c->State = HAL_I2C_STATE_BUSY_RX;
AnnaBridge	167:e84263d55307	1097	hi2c->Mode = HAL_I2C_MODE_SLAVE;
AnnaBridge	167:e84263d55307	1098	hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
AnnaBridge	167:e84263d55307	1099
AnnaBridge	167:e84263d55307	1100	/* Prepare transfer parameters */
AnnaBridge	167:e84263d55307	1101	hi2c->pBuffPtr = pData;
AnnaBridge	167:e84263d55307	1102	hi2c->XferCount = Size;
<>	144:ef7eb2e8f9f7	1103	hi2c->XferOptions = I2C_NO_OPTION_FRAME;
AnnaBridge	167:e84263d55307	1104	hi2c->XferSize = hi2c->XferCount;
AnnaBridge	167:e84263d55307	1105
<>	144:ef7eb2e8f9f7	1106	/* Enable Address Acknowledge */
<>	144:ef7eb2e8f9f7	1107	hi2c->Instance->CR1 \|= I2C_CR1_ACK;
<>	144:ef7eb2e8f9f7	1108
<>	144:ef7eb2e8f9f7	1109	/* Wait until ADDR flag is set */
<>	144:ef7eb2e8f9f7	1110	if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	1111	{
<>	144:ef7eb2e8f9f7	1112	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	1113	}
<>	144:ef7eb2e8f9f7	1114
<>	144:ef7eb2e8f9f7	1115	/* Clear ADDR flag */
<>	144:ef7eb2e8f9f7	1116	__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
<>	144:ef7eb2e8f9f7	1117
AnnaBridge	167:e84263d55307	1118	while(hi2c->XferSize > 0U)
<>	144:ef7eb2e8f9f7	1119	{
<>	144:ef7eb2e8f9f7	1120	/* Wait until RXNE flag is set */
<>	144:ef7eb2e8f9f7	1121	if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	1122	{
<>	144:ef7eb2e8f9f7	1123	/* Disable Address Acknowledge */
<>	144:ef7eb2e8f9f7	1124	hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
AnnaBridge	167:e84263d55307	1125
<>	144:ef7eb2e8f9f7	1126	if(hi2c->ErrorCode == HAL_I2C_ERROR_TIMEOUT)
<>	144:ef7eb2e8f9f7	1127	{
<>	144:ef7eb2e8f9f7	1128	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	1129	}
<>	144:ef7eb2e8f9f7	1130	else
<>	144:ef7eb2e8f9f7	1131	{
<>	144:ef7eb2e8f9f7	1132	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	1133	}
<>	144:ef7eb2e8f9f7	1134	}
<>	144:ef7eb2e8f9f7	1135
<>	144:ef7eb2e8f9f7	1136	/* Read data from DR */
AnnaBridge	167:e84263d55307	1137	(*hi2c->pBuffPtr++) = hi2c->Instance->DR;
AnnaBridge	167:e84263d55307	1138	hi2c->XferSize--;
AnnaBridge	167:e84263d55307	1139	hi2c->XferCount--;
<>	144:ef7eb2e8f9f7	1140
<>	144:ef7eb2e8f9f7	1141	if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (Size != 0U))
<>	144:ef7eb2e8f9f7	1142	{
<>	144:ef7eb2e8f9f7	1143	/* Read data from DR */
AnnaBridge	167:e84263d55307	1144	(*hi2c->pBuffPtr++) = hi2c->Instance->DR;
AnnaBridge	167:e84263d55307	1145	hi2c->XferSize--;
AnnaBridge	167:e84263d55307	1146	hi2c->XferCount--;
<>	144:ef7eb2e8f9f7	1147	}
<>	144:ef7eb2e8f9f7	1148	}
<>	144:ef7eb2e8f9f7	1149
<>	144:ef7eb2e8f9f7	1150	/* Wait until STOP flag is set */
<>	144:ef7eb2e8f9f7	1151	if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	1152	{
<>	144:ef7eb2e8f9f7	1153	/* Disable Address Acknowledge */
<>	144:ef7eb2e8f9f7	1154	hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
<>	144:ef7eb2e8f9f7	1155
<>	144:ef7eb2e8f9f7	1156	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
<>	144:ef7eb2e8f9f7	1157	{
<>	144:ef7eb2e8f9f7	1158	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	1159	}
<>	144:ef7eb2e8f9f7	1160	else
<>	144:ef7eb2e8f9f7	1161	{
<>	144:ef7eb2e8f9f7	1162	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	1163	}
<>	144:ef7eb2e8f9f7	1164	}
<>	144:ef7eb2e8f9f7	1165
<>	144:ef7eb2e8f9f7	1166	/* Clear STOP flag */
<>	144:ef7eb2e8f9f7	1167	__HAL_I2C_CLEAR_STOPFLAG(hi2c);
<>	144:ef7eb2e8f9f7	1168
<>	144:ef7eb2e8f9f7	1169	/* Disable Address Acknowledge */
<>	144:ef7eb2e8f9f7	1170	hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
<>	144:ef7eb2e8f9f7	1171
<>	144:ef7eb2e8f9f7	1172	hi2c->State = HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	1173	hi2c->Mode = HAL_I2C_MODE_NONE;
AnnaBridge	167:e84263d55307	1174
<>	144:ef7eb2e8f9f7	1175	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	1176	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	1177
<>	144:ef7eb2e8f9f7	1178	return HAL_OK;
<>	144:ef7eb2e8f9f7	1179	}
<>	144:ef7eb2e8f9f7	1180	else
<>	144:ef7eb2e8f9f7	1181	{
<>	144:ef7eb2e8f9f7	1182	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	1183	}
<>	144:ef7eb2e8f9f7	1184	}
<>	144:ef7eb2e8f9f7	1185
<>	144:ef7eb2e8f9f7	1186	/**
AnnaBridge	167:e84263d55307	1187	* @brief Transmit in master mode an amount of data in non-blocking mode with Interrupt
<>	144:ef7eb2e8f9f7	1188	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
AnnaBridge	167:e84263d55307	1189	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	1190	* @param DevAddress Target device address: The device 7 bits address value
<>	144:ef7eb2e8f9f7	1191	* in datasheet must be shift at right before call interface
<>	144:ef7eb2e8f9f7	1192	* @param pData Pointer to data buffer
<>	144:ef7eb2e8f9f7	1193	* @param Size Amount of data to be sent
<>	144:ef7eb2e8f9f7	1194	* @retval HAL status
<>	144:ef7eb2e8f9f7	1195	*/
<>	144:ef7eb2e8f9f7	1196	HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef hi2c, uint16_t DevAddress, uint8_t pData, uint16_t Size)
<>	144:ef7eb2e8f9f7	1197	{
<>	144:ef7eb2e8f9f7	1198	__IO uint32_t count = 0U;
<>	144:ef7eb2e8f9f7	1199
<>	144:ef7eb2e8f9f7	1200	if(hi2c->State == HAL_I2C_STATE_READY)
<>	144:ef7eb2e8f9f7	1201	{
<>	144:ef7eb2e8f9f7	1202	/* Wait until BUSY flag is reset */
<>	144:ef7eb2e8f9f7	1203	count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U);
<>	144:ef7eb2e8f9f7	1204	do
<>	144:ef7eb2e8f9f7	1205	{
<>	144:ef7eb2e8f9f7	1206	if(count-- == 0U)
<>	144:ef7eb2e8f9f7	1207	{
<>	144:ef7eb2e8f9f7	1208	hi2c->PreviousState = I2C_STATE_NONE;
<>	144:ef7eb2e8f9f7	1209	hi2c->State= HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	1210
<>	144:ef7eb2e8f9f7	1211	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	1212	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	1213
AnnaBridge	167:e84263d55307	1214	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	1215	}
<>	144:ef7eb2e8f9f7	1216	}
<>	144:ef7eb2e8f9f7	1217	while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
<>	144:ef7eb2e8f9f7	1218
<>	144:ef7eb2e8f9f7	1219	/* Process Locked */
<>	144:ef7eb2e8f9f7	1220	__HAL_LOCK(hi2c);
AnnaBridge	167:e84263d55307	1221
AnnaBridge	167:e84263d55307	1222	/* Check if the I2C is already enabled */
AnnaBridge	167:e84263d55307	1223	if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
AnnaBridge	167:e84263d55307	1224	{
AnnaBridge	167:e84263d55307	1225	/* Enable I2C peripheral */
AnnaBridge	167:e84263d55307	1226	__HAL_I2C_ENABLE(hi2c);
AnnaBridge	167:e84263d55307	1227	}
<>	144:ef7eb2e8f9f7	1228
<>	144:ef7eb2e8f9f7	1229	/* Disable Pos */
<>	144:ef7eb2e8f9f7	1230	hi2c->Instance->CR1 &= ~I2C_CR1_POS;
<>	144:ef7eb2e8f9f7	1231
AnnaBridge	167:e84263d55307	1232	hi2c->State = HAL_I2C_STATE_BUSY_TX;
AnnaBridge	167:e84263d55307	1233	hi2c->Mode = HAL_I2C_MODE_MASTER;
<>	144:ef7eb2e8f9f7	1234	hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
<>	144:ef7eb2e8f9f7	1235
AnnaBridge	167:e84263d55307	1236	/* Prepare transfer parameters */
AnnaBridge	167:e84263d55307	1237	hi2c->pBuffPtr = pData;
AnnaBridge	167:e84263d55307	1238	hi2c->XferCount = Size;
<>	144:ef7eb2e8f9f7	1239	hi2c->XferOptions = I2C_NO_OPTION_FRAME;
AnnaBridge	167:e84263d55307	1240	hi2c->XferSize = hi2c->XferCount;
AnnaBridge	167:e84263d55307	1241	hi2c->Devaddress = DevAddress;
<>	144:ef7eb2e8f9f7	1242
<>	144:ef7eb2e8f9f7	1243	/* Generate Start */
<>	144:ef7eb2e8f9f7	1244	hi2c->Instance->CR1 \|= I2C_CR1_START;
<>	144:ef7eb2e8f9f7	1245
<>	144:ef7eb2e8f9f7	1246	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	1247	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	1248
<>	144:ef7eb2e8f9f7	1249	/* Note : The I2C interrupts must be enabled after unlocking current process
<>	144:ef7eb2e8f9f7	1250	to avoid the risk of I2C interrupt handle execution before current
<>	144:ef7eb2e8f9f7	1251	process unlock */
<>	144:ef7eb2e8f9f7	1252	/* Enable EVT, BUF and ERR interrupt */
<>	144:ef7eb2e8f9f7	1253	__HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT \| I2C_IT_BUF \| I2C_IT_ERR);
<>	144:ef7eb2e8f9f7	1254
<>	144:ef7eb2e8f9f7	1255	return HAL_OK;
<>	144:ef7eb2e8f9f7	1256	}
<>	144:ef7eb2e8f9f7	1257	else
<>	144:ef7eb2e8f9f7	1258	{
<>	144:ef7eb2e8f9f7	1259	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	1260	}
<>	144:ef7eb2e8f9f7	1261	}
<>	144:ef7eb2e8f9f7	1262
<>	144:ef7eb2e8f9f7	1263	/**
AnnaBridge	167:e84263d55307	1264	* @brief Receive in master mode an amount of data in non-blocking mode with Interrupt
<>	144:ef7eb2e8f9f7	1265	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
AnnaBridge	167:e84263d55307	1266	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	1267	* @param DevAddress Target device address: The device 7 bits address value
<>	144:ef7eb2e8f9f7	1268	* in datasheet must be shift at right before call interface
<>	144:ef7eb2e8f9f7	1269	* @param pData Pointer to data buffer
<>	144:ef7eb2e8f9f7	1270	* @param Size Amount of data to be sent
<>	144:ef7eb2e8f9f7	1271	* @retval HAL status
<>	144:ef7eb2e8f9f7	1272	*/
<>	144:ef7eb2e8f9f7	1273	HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef hi2c, uint16_t DevAddress, uint8_t pData, uint16_t Size)
<>	144:ef7eb2e8f9f7	1274	{
<>	144:ef7eb2e8f9f7	1275	__IO uint32_t count = 0U;
<>	144:ef7eb2e8f9f7	1276
<>	144:ef7eb2e8f9f7	1277	if(hi2c->State == HAL_I2C_STATE_READY)
<>	144:ef7eb2e8f9f7	1278	{
<>	144:ef7eb2e8f9f7	1279	/* Wait until BUSY flag is reset */
<>	144:ef7eb2e8f9f7	1280	count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U);
<>	144:ef7eb2e8f9f7	1281	do
<>	144:ef7eb2e8f9f7	1282	{
<>	144:ef7eb2e8f9f7	1283	if(count-- == 0U)
<>	144:ef7eb2e8f9f7	1284	{
<>	144:ef7eb2e8f9f7	1285	hi2c->PreviousState = I2C_STATE_NONE;
<>	144:ef7eb2e8f9f7	1286	hi2c->State= HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	1287
<>	144:ef7eb2e8f9f7	1288	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	1289	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	1290
<>	144:ef7eb2e8f9f7	1291	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	1292	}
<>	144:ef7eb2e8f9f7	1293	}
<>	144:ef7eb2e8f9f7	1294	while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
<>	144:ef7eb2e8f9f7	1295
<>	144:ef7eb2e8f9f7	1296	/* Process Locked */
<>	144:ef7eb2e8f9f7	1297	__HAL_LOCK(hi2c);
<>	144:ef7eb2e8f9f7	1298
AnnaBridge	167:e84263d55307	1299	/* Check if the I2C is already enabled */
AnnaBridge	167:e84263d55307	1300	if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
AnnaBridge	167:e84263d55307	1301	{
AnnaBridge	167:e84263d55307	1302	/* Enable I2C peripheral */
AnnaBridge	167:e84263d55307	1303	__HAL_I2C_ENABLE(hi2c);
AnnaBridge	167:e84263d55307	1304	}
AnnaBridge	167:e84263d55307	1305
<>	144:ef7eb2e8f9f7	1306	/* Disable Pos */
<>	144:ef7eb2e8f9f7	1307	hi2c->Instance->CR1 &= ~I2C_CR1_POS;
<>	144:ef7eb2e8f9f7	1308
AnnaBridge	167:e84263d55307	1309	hi2c->State = HAL_I2C_STATE_BUSY_RX;
AnnaBridge	167:e84263d55307	1310	hi2c->Mode = HAL_I2C_MODE_MASTER;
<>	144:ef7eb2e8f9f7	1311	hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
AnnaBridge	167:e84263d55307	1312
AnnaBridge	167:e84263d55307	1313	/* Prepare transfer parameters */
AnnaBridge	167:e84263d55307	1314	hi2c->pBuffPtr = pData;
AnnaBridge	167:e84263d55307	1315	hi2c->XferCount = Size;
<>	144:ef7eb2e8f9f7	1316	hi2c->XferOptions = I2C_NO_OPTION_FRAME;
AnnaBridge	167:e84263d55307	1317	hi2c->XferSize = hi2c->XferCount;
AnnaBridge	167:e84263d55307	1318	hi2c->Devaddress = DevAddress;
AnnaBridge	167:e84263d55307	1319
<>	144:ef7eb2e8f9f7	1320	/* Enable Acknowledge */
<>	144:ef7eb2e8f9f7	1321	hi2c->Instance->CR1 \|= I2C_CR1_ACK;
AnnaBridge	167:e84263d55307	1322
<>	144:ef7eb2e8f9f7	1323	/* Generate Start */
<>	144:ef7eb2e8f9f7	1324	hi2c->Instance->CR1 \|= I2C_CR1_START;
AnnaBridge	167:e84263d55307	1325
<>	144:ef7eb2e8f9f7	1326	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	1327	__HAL_UNLOCK(hi2c);
AnnaBridge	167:e84263d55307	1328
<>	144:ef7eb2e8f9f7	1329	/* Note : The I2C interrupts must be enabled after unlocking current process
<>	144:ef7eb2e8f9f7	1330	to avoid the risk of I2C interrupt handle execution before current
<>	144:ef7eb2e8f9f7	1331	process unlock */
AnnaBridge	167:e84263d55307	1332
<>	144:ef7eb2e8f9f7	1333	/* Enable EVT, BUF and ERR interrupt */
<>	144:ef7eb2e8f9f7	1334	__HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT \| I2C_IT_BUF \| I2C_IT_ERR);
AnnaBridge	167:e84263d55307	1335
<>	144:ef7eb2e8f9f7	1336	return HAL_OK;
<>	144:ef7eb2e8f9f7	1337	}
<>	144:ef7eb2e8f9f7	1338	else
<>	144:ef7eb2e8f9f7	1339	{
<>	144:ef7eb2e8f9f7	1340	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	1341	}
<>	144:ef7eb2e8f9f7	1342	}
<>	144:ef7eb2e8f9f7	1343
<>	144:ef7eb2e8f9f7	1344	/**
AnnaBridge	167:e84263d55307	1345	* @brief Sequential transmit in master mode an amount of data in non-blocking mode with Interrupt
<>	144:ef7eb2e8f9f7	1346	* @note This interface allow to manage repeated start condition when a direction change during transfer
<>	144:ef7eb2e8f9f7	1347	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
AnnaBridge	167:e84263d55307	1348	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	1349	* @param DevAddress Target device address: The device 7 bits address value
<>	144:ef7eb2e8f9f7	1350	* in datasheet must be shift at right before call interface
<>	144:ef7eb2e8f9f7	1351	* @param pData Pointer to data buffer
<>	144:ef7eb2e8f9f7	1352	* @param Size Amount of data to be sent
<>	144:ef7eb2e8f9f7	1353	* @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition
<>	144:ef7eb2e8f9f7	1354	* @retval HAL status
<>	144:ef7eb2e8f9f7	1355	*/
<>	144:ef7eb2e8f9f7	1356	HAL_StatusTypeDef HAL_I2C_Master_Sequential_Transmit_IT(I2C_HandleTypeDef hi2c, uint16_t DevAddress, uint8_t pData, uint16_t Size, uint32_t XferOptions)
<>	144:ef7eb2e8f9f7	1357	{
AnnaBridge	167:e84263d55307	1358	__IO uint32_t Prev_State = 0x00U;
AnnaBridge	167:e84263d55307	1359	__IO uint32_t count = 0x00U;
<>	144:ef7eb2e8f9f7	1360
<>	144:ef7eb2e8f9f7	1361	/* Check the parameters */
<>	144:ef7eb2e8f9f7	1362	assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
<>	144:ef7eb2e8f9f7	1363
<>	144:ef7eb2e8f9f7	1364	if(hi2c->State == HAL_I2C_STATE_READY)
<>	144:ef7eb2e8f9f7	1365	{
<>	144:ef7eb2e8f9f7	1366	/* Check Busy Flag only if FIRST call of Master interface */
<>	144:ef7eb2e8f9f7	1367	if((XferOptions == I2C_FIRST_AND_LAST_FRAME) \|\| (XferOptions == I2C_FIRST_FRAME))
<>	144:ef7eb2e8f9f7	1368	{
<>	144:ef7eb2e8f9f7	1369	/* Wait until BUSY flag is reset */
<>	144:ef7eb2e8f9f7	1370	count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U);
<>	144:ef7eb2e8f9f7	1371	do
<>	144:ef7eb2e8f9f7	1372	{
<>	144:ef7eb2e8f9f7	1373	if(count-- == 0U)
<>	144:ef7eb2e8f9f7	1374	{
<>	144:ef7eb2e8f9f7	1375	hi2c->PreviousState = I2C_STATE_NONE;
<>	144:ef7eb2e8f9f7	1376	hi2c->State= HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	1377
<>	144:ef7eb2e8f9f7	1378	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	1379	__HAL_UNLOCK(hi2c);
<>	148:21d94c44109e	1380
<>	144:ef7eb2e8f9f7	1381	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	1382	}
<>	144:ef7eb2e8f9f7	1383	}
<>	144:ef7eb2e8f9f7	1384	while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
<>	144:ef7eb2e8f9f7	1385	}
<>	144:ef7eb2e8f9f7	1386
<>	144:ef7eb2e8f9f7	1387	/* Process Locked */
<>	144:ef7eb2e8f9f7	1388	__HAL_LOCK(hi2c);
<>	144:ef7eb2e8f9f7	1389
AnnaBridge	167:e84263d55307	1390	/* Check if the I2C is already enabled */
AnnaBridge	167:e84263d55307	1391	if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
AnnaBridge	167:e84263d55307	1392	{
AnnaBridge	167:e84263d55307	1393	/* Enable I2C peripheral */
AnnaBridge	167:e84263d55307	1394	__HAL_I2C_ENABLE(hi2c);
AnnaBridge	167:e84263d55307	1395	}
AnnaBridge	167:e84263d55307	1396
<>	144:ef7eb2e8f9f7	1397	/* Disable Pos */
<>	144:ef7eb2e8f9f7	1398	hi2c->Instance->CR1 &= ~I2C_CR1_POS;
<>	144:ef7eb2e8f9f7	1399
AnnaBridge	167:e84263d55307	1400	hi2c->State = HAL_I2C_STATE_BUSY_TX;
AnnaBridge	167:e84263d55307	1401	hi2c->Mode = HAL_I2C_MODE_MASTER;
<>	144:ef7eb2e8f9f7	1402	hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
<>	144:ef7eb2e8f9f7	1403
AnnaBridge	167:e84263d55307	1404	/* Prepare transfer parameters */
AnnaBridge	167:e84263d55307	1405	hi2c->pBuffPtr = pData;
AnnaBridge	167:e84263d55307	1406	hi2c->XferCount = Size;
<>	144:ef7eb2e8f9f7	1407	hi2c->XferOptions = XferOptions;
AnnaBridge	167:e84263d55307	1408	hi2c->XferSize = hi2c->XferCount;
AnnaBridge	167:e84263d55307	1409	hi2c->Devaddress = DevAddress;
<>	144:ef7eb2e8f9f7	1410
<>	144:ef7eb2e8f9f7	1411	Prev_State = hi2c->PreviousState;
<>	148:21d94c44109e	1412
<>	144:ef7eb2e8f9f7	1413	/* Generate Start */
<>	144:ef7eb2e8f9f7	1414	if((Prev_State == I2C_STATE_MASTER_BUSY_RX) \|\| (Prev_State == I2C_STATE_NONE))
<>	144:ef7eb2e8f9f7	1415	{
Kojto	170:19eb464bc2be	1416	/* Generate Start condition if first transfer */
Kojto	170:19eb464bc2be	1417	if((XferOptions == I2C_FIRST_AND_LAST_FRAME) \|\| (XferOptions == I2C_FIRST_FRAME))
Kojto	170:19eb464bc2be	1418	{
Kojto	170:19eb464bc2be	1419	/* Generate Start */
<>	144:ef7eb2e8f9f7	1420	hi2c->Instance->CR1 \|= I2C_CR1_START;
Kojto	170:19eb464bc2be	1421	}
Kojto	170:19eb464bc2be	1422	else if(Prev_State == I2C_STATE_MASTER_BUSY_RX) // MBED
Kojto	170:19eb464bc2be	1423	{
Kojto	170:19eb464bc2be	1424	/* Generate ReStart */
Kojto	170:19eb464bc2be	1425	hi2c->Instance->CR1 \|= I2C_CR1_START;
Kojto	170:19eb464bc2be	1426	}
<>	144:ef7eb2e8f9f7	1427	}
<>	144:ef7eb2e8f9f7	1428
<>	144:ef7eb2e8f9f7	1429	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	1430	__HAL_UNLOCK(hi2c);
AnnaBridge	167:e84263d55307	1431
<>	144:ef7eb2e8f9f7	1432	/* Note : The I2C interrupts must be enabled after unlocking current process
<>	144:ef7eb2e8f9f7	1433	to avoid the risk of I2C interrupt handle execution before current
<>	144:ef7eb2e8f9f7	1434	process unlock */
AnnaBridge	167:e84263d55307	1435
<>	144:ef7eb2e8f9f7	1436	/* Enable EVT, BUF and ERR interrupt */
<>	144:ef7eb2e8f9f7	1437	__HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT \| I2C_IT_BUF \| I2C_IT_ERR);
AnnaBridge	167:e84263d55307	1438
<>	144:ef7eb2e8f9f7	1439	return HAL_OK;
<>	144:ef7eb2e8f9f7	1440	}
<>	144:ef7eb2e8f9f7	1441	else
<>	144:ef7eb2e8f9f7	1442	{
<>	144:ef7eb2e8f9f7	1443	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	1444	}
<>	144:ef7eb2e8f9f7	1445	}
<>	144:ef7eb2e8f9f7	1446
<>	144:ef7eb2e8f9f7	1447	/**
AnnaBridge	167:e84263d55307	1448	* @brief Sequential receive in master mode an amount of data in non-blocking mode with Interrupt
<>	144:ef7eb2e8f9f7	1449	* @note This interface allow to manage repeated start condition when a direction change during transfer
<>	144:ef7eb2e8f9f7	1450	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
AnnaBridge	167:e84263d55307	1451	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	1452	* @param DevAddress Target device address: The device 7 bits address value
<>	144:ef7eb2e8f9f7	1453	* in datasheet must be shift at right before call interface
<>	144:ef7eb2e8f9f7	1454	* @param pData Pointer to data buffer
<>	144:ef7eb2e8f9f7	1455	* @param Size Amount of data to be sent
<>	144:ef7eb2e8f9f7	1456	* @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition
<>	144:ef7eb2e8f9f7	1457	* @retval HAL status
<>	144:ef7eb2e8f9f7	1458	*/
<>	144:ef7eb2e8f9f7	1459	HAL_StatusTypeDef HAL_I2C_Master_Sequential_Receive_IT(I2C_HandleTypeDef hi2c, uint16_t DevAddress, uint8_t pData, uint16_t Size, uint32_t XferOptions)
<>	144:ef7eb2e8f9f7	1460	{
<>	144:ef7eb2e8f9f7	1461	__IO uint32_t count = 0U;
<>	144:ef7eb2e8f9f7	1462
<>	144:ef7eb2e8f9f7	1463	/* Check the parameters */
<>	144:ef7eb2e8f9f7	1464	assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
<>	144:ef7eb2e8f9f7	1465
<>	144:ef7eb2e8f9f7	1466	if(hi2c->State == HAL_I2C_STATE_READY)
<>	144:ef7eb2e8f9f7	1467	{
<>	144:ef7eb2e8f9f7	1468	/* Check Busy Flag only if FIRST call of Master interface */
<>	144:ef7eb2e8f9f7	1469	if((XferOptions == I2C_FIRST_AND_LAST_FRAME) \|\| (XferOptions == I2C_FIRST_FRAME))
<>	144:ef7eb2e8f9f7	1470	{
<>	144:ef7eb2e8f9f7	1471	/* Wait until BUSY flag is reset */
<>	144:ef7eb2e8f9f7	1472	count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U);
<>	144:ef7eb2e8f9f7	1473	do
<>	144:ef7eb2e8f9f7	1474	{
<>	144:ef7eb2e8f9f7	1475	if(count-- == 0U)
<>	144:ef7eb2e8f9f7	1476	{
<>	144:ef7eb2e8f9f7	1477	hi2c->PreviousState = I2C_STATE_NONE;
<>	144:ef7eb2e8f9f7	1478	hi2c->State= HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	1479
<>	144:ef7eb2e8f9f7	1480	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	1481	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	1482
<>	144:ef7eb2e8f9f7	1483	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	1484	}
<>	144:ef7eb2e8f9f7	1485	}
<>	144:ef7eb2e8f9f7	1486	while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
<>	144:ef7eb2e8f9f7	1487	}
<>	144:ef7eb2e8f9f7	1488
<>	144:ef7eb2e8f9f7	1489	/* Process Locked */
<>	144:ef7eb2e8f9f7	1490	__HAL_LOCK(hi2c);
<>	144:ef7eb2e8f9f7	1491
AnnaBridge	167:e84263d55307	1492	/* Check if the I2C is already enabled */
AnnaBridge	167:e84263d55307	1493	if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
AnnaBridge	167:e84263d55307	1494	{
AnnaBridge	167:e84263d55307	1495	/* Enable I2C peripheral */
AnnaBridge	167:e84263d55307	1496	__HAL_I2C_ENABLE(hi2c);
AnnaBridge	167:e84263d55307	1497	}
AnnaBridge	167:e84263d55307	1498
<>	144:ef7eb2e8f9f7	1499	/* Disable Pos */
<>	144:ef7eb2e8f9f7	1500	hi2c->Instance->CR1 &= ~I2C_CR1_POS;
<>	144:ef7eb2e8f9f7	1501
AnnaBridge	167:e84263d55307	1502	hi2c->State = HAL_I2C_STATE_BUSY_RX;
AnnaBridge	167:e84263d55307	1503	hi2c->Mode = HAL_I2C_MODE_MASTER;
<>	144:ef7eb2e8f9f7	1504	hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
<>	144:ef7eb2e8f9f7	1505
AnnaBridge	167:e84263d55307	1506	/* Prepare transfer parameters */
<>	144:ef7eb2e8f9f7	1507	hi2c->pBuffPtr = pData;
<>	144:ef7eb2e8f9f7	1508	hi2c->XferCount = Size;
<>	144:ef7eb2e8f9f7	1509	hi2c->XferOptions = XferOptions;
AnnaBridge	167:e84263d55307	1510	hi2c->XferSize = hi2c->XferCount;
<>	144:ef7eb2e8f9f7	1511	hi2c->Devaddress = DevAddress;
<>	144:ef7eb2e8f9f7	1512
AnnaBridge	167:e84263d55307	1513	if((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) \|\| (hi2c->PreviousState == I2C_STATE_NONE))
<>	144:ef7eb2e8f9f7	1514	{
Kojto	170:19eb464bc2be	1515	/* Generate Start condition if first transfer */
Kojto	170:19eb464bc2be	1516	if((XferOptions == I2C_FIRST_AND_LAST_FRAME) \|\| (XferOptions == I2C_FIRST_FRAME) \|\| (XferOptions == I2C_NO_OPTION_FRAME))
Kojto	170:19eb464bc2be	1517	{
<>	144:ef7eb2e8f9f7	1518	/* Enable Acknowledge */
<>	144:ef7eb2e8f9f7	1519	hi2c->Instance->CR1 \|= I2C_CR1_ACK;
Kojto	170:19eb464bc2be	1520
Kojto	170:19eb464bc2be	1521	/* Generate Start */
<>	144:ef7eb2e8f9f7	1522	hi2c->Instance->CR1 \|= I2C_CR1_START;
Kojto	170:19eb464bc2be	1523	}
Kojto	170:19eb464bc2be	1524	else if(hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX)
Kojto	170:19eb464bc2be	1525	{
Kojto	170:19eb464bc2be	1526	/* Enable Acknowledge */
Kojto	170:19eb464bc2be	1527	hi2c->Instance->CR1 \|= I2C_CR1_ACK;
Kojto	170:19eb464bc2be	1528
Kojto	170:19eb464bc2be	1529	/* Generate ReStart */
Kojto	170:19eb464bc2be	1530	hi2c->Instance->CR1 \|= I2C_CR1_START;
Kojto	170:19eb464bc2be	1531	}
<>	144:ef7eb2e8f9f7	1532	}
<>	144:ef7eb2e8f9f7	1533
<>	144:ef7eb2e8f9f7	1534	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	1535	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	1536
<>	144:ef7eb2e8f9f7	1537	/* Note : The I2C interrupts must be enabled after unlocking current process
<>	144:ef7eb2e8f9f7	1538	to avoid the risk of I2C interrupt handle execution before current
<>	144:ef7eb2e8f9f7	1539	process unlock */
<>	144:ef7eb2e8f9f7	1540
<>	144:ef7eb2e8f9f7	1541	/* Enable EVT, BUF and ERR interrupt */
<>	144:ef7eb2e8f9f7	1542	__HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT \| I2C_IT_BUF \| I2C_IT_ERR);
<>	144:ef7eb2e8f9f7	1543
<>	144:ef7eb2e8f9f7	1544	return HAL_OK;
<>	144:ef7eb2e8f9f7	1545	}
<>	144:ef7eb2e8f9f7	1546	else
<>	144:ef7eb2e8f9f7	1547	{
<>	144:ef7eb2e8f9f7	1548	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	1549	}
<>	144:ef7eb2e8f9f7	1550	}
<>	144:ef7eb2e8f9f7	1551
<>	144:ef7eb2e8f9f7	1552	/**
AnnaBridge	167:e84263d55307	1553	* @brief Transmit in slave mode an amount of data in non-blocking mode with Interrupt
<>	144:ef7eb2e8f9f7	1554	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
AnnaBridge	167:e84263d55307	1555	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	1556	* @param pData Pointer to data buffer
<>	144:ef7eb2e8f9f7	1557	* @param Size Amount of data to be sent
<>	144:ef7eb2e8f9f7	1558	* @retval HAL status
<>	144:ef7eb2e8f9f7	1559	*/
<>	144:ef7eb2e8f9f7	1560	HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef hi2c, uint8_t pData, uint16_t Size)
<>	144:ef7eb2e8f9f7	1561	{
<>	144:ef7eb2e8f9f7	1562	__IO uint32_t count = 0U;
AnnaBridge	167:e84263d55307	1563
<>	144:ef7eb2e8f9f7	1564	if(hi2c->State == HAL_I2C_STATE_READY)
<>	144:ef7eb2e8f9f7	1565	{
<>	144:ef7eb2e8f9f7	1566	if((pData == NULL) \|\| (Size == 0U))
<>	144:ef7eb2e8f9f7	1567	{
<>	144:ef7eb2e8f9f7	1568	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	1569	}
AnnaBridge	167:e84263d55307	1570
<>	144:ef7eb2e8f9f7	1571	/* Wait until BUSY flag is reset */
<>	144:ef7eb2e8f9f7	1572	count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U);
<>	144:ef7eb2e8f9f7	1573	do
<>	144:ef7eb2e8f9f7	1574	{
<>	144:ef7eb2e8f9f7	1575	if(count-- == 0U)
<>	144:ef7eb2e8f9f7	1576	{
<>	144:ef7eb2e8f9f7	1577	hi2c->PreviousState = I2C_STATE_NONE;
<>	144:ef7eb2e8f9f7	1578	hi2c->State= HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	1579
<>	144:ef7eb2e8f9f7	1580	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	1581	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	1582
<>	144:ef7eb2e8f9f7	1583	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	1584	}
<>	144:ef7eb2e8f9f7	1585	}
<>	144:ef7eb2e8f9f7	1586	while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
<>	144:ef7eb2e8f9f7	1587
<>	144:ef7eb2e8f9f7	1588	/* Process Locked */
<>	144:ef7eb2e8f9f7	1589	__HAL_LOCK(hi2c);
AnnaBridge	167:e84263d55307	1590
AnnaBridge	167:e84263d55307	1591	/* Check if the I2C is already enabled */
AnnaBridge	167:e84263d55307	1592	if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
AnnaBridge	167:e84263d55307	1593	{
AnnaBridge	167:e84263d55307	1594	/* Enable I2C peripheral */
AnnaBridge	167:e84263d55307	1595	__HAL_I2C_ENABLE(hi2c);
AnnaBridge	167:e84263d55307	1596	}
AnnaBridge	167:e84263d55307	1597
<>	144:ef7eb2e8f9f7	1598	/* Disable Pos */
<>	144:ef7eb2e8f9f7	1599	hi2c->Instance->CR1 &= ~I2C_CR1_POS;
<>	144:ef7eb2e8f9f7	1600
AnnaBridge	167:e84263d55307	1601	hi2c->State = HAL_I2C_STATE_BUSY_TX;
AnnaBridge	167:e84263d55307	1602	hi2c->Mode = HAL_I2C_MODE_SLAVE;
<>	144:ef7eb2e8f9f7	1603	hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
<>	144:ef7eb2e8f9f7	1604
AnnaBridge	167:e84263d55307	1605	/* Prepare transfer parameters */
AnnaBridge	167:e84263d55307	1606	hi2c->pBuffPtr = pData;
AnnaBridge	167:e84263d55307	1607	hi2c->XferCount = Size;
<>	144:ef7eb2e8f9f7	1608	hi2c->XferOptions = I2C_NO_OPTION_FRAME;
AnnaBridge	167:e84263d55307	1609	hi2c->XferSize = hi2c->XferCount;
<>	144:ef7eb2e8f9f7	1610
<>	144:ef7eb2e8f9f7	1611	/* Enable Address Acknowledge */
<>	144:ef7eb2e8f9f7	1612	hi2c->Instance->CR1 \|= I2C_CR1_ACK;
<>	144:ef7eb2e8f9f7	1613
<>	144:ef7eb2e8f9f7	1614	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	1615	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	1616
<>	144:ef7eb2e8f9f7	1617	/* Note : The I2C interrupts must be enabled after unlocking current process
<>	144:ef7eb2e8f9f7	1618	to avoid the risk of I2C interrupt handle execution before current
<>	144:ef7eb2e8f9f7	1619	process unlock */
<>	144:ef7eb2e8f9f7	1620
<>	144:ef7eb2e8f9f7	1621	/* Enable EVT, BUF and ERR interrupt */
<>	144:ef7eb2e8f9f7	1622	__HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT \| I2C_IT_BUF \| I2C_IT_ERR);
<>	144:ef7eb2e8f9f7	1623
<>	144:ef7eb2e8f9f7	1624	return HAL_OK;
<>	144:ef7eb2e8f9f7	1625	}
<>	144:ef7eb2e8f9f7	1626	else
<>	144:ef7eb2e8f9f7	1627	{
<>	144:ef7eb2e8f9f7	1628	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	1629	}
<>	144:ef7eb2e8f9f7	1630	}
<>	144:ef7eb2e8f9f7	1631
<>	144:ef7eb2e8f9f7	1632	/**
AnnaBridge	167:e84263d55307	1633	* @brief Receive in slave mode an amount of data in non-blocking mode with Interrupt
<>	144:ef7eb2e8f9f7	1634	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
AnnaBridge	167:e84263d55307	1635	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	1636	* @param pData Pointer to data buffer
<>	144:ef7eb2e8f9f7	1637	* @param Size Amount of data to be sent
<>	144:ef7eb2e8f9f7	1638	* @retval HAL status
<>	144:ef7eb2e8f9f7	1639	*/
<>	144:ef7eb2e8f9f7	1640	HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef hi2c, uint8_t pData, uint16_t Size)
<>	144:ef7eb2e8f9f7	1641	{
<>	144:ef7eb2e8f9f7	1642	__IO uint32_t count = 0U;
<>	144:ef7eb2e8f9f7	1643
<>	144:ef7eb2e8f9f7	1644	if(hi2c->State == HAL_I2C_STATE_READY)
<>	144:ef7eb2e8f9f7	1645	{
<>	144:ef7eb2e8f9f7	1646	if((pData == NULL) \|\| (Size == 0U))
<>	144:ef7eb2e8f9f7	1647	{
<>	144:ef7eb2e8f9f7	1648	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	1649	}
<>	144:ef7eb2e8f9f7	1650
<>	144:ef7eb2e8f9f7	1651	/* Wait until BUSY flag is reset */
<>	144:ef7eb2e8f9f7	1652	count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U);
<>	144:ef7eb2e8f9f7	1653	do
<>	144:ef7eb2e8f9f7	1654	{
<>	144:ef7eb2e8f9f7	1655	if(count-- == 0U)
<>	144:ef7eb2e8f9f7	1656	{
<>	144:ef7eb2e8f9f7	1657	hi2c->PreviousState = I2C_STATE_NONE;
<>	144:ef7eb2e8f9f7	1658	hi2c->State= HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	1659
<>	144:ef7eb2e8f9f7	1660	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	1661	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	1662
<>	144:ef7eb2e8f9f7	1663	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	1664	}
<>	144:ef7eb2e8f9f7	1665	}
<>	144:ef7eb2e8f9f7	1666	while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
<>	144:ef7eb2e8f9f7	1667
<>	144:ef7eb2e8f9f7	1668	/* Process Locked */
<>	144:ef7eb2e8f9f7	1669	__HAL_LOCK(hi2c);
AnnaBridge	167:e84263d55307	1670
AnnaBridge	167:e84263d55307	1671	/* Check if the I2C is already enabled */
AnnaBridge	167:e84263d55307	1672	if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
AnnaBridge	167:e84263d55307	1673	{
AnnaBridge	167:e84263d55307	1674	/* Enable I2C peripheral */
AnnaBridge	167:e84263d55307	1675	__HAL_I2C_ENABLE(hi2c);
AnnaBridge	167:e84263d55307	1676	}
AnnaBridge	167:e84263d55307	1677
<>	144:ef7eb2e8f9f7	1678	/* Disable Pos */
<>	144:ef7eb2e8f9f7	1679	hi2c->Instance->CR1 &= ~I2C_CR1_POS;
<>	144:ef7eb2e8f9f7	1680
AnnaBridge	167:e84263d55307	1681	hi2c->State = HAL_I2C_STATE_BUSY_RX;
AnnaBridge	167:e84263d55307	1682	hi2c->Mode = HAL_I2C_MODE_SLAVE;
<>	144:ef7eb2e8f9f7	1683	hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
<>	144:ef7eb2e8f9f7	1684
AnnaBridge	167:e84263d55307	1685	/* Prepare transfer parameters */
<>	144:ef7eb2e8f9f7	1686	hi2c->pBuffPtr = pData;
<>	144:ef7eb2e8f9f7	1687	hi2c->XferSize = Size;
<>	144:ef7eb2e8f9f7	1688	hi2c->XferCount = Size;
<>	144:ef7eb2e8f9f7	1689	hi2c->XferOptions = I2C_NO_OPTION_FRAME;
<>	144:ef7eb2e8f9f7	1690
<>	144:ef7eb2e8f9f7	1691	/* Enable Address Acknowledge */
<>	144:ef7eb2e8f9f7	1692	hi2c->Instance->CR1 \|= I2C_CR1_ACK;
<>	144:ef7eb2e8f9f7	1693
<>	144:ef7eb2e8f9f7	1694	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	1695	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	1696
<>	144:ef7eb2e8f9f7	1697	/* Note : The I2C interrupts must be enabled after unlocking current process
<>	144:ef7eb2e8f9f7	1698	to avoid the risk of I2C interrupt handle execution before current
<>	144:ef7eb2e8f9f7	1699	process unlock */
<>	144:ef7eb2e8f9f7	1700
<>	144:ef7eb2e8f9f7	1701	/* Enable EVT, BUF and ERR interrupt */
<>	144:ef7eb2e8f9f7	1702	__HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT \| I2C_IT_BUF \| I2C_IT_ERR);
<>	144:ef7eb2e8f9f7	1703
<>	144:ef7eb2e8f9f7	1704	return HAL_OK;
<>	144:ef7eb2e8f9f7	1705	}
<>	144:ef7eb2e8f9f7	1706	else
<>	144:ef7eb2e8f9f7	1707	{
<>	144:ef7eb2e8f9f7	1708	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	1709	}
<>	144:ef7eb2e8f9f7	1710	}
<>	144:ef7eb2e8f9f7	1711
<>	144:ef7eb2e8f9f7	1712	/**
<>	144:ef7eb2e8f9f7	1713	* @brief Sequential transmit in slave mode an amount of data in no-blocking mode with Interrupt
<>	144:ef7eb2e8f9f7	1714	* @note This interface allow to manage repeated start condition when a direction change during transfer
<>	144:ef7eb2e8f9f7	1715	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	1716	* the configuration information for I2C module
<>	144:ef7eb2e8f9f7	1717	* @param pData Pointer to data buffer
<>	144:ef7eb2e8f9f7	1718	* @param Size Amount of data to be sent
<>	144:ef7eb2e8f9f7	1719	* @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition
<>	144:ef7eb2e8f9f7	1720	* @retval HAL status
<>	144:ef7eb2e8f9f7	1721	*/
<>	144:ef7eb2e8f9f7	1722	HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Transmit_IT(I2C_HandleTypeDef hi2c, uint8_t pData, uint16_t Size, uint32_t XferOptions)
<>	144:ef7eb2e8f9f7	1723	{
<>	144:ef7eb2e8f9f7	1724	/* Check the parameters */
<>	144:ef7eb2e8f9f7	1725	assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
<>	144:ef7eb2e8f9f7	1726
<>	144:ef7eb2e8f9f7	1727	if(hi2c->State == HAL_I2C_STATE_LISTEN)
<>	144:ef7eb2e8f9f7	1728	{
<>	144:ef7eb2e8f9f7	1729	if((pData == NULL) \|\| (Size == 0U))
<>	144:ef7eb2e8f9f7	1730	{
<>	144:ef7eb2e8f9f7	1731	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	1732	}
<>	144:ef7eb2e8f9f7	1733
<>	144:ef7eb2e8f9f7	1734	/* Process Locked */
<>	144:ef7eb2e8f9f7	1735	__HAL_LOCK(hi2c);
<>	144:ef7eb2e8f9f7	1736
AnnaBridge	167:e84263d55307	1737	/* Check if the I2C is already enabled */
AnnaBridge	167:e84263d55307	1738	if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
AnnaBridge	167:e84263d55307	1739	{
AnnaBridge	167:e84263d55307	1740	/* Enable I2C peripheral */
AnnaBridge	167:e84263d55307	1741	__HAL_I2C_ENABLE(hi2c);
AnnaBridge	167:e84263d55307	1742	}
AnnaBridge	167:e84263d55307	1743
<>	144:ef7eb2e8f9f7	1744	/* Disable Pos */
<>	144:ef7eb2e8f9f7	1745	hi2c->Instance->CR1 &= ~I2C_CR1_POS;
<>	144:ef7eb2e8f9f7	1746
AnnaBridge	167:e84263d55307	1747	hi2c->State = HAL_I2C_STATE_BUSY_TX_LISTEN;
AnnaBridge	167:e84263d55307	1748	hi2c->Mode = HAL_I2C_MODE_SLAVE;
<>	144:ef7eb2e8f9f7	1749	hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
<>	144:ef7eb2e8f9f7	1750
AnnaBridge	167:e84263d55307	1751	/* Prepare transfer parameters */
AnnaBridge	167:e84263d55307	1752	hi2c->pBuffPtr = pData;
AnnaBridge	167:e84263d55307	1753	hi2c->XferCount = Size;
<>	144:ef7eb2e8f9f7	1754	hi2c->XferOptions = XferOptions;
AnnaBridge	167:e84263d55307	1755	hi2c->XferSize = hi2c->XferCount;
<>	144:ef7eb2e8f9f7	1756
<>	144:ef7eb2e8f9f7	1757	/* Clear ADDR flag */
<>	144:ef7eb2e8f9f7	1758	__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
AnnaBridge	167:e84263d55307	1759
<>	144:ef7eb2e8f9f7	1760	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	1761	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	1762
<>	144:ef7eb2e8f9f7	1763	/* Note : The I2C interrupts must be enabled after unlocking current process
<>	144:ef7eb2e8f9f7	1764	to avoid the risk of I2C interrupt handle execution before current
<>	144:ef7eb2e8f9f7	1765	process unlock */
<>	144:ef7eb2e8f9f7	1766
<>	144:ef7eb2e8f9f7	1767	/* Enable EVT, BUF and ERR interrupt */
<>	144:ef7eb2e8f9f7	1768	__HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT \| I2C_IT_BUF \| I2C_IT_ERR);
<>	144:ef7eb2e8f9f7	1769
<>	144:ef7eb2e8f9f7	1770	return HAL_OK;
<>	144:ef7eb2e8f9f7	1771	}
<>	144:ef7eb2e8f9f7	1772	else
<>	144:ef7eb2e8f9f7	1773	{
<>	144:ef7eb2e8f9f7	1774	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	1775	}
<>	144:ef7eb2e8f9f7	1776	}
<>	144:ef7eb2e8f9f7	1777
<>	144:ef7eb2e8f9f7	1778	/**
AnnaBridge	167:e84263d55307	1779	* @brief Sequential receive in slave mode an amount of data in non-blocking mode with Interrupt
<>	144:ef7eb2e8f9f7	1780	* @note This interface allow to manage repeated start condition when a direction change during transfer
<>	144:ef7eb2e8f9f7	1781	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
AnnaBridge	167:e84263d55307	1782	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	1783	* @param pData Pointer to data buffer
<>	144:ef7eb2e8f9f7	1784	* @param Size Amount of data to be sent
<>	144:ef7eb2e8f9f7	1785	* @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition
<>	144:ef7eb2e8f9f7	1786	* @retval HAL status
<>	144:ef7eb2e8f9f7	1787	*/
<>	144:ef7eb2e8f9f7	1788	HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Receive_IT(I2C_HandleTypeDef hi2c, uint8_t pData, uint16_t Size, uint32_t XferOptions)
<>	144:ef7eb2e8f9f7	1789	{
<>	144:ef7eb2e8f9f7	1790	/* Check the parameters */
<>	144:ef7eb2e8f9f7	1791	assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
<>	144:ef7eb2e8f9f7	1792
<>	144:ef7eb2e8f9f7	1793	if(hi2c->State == HAL_I2C_STATE_LISTEN)
<>	144:ef7eb2e8f9f7	1794	{
<>	144:ef7eb2e8f9f7	1795	if((pData == NULL) \|\| (Size == 0U))
<>	144:ef7eb2e8f9f7	1796	{
<>	144:ef7eb2e8f9f7	1797	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	1798	}
<>	144:ef7eb2e8f9f7	1799
<>	144:ef7eb2e8f9f7	1800	/* Process Locked */
<>	144:ef7eb2e8f9f7	1801	__HAL_LOCK(hi2c);
<>	144:ef7eb2e8f9f7	1802
AnnaBridge	167:e84263d55307	1803	/* Check if the I2C is already enabled */
AnnaBridge	167:e84263d55307	1804	if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
AnnaBridge	167:e84263d55307	1805	{
AnnaBridge	167:e84263d55307	1806	/* Enable I2C peripheral */
AnnaBridge	167:e84263d55307	1807	__HAL_I2C_ENABLE(hi2c);
AnnaBridge	167:e84263d55307	1808	}
AnnaBridge	167:e84263d55307	1809
<>	144:ef7eb2e8f9f7	1810	/* Disable Pos */
<>	144:ef7eb2e8f9f7	1811	hi2c->Instance->CR1 &= ~I2C_CR1_POS;
<>	144:ef7eb2e8f9f7	1812
AnnaBridge	167:e84263d55307	1813	hi2c->State = HAL_I2C_STATE_BUSY_RX_LISTEN;
AnnaBridge	167:e84263d55307	1814	hi2c->Mode = HAL_I2C_MODE_SLAVE;
<>	144:ef7eb2e8f9f7	1815	hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
<>	144:ef7eb2e8f9f7	1816
AnnaBridge	167:e84263d55307	1817	/* Prepare transfer parameters */
AnnaBridge	167:e84263d55307	1818	hi2c->pBuffPtr = pData;
AnnaBridge	167:e84263d55307	1819	hi2c->XferCount = Size;
<>	144:ef7eb2e8f9f7	1820	hi2c->XferOptions = XferOptions;
AnnaBridge	167:e84263d55307	1821	hi2c->XferSize = hi2c->XferCount;
<>	144:ef7eb2e8f9f7	1822
<>	144:ef7eb2e8f9f7	1823	/* Clear ADDR flag */
<>	144:ef7eb2e8f9f7	1824	__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
<>	144:ef7eb2e8f9f7	1825
<>	144:ef7eb2e8f9f7	1826	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	1827	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	1828
<>	144:ef7eb2e8f9f7	1829	/* Note : The I2C interrupts must be enabled after unlocking current process
<>	144:ef7eb2e8f9f7	1830	to avoid the risk of I2C interrupt handle execution before current
<>	144:ef7eb2e8f9f7	1831	process unlock */
<>	144:ef7eb2e8f9f7	1832
<>	144:ef7eb2e8f9f7	1833	/* Enable EVT, BUF and ERR interrupt */
<>	144:ef7eb2e8f9f7	1834	__HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT \| I2C_IT_BUF \| I2C_IT_ERR);
<>	144:ef7eb2e8f9f7	1835
<>	144:ef7eb2e8f9f7	1836	return HAL_OK;
<>	144:ef7eb2e8f9f7	1837	}
<>	144:ef7eb2e8f9f7	1838	else
<>	144:ef7eb2e8f9f7	1839	{
<>	144:ef7eb2e8f9f7	1840	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	1841	}
<>	144:ef7eb2e8f9f7	1842	}
<>	144:ef7eb2e8f9f7	1843
<>	144:ef7eb2e8f9f7	1844	/**
<>	144:ef7eb2e8f9f7	1845	* @brief Enable the Address listen mode with Interrupt.
<>	144:ef7eb2e8f9f7	1846	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	1847	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	1848	* @retval HAL status
<>	144:ef7eb2e8f9f7	1849	*/
<>	144:ef7eb2e8f9f7	1850	HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c)
<>	144:ef7eb2e8f9f7	1851	{
<>	144:ef7eb2e8f9f7	1852	if(hi2c->State == HAL_I2C_STATE_READY)
<>	144:ef7eb2e8f9f7	1853	{
<>	144:ef7eb2e8f9f7	1854	hi2c->State = HAL_I2C_STATE_LISTEN;
<>	144:ef7eb2e8f9f7	1855
AnnaBridge	167:e84263d55307	1856	/* Check if the I2C is already enabled */
AnnaBridge	167:e84263d55307	1857	if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
AnnaBridge	167:e84263d55307	1858	{
AnnaBridge	167:e84263d55307	1859	/* Enable I2C peripheral */
AnnaBridge	167:e84263d55307	1860	__HAL_I2C_ENABLE(hi2c);
AnnaBridge	167:e84263d55307	1861	}
AnnaBridge	167:e84263d55307	1862
<>	144:ef7eb2e8f9f7	1863	/* Enable Address Acknowledge */
<>	144:ef7eb2e8f9f7	1864	hi2c->Instance->CR1 \|= I2C_CR1_ACK;
<>	144:ef7eb2e8f9f7	1865
<>	144:ef7eb2e8f9f7	1866	/* Enable EVT and ERR interrupt */
<>	144:ef7eb2e8f9f7	1867	__HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT \| I2C_IT_ERR);
AnnaBridge	167:e84263d55307	1868
<>	144:ef7eb2e8f9f7	1869	return HAL_OK;
<>	144:ef7eb2e8f9f7	1870	}
<>	144:ef7eb2e8f9f7	1871	else
<>	144:ef7eb2e8f9f7	1872	{
<>	144:ef7eb2e8f9f7	1873	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	1874	}
<>	144:ef7eb2e8f9f7	1875	}
<>	144:ef7eb2e8f9f7	1876
<>	144:ef7eb2e8f9f7	1877	/**
<>	144:ef7eb2e8f9f7	1878	* @brief Disable the Address listen mode with Interrupt.
<>	144:ef7eb2e8f9f7	1879	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	1880	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	1881	* @retval HAL status
<>	144:ef7eb2e8f9f7	1882	*/
<>	144:ef7eb2e8f9f7	1883	HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c)
<>	144:ef7eb2e8f9f7	1884	{
<>	144:ef7eb2e8f9f7	1885	/* Declaration of tmp to prevent undefined behavior of volatile usage */
<>	144:ef7eb2e8f9f7	1886	uint32_t tmp;
AnnaBridge	167:e84263d55307	1887
<>	144:ef7eb2e8f9f7	1888	/* Disable Address listen mode only if a transfer is not ongoing */
<>	144:ef7eb2e8f9f7	1889	if(hi2c->State == HAL_I2C_STATE_LISTEN)
<>	144:ef7eb2e8f9f7	1890	{
<>	144:ef7eb2e8f9f7	1891	tmp = (uint32_t)(hi2c->State) & I2C_STATE_MSK;
<>	144:ef7eb2e8f9f7	1892	hi2c->PreviousState = tmp \| (uint32_t)(hi2c->Mode);
<>	144:ef7eb2e8f9f7	1893	hi2c->State = HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	1894	hi2c->Mode = HAL_I2C_MODE_NONE;
AnnaBridge	167:e84263d55307	1895
<>	144:ef7eb2e8f9f7	1896	/* Disable Address Acknowledge */
<>	144:ef7eb2e8f9f7	1897	hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
<>	144:ef7eb2e8f9f7	1898
<>	144:ef7eb2e8f9f7	1899	/* Disable EVT and ERR interrupt */
<>	144:ef7eb2e8f9f7	1900	__HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT \| I2C_IT_ERR);
<>	144:ef7eb2e8f9f7	1901
<>	144:ef7eb2e8f9f7	1902	return HAL_OK;
<>	144:ef7eb2e8f9f7	1903	}
<>	144:ef7eb2e8f9f7	1904	else
<>	144:ef7eb2e8f9f7	1905	{
<>	144:ef7eb2e8f9f7	1906	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	1907	}
<>	144:ef7eb2e8f9f7	1908	}
<>	144:ef7eb2e8f9f7	1909
<>	144:ef7eb2e8f9f7	1910	/**
AnnaBridge	167:e84263d55307	1911	* @brief Transmit in master mode an amount of data in non-blocking mode with DMA
<>	144:ef7eb2e8f9f7	1912	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
AnnaBridge	167:e84263d55307	1913	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	1914	* @param DevAddress Target device address: The device 7 bits address value
<>	144:ef7eb2e8f9f7	1915	* in datasheet must be shift at right before call interface
<>	144:ef7eb2e8f9f7	1916	* @param pData Pointer to data buffer
<>	144:ef7eb2e8f9f7	1917	* @param Size Amount of data to be sent
<>	144:ef7eb2e8f9f7	1918	* @retval HAL status
<>	144:ef7eb2e8f9f7	1919	*/
<>	144:ef7eb2e8f9f7	1920	HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef hi2c, uint16_t DevAddress, uint8_t pData, uint16_t Size)
<>	144:ef7eb2e8f9f7	1921	{
<>	144:ef7eb2e8f9f7	1922	__IO uint32_t count = 0U;
<>	144:ef7eb2e8f9f7	1923
<>	144:ef7eb2e8f9f7	1924	if(hi2c->State == HAL_I2C_STATE_READY)
<>	144:ef7eb2e8f9f7	1925	{
<>	144:ef7eb2e8f9f7	1926	/* Wait until BUSY flag is reset */
<>	144:ef7eb2e8f9f7	1927	count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U);
<>	144:ef7eb2e8f9f7	1928	do
<>	144:ef7eb2e8f9f7	1929	{
<>	144:ef7eb2e8f9f7	1930	if(count-- == 0U)
<>	144:ef7eb2e8f9f7	1931	{
<>	144:ef7eb2e8f9f7	1932	hi2c->PreviousState = I2C_STATE_NONE;
<>	144:ef7eb2e8f9f7	1933	hi2c->State= HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	1934
<>	144:ef7eb2e8f9f7	1935	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	1936	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	1937
<>	144:ef7eb2e8f9f7	1938	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	1939	}
<>	144:ef7eb2e8f9f7	1940	}
<>	144:ef7eb2e8f9f7	1941	while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
<>	144:ef7eb2e8f9f7	1942
<>	144:ef7eb2e8f9f7	1943	/* Process Locked */
<>	144:ef7eb2e8f9f7	1944	__HAL_LOCK(hi2c);
<>	144:ef7eb2e8f9f7	1945
AnnaBridge	167:e84263d55307	1946	/* Check if the I2C is already enabled */
AnnaBridge	167:e84263d55307	1947	if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
AnnaBridge	167:e84263d55307	1948	{
AnnaBridge	167:e84263d55307	1949	/* Enable I2C peripheral */
AnnaBridge	167:e84263d55307	1950	__HAL_I2C_ENABLE(hi2c);
AnnaBridge	167:e84263d55307	1951	}
AnnaBridge	167:e84263d55307	1952
<>	144:ef7eb2e8f9f7	1953	/* Disable Pos */
<>	144:ef7eb2e8f9f7	1954	hi2c->Instance->CR1 &= ~I2C_CR1_POS;
<>	144:ef7eb2e8f9f7	1955
AnnaBridge	167:e84263d55307	1956	hi2c->State = HAL_I2C_STATE_BUSY_TX;
AnnaBridge	167:e84263d55307	1957	hi2c->Mode = HAL_I2C_MODE_MASTER;
<>	144:ef7eb2e8f9f7	1958	hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
<>	144:ef7eb2e8f9f7	1959
AnnaBridge	167:e84263d55307	1960	/* Prepare transfer parameters */
AnnaBridge	167:e84263d55307	1961	hi2c->pBuffPtr = pData;
AnnaBridge	167:e84263d55307	1962	hi2c->XferCount = Size;
<>	144:ef7eb2e8f9f7	1963	hi2c->XferOptions = I2C_NO_OPTION_FRAME;
AnnaBridge	167:e84263d55307	1964	hi2c->XferSize = hi2c->XferCount;
AnnaBridge	167:e84263d55307	1965	hi2c->Devaddress = DevAddress;
<>	144:ef7eb2e8f9f7	1966
<>	144:ef7eb2e8f9f7	1967	if(hi2c->XferSize > 0U)
<>	144:ef7eb2e8f9f7	1968	{
<>	144:ef7eb2e8f9f7	1969	/* Set the I2C DMA transfer complete callback */
<>	144:ef7eb2e8f9f7	1970	hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt;
<>	144:ef7eb2e8f9f7	1971
<>	144:ef7eb2e8f9f7	1972	/* Set the DMA error callback */
<>	144:ef7eb2e8f9f7	1973	hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
<>	144:ef7eb2e8f9f7	1974
<>	144:ef7eb2e8f9f7	1975	/* Set the unused DMA callbacks to NULL */
<>	144:ef7eb2e8f9f7	1976	hi2c->hdmatx->XferHalfCpltCallback = NULL;
<>	144:ef7eb2e8f9f7	1977	hi2c->hdmatx->XferM1CpltCallback = NULL;
<>	144:ef7eb2e8f9f7	1978	hi2c->hdmatx->XferM1HalfCpltCallback = NULL;
<>	144:ef7eb2e8f9f7	1979	hi2c->hdmatx->XferAbortCallback = NULL;
<>	144:ef7eb2e8f9f7	1980
<>	144:ef7eb2e8f9f7	1981	/* Enable the DMA Stream */
AnnaBridge	167:e84263d55307	1982	HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->DR, hi2c->XferSize);
AnnaBridge	167:e84263d55307	1983
AnnaBridge	167:e84263d55307	1984	/* Enable Acknowledge */
AnnaBridge	167:e84263d55307	1985	hi2c->Instance->CR1 \|= I2C_CR1_ACK;
AnnaBridge	167:e84263d55307	1986
AnnaBridge	167:e84263d55307	1987	/* Generate Start */
AnnaBridge	167:e84263d55307	1988	hi2c->Instance->CR1 \|= I2C_CR1_START;
AnnaBridge	167:e84263d55307	1989
AnnaBridge	167:e84263d55307	1990	/* Process Unlocked */
AnnaBridge	167:e84263d55307	1991	__HAL_UNLOCK(hi2c);
AnnaBridge	167:e84263d55307	1992
AnnaBridge	167:e84263d55307	1993	/* Note : The I2C interrupts must be enabled after unlocking current process
AnnaBridge	167:e84263d55307	1994	to avoid the risk of I2C interrupt handle execution before current
AnnaBridge	167:e84263d55307	1995	process unlock */
AnnaBridge	167:e84263d55307	1996
AnnaBridge	167:e84263d55307	1997	/* Enable EVT and ERR interrupt */
AnnaBridge	167:e84263d55307	1998	__HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT \| I2C_IT_ERR);
<>	144:ef7eb2e8f9f7	1999
<>	144:ef7eb2e8f9f7	2000	/* Enable DMA Request */
<>	144:ef7eb2e8f9f7	2001	hi2c->Instance->CR2 \|= I2C_CR2_DMAEN;
<>	144:ef7eb2e8f9f7	2002	}
<>	144:ef7eb2e8f9f7	2003	else
<>	144:ef7eb2e8f9f7	2004	{
AnnaBridge	167:e84263d55307	2005	/* Enable Acknowledge */
AnnaBridge	167:e84263d55307	2006	hi2c->Instance->CR1 \|= I2C_CR1_ACK;
AnnaBridge	167:e84263d55307	2007
AnnaBridge	167:e84263d55307	2008	/* Generate Start */
AnnaBridge	167:e84263d55307	2009	hi2c->Instance->CR1 \|= I2C_CR1_START;
AnnaBridge	167:e84263d55307	2010
AnnaBridge	167:e84263d55307	2011	/* Process Unlocked */
AnnaBridge	167:e84263d55307	2012	__HAL_UNLOCK(hi2c);
AnnaBridge	167:e84263d55307	2013
AnnaBridge	167:e84263d55307	2014	/* Note : The I2C interrupts must be enabled after unlocking current process
AnnaBridge	167:e84263d55307	2015	to avoid the risk of I2C interrupt handle execution before current
AnnaBridge	167:e84263d55307	2016	process unlock */
AnnaBridge	167:e84263d55307	2017
AnnaBridge	167:e84263d55307	2018	/* Enable EVT, BUF and ERR interrupt */
AnnaBridge	167:e84263d55307	2019	__HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT \| I2C_IT_BUF \| I2C_IT_ERR);
<>	144:ef7eb2e8f9f7	2020	}
<>	144:ef7eb2e8f9f7	2021
<>	144:ef7eb2e8f9f7	2022	return HAL_OK;
<>	144:ef7eb2e8f9f7	2023	}
<>	144:ef7eb2e8f9f7	2024	else
<>	144:ef7eb2e8f9f7	2025	{
<>	144:ef7eb2e8f9f7	2026	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	2027	}
<>	144:ef7eb2e8f9f7	2028	}
<>	144:ef7eb2e8f9f7	2029
<>	144:ef7eb2e8f9f7	2030	/**
AnnaBridge	167:e84263d55307	2031	* @brief Receive in master mode an amount of data in non-blocking mode with DMA
<>	144:ef7eb2e8f9f7	2032	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
AnnaBridge	167:e84263d55307	2033	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	2034	* @param DevAddress Target device address: The device 7 bits address value
<>	144:ef7eb2e8f9f7	2035	* in datasheet must be shift at right before call interface
<>	144:ef7eb2e8f9f7	2036	* @param pData Pointer to data buffer
<>	144:ef7eb2e8f9f7	2037	* @param Size Amount of data to be sent
<>	144:ef7eb2e8f9f7	2038	* @retval HAL status
<>	144:ef7eb2e8f9f7	2039	*/
<>	144:ef7eb2e8f9f7	2040	HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef hi2c, uint16_t DevAddress, uint8_t pData, uint16_t Size)
<>	144:ef7eb2e8f9f7	2041	{
<>	144:ef7eb2e8f9f7	2042	__IO uint32_t count = 0U;
AnnaBridge	167:e84263d55307	2043
<>	144:ef7eb2e8f9f7	2044	if(hi2c->State == HAL_I2C_STATE_READY)
<>	144:ef7eb2e8f9f7	2045	{
<>	144:ef7eb2e8f9f7	2046	/* Wait until BUSY flag is reset */
<>	144:ef7eb2e8f9f7	2047	count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U);
<>	144:ef7eb2e8f9f7	2048	do
<>	144:ef7eb2e8f9f7	2049	{
<>	144:ef7eb2e8f9f7	2050	if(count-- == 0U)
<>	144:ef7eb2e8f9f7	2051	{
<>	144:ef7eb2e8f9f7	2052	hi2c->PreviousState = I2C_STATE_NONE;
<>	144:ef7eb2e8f9f7	2053	hi2c->State= HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	2054
<>	144:ef7eb2e8f9f7	2055	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	2056	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	2057
<>	144:ef7eb2e8f9f7	2058	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	2059	}
<>	144:ef7eb2e8f9f7	2060	}
<>	144:ef7eb2e8f9f7	2061	while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
<>	144:ef7eb2e8f9f7	2062
<>	144:ef7eb2e8f9f7	2063	/* Process Locked */
<>	144:ef7eb2e8f9f7	2064	__HAL_LOCK(hi2c);
<>	144:ef7eb2e8f9f7	2065
AnnaBridge	167:e84263d55307	2066	/* Check if the I2C is already enabled */
AnnaBridge	167:e84263d55307	2067	if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
AnnaBridge	167:e84263d55307	2068	{
AnnaBridge	167:e84263d55307	2069	/* Enable I2C peripheral */
AnnaBridge	167:e84263d55307	2070	__HAL_I2C_ENABLE(hi2c);
AnnaBridge	167:e84263d55307	2071	}
AnnaBridge	167:e84263d55307	2072
<>	144:ef7eb2e8f9f7	2073	/* Disable Pos */
<>	144:ef7eb2e8f9f7	2074	hi2c->Instance->CR1 &= ~I2C_CR1_POS;
<>	144:ef7eb2e8f9f7	2075
AnnaBridge	167:e84263d55307	2076	hi2c->State = HAL_I2C_STATE_BUSY_RX;
AnnaBridge	167:e84263d55307	2077	hi2c->Mode = HAL_I2C_MODE_MASTER;
<>	144:ef7eb2e8f9f7	2078	hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
<>	144:ef7eb2e8f9f7	2079
AnnaBridge	167:e84263d55307	2080	/* Prepare transfer parameters */
AnnaBridge	167:e84263d55307	2081	hi2c->pBuffPtr = pData;
AnnaBridge	167:e84263d55307	2082	hi2c->XferCount = Size;
<>	144:ef7eb2e8f9f7	2083	hi2c->XferOptions = I2C_NO_OPTION_FRAME;
AnnaBridge	167:e84263d55307	2084	hi2c->XferSize = hi2c->XferCount;
AnnaBridge	167:e84263d55307	2085	hi2c->Devaddress = DevAddress;
<>	144:ef7eb2e8f9f7	2086
<>	144:ef7eb2e8f9f7	2087	if(hi2c->XferSize > 0U)
<>	144:ef7eb2e8f9f7	2088	{
<>	144:ef7eb2e8f9f7	2089	/* Set the I2C DMA transfer complete callback */
<>	144:ef7eb2e8f9f7	2090	hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt;
<>	144:ef7eb2e8f9f7	2091
<>	144:ef7eb2e8f9f7	2092	/* Set the DMA error callback */
<>	144:ef7eb2e8f9f7	2093	hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
<>	144:ef7eb2e8f9f7	2094
<>	144:ef7eb2e8f9f7	2095	/* Set the unused DMA callbacks to NULL */
<>	144:ef7eb2e8f9f7	2096	hi2c->hdmarx->XferHalfCpltCallback = NULL;
<>	144:ef7eb2e8f9f7	2097	hi2c->hdmarx->XferM1CpltCallback = NULL;
<>	144:ef7eb2e8f9f7	2098	hi2c->hdmarx->XferM1HalfCpltCallback = NULL;
<>	144:ef7eb2e8f9f7	2099	hi2c->hdmarx->XferAbortCallback = NULL;
<>	144:ef7eb2e8f9f7	2100
<>	144:ef7eb2e8f9f7	2101	/* Enable the DMA Stream */
AnnaBridge	167:e84263d55307	2102	HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize);
AnnaBridge	167:e84263d55307	2103
AnnaBridge	167:e84263d55307	2104	/* Enable Acknowledge */
AnnaBridge	167:e84263d55307	2105	hi2c->Instance->CR1 \|= I2C_CR1_ACK;
AnnaBridge	167:e84263d55307	2106
AnnaBridge	167:e84263d55307	2107	/* Generate Start */
AnnaBridge	167:e84263d55307	2108	hi2c->Instance->CR1 \|= I2C_CR1_START;
<>	144:ef7eb2e8f9f7	2109
<>	144:ef7eb2e8f9f7	2110	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	2111	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	2112
<>	144:ef7eb2e8f9f7	2113	/* Note : The I2C interrupts must be enabled after unlocking current process
<>	144:ef7eb2e8f9f7	2114	to avoid the risk of I2C interrupt handle execution before current
<>	144:ef7eb2e8f9f7	2115	process unlock */
AnnaBridge	167:e84263d55307	2116
AnnaBridge	167:e84263d55307	2117	/* Enable EVT and ERR interrupt */
AnnaBridge	167:e84263d55307	2118	__HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT \| I2C_IT_ERR);
<>	144:ef7eb2e8f9f7	2119
<>	144:ef7eb2e8f9f7	2120	/* Enable DMA Request */
<>	144:ef7eb2e8f9f7	2121	hi2c->Instance->CR2 \|= I2C_CR2_DMAEN;
<>	144:ef7eb2e8f9f7	2122	}
<>	144:ef7eb2e8f9f7	2123	else
<>	144:ef7eb2e8f9f7	2124	{
AnnaBridge	167:e84263d55307	2125	/* Enable Acknowledge */
AnnaBridge	167:e84263d55307	2126	hi2c->Instance->CR1 \|= I2C_CR1_ACK;
AnnaBridge	167:e84263d55307	2127
AnnaBridge	167:e84263d55307	2128	/* Generate Start */
AnnaBridge	167:e84263d55307	2129	hi2c->Instance->CR1 \|= I2C_CR1_START;
AnnaBridge	167:e84263d55307	2130
<>	144:ef7eb2e8f9f7	2131	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	2132	__HAL_UNLOCK(hi2c);
AnnaBridge	167:e84263d55307	2133
AnnaBridge	167:e84263d55307	2134	/* Note : The I2C interrupts must be enabled after unlocking current process
AnnaBridge	167:e84263d55307	2135	to avoid the risk of I2C interrupt handle execution before current
AnnaBridge	167:e84263d55307	2136	process unlock */
AnnaBridge	167:e84263d55307	2137
AnnaBridge	167:e84263d55307	2138	/* Enable EVT, BUF and ERR interrupt */
AnnaBridge	167:e84263d55307	2139	__HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT \| I2C_IT_BUF \| I2C_IT_ERR);
<>	144:ef7eb2e8f9f7	2140	}
<>	144:ef7eb2e8f9f7	2141
<>	144:ef7eb2e8f9f7	2142	return HAL_OK;
<>	144:ef7eb2e8f9f7	2143	}
<>	144:ef7eb2e8f9f7	2144	else
<>	144:ef7eb2e8f9f7	2145	{
<>	144:ef7eb2e8f9f7	2146	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	2147	}
<>	144:ef7eb2e8f9f7	2148	}
<>	144:ef7eb2e8f9f7	2149
<>	144:ef7eb2e8f9f7	2150	/**
<>	144:ef7eb2e8f9f7	2151	* @brief Abort a master I2C process communication with Interrupt.
<>	144:ef7eb2e8f9f7	2152	* @note This abort can be called only if state is ready
<>	144:ef7eb2e8f9f7	2153	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	2154	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	2155	* @param DevAddress Target device address: The device 7 bits address value
<>	144:ef7eb2e8f9f7	2156	* in datasheet must be shift at right before call interface
<>	144:ef7eb2e8f9f7	2157	* @retval HAL status
<>	144:ef7eb2e8f9f7	2158	*/
<>	144:ef7eb2e8f9f7	2159	HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress)
<>	144:ef7eb2e8f9f7	2160	{
AnnaBridge	167:e84263d55307	2161	/* Prevent unused argument(s) compilation warning */
AnnaBridge	167:e84263d55307	2162	UNUSED(DevAddress);
AnnaBridge	167:e84263d55307	2163
<>	144:ef7eb2e8f9f7	2164	/* Abort Master transfer during Receive or Transmit process */
<>	144:ef7eb2e8f9f7	2165	if(hi2c->Mode == HAL_I2C_MODE_MASTER)
<>	144:ef7eb2e8f9f7	2166	{
<>	144:ef7eb2e8f9f7	2167	/* Process Locked */
<>	144:ef7eb2e8f9f7	2168	__HAL_LOCK(hi2c);
<>	144:ef7eb2e8f9f7	2169
<>	144:ef7eb2e8f9f7	2170	hi2c->PreviousState = I2C_STATE_NONE;
<>	144:ef7eb2e8f9f7	2171	hi2c->State = HAL_I2C_STATE_ABORT;
<>	144:ef7eb2e8f9f7	2172
<>	144:ef7eb2e8f9f7	2173	/* Disable Acknowledge */
<>	144:ef7eb2e8f9f7	2174	hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
<>	144:ef7eb2e8f9f7	2175
<>	144:ef7eb2e8f9f7	2176	/* Generate Stop */
<>	144:ef7eb2e8f9f7	2177	hi2c->Instance->CR1 \|= I2C_CR1_STOP;
<>	144:ef7eb2e8f9f7	2178
<>	144:ef7eb2e8f9f7	2179	hi2c->XferCount = 0U;
<>	144:ef7eb2e8f9f7	2180
<>	144:ef7eb2e8f9f7	2181	/* Disable EVT, BUF and ERR interrupt */
<>	144:ef7eb2e8f9f7	2182	__HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT \| I2C_IT_BUF \| I2C_IT_ERR);
<>	144:ef7eb2e8f9f7	2183
<>	144:ef7eb2e8f9f7	2184	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	2185	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	2186
AnnaBridge	167:e84263d55307	2187	/* Call the corresponding callback to inform upper layer of End of Transfer */
AnnaBridge	167:e84263d55307	2188	I2C_ITError(hi2c);
<>	144:ef7eb2e8f9f7	2189
<>	144:ef7eb2e8f9f7	2190	return HAL_OK;
<>	144:ef7eb2e8f9f7	2191	}
<>	144:ef7eb2e8f9f7	2192	else
<>	144:ef7eb2e8f9f7	2193	{
<>	144:ef7eb2e8f9f7	2194	/* Wrong usage of abort function */
<>	144:ef7eb2e8f9f7	2195	/* This function should be used only in case of abort monitored by master device */
<>	144:ef7eb2e8f9f7	2196	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	2197	}
<>	144:ef7eb2e8f9f7	2198	}
<>	144:ef7eb2e8f9f7	2199
<>	144:ef7eb2e8f9f7	2200	/**
AnnaBridge	167:e84263d55307	2201	* @brief Transmit in slave mode an amount of data in non-blocking mode with DMA
<>	144:ef7eb2e8f9f7	2202	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
AnnaBridge	167:e84263d55307	2203	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	2204	* @param pData Pointer to data buffer
<>	144:ef7eb2e8f9f7	2205	* @param Size Amount of data to be sent
<>	144:ef7eb2e8f9f7	2206	* @retval HAL status
<>	144:ef7eb2e8f9f7	2207	*/
<>	144:ef7eb2e8f9f7	2208	HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef hi2c, uint8_t pData, uint16_t Size)
<>	144:ef7eb2e8f9f7	2209	{
<>	144:ef7eb2e8f9f7	2210	__IO uint32_t count = 0U;
<>	144:ef7eb2e8f9f7	2211
<>	144:ef7eb2e8f9f7	2212	if(hi2c->State == HAL_I2C_STATE_READY)
<>	144:ef7eb2e8f9f7	2213	{
<>	144:ef7eb2e8f9f7	2214	if((pData == NULL) \|\| (Size == 0U))
<>	144:ef7eb2e8f9f7	2215	{
<>	144:ef7eb2e8f9f7	2216	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	2217	}
<>	144:ef7eb2e8f9f7	2218
<>	144:ef7eb2e8f9f7	2219	/* Wait until BUSY flag is reset */
<>	144:ef7eb2e8f9f7	2220	count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U);
<>	144:ef7eb2e8f9f7	2221	do
<>	144:ef7eb2e8f9f7	2222	{
<>	144:ef7eb2e8f9f7	2223	if(count-- == 0U)
<>	144:ef7eb2e8f9f7	2224	{
<>	144:ef7eb2e8f9f7	2225	hi2c->PreviousState = I2C_STATE_NONE;
<>	144:ef7eb2e8f9f7	2226	hi2c->State= HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	2227
<>	144:ef7eb2e8f9f7	2228	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	2229	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	2230
<>	144:ef7eb2e8f9f7	2231	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	2232	}
<>	144:ef7eb2e8f9f7	2233	}
<>	144:ef7eb2e8f9f7	2234	while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
<>	144:ef7eb2e8f9f7	2235
<>	144:ef7eb2e8f9f7	2236	/* Process Locked */
<>	144:ef7eb2e8f9f7	2237	__HAL_LOCK(hi2c);
AnnaBridge	167:e84263d55307	2238
AnnaBridge	167:e84263d55307	2239	/* Check if the I2C is already enabled */
AnnaBridge	167:e84263d55307	2240	if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
AnnaBridge	167:e84263d55307	2241	{
AnnaBridge	167:e84263d55307	2242	/* Enable I2C peripheral */
AnnaBridge	167:e84263d55307	2243	__HAL_I2C_ENABLE(hi2c);
AnnaBridge	167:e84263d55307	2244	}
AnnaBridge	167:e84263d55307	2245
<>	144:ef7eb2e8f9f7	2246	/* Disable Pos */
<>	144:ef7eb2e8f9f7	2247	hi2c->Instance->CR1 &= ~I2C_CR1_POS;
<>	144:ef7eb2e8f9f7	2248
AnnaBridge	167:e84263d55307	2249	hi2c->State = HAL_I2C_STATE_BUSY_TX;
AnnaBridge	167:e84263d55307	2250	hi2c->Mode = HAL_I2C_MODE_SLAVE;
<>	144:ef7eb2e8f9f7	2251	hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
<>	144:ef7eb2e8f9f7	2252
AnnaBridge	167:e84263d55307	2253	/* Prepare transfer parameters */
AnnaBridge	167:e84263d55307	2254	hi2c->pBuffPtr = pData;
AnnaBridge	167:e84263d55307	2255	hi2c->XferCount = Size;
<>	144:ef7eb2e8f9f7	2256	hi2c->XferOptions = I2C_NO_OPTION_FRAME;
AnnaBridge	167:e84263d55307	2257	hi2c->XferSize = hi2c->XferCount;
<>	144:ef7eb2e8f9f7	2258
<>	144:ef7eb2e8f9f7	2259	/* Set the I2C DMA transfer complete callback */
<>	144:ef7eb2e8f9f7	2260	hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt;
<>	144:ef7eb2e8f9f7	2261
<>	144:ef7eb2e8f9f7	2262	/* Set the DMA error callback */
<>	144:ef7eb2e8f9f7	2263	hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
<>	144:ef7eb2e8f9f7	2264
<>	144:ef7eb2e8f9f7	2265	/* Set the unused DMA callbacks to NULL */
<>	144:ef7eb2e8f9f7	2266	hi2c->hdmatx->XferHalfCpltCallback = NULL;
<>	144:ef7eb2e8f9f7	2267	hi2c->hdmatx->XferM1CpltCallback = NULL;
<>	144:ef7eb2e8f9f7	2268	hi2c->hdmatx->XferM1HalfCpltCallback = NULL;
<>	144:ef7eb2e8f9f7	2269	hi2c->hdmatx->XferAbortCallback = NULL;
<>	144:ef7eb2e8f9f7	2270
<>	144:ef7eb2e8f9f7	2271	/* Enable the DMA Stream */
AnnaBridge	167:e84263d55307	2272	HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->DR, hi2c->XferSize);
<>	144:ef7eb2e8f9f7	2273
<>	144:ef7eb2e8f9f7	2274	/* Enable Address Acknowledge */
<>	144:ef7eb2e8f9f7	2275	hi2c->Instance->CR1 \|= I2C_CR1_ACK;
<>	144:ef7eb2e8f9f7	2276
<>	144:ef7eb2e8f9f7	2277	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	2278	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	2279
<>	144:ef7eb2e8f9f7	2280	/* Note : The I2C interrupts must be enabled after unlocking current process
<>	144:ef7eb2e8f9f7	2281	to avoid the risk of I2C interrupt handle execution before current
<>	144:ef7eb2e8f9f7	2282	process unlock */
AnnaBridge	167:e84263d55307	2283	/* Enable EVT and ERR interrupt */
AnnaBridge	167:e84263d55307	2284	__HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT \| I2C_IT_ERR);
AnnaBridge	167:e84263d55307	2285
AnnaBridge	167:e84263d55307	2286	/* Enable DMA Request */
AnnaBridge	167:e84263d55307	2287	hi2c->Instance->CR2 \|= I2C_CR2_DMAEN;
<>	144:ef7eb2e8f9f7	2288
<>	144:ef7eb2e8f9f7	2289	return HAL_OK;
<>	144:ef7eb2e8f9f7	2290	}
<>	144:ef7eb2e8f9f7	2291	else
<>	144:ef7eb2e8f9f7	2292	{
<>	144:ef7eb2e8f9f7	2293	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	2294	}
<>	144:ef7eb2e8f9f7	2295	}
<>	144:ef7eb2e8f9f7	2296
<>	144:ef7eb2e8f9f7	2297	/**
AnnaBridge	167:e84263d55307	2298	* @brief Receive in slave mode an amount of data in non-blocking mode with DMA
<>	144:ef7eb2e8f9f7	2299	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
AnnaBridge	167:e84263d55307	2300	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	2301	* @param pData Pointer to data buffer
<>	144:ef7eb2e8f9f7	2302	* @param Size Amount of data to be sent
<>	144:ef7eb2e8f9f7	2303	* @retval HAL status
<>	144:ef7eb2e8f9f7	2304	*/
<>	144:ef7eb2e8f9f7	2305	HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef hi2c, uint8_t pData, uint16_t Size)
<>	144:ef7eb2e8f9f7	2306	{
<>	144:ef7eb2e8f9f7	2307	__IO uint32_t count = 0U;
<>	144:ef7eb2e8f9f7	2308
<>	144:ef7eb2e8f9f7	2309	if(hi2c->State == HAL_I2C_STATE_READY)
<>	144:ef7eb2e8f9f7	2310	{
<>	144:ef7eb2e8f9f7	2311	if((pData == NULL) \|\| (Size == 0U))
<>	144:ef7eb2e8f9f7	2312	{
<>	144:ef7eb2e8f9f7	2313	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	2314	}
<>	144:ef7eb2e8f9f7	2315
<>	144:ef7eb2e8f9f7	2316	/* Wait until BUSY flag is reset */
<>	144:ef7eb2e8f9f7	2317	count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U);
<>	144:ef7eb2e8f9f7	2318	do
<>	144:ef7eb2e8f9f7	2319	{
<>	144:ef7eb2e8f9f7	2320	if(count-- == 0U)
<>	144:ef7eb2e8f9f7	2321	{
<>	144:ef7eb2e8f9f7	2322	hi2c->PreviousState = I2C_STATE_NONE;
<>	144:ef7eb2e8f9f7	2323	hi2c->State= HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	2324
<>	144:ef7eb2e8f9f7	2325	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	2326	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	2327
<>	144:ef7eb2e8f9f7	2328	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	2329	}
<>	144:ef7eb2e8f9f7	2330	}
<>	144:ef7eb2e8f9f7	2331	while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
<>	144:ef7eb2e8f9f7	2332
<>	144:ef7eb2e8f9f7	2333	/* Process Locked */
<>	144:ef7eb2e8f9f7	2334	__HAL_LOCK(hi2c);
AnnaBridge	167:e84263d55307	2335
AnnaBridge	167:e84263d55307	2336	/* Check if the I2C is already enabled */
AnnaBridge	167:e84263d55307	2337	if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
AnnaBridge	167:e84263d55307	2338	{
AnnaBridge	167:e84263d55307	2339	/* Enable I2C peripheral */
AnnaBridge	167:e84263d55307	2340	__HAL_I2C_ENABLE(hi2c);
AnnaBridge	167:e84263d55307	2341	}
AnnaBridge	167:e84263d55307	2342
<>	144:ef7eb2e8f9f7	2343	/* Disable Pos */
<>	144:ef7eb2e8f9f7	2344	hi2c->Instance->CR1 &= ~I2C_CR1_POS;
<>	144:ef7eb2e8f9f7	2345
AnnaBridge	167:e84263d55307	2346	hi2c->State = HAL_I2C_STATE_BUSY_RX;
AnnaBridge	167:e84263d55307	2347	hi2c->Mode = HAL_I2C_MODE_SLAVE;
<>	144:ef7eb2e8f9f7	2348	hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
<>	144:ef7eb2e8f9f7	2349
AnnaBridge	167:e84263d55307	2350	/* Prepare transfer parameters */
AnnaBridge	167:e84263d55307	2351	hi2c->pBuffPtr = pData;
AnnaBridge	167:e84263d55307	2352	hi2c->XferCount = Size;
<>	144:ef7eb2e8f9f7	2353	hi2c->XferOptions = I2C_NO_OPTION_FRAME;
AnnaBridge	167:e84263d55307	2354	hi2c->XferSize = hi2c->XferCount;
AnnaBridge	167:e84263d55307	2355
<>	144:ef7eb2e8f9f7	2356	/* Set the I2C DMA transfer complete callback */
<>	144:ef7eb2e8f9f7	2357	hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt;
<>	144:ef7eb2e8f9f7	2358
<>	144:ef7eb2e8f9f7	2359	/* Set the DMA error callback */
<>	144:ef7eb2e8f9f7	2360	hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
AnnaBridge	167:e84263d55307	2361
<>	144:ef7eb2e8f9f7	2362	/* Set the unused DMA callbacks to NULL */
<>	144:ef7eb2e8f9f7	2363	hi2c->hdmarx->XferHalfCpltCallback = NULL;
<>	144:ef7eb2e8f9f7	2364	hi2c->hdmarx->XferM1CpltCallback = NULL;
<>	144:ef7eb2e8f9f7	2365	hi2c->hdmarx->XferM1HalfCpltCallback = NULL;
<>	144:ef7eb2e8f9f7	2366	hi2c->hdmarx->XferAbortCallback = NULL;
<>	144:ef7eb2e8f9f7	2367
<>	144:ef7eb2e8f9f7	2368	/* Enable the DMA Stream */
AnnaBridge	167:e84263d55307	2369	HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize);
<>	144:ef7eb2e8f9f7	2370
<>	144:ef7eb2e8f9f7	2371	/* Enable Address Acknowledge */
<>	144:ef7eb2e8f9f7	2372	hi2c->Instance->CR1 \|= I2C_CR1_ACK;
<>	144:ef7eb2e8f9f7	2373
<>	144:ef7eb2e8f9f7	2374	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	2375	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	2376
<>	144:ef7eb2e8f9f7	2377	/* Note : The I2C interrupts must be enabled after unlocking current process
<>	144:ef7eb2e8f9f7	2378	to avoid the risk of I2C interrupt handle execution before current
<>	144:ef7eb2e8f9f7	2379	process unlock */
AnnaBridge	167:e84263d55307	2380	/* Enable EVT and ERR interrupt */
AnnaBridge	167:e84263d55307	2381	__HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT \| I2C_IT_ERR);
AnnaBridge	167:e84263d55307	2382
AnnaBridge	167:e84263d55307	2383	/* Enable DMA Request */
AnnaBridge	167:e84263d55307	2384	hi2c->Instance->CR2 \|= I2C_CR2_DMAEN;
<>	144:ef7eb2e8f9f7	2385
<>	144:ef7eb2e8f9f7	2386	return HAL_OK;
<>	144:ef7eb2e8f9f7	2387	}
<>	144:ef7eb2e8f9f7	2388	else
<>	144:ef7eb2e8f9f7	2389	{
<>	144:ef7eb2e8f9f7	2390	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	2391	}
<>	144:ef7eb2e8f9f7	2392	}
<>	144:ef7eb2e8f9f7	2393	/**
<>	144:ef7eb2e8f9f7	2394	* @brief Write an amount of data in blocking mode to a specific memory address
<>	144:ef7eb2e8f9f7	2395	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
AnnaBridge	167:e84263d55307	2396	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	2397	* @param DevAddress Target device address
<>	144:ef7eb2e8f9f7	2398	* @param MemAddress Internal memory address
<>	144:ef7eb2e8f9f7	2399	* @param MemAddSize Size of internal memory address
<>	144:ef7eb2e8f9f7	2400	* @param pData Pointer to data buffer
<>	144:ef7eb2e8f9f7	2401	* @param Size Amount of data to be sent
<>	144:ef7eb2e8f9f7	2402	* @param Timeout Timeout duration
<>	144:ef7eb2e8f9f7	2403	* @retval HAL status
<>	144:ef7eb2e8f9f7	2404	*/
<>	144:ef7eb2e8f9f7	2405	HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t pData, uint16_t Size, uint32_t Timeout)
<>	144:ef7eb2e8f9f7	2406	{
<>	144:ef7eb2e8f9f7	2407	uint32_t tickstart = 0x00U;
<>	144:ef7eb2e8f9f7	2408
<>	144:ef7eb2e8f9f7	2409	/* Init tickstart for timeout management*/
<>	144:ef7eb2e8f9f7	2410	tickstart = HAL_GetTick();
<>	144:ef7eb2e8f9f7	2411
<>	144:ef7eb2e8f9f7	2412	/* Check the parameters */
<>	144:ef7eb2e8f9f7	2413	assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
<>	144:ef7eb2e8f9f7	2414
<>	144:ef7eb2e8f9f7	2415	if(hi2c->State == HAL_I2C_STATE_READY)
<>	144:ef7eb2e8f9f7	2416	{
<>	144:ef7eb2e8f9f7	2417	/* Wait until BUSY flag is reset */
<>	144:ef7eb2e8f9f7	2418	if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	2419	{
<>	144:ef7eb2e8f9f7	2420	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	2421	}
<>	144:ef7eb2e8f9f7	2422
<>	144:ef7eb2e8f9f7	2423	/* Process Locked */
<>	144:ef7eb2e8f9f7	2424	__HAL_LOCK(hi2c);
<>	144:ef7eb2e8f9f7	2425
AnnaBridge	167:e84263d55307	2426	/* Check if the I2C is already enabled */
AnnaBridge	167:e84263d55307	2427	if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
AnnaBridge	167:e84263d55307	2428	{
AnnaBridge	167:e84263d55307	2429	/* Enable I2C peripheral */
AnnaBridge	167:e84263d55307	2430	__HAL_I2C_ENABLE(hi2c);
AnnaBridge	167:e84263d55307	2431	}
AnnaBridge	167:e84263d55307	2432
<>	144:ef7eb2e8f9f7	2433	/* Disable Pos */
<>	144:ef7eb2e8f9f7	2434	hi2c->Instance->CR1 &= ~I2C_CR1_POS;
<>	144:ef7eb2e8f9f7	2435
AnnaBridge	167:e84263d55307	2436	hi2c->State = HAL_I2C_STATE_BUSY_TX;
AnnaBridge	167:e84263d55307	2437	hi2c->Mode = HAL_I2C_MODE_MEM;
<>	144:ef7eb2e8f9f7	2438	hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
AnnaBridge	167:e84263d55307	2439
AnnaBridge	167:e84263d55307	2440	/* Prepare transfer parameters */
AnnaBridge	167:e84263d55307	2441	hi2c->pBuffPtr = pData;
AnnaBridge	167:e84263d55307	2442	hi2c->XferCount = Size;
<>	144:ef7eb2e8f9f7	2443	hi2c->XferOptions = I2C_NO_OPTION_FRAME;
AnnaBridge	167:e84263d55307	2444	hi2c->XferSize = hi2c->XferCount;
<>	144:ef7eb2e8f9f7	2445
<>	144:ef7eb2e8f9f7	2446	/* Send Slave Address and Memory Address */
<>	144:ef7eb2e8f9f7	2447	if(I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	2448	{
<>	144:ef7eb2e8f9f7	2449	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
<>	144:ef7eb2e8f9f7	2450	{
<>	144:ef7eb2e8f9f7	2451	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	2452	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	2453	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	2454	}
<>	144:ef7eb2e8f9f7	2455	else
<>	144:ef7eb2e8f9f7	2456	{
<>	144:ef7eb2e8f9f7	2457	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	2458	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	2459	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	2460	}
<>	144:ef7eb2e8f9f7	2461	}
<>	144:ef7eb2e8f9f7	2462
AnnaBridge	167:e84263d55307	2463	while(hi2c->XferSize > 0U)
<>	144:ef7eb2e8f9f7	2464	{
<>	144:ef7eb2e8f9f7	2465	/* Wait until TXE flag is set */
<>	144:ef7eb2e8f9f7	2466	if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	2467	{
<>	144:ef7eb2e8f9f7	2468	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
<>	144:ef7eb2e8f9f7	2469	{
<>	144:ef7eb2e8f9f7	2470	/* Generate Stop */
<>	144:ef7eb2e8f9f7	2471	hi2c->Instance->CR1 \|= I2C_CR1_STOP;
<>	144:ef7eb2e8f9f7	2472	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	2473	}
<>	144:ef7eb2e8f9f7	2474	else
<>	144:ef7eb2e8f9f7	2475	{
<>	144:ef7eb2e8f9f7	2476	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	2477	}
<>	144:ef7eb2e8f9f7	2478	}
<>	144:ef7eb2e8f9f7	2479
<>	144:ef7eb2e8f9f7	2480	/* Write data to DR */
AnnaBridge	167:e84263d55307	2481	hi2c->Instance->DR = (*hi2c->pBuffPtr++);
AnnaBridge	167:e84263d55307	2482	hi2c->XferSize--;
AnnaBridge	167:e84263d55307	2483	hi2c->XferCount--;
AnnaBridge	167:e84263d55307	2484
AnnaBridge	167:e84263d55307	2485	if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (hi2c->XferSize != 0U))
<>	144:ef7eb2e8f9f7	2486	{
<>	144:ef7eb2e8f9f7	2487	/* Write data to DR */
AnnaBridge	167:e84263d55307	2488	hi2c->Instance->DR = (*hi2c->pBuffPtr++);
AnnaBridge	167:e84263d55307	2489	hi2c->XferSize--;
AnnaBridge	167:e84263d55307	2490	hi2c->XferCount--;
<>	144:ef7eb2e8f9f7	2491	}
<>	144:ef7eb2e8f9f7	2492	}
<>	144:ef7eb2e8f9f7	2493
<>	144:ef7eb2e8f9f7	2494	/* Wait until BTF flag is set */
<>	144:ef7eb2e8f9f7	2495	if(I2C_WaitOnBTFFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	2496	{
<>	144:ef7eb2e8f9f7	2497	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
<>	144:ef7eb2e8f9f7	2498	{
<>	144:ef7eb2e8f9f7	2499	/* Generate Stop */
<>	144:ef7eb2e8f9f7	2500	hi2c->Instance->CR1 \|= I2C_CR1_STOP;
<>	144:ef7eb2e8f9f7	2501	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	2502	}
<>	144:ef7eb2e8f9f7	2503	else
<>	144:ef7eb2e8f9f7	2504	{
<>	144:ef7eb2e8f9f7	2505	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	2506	}
<>	144:ef7eb2e8f9f7	2507	}
<>	144:ef7eb2e8f9f7	2508
<>	144:ef7eb2e8f9f7	2509	/* Generate Stop */
<>	144:ef7eb2e8f9f7	2510	hi2c->Instance->CR1 \|= I2C_CR1_STOP;
<>	144:ef7eb2e8f9f7	2511
<>	144:ef7eb2e8f9f7	2512	hi2c->State = HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	2513	hi2c->Mode = HAL_I2C_MODE_NONE;
<>	144:ef7eb2e8f9f7	2514
<>	144:ef7eb2e8f9f7	2515	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	2516	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	2517
<>	144:ef7eb2e8f9f7	2518	return HAL_OK;
<>	144:ef7eb2e8f9f7	2519	}
<>	144:ef7eb2e8f9f7	2520	else
<>	144:ef7eb2e8f9f7	2521	{
<>	144:ef7eb2e8f9f7	2522	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	2523	}
<>	144:ef7eb2e8f9f7	2524	}
<>	144:ef7eb2e8f9f7	2525
<>	144:ef7eb2e8f9f7	2526	/**
<>	144:ef7eb2e8f9f7	2527	* @brief Read an amount of data in blocking mode from a specific memory address
<>	144:ef7eb2e8f9f7	2528	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
AnnaBridge	167:e84263d55307	2529	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	2530	* @param DevAddress Target device address
<>	144:ef7eb2e8f9f7	2531	* @param MemAddress Internal memory address
<>	144:ef7eb2e8f9f7	2532	* @param MemAddSize Size of internal memory address
<>	144:ef7eb2e8f9f7	2533	* @param pData Pointer to data buffer
<>	144:ef7eb2e8f9f7	2534	* @param Size Amount of data to be sent
<>	144:ef7eb2e8f9f7	2535	* @param Timeout Timeout duration
<>	144:ef7eb2e8f9f7	2536	* @retval HAL status
<>	144:ef7eb2e8f9f7	2537	*/
<>	144:ef7eb2e8f9f7	2538	HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t pData, uint16_t Size, uint32_t Timeout)
<>	144:ef7eb2e8f9f7	2539	{
<>	144:ef7eb2e8f9f7	2540	uint32_t tickstart = 0x00U;
<>	144:ef7eb2e8f9f7	2541
<>	144:ef7eb2e8f9f7	2542	/* Init tickstart for timeout management*/
<>	144:ef7eb2e8f9f7	2543	tickstart = HAL_GetTick();
<>	144:ef7eb2e8f9f7	2544
<>	144:ef7eb2e8f9f7	2545	/* Check the parameters */
<>	144:ef7eb2e8f9f7	2546	assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
<>	144:ef7eb2e8f9f7	2547
<>	144:ef7eb2e8f9f7	2548	if(hi2c->State == HAL_I2C_STATE_READY)
<>	144:ef7eb2e8f9f7	2549	{
<>	144:ef7eb2e8f9f7	2550	/* Wait until BUSY flag is reset */
<>	144:ef7eb2e8f9f7	2551	if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	2552	{
<>	144:ef7eb2e8f9f7	2553	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	2554	}
<>	144:ef7eb2e8f9f7	2555
<>	144:ef7eb2e8f9f7	2556	/* Process Locked */
<>	144:ef7eb2e8f9f7	2557	__HAL_LOCK(hi2c);
<>	144:ef7eb2e8f9f7	2558
AnnaBridge	167:e84263d55307	2559	/* Check if the I2C is already enabled */
AnnaBridge	167:e84263d55307	2560	if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
AnnaBridge	167:e84263d55307	2561	{
AnnaBridge	167:e84263d55307	2562	/* Enable I2C peripheral */
AnnaBridge	167:e84263d55307	2563	__HAL_I2C_ENABLE(hi2c);
AnnaBridge	167:e84263d55307	2564	}
AnnaBridge	167:e84263d55307	2565
<>	144:ef7eb2e8f9f7	2566	/* Disable Pos */
<>	144:ef7eb2e8f9f7	2567	hi2c->Instance->CR1 &= ~I2C_CR1_POS;
<>	144:ef7eb2e8f9f7	2568
AnnaBridge	167:e84263d55307	2569	hi2c->State = HAL_I2C_STATE_BUSY_RX;
AnnaBridge	167:e84263d55307	2570	hi2c->Mode = HAL_I2C_MODE_MEM;
<>	144:ef7eb2e8f9f7	2571	hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
AnnaBridge	167:e84263d55307	2572
AnnaBridge	167:e84263d55307	2573	/* Prepare transfer parameters */
AnnaBridge	167:e84263d55307	2574	hi2c->pBuffPtr = pData;
AnnaBridge	167:e84263d55307	2575	hi2c->XferCount = Size;
<>	144:ef7eb2e8f9f7	2576	hi2c->XferOptions = I2C_NO_OPTION_FRAME;
AnnaBridge	167:e84263d55307	2577	hi2c->XferSize = hi2c->XferCount;
AnnaBridge	167:e84263d55307	2578
<>	144:ef7eb2e8f9f7	2579	/* Send Slave Address and Memory Address */
<>	144:ef7eb2e8f9f7	2580	if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	2581	{
<>	144:ef7eb2e8f9f7	2582	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
<>	144:ef7eb2e8f9f7	2583	{
<>	144:ef7eb2e8f9f7	2584	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	2585	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	2586	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	2587	}
<>	144:ef7eb2e8f9f7	2588	else
<>	144:ef7eb2e8f9f7	2589	{
<>	144:ef7eb2e8f9f7	2590	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	2591	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	2592	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	2593	}
<>	144:ef7eb2e8f9f7	2594	}
<>	144:ef7eb2e8f9f7	2595
AnnaBridge	167:e84263d55307	2596	if(hi2c->XferSize == 0U)
<>	144:ef7eb2e8f9f7	2597	{
<>	144:ef7eb2e8f9f7	2598	/* Clear ADDR flag */
<>	144:ef7eb2e8f9f7	2599	__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
<>	144:ef7eb2e8f9f7	2600
<>	144:ef7eb2e8f9f7	2601	/* Generate Stop */
<>	144:ef7eb2e8f9f7	2602	hi2c->Instance->CR1 \|= I2C_CR1_STOP;
<>	144:ef7eb2e8f9f7	2603	}
AnnaBridge	167:e84263d55307	2604	else if(hi2c->XferSize == 1U)
<>	144:ef7eb2e8f9f7	2605	{
<>	144:ef7eb2e8f9f7	2606	/* Disable Acknowledge */
<>	144:ef7eb2e8f9f7	2607	hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
<>	144:ef7eb2e8f9f7	2608
<>	144:ef7eb2e8f9f7	2609	/* Clear ADDR flag */
<>	144:ef7eb2e8f9f7	2610	__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
<>	144:ef7eb2e8f9f7	2611
<>	144:ef7eb2e8f9f7	2612	/* Generate Stop */
<>	144:ef7eb2e8f9f7	2613	hi2c->Instance->CR1 \|= I2C_CR1_STOP;
<>	144:ef7eb2e8f9f7	2614	}
AnnaBridge	167:e84263d55307	2615	else if(hi2c->XferSize == 2U)
<>	144:ef7eb2e8f9f7	2616	{
<>	144:ef7eb2e8f9f7	2617	/* Disable Acknowledge */
<>	144:ef7eb2e8f9f7	2618	hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
<>	144:ef7eb2e8f9f7	2619
<>	144:ef7eb2e8f9f7	2620	/* Enable Pos */
<>	144:ef7eb2e8f9f7	2621	hi2c->Instance->CR1 \|= I2C_CR1_POS;
<>	144:ef7eb2e8f9f7	2622
<>	144:ef7eb2e8f9f7	2623	/* Clear ADDR flag */
<>	144:ef7eb2e8f9f7	2624	__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
<>	144:ef7eb2e8f9f7	2625	}
<>	144:ef7eb2e8f9f7	2626	else
<>	144:ef7eb2e8f9f7	2627	{
<>	144:ef7eb2e8f9f7	2628	/* Clear ADDR flag */
<>	144:ef7eb2e8f9f7	2629	__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
<>	144:ef7eb2e8f9f7	2630	}
<>	144:ef7eb2e8f9f7	2631
AnnaBridge	167:e84263d55307	2632	while(hi2c->XferSize > 0U)
<>	144:ef7eb2e8f9f7	2633	{
AnnaBridge	167:e84263d55307	2634	if(hi2c->XferSize <= 3U)
<>	144:ef7eb2e8f9f7	2635	{
<>	144:ef7eb2e8f9f7	2636	/* One byte */
AnnaBridge	167:e84263d55307	2637	if(hi2c->XferSize== 1U)
<>	144:ef7eb2e8f9f7	2638	{
<>	144:ef7eb2e8f9f7	2639	/* Wait until RXNE flag is set */
<>	144:ef7eb2e8f9f7	2640	if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	2641	{
<>	144:ef7eb2e8f9f7	2642	if(hi2c->ErrorCode == HAL_I2C_ERROR_TIMEOUT)
<>	144:ef7eb2e8f9f7	2643	{
<>	144:ef7eb2e8f9f7	2644	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	2645	}
<>	144:ef7eb2e8f9f7	2646	else
<>	144:ef7eb2e8f9f7	2647	{
<>	144:ef7eb2e8f9f7	2648	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	2649	}
<>	144:ef7eb2e8f9f7	2650	}
<>	144:ef7eb2e8f9f7	2651
<>	144:ef7eb2e8f9f7	2652	/* Read data from DR */
AnnaBridge	167:e84263d55307	2653	(*hi2c->pBuffPtr++) = hi2c->Instance->DR;
AnnaBridge	167:e84263d55307	2654	hi2c->XferSize--;
AnnaBridge	167:e84263d55307	2655	hi2c->XferCount--;
<>	144:ef7eb2e8f9f7	2656	}
<>	144:ef7eb2e8f9f7	2657	/* Two bytes */
AnnaBridge	167:e84263d55307	2658	else if(hi2c->XferSize == 2U)
<>	144:ef7eb2e8f9f7	2659	{
<>	144:ef7eb2e8f9f7	2660	/* Wait until BTF flag is set */
<>	144:ef7eb2e8f9f7	2661	if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	2662	{
<>	144:ef7eb2e8f9f7	2663	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	2664	}
<>	144:ef7eb2e8f9f7	2665
<>	144:ef7eb2e8f9f7	2666	/* Generate Stop */
<>	144:ef7eb2e8f9f7	2667	hi2c->Instance->CR1 \|= I2C_CR1_STOP;
<>	144:ef7eb2e8f9f7	2668
<>	144:ef7eb2e8f9f7	2669	/* Read data from DR */
AnnaBridge	167:e84263d55307	2670	(*hi2c->pBuffPtr++) = hi2c->Instance->DR;
AnnaBridge	167:e84263d55307	2671	hi2c->XferSize--;
AnnaBridge	167:e84263d55307	2672	hi2c->XferCount--;
<>	144:ef7eb2e8f9f7	2673
<>	144:ef7eb2e8f9f7	2674	/* Read data from DR */
AnnaBridge	167:e84263d55307	2675	(*hi2c->pBuffPtr++) = hi2c->Instance->DR;
AnnaBridge	167:e84263d55307	2676	hi2c->XferSize--;
AnnaBridge	167:e84263d55307	2677	hi2c->XferCount--;
<>	144:ef7eb2e8f9f7	2678	}
<>	144:ef7eb2e8f9f7	2679	/* 3 Last bytes */
<>	144:ef7eb2e8f9f7	2680	else
<>	144:ef7eb2e8f9f7	2681	{
<>	144:ef7eb2e8f9f7	2682	/* Wait until BTF flag is set */
<>	144:ef7eb2e8f9f7	2683	if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	2684	{
<>	144:ef7eb2e8f9f7	2685	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	2686	}
<>	144:ef7eb2e8f9f7	2687
<>	144:ef7eb2e8f9f7	2688	/* Disable Acknowledge */
<>	144:ef7eb2e8f9f7	2689	hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
<>	144:ef7eb2e8f9f7	2690
<>	144:ef7eb2e8f9f7	2691	/* Read data from DR */
AnnaBridge	167:e84263d55307	2692	(*hi2c->pBuffPtr++) = hi2c->Instance->DR;
AnnaBridge	167:e84263d55307	2693	hi2c->XferSize--;
AnnaBridge	167:e84263d55307	2694	hi2c->XferCount--;
<>	144:ef7eb2e8f9f7	2695
<>	144:ef7eb2e8f9f7	2696	/* Wait until BTF flag is set */
<>	144:ef7eb2e8f9f7	2697	if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	2698	{
<>	144:ef7eb2e8f9f7	2699	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	2700	}
<>	144:ef7eb2e8f9f7	2701
<>	144:ef7eb2e8f9f7	2702	/* Generate Stop */
<>	144:ef7eb2e8f9f7	2703	hi2c->Instance->CR1 \|= I2C_CR1_STOP;
<>	144:ef7eb2e8f9f7	2704
<>	144:ef7eb2e8f9f7	2705	/* Read data from DR */
AnnaBridge	167:e84263d55307	2706	(*hi2c->pBuffPtr++) = hi2c->Instance->DR;
AnnaBridge	167:e84263d55307	2707	hi2c->XferSize--;
AnnaBridge	167:e84263d55307	2708	hi2c->XferCount--;
<>	144:ef7eb2e8f9f7	2709
<>	144:ef7eb2e8f9f7	2710	/* Read data from DR */
AnnaBridge	167:e84263d55307	2711	(*hi2c->pBuffPtr++) = hi2c->Instance->DR;
AnnaBridge	167:e84263d55307	2712	hi2c->XferSize--;
AnnaBridge	167:e84263d55307	2713	hi2c->XferCount--;
<>	144:ef7eb2e8f9f7	2714	}
<>	144:ef7eb2e8f9f7	2715	}
<>	144:ef7eb2e8f9f7	2716	else
<>	144:ef7eb2e8f9f7	2717	{
<>	144:ef7eb2e8f9f7	2718	/* Wait until RXNE flag is set */
AnnaBridge	167:e84263d55307	2719	if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	2720	{
<>	144:ef7eb2e8f9f7	2721	if(hi2c->ErrorCode == HAL_I2C_ERROR_TIMEOUT)
<>	144:ef7eb2e8f9f7	2722	{
<>	144:ef7eb2e8f9f7	2723	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	2724	}
<>	144:ef7eb2e8f9f7	2725	else
<>	144:ef7eb2e8f9f7	2726	{
<>	144:ef7eb2e8f9f7	2727	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	2728	}
<>	144:ef7eb2e8f9f7	2729	}
<>	144:ef7eb2e8f9f7	2730
<>	144:ef7eb2e8f9f7	2731	/* Read data from DR */
AnnaBridge	167:e84263d55307	2732	(*hi2c->pBuffPtr++) = hi2c->Instance->DR;
AnnaBridge	167:e84263d55307	2733	hi2c->XferSize--;
AnnaBridge	167:e84263d55307	2734	hi2c->XferCount--;
<>	144:ef7eb2e8f9f7	2735
<>	144:ef7eb2e8f9f7	2736	if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET)
<>	144:ef7eb2e8f9f7	2737	{
<>	144:ef7eb2e8f9f7	2738	/* Read data from DR */
AnnaBridge	167:e84263d55307	2739	(*hi2c->pBuffPtr++) = hi2c->Instance->DR;
AnnaBridge	167:e84263d55307	2740	hi2c->XferSize--;
AnnaBridge	167:e84263d55307	2741	hi2c->XferCount--;
<>	144:ef7eb2e8f9f7	2742	}
<>	144:ef7eb2e8f9f7	2743	}
<>	144:ef7eb2e8f9f7	2744	}
<>	144:ef7eb2e8f9f7	2745
<>	144:ef7eb2e8f9f7	2746	hi2c->State = HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	2747	hi2c->Mode = HAL_I2C_MODE_NONE;
<>	144:ef7eb2e8f9f7	2748
<>	144:ef7eb2e8f9f7	2749	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	2750	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	2751
<>	144:ef7eb2e8f9f7	2752	return HAL_OK;
<>	144:ef7eb2e8f9f7	2753	}
<>	144:ef7eb2e8f9f7	2754	else
<>	144:ef7eb2e8f9f7	2755	{
<>	144:ef7eb2e8f9f7	2756	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	2757	}
<>	144:ef7eb2e8f9f7	2758	}
<>	144:ef7eb2e8f9f7	2759
<>	144:ef7eb2e8f9f7	2760	/**
AnnaBridge	167:e84263d55307	2761	* @brief Write an amount of data in non-blocking mode with Interrupt to a specific memory address
<>	144:ef7eb2e8f9f7	2762	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
AnnaBridge	167:e84263d55307	2763	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	2764	* @param DevAddress Target device address
<>	144:ef7eb2e8f9f7	2765	* @param MemAddress Internal memory address
<>	144:ef7eb2e8f9f7	2766	* @param MemAddSize Size of internal memory address
<>	144:ef7eb2e8f9f7	2767	* @param pData Pointer to data buffer
<>	144:ef7eb2e8f9f7	2768	* @param Size Amount of data to be sent
<>	144:ef7eb2e8f9f7	2769	* @retval HAL status
<>	144:ef7eb2e8f9f7	2770	*/
<>	144:ef7eb2e8f9f7	2771	HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t pData, uint16_t Size)
<>	144:ef7eb2e8f9f7	2772	{
<>	144:ef7eb2e8f9f7	2773	__IO uint32_t count = 0U;
<>	144:ef7eb2e8f9f7	2774
<>	144:ef7eb2e8f9f7	2775	/* Check the parameters */
<>	144:ef7eb2e8f9f7	2776	assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
<>	144:ef7eb2e8f9f7	2777
<>	144:ef7eb2e8f9f7	2778	if(hi2c->State == HAL_I2C_STATE_READY)
<>	144:ef7eb2e8f9f7	2779	{
<>	144:ef7eb2e8f9f7	2780	/* Wait until BUSY flag is reset */
<>	144:ef7eb2e8f9f7	2781	count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U);
<>	144:ef7eb2e8f9f7	2782	do
<>	144:ef7eb2e8f9f7	2783	{
<>	144:ef7eb2e8f9f7	2784	if(count-- == 0U)
<>	144:ef7eb2e8f9f7	2785	{
<>	144:ef7eb2e8f9f7	2786	hi2c->PreviousState = I2C_STATE_NONE;
<>	144:ef7eb2e8f9f7	2787	hi2c->State= HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	2788
<>	144:ef7eb2e8f9f7	2789	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	2790	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	2791
<>	144:ef7eb2e8f9f7	2792	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	2793	}
<>	144:ef7eb2e8f9f7	2794	}
<>	144:ef7eb2e8f9f7	2795	while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
<>	144:ef7eb2e8f9f7	2796
<>	144:ef7eb2e8f9f7	2797	/* Process Locked */
<>	144:ef7eb2e8f9f7	2798	__HAL_LOCK(hi2c);
AnnaBridge	167:e84263d55307	2799
AnnaBridge	167:e84263d55307	2800	/* Check if the I2C is already enabled */
AnnaBridge	167:e84263d55307	2801	if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
AnnaBridge	167:e84263d55307	2802	{
AnnaBridge	167:e84263d55307	2803	/* Enable I2C peripheral */
AnnaBridge	167:e84263d55307	2804	__HAL_I2C_ENABLE(hi2c);
AnnaBridge	167:e84263d55307	2805	}
AnnaBridge	167:e84263d55307	2806
<>	144:ef7eb2e8f9f7	2807	/* Disable Pos */
<>	144:ef7eb2e8f9f7	2808	hi2c->Instance->CR1 &= ~I2C_CR1_POS;
<>	144:ef7eb2e8f9f7	2809
<>	144:ef7eb2e8f9f7	2810	hi2c->State = HAL_I2C_STATE_BUSY_TX;
<>	144:ef7eb2e8f9f7	2811	hi2c->Mode = HAL_I2C_MODE_MEM;
<>	144:ef7eb2e8f9f7	2812	hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
<>	144:ef7eb2e8f9f7	2813
AnnaBridge	167:e84263d55307	2814	/* Prepare transfer parameters */
<>	144:ef7eb2e8f9f7	2815	hi2c->pBuffPtr = pData;
<>	144:ef7eb2e8f9f7	2816	hi2c->XferSize = Size;
<>	144:ef7eb2e8f9f7	2817	hi2c->XferCount = Size;
<>	144:ef7eb2e8f9f7	2818	hi2c->XferOptions = I2C_NO_OPTION_FRAME;
<>	144:ef7eb2e8f9f7	2819	hi2c->Devaddress = DevAddress;
<>	144:ef7eb2e8f9f7	2820	hi2c->Memaddress = MemAddress;
<>	144:ef7eb2e8f9f7	2821	hi2c->MemaddSize = MemAddSize;
<>	144:ef7eb2e8f9f7	2822	hi2c->EventCount = 0U;
<>	144:ef7eb2e8f9f7	2823
<>	144:ef7eb2e8f9f7	2824	/* Generate Start */
<>	144:ef7eb2e8f9f7	2825	hi2c->Instance->CR1 \|= I2C_CR1_START;
<>	144:ef7eb2e8f9f7	2826
<>	144:ef7eb2e8f9f7	2827	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	2828	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	2829
<>	144:ef7eb2e8f9f7	2830	/* Note : The I2C interrupts must be enabled after unlocking current process
<>	144:ef7eb2e8f9f7	2831	to avoid the risk of I2C interrupt handle execution before current
<>	144:ef7eb2e8f9f7	2832	process unlock */
<>	144:ef7eb2e8f9f7	2833
<>	144:ef7eb2e8f9f7	2834	/* Enable EVT, BUF and ERR interrupt */
<>	144:ef7eb2e8f9f7	2835	__HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT \| I2C_IT_BUF \| I2C_IT_ERR);
<>	144:ef7eb2e8f9f7	2836
<>	144:ef7eb2e8f9f7	2837	return HAL_OK;
<>	144:ef7eb2e8f9f7	2838	}
<>	144:ef7eb2e8f9f7	2839	else
<>	144:ef7eb2e8f9f7	2840	{
<>	144:ef7eb2e8f9f7	2841	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	2842	}
<>	144:ef7eb2e8f9f7	2843	}
<>	144:ef7eb2e8f9f7	2844
<>	144:ef7eb2e8f9f7	2845	/**
AnnaBridge	167:e84263d55307	2846	* @brief Read an amount of data in non-blocking mode with Interrupt from a specific memory address
<>	144:ef7eb2e8f9f7	2847	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
AnnaBridge	167:e84263d55307	2848	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	2849	* @param DevAddress Target device address
<>	144:ef7eb2e8f9f7	2850	* @param MemAddress Internal memory address
<>	144:ef7eb2e8f9f7	2851	* @param MemAddSize Size of internal memory address
<>	144:ef7eb2e8f9f7	2852	* @param pData Pointer to data buffer
<>	144:ef7eb2e8f9f7	2853	* @param Size Amount of data to be sent
<>	144:ef7eb2e8f9f7	2854	* @retval HAL status
<>	144:ef7eb2e8f9f7	2855	*/
<>	144:ef7eb2e8f9f7	2856	HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t pData, uint16_t Size)
<>	144:ef7eb2e8f9f7	2857	{
<>	144:ef7eb2e8f9f7	2858	__IO uint32_t count = 0U;
<>	144:ef7eb2e8f9f7	2859
<>	144:ef7eb2e8f9f7	2860	/* Check the parameters */
<>	144:ef7eb2e8f9f7	2861	assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
<>	144:ef7eb2e8f9f7	2862
<>	144:ef7eb2e8f9f7	2863	if(hi2c->State == HAL_I2C_STATE_READY)
<>	144:ef7eb2e8f9f7	2864	{
<>	144:ef7eb2e8f9f7	2865	/* Wait until BUSY flag is reset */
<>	144:ef7eb2e8f9f7	2866	count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U);
<>	144:ef7eb2e8f9f7	2867	do
<>	144:ef7eb2e8f9f7	2868	{
<>	144:ef7eb2e8f9f7	2869	if(count-- == 0U)
<>	144:ef7eb2e8f9f7	2870	{
<>	144:ef7eb2e8f9f7	2871	hi2c->PreviousState = I2C_STATE_NONE;
<>	144:ef7eb2e8f9f7	2872	hi2c->State= HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	2873
<>	144:ef7eb2e8f9f7	2874	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	2875	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	2876
<>	144:ef7eb2e8f9f7	2877	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	2878	}
<>	144:ef7eb2e8f9f7	2879	}
<>	144:ef7eb2e8f9f7	2880	while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
<>	144:ef7eb2e8f9f7	2881
<>	144:ef7eb2e8f9f7	2882	/* Process Locked */
<>	144:ef7eb2e8f9f7	2883	__HAL_LOCK(hi2c);
<>	144:ef7eb2e8f9f7	2884
AnnaBridge	167:e84263d55307	2885	/* Check if the I2C is already enabled */
AnnaBridge	167:e84263d55307	2886	if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
AnnaBridge	167:e84263d55307	2887	{
AnnaBridge	167:e84263d55307	2888	/* Enable I2C peripheral */
AnnaBridge	167:e84263d55307	2889	__HAL_I2C_ENABLE(hi2c);
AnnaBridge	167:e84263d55307	2890	}
AnnaBridge	167:e84263d55307	2891
<>	144:ef7eb2e8f9f7	2892	/* Disable Pos */
<>	144:ef7eb2e8f9f7	2893	hi2c->Instance->CR1 &= ~I2C_CR1_POS;
<>	144:ef7eb2e8f9f7	2894
<>	144:ef7eb2e8f9f7	2895	hi2c->State = HAL_I2C_STATE_BUSY_RX;
<>	144:ef7eb2e8f9f7	2896	hi2c->Mode = HAL_I2C_MODE_MEM;
<>	144:ef7eb2e8f9f7	2897	hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
<>	144:ef7eb2e8f9f7	2898
AnnaBridge	167:e84263d55307	2899	/* Prepare transfer parameters */
<>	144:ef7eb2e8f9f7	2900	hi2c->pBuffPtr = pData;
<>	144:ef7eb2e8f9f7	2901	hi2c->XferSize = Size;
<>	144:ef7eb2e8f9f7	2902	hi2c->XferCount = Size;
<>	144:ef7eb2e8f9f7	2903	hi2c->XferOptions = I2C_NO_OPTION_FRAME;
<>	144:ef7eb2e8f9f7	2904	hi2c->Devaddress = DevAddress;
<>	144:ef7eb2e8f9f7	2905	hi2c->Memaddress = MemAddress;
<>	144:ef7eb2e8f9f7	2906	hi2c->MemaddSize = MemAddSize;
<>	144:ef7eb2e8f9f7	2907	hi2c->EventCount = 0U;
<>	144:ef7eb2e8f9f7	2908
<>	144:ef7eb2e8f9f7	2909	/* Enable Acknowledge */
<>	144:ef7eb2e8f9f7	2910	hi2c->Instance->CR1 \|= I2C_CR1_ACK;
<>	144:ef7eb2e8f9f7	2911
<>	144:ef7eb2e8f9f7	2912	/* Generate Start */
<>	144:ef7eb2e8f9f7	2913	hi2c->Instance->CR1 \|= I2C_CR1_START;
<>	144:ef7eb2e8f9f7	2914
<>	144:ef7eb2e8f9f7	2915	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	2916	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	2917
<>	144:ef7eb2e8f9f7	2918	if(hi2c->XferSize > 0U)
<>	144:ef7eb2e8f9f7	2919	{
<>	144:ef7eb2e8f9f7	2920	/* Note : The I2C interrupts must be enabled after unlocking current process
<>	144:ef7eb2e8f9f7	2921	to avoid the risk of I2C interrupt handle execution before current
<>	144:ef7eb2e8f9f7	2922	process unlock */
<>	144:ef7eb2e8f9f7	2923
<>	144:ef7eb2e8f9f7	2924	/* Enable EVT, BUF and ERR interrupt */
<>	144:ef7eb2e8f9f7	2925	__HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT \| I2C_IT_BUF \| I2C_IT_ERR);
<>	144:ef7eb2e8f9f7	2926	}
<>	144:ef7eb2e8f9f7	2927	return HAL_OK;
<>	144:ef7eb2e8f9f7	2928	}
<>	144:ef7eb2e8f9f7	2929	else
<>	144:ef7eb2e8f9f7	2930	{
<>	144:ef7eb2e8f9f7	2931	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	2932	}
<>	144:ef7eb2e8f9f7	2933	}
<>	144:ef7eb2e8f9f7	2934
<>	144:ef7eb2e8f9f7	2935	/**
AnnaBridge	167:e84263d55307	2936	* @brief Write an amount of data in non-blocking mode with DMA to a specific memory address
<>	144:ef7eb2e8f9f7	2937	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
AnnaBridge	167:e84263d55307	2938	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	2939	* @param DevAddress Target device address
<>	144:ef7eb2e8f9f7	2940	* @param MemAddress Internal memory address
<>	144:ef7eb2e8f9f7	2941	* @param MemAddSize Size of internal memory address
<>	144:ef7eb2e8f9f7	2942	* @param pData Pointer to data buffer
<>	144:ef7eb2e8f9f7	2943	* @param Size Amount of data to be sent
<>	144:ef7eb2e8f9f7	2944	* @retval HAL status
<>	144:ef7eb2e8f9f7	2945	*/
<>	144:ef7eb2e8f9f7	2946	HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t pData, uint16_t Size)
<>	144:ef7eb2e8f9f7	2947	{
AnnaBridge	167:e84263d55307	2948	__IO uint32_t count = 0U;
AnnaBridge	167:e84263d55307	2949
<>	144:ef7eb2e8f9f7	2950	uint32_t tickstart = 0x00U;
<>	144:ef7eb2e8f9f7	2951
<>	144:ef7eb2e8f9f7	2952	/* Init tickstart for timeout management*/
<>	144:ef7eb2e8f9f7	2953	tickstart = HAL_GetTick();
<>	144:ef7eb2e8f9f7	2954
AnnaBridge	167:e84263d55307	2955	/* Check the parameters */
AnnaBridge	167:e84263d55307	2956	assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
AnnaBridge	167:e84263d55307	2957
AnnaBridge	167:e84263d55307	2958	if(hi2c->State == HAL_I2C_STATE_READY)
AnnaBridge	167:e84263d55307	2959	{
AnnaBridge	167:e84263d55307	2960	/* Wait until BUSY flag is reset */
AnnaBridge	167:e84263d55307	2961	count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U);
AnnaBridge	167:e84263d55307	2962	do
AnnaBridge	167:e84263d55307	2963	{
AnnaBridge	167:e84263d55307	2964	if(count-- == 0U)
AnnaBridge	167:e84263d55307	2965	{
AnnaBridge	167:e84263d55307	2966	hi2c->PreviousState = I2C_STATE_NONE;
AnnaBridge	167:e84263d55307	2967	hi2c->State= HAL_I2C_STATE_READY;
AnnaBridge	167:e84263d55307	2968
AnnaBridge	167:e84263d55307	2969	/* Process Unlocked */
AnnaBridge	167:e84263d55307	2970	__HAL_UNLOCK(hi2c);
AnnaBridge	167:e84263d55307	2971
AnnaBridge	167:e84263d55307	2972	return HAL_TIMEOUT;
AnnaBridge	167:e84263d55307	2973	}
AnnaBridge	167:e84263d55307	2974	}
AnnaBridge	167:e84263d55307	2975	while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
AnnaBridge	167:e84263d55307	2976
AnnaBridge	167:e84263d55307	2977	/* Process Locked */
AnnaBridge	167:e84263d55307	2978	__HAL_LOCK(hi2c);
AnnaBridge	167:e84263d55307	2979
AnnaBridge	167:e84263d55307	2980	/* Check if the I2C is already enabled */
AnnaBridge	167:e84263d55307	2981	if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
AnnaBridge	167:e84263d55307	2982	{
AnnaBridge	167:e84263d55307	2983	/* Enable I2C peripheral */
AnnaBridge	167:e84263d55307	2984	__HAL_I2C_ENABLE(hi2c);
AnnaBridge	167:e84263d55307	2985	}
AnnaBridge	167:e84263d55307	2986
AnnaBridge	167:e84263d55307	2987	/* Disable Pos */
AnnaBridge	167:e84263d55307	2988	hi2c->Instance->CR1 &= ~I2C_CR1_POS;
AnnaBridge	167:e84263d55307	2989
AnnaBridge	167:e84263d55307	2990	hi2c->State = HAL_I2C_STATE_BUSY_TX;
AnnaBridge	167:e84263d55307	2991	hi2c->Mode = HAL_I2C_MODE_MEM;
AnnaBridge	167:e84263d55307	2992	hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
AnnaBridge	167:e84263d55307	2993
AnnaBridge	167:e84263d55307	2994	/* Prepare transfer parameters */
AnnaBridge	167:e84263d55307	2995	hi2c->pBuffPtr = pData;
AnnaBridge	167:e84263d55307	2996	hi2c->XferSize = Size;
AnnaBridge	167:e84263d55307	2997	hi2c->XferCount = Size;
AnnaBridge	167:e84263d55307	2998	hi2c->XferOptions = I2C_NO_OPTION_FRAME;
AnnaBridge	167:e84263d55307	2999
AnnaBridge	167:e84263d55307	3000	if(hi2c->XferSize > 0U)
AnnaBridge	167:e84263d55307	3001	{
AnnaBridge	167:e84263d55307	3002	/* Set the I2C DMA transfer complete callback */
AnnaBridge	167:e84263d55307	3003	hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt;
AnnaBridge	167:e84263d55307	3004
AnnaBridge	167:e84263d55307	3005	/* Set the DMA error callback */
AnnaBridge	167:e84263d55307	3006	hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
AnnaBridge	167:e84263d55307	3007
AnnaBridge	167:e84263d55307	3008	/* Set the unused DMA callbacks to NULL */
AnnaBridge	167:e84263d55307	3009	hi2c->hdmatx->XferHalfCpltCallback = NULL;
AnnaBridge	167:e84263d55307	3010	hi2c->hdmatx->XferM1CpltCallback = NULL;
AnnaBridge	167:e84263d55307	3011	hi2c->hdmatx->XferM1HalfCpltCallback = NULL;
AnnaBridge	167:e84263d55307	3012	hi2c->hdmatx->XferAbortCallback = NULL;
AnnaBridge	167:e84263d55307	3013
AnnaBridge	167:e84263d55307	3014	/* Enable the DMA Stream */
AnnaBridge	167:e84263d55307	3015	HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->DR, hi2c->XferSize);
AnnaBridge	167:e84263d55307	3016
AnnaBridge	167:e84263d55307	3017	/* Send Slave Address and Memory Address */
AnnaBridge	167:e84263d55307	3018	if(I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
AnnaBridge	167:e84263d55307	3019	{
AnnaBridge	167:e84263d55307	3020	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
AnnaBridge	167:e84263d55307	3021	{
AnnaBridge	167:e84263d55307	3022	/* Process Unlocked */
AnnaBridge	167:e84263d55307	3023	__HAL_UNLOCK(hi2c);
AnnaBridge	167:e84263d55307	3024	return HAL_ERROR;
AnnaBridge	167:e84263d55307	3025	}
AnnaBridge	167:e84263d55307	3026	else
AnnaBridge	167:e84263d55307	3027	{
AnnaBridge	167:e84263d55307	3028	/* Process Unlocked */
AnnaBridge	167:e84263d55307	3029	__HAL_UNLOCK(hi2c);
AnnaBridge	167:e84263d55307	3030	return HAL_TIMEOUT;
AnnaBridge	167:e84263d55307	3031	}
AnnaBridge	167:e84263d55307	3032	}
AnnaBridge	167:e84263d55307	3033
AnnaBridge	167:e84263d55307	3034	/* Clear ADDR flag */
AnnaBridge	167:e84263d55307	3035	__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
AnnaBridge	167:e84263d55307	3036
AnnaBridge	167:e84263d55307	3037	/* Process Unlocked */
AnnaBridge	167:e84263d55307	3038	__HAL_UNLOCK(hi2c);
AnnaBridge	167:e84263d55307	3039
AnnaBridge	167:e84263d55307	3040	/* Note : The I2C interrupts must be enabled after unlocking current process
AnnaBridge	167:e84263d55307	3041	to avoid the risk of I2C interrupt handle execution before current
AnnaBridge	167:e84263d55307	3042	process unlock */
AnnaBridge	167:e84263d55307	3043	/* Enable ERR interrupt */
AnnaBridge	167:e84263d55307	3044	__HAL_I2C_ENABLE_IT(hi2c, I2C_IT_ERR);
AnnaBridge	167:e84263d55307	3045
AnnaBridge	167:e84263d55307	3046	/* Enable DMA Request */
AnnaBridge	167:e84263d55307	3047	hi2c->Instance->CR2 \|= I2C_CR2_DMAEN;
AnnaBridge	167:e84263d55307	3048	}
AnnaBridge	167:e84263d55307	3049	return HAL_OK;
AnnaBridge	167:e84263d55307	3050	}
AnnaBridge	167:e84263d55307	3051	else
AnnaBridge	167:e84263d55307	3052	{
AnnaBridge	167:e84263d55307	3053	return HAL_BUSY;
AnnaBridge	167:e84263d55307	3054	}
AnnaBridge	167:e84263d55307	3055	}
AnnaBridge	167:e84263d55307	3056
AnnaBridge	167:e84263d55307	3057	/**
AnnaBridge	167:e84263d55307	3058	* @brief Reads an amount of data in non-blocking mode with DMA from a specific memory address.
AnnaBridge	167:e84263d55307	3059	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
AnnaBridge	167:e84263d55307	3060	* the configuration information for the specified I2C.
AnnaBridge	167:e84263d55307	3061	* @param DevAddress Target device address
AnnaBridge	167:e84263d55307	3062	* @param MemAddress Internal memory address
AnnaBridge	167:e84263d55307	3063	* @param MemAddSize Size of internal memory address
AnnaBridge	167:e84263d55307	3064	* @param pData Pointer to data buffer
AnnaBridge	167:e84263d55307	3065	* @param Size Amount of data to be read
AnnaBridge	167:e84263d55307	3066	* @retval HAL status
AnnaBridge	167:e84263d55307	3067	*/
AnnaBridge	167:e84263d55307	3068	HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t pData, uint16_t Size)
AnnaBridge	167:e84263d55307	3069	{
AnnaBridge	167:e84263d55307	3070	uint32_t tickstart = 0x00U;
<>	144:ef7eb2e8f9f7	3071	__IO uint32_t count = 0U;
<>	144:ef7eb2e8f9f7	3072
AnnaBridge	167:e84263d55307	3073	/* Init tickstart for timeout management*/
AnnaBridge	167:e84263d55307	3074	tickstart = HAL_GetTick();
AnnaBridge	167:e84263d55307	3075
<>	144:ef7eb2e8f9f7	3076	/* Check the parameters */
<>	144:ef7eb2e8f9f7	3077	assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
<>	144:ef7eb2e8f9f7	3078
<>	144:ef7eb2e8f9f7	3079	if(hi2c->State == HAL_I2C_STATE_READY)
<>	144:ef7eb2e8f9f7	3080	{
<>	144:ef7eb2e8f9f7	3081	/* Wait until BUSY flag is reset */
<>	144:ef7eb2e8f9f7	3082	count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U);
<>	144:ef7eb2e8f9f7	3083	do
<>	144:ef7eb2e8f9f7	3084	{
<>	144:ef7eb2e8f9f7	3085	if(count-- == 0U)
<>	144:ef7eb2e8f9f7	3086	{
<>	144:ef7eb2e8f9f7	3087	hi2c->PreviousState = I2C_STATE_NONE;
<>	144:ef7eb2e8f9f7	3088	hi2c->State= HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	3089
<>	144:ef7eb2e8f9f7	3090	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	3091	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	3092
<>	144:ef7eb2e8f9f7	3093	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	3094	}
<>	144:ef7eb2e8f9f7	3095	}
<>	144:ef7eb2e8f9f7	3096	while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
<>	144:ef7eb2e8f9f7	3097
<>	144:ef7eb2e8f9f7	3098	/* Process Locked */
<>	144:ef7eb2e8f9f7	3099	__HAL_LOCK(hi2c);
<>	144:ef7eb2e8f9f7	3100
AnnaBridge	167:e84263d55307	3101	/* Check if the I2C is already enabled */
AnnaBridge	167:e84263d55307	3102	if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
<>	144:ef7eb2e8f9f7	3103	{
AnnaBridge	167:e84263d55307	3104	/* Enable I2C peripheral */
AnnaBridge	167:e84263d55307	3105	__HAL_I2C_ENABLE(hi2c);
<>	144:ef7eb2e8f9f7	3106	}
<>	144:ef7eb2e8f9f7	3107
<>	144:ef7eb2e8f9f7	3108	/* Disable Pos */
<>	144:ef7eb2e8f9f7	3109	hi2c->Instance->CR1 &= ~I2C_CR1_POS;
<>	144:ef7eb2e8f9f7	3110
AnnaBridge	167:e84263d55307	3111	hi2c->State = HAL_I2C_STATE_BUSY_RX;
AnnaBridge	167:e84263d55307	3112	hi2c->Mode = HAL_I2C_MODE_MEM;
<>	144:ef7eb2e8f9f7	3113	hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
<>	144:ef7eb2e8f9f7	3114
AnnaBridge	167:e84263d55307	3115	/* Prepare transfer parameters */
<>	144:ef7eb2e8f9f7	3116	hi2c->pBuffPtr = pData;
<>	144:ef7eb2e8f9f7	3117	hi2c->XferCount = Size;
<>	144:ef7eb2e8f9f7	3118	hi2c->XferOptions = I2C_NO_OPTION_FRAME;
AnnaBridge	167:e84263d55307	3119	hi2c->XferSize = hi2c->XferCount;
<>	144:ef7eb2e8f9f7	3120
<>	144:ef7eb2e8f9f7	3121	if(hi2c->XferSize > 0U)
<>	144:ef7eb2e8f9f7	3122	{
<>	144:ef7eb2e8f9f7	3123	/* Set the I2C DMA transfer complete callback */
<>	144:ef7eb2e8f9f7	3124	hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt;
<>	144:ef7eb2e8f9f7	3125
<>	144:ef7eb2e8f9f7	3126	/* Set the DMA error callback */
<>	144:ef7eb2e8f9f7	3127	hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
<>	144:ef7eb2e8f9f7	3128
<>	144:ef7eb2e8f9f7	3129	/* Set the unused DMA callbacks to NULL */
<>	144:ef7eb2e8f9f7	3130	hi2c->hdmarx->XferHalfCpltCallback = NULL;
<>	144:ef7eb2e8f9f7	3131	hi2c->hdmarx->XferM1CpltCallback = NULL;
<>	144:ef7eb2e8f9f7	3132	hi2c->hdmarx->XferM1HalfCpltCallback = NULL;
<>	144:ef7eb2e8f9f7	3133	hi2c->hdmarx->XferAbortCallback = NULL;
<>	144:ef7eb2e8f9f7	3134
<>	144:ef7eb2e8f9f7	3135	/* Enable the DMA Stream */
AnnaBridge	167:e84263d55307	3136	HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize);
<>	144:ef7eb2e8f9f7	3137
<>	144:ef7eb2e8f9f7	3138	/* Send Slave Address and Memory Address */
<>	144:ef7eb2e8f9f7	3139	if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	3140	{
<>	144:ef7eb2e8f9f7	3141	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
<>	144:ef7eb2e8f9f7	3142	{
<>	144:ef7eb2e8f9f7	3143	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	3144	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	3145	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	3146	}
<>	144:ef7eb2e8f9f7	3147	else
<>	144:ef7eb2e8f9f7	3148	{
<>	144:ef7eb2e8f9f7	3149	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	3150	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	3151	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	3152	}
<>	144:ef7eb2e8f9f7	3153	}
<>	144:ef7eb2e8f9f7	3154
<>	144:ef7eb2e8f9f7	3155	if(Size == 1U)
<>	144:ef7eb2e8f9f7	3156	{
<>	144:ef7eb2e8f9f7	3157	/* Disable Acknowledge */
<>	144:ef7eb2e8f9f7	3158	hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
<>	144:ef7eb2e8f9f7	3159	}
<>	144:ef7eb2e8f9f7	3160	else
<>	144:ef7eb2e8f9f7	3161	{
<>	144:ef7eb2e8f9f7	3162	/* Enable Last DMA bit */
<>	144:ef7eb2e8f9f7	3163	hi2c->Instance->CR2 \|= I2C_CR2_LAST;
<>	144:ef7eb2e8f9f7	3164	}
<>	144:ef7eb2e8f9f7	3165
<>	144:ef7eb2e8f9f7	3166	/* Clear ADDR flag */
<>	144:ef7eb2e8f9f7	3167	__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
<>	144:ef7eb2e8f9f7	3168
<>	144:ef7eb2e8f9f7	3169	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	3170	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	3171
<>	144:ef7eb2e8f9f7	3172	/* Note : The I2C interrupts must be enabled after unlocking current process
<>	144:ef7eb2e8f9f7	3173	to avoid the risk of I2C interrupt handle execution before current
<>	144:ef7eb2e8f9f7	3174	process unlock */
<>	144:ef7eb2e8f9f7	3175	/* Enable ERR interrupt */
<>	144:ef7eb2e8f9f7	3176	__HAL_I2C_ENABLE_IT(hi2c, I2C_IT_ERR);
<>	144:ef7eb2e8f9f7	3177
<>	144:ef7eb2e8f9f7	3178	/* Enable DMA Request */
<>	144:ef7eb2e8f9f7	3179	hi2c->Instance->CR2 \|= I2C_CR2_DMAEN;
<>	144:ef7eb2e8f9f7	3180	}
<>	144:ef7eb2e8f9f7	3181	else
<>	144:ef7eb2e8f9f7	3182	{
<>	144:ef7eb2e8f9f7	3183	/* Send Slave Address and Memory Address */
<>	144:ef7eb2e8f9f7	3184	if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	3185	{
<>	144:ef7eb2e8f9f7	3186	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
<>	144:ef7eb2e8f9f7	3187	{
<>	144:ef7eb2e8f9f7	3188	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	3189	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	3190	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	3191	}
<>	144:ef7eb2e8f9f7	3192	else
<>	144:ef7eb2e8f9f7	3193	{
<>	144:ef7eb2e8f9f7	3194	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	3195	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	3196	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	3197	}
<>	144:ef7eb2e8f9f7	3198	}
<>	144:ef7eb2e8f9f7	3199
<>	144:ef7eb2e8f9f7	3200	/* Clear ADDR flag */
<>	144:ef7eb2e8f9f7	3201	__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
<>	144:ef7eb2e8f9f7	3202
<>	144:ef7eb2e8f9f7	3203	/* Generate Stop */
<>	144:ef7eb2e8f9f7	3204	hi2c->Instance->CR1 \|= I2C_CR1_STOP;
<>	144:ef7eb2e8f9f7	3205
<>	144:ef7eb2e8f9f7	3206	hi2c->State = HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	3207
<>	144:ef7eb2e8f9f7	3208	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	3209	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	3210	}
<>	144:ef7eb2e8f9f7	3211
<>	144:ef7eb2e8f9f7	3212	return HAL_OK;
<>	144:ef7eb2e8f9f7	3213	}
<>	144:ef7eb2e8f9f7	3214	else
<>	144:ef7eb2e8f9f7	3215	{
<>	144:ef7eb2e8f9f7	3216	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	3217	}
<>	144:ef7eb2e8f9f7	3218	}
<>	144:ef7eb2e8f9f7	3219
<>	144:ef7eb2e8f9f7	3220	/**
<>	144:ef7eb2e8f9f7	3221	* @brief Checks if target device is ready for communication.
<>	144:ef7eb2e8f9f7	3222	* @note This function is used with Memory devices
<>	144:ef7eb2e8f9f7	3223	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
AnnaBridge	167:e84263d55307	3224	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	3225	* @param DevAddress Target device address
<>	144:ef7eb2e8f9f7	3226	* @param Trials Number of trials
<>	144:ef7eb2e8f9f7	3227	* @param Timeout Timeout duration
<>	144:ef7eb2e8f9f7	3228	* @retval HAL status
<>	144:ef7eb2e8f9f7	3229	*/
<>	144:ef7eb2e8f9f7	3230	HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout)
<>	144:ef7eb2e8f9f7	3231	{
<>	144:ef7eb2e8f9f7	3232	uint32_t tickstart = 0U, tmp1 = 0U, tmp2 = 0U, tmp3 = 0U, I2C_Trials = 1U;
<>	144:ef7eb2e8f9f7	3233
<>	144:ef7eb2e8f9f7	3234	/* Get tick */
<>	144:ef7eb2e8f9f7	3235	tickstart = HAL_GetTick();
<>	144:ef7eb2e8f9f7	3236
<>	144:ef7eb2e8f9f7	3237	if(hi2c->State == HAL_I2C_STATE_READY)
<>	144:ef7eb2e8f9f7	3238	{
<>	144:ef7eb2e8f9f7	3239	/* Wait until BUSY flag is reset */
<>	144:ef7eb2e8f9f7	3240	if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	3241	{
<>	144:ef7eb2e8f9f7	3242	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	3243	}
<>	144:ef7eb2e8f9f7	3244
<>	144:ef7eb2e8f9f7	3245	/* Process Locked */
<>	144:ef7eb2e8f9f7	3246	__HAL_LOCK(hi2c);
<>	144:ef7eb2e8f9f7	3247
AnnaBridge	167:e84263d55307	3248	/* Check if the I2C is already enabled */
AnnaBridge	167:e84263d55307	3249	if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
AnnaBridge	167:e84263d55307	3250	{
AnnaBridge	167:e84263d55307	3251	/* Enable I2C peripheral */
AnnaBridge	167:e84263d55307	3252	__HAL_I2C_ENABLE(hi2c);
AnnaBridge	167:e84263d55307	3253	}
AnnaBridge	167:e84263d55307	3254
<>	144:ef7eb2e8f9f7	3255	/* Disable Pos */
<>	144:ef7eb2e8f9f7	3256	hi2c->Instance->CR1 &= ~I2C_CR1_POS;
<>	144:ef7eb2e8f9f7	3257
<>	144:ef7eb2e8f9f7	3258	hi2c->State = HAL_I2C_STATE_BUSY;
<>	144:ef7eb2e8f9f7	3259	hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
<>	144:ef7eb2e8f9f7	3260	hi2c->XferOptions = I2C_NO_OPTION_FRAME;
<>	144:ef7eb2e8f9f7	3261
<>	144:ef7eb2e8f9f7	3262	do
<>	144:ef7eb2e8f9f7	3263	{
<>	144:ef7eb2e8f9f7	3264	/* Generate Start */
<>	144:ef7eb2e8f9f7	3265	hi2c->Instance->CR1 \|= I2C_CR1_START;
<>	144:ef7eb2e8f9f7	3266
<>	144:ef7eb2e8f9f7	3267	/* Wait until SB flag is set */
<>	144:ef7eb2e8f9f7	3268	if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	3269	{
<>	144:ef7eb2e8f9f7	3270	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	3271	}
<>	144:ef7eb2e8f9f7	3272
<>	144:ef7eb2e8f9f7	3273	/* Send slave address */
<>	144:ef7eb2e8f9f7	3274	hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress);
<>	144:ef7eb2e8f9f7	3275
<>	144:ef7eb2e8f9f7	3276	/* Wait until ADDR or AF flag are set */
<>	144:ef7eb2e8f9f7	3277	/* Get tick */
<>	144:ef7eb2e8f9f7	3278	tickstart = HAL_GetTick();
<>	144:ef7eb2e8f9f7	3279
<>	144:ef7eb2e8f9f7	3280	tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR);
<>	144:ef7eb2e8f9f7	3281	tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF);
<>	144:ef7eb2e8f9f7	3282	tmp3 = hi2c->State;
<>	144:ef7eb2e8f9f7	3283	while((tmp1 == RESET) && (tmp2 == RESET) && (tmp3 != HAL_I2C_STATE_TIMEOUT))
<>	144:ef7eb2e8f9f7	3284	{
<>	144:ef7eb2e8f9f7	3285	if((Timeout == 0U)\|\|((HAL_GetTick() - tickstart ) > Timeout))
<>	144:ef7eb2e8f9f7	3286	{
<>	144:ef7eb2e8f9f7	3287	hi2c->State = HAL_I2C_STATE_TIMEOUT;
<>	144:ef7eb2e8f9f7	3288	}
<>	144:ef7eb2e8f9f7	3289	tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR);
<>	144:ef7eb2e8f9f7	3290	tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF);
<>	144:ef7eb2e8f9f7	3291	tmp3 = hi2c->State;
<>	144:ef7eb2e8f9f7	3292	}
<>	144:ef7eb2e8f9f7	3293
<>	144:ef7eb2e8f9f7	3294	hi2c->State = HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	3295
<>	144:ef7eb2e8f9f7	3296	/* Check if the ADDR flag has been set */
<>	144:ef7eb2e8f9f7	3297	if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR) == SET)
<>	144:ef7eb2e8f9f7	3298	{
<>	144:ef7eb2e8f9f7	3299	/* Generate Stop */
<>	144:ef7eb2e8f9f7	3300	hi2c->Instance->CR1 \|= I2C_CR1_STOP;
<>	144:ef7eb2e8f9f7	3301
<>	144:ef7eb2e8f9f7	3302	/* Clear ADDR Flag */
<>	144:ef7eb2e8f9f7	3303	__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
<>	144:ef7eb2e8f9f7	3304
<>	144:ef7eb2e8f9f7	3305	/* Wait until BUSY flag is reset */
<>	144:ef7eb2e8f9f7	3306	if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	3307	{
<>	144:ef7eb2e8f9f7	3308	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	3309	}
<>	144:ef7eb2e8f9f7	3310
<>	144:ef7eb2e8f9f7	3311	hi2c->State = HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	3312
<>	144:ef7eb2e8f9f7	3313	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	3314	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	3315
<>	144:ef7eb2e8f9f7	3316	return HAL_OK;
<>	144:ef7eb2e8f9f7	3317	}
<>	144:ef7eb2e8f9f7	3318	else
<>	144:ef7eb2e8f9f7	3319	{
<>	144:ef7eb2e8f9f7	3320	/* Generate Stop */
<>	144:ef7eb2e8f9f7	3321	hi2c->Instance->CR1 \|= I2C_CR1_STOP;
<>	144:ef7eb2e8f9f7	3322
<>	144:ef7eb2e8f9f7	3323	/* Clear AF Flag */
<>	144:ef7eb2e8f9f7	3324	__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
<>	144:ef7eb2e8f9f7	3325
<>	144:ef7eb2e8f9f7	3326	/* Wait until BUSY flag is reset */
<>	144:ef7eb2e8f9f7	3327	if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	3328	{
<>	144:ef7eb2e8f9f7	3329	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	3330	}
<>	144:ef7eb2e8f9f7	3331	}
<>	144:ef7eb2e8f9f7	3332	}while(I2C_Trials++ < Trials);
<>	144:ef7eb2e8f9f7	3333
<>	144:ef7eb2e8f9f7	3334	hi2c->State = HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	3335
<>	144:ef7eb2e8f9f7	3336	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	3337	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	3338
<>	144:ef7eb2e8f9f7	3339	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	3340	}
<>	144:ef7eb2e8f9f7	3341	else
<>	144:ef7eb2e8f9f7	3342	{
<>	144:ef7eb2e8f9f7	3343	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	3344	}
<>	144:ef7eb2e8f9f7	3345	}
<>	144:ef7eb2e8f9f7	3346
<>	144:ef7eb2e8f9f7	3347	/**
<>	144:ef7eb2e8f9f7	3348	* @brief This function handles I2C event interrupt request.
<>	144:ef7eb2e8f9f7	3349	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
AnnaBridge	167:e84263d55307	3350	* the configuration information for the specified I2C.
AnnaBridge	167:e84263d55307	3351	* @retval None
<>	144:ef7eb2e8f9f7	3352	*/
<>	144:ef7eb2e8f9f7	3353	void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c)
<>	144:ef7eb2e8f9f7	3354	{
<>	144:ef7eb2e8f9f7	3355	uint32_t sr2itflags = READ_REG(hi2c->Instance->SR2);
<>	144:ef7eb2e8f9f7	3356	uint32_t sr1itflags = READ_REG(hi2c->Instance->SR1);
<>	144:ef7eb2e8f9f7	3357	uint32_t itsources = READ_REG(hi2c->Instance->CR2);
<>	144:ef7eb2e8f9f7	3358
<>	144:ef7eb2e8f9f7	3359	uint32_t CurrentMode = hi2c->Mode;
<>	144:ef7eb2e8f9f7	3360
<>	144:ef7eb2e8f9f7	3361	/* Master or Memory mode selected */
<>	144:ef7eb2e8f9f7	3362	if((CurrentMode == HAL_I2C_MODE_MASTER) \|\| (CurrentMode == HAL_I2C_MODE_MEM))
<>	144:ef7eb2e8f9f7	3363	{
<>	144:ef7eb2e8f9f7	3364	/* SB Set ----------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	3365	if(((sr1itflags & I2C_FLAG_SB) != RESET) && ((itsources & I2C_IT_EVT) != RESET))
<>	144:ef7eb2e8f9f7	3366	{
<>	144:ef7eb2e8f9f7	3367	I2C_Master_SB(hi2c);
<>	144:ef7eb2e8f9f7	3368	}
<>	144:ef7eb2e8f9f7	3369	/* ADD10 Set -------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	3370	else if(((sr1itflags & I2C_FLAG_ADD10) != RESET) && ((itsources & I2C_IT_EVT) != RESET))
<>	144:ef7eb2e8f9f7	3371	{
<>	144:ef7eb2e8f9f7	3372	I2C_Master_ADD10(hi2c);
<>	144:ef7eb2e8f9f7	3373	}
<>	144:ef7eb2e8f9f7	3374	/* ADDR Set --------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	3375	else if(((sr1itflags & I2C_FLAG_ADDR) != RESET) && ((itsources & I2C_IT_EVT) != RESET))
<>	144:ef7eb2e8f9f7	3376	{
<>	144:ef7eb2e8f9f7	3377	I2C_Master_ADDR(hi2c);
<>	144:ef7eb2e8f9f7	3378	}
<>	144:ef7eb2e8f9f7	3379
<>	144:ef7eb2e8f9f7	3380	/* I2C in mode Transmitter -----------------------------------------------*/
<>	144:ef7eb2e8f9f7	3381	if((sr2itflags & I2C_FLAG_TRA) != RESET)
<>	144:ef7eb2e8f9f7	3382	{
<>	144:ef7eb2e8f9f7	3383	/* TXE set and BTF reset -----------------------------------------------*/
<>	144:ef7eb2e8f9f7	3384	if(((sr1itflags & I2C_FLAG_TXE) != RESET) && ((itsources & I2C_IT_BUF) != RESET) && ((sr1itflags & I2C_FLAG_BTF) == RESET))
<>	144:ef7eb2e8f9f7	3385	{
<>	144:ef7eb2e8f9f7	3386	I2C_MasterTransmit_TXE(hi2c);
<>	144:ef7eb2e8f9f7	3387	}
<>	144:ef7eb2e8f9f7	3388	/* BTF set -------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	3389	else if(((sr1itflags & I2C_FLAG_BTF) != RESET) && ((itsources & I2C_IT_EVT) != RESET))
<>	144:ef7eb2e8f9f7	3390	{
<>	144:ef7eb2e8f9f7	3391	I2C_MasterTransmit_BTF(hi2c);
<>	144:ef7eb2e8f9f7	3392	}
<>	144:ef7eb2e8f9f7	3393	}
<>	144:ef7eb2e8f9f7	3394	/* I2C in mode Receiver --------------------------------------------------*/
<>	144:ef7eb2e8f9f7	3395	else
<>	144:ef7eb2e8f9f7	3396	{
<>	144:ef7eb2e8f9f7	3397	/* RXNE set and BTF reset -----------------------------------------------*/
<>	144:ef7eb2e8f9f7	3398	if(((sr1itflags & I2C_FLAG_RXNE) != RESET) && ((itsources & I2C_IT_BUF) != RESET) && ((sr1itflags & I2C_FLAG_BTF) == RESET))
<>	144:ef7eb2e8f9f7	3399	{
<>	144:ef7eb2e8f9f7	3400	I2C_MasterReceive_RXNE(hi2c);
<>	144:ef7eb2e8f9f7	3401	}
<>	144:ef7eb2e8f9f7	3402	/* BTF set -------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	3403	else if(((sr1itflags & I2C_FLAG_BTF) != RESET) && ((itsources & I2C_IT_EVT) != RESET))
<>	144:ef7eb2e8f9f7	3404	{
<>	144:ef7eb2e8f9f7	3405	I2C_MasterReceive_BTF(hi2c);
<>	144:ef7eb2e8f9f7	3406	}
<>	144:ef7eb2e8f9f7	3407	}
<>	144:ef7eb2e8f9f7	3408	}
<>	144:ef7eb2e8f9f7	3409	/* Slave mode selected */
<>	144:ef7eb2e8f9f7	3410	else
<>	144:ef7eb2e8f9f7	3411	{
<>	144:ef7eb2e8f9f7	3412	/* ADDR set --------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	3413	if(((sr1itflags & I2C_FLAG_ADDR) != RESET) && ((itsources & I2C_IT_EVT) != RESET))
<>	144:ef7eb2e8f9f7	3414	{
<>	144:ef7eb2e8f9f7	3415	I2C_Slave_ADDR(hi2c);
<>	144:ef7eb2e8f9f7	3416	}
<>	144:ef7eb2e8f9f7	3417	/* STOPF set --------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	3418	else if(((sr1itflags & I2C_FLAG_STOPF) != RESET) && ((itsources & I2C_IT_EVT) != RESET))
<>	144:ef7eb2e8f9f7	3419	{
<>	144:ef7eb2e8f9f7	3420	I2C_Slave_STOPF(hi2c);
<>	144:ef7eb2e8f9f7	3421	}
<>	144:ef7eb2e8f9f7	3422	/* I2C in mode Transmitter -----------------------------------------------*/
<>	144:ef7eb2e8f9f7	3423	else if((sr2itflags & I2C_FLAG_TRA) != RESET)
<>	144:ef7eb2e8f9f7	3424	{
<>	144:ef7eb2e8f9f7	3425	/* TXE set and BTF reset -----------------------------------------------*/
<>	144:ef7eb2e8f9f7	3426	if(((sr1itflags & I2C_FLAG_TXE) != RESET) && ((itsources & I2C_IT_BUF) != RESET) && ((sr1itflags & I2C_FLAG_BTF) == RESET))
<>	144:ef7eb2e8f9f7	3427	{
<>	144:ef7eb2e8f9f7	3428	I2C_SlaveTransmit_TXE(hi2c);
<>	144:ef7eb2e8f9f7	3429	}
<>	144:ef7eb2e8f9f7	3430	/* BTF set -------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	3431	else if(((sr1itflags & I2C_FLAG_BTF) != RESET) && ((itsources & I2C_IT_EVT) != RESET))
<>	144:ef7eb2e8f9f7	3432	{
<>	144:ef7eb2e8f9f7	3433	I2C_SlaveTransmit_BTF(hi2c);
<>	144:ef7eb2e8f9f7	3434	}
<>	144:ef7eb2e8f9f7	3435	}
<>	144:ef7eb2e8f9f7	3436	/* I2C in mode Receiver --------------------------------------------------*/
<>	144:ef7eb2e8f9f7	3437	else
<>	144:ef7eb2e8f9f7	3438	{
<>	144:ef7eb2e8f9f7	3439	/* RXNE set and BTF reset ----------------------------------------------*/
<>	144:ef7eb2e8f9f7	3440	if(((sr1itflags & I2C_FLAG_RXNE) != RESET) && ((itsources & I2C_IT_BUF) != RESET) && ((sr1itflags & I2C_FLAG_BTF) == RESET))
<>	144:ef7eb2e8f9f7	3441	{
<>	144:ef7eb2e8f9f7	3442	I2C_SlaveReceive_RXNE(hi2c);
<>	144:ef7eb2e8f9f7	3443	}
<>	144:ef7eb2e8f9f7	3444	/* BTF set -------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	3445	else if(((sr1itflags & I2C_FLAG_BTF) != RESET) && ((itsources & I2C_IT_EVT) != RESET))
<>	144:ef7eb2e8f9f7	3446	{
<>	144:ef7eb2e8f9f7	3447	I2C_SlaveReceive_BTF(hi2c);
<>	144:ef7eb2e8f9f7	3448	}
<>	144:ef7eb2e8f9f7	3449	}
<>	144:ef7eb2e8f9f7	3450	}
<>	144:ef7eb2e8f9f7	3451	}
<>	144:ef7eb2e8f9f7	3452
<>	144:ef7eb2e8f9f7	3453	/**
<>	144:ef7eb2e8f9f7	3454	* @brief This function handles I2C error interrupt request.
<>	144:ef7eb2e8f9f7	3455	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
AnnaBridge	167:e84263d55307	3456	* the configuration information for the specified I2C.
AnnaBridge	167:e84263d55307	3457	* @retval None
<>	144:ef7eb2e8f9f7	3458	*/
<>	144:ef7eb2e8f9f7	3459	void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c)
<>	144:ef7eb2e8f9f7	3460	{
<>	144:ef7eb2e8f9f7	3461	uint32_t tmp1 = 0U, tmp2 = 0U, tmp3 = 0U, tmp4 = 0U;
<>	144:ef7eb2e8f9f7	3462	uint32_t sr1itflags = READ_REG(hi2c->Instance->SR1);
<>	144:ef7eb2e8f9f7	3463	uint32_t itsources = READ_REG(hi2c->Instance->CR2);
<>	144:ef7eb2e8f9f7	3464
<>	144:ef7eb2e8f9f7	3465	/* I2C Bus error interrupt occurred ----------------------------------------*/
<>	144:ef7eb2e8f9f7	3466	if(((sr1itflags & I2C_FLAG_BERR) != RESET) && ((itsources & I2C_IT_ERR) != RESET))
<>	144:ef7eb2e8f9f7	3467	{
<>	144:ef7eb2e8f9f7	3468	hi2c->ErrorCode \|= HAL_I2C_ERROR_BERR;
<>	144:ef7eb2e8f9f7	3469
<>	144:ef7eb2e8f9f7	3470	/* Clear BERR flag */
<>	144:ef7eb2e8f9f7	3471	__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR);
<>	144:ef7eb2e8f9f7	3472	}
<>	144:ef7eb2e8f9f7	3473
<>	144:ef7eb2e8f9f7	3474	/* I2C Arbitration Loss error interrupt occurred ---------------------------*/
<>	144:ef7eb2e8f9f7	3475	if(((sr1itflags & I2C_FLAG_ARLO) != RESET) && ((itsources & I2C_IT_ERR) != RESET))
<>	144:ef7eb2e8f9f7	3476	{
<>	144:ef7eb2e8f9f7	3477	hi2c->ErrorCode \|= HAL_I2C_ERROR_ARLO;
<>	144:ef7eb2e8f9f7	3478
<>	144:ef7eb2e8f9f7	3479	/* Clear ARLO flag */
<>	144:ef7eb2e8f9f7	3480	__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO);
<>	144:ef7eb2e8f9f7	3481	}
<>	144:ef7eb2e8f9f7	3482
<>	144:ef7eb2e8f9f7	3483	/* I2C Acknowledge failure error interrupt occurred ------------------------*/
<>	144:ef7eb2e8f9f7	3484	if(((sr1itflags & I2C_FLAG_AF) != RESET) && ((itsources & I2C_IT_ERR) != RESET))
<>	144:ef7eb2e8f9f7	3485	{
<>	144:ef7eb2e8f9f7	3486	tmp1 = hi2c->Mode;
<>	144:ef7eb2e8f9f7	3487	tmp2 = hi2c->XferCount;
<>	144:ef7eb2e8f9f7	3488	tmp3 = hi2c->State;
<>	144:ef7eb2e8f9f7	3489	tmp4 = hi2c->PreviousState;
<>	144:ef7eb2e8f9f7	3490	if((tmp1 == HAL_I2C_MODE_SLAVE) && (tmp2 == 0U) && \
<>	144:ef7eb2e8f9f7	3491	((tmp3 == HAL_I2C_STATE_BUSY_TX) \|\| (tmp3 == HAL_I2C_STATE_BUSY_TX_LISTEN) \|\| \
<>	144:ef7eb2e8f9f7	3492	((tmp3 == HAL_I2C_STATE_LISTEN) && (tmp4 == I2C_STATE_SLAVE_BUSY_TX))))
<>	144:ef7eb2e8f9f7	3493	{
<>	144:ef7eb2e8f9f7	3494	I2C_Slave_AF(hi2c);
<>	144:ef7eb2e8f9f7	3495	}
<>	144:ef7eb2e8f9f7	3496	else
<>	144:ef7eb2e8f9f7	3497	{
<>	144:ef7eb2e8f9f7	3498	hi2c->ErrorCode \|= HAL_I2C_ERROR_AF;
<>	144:ef7eb2e8f9f7	3499
AnnaBridge	167:e84263d55307	3500	/* Do not generate a STOP in case of Slave receive non acknowledge during transfer (mean not at the end of transfer) */
AnnaBridge	167:e84263d55307	3501	if(hi2c->Mode == HAL_I2C_MODE_MASTER)
AnnaBridge	167:e84263d55307	3502	{
AnnaBridge	167:e84263d55307	3503	/* Generate Stop */
AnnaBridge	167:e84263d55307	3504	SET_BIT(hi2c->Instance->CR1,I2C_CR1_STOP);
AnnaBridge	167:e84263d55307	3505	}
<>	144:ef7eb2e8f9f7	3506
<>	144:ef7eb2e8f9f7	3507	/* Clear AF flag */
<>	144:ef7eb2e8f9f7	3508	__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
<>	144:ef7eb2e8f9f7	3509	}
<>	144:ef7eb2e8f9f7	3510	}
<>	144:ef7eb2e8f9f7	3511
<>	144:ef7eb2e8f9f7	3512	/* I2C Over-Run/Under-Run interrupt occurred -------------------------------*/
<>	144:ef7eb2e8f9f7	3513	if(((sr1itflags & I2C_FLAG_OVR) != RESET) && ((itsources & I2C_IT_ERR) != RESET))
<>	144:ef7eb2e8f9f7	3514	{
<>	144:ef7eb2e8f9f7	3515	hi2c->ErrorCode \|= HAL_I2C_ERROR_OVR;
<>	144:ef7eb2e8f9f7	3516	/* Clear OVR flag */
<>	144:ef7eb2e8f9f7	3517	__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR);
<>	144:ef7eb2e8f9f7	3518	}
<>	144:ef7eb2e8f9f7	3519
<>	144:ef7eb2e8f9f7	3520	/* Call the Error Callback in case of Error detected -----------------------*/
<>	144:ef7eb2e8f9f7	3521	if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
<>	144:ef7eb2e8f9f7	3522	{
<>	144:ef7eb2e8f9f7	3523	I2C_ITError(hi2c);
<>	144:ef7eb2e8f9f7	3524	}
<>	144:ef7eb2e8f9f7	3525	}
<>	144:ef7eb2e8f9f7	3526
<>	144:ef7eb2e8f9f7	3527	/**
AnnaBridge	167:e84263d55307	3528	* @brief Master Tx Transfer completed callback.
<>	144:ef7eb2e8f9f7	3529	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
AnnaBridge	167:e84263d55307	3530	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	3531	* @retval None
<>	144:ef7eb2e8f9f7	3532	*/
<>	144:ef7eb2e8f9f7	3533	__weak void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c)
<>	144:ef7eb2e8f9f7	3534	{
<>	144:ef7eb2e8f9f7	3535	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	3536	UNUSED(hi2c);
AnnaBridge	167:e84263d55307	3537
<>	144:ef7eb2e8f9f7	3538	/* NOTE : This function should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	3539	the HAL_I2C_MasterTxCpltCallback can be implemented in the user file
<>	144:ef7eb2e8f9f7	3540	*/
<>	144:ef7eb2e8f9f7	3541	}
<>	144:ef7eb2e8f9f7	3542
<>	144:ef7eb2e8f9f7	3543	/**
AnnaBridge	167:e84263d55307	3544	* @brief Master Rx Transfer completed callback.
<>	144:ef7eb2e8f9f7	3545	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
AnnaBridge	167:e84263d55307	3546	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	3547	* @retval None
<>	144:ef7eb2e8f9f7	3548	*/
<>	144:ef7eb2e8f9f7	3549	__weak void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c)
<>	144:ef7eb2e8f9f7	3550	{
<>	144:ef7eb2e8f9f7	3551	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	3552	UNUSED(hi2c);
AnnaBridge	167:e84263d55307	3553
<>	144:ef7eb2e8f9f7	3554	/* NOTE : This function should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	3555	the HAL_I2C_MasterRxCpltCallback can be implemented in the user file
<>	144:ef7eb2e8f9f7	3556	*/
<>	144:ef7eb2e8f9f7	3557	}
<>	144:ef7eb2e8f9f7	3558
AnnaBridge	167:e84263d55307	3559	/** @brief Slave Tx Transfer completed callback.
<>	144:ef7eb2e8f9f7	3560	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
AnnaBridge	167:e84263d55307	3561	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	3562	* @retval None
<>	144:ef7eb2e8f9f7	3563	*/
<>	144:ef7eb2e8f9f7	3564	__weak void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c)
<>	144:ef7eb2e8f9f7	3565	{
<>	144:ef7eb2e8f9f7	3566	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	3567	UNUSED(hi2c);
AnnaBridge	167:e84263d55307	3568
<>	144:ef7eb2e8f9f7	3569	/* NOTE : This function should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	3570	the HAL_I2C_SlaveTxCpltCallback can be implemented in the user file
<>	144:ef7eb2e8f9f7	3571	*/
<>	144:ef7eb2e8f9f7	3572	}
<>	144:ef7eb2e8f9f7	3573
<>	144:ef7eb2e8f9f7	3574	/**
AnnaBridge	167:e84263d55307	3575	* @brief Slave Rx Transfer completed callback.
<>	144:ef7eb2e8f9f7	3576	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
AnnaBridge	167:e84263d55307	3577	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	3578	* @retval None
<>	144:ef7eb2e8f9f7	3579	*/
<>	144:ef7eb2e8f9f7	3580	__weak void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c)
<>	144:ef7eb2e8f9f7	3581	{
<>	144:ef7eb2e8f9f7	3582	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	3583	UNUSED(hi2c);
AnnaBridge	167:e84263d55307	3584
<>	144:ef7eb2e8f9f7	3585	/* NOTE : This function should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	3586	the HAL_I2C_SlaveRxCpltCallback can be implemented in the user file
<>	144:ef7eb2e8f9f7	3587	*/
<>	144:ef7eb2e8f9f7	3588	}
<>	144:ef7eb2e8f9f7	3589
<>	144:ef7eb2e8f9f7	3590	/**
<>	144:ef7eb2e8f9f7	3591	* @brief Slave Address Match callback.
<>	144:ef7eb2e8f9f7	3592	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	3593	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	3594	* @param TransferDirection Master request Transfer Direction (Write/Read), value of @ref I2C_XferOptions_definition
<>	144:ef7eb2e8f9f7	3595	* @param AddrMatchCode Address Match Code
<>	144:ef7eb2e8f9f7	3596	* @retval None
<>	144:ef7eb2e8f9f7	3597	*/
<>	144:ef7eb2e8f9f7	3598	__weak void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode)
<>	144:ef7eb2e8f9f7	3599	{
<>	144:ef7eb2e8f9f7	3600	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	3601	UNUSED(hi2c);
<>	144:ef7eb2e8f9f7	3602	UNUSED(TransferDirection);
<>	144:ef7eb2e8f9f7	3603	UNUSED(AddrMatchCode);
AnnaBridge	167:e84263d55307	3604
<>	144:ef7eb2e8f9f7	3605	/* NOTE : This function should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	3606	the HAL_I2C_AddrCallback can be implemented in the user file
<>	144:ef7eb2e8f9f7	3607	*/
<>	144:ef7eb2e8f9f7	3608	}
<>	144:ef7eb2e8f9f7	3609
<>	144:ef7eb2e8f9f7	3610	/**
<>	144:ef7eb2e8f9f7	3611	* @brief Listen Complete callback.
<>	144:ef7eb2e8f9f7	3612	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	3613	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	3614	* @retval None
<>	144:ef7eb2e8f9f7	3615	*/
<>	144:ef7eb2e8f9f7	3616	__weak void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c)
<>	144:ef7eb2e8f9f7	3617	{
<>	144:ef7eb2e8f9f7	3618	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	3619	UNUSED(hi2c);
AnnaBridge	167:e84263d55307	3620
<>	144:ef7eb2e8f9f7	3621	/* NOTE : This function should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	3622	the HAL_I2C_ListenCpltCallback can be implemented in the user file
<>	144:ef7eb2e8f9f7	3623	*/
<>	144:ef7eb2e8f9f7	3624	}
<>	144:ef7eb2e8f9f7	3625
<>	144:ef7eb2e8f9f7	3626	/**
AnnaBridge	167:e84263d55307	3627	* @brief Memory Tx Transfer completed callback.
<>	144:ef7eb2e8f9f7	3628	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
AnnaBridge	167:e84263d55307	3629	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	3630	* @retval None
<>	144:ef7eb2e8f9f7	3631	*/
<>	144:ef7eb2e8f9f7	3632	__weak void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c)
<>	144:ef7eb2e8f9f7	3633	{
<>	144:ef7eb2e8f9f7	3634	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	3635	UNUSED(hi2c);
AnnaBridge	167:e84263d55307	3636
<>	144:ef7eb2e8f9f7	3637	/* NOTE : This function should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	3638	the HAL_I2C_MemTxCpltCallback can be implemented in the user file
<>	144:ef7eb2e8f9f7	3639	*/
<>	144:ef7eb2e8f9f7	3640	}
<>	144:ef7eb2e8f9f7	3641
<>	144:ef7eb2e8f9f7	3642	/**
AnnaBridge	167:e84263d55307	3643	* @brief Memory Rx Transfer completed callback.
<>	144:ef7eb2e8f9f7	3644	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
AnnaBridge	167:e84263d55307	3645	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	3646	* @retval None
<>	144:ef7eb2e8f9f7	3647	*/
<>	144:ef7eb2e8f9f7	3648	__weak void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c)
<>	144:ef7eb2e8f9f7	3649	{
<>	144:ef7eb2e8f9f7	3650	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	3651	UNUSED(hi2c);
AnnaBridge	167:e84263d55307	3652
<>	144:ef7eb2e8f9f7	3653	/* NOTE : This function should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	3654	the HAL_I2C_MemRxCpltCallback can be implemented in the user file
<>	144:ef7eb2e8f9f7	3655	*/
<>	144:ef7eb2e8f9f7	3656	}
<>	144:ef7eb2e8f9f7	3657
<>	144:ef7eb2e8f9f7	3658	/**
AnnaBridge	167:e84263d55307	3659	* @brief I2C error callback.
<>	144:ef7eb2e8f9f7	3660	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
AnnaBridge	167:e84263d55307	3661	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	3662	* @retval None
<>	144:ef7eb2e8f9f7	3663	*/
<>	144:ef7eb2e8f9f7	3664	__weak void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c)
<>	144:ef7eb2e8f9f7	3665	{
<>	144:ef7eb2e8f9f7	3666	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	3667	UNUSED(hi2c);
AnnaBridge	167:e84263d55307	3668
<>	144:ef7eb2e8f9f7	3669	/* NOTE : This function should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	3670	the HAL_I2C_ErrorCallback can be implemented in the user file
<>	144:ef7eb2e8f9f7	3671	*/
<>	144:ef7eb2e8f9f7	3672	}
<>	144:ef7eb2e8f9f7	3673
<>	144:ef7eb2e8f9f7	3674	/**
<>	144:ef7eb2e8f9f7	3675	* @brief I2C abort callback.
<>	144:ef7eb2e8f9f7	3676	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	3677	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	3678	* @retval None
<>	144:ef7eb2e8f9f7	3679	*/
<>	144:ef7eb2e8f9f7	3680	__weak void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c)
<>	144:ef7eb2e8f9f7	3681	{
<>	144:ef7eb2e8f9f7	3682	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	3683	UNUSED(hi2c);
<>	144:ef7eb2e8f9f7	3684
<>	144:ef7eb2e8f9f7	3685	/* NOTE : This function should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	3686	the HAL_I2C_AbortCpltCallback could be implemented in the user file
<>	144:ef7eb2e8f9f7	3687	*/
<>	144:ef7eb2e8f9f7	3688	}
<>	144:ef7eb2e8f9f7	3689
<>	144:ef7eb2e8f9f7	3690	/**
<>	144:ef7eb2e8f9f7	3691	* @}
<>	144:ef7eb2e8f9f7	3692	*/
<>	144:ef7eb2e8f9f7	3693
AnnaBridge	167:e84263d55307	3694	/** @defgroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions
<>	144:ef7eb2e8f9f7	3695	* @brief Peripheral State and Errors functions
<>	144:ef7eb2e8f9f7	3696	*
<>	144:ef7eb2e8f9f7	3697	@verbatim
<>	144:ef7eb2e8f9f7	3698	===============================================================================
AnnaBridge	167:e84263d55307	3699	##### Peripheral State, Mode and Error functions #####
<>	144:ef7eb2e8f9f7	3700	===============================================================================
<>	144:ef7eb2e8f9f7	3701	[..]
<>	144:ef7eb2e8f9f7	3702	This subsection permits to get in run-time the status of the peripheral
<>	144:ef7eb2e8f9f7	3703	and the data flow.
<>	144:ef7eb2e8f9f7	3704
<>	144:ef7eb2e8f9f7	3705	@endverbatim
<>	144:ef7eb2e8f9f7	3706	* @{
<>	144:ef7eb2e8f9f7	3707	*/
<>	144:ef7eb2e8f9f7	3708
<>	144:ef7eb2e8f9f7	3709	/**
AnnaBridge	167:e84263d55307	3710	* @brief Return the I2C handle state.
<>	144:ef7eb2e8f9f7	3711	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
AnnaBridge	167:e84263d55307	3712	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	3713	* @retval HAL state
<>	144:ef7eb2e8f9f7	3714	*/
<>	144:ef7eb2e8f9f7	3715	HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c)
<>	144:ef7eb2e8f9f7	3716	{
AnnaBridge	167:e84263d55307	3717	/* Return I2C handle state */
<>	144:ef7eb2e8f9f7	3718	return hi2c->State;
<>	144:ef7eb2e8f9f7	3719	}
<>	144:ef7eb2e8f9f7	3720
<>	144:ef7eb2e8f9f7	3721	/**
AnnaBridge	167:e84263d55307	3722	* @brief Return the I2C Master, Slave, Memory or no mode.
<>	144:ef7eb2e8f9f7	3723	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	3724	* the configuration information for I2C module
<>	144:ef7eb2e8f9f7	3725	* @retval HAL mode
<>	144:ef7eb2e8f9f7	3726	*/
<>	144:ef7eb2e8f9f7	3727	HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c)
<>	144:ef7eb2e8f9f7	3728	{
<>	144:ef7eb2e8f9f7	3729	return hi2c->Mode;
<>	144:ef7eb2e8f9f7	3730	}
<>	144:ef7eb2e8f9f7	3731
<>	144:ef7eb2e8f9f7	3732	/**
<>	144:ef7eb2e8f9f7	3733	* @brief Return the I2C error code
<>	144:ef7eb2e8f9f7	3734	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	3735	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	3736	* @retval I2C Error Code
<>	144:ef7eb2e8f9f7	3737	*/
<>	144:ef7eb2e8f9f7	3738	uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c)
<>	144:ef7eb2e8f9f7	3739	{
<>	144:ef7eb2e8f9f7	3740	return hi2c->ErrorCode;
<>	144:ef7eb2e8f9f7	3741	}
<>	144:ef7eb2e8f9f7	3742
<>	144:ef7eb2e8f9f7	3743	/**
<>	144:ef7eb2e8f9f7	3744	* @}
<>	144:ef7eb2e8f9f7	3745	*/
<>	144:ef7eb2e8f9f7	3746
<>	144:ef7eb2e8f9f7	3747	/**
<>	144:ef7eb2e8f9f7	3748	* @brief Handle TXE flag for Master
<>	144:ef7eb2e8f9f7	3749	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	3750	* the configuration information for I2C module
<>	144:ef7eb2e8f9f7	3751	* @retval HAL status
<>	144:ef7eb2e8f9f7	3752	*/
<>	144:ef7eb2e8f9f7	3753	static HAL_StatusTypeDef I2C_MasterTransmit_TXE(I2C_HandleTypeDef *hi2c)
<>	144:ef7eb2e8f9f7	3754	{
<>	144:ef7eb2e8f9f7	3755	/* Declaration of temporary variables to prevent undefined behavior of volatile usage */
<>	144:ef7eb2e8f9f7	3756	uint32_t CurrentState = hi2c->State;
<>	144:ef7eb2e8f9f7	3757	uint32_t CurrentMode = hi2c->Mode;
<>	144:ef7eb2e8f9f7	3758	uint32_t CurrentXferOptions = hi2c->XferOptions;
<>	144:ef7eb2e8f9f7	3759
<>	144:ef7eb2e8f9f7	3760	if((hi2c->XferSize == 0U) && (CurrentState == HAL_I2C_STATE_BUSY_TX))
<>	144:ef7eb2e8f9f7	3761	{
<>	144:ef7eb2e8f9f7	3762	/* Call TxCpltCallback() directly if no stop mode is set */
<>	144:ef7eb2e8f9f7	3763	if((CurrentXferOptions != I2C_FIRST_AND_LAST_FRAME) && (CurrentXferOptions != I2C_LAST_FRAME) && (CurrentXferOptions != I2C_NO_OPTION_FRAME))
<>	144:ef7eb2e8f9f7	3764	{
<>	144:ef7eb2e8f9f7	3765	__HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT \| I2C_IT_BUF \| I2C_IT_ERR);
AnnaBridge	167:e84263d55307	3766
AnnaBridge	167:e84263d55307	3767	hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX;
<>	144:ef7eb2e8f9f7	3768	hi2c->Mode = HAL_I2C_MODE_NONE;
<>	144:ef7eb2e8f9f7	3769	hi2c->State = HAL_I2C_STATE_READY;
AnnaBridge	167:e84263d55307	3770
<>	144:ef7eb2e8f9f7	3771	HAL_I2C_MasterTxCpltCallback(hi2c);
<>	144:ef7eb2e8f9f7	3772	}
<>	144:ef7eb2e8f9f7	3773	else /* Generate Stop condition then Call TxCpltCallback() */
<>	144:ef7eb2e8f9f7	3774	{
<>	144:ef7eb2e8f9f7	3775	/* Disable EVT, BUF and ERR interrupt */
<>	144:ef7eb2e8f9f7	3776	__HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT \| I2C_IT_BUF \| I2C_IT_ERR);
AnnaBridge	167:e84263d55307	3777
<>	144:ef7eb2e8f9f7	3778	/* Generate Stop */
<>	144:ef7eb2e8f9f7	3779	hi2c->Instance->CR1 \|= I2C_CR1_STOP;
<>	148:21d94c44109e	3780
<>	144:ef7eb2e8f9f7	3781	hi2c->PreviousState = I2C_STATE_NONE;
<>	144:ef7eb2e8f9f7	3782	hi2c->State = HAL_I2C_STATE_READY;
AnnaBridge	167:e84263d55307	3783
<>	144:ef7eb2e8f9f7	3784	if(hi2c->Mode == HAL_I2C_MODE_MEM)
<>	144:ef7eb2e8f9f7	3785	{
<>	144:ef7eb2e8f9f7	3786	hi2c->Mode = HAL_I2C_MODE_NONE;
<>	144:ef7eb2e8f9f7	3787	HAL_I2C_MemTxCpltCallback(hi2c);
<>	144:ef7eb2e8f9f7	3788	}
<>	144:ef7eb2e8f9f7	3789	else
<>	144:ef7eb2e8f9f7	3790	{
<>	144:ef7eb2e8f9f7	3791	hi2c->Mode = HAL_I2C_MODE_NONE;
<>	144:ef7eb2e8f9f7	3792	HAL_I2C_MasterTxCpltCallback(hi2c);
<>	144:ef7eb2e8f9f7	3793	}
<>	144:ef7eb2e8f9f7	3794	}
<>	144:ef7eb2e8f9f7	3795	}
<>	144:ef7eb2e8f9f7	3796	else if((CurrentState == HAL_I2C_STATE_BUSY_TX) \|\| \
<>	144:ef7eb2e8f9f7	3797	((CurrentMode == HAL_I2C_MODE_MEM) && (CurrentState == HAL_I2C_STATE_BUSY_RX)))
<>	144:ef7eb2e8f9f7	3798	{
<>	144:ef7eb2e8f9f7	3799	if(hi2c->XferCount == 0U)
<>	144:ef7eb2e8f9f7	3800	{
<>	144:ef7eb2e8f9f7	3801	/* Disable BUF interrupt */
<>	144:ef7eb2e8f9f7	3802	__HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF);
<>	144:ef7eb2e8f9f7	3803	}
<>	144:ef7eb2e8f9f7	3804	else
<>	144:ef7eb2e8f9f7	3805	{
<>	144:ef7eb2e8f9f7	3806	if(hi2c->Mode == HAL_I2C_MODE_MEM)
<>	144:ef7eb2e8f9f7	3807	{
<>	144:ef7eb2e8f9f7	3808	if(hi2c->EventCount == 0)
<>	144:ef7eb2e8f9f7	3809	{
<>	144:ef7eb2e8f9f7	3810	/* If Memory address size is 8Bit */
<>	144:ef7eb2e8f9f7	3811	if(hi2c->MemaddSize == I2C_MEMADD_SIZE_8BIT)
<>	144:ef7eb2e8f9f7	3812	{
<>	144:ef7eb2e8f9f7	3813	/* Send Memory Address */
<>	144:ef7eb2e8f9f7	3814	hi2c->Instance->DR = I2C_MEM_ADD_LSB(hi2c->Memaddress);
<>	144:ef7eb2e8f9f7	3815
<>	144:ef7eb2e8f9f7	3816	hi2c->EventCount += 2;
<>	144:ef7eb2e8f9f7	3817	}
<>	144:ef7eb2e8f9f7	3818	/* If Memory address size is 16Bit */
<>	144:ef7eb2e8f9f7	3819	else
<>	144:ef7eb2e8f9f7	3820	{
<>	144:ef7eb2e8f9f7	3821	/* Send MSB of Memory Address */
<>	144:ef7eb2e8f9f7	3822	hi2c->Instance->DR = I2C_MEM_ADD_MSB(hi2c->Memaddress);
<>	144:ef7eb2e8f9f7	3823
<>	144:ef7eb2e8f9f7	3824	hi2c->EventCount++;
<>	144:ef7eb2e8f9f7	3825	}
<>	144:ef7eb2e8f9f7	3826	}
<>	144:ef7eb2e8f9f7	3827	else if(hi2c->EventCount == 1)
<>	144:ef7eb2e8f9f7	3828	{
<>	144:ef7eb2e8f9f7	3829	/* Send LSB of Memory Address */
<>	144:ef7eb2e8f9f7	3830	hi2c->Instance->DR = I2C_MEM_ADD_LSB(hi2c->Memaddress);
<>	144:ef7eb2e8f9f7	3831
<>	144:ef7eb2e8f9f7	3832	hi2c->EventCount++;
<>	144:ef7eb2e8f9f7	3833	}
<>	144:ef7eb2e8f9f7	3834	else if(hi2c->EventCount == 2)
<>	144:ef7eb2e8f9f7	3835	{
<>	144:ef7eb2e8f9f7	3836	if(hi2c->State == HAL_I2C_STATE_BUSY_RX)
<>	144:ef7eb2e8f9f7	3837	{
<>	144:ef7eb2e8f9f7	3838	/* Generate Restart */
<>	144:ef7eb2e8f9f7	3839	hi2c->Instance->CR1 \|= I2C_CR1_START;
<>	144:ef7eb2e8f9f7	3840	}
<>	144:ef7eb2e8f9f7	3841	else if(hi2c->State == HAL_I2C_STATE_BUSY_TX)
<>	144:ef7eb2e8f9f7	3842	{
<>	144:ef7eb2e8f9f7	3843	/* Write data to DR */
<>	144:ef7eb2e8f9f7	3844	hi2c->Instance->DR = (*hi2c->pBuffPtr++);
<>	144:ef7eb2e8f9f7	3845	hi2c->XferCount--;
<>	144:ef7eb2e8f9f7	3846	}
<>	144:ef7eb2e8f9f7	3847	}
<>	144:ef7eb2e8f9f7	3848	}
<>	144:ef7eb2e8f9f7	3849	else
<>	144:ef7eb2e8f9f7	3850	{
<>	144:ef7eb2e8f9f7	3851	/* Write data to DR */
<>	144:ef7eb2e8f9f7	3852	hi2c->Instance->DR = (*hi2c->pBuffPtr++);
<>	144:ef7eb2e8f9f7	3853	hi2c->XferCount--;
<>	144:ef7eb2e8f9f7	3854	}
<>	144:ef7eb2e8f9f7	3855	}
<>	144:ef7eb2e8f9f7	3856	}
<>	144:ef7eb2e8f9f7	3857	return HAL_OK;
<>	144:ef7eb2e8f9f7	3858	}
<>	144:ef7eb2e8f9f7	3859
<>	144:ef7eb2e8f9f7	3860	/**
<>	144:ef7eb2e8f9f7	3861	* @brief Handle BTF flag for Master transmitter
<>	144:ef7eb2e8f9f7	3862	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	3863	* the configuration information for I2C module
<>	144:ef7eb2e8f9f7	3864	* @retval HAL status
<>	144:ef7eb2e8f9f7	3865	*/
<>	144:ef7eb2e8f9f7	3866	static HAL_StatusTypeDef I2C_MasterTransmit_BTF(I2C_HandleTypeDef *hi2c)
<>	144:ef7eb2e8f9f7	3867	{
<>	144:ef7eb2e8f9f7	3868	/* Declaration of temporary variables to prevent undefined behavior of volatile usage */
<>	144:ef7eb2e8f9f7	3869	uint32_t CurrentXferOptions = hi2c->XferOptions;
<>	144:ef7eb2e8f9f7	3870
<>	144:ef7eb2e8f9f7	3871	if(hi2c->State == HAL_I2C_STATE_BUSY_TX)
<>	144:ef7eb2e8f9f7	3872	{
<>	144:ef7eb2e8f9f7	3873	if(hi2c->XferCount != 0U)
<>	144:ef7eb2e8f9f7	3874	{
<>	144:ef7eb2e8f9f7	3875	/* Write data to DR */
<>	144:ef7eb2e8f9f7	3876	hi2c->Instance->DR = (*hi2c->pBuffPtr++);
<>	144:ef7eb2e8f9f7	3877	hi2c->XferCount--;
<>	144:ef7eb2e8f9f7	3878	}
<>	144:ef7eb2e8f9f7	3879	else
<>	144:ef7eb2e8f9f7	3880	{
<>	144:ef7eb2e8f9f7	3881	/* Call TxCpltCallback() directly if no stop mode is set */
<>	144:ef7eb2e8f9f7	3882	if((CurrentXferOptions != I2C_FIRST_AND_LAST_FRAME) && (CurrentXferOptions != I2C_LAST_FRAME) && (CurrentXferOptions != I2C_NO_OPTION_FRAME))
<>	144:ef7eb2e8f9f7	3883	{
<>	144:ef7eb2e8f9f7	3884	__HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT \| I2C_IT_BUF \| I2C_IT_ERR);
<>	144:ef7eb2e8f9f7	3885
AnnaBridge	167:e84263d55307	3886	hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX;
<>	144:ef7eb2e8f9f7	3887	hi2c->Mode = HAL_I2C_MODE_NONE;
<>	144:ef7eb2e8f9f7	3888	hi2c->State = HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	3889
<>	144:ef7eb2e8f9f7	3890	HAL_I2C_MasterTxCpltCallback(hi2c);
<>	144:ef7eb2e8f9f7	3891	}
<>	144:ef7eb2e8f9f7	3892	else /* Generate Stop condition then Call TxCpltCallback() */
<>	144:ef7eb2e8f9f7	3893	{
<>	144:ef7eb2e8f9f7	3894	/* Disable EVT, BUF and ERR interrupt */
<>	144:ef7eb2e8f9f7	3895	__HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT \| I2C_IT_BUF \| I2C_IT_ERR);
<>	144:ef7eb2e8f9f7	3896
<>	144:ef7eb2e8f9f7	3897	/* Generate Stop */
<>	144:ef7eb2e8f9f7	3898	hi2c->Instance->CR1 \|= I2C_CR1_STOP;
<>	144:ef7eb2e8f9f7	3899
<>	144:ef7eb2e8f9f7	3900	hi2c->PreviousState = I2C_STATE_NONE;
<>	144:ef7eb2e8f9f7	3901	hi2c->State = HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	3902
<>	144:ef7eb2e8f9f7	3903	if(hi2c->Mode == HAL_I2C_MODE_MEM)
<>	144:ef7eb2e8f9f7	3904	{
<>	144:ef7eb2e8f9f7	3905	hi2c->Mode = HAL_I2C_MODE_NONE;
<>	144:ef7eb2e8f9f7	3906
<>	144:ef7eb2e8f9f7	3907	HAL_I2C_MemTxCpltCallback(hi2c);
<>	144:ef7eb2e8f9f7	3908	}
<>	144:ef7eb2e8f9f7	3909	else
<>	144:ef7eb2e8f9f7	3910	{
<>	144:ef7eb2e8f9f7	3911	hi2c->Mode = HAL_I2C_MODE_NONE;
<>	144:ef7eb2e8f9f7	3912
<>	144:ef7eb2e8f9f7	3913	HAL_I2C_MasterTxCpltCallback(hi2c);
<>	144:ef7eb2e8f9f7	3914	}
<>	144:ef7eb2e8f9f7	3915	}
<>	144:ef7eb2e8f9f7	3916	}
<>	144:ef7eb2e8f9f7	3917	}
<>	144:ef7eb2e8f9f7	3918	return HAL_OK;
<>	144:ef7eb2e8f9f7	3919	}
<>	144:ef7eb2e8f9f7	3920
<>	144:ef7eb2e8f9f7	3921	/**
<>	144:ef7eb2e8f9f7	3922	* @brief Handle RXNE flag for Master
<>	144:ef7eb2e8f9f7	3923	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	3924	* the configuration information for I2C module
<>	144:ef7eb2e8f9f7	3925	* @retval HAL status
<>	144:ef7eb2e8f9f7	3926	*/
<>	144:ef7eb2e8f9f7	3927	static HAL_StatusTypeDef I2C_MasterReceive_RXNE(I2C_HandleTypeDef *hi2c)
<>	144:ef7eb2e8f9f7	3928	{
<>	148:21d94c44109e	3929
<>	144:ef7eb2e8f9f7	3930	if(hi2c->State == HAL_I2C_STATE_BUSY_RX)
<>	144:ef7eb2e8f9f7	3931	{
<>	144:ef7eb2e8f9f7	3932	uint32_t tmp = 0U;
<>	144:ef7eb2e8f9f7	3933
<>	144:ef7eb2e8f9f7	3934	tmp = hi2c->XferCount;
<>	144:ef7eb2e8f9f7	3935	if(tmp > 3U)
<>	144:ef7eb2e8f9f7	3936	{
<>	144:ef7eb2e8f9f7	3937	/* Read data from DR */
<>	144:ef7eb2e8f9f7	3938	(*hi2c->pBuffPtr++) = hi2c->Instance->DR;
<>	144:ef7eb2e8f9f7	3939	hi2c->XferCount--;
<>	144:ef7eb2e8f9f7	3940	}
<>	144:ef7eb2e8f9f7	3941	else if((tmp == 2U) \|\| (tmp == 3U))
<>	144:ef7eb2e8f9f7	3942	{
<>	148:21d94c44109e	3943	/* Disable Acknowledge */
<>	148:21d94c44109e	3944	hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
AnnaBridge	167:e84263d55307	3945
<>	148:21d94c44109e	3946	/* Enable Pos */
<>	148:21d94c44109e	3947	hi2c->Instance->CR1 \|= I2C_CR1_POS;
<>	144:ef7eb2e8f9f7	3948
<>	144:ef7eb2e8f9f7	3949	/* Disable BUF interrupt */
<>	144:ef7eb2e8f9f7	3950	__HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF);
<>	144:ef7eb2e8f9f7	3951	}
<>	144:ef7eb2e8f9f7	3952	else
<>	144:ef7eb2e8f9f7	3953	{
<>	148:21d94c44109e	3954	/* Disable Acknowledge */
<>	148:21d94c44109e	3955	hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
<>	148:21d94c44109e	3956
<>	148:21d94c44109e	3957	if(hi2c->XferOptions == I2C_NEXT_FRAME)
<>	144:ef7eb2e8f9f7	3958	{
<>	148:21d94c44109e	3959	/* Enable Pos */
<>	148:21d94c44109e	3960	hi2c->Instance->CR1 \|= I2C_CR1_POS;
<>	144:ef7eb2e8f9f7	3961	}
<>	144:ef7eb2e8f9f7	3962
<>	144:ef7eb2e8f9f7	3963	/* Disable EVT, BUF and ERR interrupt */
<>	144:ef7eb2e8f9f7	3964	__HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT \| I2C_IT_BUF \| I2C_IT_ERR);
<>	144:ef7eb2e8f9f7	3965
<>	144:ef7eb2e8f9f7	3966	/* Read data from DR */
<>	144:ef7eb2e8f9f7	3967	(*hi2c->pBuffPtr++) = hi2c->Instance->DR;
<>	144:ef7eb2e8f9f7	3968	hi2c->XferCount--;
<>	144:ef7eb2e8f9f7	3969
<>	144:ef7eb2e8f9f7	3970	hi2c->State = HAL_I2C_STATE_READY;
AnnaBridge	167:e84263d55307	3971	hi2c->PreviousState = I2C_STATE_NONE;
<>	144:ef7eb2e8f9f7	3972
<>	144:ef7eb2e8f9f7	3973	if(hi2c->Mode == HAL_I2C_MODE_MEM)
<>	144:ef7eb2e8f9f7	3974	{
<>	144:ef7eb2e8f9f7	3975	hi2c->Mode = HAL_I2C_MODE_NONE;
<>	144:ef7eb2e8f9f7	3976	HAL_I2C_MemRxCpltCallback(hi2c);
<>	144:ef7eb2e8f9f7	3977	}
<>	144:ef7eb2e8f9f7	3978	else
<>	144:ef7eb2e8f9f7	3979	{
<>	144:ef7eb2e8f9f7	3980	hi2c->Mode = HAL_I2C_MODE_NONE;
<>	144:ef7eb2e8f9f7	3981	HAL_I2C_MasterRxCpltCallback(hi2c);
<>	144:ef7eb2e8f9f7	3982	}
<>	144:ef7eb2e8f9f7	3983	}
<>	144:ef7eb2e8f9f7	3984	}
<>	144:ef7eb2e8f9f7	3985	return HAL_OK;
<>	144:ef7eb2e8f9f7	3986	}
<>	144:ef7eb2e8f9f7	3987
<>	144:ef7eb2e8f9f7	3988	/**
<>	144:ef7eb2e8f9f7	3989	* @brief Handle BTF flag for Master receiver
<>	144:ef7eb2e8f9f7	3990	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	3991	* the configuration information for I2C module
<>	144:ef7eb2e8f9f7	3992	* @retval HAL status
<>	144:ef7eb2e8f9f7	3993	*/
<>	144:ef7eb2e8f9f7	3994	static HAL_StatusTypeDef I2C_MasterReceive_BTF(I2C_HandleTypeDef *hi2c)
<>	144:ef7eb2e8f9f7	3995	{
<>	144:ef7eb2e8f9f7	3996	/* Declaration of temporary variables to prevent undefined behavior of volatile usage */
<>	144:ef7eb2e8f9f7	3997	uint32_t CurrentXferOptions = hi2c->XferOptions;
<>	144:ef7eb2e8f9f7	3998
<>	144:ef7eb2e8f9f7	3999	if(hi2c->XferCount == 3U)
<>	144:ef7eb2e8f9f7	4000	{
<>	144:ef7eb2e8f9f7	4001	if((CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) \|\| (CurrentXferOptions == I2C_LAST_FRAME) \|\| (CurrentXferOptions == I2C_NO_OPTION_FRAME))
<>	144:ef7eb2e8f9f7	4002	{
<>	144:ef7eb2e8f9f7	4003	/* Disable Acknowledge */
<>	144:ef7eb2e8f9f7	4004	hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
<>	144:ef7eb2e8f9f7	4005	}
<>	144:ef7eb2e8f9f7	4006
<>	144:ef7eb2e8f9f7	4007	/* Read data from DR */
<>	144:ef7eb2e8f9f7	4008	(*hi2c->pBuffPtr++) = hi2c->Instance->DR;
<>	144:ef7eb2e8f9f7	4009	hi2c->XferCount--;
<>	144:ef7eb2e8f9f7	4010	}
<>	144:ef7eb2e8f9f7	4011	else if(hi2c->XferCount == 2U)
<>	144:ef7eb2e8f9f7	4012	{
<>	144:ef7eb2e8f9f7	4013	/* Prepare next transfer or stop current transfer */
<>	144:ef7eb2e8f9f7	4014	if((CurrentXferOptions != I2C_FIRST_AND_LAST_FRAME) && (CurrentXferOptions != I2C_LAST_FRAME) && (CurrentXferOptions != I2C_NO_OPTION_FRAME))
<>	144:ef7eb2e8f9f7	4015	{
<>	148:21d94c44109e	4016	/* Disable Acknowledge */
<>	148:21d94c44109e	4017	hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
Kojto	170:19eb464bc2be	4018
Kojto	170:19eb464bc2be	4019	if((CurrentXferOptions == I2C_NEXT_FRAME) \|\| (CurrentXferOptions == I2C_FIRST_FRAME))
Kojto	170:19eb464bc2be	4020	{
Kojto	170:19eb464bc2be	4021	/* Generate ReStart */
Kojto	170:19eb464bc2be	4022	hi2c->Instance->CR1 \|= I2C_CR1_START;
Kojto	170:19eb464bc2be	4023	}
<>	144:ef7eb2e8f9f7	4024	}
<>	144:ef7eb2e8f9f7	4025	else
<>	144:ef7eb2e8f9f7	4026	{
<>	144:ef7eb2e8f9f7	4027	/* Generate Stop */
<>	144:ef7eb2e8f9f7	4028	hi2c->Instance->CR1 \|= I2C_CR1_STOP;
<>	144:ef7eb2e8f9f7	4029	}
<>	144:ef7eb2e8f9f7	4030
<>	144:ef7eb2e8f9f7	4031	/* Read data from DR */
<>	144:ef7eb2e8f9f7	4032	(*hi2c->pBuffPtr++) = hi2c->Instance->DR;
<>	144:ef7eb2e8f9f7	4033	hi2c->XferCount--;
<>	144:ef7eb2e8f9f7	4034
<>	144:ef7eb2e8f9f7	4035	/* Read data from DR */
<>	144:ef7eb2e8f9f7	4036	(*hi2c->pBuffPtr++) = hi2c->Instance->DR;
<>	144:ef7eb2e8f9f7	4037	hi2c->XferCount--;
<>	144:ef7eb2e8f9f7	4038
<>	144:ef7eb2e8f9f7	4039	/* Disable EVT and ERR interrupt */
<>	144:ef7eb2e8f9f7	4040	__HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT \| I2C_IT_ERR);
<>	144:ef7eb2e8f9f7	4041
<>	144:ef7eb2e8f9f7	4042	hi2c->State = HAL_I2C_STATE_READY;
<>	151:5eaa88a5bcc7	4043	hi2c->PreviousState = I2C_STATE_NONE;
<>	151:5eaa88a5bcc7	4044
<>	144:ef7eb2e8f9f7	4045	if(hi2c->Mode == HAL_I2C_MODE_MEM)
<>	144:ef7eb2e8f9f7	4046	{
<>	144:ef7eb2e8f9f7	4047	hi2c->Mode = HAL_I2C_MODE_NONE;
<>	144:ef7eb2e8f9f7	4048
<>	144:ef7eb2e8f9f7	4049	HAL_I2C_MemRxCpltCallback(hi2c);
<>	144:ef7eb2e8f9f7	4050	}
<>	144:ef7eb2e8f9f7	4051	else
<>	144:ef7eb2e8f9f7	4052	{
<>	144:ef7eb2e8f9f7	4053	hi2c->Mode = HAL_I2C_MODE_NONE;
<>	144:ef7eb2e8f9f7	4054
<>	144:ef7eb2e8f9f7	4055	HAL_I2C_MasterRxCpltCallback(hi2c);
<>	144:ef7eb2e8f9f7	4056	}
<>	144:ef7eb2e8f9f7	4057	}
<>	144:ef7eb2e8f9f7	4058	else
<>	144:ef7eb2e8f9f7	4059	{
<>	144:ef7eb2e8f9f7	4060	/* Read data from DR */
<>	144:ef7eb2e8f9f7	4061	(*hi2c->pBuffPtr++) = hi2c->Instance->DR;
<>	144:ef7eb2e8f9f7	4062	hi2c->XferCount--;
<>	144:ef7eb2e8f9f7	4063	}
<>	144:ef7eb2e8f9f7	4064	return HAL_OK;
<>	144:ef7eb2e8f9f7	4065	}
<>	144:ef7eb2e8f9f7	4066
<>	144:ef7eb2e8f9f7	4067	/**
<>	144:ef7eb2e8f9f7	4068	* @brief Handle SB flag for Master
<>	144:ef7eb2e8f9f7	4069	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	4070	* the configuration information for I2C module
<>	144:ef7eb2e8f9f7	4071	* @retval HAL status
<>	144:ef7eb2e8f9f7	4072	*/
<>	144:ef7eb2e8f9f7	4073	static HAL_StatusTypeDef I2C_Master_SB(I2C_HandleTypeDef *hi2c)
<>	144:ef7eb2e8f9f7	4074	{
<>	144:ef7eb2e8f9f7	4075	if(hi2c->Mode == HAL_I2C_MODE_MEM)
<>	144:ef7eb2e8f9f7	4076	{
<>	144:ef7eb2e8f9f7	4077	if(hi2c->EventCount == 0U)
<>	144:ef7eb2e8f9f7	4078	{
<>	144:ef7eb2e8f9f7	4079	/* Send slave address */
<>	144:ef7eb2e8f9f7	4080	hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(hi2c->Devaddress);
<>	144:ef7eb2e8f9f7	4081	}
<>	144:ef7eb2e8f9f7	4082	else
<>	144:ef7eb2e8f9f7	4083	{
<>	144:ef7eb2e8f9f7	4084	hi2c->Instance->DR = I2C_7BIT_ADD_READ(hi2c->Devaddress);
<>	144:ef7eb2e8f9f7	4085	}
<>	144:ef7eb2e8f9f7	4086	}
<>	144:ef7eb2e8f9f7	4087	else
<>	144:ef7eb2e8f9f7	4088	{
<>	144:ef7eb2e8f9f7	4089	if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
<>	144:ef7eb2e8f9f7	4090	{
<>	144:ef7eb2e8f9f7	4091	/* Send slave 7 Bits address */
<>	144:ef7eb2e8f9f7	4092	if(hi2c->State == HAL_I2C_STATE_BUSY_TX)
<>	144:ef7eb2e8f9f7	4093	{
<>	144:ef7eb2e8f9f7	4094	hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(hi2c->Devaddress);
<>	144:ef7eb2e8f9f7	4095	}
<>	144:ef7eb2e8f9f7	4096	else
<>	144:ef7eb2e8f9f7	4097	{
<>	144:ef7eb2e8f9f7	4098	hi2c->Instance->DR = I2C_7BIT_ADD_READ(hi2c->Devaddress);
<>	144:ef7eb2e8f9f7	4099	}
<>	144:ef7eb2e8f9f7	4100	}
<>	144:ef7eb2e8f9f7	4101	else
<>	144:ef7eb2e8f9f7	4102	{
<>	144:ef7eb2e8f9f7	4103	if(hi2c->EventCount == 0U)
<>	144:ef7eb2e8f9f7	4104	{
<>	144:ef7eb2e8f9f7	4105	/* Send header of slave address */
<>	144:ef7eb2e8f9f7	4106	hi2c->Instance->DR = I2C_10BIT_HEADER_WRITE(hi2c->Devaddress);
<>	144:ef7eb2e8f9f7	4107	}
<>	144:ef7eb2e8f9f7	4108	else if(hi2c->EventCount == 1U)
<>	144:ef7eb2e8f9f7	4109	{
<>	144:ef7eb2e8f9f7	4110	/* Send header of slave address */
<>	144:ef7eb2e8f9f7	4111	hi2c->Instance->DR = I2C_10BIT_HEADER_READ(hi2c->Devaddress);
<>	144:ef7eb2e8f9f7	4112	}
<>	144:ef7eb2e8f9f7	4113	}
<>	144:ef7eb2e8f9f7	4114	}
<>	144:ef7eb2e8f9f7	4115
<>	144:ef7eb2e8f9f7	4116	return HAL_OK;
<>	144:ef7eb2e8f9f7	4117	}
<>	144:ef7eb2e8f9f7	4118
<>	144:ef7eb2e8f9f7	4119	/**
<>	144:ef7eb2e8f9f7	4120	* @brief Handle ADD10 flag for Master
<>	144:ef7eb2e8f9f7	4121	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	4122	* the configuration information for I2C module
<>	144:ef7eb2e8f9f7	4123	* @retval HAL status
<>	144:ef7eb2e8f9f7	4124	*/
<>	144:ef7eb2e8f9f7	4125	static HAL_StatusTypeDef I2C_Master_ADD10(I2C_HandleTypeDef *hi2c)
<>	144:ef7eb2e8f9f7	4126	{
<>	144:ef7eb2e8f9f7	4127	/* Send slave address */
<>	144:ef7eb2e8f9f7	4128	hi2c->Instance->DR = I2C_10BIT_ADDRESS(hi2c->Devaddress);
<>	144:ef7eb2e8f9f7	4129
<>	144:ef7eb2e8f9f7	4130	return HAL_OK;
<>	144:ef7eb2e8f9f7	4131	}
<>	144:ef7eb2e8f9f7	4132
<>	144:ef7eb2e8f9f7	4133	/**
<>	144:ef7eb2e8f9f7	4134	* @brief Handle ADDR flag for Master
<>	144:ef7eb2e8f9f7	4135	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	4136	* the configuration information for I2C module
<>	144:ef7eb2e8f9f7	4137	* @retval HAL status
<>	144:ef7eb2e8f9f7	4138	*/
<>	144:ef7eb2e8f9f7	4139	static HAL_StatusTypeDef I2C_Master_ADDR(I2C_HandleTypeDef *hi2c)
<>	144:ef7eb2e8f9f7	4140	{
<>	144:ef7eb2e8f9f7	4141	/* Declaration of temporary variable to prevent undefined behavior of volatile usage */
<>	144:ef7eb2e8f9f7	4142	uint32_t CurrentMode = hi2c->Mode;
<>	144:ef7eb2e8f9f7	4143	uint32_t CurrentXferOptions = hi2c->XferOptions;
<>	144:ef7eb2e8f9f7	4144	uint32_t Prev_State = hi2c->PreviousState;
AnnaBridge	167:e84263d55307	4145
<>	144:ef7eb2e8f9f7	4146	if(hi2c->State == HAL_I2C_STATE_BUSY_RX)
<>	144:ef7eb2e8f9f7	4147	{
<>	144:ef7eb2e8f9f7	4148	if((hi2c->EventCount == 0U) && (CurrentMode == HAL_I2C_MODE_MEM))
<>	144:ef7eb2e8f9f7	4149	{
<>	144:ef7eb2e8f9f7	4150	/* Clear ADDR flag */
<>	144:ef7eb2e8f9f7	4151	__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
<>	144:ef7eb2e8f9f7	4152	}
<>	144:ef7eb2e8f9f7	4153	else if((hi2c->EventCount == 0U) && (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT))
<>	144:ef7eb2e8f9f7	4154	{
<>	144:ef7eb2e8f9f7	4155	/* Clear ADDR flag */
<>	144:ef7eb2e8f9f7	4156	__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
<>	144:ef7eb2e8f9f7	4157
<>	144:ef7eb2e8f9f7	4158	/* Generate Restart */
<>	144:ef7eb2e8f9f7	4159	hi2c->Instance->CR1 \|= I2C_CR1_START;
<>	144:ef7eb2e8f9f7	4160
<>	144:ef7eb2e8f9f7	4161	hi2c->EventCount++;
<>	144:ef7eb2e8f9f7	4162	}
<>	144:ef7eb2e8f9f7	4163	else
<>	144:ef7eb2e8f9f7	4164	{
<>	144:ef7eb2e8f9f7	4165	if(hi2c->XferCount == 0U)
<>	144:ef7eb2e8f9f7	4166	{
<>	144:ef7eb2e8f9f7	4167	/* Clear ADDR flag */
<>	144:ef7eb2e8f9f7	4168	__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
<>	144:ef7eb2e8f9f7	4169
<>	144:ef7eb2e8f9f7	4170	/* Generate Stop */
<>	144:ef7eb2e8f9f7	4171	hi2c->Instance->CR1 \|= I2C_CR1_STOP;
<>	144:ef7eb2e8f9f7	4172	}
<>	144:ef7eb2e8f9f7	4173	else if(hi2c->XferCount == 1U)
<>	144:ef7eb2e8f9f7	4174	{
AnnaBridge	167:e84263d55307	4175	if(CurrentXferOptions == I2C_NO_OPTION_FRAME)
AnnaBridge	167:e84263d55307	4176	{
AnnaBridge	167:e84263d55307	4177	/* Disable Acknowledge */
AnnaBridge	167:e84263d55307	4178	hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
AnnaBridge	167:e84263d55307	4179
AnnaBridge	167:e84263d55307	4180	if((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN)
AnnaBridge	167:e84263d55307	4181	{
AnnaBridge	167:e84263d55307	4182	/* Disable Acknowledge */
AnnaBridge	167:e84263d55307	4183	hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
AnnaBridge	167:e84263d55307	4184
AnnaBridge	167:e84263d55307	4185	/* Clear ADDR flag */
AnnaBridge	167:e84263d55307	4186	__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
AnnaBridge	167:e84263d55307	4187	}
AnnaBridge	167:e84263d55307	4188	else
AnnaBridge	167:e84263d55307	4189	{
AnnaBridge	167:e84263d55307	4190	/* Clear ADDR flag */
AnnaBridge	167:e84263d55307	4191	__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
AnnaBridge	167:e84263d55307	4192
AnnaBridge	167:e84263d55307	4193	/* Generate Stop */
AnnaBridge	167:e84263d55307	4194	hi2c->Instance->CR1 \|= I2C_CR1_STOP;
AnnaBridge	167:e84263d55307	4195	}
AnnaBridge	167:e84263d55307	4196	}
<>	144:ef7eb2e8f9f7	4197	/* Prepare next transfer or stop current transfer */
AnnaBridge	167:e84263d55307	4198	else if((CurrentXferOptions != I2C_FIRST_AND_LAST_FRAME) && (CurrentXferOptions != I2C_LAST_FRAME) \
<>	144:ef7eb2e8f9f7	4199	&& (Prev_State != I2C_STATE_MASTER_BUSY_RX))
<>	144:ef7eb2e8f9f7	4200	{
<>	144:ef7eb2e8f9f7	4201	if(hi2c->XferOptions != I2C_NEXT_FRAME)
<>	144:ef7eb2e8f9f7	4202	{
<>	144:ef7eb2e8f9f7	4203	/* Disable Acknowledge */
<>	144:ef7eb2e8f9f7	4204	hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
<>	144:ef7eb2e8f9f7	4205	}
<>	144:ef7eb2e8f9f7	4206	else
<>	144:ef7eb2e8f9f7	4207	{
<>	144:ef7eb2e8f9f7	4208	/* Enable Acknowledge */
<>	144:ef7eb2e8f9f7	4209	hi2c->Instance->CR1 \|= I2C_CR1_ACK;
<>	144:ef7eb2e8f9f7	4210	}
<>	144:ef7eb2e8f9f7	4211
<>	144:ef7eb2e8f9f7	4212	/* Clear ADDR flag */
<>	144:ef7eb2e8f9f7	4213	__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
<>	144:ef7eb2e8f9f7	4214	}
<>	144:ef7eb2e8f9f7	4215	else
<>	144:ef7eb2e8f9f7	4216	{
<>	144:ef7eb2e8f9f7	4217	/* Disable Acknowledge */
<>	144:ef7eb2e8f9f7	4218	hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
<>	144:ef7eb2e8f9f7	4219
<>	144:ef7eb2e8f9f7	4220	/* Clear ADDR flag */
<>	144:ef7eb2e8f9f7	4221	__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
<>	144:ef7eb2e8f9f7	4222
<>	144:ef7eb2e8f9f7	4223	/* Generate Stop */
<>	144:ef7eb2e8f9f7	4224	hi2c->Instance->CR1 \|= I2C_CR1_STOP;
<>	144:ef7eb2e8f9f7	4225	}
<>	144:ef7eb2e8f9f7	4226	}
<>	144:ef7eb2e8f9f7	4227	else if(hi2c->XferCount == 2U)
<>	144:ef7eb2e8f9f7	4228	{
<>	144:ef7eb2e8f9f7	4229	if(hi2c->XferOptions != I2C_NEXT_FRAME)
<>	144:ef7eb2e8f9f7	4230	{
<>	144:ef7eb2e8f9f7	4231	/* Disable Acknowledge */
<>	144:ef7eb2e8f9f7	4232	hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
<>	144:ef7eb2e8f9f7	4233
<>	144:ef7eb2e8f9f7	4234	/* Enable Pos */
<>	144:ef7eb2e8f9f7	4235	hi2c->Instance->CR1 \|= I2C_CR1_POS;
<>	144:ef7eb2e8f9f7	4236	}
<>	144:ef7eb2e8f9f7	4237	else
<>	144:ef7eb2e8f9f7	4238	{
<>	144:ef7eb2e8f9f7	4239	/* Enable Acknowledge */
<>	144:ef7eb2e8f9f7	4240	hi2c->Instance->CR1 \|= I2C_CR1_ACK;
<>	144:ef7eb2e8f9f7	4241	}
AnnaBridge	167:e84263d55307	4242
AnnaBridge	167:e84263d55307	4243	if((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN)
AnnaBridge	167:e84263d55307	4244	{
AnnaBridge	167:e84263d55307	4245	/* Enable Last DMA bit */
AnnaBridge	167:e84263d55307	4246	hi2c->Instance->CR2 \|= I2C_CR2_LAST;
AnnaBridge	167:e84263d55307	4247	}
AnnaBridge	167:e84263d55307	4248
<>	144:ef7eb2e8f9f7	4249	/* Clear ADDR flag */
<>	144:ef7eb2e8f9f7	4250	__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
<>	144:ef7eb2e8f9f7	4251	}
<>	144:ef7eb2e8f9f7	4252	else
<>	144:ef7eb2e8f9f7	4253	{
<>	144:ef7eb2e8f9f7	4254	/* Enable Acknowledge */
<>	144:ef7eb2e8f9f7	4255	hi2c->Instance->CR1 \|= I2C_CR1_ACK;
AnnaBridge	167:e84263d55307	4256
AnnaBridge	167:e84263d55307	4257	if((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN)
AnnaBridge	167:e84263d55307	4258	{
AnnaBridge	167:e84263d55307	4259	/* Enable Last DMA bit */
AnnaBridge	167:e84263d55307	4260	hi2c->Instance->CR2 \|= I2C_CR2_LAST;
AnnaBridge	167:e84263d55307	4261	}
AnnaBridge	167:e84263d55307	4262
<>	144:ef7eb2e8f9f7	4263	/* Clear ADDR flag */
<>	144:ef7eb2e8f9f7	4264	__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
<>	144:ef7eb2e8f9f7	4265	}
<>	144:ef7eb2e8f9f7	4266
<>	144:ef7eb2e8f9f7	4267	/* Reset Event counter */
AnnaBridge	167:e84263d55307	4268	hi2c->EventCount = 0U;
<>	144:ef7eb2e8f9f7	4269	}
<>	144:ef7eb2e8f9f7	4270	}
<>	144:ef7eb2e8f9f7	4271	else
<>	144:ef7eb2e8f9f7	4272	{
<>	144:ef7eb2e8f9f7	4273	/* Clear ADDR flag */
<>	144:ef7eb2e8f9f7	4274	__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
<>	144:ef7eb2e8f9f7	4275	}
<>	144:ef7eb2e8f9f7	4276
<>	144:ef7eb2e8f9f7	4277	return HAL_OK;
<>	144:ef7eb2e8f9f7	4278	}
<>	144:ef7eb2e8f9f7	4279
<>	144:ef7eb2e8f9f7	4280	/**
<>	144:ef7eb2e8f9f7	4281	* @brief Handle TXE flag for Slave
<>	144:ef7eb2e8f9f7	4282	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	4283	* the configuration information for I2C module
<>	144:ef7eb2e8f9f7	4284	* @retval HAL status
<>	144:ef7eb2e8f9f7	4285	*/
<>	144:ef7eb2e8f9f7	4286	static HAL_StatusTypeDef I2C_SlaveTransmit_TXE(I2C_HandleTypeDef *hi2c)
<>	144:ef7eb2e8f9f7	4287	{
<>	144:ef7eb2e8f9f7	4288	/* Declaration of temporary variables to prevent undefined behavior of volatile usage */
<>	144:ef7eb2e8f9f7	4289	uint32_t CurrentState = hi2c->State;
<>	144:ef7eb2e8f9f7	4290
<>	144:ef7eb2e8f9f7	4291	if(hi2c->XferCount != 0U)
<>	144:ef7eb2e8f9f7	4292	{
<>	144:ef7eb2e8f9f7	4293	/* Write data to DR */
<>	144:ef7eb2e8f9f7	4294	hi2c->Instance->DR = (*hi2c->pBuffPtr++);
<>	144:ef7eb2e8f9f7	4295	hi2c->XferCount--;
<>	144:ef7eb2e8f9f7	4296
<>	144:ef7eb2e8f9f7	4297	if((hi2c->XferCount == 0U) && (CurrentState == HAL_I2C_STATE_BUSY_TX_LISTEN))
<>	144:ef7eb2e8f9f7	4298	{
<>	144:ef7eb2e8f9f7	4299	/* Last Byte is received, disable Interrupt */
<>	144:ef7eb2e8f9f7	4300	__HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF);
<>	144:ef7eb2e8f9f7	4301
<>	144:ef7eb2e8f9f7	4302	/* Set state at HAL_I2C_STATE_LISTEN */
AnnaBridge	167:e84263d55307	4303	hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
<>	144:ef7eb2e8f9f7	4304	hi2c->State = HAL_I2C_STATE_LISTEN;
<>	144:ef7eb2e8f9f7	4305
<>	144:ef7eb2e8f9f7	4306	/* Call the Tx complete callback to inform upper layer of the end of receive process */
<>	144:ef7eb2e8f9f7	4307	HAL_I2C_SlaveTxCpltCallback(hi2c);
<>	144:ef7eb2e8f9f7	4308	}
<>	144:ef7eb2e8f9f7	4309	}
<>	144:ef7eb2e8f9f7	4310	return HAL_OK;
<>	144:ef7eb2e8f9f7	4311	}
<>	144:ef7eb2e8f9f7	4312
<>	144:ef7eb2e8f9f7	4313	/**
<>	144:ef7eb2e8f9f7	4314	* @brief Handle BTF flag for Slave transmitter
<>	144:ef7eb2e8f9f7	4315	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	4316	* the configuration information for I2C module
<>	144:ef7eb2e8f9f7	4317	* @retval HAL status
<>	144:ef7eb2e8f9f7	4318	*/
<>	144:ef7eb2e8f9f7	4319	static HAL_StatusTypeDef I2C_SlaveTransmit_BTF(I2C_HandleTypeDef *hi2c)
<>	144:ef7eb2e8f9f7	4320	{
<>	144:ef7eb2e8f9f7	4321	if(hi2c->XferCount != 0U)
<>	144:ef7eb2e8f9f7	4322	{
<>	144:ef7eb2e8f9f7	4323	/* Write data to DR */
<>	144:ef7eb2e8f9f7	4324	hi2c->Instance->DR = (*hi2c->pBuffPtr++);
<>	144:ef7eb2e8f9f7	4325	hi2c->XferCount--;
<>	144:ef7eb2e8f9f7	4326	}
<>	144:ef7eb2e8f9f7	4327	return HAL_OK;
<>	144:ef7eb2e8f9f7	4328	}
<>	144:ef7eb2e8f9f7	4329
<>	144:ef7eb2e8f9f7	4330	/**
<>	144:ef7eb2e8f9f7	4331	* @brief Handle RXNE flag for Slave
<>	144:ef7eb2e8f9f7	4332	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	4333	* the configuration information for I2C module
<>	144:ef7eb2e8f9f7	4334	* @retval HAL status
<>	144:ef7eb2e8f9f7	4335	*/
<>	144:ef7eb2e8f9f7	4336	static HAL_StatusTypeDef I2C_SlaveReceive_RXNE(I2C_HandleTypeDef *hi2c)
<>	144:ef7eb2e8f9f7	4337	{
<>	144:ef7eb2e8f9f7	4338	/* Declaration of temporary variables to prevent undefined behavior of volatile usage */
<>	144:ef7eb2e8f9f7	4339	uint32_t CurrentState = hi2c->State;
<>	144:ef7eb2e8f9f7	4340
<>	144:ef7eb2e8f9f7	4341	if(hi2c->XferCount != 0U)
<>	144:ef7eb2e8f9f7	4342	{
<>	144:ef7eb2e8f9f7	4343	/* Read data from DR */
<>	144:ef7eb2e8f9f7	4344	(*hi2c->pBuffPtr++) = hi2c->Instance->DR;
<>	144:ef7eb2e8f9f7	4345	hi2c->XferCount--;
<>	144:ef7eb2e8f9f7	4346
<>	144:ef7eb2e8f9f7	4347	if((hi2c->XferCount == 0U) && (CurrentState == HAL_I2C_STATE_BUSY_RX_LISTEN))
<>	144:ef7eb2e8f9f7	4348	{
<>	144:ef7eb2e8f9f7	4349	/* Last Byte is received, disable Interrupt */
<>	144:ef7eb2e8f9f7	4350	__HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF);
AnnaBridge	167:e84263d55307	4351
<>	144:ef7eb2e8f9f7	4352	/* Set state at HAL_I2C_STATE_LISTEN */
AnnaBridge	167:e84263d55307	4353	hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX;
<>	144:ef7eb2e8f9f7	4354	hi2c->State = HAL_I2C_STATE_LISTEN;
AnnaBridge	167:e84263d55307	4355
<>	144:ef7eb2e8f9f7	4356	/* Call the Rx complete callback to inform upper layer of the end of receive process */
<>	144:ef7eb2e8f9f7	4357	HAL_I2C_SlaveRxCpltCallback(hi2c);
<>	144:ef7eb2e8f9f7	4358	}
<>	144:ef7eb2e8f9f7	4359	}
<>	144:ef7eb2e8f9f7	4360	return HAL_OK;
<>	144:ef7eb2e8f9f7	4361	}
<>	144:ef7eb2e8f9f7	4362
<>	144:ef7eb2e8f9f7	4363	/**
<>	144:ef7eb2e8f9f7	4364	* @brief Handle BTF flag for Slave receiver
<>	144:ef7eb2e8f9f7	4365	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	4366	* the configuration information for I2C module
<>	144:ef7eb2e8f9f7	4367	* @retval HAL status
<>	144:ef7eb2e8f9f7	4368	*/
<>	144:ef7eb2e8f9f7	4369	static HAL_StatusTypeDef I2C_SlaveReceive_BTF(I2C_HandleTypeDef *hi2c)
<>	144:ef7eb2e8f9f7	4370	{
<>	144:ef7eb2e8f9f7	4371	if(hi2c->XferCount != 0U)
<>	144:ef7eb2e8f9f7	4372	{
<>	144:ef7eb2e8f9f7	4373	/* Read data from DR */
<>	144:ef7eb2e8f9f7	4374	(*hi2c->pBuffPtr++) = hi2c->Instance->DR;
<>	144:ef7eb2e8f9f7	4375	hi2c->XferCount--;
<>	144:ef7eb2e8f9f7	4376	}
<>	144:ef7eb2e8f9f7	4377	return HAL_OK;
<>	144:ef7eb2e8f9f7	4378	}
<>	144:ef7eb2e8f9f7	4379
<>	144:ef7eb2e8f9f7	4380	/**
<>	144:ef7eb2e8f9f7	4381	* @brief Handle ADD flag for Slave
<>	144:ef7eb2e8f9f7	4382	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	4383	* the configuration information for I2C module
<>	144:ef7eb2e8f9f7	4384	* @retval HAL status
<>	144:ef7eb2e8f9f7	4385	*/
<>	144:ef7eb2e8f9f7	4386	static HAL_StatusTypeDef I2C_Slave_ADDR(I2C_HandleTypeDef *hi2c)
<>	144:ef7eb2e8f9f7	4387	{
<>	144:ef7eb2e8f9f7	4388	uint8_t TransferDirection = I2C_DIRECTION_RECEIVE;
<>	144:ef7eb2e8f9f7	4389	uint16_t SlaveAddrCode = 0U;
<>	144:ef7eb2e8f9f7	4390
<>	144:ef7eb2e8f9f7	4391	/* Transfer Direction requested by Master */
<>	144:ef7eb2e8f9f7	4392	if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TRA) == RESET)
<>	144:ef7eb2e8f9f7	4393	{
<>	144:ef7eb2e8f9f7	4394	TransferDirection = I2C_DIRECTION_TRANSMIT;
<>	144:ef7eb2e8f9f7	4395	}
<>	144:ef7eb2e8f9f7	4396
<>	144:ef7eb2e8f9f7	4397	if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_DUALF) == RESET)
<>	144:ef7eb2e8f9f7	4398	{
<>	144:ef7eb2e8f9f7	4399	SlaveAddrCode = hi2c->Init.OwnAddress1;
<>	144:ef7eb2e8f9f7	4400	}
<>	144:ef7eb2e8f9f7	4401	else
<>	144:ef7eb2e8f9f7	4402	{
<>	144:ef7eb2e8f9f7	4403	SlaveAddrCode = hi2c->Init.OwnAddress2;
<>	144:ef7eb2e8f9f7	4404	}
<>	144:ef7eb2e8f9f7	4405
<>	144:ef7eb2e8f9f7	4406	/* Call Slave Addr callback */
<>	144:ef7eb2e8f9f7	4407	HAL_I2C_AddrCallback(hi2c, TransferDirection, SlaveAddrCode);
<>	144:ef7eb2e8f9f7	4408
<>	144:ef7eb2e8f9f7	4409	return HAL_OK;
<>	144:ef7eb2e8f9f7	4410	}
<>	144:ef7eb2e8f9f7	4411
<>	144:ef7eb2e8f9f7	4412	/**
<>	144:ef7eb2e8f9f7	4413	* @brief Handle STOPF flag for Slave
<>	144:ef7eb2e8f9f7	4414	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	4415	* the configuration information for I2C module
<>	144:ef7eb2e8f9f7	4416	* @retval HAL status
<>	144:ef7eb2e8f9f7	4417	*/
<>	144:ef7eb2e8f9f7	4418	static HAL_StatusTypeDef I2C_Slave_STOPF(I2C_HandleTypeDef *hi2c)
<>	144:ef7eb2e8f9f7	4419	{
<>	144:ef7eb2e8f9f7	4420	/* Declaration of temporary variable to prevent undefined behavior of volatile usage */
<>	144:ef7eb2e8f9f7	4421	uint32_t CurrentState = hi2c->State;
<>	144:ef7eb2e8f9f7	4422
<>	144:ef7eb2e8f9f7	4423	/* Disable EVT, BUF and ERR interrupt */
<>	144:ef7eb2e8f9f7	4424	__HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT \| I2C_IT_BUF \| I2C_IT_ERR);
<>	144:ef7eb2e8f9f7	4425
<>	144:ef7eb2e8f9f7	4426	/* Clear STOPF flag */
<>	144:ef7eb2e8f9f7	4427	__HAL_I2C_CLEAR_STOPFLAG(hi2c);
<>	144:ef7eb2e8f9f7	4428
<>	144:ef7eb2e8f9f7	4429	/* Disable Acknowledge */
<>	144:ef7eb2e8f9f7	4430	hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
<>	144:ef7eb2e8f9f7	4431
AnnaBridge	167:e84263d55307	4432	/* If a DMA is ongoing, Update handle size context */
AnnaBridge	167:e84263d55307	4433	if((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN)
AnnaBridge	167:e84263d55307	4434	{
AnnaBridge	167:e84263d55307	4435	if((hi2c->State == HAL_I2C_STATE_BUSY_RX) \|\| (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN))
AnnaBridge	167:e84263d55307	4436	{
AnnaBridge	167:e84263d55307	4437	hi2c->XferCount = __HAL_DMA_GET_COUNTER(hi2c->hdmarx);
AnnaBridge	167:e84263d55307	4438	}
AnnaBridge	167:e84263d55307	4439	else
AnnaBridge	167:e84263d55307	4440	{
AnnaBridge	167:e84263d55307	4441	hi2c->XferCount = __HAL_DMA_GET_COUNTER(hi2c->hdmatx);
AnnaBridge	167:e84263d55307	4442	}
AnnaBridge	167:e84263d55307	4443	}
AnnaBridge	167:e84263d55307	4444
AnnaBridge	167:e84263d55307	4445	/* All data are not transferred, so set error code accordingly */
AnnaBridge	167:e84263d55307	4446	if(hi2c->XferCount != 0U)
<>	144:ef7eb2e8f9f7	4447	{
AnnaBridge	167:e84263d55307	4448	/* Store Last receive data if any */
AnnaBridge	167:e84263d55307	4449	if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET)
AnnaBridge	167:e84263d55307	4450	{
AnnaBridge	167:e84263d55307	4451	/* Read data from DR */
AnnaBridge	167:e84263d55307	4452	(*hi2c->pBuffPtr++) = hi2c->Instance->DR;
AnnaBridge	167:e84263d55307	4453	hi2c->XferCount--;
AnnaBridge	167:e84263d55307	4454	}
AnnaBridge	167:e84263d55307	4455
AnnaBridge	167:e84263d55307	4456	/* Store Last receive data if any */
AnnaBridge	167:e84263d55307	4457	if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET)
AnnaBridge	167:e84263d55307	4458	{
AnnaBridge	167:e84263d55307	4459	/* Read data from DR */
AnnaBridge	167:e84263d55307	4460	(*hi2c->pBuffPtr++) = hi2c->Instance->DR;
AnnaBridge	167:e84263d55307	4461	hi2c->XferCount--;
AnnaBridge	167:e84263d55307	4462	}
AnnaBridge	167:e84263d55307	4463
AnnaBridge	167:e84263d55307	4464	/* Set ErrorCode corresponding to a Non-Acknowledge */
AnnaBridge	167:e84263d55307	4465	hi2c->ErrorCode \|= HAL_I2C_ERROR_AF;
AnnaBridge	167:e84263d55307	4466	}
AnnaBridge	167:e84263d55307	4467
AnnaBridge	167:e84263d55307	4468	if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
AnnaBridge	167:e84263d55307	4469	{
AnnaBridge	167:e84263d55307	4470	/* Call the corresponding callback to inform upper layer of End of Transfer */
AnnaBridge	167:e84263d55307	4471	I2C_ITError(hi2c);
<>	144:ef7eb2e8f9f7	4472	}
<>	144:ef7eb2e8f9f7	4473	else
<>	144:ef7eb2e8f9f7	4474	{
AnnaBridge	167:e84263d55307	4475	if((CurrentState == HAL_I2C_STATE_LISTEN ) \|\| (CurrentState == HAL_I2C_STATE_BUSY_RX_LISTEN) \|\| \
AnnaBridge	167:e84263d55307	4476	(CurrentState == HAL_I2C_STATE_BUSY_TX_LISTEN))
<>	144:ef7eb2e8f9f7	4477	{
AnnaBridge	167:e84263d55307	4478	hi2c->XferOptions = I2C_NO_OPTION_FRAME;
<>	144:ef7eb2e8f9f7	4479	hi2c->PreviousState = I2C_STATE_NONE;
<>	144:ef7eb2e8f9f7	4480	hi2c->State = HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	4481	hi2c->Mode = HAL_I2C_MODE_NONE;
AnnaBridge	167:e84263d55307	4482
AnnaBridge	167:e84263d55307	4483	/* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
AnnaBridge	167:e84263d55307	4484	HAL_I2C_ListenCpltCallback(hi2c);
AnnaBridge	167:e84263d55307	4485	}
AnnaBridge	167:e84263d55307	4486	else
AnnaBridge	167:e84263d55307	4487	{
AnnaBridge	167:e84263d55307	4488	if((hi2c->PreviousState == I2C_STATE_SLAVE_BUSY_RX) \|\| (CurrentState == HAL_I2C_STATE_BUSY_RX))
AnnaBridge	167:e84263d55307	4489	{
AnnaBridge	167:e84263d55307	4490	hi2c->PreviousState = I2C_STATE_NONE;
AnnaBridge	167:e84263d55307	4491	hi2c->State = HAL_I2C_STATE_READY;
AnnaBridge	167:e84263d55307	4492	hi2c->Mode = HAL_I2C_MODE_NONE;
AnnaBridge	167:e84263d55307	4493
AnnaBridge	167:e84263d55307	4494	HAL_I2C_SlaveRxCpltCallback(hi2c);
AnnaBridge	167:e84263d55307	4495	}
<>	144:ef7eb2e8f9f7	4496	}
<>	144:ef7eb2e8f9f7	4497	}
<>	144:ef7eb2e8f9f7	4498	return HAL_OK;
<>	144:ef7eb2e8f9f7	4499	}
<>	144:ef7eb2e8f9f7	4500
<>	144:ef7eb2e8f9f7	4501	/**
<>	144:ef7eb2e8f9f7	4502	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	4503	* the configuration information for I2C module
<>	144:ef7eb2e8f9f7	4504	* @retval HAL status
<>	144:ef7eb2e8f9f7	4505	*/
<>	144:ef7eb2e8f9f7	4506	static HAL_StatusTypeDef I2C_Slave_AF(I2C_HandleTypeDef *hi2c)
<>	144:ef7eb2e8f9f7	4507	{
<>	144:ef7eb2e8f9f7	4508	/* Declaration of temporary variables to prevent undefined behavior of volatile usage */
<>	144:ef7eb2e8f9f7	4509	uint32_t CurrentState = hi2c->State;
<>	144:ef7eb2e8f9f7	4510	uint32_t CurrentXferOptions = hi2c->XferOptions;
<>	144:ef7eb2e8f9f7	4511
<>	144:ef7eb2e8f9f7	4512	if(((CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) \|\| (CurrentXferOptions == I2C_LAST_FRAME)) && \
<>	144:ef7eb2e8f9f7	4513	(CurrentState == HAL_I2C_STATE_LISTEN))
<>	144:ef7eb2e8f9f7	4514	{
<>	144:ef7eb2e8f9f7	4515	hi2c->XferOptions = I2C_NO_OPTION_FRAME;
<>	144:ef7eb2e8f9f7	4516
<>	144:ef7eb2e8f9f7	4517	/* Disable EVT, BUF and ERR interrupt */
<>	144:ef7eb2e8f9f7	4518	__HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT \| I2C_IT_BUF \| I2C_IT_ERR);
<>	144:ef7eb2e8f9f7	4519
<>	144:ef7eb2e8f9f7	4520	/* Clear AF flag */
<>	144:ef7eb2e8f9f7	4521	__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
<>	144:ef7eb2e8f9f7	4522
<>	144:ef7eb2e8f9f7	4523	/* Disable Acknowledge */
<>	144:ef7eb2e8f9f7	4524	hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
<>	144:ef7eb2e8f9f7	4525
<>	144:ef7eb2e8f9f7	4526	hi2c->PreviousState = I2C_STATE_NONE;
<>	144:ef7eb2e8f9f7	4527	hi2c->State = HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	4528	hi2c->Mode = HAL_I2C_MODE_NONE;
<>	144:ef7eb2e8f9f7	4529
<>	144:ef7eb2e8f9f7	4530	/* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
<>	144:ef7eb2e8f9f7	4531	HAL_I2C_ListenCpltCallback(hi2c);
<>	144:ef7eb2e8f9f7	4532	}
<>	144:ef7eb2e8f9f7	4533	else if(CurrentState == HAL_I2C_STATE_BUSY_TX)
<>	144:ef7eb2e8f9f7	4534	{
<>	144:ef7eb2e8f9f7	4535	hi2c->XferOptions = I2C_NO_OPTION_FRAME;
AnnaBridge	167:e84263d55307	4536	hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
<>	144:ef7eb2e8f9f7	4537	hi2c->State = HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	4538	hi2c->Mode = HAL_I2C_MODE_NONE;
<>	144:ef7eb2e8f9f7	4539
<>	144:ef7eb2e8f9f7	4540	/* Disable EVT, BUF and ERR interrupt */
<>	144:ef7eb2e8f9f7	4541	__HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT \| I2C_IT_BUF \| I2C_IT_ERR);
<>	144:ef7eb2e8f9f7	4542
<>	144:ef7eb2e8f9f7	4543	/* Clear AF flag */
<>	144:ef7eb2e8f9f7	4544	__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
<>	144:ef7eb2e8f9f7	4545
<>	144:ef7eb2e8f9f7	4546	/* Disable Acknowledge */
<>	144:ef7eb2e8f9f7	4547	hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
<>	144:ef7eb2e8f9f7	4548
<>	144:ef7eb2e8f9f7	4549	HAL_I2C_SlaveTxCpltCallback(hi2c);
<>	144:ef7eb2e8f9f7	4550	}
<>	144:ef7eb2e8f9f7	4551	else
<>	144:ef7eb2e8f9f7	4552	{
<>	144:ef7eb2e8f9f7	4553	/* Clear AF flag only */
<>	144:ef7eb2e8f9f7	4554	/* State Listen, but XferOptions == FIRST or NEXT */
<>	144:ef7eb2e8f9f7	4555	__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
<>	144:ef7eb2e8f9f7	4556	}
<>	144:ef7eb2e8f9f7	4557
<>	144:ef7eb2e8f9f7	4558	return HAL_OK;
<>	144:ef7eb2e8f9f7	4559	}
<>	144:ef7eb2e8f9f7	4560
<>	144:ef7eb2e8f9f7	4561	/**
<>	144:ef7eb2e8f9f7	4562	* @brief I2C interrupts error process
<>	144:ef7eb2e8f9f7	4563	* @param hi2c I2C handle.
<>	144:ef7eb2e8f9f7	4564	* @retval None
<>	144:ef7eb2e8f9f7	4565	*/
<>	144:ef7eb2e8f9f7	4566	static void I2C_ITError(I2C_HandleTypeDef *hi2c)
<>	144:ef7eb2e8f9f7	4567	{
<>	144:ef7eb2e8f9f7	4568	/* Declaration of temporary variable to prevent undefined behavior of volatile usage */
<>	144:ef7eb2e8f9f7	4569	uint32_t CurrentState = hi2c->State;
<>	144:ef7eb2e8f9f7	4570
<>	144:ef7eb2e8f9f7	4571	if((CurrentState == HAL_I2C_STATE_BUSY_TX_LISTEN) \|\| (CurrentState == HAL_I2C_STATE_BUSY_RX_LISTEN))
<>	144:ef7eb2e8f9f7	4572	{
<>	144:ef7eb2e8f9f7	4573	/* keep HAL_I2C_STATE_LISTEN */
<>	144:ef7eb2e8f9f7	4574	hi2c->PreviousState = I2C_STATE_NONE;
<>	144:ef7eb2e8f9f7	4575	hi2c->State = HAL_I2C_STATE_LISTEN;
<>	144:ef7eb2e8f9f7	4576	}
<>	144:ef7eb2e8f9f7	4577	else
<>	144:ef7eb2e8f9f7	4578	{
<>	144:ef7eb2e8f9f7	4579	/* If state is an abort treatment on going, don't change state */
<>	144:ef7eb2e8f9f7	4580	/* This change will be do later */
AnnaBridge	167:e84263d55307	4581	if((hi2c->State != HAL_I2C_STATE_ABORT) && ((hi2c->Instance->CR2 & I2C_CR2_DMAEN) != I2C_CR2_DMAEN))
<>	144:ef7eb2e8f9f7	4582	{
<>	144:ef7eb2e8f9f7	4583	hi2c->State = HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	4584	}
<>	144:ef7eb2e8f9f7	4585	hi2c->PreviousState = I2C_STATE_NONE;
<>	144:ef7eb2e8f9f7	4586	hi2c->Mode = HAL_I2C_MODE_NONE;
<>	144:ef7eb2e8f9f7	4587	}
<>	144:ef7eb2e8f9f7	4588
<>	144:ef7eb2e8f9f7	4589	/* Disable Pos bit in I2C CR1 when error occurred in Master/Mem Receive IT Process */
<>	144:ef7eb2e8f9f7	4590	hi2c->Instance->CR1 &= ~I2C_CR1_POS;
<>	144:ef7eb2e8f9f7	4591
<>	144:ef7eb2e8f9f7	4592	/* Abort DMA transfer */
AnnaBridge	167:e84263d55307	4593	if((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN)
<>	144:ef7eb2e8f9f7	4594	{
<>	144:ef7eb2e8f9f7	4595	hi2c->Instance->CR2 &= ~I2C_CR2_DMAEN;
<>	144:ef7eb2e8f9f7	4596
AnnaBridge	167:e84263d55307	4597	if(hi2c->hdmatx->State != HAL_DMA_STATE_READY)
<>	144:ef7eb2e8f9f7	4598	{
<>	144:ef7eb2e8f9f7	4599	/* Set the DMA Abort callback :
<>	144:ef7eb2e8f9f7	4600	will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
<>	144:ef7eb2e8f9f7	4601	hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
<>	144:ef7eb2e8f9f7	4602
<>	144:ef7eb2e8f9f7	4603	if(HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
<>	144:ef7eb2e8f9f7	4604	{
AnnaBridge	167:e84263d55307	4605	/* Disable I2C peripheral to prevent dummy data in buffer */
AnnaBridge	167:e84263d55307	4606	__HAL_I2C_DISABLE(hi2c);
AnnaBridge	167:e84263d55307	4607
AnnaBridge	167:e84263d55307	4608	hi2c->State = HAL_I2C_STATE_READY;
AnnaBridge	167:e84263d55307	4609
<>	144:ef7eb2e8f9f7	4610	/* Call Directly XferAbortCallback function in case of error */
<>	144:ef7eb2e8f9f7	4611	hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
<>	144:ef7eb2e8f9f7	4612	}
<>	144:ef7eb2e8f9f7	4613	}
AnnaBridge	167:e84263d55307	4614	else
<>	144:ef7eb2e8f9f7	4615	{
<>	144:ef7eb2e8f9f7	4616	/* Set the DMA Abort callback :
<>	144:ef7eb2e8f9f7	4617	will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
<>	144:ef7eb2e8f9f7	4618	hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
<>	144:ef7eb2e8f9f7	4619
<>	144:ef7eb2e8f9f7	4620	if(HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
<>	144:ef7eb2e8f9f7	4621	{
AnnaBridge	167:e84263d55307	4622	/* Store Last receive data if any */
AnnaBridge	167:e84263d55307	4623	if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET)
AnnaBridge	167:e84263d55307	4624	{
AnnaBridge	167:e84263d55307	4625	/* Read data from DR */
AnnaBridge	167:e84263d55307	4626	(*hi2c->pBuffPtr++) = hi2c->Instance->DR;
AnnaBridge	167:e84263d55307	4627	}
AnnaBridge	167:e84263d55307	4628
AnnaBridge	167:e84263d55307	4629	/* Disable I2C peripheral to prevent dummy data in buffer */
AnnaBridge	167:e84263d55307	4630	__HAL_I2C_DISABLE(hi2c);
AnnaBridge	167:e84263d55307	4631
AnnaBridge	167:e84263d55307	4632	hi2c->State = HAL_I2C_STATE_READY;
AnnaBridge	167:e84263d55307	4633
<>	144:ef7eb2e8f9f7	4634	/* Call Directly hi2c->hdmarx->XferAbortCallback function in case of error */
<>	144:ef7eb2e8f9f7	4635	hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
<>	144:ef7eb2e8f9f7	4636	}
<>	144:ef7eb2e8f9f7	4637	}
<>	144:ef7eb2e8f9f7	4638	}
<>	144:ef7eb2e8f9f7	4639	else if(hi2c->State == HAL_I2C_STATE_ABORT)
<>	144:ef7eb2e8f9f7	4640	{
<>	144:ef7eb2e8f9f7	4641	hi2c->State = HAL_I2C_STATE_READY;
AnnaBridge	167:e84263d55307	4642	hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
AnnaBridge	167:e84263d55307	4643
AnnaBridge	167:e84263d55307	4644	/* Store Last receive data if any */
AnnaBridge	167:e84263d55307	4645	if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET)
AnnaBridge	167:e84263d55307	4646	{
AnnaBridge	167:e84263d55307	4647	/* Read data from DR */
AnnaBridge	167:e84263d55307	4648	(*hi2c->pBuffPtr++) = hi2c->Instance->DR;
AnnaBridge	167:e84263d55307	4649	}
AnnaBridge	167:e84263d55307	4650
AnnaBridge	167:e84263d55307	4651	/* Disable I2C peripheral to prevent dummy data in buffer */
AnnaBridge	167:e84263d55307	4652	__HAL_I2C_DISABLE(hi2c);
<>	144:ef7eb2e8f9f7	4653
<>	144:ef7eb2e8f9f7	4654	/* Call the corresponding callback to inform upper layer of End of Transfer */
<>	144:ef7eb2e8f9f7	4655	HAL_I2C_AbortCpltCallback(hi2c);
<>	144:ef7eb2e8f9f7	4656	}
<>	144:ef7eb2e8f9f7	4657	else
<>	144:ef7eb2e8f9f7	4658	{
AnnaBridge	167:e84263d55307	4659	/* Store Last receive data if any */
AnnaBridge	167:e84263d55307	4660	if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET)
AnnaBridge	167:e84263d55307	4661	{
AnnaBridge	167:e84263d55307	4662	/* Read data from DR */
AnnaBridge	167:e84263d55307	4663	(*hi2c->pBuffPtr++) = hi2c->Instance->DR;
AnnaBridge	167:e84263d55307	4664	}
AnnaBridge	167:e84263d55307	4665
<>	144:ef7eb2e8f9f7	4666	/* Call user error callback */
<>	144:ef7eb2e8f9f7	4667	HAL_I2C_ErrorCallback(hi2c);
<>	144:ef7eb2e8f9f7	4668	}
<>	144:ef7eb2e8f9f7	4669	/* STOP Flag is not set after a NACK reception */
<>	144:ef7eb2e8f9f7	4670	/* So may inform upper layer that listen phase is stopped */
<>	144:ef7eb2e8f9f7	4671	/* during NACK error treatment */
<>	144:ef7eb2e8f9f7	4672	if((hi2c->State == HAL_I2C_STATE_LISTEN) && ((hi2c->ErrorCode & HAL_I2C_ERROR_AF) == HAL_I2C_ERROR_AF))
<>	144:ef7eb2e8f9f7	4673	{
<>	144:ef7eb2e8f9f7	4674	hi2c->XferOptions = I2C_NO_OPTION_FRAME;
<>	144:ef7eb2e8f9f7	4675	hi2c->PreviousState = I2C_STATE_NONE;
<>	144:ef7eb2e8f9f7	4676	hi2c->State = HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	4677	hi2c->Mode = HAL_I2C_MODE_NONE;
<>	144:ef7eb2e8f9f7	4678
<>	144:ef7eb2e8f9f7	4679	/* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
<>	144:ef7eb2e8f9f7	4680	HAL_I2C_ListenCpltCallback(hi2c);
<>	144:ef7eb2e8f9f7	4681	}
<>	144:ef7eb2e8f9f7	4682	}
<>	144:ef7eb2e8f9f7	4683
<>	144:ef7eb2e8f9f7	4684	/**
<>	144:ef7eb2e8f9f7	4685	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	4686	* the configuration information for I2C module
<>	144:ef7eb2e8f9f7	4687	* @param DevAddress Target device address: The device 7 bits address value
<>	144:ef7eb2e8f9f7	4688	* in datasheet must be shift at right before call interface
<>	144:ef7eb2e8f9f7	4689	* @param Timeout Timeout duration
<>	144:ef7eb2e8f9f7	4690	* @param Tickstart Tick start value
<>	144:ef7eb2e8f9f7	4691	* @retval HAL status
<>	144:ef7eb2e8f9f7	4692	*/
<>	144:ef7eb2e8f9f7	4693	static HAL_StatusTypeDef I2C_MasterRequestWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout, uint32_t Tickstart)
<>	144:ef7eb2e8f9f7	4694	{
<>	144:ef7eb2e8f9f7	4695	/* Declaration of temporary variable to prevent undefined behavior of volatile usage */
<>	144:ef7eb2e8f9f7	4696	uint32_t CurrentXferOptions = hi2c->XferOptions;
<>	144:ef7eb2e8f9f7	4697
<>	144:ef7eb2e8f9f7	4698	/* Generate Start condition if first transfer */
<>	144:ef7eb2e8f9f7	4699	if((CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) \|\| (CurrentXferOptions == I2C_FIRST_FRAME) \|\| (CurrentXferOptions == I2C_NO_OPTION_FRAME))
<>	144:ef7eb2e8f9f7	4700	{
<>	144:ef7eb2e8f9f7	4701	/* Generate Start */
<>	144:ef7eb2e8f9f7	4702	hi2c->Instance->CR1 \|= I2C_CR1_START;
<>	144:ef7eb2e8f9f7	4703	}
<>	144:ef7eb2e8f9f7	4704	else if(hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX)
<>	144:ef7eb2e8f9f7	4705	{
<>	144:ef7eb2e8f9f7	4706	/* Generate ReStart */
<>	144:ef7eb2e8f9f7	4707	hi2c->Instance->CR1 \|= I2C_CR1_START;
<>	144:ef7eb2e8f9f7	4708	}
<>	144:ef7eb2e8f9f7	4709
<>	144:ef7eb2e8f9f7	4710	/* Wait until SB flag is set */
<>	144:ef7eb2e8f9f7	4711	if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	4712	{
<>	144:ef7eb2e8f9f7	4713	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	4714	}
<>	144:ef7eb2e8f9f7	4715
<>	144:ef7eb2e8f9f7	4716	if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
<>	144:ef7eb2e8f9f7	4717	{
<>	144:ef7eb2e8f9f7	4718	/* Send slave address */
<>	144:ef7eb2e8f9f7	4719	hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress);
<>	144:ef7eb2e8f9f7	4720	}
<>	144:ef7eb2e8f9f7	4721	else
<>	144:ef7eb2e8f9f7	4722	{
<>	144:ef7eb2e8f9f7	4723	/* Send header of slave address */
<>	144:ef7eb2e8f9f7	4724	hi2c->Instance->DR = I2C_10BIT_HEADER_WRITE(DevAddress);
<>	144:ef7eb2e8f9f7	4725
<>	144:ef7eb2e8f9f7	4726	/* Wait until ADD10 flag is set */
<>	144:ef7eb2e8f9f7	4727	if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADD10, Timeout, Tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	4728	{
<>	144:ef7eb2e8f9f7	4729	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
<>	144:ef7eb2e8f9f7	4730	{
<>	144:ef7eb2e8f9f7	4731	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	4732	}
<>	144:ef7eb2e8f9f7	4733	else
<>	144:ef7eb2e8f9f7	4734	{
<>	144:ef7eb2e8f9f7	4735	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	4736	}
<>	144:ef7eb2e8f9f7	4737	}
<>	144:ef7eb2e8f9f7	4738
<>	144:ef7eb2e8f9f7	4739	/* Send slave address */
<>	144:ef7eb2e8f9f7	4740	hi2c->Instance->DR = I2C_10BIT_ADDRESS(DevAddress);
<>	144:ef7eb2e8f9f7	4741	}
<>	144:ef7eb2e8f9f7	4742
<>	144:ef7eb2e8f9f7	4743	/* Wait until ADDR flag is set */
<>	144:ef7eb2e8f9f7	4744	if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	4745	{
<>	144:ef7eb2e8f9f7	4746	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
<>	144:ef7eb2e8f9f7	4747	{
<>	144:ef7eb2e8f9f7	4748	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	4749	}
<>	144:ef7eb2e8f9f7	4750	else
<>	144:ef7eb2e8f9f7	4751	{
<>	144:ef7eb2e8f9f7	4752	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	4753	}
<>	144:ef7eb2e8f9f7	4754	}
<>	144:ef7eb2e8f9f7	4755
<>	144:ef7eb2e8f9f7	4756	return HAL_OK;
<>	144:ef7eb2e8f9f7	4757	}
<>	144:ef7eb2e8f9f7	4758
<>	144:ef7eb2e8f9f7	4759	/**
<>	144:ef7eb2e8f9f7	4760	* @brief Master sends target device address for read request.
<>	144:ef7eb2e8f9f7	4761	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	4762	* the configuration information for I2C module
<>	144:ef7eb2e8f9f7	4763	* @param DevAddress Target device address: The device 7 bits address value
<>	144:ef7eb2e8f9f7	4764	* in datasheet must be shift at right before call interface
<>	144:ef7eb2e8f9f7	4765	* @param Timeout Timeout duration
<>	144:ef7eb2e8f9f7	4766	* @param Tickstart Tick start value
<>	144:ef7eb2e8f9f7	4767	* @retval HAL status
<>	144:ef7eb2e8f9f7	4768	*/
<>	144:ef7eb2e8f9f7	4769	static HAL_StatusTypeDef I2C_MasterRequestRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout, uint32_t Tickstart)
<>	144:ef7eb2e8f9f7	4770	{
<>	144:ef7eb2e8f9f7	4771	/* Declaration of temporary variable to prevent undefined behavior of volatile usage */
<>	144:ef7eb2e8f9f7	4772	uint32_t CurrentXferOptions = hi2c->XferOptions;
<>	144:ef7eb2e8f9f7	4773
AnnaBridge	167:e84263d55307	4774	/* Enable Acknowledge */
AnnaBridge	167:e84263d55307	4775	hi2c->Instance->CR1 \|= I2C_CR1_ACK;
AnnaBridge	167:e84263d55307	4776
<>	144:ef7eb2e8f9f7	4777	/* Generate Start condition if first transfer */
<>	144:ef7eb2e8f9f7	4778	if((CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) \|\| (CurrentXferOptions == I2C_FIRST_FRAME) \|\| (CurrentXferOptions == I2C_NO_OPTION_FRAME))
<>	144:ef7eb2e8f9f7	4779	{
<>	144:ef7eb2e8f9f7	4780	/* Generate Start */
<>	144:ef7eb2e8f9f7	4781	hi2c->Instance->CR1 \|= I2C_CR1_START;
<>	144:ef7eb2e8f9f7	4782	}
<>	144:ef7eb2e8f9f7	4783	else if(hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX)
<>	144:ef7eb2e8f9f7	4784	{
<>	144:ef7eb2e8f9f7	4785	/* Generate ReStart */
<>	144:ef7eb2e8f9f7	4786	hi2c->Instance->CR1 \|= I2C_CR1_START;
<>	144:ef7eb2e8f9f7	4787	}
<>	144:ef7eb2e8f9f7	4788
<>	144:ef7eb2e8f9f7	4789	/* Wait until SB flag is set */
<>	144:ef7eb2e8f9f7	4790	if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	4791	{
<>	144:ef7eb2e8f9f7	4792	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	4793	}
<>	144:ef7eb2e8f9f7	4794
<>	144:ef7eb2e8f9f7	4795	if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
<>	144:ef7eb2e8f9f7	4796	{
<>	144:ef7eb2e8f9f7	4797	/* Send slave address */
<>	144:ef7eb2e8f9f7	4798	hi2c->Instance->DR = I2C_7BIT_ADD_READ(DevAddress);
<>	144:ef7eb2e8f9f7	4799	}
<>	144:ef7eb2e8f9f7	4800	else
<>	144:ef7eb2e8f9f7	4801	{
<>	144:ef7eb2e8f9f7	4802	/* Send header of slave address */
<>	144:ef7eb2e8f9f7	4803	hi2c->Instance->DR = I2C_10BIT_HEADER_WRITE(DevAddress);
<>	144:ef7eb2e8f9f7	4804
<>	144:ef7eb2e8f9f7	4805	/* Wait until ADD10 flag is set */
<>	144:ef7eb2e8f9f7	4806	if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADD10, Timeout, Tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	4807	{
<>	144:ef7eb2e8f9f7	4808	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
<>	144:ef7eb2e8f9f7	4809	{
<>	144:ef7eb2e8f9f7	4810	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	4811	}
<>	144:ef7eb2e8f9f7	4812	else
<>	144:ef7eb2e8f9f7	4813	{
<>	144:ef7eb2e8f9f7	4814	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	4815	}
<>	144:ef7eb2e8f9f7	4816	}
<>	144:ef7eb2e8f9f7	4817
<>	144:ef7eb2e8f9f7	4818	/* Send slave address */
<>	144:ef7eb2e8f9f7	4819	hi2c->Instance->DR = I2C_10BIT_ADDRESS(DevAddress);
<>	144:ef7eb2e8f9f7	4820
<>	144:ef7eb2e8f9f7	4821	/* Wait until ADDR flag is set */
<>	144:ef7eb2e8f9f7	4822	if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	4823	{
<>	144:ef7eb2e8f9f7	4824	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
<>	144:ef7eb2e8f9f7	4825	{
<>	144:ef7eb2e8f9f7	4826	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	4827	}
<>	144:ef7eb2e8f9f7	4828	else
<>	144:ef7eb2e8f9f7	4829	{
<>	144:ef7eb2e8f9f7	4830	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	4831	}
<>	144:ef7eb2e8f9f7	4832	}
<>	144:ef7eb2e8f9f7	4833
<>	144:ef7eb2e8f9f7	4834	/* Clear ADDR flag */
<>	144:ef7eb2e8f9f7	4835	__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
<>	144:ef7eb2e8f9f7	4836
<>	144:ef7eb2e8f9f7	4837	/* Generate Restart */
<>	144:ef7eb2e8f9f7	4838	hi2c->Instance->CR1 \|= I2C_CR1_START;
<>	144:ef7eb2e8f9f7	4839
<>	144:ef7eb2e8f9f7	4840	/* Wait until SB flag is set */
<>	144:ef7eb2e8f9f7	4841	if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	4842	{
<>	144:ef7eb2e8f9f7	4843	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	4844	}
<>	144:ef7eb2e8f9f7	4845
<>	144:ef7eb2e8f9f7	4846	/* Send header of slave address */
<>	144:ef7eb2e8f9f7	4847	hi2c->Instance->DR = I2C_10BIT_HEADER_READ(DevAddress);
<>	144:ef7eb2e8f9f7	4848	}
<>	144:ef7eb2e8f9f7	4849
<>	144:ef7eb2e8f9f7	4850	/* Wait until ADDR flag is set */
<>	144:ef7eb2e8f9f7	4851	if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	4852	{
<>	144:ef7eb2e8f9f7	4853	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
<>	144:ef7eb2e8f9f7	4854	{
<>	144:ef7eb2e8f9f7	4855	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	4856	}
<>	144:ef7eb2e8f9f7	4857	else
<>	144:ef7eb2e8f9f7	4858	{
<>	144:ef7eb2e8f9f7	4859	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	4860	}
<>	144:ef7eb2e8f9f7	4861	}
<>	144:ef7eb2e8f9f7	4862
<>	144:ef7eb2e8f9f7	4863	return HAL_OK;
<>	144:ef7eb2e8f9f7	4864	}
<>	144:ef7eb2e8f9f7	4865
<>	144:ef7eb2e8f9f7	4866	/**
<>	144:ef7eb2e8f9f7	4867	* @brief Master sends target device address followed by internal memory address for write request.
<>	144:ef7eb2e8f9f7	4868	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	4869	* the configuration information for I2C module
<>	144:ef7eb2e8f9f7	4870	* @param DevAddress Target device address
<>	144:ef7eb2e8f9f7	4871	* @param MemAddress Internal memory address
<>	144:ef7eb2e8f9f7	4872	* @param MemAddSize Size of internal memory address
<>	144:ef7eb2e8f9f7	4873	* @param Timeout Timeout duration
<>	144:ef7eb2e8f9f7	4874	* @param Tickstart Tick start value
<>	144:ef7eb2e8f9f7	4875	* @retval HAL status
<>	144:ef7eb2e8f9f7	4876	*/
<>	144:ef7eb2e8f9f7	4877	static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart)
<>	144:ef7eb2e8f9f7	4878	{
<>	144:ef7eb2e8f9f7	4879	/* Generate Start */
<>	144:ef7eb2e8f9f7	4880	hi2c->Instance->CR1 \|= I2C_CR1_START;
<>	144:ef7eb2e8f9f7	4881
<>	144:ef7eb2e8f9f7	4882	/* Wait until SB flag is set */
<>	144:ef7eb2e8f9f7	4883	if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	4884	{
<>	144:ef7eb2e8f9f7	4885	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	4886	}
<>	144:ef7eb2e8f9f7	4887
<>	144:ef7eb2e8f9f7	4888	/* Send slave address */
<>	144:ef7eb2e8f9f7	4889	hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress);
<>	144:ef7eb2e8f9f7	4890
<>	144:ef7eb2e8f9f7	4891	/* Wait until ADDR flag is set */
<>	144:ef7eb2e8f9f7	4892	if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	4893	{
<>	144:ef7eb2e8f9f7	4894	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
<>	144:ef7eb2e8f9f7	4895	{
<>	144:ef7eb2e8f9f7	4896	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	4897	}
<>	144:ef7eb2e8f9f7	4898	else
<>	144:ef7eb2e8f9f7	4899	{
<>	144:ef7eb2e8f9f7	4900	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	4901	}
<>	144:ef7eb2e8f9f7	4902	}
<>	144:ef7eb2e8f9f7	4903
<>	144:ef7eb2e8f9f7	4904	/* Clear ADDR flag */
<>	144:ef7eb2e8f9f7	4905	__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
<>	144:ef7eb2e8f9f7	4906
<>	144:ef7eb2e8f9f7	4907	/* Wait until TXE flag is set */
<>	144:ef7eb2e8f9f7	4908	if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	4909	{
<>	144:ef7eb2e8f9f7	4910	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
<>	144:ef7eb2e8f9f7	4911	{
<>	144:ef7eb2e8f9f7	4912	/* Generate Stop */
<>	144:ef7eb2e8f9f7	4913	hi2c->Instance->CR1 \|= I2C_CR1_STOP;
<>	144:ef7eb2e8f9f7	4914	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	4915	}
<>	144:ef7eb2e8f9f7	4916	else
<>	144:ef7eb2e8f9f7	4917	{
<>	144:ef7eb2e8f9f7	4918	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	4919	}
<>	144:ef7eb2e8f9f7	4920	}
<>	144:ef7eb2e8f9f7	4921
<>	144:ef7eb2e8f9f7	4922	/* If Memory address size is 8Bit */
<>	144:ef7eb2e8f9f7	4923	if(MemAddSize == I2C_MEMADD_SIZE_8BIT)
<>	144:ef7eb2e8f9f7	4924	{
<>	144:ef7eb2e8f9f7	4925	/* Send Memory Address */
<>	144:ef7eb2e8f9f7	4926	hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress);
<>	144:ef7eb2e8f9f7	4927	}
<>	144:ef7eb2e8f9f7	4928	/* If Memory address size is 16Bit */
<>	144:ef7eb2e8f9f7	4929	else
<>	144:ef7eb2e8f9f7	4930	{
<>	144:ef7eb2e8f9f7	4931	/* Send MSB of Memory Address */
<>	144:ef7eb2e8f9f7	4932	hi2c->Instance->DR = I2C_MEM_ADD_MSB(MemAddress);
<>	144:ef7eb2e8f9f7	4933
<>	144:ef7eb2e8f9f7	4934	/* Wait until TXE flag is set */
<>	144:ef7eb2e8f9f7	4935	if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	4936	{
<>	144:ef7eb2e8f9f7	4937	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
<>	144:ef7eb2e8f9f7	4938	{
<>	144:ef7eb2e8f9f7	4939	/* Generate Stop */
<>	144:ef7eb2e8f9f7	4940	hi2c->Instance->CR1 \|= I2C_CR1_STOP;
<>	144:ef7eb2e8f9f7	4941	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	4942	}
<>	144:ef7eb2e8f9f7	4943	else
<>	144:ef7eb2e8f9f7	4944	{
<>	144:ef7eb2e8f9f7	4945	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	4946	}
<>	144:ef7eb2e8f9f7	4947	}
<>	144:ef7eb2e8f9f7	4948
<>	144:ef7eb2e8f9f7	4949	/* Send LSB of Memory Address */
<>	144:ef7eb2e8f9f7	4950	hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress);
<>	144:ef7eb2e8f9f7	4951	}
<>	144:ef7eb2e8f9f7	4952
<>	144:ef7eb2e8f9f7	4953	return HAL_OK;
<>	144:ef7eb2e8f9f7	4954	}
<>	144:ef7eb2e8f9f7	4955
<>	144:ef7eb2e8f9f7	4956	/**
<>	144:ef7eb2e8f9f7	4957	* @brief Master sends target device address followed by internal memory address for read request.
<>	144:ef7eb2e8f9f7	4958	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	4959	* the configuration information for I2C module
<>	144:ef7eb2e8f9f7	4960	* @param DevAddress Target device address
<>	144:ef7eb2e8f9f7	4961	* @param MemAddress Internal memory address
<>	144:ef7eb2e8f9f7	4962	* @param MemAddSize Size of internal memory address
<>	144:ef7eb2e8f9f7	4963	* @param Timeout Timeout duration
<>	144:ef7eb2e8f9f7	4964	* @param Tickstart Tick start value
<>	144:ef7eb2e8f9f7	4965	* @retval HAL status
<>	144:ef7eb2e8f9f7	4966	*/
<>	144:ef7eb2e8f9f7	4967	static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart)
<>	144:ef7eb2e8f9f7	4968	{
<>	144:ef7eb2e8f9f7	4969	/* Enable Acknowledge */
<>	144:ef7eb2e8f9f7	4970	hi2c->Instance->CR1 \|= I2C_CR1_ACK;
<>	144:ef7eb2e8f9f7	4971
<>	144:ef7eb2e8f9f7	4972	/* Generate Start */
<>	144:ef7eb2e8f9f7	4973	hi2c->Instance->CR1 \|= I2C_CR1_START;
<>	144:ef7eb2e8f9f7	4974
<>	144:ef7eb2e8f9f7	4975	/* Wait until SB flag is set */
<>	144:ef7eb2e8f9f7	4976	if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	4977	{
<>	144:ef7eb2e8f9f7	4978	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	4979	}
<>	144:ef7eb2e8f9f7	4980
<>	144:ef7eb2e8f9f7	4981	/* Send slave address */
<>	144:ef7eb2e8f9f7	4982	hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress);
<>	144:ef7eb2e8f9f7	4983
<>	144:ef7eb2e8f9f7	4984	/* Wait until ADDR flag is set */
<>	144:ef7eb2e8f9f7	4985	if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	4986	{
<>	144:ef7eb2e8f9f7	4987	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
<>	144:ef7eb2e8f9f7	4988	{
<>	144:ef7eb2e8f9f7	4989	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	4990	}
<>	144:ef7eb2e8f9f7	4991	else
<>	144:ef7eb2e8f9f7	4992	{
<>	144:ef7eb2e8f9f7	4993	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	4994	}
<>	144:ef7eb2e8f9f7	4995	}
<>	144:ef7eb2e8f9f7	4996
<>	144:ef7eb2e8f9f7	4997	/* Clear ADDR flag */
<>	144:ef7eb2e8f9f7	4998	__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
<>	144:ef7eb2e8f9f7	4999
<>	144:ef7eb2e8f9f7	5000	/* Wait until TXE flag is set */
<>	144:ef7eb2e8f9f7	5001	if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	5002	{
<>	144:ef7eb2e8f9f7	5003	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
<>	144:ef7eb2e8f9f7	5004	{
<>	144:ef7eb2e8f9f7	5005	/* Generate Stop */
<>	144:ef7eb2e8f9f7	5006	hi2c->Instance->CR1 \|= I2C_CR1_STOP;
<>	144:ef7eb2e8f9f7	5007	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	5008	}
<>	144:ef7eb2e8f9f7	5009	else
<>	144:ef7eb2e8f9f7	5010	{
<>	144:ef7eb2e8f9f7	5011	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	5012	}
<>	144:ef7eb2e8f9f7	5013	}
<>	144:ef7eb2e8f9f7	5014
<>	144:ef7eb2e8f9f7	5015	/* If Memory address size is 8Bit */
<>	144:ef7eb2e8f9f7	5016	if(MemAddSize == I2C_MEMADD_SIZE_8BIT)
<>	144:ef7eb2e8f9f7	5017	{
<>	144:ef7eb2e8f9f7	5018	/* Send Memory Address */
<>	144:ef7eb2e8f9f7	5019	hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress);
<>	144:ef7eb2e8f9f7	5020	}
<>	144:ef7eb2e8f9f7	5021	/* If Memory address size is 16Bit */
<>	144:ef7eb2e8f9f7	5022	else
<>	144:ef7eb2e8f9f7	5023	{
<>	144:ef7eb2e8f9f7	5024	/* Send MSB of Memory Address */
<>	144:ef7eb2e8f9f7	5025	hi2c->Instance->DR = I2C_MEM_ADD_MSB(MemAddress);
<>	144:ef7eb2e8f9f7	5026
<>	144:ef7eb2e8f9f7	5027	/* Wait until TXE flag is set */
<>	144:ef7eb2e8f9f7	5028	if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	5029	{
<>	144:ef7eb2e8f9f7	5030	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
<>	144:ef7eb2e8f9f7	5031	{
<>	144:ef7eb2e8f9f7	5032	/* Generate Stop */
<>	144:ef7eb2e8f9f7	5033	hi2c->Instance->CR1 \|= I2C_CR1_STOP;
<>	144:ef7eb2e8f9f7	5034	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	5035	}
<>	144:ef7eb2e8f9f7	5036	else
<>	144:ef7eb2e8f9f7	5037	{
<>	144:ef7eb2e8f9f7	5038	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	5039	}
<>	144:ef7eb2e8f9f7	5040	}
<>	144:ef7eb2e8f9f7	5041
<>	144:ef7eb2e8f9f7	5042	/* Send LSB of Memory Address */
<>	144:ef7eb2e8f9f7	5043	hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress);
<>	144:ef7eb2e8f9f7	5044	}
<>	144:ef7eb2e8f9f7	5045
<>	144:ef7eb2e8f9f7	5046	/* Wait until TXE flag is set */
<>	144:ef7eb2e8f9f7	5047	if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	5048	{
<>	144:ef7eb2e8f9f7	5049	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
<>	144:ef7eb2e8f9f7	5050	{
<>	144:ef7eb2e8f9f7	5051	/* Generate Stop */
<>	144:ef7eb2e8f9f7	5052	hi2c->Instance->CR1 \|= I2C_CR1_STOP;
<>	144:ef7eb2e8f9f7	5053	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	5054	}
<>	144:ef7eb2e8f9f7	5055	else
<>	144:ef7eb2e8f9f7	5056	{
<>	144:ef7eb2e8f9f7	5057	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	5058	}
<>	144:ef7eb2e8f9f7	5059	}
<>	144:ef7eb2e8f9f7	5060
<>	144:ef7eb2e8f9f7	5061	/* Generate Restart */
<>	144:ef7eb2e8f9f7	5062	hi2c->Instance->CR1 \|= I2C_CR1_START;
<>	144:ef7eb2e8f9f7	5063
<>	144:ef7eb2e8f9f7	5064	/* Wait until SB flag is set */
<>	144:ef7eb2e8f9f7	5065	if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	5066	{
<>	144:ef7eb2e8f9f7	5067	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	5068	}
<>	144:ef7eb2e8f9f7	5069
<>	144:ef7eb2e8f9f7	5070	/* Send slave address */
<>	144:ef7eb2e8f9f7	5071	hi2c->Instance->DR = I2C_7BIT_ADD_READ(DevAddress);
<>	144:ef7eb2e8f9f7	5072
<>	144:ef7eb2e8f9f7	5073	/* Wait until ADDR flag is set */
<>	144:ef7eb2e8f9f7	5074	if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	5075	{
<>	144:ef7eb2e8f9f7	5076	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
<>	144:ef7eb2e8f9f7	5077	{
<>	144:ef7eb2e8f9f7	5078	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	5079	}
<>	144:ef7eb2e8f9f7	5080	else
<>	144:ef7eb2e8f9f7	5081	{
<>	144:ef7eb2e8f9f7	5082	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	5083	}
<>	144:ef7eb2e8f9f7	5084	}
<>	144:ef7eb2e8f9f7	5085
<>	144:ef7eb2e8f9f7	5086	return HAL_OK;
<>	144:ef7eb2e8f9f7	5087	}
<>	144:ef7eb2e8f9f7	5088
<>	144:ef7eb2e8f9f7	5089	/**
<>	144:ef7eb2e8f9f7	5090	* @brief DMA I2C process complete callback.
<>	144:ef7eb2e8f9f7	5091	* @param hdma DMA handle
<>	144:ef7eb2e8f9f7	5092	* @retval None
<>	144:ef7eb2e8f9f7	5093	*/
<>	144:ef7eb2e8f9f7	5094	static void I2C_DMAXferCplt(DMA_HandleTypeDef *hdma)
<>	144:ef7eb2e8f9f7	5095	{
<>	144:ef7eb2e8f9f7	5096	I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef)((DMA_HandleTypeDef)hdma)->Parent;
<>	144:ef7eb2e8f9f7	5097
<>	144:ef7eb2e8f9f7	5098	/* Declaration of temporary variable to prevent undefined behavior of volatile usage */
<>	144:ef7eb2e8f9f7	5099	uint32_t CurrentState = hi2c->State;
<>	144:ef7eb2e8f9f7	5100	uint32_t CurrentMode = hi2c->Mode;
<>	144:ef7eb2e8f9f7	5101
<>	144:ef7eb2e8f9f7	5102	if((CurrentState == HAL_I2C_STATE_BUSY_TX) \|\| ((CurrentState == HAL_I2C_STATE_BUSY_RX) && (CurrentMode == HAL_I2C_MODE_SLAVE)))
<>	144:ef7eb2e8f9f7	5103	{
<>	144:ef7eb2e8f9f7	5104	/* Disable DMA Request */
<>	144:ef7eb2e8f9f7	5105	hi2c->Instance->CR2 &= ~I2C_CR2_DMAEN;
<>	144:ef7eb2e8f9f7	5106
<>	144:ef7eb2e8f9f7	5107	hi2c->XferCount = 0U;
<>	144:ef7eb2e8f9f7	5108
<>	144:ef7eb2e8f9f7	5109	/* Enable EVT and ERR interrupt */
<>	144:ef7eb2e8f9f7	5110	__HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT \| I2C_IT_ERR);
<>	144:ef7eb2e8f9f7	5111	}
<>	144:ef7eb2e8f9f7	5112	else
<>	144:ef7eb2e8f9f7	5113	{
<>	144:ef7eb2e8f9f7	5114	/* Disable Acknowledge */
<>	144:ef7eb2e8f9f7	5115	hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
<>	144:ef7eb2e8f9f7	5116
<>	144:ef7eb2e8f9f7	5117	/* Generate Stop */
<>	144:ef7eb2e8f9f7	5118	hi2c->Instance->CR1 \|= I2C_CR1_STOP;
<>	144:ef7eb2e8f9f7	5119
<>	144:ef7eb2e8f9f7	5120	/* Disable Last DMA */
<>	144:ef7eb2e8f9f7	5121	hi2c->Instance->CR2 &= ~I2C_CR2_LAST;
<>	144:ef7eb2e8f9f7	5122
<>	144:ef7eb2e8f9f7	5123	/* Disable DMA Request */
<>	144:ef7eb2e8f9f7	5124	hi2c->Instance->CR2 &= ~I2C_CR2_DMAEN;
<>	144:ef7eb2e8f9f7	5125
<>	144:ef7eb2e8f9f7	5126	hi2c->XferCount = 0U;
<>	144:ef7eb2e8f9f7	5127
<>	144:ef7eb2e8f9f7	5128	/* Check if Errors has been detected during transfer */
<>	144:ef7eb2e8f9f7	5129	if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
<>	144:ef7eb2e8f9f7	5130	{
<>	144:ef7eb2e8f9f7	5131	HAL_I2C_ErrorCallback(hi2c);
<>	144:ef7eb2e8f9f7	5132	}
<>	144:ef7eb2e8f9f7	5133	else
<>	144:ef7eb2e8f9f7	5134	{
<>	144:ef7eb2e8f9f7	5135	hi2c->State = HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	5136
<>	144:ef7eb2e8f9f7	5137	if(hi2c->Mode == HAL_I2C_MODE_MEM)
<>	144:ef7eb2e8f9f7	5138	{
<>	144:ef7eb2e8f9f7	5139	hi2c->Mode = HAL_I2C_MODE_NONE;
<>	144:ef7eb2e8f9f7	5140
<>	144:ef7eb2e8f9f7	5141	HAL_I2C_MemRxCpltCallback(hi2c);
<>	144:ef7eb2e8f9f7	5142	}
<>	144:ef7eb2e8f9f7	5143	else
<>	144:ef7eb2e8f9f7	5144	{
<>	144:ef7eb2e8f9f7	5145	hi2c->Mode = HAL_I2C_MODE_NONE;
<>	144:ef7eb2e8f9f7	5146
<>	144:ef7eb2e8f9f7	5147	HAL_I2C_MasterRxCpltCallback(hi2c);
<>	144:ef7eb2e8f9f7	5148	}
<>	144:ef7eb2e8f9f7	5149	}
<>	144:ef7eb2e8f9f7	5150	}
<>	144:ef7eb2e8f9f7	5151	}
<>	144:ef7eb2e8f9f7	5152
<>	144:ef7eb2e8f9f7	5153	/**
<>	144:ef7eb2e8f9f7	5154	* @brief DMA I2C communication error callback.
<>	144:ef7eb2e8f9f7	5155	* @param hdma DMA handle
<>	144:ef7eb2e8f9f7	5156	* @retval None
<>	144:ef7eb2e8f9f7	5157	*/
<>	144:ef7eb2e8f9f7	5158	static void I2C_DMAError(DMA_HandleTypeDef *hdma)
<>	144:ef7eb2e8f9f7	5159	{
<>	144:ef7eb2e8f9f7	5160	I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef)((DMA_HandleTypeDef)hdma)->Parent;
AnnaBridge	167:e84263d55307	5161
AnnaBridge	167:e84263d55307	5162	/* Ignore DMA FIFO error */
AnnaBridge	167:e84263d55307	5163	if(HAL_DMA_GetError(hdma) != HAL_DMA_ERROR_FE)
AnnaBridge	167:e84263d55307	5164	{
AnnaBridge	167:e84263d55307	5165	/* Disable Acknowledge */
AnnaBridge	167:e84263d55307	5166	hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
AnnaBridge	167:e84263d55307	5167
AnnaBridge	167:e84263d55307	5168	hi2c->XferCount = 0U;
AnnaBridge	167:e84263d55307	5169
AnnaBridge	167:e84263d55307	5170	hi2c->State = HAL_I2C_STATE_READY;
AnnaBridge	167:e84263d55307	5171	hi2c->Mode = HAL_I2C_MODE_NONE;
AnnaBridge	167:e84263d55307	5172
AnnaBridge	167:e84263d55307	5173	hi2c->ErrorCode \|= HAL_I2C_ERROR_DMA;
AnnaBridge	167:e84263d55307	5174
AnnaBridge	167:e84263d55307	5175	HAL_I2C_ErrorCallback(hi2c);
AnnaBridge	167:e84263d55307	5176	}
<>	144:ef7eb2e8f9f7	5177	}
<>	144:ef7eb2e8f9f7	5178
<>	144:ef7eb2e8f9f7	5179	/**
<>	144:ef7eb2e8f9f7	5180	* @brief DMA I2C communication abort callback
<>	144:ef7eb2e8f9f7	5181	* (To be called at end of DMA Abort procedure).
<>	144:ef7eb2e8f9f7	5182	* @param hdma: DMA handle.
<>	144:ef7eb2e8f9f7	5183	* @retval None
<>	144:ef7eb2e8f9f7	5184	*/
<>	144:ef7eb2e8f9f7	5185	static void I2C_DMAAbort(DMA_HandleTypeDef *hdma)
<>	144:ef7eb2e8f9f7	5186	{
<>	144:ef7eb2e8f9f7	5187	I2C_HandleTypeDef* hi2c = ( I2C_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<>	144:ef7eb2e8f9f7	5188
<>	144:ef7eb2e8f9f7	5189	/* Disable Acknowledge */
<>	144:ef7eb2e8f9f7	5190	hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
<>	144:ef7eb2e8f9f7	5191
<>	144:ef7eb2e8f9f7	5192	hi2c->XferCount = 0U;
<>	144:ef7eb2e8f9f7	5193
<>	144:ef7eb2e8f9f7	5194	/* Reset XferAbortCallback */
<>	144:ef7eb2e8f9f7	5195	hi2c->hdmatx->XferAbortCallback = NULL;
<>	144:ef7eb2e8f9f7	5196	hi2c->hdmarx->XferAbortCallback = NULL;
<>	144:ef7eb2e8f9f7	5197
<>	144:ef7eb2e8f9f7	5198	/* Check if come from abort from user */
<>	144:ef7eb2e8f9f7	5199	if(hi2c->State == HAL_I2C_STATE_ABORT)
<>	144:ef7eb2e8f9f7	5200	{
<>	144:ef7eb2e8f9f7	5201	hi2c->State = HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	5202	hi2c->Mode = HAL_I2C_MODE_NONE;
AnnaBridge	167:e84263d55307	5203	hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
AnnaBridge	167:e84263d55307	5204
AnnaBridge	167:e84263d55307	5205	/* Disable I2C peripheral to prevent dummy data in buffer */
AnnaBridge	167:e84263d55307	5206	__HAL_I2C_DISABLE(hi2c);
<>	144:ef7eb2e8f9f7	5207
<>	144:ef7eb2e8f9f7	5208	/* Call the corresponding callback to inform upper layer of End of Transfer */
<>	144:ef7eb2e8f9f7	5209	HAL_I2C_AbortCpltCallback(hi2c);
<>	144:ef7eb2e8f9f7	5210	}
<>	144:ef7eb2e8f9f7	5211	else
<>	144:ef7eb2e8f9f7	5212	{
<>	144:ef7eb2e8f9f7	5213	hi2c->State = HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	5214	hi2c->Mode = HAL_I2C_MODE_NONE;
<>	144:ef7eb2e8f9f7	5215
AnnaBridge	167:e84263d55307	5216	/* Disable I2C peripheral to prevent dummy data in buffer */
AnnaBridge	167:e84263d55307	5217	__HAL_I2C_DISABLE(hi2c);
AnnaBridge	167:e84263d55307	5218
<>	144:ef7eb2e8f9f7	5219	/* Call the corresponding callback to inform upper layer of End of Transfer */
<>	144:ef7eb2e8f9f7	5220	HAL_I2C_ErrorCallback(hi2c);
<>	144:ef7eb2e8f9f7	5221	}
<>	144:ef7eb2e8f9f7	5222	}
<>	144:ef7eb2e8f9f7	5223
<>	144:ef7eb2e8f9f7	5224	/**
<>	144:ef7eb2e8f9f7	5225	* @brief This function handles I2C Communication Timeout.
<>	144:ef7eb2e8f9f7	5226	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	5227	* the configuration information for I2C module
<>	144:ef7eb2e8f9f7	5228	* @param Flag specifies the I2C flag to check.
<>	144:ef7eb2e8f9f7	5229	* @param Status The new Flag status (SET or RESET).
<>	144:ef7eb2e8f9f7	5230	* @param Timeout Timeout duration
<>	144:ef7eb2e8f9f7	5231	* @param Tickstart Tick start value
<>	144:ef7eb2e8f9f7	5232	* @retval HAL status
<>	144:ef7eb2e8f9f7	5233	*/
<>	144:ef7eb2e8f9f7	5234	static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart)
<>	144:ef7eb2e8f9f7	5235	{
<>	144:ef7eb2e8f9f7	5236	/* Wait until flag is set */
<>	144:ef7eb2e8f9f7	5237	while((__HAL_I2C_GET_FLAG(hi2c, Flag) ? SET : RESET) == Status)
<>	144:ef7eb2e8f9f7	5238	{
<>	144:ef7eb2e8f9f7	5239	/* Check for the Timeout */
<>	144:ef7eb2e8f9f7	5240	if(Timeout != HAL_MAX_DELAY)
<>	144:ef7eb2e8f9f7	5241	{
<>	144:ef7eb2e8f9f7	5242	if((Timeout == 0U)\|\|((HAL_GetTick() - Tickstart ) > Timeout))
<>	144:ef7eb2e8f9f7	5243	{
<>	144:ef7eb2e8f9f7	5244	hi2c->PreviousState = I2C_STATE_NONE;
<>	144:ef7eb2e8f9f7	5245	hi2c->State= HAL_I2C_STATE_READY;
AnnaBridge	167:e84263d55307	5246	hi2c->Mode = HAL_I2C_MODE_NONE;
AnnaBridge	167:e84263d55307	5247
<>	144:ef7eb2e8f9f7	5248	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	5249	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	5250
<>	144:ef7eb2e8f9f7	5251	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	5252	}
<>	144:ef7eb2e8f9f7	5253	}
<>	144:ef7eb2e8f9f7	5254	}
<>	144:ef7eb2e8f9f7	5255
<>	144:ef7eb2e8f9f7	5256	return HAL_OK;
<>	144:ef7eb2e8f9f7	5257	}
<>	144:ef7eb2e8f9f7	5258
<>	144:ef7eb2e8f9f7	5259	/**
<>	144:ef7eb2e8f9f7	5260	* @brief This function handles I2C Communication Timeout for Master addressing phase.
<>	144:ef7eb2e8f9f7	5261	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	5262	* the configuration information for I2C module
<>	144:ef7eb2e8f9f7	5263	* @param Flag specifies the I2C flag to check.
<>	144:ef7eb2e8f9f7	5264	* @param Timeout Timeout duration
<>	144:ef7eb2e8f9f7	5265	* @param Tickstart Tick start value
<>	144:ef7eb2e8f9f7	5266	* @retval HAL status
<>	144:ef7eb2e8f9f7	5267	*/
<>	144:ef7eb2e8f9f7	5268	static HAL_StatusTypeDef I2C_WaitOnMasterAddressFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, uint32_t Timeout, uint32_t Tickstart)
<>	144:ef7eb2e8f9f7	5269	{
<>	144:ef7eb2e8f9f7	5270	while(__HAL_I2C_GET_FLAG(hi2c, Flag) == RESET)
<>	144:ef7eb2e8f9f7	5271	{
<>	144:ef7eb2e8f9f7	5272	if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
<>	144:ef7eb2e8f9f7	5273	{
<>	144:ef7eb2e8f9f7	5274	/* Generate Stop */
<>	144:ef7eb2e8f9f7	5275	hi2c->Instance->CR1 \|= I2C_CR1_STOP;
<>	144:ef7eb2e8f9f7	5276
<>	144:ef7eb2e8f9f7	5277	/* Clear AF Flag */
<>	144:ef7eb2e8f9f7	5278	__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
<>	144:ef7eb2e8f9f7	5279
<>	144:ef7eb2e8f9f7	5280	hi2c->ErrorCode = HAL_I2C_ERROR_AF;
<>	144:ef7eb2e8f9f7	5281	hi2c->PreviousState = I2C_STATE_NONE;
<>	144:ef7eb2e8f9f7	5282	hi2c->State= HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	5283
<>	144:ef7eb2e8f9f7	5284	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	5285	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	5286
<>	144:ef7eb2e8f9f7	5287	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	5288	}
<>	144:ef7eb2e8f9f7	5289
<>	144:ef7eb2e8f9f7	5290	/* Check for the Timeout */
<>	144:ef7eb2e8f9f7	5291	if(Timeout != HAL_MAX_DELAY)
<>	144:ef7eb2e8f9f7	5292	{
<>	144:ef7eb2e8f9f7	5293	if((Timeout == 0U)\|\|((HAL_GetTick() - Tickstart ) > Timeout))
<>	144:ef7eb2e8f9f7	5294	{
<>	144:ef7eb2e8f9f7	5295	hi2c->PreviousState = I2C_STATE_NONE;
<>	144:ef7eb2e8f9f7	5296	hi2c->State= HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	5297
<>	144:ef7eb2e8f9f7	5298	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	5299	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	5300
<>	144:ef7eb2e8f9f7	5301	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	5302	}
<>	144:ef7eb2e8f9f7	5303	}
<>	144:ef7eb2e8f9f7	5304	}
<>	144:ef7eb2e8f9f7	5305	return HAL_OK;
<>	144:ef7eb2e8f9f7	5306	}
<>	144:ef7eb2e8f9f7	5307
<>	144:ef7eb2e8f9f7	5308	/**
<>	144:ef7eb2e8f9f7	5309	* @brief This function handles I2C Communication Timeout for specific usage of TXE flag.
<>	144:ef7eb2e8f9f7	5310	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	5311	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	5312	* @param Timeout Timeout duration
<>	144:ef7eb2e8f9f7	5313	* @param Tickstart Tick start value
<>	144:ef7eb2e8f9f7	5314	* @retval HAL status
<>	144:ef7eb2e8f9f7	5315	*/
<>	144:ef7eb2e8f9f7	5316	static HAL_StatusTypeDef I2C_WaitOnTXEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
<>	144:ef7eb2e8f9f7	5317	{
<>	144:ef7eb2e8f9f7	5318	while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET)
<>	144:ef7eb2e8f9f7	5319	{
<>	144:ef7eb2e8f9f7	5320	/* Check if a NACK is detected */
<>	144:ef7eb2e8f9f7	5321	if(I2C_IsAcknowledgeFailed(hi2c) != HAL_OK)
<>	144:ef7eb2e8f9f7	5322	{
<>	144:ef7eb2e8f9f7	5323	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	5324	}
<>	144:ef7eb2e8f9f7	5325
<>	144:ef7eb2e8f9f7	5326	/* Check for the Timeout */
<>	144:ef7eb2e8f9f7	5327	if(Timeout != HAL_MAX_DELAY)
<>	144:ef7eb2e8f9f7	5328	{
<>	144:ef7eb2e8f9f7	5329	if((Timeout == 0U) \|\| ((HAL_GetTick()-Tickstart) > Timeout))
<>	144:ef7eb2e8f9f7	5330	{
<>	144:ef7eb2e8f9f7	5331	hi2c->ErrorCode \|= HAL_I2C_ERROR_TIMEOUT;
<>	144:ef7eb2e8f9f7	5332	hi2c->PreviousState = I2C_STATE_NONE;
<>	144:ef7eb2e8f9f7	5333	hi2c->State= HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	5334
<>	144:ef7eb2e8f9f7	5335	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	5336	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	5337
<>	144:ef7eb2e8f9f7	5338	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	5339	}
<>	144:ef7eb2e8f9f7	5340	}
<>	144:ef7eb2e8f9f7	5341	}
<>	144:ef7eb2e8f9f7	5342	return HAL_OK;
<>	144:ef7eb2e8f9f7	5343	}
<>	144:ef7eb2e8f9f7	5344
<>	144:ef7eb2e8f9f7	5345	/**
<>	144:ef7eb2e8f9f7	5346	* @brief This function handles I2C Communication Timeout for specific usage of BTF flag.
<>	144:ef7eb2e8f9f7	5347	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	5348	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	5349	* @param Timeout Timeout duration
<>	144:ef7eb2e8f9f7	5350	* @param Tickstart Tick start value
<>	144:ef7eb2e8f9f7	5351	* @retval HAL status
<>	144:ef7eb2e8f9f7	5352	*/
<>	144:ef7eb2e8f9f7	5353	static HAL_StatusTypeDef I2C_WaitOnBTFFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
<>	144:ef7eb2e8f9f7	5354	{
<>	144:ef7eb2e8f9f7	5355	while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == RESET)
<>	144:ef7eb2e8f9f7	5356	{
<>	144:ef7eb2e8f9f7	5357	/* Check if a NACK is detected */
<>	144:ef7eb2e8f9f7	5358	if(I2C_IsAcknowledgeFailed(hi2c) != HAL_OK)
<>	144:ef7eb2e8f9f7	5359	{
<>	144:ef7eb2e8f9f7	5360	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	5361	}
<>	144:ef7eb2e8f9f7	5362
<>	144:ef7eb2e8f9f7	5363	/* Check for the Timeout */
<>	144:ef7eb2e8f9f7	5364	if(Timeout != HAL_MAX_DELAY)
<>	144:ef7eb2e8f9f7	5365	{
<>	144:ef7eb2e8f9f7	5366	if((Timeout == 0U) \|\| ((HAL_GetTick()-Tickstart) > Timeout))
<>	144:ef7eb2e8f9f7	5367	{
<>	144:ef7eb2e8f9f7	5368	hi2c->ErrorCode \|= HAL_I2C_ERROR_TIMEOUT;
<>	144:ef7eb2e8f9f7	5369	hi2c->PreviousState = I2C_STATE_NONE;
<>	144:ef7eb2e8f9f7	5370	hi2c->State= HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	5371
<>	144:ef7eb2e8f9f7	5372	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	5373	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	5374
<>	144:ef7eb2e8f9f7	5375	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	5376	}
<>	144:ef7eb2e8f9f7	5377	}
<>	144:ef7eb2e8f9f7	5378	}
<>	144:ef7eb2e8f9f7	5379	return HAL_OK;
<>	144:ef7eb2e8f9f7	5380	}
<>	144:ef7eb2e8f9f7	5381
<>	144:ef7eb2e8f9f7	5382	/**
<>	144:ef7eb2e8f9f7	5383	* @brief This function handles I2C Communication Timeout for specific usage of STOP flag.
<>	144:ef7eb2e8f9f7	5384	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	5385	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	5386	* @param Timeout Timeout duration
<>	144:ef7eb2e8f9f7	5387	* @param Tickstart Tick start value
<>	144:ef7eb2e8f9f7	5388	* @retval HAL status
<>	144:ef7eb2e8f9f7	5389	*/
<>	144:ef7eb2e8f9f7	5390	static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
<>	144:ef7eb2e8f9f7	5391	{
<>	144:ef7eb2e8f9f7	5392	while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
<>	144:ef7eb2e8f9f7	5393	{
<>	144:ef7eb2e8f9f7	5394	/* Check if a NACK is detected */
<>	144:ef7eb2e8f9f7	5395	if(I2C_IsAcknowledgeFailed(hi2c) != HAL_OK)
<>	144:ef7eb2e8f9f7	5396	{
<>	144:ef7eb2e8f9f7	5397	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	5398	}
<>	144:ef7eb2e8f9f7	5399
<>	144:ef7eb2e8f9f7	5400	/* Check for the Timeout */
<>	144:ef7eb2e8f9f7	5401	if((Timeout == 0U) \|\| ((HAL_GetTick()-Tickstart) > Timeout))
<>	144:ef7eb2e8f9f7	5402	{
<>	144:ef7eb2e8f9f7	5403	hi2c->ErrorCode \|= HAL_I2C_ERROR_TIMEOUT;
<>	144:ef7eb2e8f9f7	5404	hi2c->PreviousState = I2C_STATE_NONE;
<>	144:ef7eb2e8f9f7	5405	hi2c->State= HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	5406
<>	144:ef7eb2e8f9f7	5407	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	5408	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	5409
<>	144:ef7eb2e8f9f7	5410	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	5411	}
<>	144:ef7eb2e8f9f7	5412	}
<>	144:ef7eb2e8f9f7	5413	return HAL_OK;
<>	144:ef7eb2e8f9f7	5414	}
<>	144:ef7eb2e8f9f7	5415
<>	144:ef7eb2e8f9f7	5416	/**
<>	144:ef7eb2e8f9f7	5417	* @brief This function handles I2C Communication Timeout for specific usage of RXNE flag.
<>	144:ef7eb2e8f9f7	5418	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	5419	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	5420	* @param Timeout Timeout duration
<>	144:ef7eb2e8f9f7	5421	* @param Tickstart Tick start value
<>	144:ef7eb2e8f9f7	5422	* @retval HAL status
<>	144:ef7eb2e8f9f7	5423	*/
<>	144:ef7eb2e8f9f7	5424	static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
<>	144:ef7eb2e8f9f7	5425	{
<>	144:ef7eb2e8f9f7	5426
<>	144:ef7eb2e8f9f7	5427	while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET)
<>	144:ef7eb2e8f9f7	5428	{
<>	144:ef7eb2e8f9f7	5429	/* Check if a STOPF is detected */
<>	144:ef7eb2e8f9f7	5430	if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET)
<>	144:ef7eb2e8f9f7	5431	{
<>	144:ef7eb2e8f9f7	5432	/* Clear STOP Flag */
<>	144:ef7eb2e8f9f7	5433	__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
<>	144:ef7eb2e8f9f7	5434
<>	144:ef7eb2e8f9f7	5435	hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
<>	144:ef7eb2e8f9f7	5436	hi2c->PreviousState = I2C_STATE_NONE;
<>	144:ef7eb2e8f9f7	5437	hi2c->State= HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	5438
<>	144:ef7eb2e8f9f7	5439	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	5440	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	5441
<>	144:ef7eb2e8f9f7	5442	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	5443	}
<>	144:ef7eb2e8f9f7	5444
<>	144:ef7eb2e8f9f7	5445	/* Check for the Timeout */
<>	144:ef7eb2e8f9f7	5446	if((Timeout == 0U) \|\| ((HAL_GetTick()-Tickstart) > Timeout))
<>	144:ef7eb2e8f9f7	5447	{
<>	144:ef7eb2e8f9f7	5448	hi2c->ErrorCode \|= HAL_I2C_ERROR_TIMEOUT;
<>	144:ef7eb2e8f9f7	5449	hi2c->State= HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	5450
<>	144:ef7eb2e8f9f7	5451	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	5452	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	5453
<>	144:ef7eb2e8f9f7	5454	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	5455	}
<>	144:ef7eb2e8f9f7	5456	}
<>	144:ef7eb2e8f9f7	5457	return HAL_OK;
<>	144:ef7eb2e8f9f7	5458	}
<>	144:ef7eb2e8f9f7	5459
<>	144:ef7eb2e8f9f7	5460	/**
<>	144:ef7eb2e8f9f7	5461	* @brief This function handles Acknowledge failed detection during an I2C Communication.
<>	144:ef7eb2e8f9f7	5462	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	5463	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	5464	* @retval HAL status
<>	144:ef7eb2e8f9f7	5465	*/
<>	144:ef7eb2e8f9f7	5466	static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c)
<>	144:ef7eb2e8f9f7	5467	{
<>	144:ef7eb2e8f9f7	5468	if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
<>	144:ef7eb2e8f9f7	5469	{
<>	144:ef7eb2e8f9f7	5470	/* Clear NACKF Flag */
<>	144:ef7eb2e8f9f7	5471	__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
<>	144:ef7eb2e8f9f7	5472
<>	144:ef7eb2e8f9f7	5473	hi2c->ErrorCode = HAL_I2C_ERROR_AF;
<>	144:ef7eb2e8f9f7	5474	hi2c->PreviousState = I2C_STATE_NONE;
<>	144:ef7eb2e8f9f7	5475	hi2c->State= HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	5476
<>	144:ef7eb2e8f9f7	5477	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	5478	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	5479
<>	144:ef7eb2e8f9f7	5480	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	5481	}
<>	144:ef7eb2e8f9f7	5482	return HAL_OK;
<>	144:ef7eb2e8f9f7	5483	}
<>	144:ef7eb2e8f9f7	5484	/**
<>	144:ef7eb2e8f9f7	5485	* @}
<>	144:ef7eb2e8f9f7	5486	*/
<>	144:ef7eb2e8f9f7	5487
<>	144:ef7eb2e8f9f7	5488	#endif /* HAL_I2C_MODULE_ENABLED */
<>	144:ef7eb2e8f9f7	5489
<>	144:ef7eb2e8f9f7	5490	/**
<>	144:ef7eb2e8f9f7	5491	* @}
<>	144:ef7eb2e8f9f7	5492	*/
<>	144:ef7eb2e8f9f7	5493
<>	144:ef7eb2e8f9f7	5494	/**
<>	144:ef7eb2e8f9f7	5495	* @}
<>	144:ef7eb2e8f9f7	5496	*/
<>	144:ef7eb2e8f9f7	5497
<>	144:ef7eb2e8f9f7	5498	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/